SN75LVDS84ADGG [TI]
FLATLINKE TRANSMITTER; FLATLINKE变送器
| 型号： | SN75LVDS84ADGG |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | FLATLINKE TRANSMITTER |
| 文件： | 总14页 (文件大小：192K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN75LVDS84A
FLATLINK TRANSMITTER
SLLS354C – MAY 1999 – REVISED NOVEMBER 1999
DGG PACKAGE
(TOP VIEW)
21:3 Data Channel Compression at up to
196 Million Bytes per Second Throughput
Suited for SVGA, XGA, or SXGA Data
Transmission From Controller to Display
With Very Low EMI
D4
D3
1
48
47
46
45
44
43
42
41
40
39
38
V
D2
2
CC
D5
GND
D1
3
21 Data Channels Plus Clock In
D6
4
Low-Voltage TTL inputs and 3 Data
Channels Plus Clock Out Low-Voltage
Differential Signaling (LVDS) Outputs
GND
D7
D0
5
NC
6
D8
LVDSGND
Y0M
Y0P
Y1M
Y1P
7
Operates From a Single 3.3-V Supply and
89 mW (Typ)
V
8
CC
D9
D10
9
10
11
Ultra Low Power 3.3-V CMOS Version of the
SN75LVDS84. Power Consumption About
One Third of the ’LVDS84
GND
D11 12
D12 13
NC 14
37 LVDSV
CC
36 LVDSGND
35 Y2M
Packaged in Thin Shrink Small-Outline
Package (TSSOP) With 20 Mil Terminal
Pitch
15
16
17
18
19
20
21
22
23
24
34
33
32
31
30
29
28
27
26
25
D13
D14
GND
D15
D16
D17
Y2P
CLKOUTM
CLKOUTP
LVDSGND
PLLGND
Consumes Less Than 0.54 mW When
Disabled
Wide Phase-Lock Input Frequency Range:
31 MHz to 75 MHz
PLLV
CC
No External Components Required for PLL
V
PLLGND
SHTDN
CLKIN
D20
CC
Outputs Meet or Exceed the Requirements
of ANSI EIA/TIA–644 Standard
D18
D19
GND
SSC Tracking Capability of 3% Center
Spread at 50-kHz Modulation Frequency
NC – Not Connected
Improved Replacement for SN75LVDS84
and NSC’s DS90CF363A 3-V Device
description
The SN75LVDS84A FlatLink transmitter contains three 7-bit parallel-load serial-out shift registers, and four
low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These functions allow 21 bits
of single-ended LVTTL data to be synchronously transmitted over 3 balanced-pair conductors for receipt by a
compatible receiver, such as the SN75LVDS82 or SN75LVDS86/86A.
When transmitting, data bits D0 – D20 are each loaded into registers of the ’LVDS84A upon the falling edge.
The internal PLL is frequency-locked to CLKIN and then used to unload the data registers in 7-bit slices. The
threeserialstreamsandaphase-lockedclock(CLKOUT)arethenoutputtoLVDSoutputdrivers. Thefrequency
of CLKOUT is the same as the input clock, CLKIN.
The ’LVDS84A requires no external components and little or no control. The data bus appears the same at the
input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only
user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut
off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers
to a low level.
The SN75LVDS84A is characterized for operation over ambient free-air temperatures of 0 C to 70 C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a trademark of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS84A
FLATLINK TRANSMITTER
SLLS354C – MAY 1999 – REVISED NOVEMBER 1999
functional block diagram
Parallel-Load 7-Bit
Shift Register
7
Y0P
Y0M
D0 – D6
A,B, ...G
SHIFT/LOAD
CLK
Parallel-Load 7-Bit
Shift Register
7
Y1P
Y1M
A,B, ...G
SHIFT/LOAD
CLK
D7 – D13
Parallel-Load 7-Bit
Shift Register
7
Y2P
Y2M
A,B, ...G
SHIFT/LOAD
CLK
D14 – D20
Control Logic
PLL
SHTDN
CLKIN
CLKOUTP
CLKOUTM
CLK
CLKINH
schematics of input and output
EQUIVALENT OF EACH INPUT
EQUIVALENT OF EACH OUTPUT
V
CC
V
CC
7 V
180 Ω
D or
YnP or YnM
SHTDN
5 V
7 V
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS84A
FLATLINK TRANSMITTER
SLLS354C – MAY 1999 – REVISED NOVEMBER 1999
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
CC
Input and output voltage ranges, V , V (all terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V + 0.5 V
I
O
CC
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Electrostatic discharge: ESD machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 V
ESD human-body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6000 V
ESD charged-device model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 V
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 C to 150 C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the GND terminals.
DISSIPATION RATING TABLE
≤ 25°C DERATING FACTOR
‡
T
A
T = 70°C
A
POWER RATING
PACKAGE
POWER RATING
ABOVE T = 25°C
A
DGG
1316 mW
13.1 mW/°C
726 mW
‡
This is the inverse of the junction-to-ambient thermal resistance when board mounted and
with no air flow.
recommended operating conditions
MIN NOM MAX
UNIT
V
Supply voltage, V
CC
3
2
3.3
3.6
High-level input voltage, V
IH
V
Low-level input voltage, V
0.8
132
70
V
IL
Differential load impedance, Z
90
0
Ω
L
Operating free-air temperature, T
°C
A
timing requirements
MIN NOM
13.3
0.4t
MAX
UNIT
ns
t
t
t
t
t
Input clock period
t
c
32.4
c
Pulse duration, high-level input clock
0.6t
c
ns
w
t
c
Transition time, input signal
5
ns
Setup time, data, D0 – D20 valid before CLKIN↓ (See Figure 2)
Hold time, data, D0 – D20 valid after CLKIN↓ (See Figure 2)
3
ns
su
h
1.5
ns
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS84A
FLATLINK TRANSMITTER
SLLS354C – MAY 1999 – REVISED NOVEMBER 1999
electrical characteristics over recommended operating conditions (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
1.4
MAX
UNIT
V
IT
Input threshold voltage
V
Differential steady-state output voltage magni-
tude
R = 100 Ω,
L
|V
|
247
454
50
mV
mV
V
OD
See Figure 3
Change in the steady-state differential output
voltage magnitude between opposite binary
states
∆|V
|
OD
R
= 100 Ω,
L
V
V
Steady-state common-mode output voltage
1.125
1.375
OC(SS)
See Figure 3
Peak-to-peak common-mode output voltage
High-level input current
80
150
20
mV
µA
OC(PP)
I
I
V
V
V
V
V
= V
= 0
IH
IH
CC
= 0
Low-level input current
±10
±24
±12
±10
µA
IL
IL
–6
–6
mA
mA
µA
O(Yn)
I
Short-circuit output current
OS
OZ
= 0
OD
= 0 to V
I
High-impedance output current
O
CC
Disabled,
All inputs at GND
15
27
30
28
150
35
38
36
39
µA
Enabled,
f = 65 MHz
f = 75 MHz
f = 65 MHz
f = 75 MHz
R
= 100 Ω (4 places)
L
Gray-scale pattern
(see Figure 4)
I
Quiescent supply current (average)
CC(AVG)
mA
pF
Enabled,
R
= 100 Ω, (4 places)
Worst-case pattern
(see Figure 5)
31
2
C
Input capacitance
I
†
All typical values are at V = 3.3 V, T = 25°C.
CC
A
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS84A
FLATLINK TRANSMITTER
SLLS354C – MAY 1999 – REVISED NOVEMBER 1999
switching characteristics over recommended operating conditions (unless otherwise noted)
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Delay time, CLKOUT↑ to serial bit
position 0
t
t
t
t
t
t
–0.2
0.2
ns
d0
d1
d2
d3
d4
d5
Delay time, CLKOUT↑ to serial bit
position 1
1
7
1
7
ns
ns
ns
ns
ns
t
t
t
t
t
t
0.2
0.2
0.2
0.2
0.2
t
t
t
0.2
0.2
0.2
c
c
c
c
c
c
c
c
c
Delay time, CLKOUT↑ to serial bit
position 2
2
7
2
7
t = 15.38 ns (± 0.2%),
|Input clock jitter| < 50 ps ,
See Figure 6
c
Delay time, CLKOUT↑ to serial bit
position 3
3
7
3
7
‡
Delay time, CLKOUT↑ to serial bit
position 4
4
7
4
7
t
t
0.2
0.2
c
c
Delay time, CLKOUT↑ to serial bit
position 5
5
7
5
7
Delay time, CLKOUT↑ to serial bit
position 6
6
7
6
7
t
t
ns
ns
0.2
t
0.2
0.2
d6
c
n
7
–0.2
Output skew, t
t
c
sk(o)
n
t = 15.38 ns (± 0.2%),
|Input clock jitter| < 50 ps ,
See Figure 6
c
‡
t
d7
Delay time, CLKIN↓ to CLKOUT↑
2.7
ns
t = 15.38 + 0.308 sin (2π500E3t) ± 0.05 ns,
See Figure 7
c
±62
ps
ps
ns
ps
ms
ns
§
∆t
c(o)
Cycle time, output clock jitter
t = 15.38 + 0.308 sin (2π3E6t) ± 0.05 ns,
c
±121
See Figure 7
4
7
t
c
t
Pulse duration, high-level output clock
Transition time, differential output
w
t
t
t
See Figure 3
See Figure 8
See Figure 9
700
1
1500
t
voltage (t or t )
r
f
Enable time, SHTDN↑ to phase lock
(Yn valid)
en
Disable time, SHTDN↓ to off state
(CLKOUT low)
6.5
dis
†
‡
§
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
|Input clock jitter| is the magnitude of the change in the input clock period.
Output clock jitter is the change in the output clock period from one cycle to the next cycle observed over 15000 cycles.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS84A
FLATLINK TRANSMITTER
SLLS354C – MAY 1999 – REVISED NOVEMBER 1999
PARAMETER MEASUREMENT INFORMATION
D0
CLKIN
CLKOUT
Next
Cycle
Previous Cycle
Current Cycle
D0–1
D7–1
D6
D5
D4
D3
D2
D1
D8
D0
D7
D6+1
Y0
Y1
Y2
D13
D12
D11
D18
D10
D9
D13+1
D14–1
D20
D19
D17
D16
D15
D14
D20+1
Figure 1. Typical Load and Shift Sequences
t
t
h
su
Dn
CLKIN
NOTE A: All input timing is defined at 1.4 V on an input signal with a 10%-to-90% rise or fall time of less than 5 ns.
Figure 2. Setup and Hold Time Definition
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS84A
FLATLINK TRANSMITTER
SLLS354C – MAY 1999 – REVISED NOVEMBER 1999
49.9 Ω ± 1% (2 Places)
YP
V
OD
V
OC
YM
C
= 10 pF Max
L
(2 Places)
NOTE A: The lumped instrumentation capacitance for any single-ended voltage measurement is less than or equal to 10 pF. When making
measurements at YP or YM, the complementary output is similarly loaded.
(a) SCHEMATIC
100%
80%
V
OD(H)
0 V
V
OD(L)
20%
0%
t
t
r
f
V
OC(PP)
V
V
OC(SS)
OC(SS)
0 V
(b) WAVEFORMS
Figure 3. Test Load and Voltage Definitions for LVDS Outputs
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS84A
FLATLINK TRANSMITTER
SLLS354C – MAY 1999 – REVISED NOVEMBER 1999
PARAMETER MEASUREMENT INFORMATION
CLKIN
D0, 6, 12
D1, 7, 13
D2, 8, 14
D3, 9, 15
D18, 19, 20
All others
NOTES: A. The 16-grayscale test-pattern test device power consumption for a typical display pattern.
B.
V
IH
= 2 V and V = 0.8 V
IL
Figure 4. 16-Grayscale Test-Pattern Waveforms
t
c
CLKIN
Even Dn
Odd Dn
NOTES: A. The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs.
B. = 2 V and V = 0.8 V
V
IH
IL
Figure 5. Worst-Case Test-Pattern Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS84A
FLATLINK TRANSMITTER
SLLS354C – MAY 1999 – REVISED NOVEMBER 1999
PARAMETER MEASUREMENT INFORMATION
t
d7
CLKIN
CLKOUT
t
d0
Yn
t
d1
t
d2
t
d3
t
d4
t
d5
t
d6
V
0 V
V
OD(H)
CLKOUT
CLKIN
1.4 V
or
Yn
OD(L)
t
d7
t
– t
d0 d6
Figure 6. Timing Definitions
Device
Under
Test
+
Reference
VCO
∑
+
Modulation
V(t) = A sin (2 π f
t)
(mod)
HP8665A
Synthesized
HP8133A
Pulse Generator
Device Under Test
Tek TDS794D
Digital Scope
Signal Generator
0.1 MHz – 4200 MHz
OUTPUT
CLKIN
CLKOUT
Input
RF Output
Ext. Input
Figure 7. Clock Jitter Test Setup
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS84A
FLATLINK TRANSMITTER
SLLS354C – MAY 1999 – REVISED NOVEMBER 1999
TYPICAL CHARACTERISTICS
CLKIN
Dn
t
en
SHTDN
Yn
Invalid
Valid
Figure 8. Enable Time Waveforms
CLKIN
t
dis
SHTDN
CLKOUT
Figure 9. Disable Time Waveforms
PEAK-TO-PEAK OUTPUT JITTER (NORMALIZED)
AVERAGE SUPPLY CURRENT
vs
vs
CLOCK FREQUENCY
31
MODULATION FREQUENCY
10
29
V
CC
= 3.6 V
27
25
23
V
CC
= 3.3 V
1
V
CC
= 3 V
21
19
17
15
0.1
0.1
1
10
30 35
40
45 50
55 60
65
70
75
f
– Modulation Frequency – MHz
(mod)
f
– Clock Frequency – MHz
c
Figure 11. Output Period Jitter vs
Modulation Frequency
Figure 10. Grayscale Input Pattern
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS84A
FLATLINK TRANSMITTER
SLLS354C – MAY 1999 – REVISED NOVEMBER 1999
APPLICATION INFORMATION
Host
Cable
Flat Panel Display
Graphics Controller
SN75LVDS84A
SN75LVDS86/86A
12-BIT
RED0
RED1
RED2
RED3
NA
18-BIT
RED0
RED1
RED2
RED3
RED4
RED5
41
8
44
45
47
48
1
D0
Y0M
A0M
D1
100 Ω
100 Ω
100 Ω
100 Ω
D2
40
39
9
D3
Y0P
Y1M
A0P
A1M
D4
3
NA
D5
4
10
GREEN0 GREEN0
GREEN1 GREEN1
GREEN2 GREEN2
GREEN3 GREEN3
D6
6
D7
7
D8
9
38
35
11
14
D9
Y1P
Y2M
A1P
A2M
10
12
13
15
16
18
19
20
22
23
25
26
NA
GREEN4
GREEN5
BLUE0
BLUE1
BLUE2
BLUE3
BLUE4
BLUE5
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
CLKIN
NA
BLUE0
BLUE1
BLUE2
BLUE3
NA
34
33
15
16
Y2P
CLKOUTM
CLKOUTP
A2P
NA
H_SYNC H_SYNC
V_SYNC V_SYNC
ENABLE ENABLE
CLKINM
32
17
CLOCK
CLOCK
CLKINP
NOTES: A. The five 100-Ω terminating resistors are recommended to be 0603 types.
B. NA – not applicable, these unused inputs should be left open.
Figure 12. Color Host to LCD Panel Application
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS84A
FLATLINK TRANSMITTER
SLLS354C – MAY 1999 – REVISED NOVEMBER 1999
APPLICATION INFORMATION
Host
Cable
Flat Panel Display
Graphics Controller
SN75LVDS84A
SN75LVDS82
12-BIT
RED0
RED1
RED2
RED3
NA
18-BIT
RED0
RED1
RED2
RED3
RED4
RED5
41
9
44
45
47
48
1
D0
Y0M
A0M
D1
100 Ω
100 Ω
100 Ω
100 Ω
D2
40
39
10
11
D3
Y0P
Y1M
A0P
A1M
D4
3
NA
D5
4
GREEN0 GREEN0
GREEN1 GREEN1
GREEN2 GREEN2
GREEN3 GREEN3
D6
6
D7
7
D8
9
38
35
12
15
D9
Y1P
Y2M
A1P
A2M
10
12
13
15
16
18
19
20
22
23
25
26
NA
GREEN4
GREEN5
BLUE0
BLUE1
BLUE2
BLUE3
BLUE4
BLUE5
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
CLKIN
NA
BLUE0
BLUE1
BLUE2
BLUE3
NA
34
33
32
16
Y2P
CLKOUTM
CLKOUTP
A2P
NA
H_SYNC H_SYNC
V_SYNC V_SYNC
ENABLE ENABLE
CLKINM
CLOCK
CLOCK
CLKINP
A3M
100 Ω
A3P
NOTES: A. The four 100-Ω terminating resistors are recommended to be 0603 types.
B. NA – not applicable, these unused inputs should be left open.
Figure 13. 18-Bit Color Host to 24-Bit LCD Display Panel Application
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS84A
FLATLINK TRANSMITTER
SLLS354C – MAY 1999 – REVISED NOVEMBER 1999
MECHANICAL INFORMATION
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PIN SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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Copyright 1999, Texas Instruments Incorporated
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