SN75LVPE5421 [TI]
具有集成式 2:1 多路复用器的 PCIe® 5.0 32Gbps 4 通道线性转接驱动器;
| 型号： | SN75LVPE5421 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成式 2:1 多路复用器的 PCIe® 5.0 32Gbps 4 通道线性转接驱动器 PC 驱动 复用器 驱动器 |
| 文件： | 总35页 (文件大小：2483K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN75LVPE5421
ZHCSN44A –DECEMBER 2021 –REVISED OCTOBER 2022
SN75LVPE5421 具有2:1 多路复用器的PCIe® 5.0 32Gbps 4 通道线性转接驱动器
1 特性
3 说明
• 具有集成式2:1 多路复用器的四通道PCIe 5.0 线性
转接驱动器或中继器
• 此线性转接驱动器与协议无关，可兼容PCIe、
UPI、CCIX、NVLink、DisplayPort、SAS、SATA
和XFI
SN75LVPE5421 是一款具有集成式多路复用器的四通
道线性转接驱动器。这款低功耗高性能线性转接驱动器
专为支持 PCIe 5.0 和其他速率高达 32Gbps 的接口而
设计。
SN75LVPE5421 接收器部署了连续时间线性均衡器
(CTLE)，可提供高频增强。均衡器可以打开由于 PCB
布线或电缆等互连介质引起的码间串扰 (ISI) 而完全关
闭的输入眼图。在 PCIe 链路训练期间，线性转接驱动
器与根复合体 (RC) 和端点 (EP) 之间的无源通道作为
一个整体接受训练，以达到理想的发送和接收均衡设
置，从而实现出色的电气链路。该器件具有低通道间串
扰、低附加抖动和极低的回波损耗，因此在链路中几乎
可作为无源元件。这款器件具有内部线性稳压器，对板
上电源噪声具有高抗扰度，从而为高速数据路径提供纯
净电源。
• 单个3.3V 电源，可使用PCIe 电源轨
• 4 通道运行时，有功功率低至720mW
• 无需散热器
• 频率为16GHz 时，支持高达24dB 的均衡功能
• 出色的RX/TX 差分RL（8-16GHz 时，为-10dB）
• 55fs RMS 的低附加随机抖动（带PRBS 数据）
• 90ps 低延迟
• 自动接收器检测和无缝支持PCIe 链路训练
• 通过引脚控制或SMBus/I2C 进行器件配置。
• 通过引脚选择多路复用器
• 内部稳压器具有抗电源噪声能力
• 高速量产测试可确保制造可靠性
SN75LVPE5421 在量产期间实施了高速测试，从而确
保可靠的高产量制造。此器件还具有低交流和直流增益
变化，可在各种平台部署中提供一致的均衡功能。
• 通过一个或多个器件支持x4、x8 和x16 总线宽度
• 可提供配套多路信号分离器产品SN75LVPE5412
• 0°C 至85°C 温度范围
封装信息(1)
• 3.5mm × 9mm 42 引脚0.5mm 间距WQFN 封装
封装尺寸（标称值）
器件型号
封装
2 应用
SN75LVPE5421
RUA (WQFN, 42)
3.50 mm × 9.00 mm
• 台式计算机和主板
• 显示面板、游戏机
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 机架式服务器、微服务器和塔式服务器
• 高性能计算、硬件加速器
• 数据存储、网络附加存储
• 存储区域网络(SAN) 和主机总线适配器(HBA) 卡
• 网络接口卡(NIC)
PCIe Card
x16
Slot
x8
4-Ch
4-Ch
Connector-B
RXB 8-ch
TXA
RXA
x8
RX 8-ch
LVPE5421
4 Ch 2:1 Mux
4-Ch
4-Ch
RX
TX
CPU
TX 8-ch
TXB 8-ch
LVPE5412
4 Ch 1:2 De-mux
4-Ch
4-Ch
h
c
h
c
-
8
PCIe Card
TXB
RXB
-
8
XA
T
RXA
x8
Slot
Connector-A
x8
De-multiplexer
Multiplexer
PCIe Lane Muxing
应用用例
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNLS692
SN75LVPE5421
ZHCSN44A –DECEMBER 2021 –REVISED OCTOBER 2022
www.ti.com.cn
Table of Contents
7.3 Feature Description...................................................13
7.4 Device Functional Modes..........................................15
7.5 Programming............................................................ 15
8 Application and Implementation..................................20
8.1 Application Information............................................. 20
8.2 Typical Applications.................................................. 20
9 Power Supply Recommendations................................24
10 Layout...........................................................................24
10.1 Layout Guidelines................................................... 24
10.2 Layout Example...................................................... 24
11 Device and Documentation Support..........................26
11.1 接收文档更新通知................................................... 26
11.2 支持资源..................................................................26
11.3 Trademarks............................................................. 26
11.4 Electrostatic Discharge Caution..............................26
11.5 术语表..................................................................... 26
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information....................................................7
6.5 DC Electrical Characteristics...................................... 7
6.6 High Speed Electrical Characteristics.........................8
6.7 SMBUS/I2C Timing Charateristics..............................9
6.8 Typical Characteristics..............................................10
6.9 Typical Jitter Characteristics..................................... 11
7 Detailed Description......................................................12
7.1 Overview...................................................................12
7.2 Functional Block Diagram.........................................12
Information.................................................................... 26
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (December 2021) to Revision A (October 2022)
Page
• Changed the Reset value for the 7-4 Bit in the DEVICE_ID0 Register (Offset = 0xF0) table...........................16
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5 Pin Configuration and Functions
1
38
38
RXA0P
RXA0N
RXB0P
1
GAIN/SDA
RSVD1
2
2
37
37
TX0P
TX0N
3
3
36
36
4
4
35 RXB0N
35
5
34
34
RXA1P
RXA1N
RXB1P
RXB1N
GND
VCC
GND
5
6
6
33
33
TX1P
TX1N
7
7
32
32
8
8
31
31
EP=GND
9
9
30
30
GND
RXA2P
RXA2N
RXB2P
RXB2N
TX2P 10
10
29
29
11
28
28
TX2N
RSVD2
VCC
11
12
12
27
27
13
13
26
26
TX3P
TX3N
14
14
25
25
RXA3P
RXA3N
15
15
24
24
16
GND 16
23
23 RXB3P
SEL
17
17
22
RXB3N
22
图5-1. RUA Package, 42-Pin WQFN (Top View)
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表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
Sets device control configuration modes. The 5-level IO pin is defined in 表7-1.
The pin can be exercised at device power up or in normal operation mode.
L0: Pin Mode –device control configuration is done solely by strap pins.
L1 or L2: SMBus/I2C Mode –device control configuration is done by an external
controller with SMBus/I2C primary. This pin along with ADDR pin sets devices
secondary address.
MODE
41
I, 5-level
L3 and L4 (Float): RESERVED –TI internal test modes.
EQ0 /ADDR
EQ1
40
20
I, 5-level
I, 5-level
In Pin Mode:
The EQ0 and EQ1 pins sets receiver linear equalization CTLE (AC gain) for all
channels according to 表7-2. These pins are sampled at device power-up only.
In SMBus/I2C Mode:
The ADDR pin in conjunction with MODE pin sets SMBus / I2C secondary address
according to 表7-5. The pin is sampled at device power-up only.
In Pin Mode:
Flat gain (broadbad gain –DC and AC) from the input to the output of the device
for all channels. Note: the device also provides AC (high frequency) gain in the
form of equalization controlled by EQ pins or SMBus/I2C registers. The pin is
sampled at device power-up only.
GAIN /SDA
GND
1
I, 5-level / IO
In SMBus/I2C Mode:
3.3 V SMBus/I2C data. External pullup resistor such as 4.7 kΩ required for
operation.
EP, 6, 9, 16,
21, 30, 39
P
Ground reference for the device.
EP: the Exposed Pad at the bottom of the QFN package. It is used as the GND
return for the device. The EP should be connected to one or more ground planes
through the low resistance path. A via array provides a low impedance path to
GND. The EP also improves thermal dissipation.
PD
18
I, 3.3-V LVCMOS 2-level logic controlling the operating state of the redriver. Active in both Pin Mode
and SMBus/I2C Mode. The pin is used part of PCIe RX_DET state machine as
outlined in 表7-4.
High: power down for all channels
Low: power up, normal operation for all channels
RSVD1, 2
2, 12
42
—
Reserved pins –for best signal integrity performance connect the pins to GND.
Alternate option would be 0 Ω resistors from pins to GND.
RX_DET /SCL
I, 5-level / IO
In Pin Mode:
Sets receiver detect state machine options according to 表7-4. The pin is sampled
at device power-up only.
In SMBus/I2C Mode:
3.3 V SMBus/I2C clock. External pullup resistor such as 4.7 kΩ required for
operation.
RXA0N
RXA0P
RXA1N
RXA1P
RXA2N
RXA2P
RXA3N
RXA3P
RXB0N
RXB0P
RXB1N
RXB1P
RXB2N
RXB2P
37
38
33
34
28
29
24
25
35
36
31
32
26
27
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Inverting differential RX input –Port A, Channel 0.
Noninverting differential RX input –Port A, Channel 0.
Inverting differential RX input –Port A, Channel 1.
Noninverting differential RX input –Port A, Channel 1.
Inverting differential RX input –Port A, Channel 2.
Noninverting differential RX input –Port A, Channel 2.
Inverting differential RX input –Port A, Channel 3.
Noninverting differential RX input –Port A, Channel 3.
Inverting differential RX input –Port B, Channel 0.
Noninverting differential RX input –Port B, Channel 0.
Inverting differential RX input –Port B, Channel 1.
Noninverting differential RX input –Port B, Channel 1.
Inverting differential RX input –Port B, Channel 2.
Noninverting differential RX input –Port B, Channel 2.
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表5-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
RXB3N
RXB3P
SEL
NO.
22
I
I
Inverting differential RX input –Port B, Channel 3.
Noninverting differential RX input –Port B, Channel 3.
23
17
I, 3.3 V LVCMOS Selects the mux path. Active in both Pin Mode and SMBus/I2C Mode. The pin has
a weak internal pull-down resistor. Note: the SEL pin must be exercised in system
implementations for mux selection between Port A vs Port B. The pin is used for
PCIe RX_DET state machine as outlined in 表7-4.
L: Port A selected.
H: Port B selected.
TX0N
TX0P
TX1N
TX1P
TX2N
TX2P
TX3N
TX3P
TEST
VCC
4
3
O
O
O
O
O
O
O
O
O
P
Inverting differential TX output, Channel 0.
Noninverting differential TX output, Channel 0.
Inverting differential TX output, Channel 1.
Noninverting differential TX output, Channel 1.
Inverting differential TX output, Channel 2.
Noninverting differential TX output, Channel 2.
Inverting differential TX output, Channel 3.
Noninverting differential TX output, Channel 3.
TI internal test pin. Keep no connect.
8
7
11
10
15
14
19
5, 13
Power supply, VCC = 3.3 V ± 10%. The VCC pins on this device should be
connected through a low-resistance path to the board VCC plane.
(1) I = input, O = output, P = power, GND = ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
MAX
4.0
UNIT
V
VCCABSMAX
VIOCMOS,ABSMAX
VIO5LVL,ABSMAX
VIOHS-RX,ABSMAX
VIOHS-TX,ABSMAX
TJ,ABSMAX
Supply voltage (VCC)
3.3 V LVCMOS and open drain I/O voltage
5-level input I/O voltage
4.0
V
2.75
3.2
V
High-speed I/O voltage (RXnP, RXnN)
High-speed I/O voltage (TXnP, TXnN)
Junction temperature
V
2.75
150
150
V
°C
°C
Tstg
Storage temperature range
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2 kV
may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
DC plus AC power should not
exceed these limits
VCC
NVCC
Supply voltage, VCC to GND
Supply noise tolerance
3.0
3.3
3.6
V
DC to <50 Hz, sinusoidal1
250
100
33
mVpp
mVpp
mVpp
50 Hz to 500 kHz, sinusoidal1
500 kHz to 2.5 MHz, sinusoidal1
Supply noise, >2.5 MHz,
sinusoidal1
10
mVpp
TRampVCC
VCC supply ramp time
From 0 V to 3.0 V
0.150
100
115
85
ms
°C
°C
TJ
Operating junction temperature
Operating ambient temperature
Minimum pulse width required for
0
0
TA
PWLVCMOS the device to detect a valid signal PD and SEL
on LVCMOS inputs
200
μs
SMBus/I2C SDA and SCL open
drain termination voltage
Supply voltage for open drain
pull-up resistor
VCCSMBUS
FSMBus
3.6
V
SMBus/I2C clock (SCL) frequency
in SMBus secondary mode
10
400
kHz
Source differential launch
amplitude
VIDLAUNCH
DR
800
1
1200
32
mVpp
Gbps
Data rate
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6.4 Thermal Information
SN75LVPE54
THERMAL METRIC(1)
UNIT
21
RUA, 42 Pins
RθJA-High K
RθJC(top)
RθJB
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
26.1
14.1
8.7
℃/W
℃/W
℃/W
℃/W
℃/W
℃/W
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.6
ψJT
8.6
ψJB
RθJC(bot)
2.6
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
6.5 DC Electrical Characteristics
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power
PACT
Device active power
All channels enabled (PD = L)
All channels disabled (PD = H)
720
23
970
36
mW
mW
Device power consumption in standby
power mode
PSTBY
Control IO
VIH
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
SDA, SCL, PD, SEL pins
2.1
2.1
V
V
V
V
VIL
SDA, SCL, PD, SEL pins
1.08
VOH
Rpull-up = 4.7 kΩ (SDA, SCL pins)
IOL = –4 mA (SDA, SCL pins)
VOL
0.4
100
10
Input high leakage current for SEL
pins
IIH,SEL
VInput = VCC, for SEL pin
µA
IIH
IIL
Input high leakage current
Input low leakage current
VInput = VCC, (SCL, SDA, PD pins)
µA
µA
VInput = 0 V, (SCL, SDA, PD, SEL pins)
-10
Input high leakage current for fail safe VInput = 3.6 V, VCC = 0 V, (SCL, SDA,
IIH,FS
200
10
µA
pF
input pins
PD, SEL pins)
CIN-CTRL
Input capacitance
SCL, SDA, PD, SEL pins
1.6
5 Level IOs (MODE, GAIN, EQ1, EQ0, RX_DET pins)
IIH_5L Input high leakage current, 5 level IOs VIN = 2.5 V
µA
µA
Input low leakage current for all 5 level
IOs except MODE.
IIL_5L
VIN = GND
VIN = GND
-10
Input low leakage current for MODE
pin
IIL_5L,MODE
-200
µA
Receiver
VRX-DC-CM
ZRX-DC
RX DC common mode voltage
Rx DC single-ended impedance
Device is in active or standby state
Inputs are at VRX-DC-CM voltage
1.4
50
V
Ω
ZRX-HIGH-IMP- DC input CM input impedance during
20
kΩ
Reset or power-down
DC-POS
Transmitter
Impedance of Tx during active
signaling, VID, diff = 1 Vpp
ZTX-DIFF-DC
VTX-DC-CM
ITX-SHORT
DC differential Tx impedance
Tx DC common mode Voltage
Tx short circuit current
100
1.0
70
Ω
V
Total current the Tx can supply when
shorted to GND
mA
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6.6 High Speed Electrical Characteristics
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Receiver
50 MHz to 1.25 GHz
-22
-22
-22
-16
-9
dB
dB
dB
dB
dB
dB
dB
dB
1.25 GHz to 2.5 GHz
2.5 GHz to 4.0 GHz
4.0 GHz to 8.0 GHz
8.0 GHz to 16 GHz
50 MHz to 2.5 GHz
2.5 GHz to 8.0 GHz
8.0 GHz to 16 GHz
RLRX-DIFF
Input differential return loss
-20
-14
-8
RLRX-CM
Input common-mode return loss
Receive-side pair-to-pair isolation
Pair-to-pair isolation (SDD21) between
two adjacent receiver pairs from 10
MHz to 16 GHz.
XTRX
-55
dB
Transmitter
Measured with lowest EQ, GAIN = L4;
PRBS-7, 32 Gbps, over at least
106 bits using a bandpass filter from 30
kHz to 500 MHz
Tx AC peak-to-peak common mode
voltage
VTX-AC-CM-PP
50
mVpp
mV
Measured while Tx is sensing whether
a low-impedance receiver is present.
No load is connected to the driver
output
VTX-RCV-
Amount of voltage change allowed
during receiver detection
0
600
DETECT
50 MHz to 1.25 GHz
1.25 GHz to 2.5 GHz
2.5 GHz to 4.0 GHz
4.0 GHz to 8.0 GHz
8.0 GHz to 16 GHz
50 MHz to 2.5 GHz
2.5 GHz to 8.0 GHz
8.0 GHz to 16 GHz
-22
-22
-21
-15
-9
dB
dB
dB
dB
dB
dB
dB
dB
RLTX-DIFF
Output differential return loss
-16
-12
-11
RLTX-CM
Output common-mode return loss
Transmit-side pair-to-pair isolation
Minimum pair-to-pair isolation
(SDD21) between two adjacent
transmitter pairs from 10 MHz to 16
GHz.
XTTX
-45
90
dB
Device Datapath
Input-to-output latency (propagation
For either low-to-high or high-to-low
transition.
TPLHD/PHLD
130
20
ps
ps
delay) through a data channel
Between any two lanes within a single
transmitter.
LTX-SKEW
Lane-to-lane output skew
Jitter through redriver minus the
calibration trace. 32 Gbps PRBS15.
800 mVpp-diff input swing.
TRJ-DATA
Additive random jitter with data
55
35
fs
fs
Jitter through redriver minus the
calibration trace. 32 GHz clock. 800
mVpp-diff input swing.
Intrinsic additive random jitter with
clock
TRJ-INTRINSIC
Jitter through redriver minus the
calibration trace. 32 Gbps PRBS15.
800 mVpp-diff input swing.
JITTERTOTAL-
Additive total jitter with data
1.0
0.1
ps
ps
DATA
Jitter through redriver minus the
calibration trace. 16 GHz clock. 800
mVpp-diff input swing.
JITTERTOTAL-
Intrinsic additive total jitter with clock
INTRINSIC
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6.6 High Speed Electrical Characteristics (continued)
over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Minimum EQ, GAIN1/0=L0
Minimum EQ, GAIN1/0=L1
Minimum EQ, GAIN1/0=L2
Minimum EQ, GAIN1/0=L3
Minimum EQ, GAIN1/0=L4 (Float)
MIN
TYP
-5.6
-3.8
-1.2
2.6
MAX
UNIT
dB
dB
Broadband DC and AC flat gain - input
to output, measured at DC
FLAT-GAIN
EQ-MAX16G
dB
dB
0.6
dB
EQ boost at max setting (EQ INDEX = AC gain at 16 GHz relative to gain at
24
1700
930
dB
19)
100 MHz.
LINEARITY-
DC
Output DC linearity
at 0 dB flat gain
mVpp
mVpp
LINEARITY-
AC
Output AC linearity at 32 Gbps
at 0 dB flat gain
6.7 SMBUS/I2C Timing Charateristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Secondary Mode
Pulse width of spikes which must be
suppressed by the input filter
tSP
50
ns
µs
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated
tHD-STA
0.6
tLOW
LOW period of the SCL clock
HIGH period of the SCL clock
1.3
0.6
µs
µs
THIGH
Set-up time for a repeated START
condition
tSU-STA
0.6
µs
tHD-DAT
TSU-DAT
Data hold time
Data setup time
0
µs
µs
0.1
Rise time of both SDA and SCL
signals
tr
120
2
ns
Pull-up resistor = 4.7 kΩ, Cb = 10 pF
Pull-up resistor = 4.7 kΩ, Cb = 10 pF
tf
Fall time of both SDA and SCL signals
Set-up time for STOP condition
ns
µs
tSU-STO
0.6
1.3
Bus free time between a STOP and
START condition
tBUF
µs
tVD-DAT
tVD-ACK
Cb
Data valid time
0.9
0.9
µs
µs
pF
Data valid acknowledge time
Capacitive load for each bus line
400
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6.8 Typical Characteristics
图6-1 shows typical EQ gain curves versus frequency for different EQ settings. 图6-2 shows EQ gain variation over
temperature for maximum EQ setting of 19. 图6-3 shows typical differential return loss for Rx and Tx pins.
30
25
20
15
10
5
30
25
20
15
10
5
0
0
-5
EQ=0
EQ=1
EQ=2
EQ=3
EQ=4
EQ=5
EQ=6
EQ=7
EQ=8
EQ=9
EQ=10
EQ=11
EQ=12
EQ=13
EQ=14
EQ=15
EQ=16
EQ=17
EQ=18
EQ=19
-5
-10
-15
-20
Temperature = 25 C
Temperature = 0 C
Temperature = 85 C
-10
-15
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
Frequency (GHz)
Frequency (GHz)
图6-1. Typical EQ Boost vs Frequency
图6-2. Typical EQ Boost vs Frequency at Different Temperature
with EQ=19
5
0
-5
-10
-15
-20
-25
-30
-35
-40
RX SD11
TX SD22
PCIe 5.0 Mask
0
5
10
15
20
25
30
35
40
Frequency (GHz)
图6-3. Typical Differential Return Loss
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6.9 Typical Jitter Characteristics
图6-4, 图6-5, and 图6-6 illustrate eye diagrams at source, through calibration traces, and through SN75LVPE5421
respectively.
图6-4. 32 Gbps 800 mV PRBS15 Source (1 dB Loss)
图6-5. Through Calibration Trace (6.5 dB Loss)
图6-6. Through SN75LVPE5421 (6.5 dB loss and DUT EQ=0)
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7 Detailed Description
7.1 Overview
The SN75LVPE5421 is a four channel linear redriver with ingrated multiplexer (mux). The low-power high-
performance linear repeater or redriver is designed to support PCIe 1.0, 2.0, 3.0, 4.0, and 5.0. The device is a
protocol agnostic linear redriver that can operate for other AC-coupled interface up to 32 Gbps.
The signal channels of the SN75LVPE5421 operate independently from one another. Each channel includes a
continuous-time linear equalizer (CTLE) and a linear output driver, which together compensate for a lossy
transmission channel between the source transmitter and the final receiver. The linearity of the data path is
specifically designed to preserve any transmit equalization while keeping PCIe receiver's (either from Root
Complex or Endpoint) equalization effective.
The SN75LVPE5421 can be configured in two different ways:
Pin Mode – device control configuration is done solely by strap pins. Pin mode is expected to be good enough
for many system implementation needs.
SMBus/I2C Secondary Mode – provides most flexibility. Requires an external SMBus/I2C primary device to
configure SN75LVPE5421 though writing to its secondary address.
7.2 Functional Block Diagram
One of Four 2:1 Mul plexer Modules
RX Detect
Term
Term
RXAnP
RXAnN
TXnP
TXnN
Linear
Driver
CTLE
CTLE
RXBnP
RXBnN
Term
Select
mux
control
RX
Detect
Control
Driver
Control
CTLE
Control
VCC
Voltage Regulator
Power-
On Reset
Always-On
10 MHz
Shared Digital Core
GAIN/SDA
RX_DET/SCL
Shared Digital
GND
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7.3 Feature Description
7.3.1 Five-Level Control Inputs
The SN75LVPE5421 has five 5-level inputs pins (EQ1, EQ0, GAIN, MODE, and RX_DET) that are used to
control the configuration of the device. These 5-level inputs use a resistor divider to help set the 5 valid levels
and provide a wider range of control settings. External resistors must be of 10% tolerance or better. The EQ0,
EQ1, GAIN, and RX_DET pins are sampled at power-up only. The MODE pin can be exercised at device power
up or in normal operation mode.
表7-1. 5-Level Control Pin Settings
LEVEL
L0
SETTING
1 kΩ to GND
8.25 kΩ to GND
24.9 kΩ to GND
75 kΩ to GND
F (Float)
L1
L2
L3
L4
7.3.2 Linear Equalization
The SN75LVPE5421 receivers feature a continuous-time linear equalizer (CTLE) that applies high-frequency
boost and low-frequency attenuation to help equalize the frequency-dependent insertion loss effects of a passive
channel. The receivers implement two stage linear equilizer for wide range of equalization capability. The
equalizer stages also provide flexibility to make subtle modifications of mid-frequency boost for best EQ gain
profile match with wide range of channel media characteristics. The EQ profile control feature is only available in
SMBus/I2C Mode. In Pin Mode the settings are optimized for FR4 traces.
表 7-2 shows available equalization boost through EQ control pins or SMBus/I2C registers. In Pin Control mode
EQ1 and EQ0 pins set equalization boost for all channels. In I2C Mode individual channels can be independently
programmed for EQ boost.
表7-2. Equalization Control Settings
EQUALIZATION SETTING
SMBus/I2C Mode
TYPICAL EQ BOOST (dB)
Pin Mode
0
1
L0
L0
L0
L0
L0
L1
L1
L1
L1
L1
L2
L2
L2
L0
L1
L2
L3
L4
L0
L1
L2
L3
L4
L0
L1
L2
0
1
3
7
7
0
1
2
3
4
5
6
8
0
0
0
0
1
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
3
3
7
7
7
1
1
1
1
1
0
0
0
0
0
0
0
0
2.0
4.0
4.0
6.0
2
5.0
8.0
3
7.0
10.0
12.0
12.0
13.0
14.0
15.0
15.5
16.0
17.0
17.5
4
8.0
5
7.0
6
7.5
7
8.0
8
9.0
9
10.0
10.5
11.0
12.0
10
11
12
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表7-2. Equalization Control Settings (continued)
EQUALIZATION SETTING
SMBus/I2C Mode
TYPICAL EQ BOOST (dB)
Pin Mode
13
14
15
16
17
18
19
L2
L2
L3
L3
L3
L3
L3
L3
L4
L0
L1
L2
L3
L4
10
10
11
12
13
14
15
1
2
3
4
5
6
7
7
0
0
0
0
0
0
0
12.5
13.0
14.0
15.0
16.0
16.5
17.0
18.5
19.0
20.0
21.0
22.0
23.0
24.0
15
15
15
15
15
15
7.3.3 Flat Gain
The GAIN pin can be used to set the overall datapath flat gain (broadband gain including high frequency) of the
SN75LVPE5421 when the device is in Pin Mode. The pin GAIN sets the Flat-Gain for all channels. In I2C Mode
each channel can be independently set. 表 7-3 shows flat gain control configuration settings. The default
recommendation for most systems will be GAIN = L4 (float) that provides flat gain of 0 dB.
The flat gain and equalization of the SN75LVPE5421 must be set such that the output signal swing at DC and
high frequency does not exceed the DC and AC linearity ranges of the devices, respectively.
表7-3. Flat Gain Configuration Settings
Pin Mode
GAIN
I2C Mode
flat_gain_2:0
Flat Gain
L0
L1
0
1
3
7
5
−5.6 dB
−3.8 dB
−1.2 dB
L2
L3
+2.6 dB
L4 (float)
+0.6 dB (default recommendation)
7.3.4 Receiver Detect State Machine
The SN75LVPE5421 deploys an RX detect state machine that governs the RX detection cycle as defined in the
PCI express specifications. At device power up or through manually triggered event using PD or SEL pin or
writing to the relevant I2C/SMBus register, the redriver determines whether or not a valid PCI express
termination is present at the far end of the link. The RX_DET pin of SN75LVPE5421 provides additional flexibility
for system designers to appropriately set the device in desired mode according to 表 7-4. For the PCIe
application the RX_DET pin can be left floating for default settings.
Note: power up ramp or PD/SEL event triggers RX detect for all four channels. In applications where
SN75LVPE5421 channels are used for multiple PCIe links, the RX detect function can be performed for
individual channels through writing in appropriate I2C/SMBus registers.
表7-4. Receiver Detect State Machine Settings
PD
RX_DET
RX Common-mode Impedance
COMMENTS
PCI Express RX detection state machine is disabled.
Recommended for non PCIe interface use case where the
SN75LVPE5421 is used as buffer with equalization.
L
L0
Always 50 Ω
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表7-4. Receiver Detect State Machine Settings (continued)
PD
RX_DET
RX Common-mode Impedance
COMMENTS
L
L1
Pre Detect: Hi-Z
Outputs polls until 3 consecutive valid detections
Post Detect: 50 Ω.
L
L
L2
L3
Pre Detect: Hi-Z
Post Detect: 50 Ω.
Outputs polls until 2 consecutive valid detections
Reserved
Pre Detect: Hi-Z
Post Detect: 50 Ω.
TX polls every ≅150 µs until valid termination is detected. RX CM
impedance held at Hi-Z until detection Reset by asserting PD high
for 200 µs then low. Recommended default setting for PCIe.
Pre Detect: Hi-Z
Post Detect: 50 Ω.
L
L4 (Float)
X
H
Hi-Z
Reset Channels and set their RX impedance to Hi-Z
7.4 Device Functional Modes
7.4.1 Active PCIe Mode
The device is in normal operation with PCIe state machine enabled by RX_DET = L4 (float). This mode is
recommended for PCIe use cases. In this mode, the PD pin is driven low in a system (for example, by PCIe
connector PRSNT signal). In this mode, the device redrives and equalizes PCIe RX or TX signals to provide
better signal integrity.
7.4.2 Active Buffer Mode
The device is in normal operation with PCIe state machine disabled by RX_DET = L0. This mode is
recommended for non-PCIe use cases. In this mode, the device is working as a buffer to provide linear
equalization to improve signal integrity.
7.4.3 Standby Mode
The device is in standby mode invoked by PD = H. In this mode, the device is in standby mode conserving
power.
7.5 Programming
7.5.1 Pin Mode
The SN75LVPE5421 can be fully configured through pin-strap pins. In this mode the device uses 2-level and 5-
level pins for device control and signal integrity optimum settings.
7.5.2 SMBUS/I2C Register Control Interface
If MODE = L2 (SMBus / I2C secondary control mode), the SN75LVPE5421 is configured for best signal integrity
through a standard I2C or SMBus interface that may operate up to 400 kHz. The secondary address of the
SN75LVPE5421 is determined by the pin strap settings on the ADDR and MODE pins. 表 7-5 provides the eight
possible secondary addresses (7-bit) for each channel banks of the device. In SMBus/I2C modes the SCL, SDA
pins must be pulled up to a 3.3 V supply with a pull-up resistor. The value of the resistor depends on total bus
capacitance. 4.7 kΩis a good first approximation for a bus capacitance of 10 pF.
表7-5. SMBUS/I2C Secondary Address Settings
7-bit Secondary Address
Channels 0-1
7-bit Secondary Address
Channels 2-3
MODE
ADDR
L1
L1
L1
L1
X
L0
L1
L2
L3
L4
L0
L1
0x18
0x1A
0x19
0x1B
0x1C
0x1D
0x1E
0x1F
Reserved
0x20
Reserved
0x21
L2
L2
0x22
0x23
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表7-5. SMBUS/I2C Secondary Address Settings (continued)
7-bit Secondary Address
Channels 0-1
7-bit Secondary Address
MODE
ADDR
Channels 2-3
L2
L2
L2
L3
0x24
0x26
0x25
0x27
The SN75LVPE5421 has two types of registers:
• Shared Registers: These registers can be accessed at any time and are used for device-level configuration,
status read back, control, or to read back the device ID information.
• Channel Registers: These registers are used to control and configure specific features for each individual
channel. All channels have the same register set and can be configured independent of each other or
configured as a group through broadcast writes to Bank 0 or Bank 1.
The SN75LVPE5421 features two banks of channels, Bank 0 (Channels 0-1) and Bank 1 (Channels 2-), each
featuring a separate register set and requiring a unique SMBus secondary address.
Channel Registers Base
Address
Channel Bank 0 Access
Channel Bank 1 Access
0x00
0x20
0x40
0x60
0x80
Channel 0 registers
Channel 0 registers
Channel 1 registers
Channel 1 registers
Channel 2 registers
Channel 2 registers
Channel 3 registers
Channel 3 registers
Broadcast write channel Bank 0 registers,
read channel 0 registers
Broadcast write channel Bank 1 registers,
read channel 2 registers
0xE0
Bank 0 Share registers
Bank 1 Share registers
7.5.2.1 Shared Registers
表7-6. General Registers (Offset = 0xE2)
Bit
7
Field
Type
Reset
Description
RESERVED
rst_i2c_regs
R
0x0
Reserved
6
R/W/SC
0x0
Device reset control: Reset all I2C registers to default values
(self-clearing).
5
rst_i2c_mas
RESERVED
R/W/SC
R
0x0
Reset I2C Primary (self-clearing).
4-0
0x0000
Reserved
表7-7. DEVICE_ID0 Register (Offset = 0xF0)
Bit
7-4
3
Field
Type
Reset
0x0001
0x1
Description
RESERVED
device_id0_3
device_id0_2
device_id0_1
RESERVED
R
Reserved
R
Device ID0 [3:1]: 101
see MSB
2
R
0x0
1
R
0x1
see MSB
0
R
X
Reserved
表7-8. DEVICE_ID1 Register (Offset = 0xF1)
Bit
7
Field
Type
Reset
0x0
0x0
0x1
0x0
0x1
0x0
Description
device_id[7]
device_id[6]
device_id[5]
device_id[4]
device_id[3]
device_id[2]
R
Device ID 0010 1000: SN75LVPE5421
6
R
see MSB
see MSB
see MSB
see MSB
see MSB
5
R
4
R
3
R
2
R
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表7-8. DEVICE_ID1 Register (Offset = 0xF1) (continued)
Bit
1
Field
Type
Reset
Description
device_id[1]
device_id[0]
R
0x0
see MSB
see MSB
0
R
0x1
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7.5.2.2 Channel Registers
表7-9. RX Detect Status Register (Channel Register Base + Offset = 0x00)
Bit
Field
Type
Reset
Description
7
RX_det_comp_p
R
0x0
RX Detect positive data pin status:
0: Not detected
1: Detected –the value is latched
6
RX_det_comp_n
RESERVED
R
R
0x0
0x0
RX Detect negative data pin status:
0: Not detected
1: Detected –the value is latched
5-0
Reserved
表7-10. EQ Gain Control Register (Channel Register Base + Offset = 0x01)
Bit
Field
Type
Reset
Description
7
eq_stage1_bypass
R/W
0x0
Enable EQ stage 1 bypass:
0: Bypass disabled
1: Bypass enabled
6
5
4
3
2
1
0
eq_stage1_3
eq_stage1_2
eq_stage1_1
eq_stage1_0
eq_stage2_2
eq_stage2_1
eq_stage2_0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0
0x0
0x0
0x0
0x0
0x0
0x0
EQBoost stage 1 control
See 表7-2 for details
EQ Boost stage 2 control
See 表7-2 for details
表7-11. EQ Gain / Flat Gain Control Register (Channel Register Base + Offset = 0x03)
Bit
7
Field
Type
Reset
0x0
0x0
0x0
0x0
0x0
0x1
0x0
0x1
Description
RESERVED
eq_profile_3
eq_profile_2
eq_profile_1
eq_profile_0
flat_gain_2
flat_gain_1
flat_gain_0
R
Reserved
6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EQ mid-frequency boost profile
5
See 表7-2 for details
4
3
2
Flat gain select:
1
See 表7-3 for details
0
表7-12. RX Detect Control Register (Channel Register Base + Offset = 0x04)
Bit
7-3
2
Field
Type
Reset
Description
RESERVED
mr_RX_det_man
R
0x0
Reserved
R/W
0x0
Manual override of RX_detect_p/n decision:
0: RX detect state machine is enabled
1: RX detect state machine is overridden –always valid RX
termination detected
1
0
en_RX_det_count
sel_RX_det_count
R/W
R/W
0x0
0x0
Enable additional RX detect polling
0: Additional RX detect polling disabled
1: Additional RX detect polling enabled
Select number of valid RX detect polls –gated by
en_RX_det_count = 1
0: Device transmitters poll until 2 consecutive valid detections
1: Device transmitters poll until 3 consecutive valid detections
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表7-13. PD Override Register (Channel Register Base + Offset = 0x05)
Bit
Field
Type
Reset
Description
7
device_en_override
R/W
0x0
Enable power down overrides thorugh SMBus/I2C
0: Manual override disabled
1: Manual override enabled
6-0
device_en
R/W
0x111111
Manual power down of redriver various blocks –gated by
device_en_override = 1
111111: All blocks are enabled
000000: All blocks are disabled
表7-14. RX Detect Reset Register (Channel Register Base + Offset = 0x0A)
Bit
7-3
2
Field
Type
Reset
Description
RESERVED
mr_RX_det_rst
R
0x0
Reserved
R/W
0x0
RX Detect state machine reset. Toggle the bit if RX Detect
machine needs to be reset in I2C mode
0: state machine is not reset
1: RX detect state machine is reset
1-0
RESERVED
R/W
0x0
Reserved
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The SN75LVPE5421 is a high-speed linear repeater with integrated mux. The device extends the reach of
differential channels impaired by loss from transmission media like PCBs and cables. It can be deployed in a
variety of different systems. The following sections outline typical applications and their associated design
considerations.
8.2 Typical Applications
The SN75LVPE5421 is a PCI Express linear redriver that can also be configured as interface agnostic redriver
by disabling its RX detect feature. The device can be used in a wide range of interfaces including:
• PCI Express
• Ultra Path Interconnect (UPI)
• SATA
• SAS
• DisplayPort
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8.2.1 PCIe x8 Lane Switching
The SN75LVPE5412 and SN75LVPE5421 can be used to switch PCIe lanes from a CPU into one of the two
PCIe CEM connectors. 图8-1 shows a simplified schematic for the following configuration:
• Two SN75LVPE5412 demultiplex eight TX channels from the CPU into one of the two PCIe slots.
• Two SN75LVPE5421 multiplex eight RX channels from one of the two PCIe slots to CPU.
Mux selection
Float
SEL
RX_DET
Linear
Driver
RXnP
RXnN
TXAnP
TXAnN
CTLE
8 TX Chan
8 Lanes
System Level
Power Control
1 of 4
channels
Linear
Driver
PD
TXBnP
TXBnN
GPIO mode
1 k
PCIe
Slot
A
MODE
pin strap control
for DC gain
GAIN
GND
LVPE5412
PCIe Redriver Demux
Pin strap to
fine tune
EQ gain
EQ0
EQ1
settings
VCC
RSVD1,2
VCC
0.1
(2x)
F
1
F
Minimum
recommended
decoupling
X8 Slot
Two LVPE5412
Two LVPE5421
Mux selection
SEL
CPU
(RC)
Float
RX_DET
Linear
Driver
TXnP
TXnN
RXAnP
RXAnN
CTLE
8 RX Chan
8 Lanes
1 of 4
channels
System Level
Power Control
RXBnP
RXBnN
CTLE
PD
PCIe
Slot
B
Optional pin strap
control for DC gain
GPIO mode
GAIN
MODE
LVPE5421
PCIe Redriver Mux
Pin strap to
fine tune
EQ gain
EQ0
EQ1
1 k
GND
settings
VCC
RSVD1,2
VCC
Minimum
recommended
decoupling
1
F
0.1
(2x)
F
X16 Slot
8 Lanes
图8-1. Simplified Schematic for PCIe Lane Switching
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8.2.1.1 Design Requirements
As with any high-speed design, there are many factors which influence the overall performance. The following
list indicates critical areas for consideration during design:
• Use 85 Ωimpedance traces when interfacing with PCIe CEM connectors. Length matching on the P and N
traces should be done on the single-ended segments of the differential pair.
• Use a uniform trace width and trace spacing for differential pairs.
• Place AC-coupling capacitors near to the receiver end of each channel segment to minimize reflections.
• For Gen 3.0, 4.0, and 5.0, AC-coupling capacitors of 220 nF are recommended, set the maximum body size
to 0402, and add a cutout void on the GND plane below the landing pad of the capacitor to reduce parasitic
capacitance to GND.
• Back-drill connector vias and signal vias to minimize stub length.
• Use reference plane vias to ensure a low inductance path for the return current.
8.2.1.2 Detailed Design Procedure
In PCIe Gen 3.0, 4.0, and 5.0 applications, the specification requires RX-TX link training to establish and
optimize signal conditioning settings at 8.0, 16.0, and 32.0 Gbps, respectively. In link training, the RX partner
requests a series of FIR – pre-shoot and de-emphasis coefficients (10 presets) from the TX partner. The RX
partner includes CTLE and DFE. The link training would pre-condition the signal, with an equalized link between
the Root Complex and Endpoint.
Note: there is no link training in PCIe Gen 1.0 (2.5 Gbps) or PCIe Gen 2.0 (5.0 Gbps) applications. The
SN75LVPE5421 is placed in between the TX and RX. It helps extend the PCB trace reach distance by boosting
the attenuated signals with its equalization, which allows the user to recover the signal by the downstream RX
more easily.
For operation in Gen 5.0, 4.0, and 3.0 links, the SN75LVPE5421 transmit outputs are designed to pass the TX
Preset signaling onto the RX for the PCIe Gen 5.0, 4.0, and 3.0 link to train and optimize the equalization
settings. The suggested setting for the device is GAIN = L4 (default). Adjustments to the EQ setting should be
performed based on the channel loss to optimize the eye opening in the RX partner. The TX equalization presets
or CTLE and DFE coefficients in the RX can also be adjusted to further improve the eye opening.
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8.2.2 Protocol Agnostic Linear Redriver for High Speed Interfaces
The SN75LVPE5421 can be used as a four channel protocol agnostic linear redriver multiplexer (mux) for data
rates up to 32 Gbps. To use the device in a non-PCIe application, the RX_DET pin must be pin-strapped to GND
with 1 kΩresistor (L0).
This section explains how the SN75LVPE5421 can be used in DisplayPort (DP) application. The device is a
linear redriver which is agnostic to DP link training. The DP link training negotiation between a display source
and sink stays effective through the device. The redriver becomes part of the electrical channel along with
passive traces, cables, and so forth, resulting in optimum source and sink parameters for best electrical link.
图8-2 shows a simplified schematic for DisplayPort multiplexing application using SN75LVPE5421. Auxiliary and
Hot plug detect (HPD) are muxed outside of the device. If system use case requires implementing DP power
states, then the device must be controlled by the I2C.
AUXAp
For brevity AUX
biasing is not shown
AUXAn
HPDA
AUXp
TS3A5223
AUXn
HPD
2-Ch 2:1 mux
AUXBp
AUXBn
HPDB
Demux control
AUXAp
SEL
AUXAn
HPDA
RX_DET
DisplayPort
Port A
1 k
GND
Linear
Driver
RXAnP
RXAnN
TXnP
TXnN
CTLE
CTLE
3.3 V
59 k
DisplayPort
Sink
AUXp
1 of 4
channels
RXBnP
RXBnN
PD
AUXn
HPD
DisplayPort
Port B
AUXBp
0.1
100 k
HPD
F
AUXBn
HPDB
GPIO mode
1 k
MODE
LVPE5421
DP Main Link Redriver
2:1 Mux
Optional pin strap
control for DC gain
GAIN
GND
EQ0
EQ1
Pin strap to fine tune
EQ gain settings
VCC
VCC
0.1
(2x)
F
1
F
Minimum
recommended
decoupling
图8-2. Simplified Schematic for DisplayPort Multiplexer Application
The inverted DisplayPort HPD signal can be used to put the device into standby mode by using its PD pin. Note:
in a DisplayPort link a sink can use HPD line to create an interrupt for its link partner source. If HPD signal is
used for power management, then an RC filter must be installed to filter out HPD interrupt signals.
The SN75LVPE5421 can similarly be used for other AC-coupled high speed interfaces. Care must be taken to
understand the specifications of the interface to ensure feasibility.
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9 Power Supply Recommendations
Follow these general guidelines when designing the power supply:
1. The power supply should be designed to provide the operating conditions outlined in the recommended
operating conditions section in terms of DC voltage, AC noise, and start-up ramp time.
2. The SN75LVPE5421 does not require any special power supply filtering, such as ferrite beads, provided that
the recommended operating conditions are met. Only standard supply decoupling is required. Typical supply
decoupling consists of a 0.1 µF capacitor per VCC pin, one 1.0 µF bulk capacitor per device, and one 10 µF
bulk capacitor per power bus that delivers power to one or more devices. The local decoupling (0.1 µF)
capacitors must be connected as close to the VCC pins as possible and with minimal path to the device
ground pad.
10 Layout
10.1 Layout Guidelines
The following guidelines should be followed when designing the layout:
1. Decoupling capacitors should be placed as close to the VCC pins as possible. Placing the decoupling
capacitors directly underneath the device is recommended if the board design permits.
2. High-speed differential signals TXnP/TXnN and RXnP/RXnN should be tightly coupled, skew matched, and
impedance controlled.
3. Vias should be avoided when possible on the high-speed differential signals. When vias must be used, take
care to minimize the via stub, either by transitioning through most or all layers or by back drilling.
4. GND relief can be used (but is not required) beneath the high-speed differential signal pads to improve
signal integrity by counteracting the pad capacitance.
5. GND vias should be placed directly beneath the device connecting the GND plane attached to the device to
the GND planes on other layers. This has the added benefit of improving thermal conductivity from the
device to the board.
10.2 Layout Example
图10-1 shows SN75LVPE5421 layout example.
图10-1. SN75LVPE5421 Layout Example
图10-2 shows a layout illustration where two SN75LVPE5412 and two SN75LVPE5421 are used to switch 8
lanes between the two PCIe slots.
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图10-2. Layout Example for PCIe Lane Muxing Application
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11 Device and Documentation Support
11.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
PCIe® is a registered trademark of PCI-SIG.
所有商标均为其各自所有者的财产。
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
27-May-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN75LVPE5421RUAR
SN75LVPE5421RUAT
ACTIVE
ACTIVE
WQFN
WQFN
RUA
RUA
42
42
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
0 to 85
0 to 85
5PR421
5PR421
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
27-May-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN75LVPE5421RUAT
WQFN
RUA
42
250
180.0
16.4
3.8
9.3
1.0
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WQFN RUA 42
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
SN75LVPE5421RUAT
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RUA 42
9 x 3.5, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226504/A
www.ti.com
PACKAGE OUTLINE
RUA0042A
WQFN - 0.8 mm max height
S
C
A
L
E
1
.
8
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.6
3.4
A
B
PIN 1 INDEX AREA
9.1
8.9
0.8
0.6
C
SEATING PLANE
0.08 C
0.05
0.00
2.05 0.1
2X 1.5
SYMM
(0.1) TYP
EXPOSED
THERMAL PAD
21
18
17
22
SYMM
43
2X 8
7.55 0.1
0.3
0.2
1
38
42X
42
39
38X 0.5
0.1
C A B
0.5
0.3
42X
PIN 1 ID
0.05
4219139/A 03/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RUA0042A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.05)
SYMM
SEE SOLDER MASK
DETAIL
42X (0.6)
42X (0.25)
42
39
1
38X (0.5)
38
(3.525) TYP
(R0.05) TYP
(
0.2) TYP
VIA
1.17 TYP
SYMM
43
(7.55) (8.8)
17
22
18
21
(0.775)
TYP
(3.3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219139/A 03/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RUA0042A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.56) TYP
42X (0.6)
42X (0.25)
42
39
1
38X (0.5)
38
(R0.05) TYP
(0.585)
TYP
43
SYMM
(8.8)
12X (0.97)
22
17
21
18
12X (0.92)
SYMM
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 12X
EXPOSED PAD 43
69% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219139/A 03/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
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您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
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TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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