SN75LVPE802RTJR [TI]

双通道 8.0Gbps SATA Express 转接驱动器 | RTJ | 20 | 0 to 85;


型号：	SN75LVPE802RTJR
厂家：	TEXAS INSTRUMENTS
描述：	双通道 8.0Gbps SATA Express 转接驱动器 \| RTJ \| 20 \| 0 to 85 驱动商用集成电路驱动器
文件：	总37页 (文件大小：2049K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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SN75LVPE802

ZHCSFG1B –JANUARY 2016–REVISED FEBRUARY 2017

SN75LVPE802 双通道 8Gbps SATA Express 均衡器和转接驱动器

1 特性

3 说明

•

SATA Express 支持

可选均衡和去加重功能

支持热插拔功能

SN75LVPE802 是一款通用型双通道 SATA Express

信号调节器，最高可支持 8Gbps 的数据速率。此器件

支持 SATA Gen 1、2 和 3 规范以及 PCIe 1、2 和

3。SN75LVPE802 由 3.3V 单电源供电运行，并且配

有带自偏置特性的 100Ω 线路端接电阻，适用于交流

耦合。输入端包含一个带外 (OOB) 检测器，可在输入

差分电压低于阈值时自动抑制输出端噪声，同时保持一

个稳定的共模电压。此外，该器件还被设计成依据

SATA 标准处理扩频时钟 (SSC) 传输。

•

接收器检测与带外 (OOB) 支持

集成输出静噪

多速率运行

–

SATA：1.5Gbps、3Gbps、6Gbps

PCIe：2.5Gbps、5Gbps、8Gbps

•

出色的抖动和损耗补偿功能，支持长达 24 英寸

(61cm) 以上的 FR4 走线

SN75LVPE802 通过可选均衡设置来处理其输入端的

互连损耗，能够通过编程来匹配通道中的损耗。对于

3Gbps 及以下的数据速率，SN75LVPE802 可为最大

规格达 50 英寸的 FR4 电路板材料提供信号均衡。对

于 8Gbps 的数据速率，该器件可为最大规格达 40 英

寸的 FR4 材料提供补偿。均衡级别通过设置信号控制

引脚 EQ 来控制。

低功耗

–

< 220mW（典型值）

< 50mW（在自动低功耗模式下）

< 5mW（在待机模式下）

•

20 引脚 4mm x 4mm 四方扁平无引线 (QFN) 封装

较高水平的静电放电 (ESD) 瞬态保护

–

人体模型 (HBM)：10,000V

组件充电模式 (CDM)：1500V

机器放电模式 (MM)：200V

发送侧有两个去加重级别可供选择，用于为输出端提供

0 或 1.2dB 的附加高频损耗补偿。

器件信息⁽¹⁾

•

扩展商业级温度范围为 0°C 至 85°C

器件型号

封装

封装尺寸（标称值）

2 应用

超薄四方扁平无引线

(WQFN) (20)

SN75LVPE802

4.00mm x 4.00mm

•

平板电脑

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

笔记本电脑

台式机

扩展坞

简化电路原理图

Connector

330

Host

VCC

Controller

220nF

RX1P

RX1N

GND

TX2N

TX2P

DEW2

VCC

EQ2

GND

220nF

EQ1

DEW1

TX1P

TX1N

GND

Device

220nF

DE2

470nF

220nF

VCC

DE1

RX2N

RX2P

VCC

SN75LVPE802

330

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLLSET1

SN75LVPE802

ZHCSFG1B –JANUARY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

8.3 Feature Description................................................. 15

8.4 Device Functional Modes........................................ 18

Application and Implementation ........................ 19

9.1 Application Information............................................ 19

9.2 Typical SATA Application ....................................... 19

9.3 SATA Express Applications .................................... 25

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

说明（续）.............................................................. 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 4

7.2 ESD Ratings ............................................................ 4

7.3 Recommended Operating Conditions....................... 4

7.4 Thermal Information.................................................. 4

7.5 Electrical Characteristics........................................... 5

7.6 Timing Requirements................................................ 6

7.7 Switching Characteristics.......................................... 7

7.8 Typical Characteristics.............................................. 9

Detailed Description ............................................ 15

8.1 Overview ................................................................. 15

8.2 Functional Block Diagram ....................................... 15

10 Power Supply Recommendations ..................... 26

11 Layout................................................................... 27

11.1 Layout Guidelines ................................................. 27

11.2 Layout Example .................................................... 28

12 器件和文档支持 ..................................................... 29

12.1 接收文档更新通知 ................................................. 29

12.2 社区资源................................................................ 29

12.3 商标....................................................................... 29

12.4 静电放电警告......................................................... 29

12.5 Glossary................................................................ 29

13 机械、封装和可订购信息....................................... 29

4 修订历史记录

Changes from Revision A (September 2016) to Revision B

Page

•

Changed 图 27 note From: Input Trace Length = 53 in. To: Input Trace Length = 3 in....................................................... 22

Changed title of 图 35 From: Output Eye (TP2) to: Input Eye (TP2) .................................................................................. 23

Changed 图 37 note From: Input Trace Length = 36 in. To: Input Trace Length = 48 in. .................................................. 23

Changed 图 38 note From: Input Trace Length = 36 in. To: Input Trace Length = 48 in. .................................................. 23

Changed title of 图 38 From: Input Eye (TP4) To: Output Eye (TP4) .................................................................................. 23

Changed note in 图 40 From: Output Trace Length = 0 in To: Output Trace Length = 3 in................................................ 24

Changed note in 图 42 From: Output Trace Length = 6 in To: Output Trace Length = 12 in.............................................. 24

Changes from Original (January 2016) to Revision A

Page

•

已将器件状态从“产品预览”更改为“量产数据” .......................................................................................................................... 1

5 说明（续）

该器件支持热插拔功能（要求在差分输入和输出使用交流耦合电容），能够防止器件在热插入（例如，异步信号插/

拔、不带电插/拔、带电插/拔或意外插/拔）情况下遭到损坏。

SN75LVPE802

www.ti.com.cn

ZHCSFG1B –JANUARY 2016–REVISED FEBRUARY 2017

6 Pin Configuration and Functions

RTJ Package

20 Pin (WQFN)

Top View

RX1P

RX1N

GND

15 TX1P

14 TX1N

13 GND

12 RX2N

11 RX2P

LVPE802

TX2N

TX2P

Package Thermal Pad

Pin Functions

I/O

DESCRIPTION

NAME

NO.

Control Pins

DE1⁽¹⁾

DE2⁽¹⁾

I, LVCMOS

Selects de-emphasis settings for CH 1 and CH 2 per 表 1.

Internally tied to V_CC/ 2.

DEW1

I, LVCMOS De-emphasis width control for CH 1 and CH 2.

0 = De-emphasis pulse duration, short

DEW2

I, LVCMOS

1 = De-emphasis pulse duration, long (default)

Device enable and disable pin, internally pulled to V_CC

I, LVCMOS 0 = Device in standby mode

1 = Device enabled (default)

EQ1⁽¹⁾

EQ2⁽¹⁾

I, LVCMOS

Select equalization settings for CH 1 and CH 2 per 表 1.

Internally tied to V_CC/ 2.

I, LVCMOS

High Speed Differential I/O

RX1N

RX1P

RX2N

RX2P

TX1N

TX1P

TX2N

TX2P

POWER

GND

I, CML

O, VML

Non-inverting and inverting CML differential input for CH 1 and CH 2. These pins connect to

an internal voltage bias via a dual termination resistor circuit.

Non-inverting and inverting VML differential input for CH 1 and CH 2. These pins connect to

an internal voltage bias via a dual termination resistor circuit.

3, 13, 18

10, 20

Power

Supply ground

VCC

Positive supply must be 3.3V ± 10%

(1) Internally biased to V_CC/ 2 with >200-Ωk pullup or pulldown. When 3-state pins are left as NC, board leakage at the pin pad must be < 1

µA; otherwise, drive to V_CC/ 2 to assert mid-level state.

SN75LVPE802

ZHCSFG1B –JANUARY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.5

MAX

UNIT

Supply Voltage Range⁽²⁾, V_CC

Differential I/O

Voltage Range

Control I/O

VCC + 0.5

Continuous power dissipation

Storage temperature, T_stg

See Thermal Information

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential voltages, are with respect to network ground terminal.

7.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±10000

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

Machine model⁽³⁾

V_(ESD)

Electrostatic discharge

±1500

±200

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(3) Tested in accordance with JEDEC Standard 22, Test Method A115-A

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

3.3

MAX

UNIT

V_CC

Supply Voltage

3.6

C_(coupling)

T_A

Coupling Capacitor

Operating free-air temperature

°C

7.4 Thermal Information

SN75LVPE802

THERMAL METRIC⁽¹⁾

RTJ (WQFN)

UNIT

20 PINS

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.5

ψ_JB

0.9

R_θJC(bot)

15.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

SN75LVPE802

www.ti.com.cn

ZHCSFG1B –JANUARY 2016–REVISED FEBRUARY 2017

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DEWX = EN = VCC, EQX = DEX = NC,

K28.5 pattern at 6 Gbps, V_ID= 700 mVpp

P_D

Power dissipation in active mode

188

205

EN = 0 V, DEWX = EQX = DEX = NC,

K28.5 pattern at 6 Gbps, V_ID= 700 mVpp

P_SD

Power dissipation in standby mode

Active mode supply current

EN = 3.3 V, DEWX = EQX = DEX = NC,

K28.5 pattern at 6 Gbps, V_ID= 700 mVpp

I_CC

I_CC(STDBY)

Standby mode supply current

Maximum data rate

EN = 0 V

Gbps

OOB

V_(OOB)

Input OOB threshold

F = 750 MHz

150

mVpp

DV_diff(OOB)

DV_CM(OOB)

OOB differential delta

OOB common-mode delta

CONTROL LOGIC

V_IH

High-level input voltage

For all control pins

1.4

V_IL

Low-level input voltage

Input hysteresis

0.5

V_IN(HYS)

115

µA

EQx, DEx = VCC

EN, DEWx = VCC

EQx, DEx = GND

EN, DEWx = GND

I_IH

High-level input current

–30

–10

I_IL

RECEIVER AC/DC

Low-level input current

Z_(DIFFRX)

Z_(SERX)

V_CM(RX)

Differential-Input Impedance

100

115

Single-Ended Input Impedance

Common-mode voltage

1.8

f = 150 MHz – 300 MHz

f = 300 MHz – 600 MHz

f = 600 MHz – 1.2 GHz

f = 1.2 GHz – 2.4 GHz

f = 2.4 GHz – 3 GHz

f = 3 GHz – 5 GHz

R_L(DiffRX)

Differential mode return Loss (R_L)

R_{X(DiffRLSlope)}Differential mode R_Lslope

f = 300 MHz – 6 GHz

f = 150 MHz – 300 MHz

f = 300 MHz – 600 MHz

f = 600 MHz – 1.2 GHz

f = 1.2 GHz – 2.4 GHz

f = 2.4 GHz – 3 GHz

f = 3 GHz – 5 GHz

dB/dec

R_L(CMRX)

Common mode return loss

Differential input voltage PP

V_(diffRX)

f = 1.5 GHz and 3 GHz

f = 150 MHz – 300 MHz

f = 300 MHz – 600 MHz

f = 600 MHz – 1.2 GHz

f = 1.2 GHz – 2.4 GHz

f = 2.4 GHz – 3 GHz

f = 3 GHz – 5 GHz

120

1600

mVppd

I_B(RX)

Impedance Balance

f = 5 GHz – 6.5 GHz

TRANSMITTER AC/DC

Z_(diffTX)Pair differential impedance

Z_(SETX)

100

122

1.2

Single-Ended input Impedance

Sequencing transient voltage

Transient voltages on the serial data bus

during power sequencing (lab load)

V_(TXtrans)

–1.2

SN75LVPE802

ZHCSFG1B –JANUARY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f = 150 MHz – 300 MHz

f = 300 MHz – 600 MHz

f = 600 MHz – 1.2 GHz

f = 1.2 GHz – 2.4 GHz

f = 2.4 GHz – 3 GHz

f = 3 GHz – 5 GHz

f = 300 MHz to 3 GHz

f = 150 MHz – 300 MHz

f = 300 MHz – 600 MHz

f = 600 MHz – 1.2 GHz

f = 1.2 GHz – 2.4 GHz

f = 2.4 GHz – 3 GHz

f = 3 GHz – 5 GHz

f = 150 MHz – 300 MHz

f = 300 MHz – 600 MHz

f = 600 MHz – 1.2 GHz

f = 1.2 GHz – 2.4 GHz

f = 2.4 MHz – 3 GHz

f = 3 GHz – 5 GHz

f = 5 GHz – 6.5 GHz

DE1 0r DE2 = 0

R_L(DiffTX)

Diff Mode return Loss

T_{X(DiffRLSlope)}Differential-mode R_Lslope

dB/dec

R_L(CMTX)

Common Mode return Loss

I_(BTX)

Impedance Balance

Output de-emphasis

(relative to transition bit)

DE1 0r DE2 = 1

–2

–4

550

830

630

1.8

DE1 0r DE2 = NC

DE1 0r DE2 = 0

mVppd

Diff_{(VppTX_DE)}Differential output-voltage swing dc level

DE1 0r DE2 = 1

DE1 0r DE2 = NC

At 1.5 GHz

V_{(CMAC_TX)}

TX AC CM Voltage

At 3 GHz

26 dBmV (rms)

30 dBmV (rms)

At 6 GHz

V_(CMTX)

Common-Mode Voltage

TX rise-fall imbalance

TX amplitude imbalance

T_X(R/FImb)

T_X(AmpImb)

At 3 GHz

20%

10%

7.6 Timing Requirements

MIN

NOM

MAX UNIT

DEVICE PARAMETERS

Auto low-power entry time

Auto low-power exit time

TRANSMITTER AC/DC

Electrical idle at input (see 图 24)

105

130

After first signal activity (see 图 24)

t_DE

Input OOB threshold

DEW1 or DEW2 = 0

DEW1 or DEW2 = 1

215

OUT-OF-BAND (OOB)

t_OOB1

t_OOB2

OOB mode enter

OOB mode exit

See 图 23

SN75LVPE802

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ZHCSFG1B –JANUARY 2016–REVISED FEBRUARY 2017

7.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

DEVICE PARAMETERS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Measured using K28.5 pattern

(see 图 1)

t_PDelay

Propagation delay

323

400

t_ENB

t_DIS

Device enable time

Device disable time

EN 0 → 1

EN 1 → 0

µs

RECEIVER AC/DC

Rise times and fall times measured

between 20% and 80% of the signal.

SATA 6-Gbps speed measured 1 in,

(2.5 cm) from device pin.

t_20-80RX

Rise/fall time

Difference between the single-ended

midpoint of the RX+ signal rising or

falling edge, and the single-ended

midpoint of the RX– signal falling or

rising edge.

t_SKEWRX

Differential skew

TRANSMITTER AC/DC

Rise times and fall times measured

between 20% and 80% of the signal.

At 6 Gbps under no load conditions.

t_20-80TX

Rise/fall time

Difference between the single-ended

midpoint of the TX+ signal rising or

falling edge, and the single-ended

midpoint of the TX– signal falling or

rising edge.

t_SKEWTX

Differential skew

TRANSMITTER JITTER

V_ID= 500 mVpp, UI = 333 ps, K28.5

control character

DJ_TX

RJ_TX

DJT_X

RJ_TX

DJ_TX

RJ_TX

Deterministic jitter ⁽¹⁾at CP in

0.06

0.01

0.08

0.09

0.1

UIp-p

ps-rms

UIp-p

V_ID= 500 mVpp, UI = 333 ps, K28.7

control character

Residual Random jitter⁽¹⁾

V_ID= 500 mVpp, UI = 167 ps, K28.5

control character

Deterministic jitter ⁽¹⁾at CP in

0.16

V_ID= 500 mVpp, UI = 167 ps, K28.7

control character

(1)

Residual random jitter

ps-rms

UIp-p

V_ID= 500 mVpp, UI = 125 ps, K28.5

control character

Deterministic jitter ⁽¹⁾at CP in

Residual random jitter⁽¹⁾

0.2

1.5

V_ID= 500 mVpp, UI = 125 ps, K28.7

control character

0.3

ps-rms

(1) (1) T_J= (14.1 x RJSD + DJ), where RJSD is one standard deviation value

SN75LVPE802

ZHCSFG1B –JANUARY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

t_PDELAY

OUT

图 1. Propagation Delay Timing Diagram

SN75LVPE802

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ZHCSFG1B –JANUARY 2016–REVISED FEBRUARY 2017

7.8 Typical Characteristics

Input signal characteristics:

•

Data rate = 8 Gbps 6 bps, 3 Gbps, 1.5 Gbps

Amplitude = 500 mVpp

o Data pattern = K28.5

SN75LVPE802 device setup:

•

Temperature = 25°C

Voltage = 3.3 V

De-emphasis duration = 117 ps (short)

Equalization and de-emphasis set to optimize performance at 6 Gbps

With LVPE802

16-in, 4-mil FR4 Trace

8-in, 4-mil FR4 Trace

+ 2-in, 9.5-mil FR4 Trace

+2-in, 9.5-mil FR4 Trace

Agilent

ParBERT

Agilent

DCA-J

LVPE802

TP1

TP2

TP3

TP4

Without LVPE802

16-in, 4-mil FR4 Trace

+ 4-in, 9.5-mil FR4 Trace

+ 8in, 4-mil FR4 Trace

Agilent

ParBERT

Agilent

DCA-J

TP1

TP4

图 2. Performance Curve Measurement Setup

SN75LVPE802

ZHCSFG1B –JANUARY 2016–REVISED FEBRUARY 2017

www.ti.com.cn

Typical Characteristics (接下页)

图 3. Jitter Measurement Test Condition

SN75LVPE802

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ZHCSFG1B –JANUARY 2016–REVISED FEBRUARY 2017

7.8.1 Jitter and VOD results: Case 1 at 6 Gbps

Eye

(1e-12)

(σ-σ)

(rms)

Amplitude

Width

Opening

(mV)

(1e-12)

(σ-σ)

(rms)

Amplitude

Width

Opening

(mV)

3.3

1.88

412.4

159.2

350.52

91.8

65.4

1.93

240

28.9

81.24

图 4. Test Point 1

图 5. Test Point 2

Eye

(1e-12)

(σ-σ)

15.9

(rms)

1.91

Amplitude

788.8

Width

141.3

Opening

(mV)

623.02

(1e-12)

(σ-σ)

12.7

(rms)

1.92

Amplitude

557.1

Width

149.7

Opening

(mV)

459.62

图 6. Test Point 3

图 7. Test Point 4 With LVPE802

Eye

(1e-12) ps

56.7

(σ-σ) ps

29.8

(rms) ps

Amplitude mV

165.4

Width ps

101

Opening (mV)

13.24

图 8. Test Point 4 Without LVPE802

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7.8.2 Jitter and VOD Results: Case 2 at 3 Gbps

Eye

(1e-12)

72.7

(σ-σ)

46.8

(rms)

1.89

Amplitude

314.9

Width

237

Opening

(mV)

222.36

(1e-12)

29.7

(σ-σ)

3.8

(rms)

1.89

Amplitude

430.9

Width

326

Opening

(mV)

392.84

图 10. Test Point 2

图 9. Test Point 1

Eye

(1e-12)

47.9

(σ-σ)

20.3

(rms)

1.99

Amplitude

615.3

Width

305.0

Opening

(mV)

463.42

(1e-12)

39.6

(σ-σ)

12.8

(rms)

1.96

Amplitude

714.5

Width

321

Opening

(mV)

611.62

图 12. Test Point 4 With LVPE802

图 11. Test Point 3

Eye

(1e-12) ps

128.6

(σ-σ) ps

101.8

(rms) ps

1.96

Amplitude mV

258.8

Width ps

118

Opening (mV

122.26

图 13. Test Point 4 Without LVPE802

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ZHCSFG1B –JANUARY 2016–REVISED FEBRUARY 2017

7.8.3 Jitter and VOD Results: Case 3 at 1.5 Gbps

Eye

(1e-12)

(σ-σ)

(rms)

Amplitude

Width

Opening

(mV)

(1e-12)

(σ-σ)

(rms)

Amplitude

Width

Opening

(mV)

34.3

3.4

2.26

448

659

417.28

67.5

38.6

2.11

363.4

595

318.48

图 14. Test Point 1

图 15. Test Point 2

Eye

(1e-12)

44.9

(σ-σ)

13.2

(rms)

2.31

Amplitude

753.1

Width

649

Opening

(mV)

604.02

Eye

(1e-12)

(σ-σ)

(rms)

Amplitude

Width

Opening

(mV)

57.3

21.5

2.62

672.8

632

442.42

图 16. Test Point 3

图 17. Test Point 4 With LVPE802

Eye

(1e-12) ps

113.3

(σ-σ) ps

81.9

(rms) ps

2.3

Amplitude mV

322.8

Width ps

493

Opening (mV)

217.48

图 18. Test Point 4 Without LVPE802

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7.8.4 Jitter and VOD Results: Case 4 at 8 Gbps

图 21 Test Point 3 and 图 22 Test Point 4 were taken without pre-emphasis.

Eye

(1e-12)

(σ-σ)

(rms)

Amplitude

Width

Opening

(mV)

(1e-12)

(σ-σ)

(rms)

Amplitude

Width

Opening

(mV)

14.4

10.1

0.31

580

108

274

78.1

68.9

0.67

310

图 19. Test Point 1

图 20. Test Point 2

Eye

(1e-12)

(σ-σ)

(rms)

Amplitude

Width

Opening

(mV)

(1e-12)

(σ-σ)

(rms)

Amplitude

Width

Opening

(mV)

30.6

23.6

0.51

406

292

34.4

26.8

0.56

262

图 21. Test Point 3

图 22. Test Point 4

SN75LVPE802

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ZHCSFG1B –JANUARY 2016–REVISED FEBRUARY 2017

8 Detailed Description

8.1 Overview

The SN75LVPE802 is a dual channel equalizer and redriver. The device operates over a wide range of signaling

rates, supporting operation from DC to 8 Gbps. The wide operating range supports SATA Gen 1, 2, 3 (1.5 Gbps,

3.0 Gbps, and 6.0 Gbps respectively) as well as PCI Express 1.0, 2.0, 3.0 (2.5 Gbps, 5.0 Gbps, and 8.0 Gbps).

The device also supports SATA Express (SATA 3.2) which is a form factor specification that allows for SATA and

PCI Express signaling over a single connector.

8.2 Functional Block Diagram

GND[3,13,18]

= 1.7 V TYP

wÇ

RX1P [1]

RX1N [2]

TX1P [15]

TX1N [14]

wÇ

V_BB

wÇ

RX2N [12]

RX2P [11]

TX2N [4]

TX2P [5]

DEW1 [16]

DEW2 [6]

CTRL

EQ1[17]

EQ2[19]

DE1[9]

DE2[8]

VCC[10,20]

EN[7]

8.3 Feature Description

8.3.1 SATA Express

SATA Express (sometimes SATAe) is an electro-mechanical standard that supports both SATA and PCI Express

storage devices. SATAe is standardized in the SATA 3.2 standard. The standard is concerned with providing a

smooth transition from SATA to PCIe storage devices. The standard provides for standardized cables and

connectors, and muxes the PCIe and SATA lanes at the host side so that either SATA compliant or PCIe

compliant devices may operate with a host.

SATAe provides support for SATA1, SATA2 and SATA3 devices (operating from 1.5 Gbps to 6.0 Gbps), as well

as PCIe1, PCIe2 and PCIe3 devices (operating from 2.5 Gbps to 8.0 Gbps).

SN75LVPE802

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Feature Description (接下页)

The SN75LVPE802 provides for equalization and re-drive of a single channel input signal complying with any of

the SATA or PCIe standards available with SATAe.

The SATAe standard provides for a mechanism for a host to recognize and detect whether a SATA or PCIe

device is plugged into the host. See the Typical SATA Application section for the details of the SATA Express

Interface Detect operation.

8.3.2 Receiver Termination

The receiver has integrated terminations to an internal bias voltage. The receiver differential input impedance is

nominally 100 Ω, with a ±15% variation.

8.3.3 Receiver Internal Bias

The SN75LVPE802 receiver is internally biased to 1.7 V, providing support for AC coupled inputs.

8.3.4 Input Equalization

The SN75LVPE802 incorporates programmable equalization. The EQ input controls the level of equalization that

is used to open the eye of the received input signal. If the EQ input is left open, or pulled LO, 6 dB (at 3 GHz) of

equalization is applied. When the EQ input is HIGH, the equalization is set to 13 dB (again at 3 GHz). 表 1 shows

the equalization values discussed.

表 1. EQ and DE Settings

CH1 OR CH2 EQUALIZATION

CH1 OR CH2 DE-EMPHASIS

EQ1 OR EQ2

DE1 OR DE2

(at 6 Gbps)

(at 8 Gbps)

(at 6 Gbps)

NC (default)

-4

-2

8.3.5 OOB/Squelch

The SN75LVPE802 receiver incorporates an Out-Of-Band (OOB) detection circuit in addition to the main signal

chain receiver. The OOB detector continuously monitors the differential input signal to the device. The OOB

detector has a 50-mVpp entry threshold. If the differential signal at the receiver input is less than the OOB entry

threshold, the device transmitter transitions to squelch. The SN75LVPE802 enters squelch within 5 ns of the

input signal falling below the OOB entry threshold. The SN75LVPE802 continues to monitor the input signal while

in squelch. While in squelch, if the OOB detector determines that the input signal now exceeds the 90 mVpp exit

threshold, the SN75LVPE802 exits squelch within 5 ns.

IN+

50 mV

Vcm

IN-

OOB1

OOB2

OUT+

Vcm

OUT-

图 23. OOB Enter and Exit Timing Receiver Input Termination Is Disabled

When the SN75LVPE802 enters squelch state the transmitter output is squelched. The transmitter non-inverting

(TX+) output and the transmitter inverting output (TX-) are both driven to the transmitter nominal common mode

voltage which is 1.7 V.

SN75LVPE802

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8.3.6 Auto Low Power

The SN75LVPE801 also includes an Auto Low Power Mode (ALP). ALP is entered when the differential input

signal has been less than 50 mV for > 10 µs. The device enters and exits Low Power Mode by actively

monitoring the input signal level. In this state the device selectively shuts off internal circuitry to lower power by >

90% of its normal operating power. While in ALP mode the device continues to actively monitor input signal

levels. When the input signal exceeds the OOB exit threshold level, the device reverts to the active state. Exit

time from Auto Low Power Mode is < 50 ns (max).

RX1,2P

VCM

RX1,2N

TX1,2P

TX1,2N

OOB1

AutoLP

EXIT

VCM

Power Saving

Mode

AutoLP

ENTRY

图 24. Auto Low Power Mode Entry and Exit Timing

8.3.7 Transmitter Output Signal

The SN75LVPE802 differential output signal is 650 mVpp when de-emphasis is disabled (DE input is open or

pulled low).

8.3.8 Transmitter Common Mode

The SN75LVPE802 transmitter common mode output is set to 1.7 V.

8.3.9 De-Emphasis

The SN75LVPE802 device provides the de-emphasis settings shown in 表 2. De-emphasis control is

independent for each channel, controlled by the DE1 and DE2 pin settings as shown in 表 2. The reference for

the de-emphasis settings available in the device is the transition bit amplitude for each given configuration; this

transition bit amplitude is different at 0 dB than the –2-dB and –4-dB settings by design. DEW1 and DEW2

control the DE durations for channels one and two, respectively. 表 2 lists the recommended settings for these

control pins. Output de-emphasis is capable of supporting FR4 trace at the output anywhere from 2 in. (5.1 cm)

to 12 in. (30.5 cm) at SATA 3G/6G speed.

表 2. TX and Rx EQ and DE Pulse-Duration Settings

DEW1 OR DEW2

DEVICE FUNCTION → DE WIDTH FOR CH1/CH2

De-emphasis pulse duration, short

1 (default)

De-emphasis pulse duration, long

8.3.10 Transmitter Termination

The SN75LVPE802 transmitter includes integrated terminations. The receiver differential output impedance is

nominally 100 Ω, with a ≤ 22% variation.

SN75LVPE802

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8.4 Device Functional Modes

8.4.1 Low-Power Mode

There are two low-power modes supported by the SN75LVPE802 device, listed as follows:

1. Standby mode (triggered by the EN pin, EN = 0 V)

–

The enable (EN) pin controls th low-power mode. Pulling this pin LOW puts the device in standby mode

within 2 µs (max). In this mode, the device drives all its active components to their quiescent level, and

differential outputs Hi-Z (open). Maximum power dissipation in this mode is 5 mW. Exiting from this mode

to normal operation requires a maximum latency of 5 µs.

2. Auto low-power mode (triggered when a given channel is in the electrically idle state for more than 100 µs

and EN = VCC)

–

The device enters and exits low-power mode by actively monitoring the input signal (V_IDp-p) level on each

of its channels independently. When the input signal on either or both channels is in the electrically idle

state, that is, V_IDp-p< 50 mV and stays in this state for > 100 µs, the associated channel enters into the

low-power state. In this state, output of the associated channel goes to VCM and the device selectively

shuts off some circuitry to lower power by > 80% of its normal operating power. Exit time from the auto

low-power mode is < 50 ns.

SN75LVPE802

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9 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The SN75LVPE802 can be used for SATA applications as well as SATA Express applications. The device

supports SATA Gen1, Gen2, and Gen3 applications with data rates from 1.5 to 6 Gbps. The built-in equalization

circuits provide up to 13 dB of equalization at 3 GHz. This equalization can support SATA GEN2 (3 Gbps)

applications over up to 50 inches of FR-4 material. The same 13 dB equalizer is suited to SATA Gen3 (6 Gbps)

applications up to 40 inches of FR4.

In addition to SATA applications, the SN75LVPE802 can support SATA Express applications. SATA Express

provides a standardized interface to support both SATA (Gen1, Gen2, and Gen3) and PCI Express (PCIe 1, 2

and 3).

All applications of the SN75LVPE802 share some common applications issues. For example, power supply

filtering, board layout, and equalization performance with varying interconnect losses. Other applications issues

are specific, such as implementing receiver detection for SATA Express applications. The Typical Application

examples demonstrate common implementations of the SN75LVPE802 supporting SATA, as well as SATA

Express applications.

9.2 Typical SATA Application

This typical application describes how to configure the EQ, DE, and DEW configuration pins of the

SN75LVPE802 device based on board trace length between the SATA Host and the SN75LVPE802 and the

SN75LVPE802 and SATA Device. Actual configuration settings may differ due to additional factors such as

board layout, trace widths, and connectors used in the signal path.

SN75LVPE802

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Typical SATA Application (接下页)

3.3 V

10 nF

1 5

1 4

1 3

1 2

1 1

RX1P

TX1P

TX1N

RX1N

10 nF

LVPE802

RX2N

RX2P

TX2N

TX2P

10 nF

(1) Place supply caps close to device pin

(2) EN can be left open or tied to supply when no external control is implemented

(3) Output de-emphasis selection is set at -3 dB, EQ at 7 dB and DE width for SATA I/II/III operation for both channels.

(4) Actual EQ/DE/DE width settings will depend on device placement relative to host and SATA connector.

图 25. Typical Device Implementation

9.2.1 Design Requirements

Typically, system trace length from the SATA host to the SN75LVPE802 device and trace length from the

SN75LVPE802 device to a SATA device differ and require different equalization and de-emphasis settings for the

host side and device side.

For example:

•

A system with a 6-inch trace from the SN75LVPE802 device to a SATA host may set EQ1 (Rx1±) to 7 dB,

and DE2 (Tx2±) to –2 dB and DEW2 (Tx2±) to long pulse duration.

•

The same system with a 1-inch trace from the SN75LVPE802 device to a SATA HDD may set EQ2 (Rx2±) to

0 dB, and DE1 (Tx1±) to 0 dB and DEW1 (Tx1±) to short pulse duration.

Refer to

Application Curves for recommended EQ, DE and DEW settings based on trace length. It is highly

recommended to add both pullup- and pulldown-resistor options in the layout to fine-tune the settings if needed.

Input Signal Characteristics:

•

Data Rate: 6 Gbps

Pattern: PRBS7

No pre-emphasis

Signal amplitude: 500 mVpp

18-inch SMA cable from test equipment to input and output trace

SN75LVPE802

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Typical SATA Application (接下页)

Lecroy PERT3

SN75LVPE802

25-GHz Scope

TP1

TP2

TP3

TP4

图 26. Measurement Set-up

9.2.2 Detailed Design Procedure

9.2.2.1 Equalization Configuration

Each differential input of the SN75LVPE802 device has programmable equalization in the front stage. The

equalization setting is shown in 表 1. The input equalizer is designed to recover a signal even when no eye is

present at the receiver and effectively supports FR4 trace input from 3 inches to greater than 24 inches at SATA

6 Gbps speed.

9.2.3 De-emphasis Configuration

The SN75LVPE802 device provides the de-emphasis settings shown in 表 1 and 表 2. TX and Rx EQ and DE

Pulse-Duration Settings. De-emphasis is controlled independently for each channel and is set by the DE1, DE2,

DEW1 and DEW2 pins of the SN75LVPE802 device.

SN75LVPE802

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Typical SATA Application (接下页)

9.2.4 Application Curves

Typical application curves correspond to SATA application at 6 Gbps.

9.2.4.1 SN75LVPE802 Equalization Settings for Various Input Trace Length

Input Trace Length = 3 in.

EQ1, EQ2 Setting = NC (0 dB)

图 28. Output Eye (TP4)

图 27. Input Eye (TP2)

Input Trace Length = 6 in.

EQ1, EQ2 Setting = 0 (7 dB)

图 29. Input Eye (TP2)

图 30. Output Eye (TP4)

Input Trace Length = 12 in.

EQ1, EQ2 Setting = 0 (7 dB)

Input Trace Length = 12 in.

EQ1, EQ2 Setting = 0 (7 dB)

图 31. Input Eye (TP2)

图 32. Output Eye (TP4)

SN75LVPE802

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Typical SATA Application (接下页)

Input Trace Length = 24 in.

EQ1, EQ2 Setting = 0 (7 dB)

Input Trace Length = 24 in.

EQ1, EQ2 Setting = 0 (7 dB)

图 33. Input Eye (TP2)

图 34. Output Eye (TP4)

Input Trace Length = 36 in.

EQ1, EQ2 Setting = 1 (14 dB)

图 35. Input Eye (TP2)

图 36. Output Eye (TP4)

Input Trace Length = 48 in.

EQ1, EQ2 Setting = 1 (14 dB)

图 37. Input Eye (TP2)

图 38. Output Eye (TP4)

SN75LVPE802

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Typical SATA Application (接下页)

9.2.4.2 SN75LVCP802 De-emphasis Settings For various Output Trace Lengths

Output Trace Length = 0 in.

DE, DE2 Setting = 0 (0 dB)

Output Trace Length = 3 in.

DE, DE2 Setting = 0 (0 dB)

DEW1, DEW2 Setting = 0 (Short pulse duration)

图 39. Output Eye (TP4)

图 40. Output Eye (TP4)

Output Trace Length = 6 in.

DE, DE2 Setting = 1 (-2 dB)

Output Trace Length = 12 in.

DE, DE2 Setting = 1 (-2 dB)

DEW1, DEW2 Setting = 1 (Long pulse duration)

图 41. Output Eye (TP4)

图 42. Output Eye (TP4)

Output Trace Length = 12 in.

DE, DE2 Setting = NC (-4 dB)

DEW1, DEW2 Setting = 1 (Long pulse duration)

图 43. Output Eye (TP4)

SN75LVPE802

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ZHCSFG1B –JANUARY 2016–REVISED FEBRUARY 2017

9.3 SATA Express Applications

Connector

330

Host

VCC

Controller

220nF

RX1P

RX1N

GND

TX2N

VCC

EQ2

GND

220nF

EQ1

DEW1

TX1P

TX1N

GND

Device

TX2P

220nF

DEW2

DE2

DE1

VCC

470nF

220nF

VCC

RX2N

RX2P

SN75LVPE802

330

图 44. SATAe Reference Schematic

9.3.1 Detailed Design Procedure

图 44 is a reference schematic of a SATAe implementation using the SN75LVPE802. With a SATAe design, both

SATA and PCI Express must be supported. SATAe supports both cabled and direct connections. Using a cabled

application as an example, the SATAe power connector includes an Interface Detect (IFDet, power connector pin

P4) signal that indicates whether a SATA client or a PCIe client is connected.

When the SATAe host determines that a PCIe client is connected, the SATAe host performs receiver detection.

Receiver detection determines the presence of a client by detecting the load impedance. The transmitter

performs a common mode voltage shift, and measures the rate at which the voltage at the transmitter output

changes. The rate of change indicates if a client is present (fast charging when a low impedance load is present,

or slow charging when the load is open or high impedance). With the implementation in 图 44, 330-Ω pulldowns

have been inserted between the host and the SN75LVPE802. The pulldown resistors indicate to the host that a

client is present. While an actual client would be expected to have an active load of 50 Ω single ended, the 330

Ω is chosen here to meet two requirements. The 330 Ω is low enough to force the SATAe host to decide that a

receiver is present, while also high enough to only marginally affect the load when the SN75LVPE802 is active,

and presenting a 50-Ω load. With the 50 Ω and 330 Ω are both present, the parallel combination of 43 Ω is

satisfactory for most applications.

Assuming that the SATAe host has detected (via IFDet) that a SATA client is present, the SATAe host

communicates with the client via the SN75LVPE802. The SATA standard does not have a receiver detection

mode as is present in PCIe. A SATA host does use OOB signaling to communicate identification information. The

SN75LVPE802 incorporates an OOB detector in order to support OOB signaling through the device. The OOB

detector drives a squelch circuit on the SN75LVPE802 output transmitter. (See OOB/Squelch for more details on

the OOB/Squelch circuitry.)

SN75LVPE802

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www.ti.com.cn

SATA Express Applications (接下页)

Returning to 图 44, there is a 200-nF AC coupling capacitors on the device or client side of the interface. These

capacitors allow interfacing to both SATA and PCIe clients. In the case of a PCIe client, the 200 nF is within the

acceptable range for all PCIe devices. When a SATA client is present, the 200 nF capacitor has little effect on

the overall link, as it appears in series with the 12-nF (max) AC coupling capacitor incorporated into the SATA

client. The 200 nF in series with the 12 nF presents an effective capacitance of 11.3 nF, as expected less than

the 12-nF maximum permitted.

9.3.2 PCIe Applications

PCIe-only applications are implemented in a manner very similar to SATA Express applications as covered in

Detailed Design Procedure. Looking at 图 45 and comparing it to the SATA Express application in Figure 8 20

SATAe Reference Schematic, a single change is noted. For PCIe applications the 220 nF AC-coupling

capacitors on the Host-to-Device link are relocated from the Device side of the connector to the Host side. No

other changes are required.

Connector

330

Host

VCC

Controller

RX1P

220nF

VCC

EQ2

GND

RX1N

GND

220nF

TX2N

TX2P

DEW2

EQ1

DEW1

TX1P

Device

220nF

TX1N

GND

DE2

470nF

220nF

VCC

DE1

RX2N

RX2P

VCC

SN75LVPE802

330

图 45. SN75LVPE802 PCIe Reference Schematic

10 Power Supply Recommendations

The design of SN75LVPE802 device is for operation from one 3.3-V supply. Always practice proper power supply

sequencing procedure. Apply VCC first, before application of any input signals to the device. The power down

sequence is in reverse order.

SN75LVPE802

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11 Layout

11.1 Layout Guidelines

24"

SATA

connector

Redriver

SATA Host

16"

Redriver on Motherboard

24"

SATA Host

Redriver

Main Board

Dock Board

SATA

connector

16"

Redriver on Dock Board

(1) Trace lengths are suggested values based on TI spice simulations (done over programmable limits of input EQ and

output de-emphasis) to meet SATA loss and jitter spec.

Actual trace length supported by the LVPE802 may be more or less than suggested values and will depend on board

layout, trace widths and number of connectors used in the SATA signal path.

图 46. Trace Length Example for LVPE802

SN75LVPE802

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www.ti.com.cn

11.2 Layout Example

图 47. Example Layout

SN75LVPE802

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ZHCSFG1B –JANUARY 2016–REVISED FEBRUARY 2017

12 器件和文档支持

12.1 接收文档更新通知

如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册

后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。

12.2 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.3 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

SN75LVPE802RTJR

SN75LVPE802RTJT

ACTIVE

QFN

RTJ

3000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

0 to 85

LVP802

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

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Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Apr-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

SN75LVPE802RTJR

SN75LVPE802RTJT

QFN

RTJ

3000

250

330.0

180.0

12.4

4.25

1.15

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Apr-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

SN75LVPE802RTJR

SN75LVPE802RTJT

QFN

RTJ

3000

250

346.0

210.0

346.0

185.0

33.0

35.0

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RTJ 20

4 x 4, 0.5 mm pitch

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224842/A

www.ti.com

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

SN75LVPE802RTJR [TI]

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