SN761645DBTR [TI]
DIGITAL TV TUNER IC; 数字电视调谐器IC
| 型号： | SN761645DBTR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DIGITAL TV TUNER IC |
| 文件： | 总29页 (文件大小：1057K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN761645
www.ti.com
SLES262 –SEPTEMBER 2010
DIGITAL TV TUNER IC
Check for Samples: SN761645
1
FEATURES
DBT PACKAGE
(TOP VIEW)
•
•
•
•
•
•
Integrated Mixer/Oscillator/PLL and IF GCA
VHF-L, VHF-H, UHF 3-Band Local Oscillator
RF AGC Detector Circuit
VLO OSC
VHI OSC
UHF OSC1
UHF OSC2
OSC GND
CP
1
38
37
36
35
34
33
32
31
BS4
2
3
4
UHF RFIN1
UHF RFIN2
VHI RFIN
VLO RFIN
RF GND
MIXOUT2
MIXOUT1
IFIN
I2C Bus Protocol
Seven-Step Charge Pump Current
5
Four NPN Emitter-Follower Type Band Switch
Drivers
6
VTU
7
•
•
•
•
•
•
•
One Auxiliary Port/5-Level ADC
Programmable Reference Divider Ratio
Crystal Oscillator 4-MHz/16-MHz Support
Selectable Digital IFOUT and Analog IFOUT
Standby Mode
IF GND
8
AIF OUT
9
30
29
28
27
26
25
24
23
22
21
20
DIF OUT1
DIF OUT2
P5/ADC
10
11
12
13
14
15
16
17
18
19
BUS GND
RF AGC OUT
BS3
VCC
BS2
5-V Power Supply
IF GCA IN1
IF GCA IN2
IF GCA CTRL
IF GCA GND
IF GCA OUT2
IF GCA OUT1
BS1
38-Pin TSSOP Package
SDA
SCL
APPLICATIONS
AS
•
•
•
Digital TV
Digital CATV
Set-Top Box
XTAL2
XTAL1
DESCRIPTION
The SN761645 is a low-phase-noise synthesized tuner IC designed for digital TV tuning systems. The circuit
consists of a PLL synthesizer, three-band local oscillator and mixer, RF AGC detector circuit, and IF gain
controlled amplifier, and is available in a small outline package.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN761645
SLES262 –SEPTEMBER 2010
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
IF AMP
DIFOUT1
VHF-L
OSC
VHF-H
OSC
UHF
OSC
DIFOUT 2
AIFOUT
IF GND
VHF-H
MIXER
UHF
MIXER
VHF-L
MIXER
VLO RF IN
VHI RF IN
RF AGC OUT
RF AGC
DETECT
UHF RF IN 1
UHF RF IN 2
RF GND
PROGRAMMABLE
DIVIDER
CP
VTU
XTAL
OSC
1/1,1/4
DIV
REFERENCE
DIVIDER
PHASE
DETECTOR
CHARGE
PUMP
OP
AMP
XTAL 1
XTAL 2
VCC
NPN SWITCH
PORT
I2C BUS
INTERFACE
IF GCA OUT1
IF GCA OUT2
IF GCA GND
SCL
SDA
AS
IF
GCA
5-LEVEL
ADC
BUS GND
2
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SLES262 –SEPTEMBER 2010
TERMINAL FUNCTIONS
TERMINAL
NAME
DESCRIPTION
SCHEMATIC
NO.
9
AIF OUT
AS
IF amplifier output (unbalanced)
Figure 1
Figure 2
Figure 3
Figure 3
Figure 3
Figure 3
22
25
26
27
38
29
6
Address selection input (open or connection to GND)
Band-switch 1 output (emitter follower)
Band-switch 2 output (emitter follower)
Band-switch 3 output (emitter follower)
Band-switch 4 output (emitter follower)
BUS ground
BS1
BS2
BS3
BS4
BUS GND
CP
Charge pump output
IF amplifier balance output 1
IF amplifier balance output 2
IF GCA control voltage input
IF GCA ground
Figure 4
Figure 5
Figure 5
Figure 6
DIF OUT1
DIF OUT2
10
11
16
17
14
15
19
18
8
IF GCA CTRL
IF GCA GND
IF GCA IN1
IF GCA IN2
IF GCA OUT1
IF GCA OUT2
IF GND
IF GCA input 1
Figure 7
Figure 7
Figure 8
Figure 8
IF GCA input 2
IF GCA output 1
IF GCA output 2
IF ground
IF IN
30
31
32
5
IF amplifier input
Figure 9
Figure 10
Figure 10
MIX OUT1
MIX OUT2
OSC GND
P5/ADC
Mixer output 1
Mixer output 2
Oscillator ground
12
28
33
23
24
3
Port-5 output/ADC input
RF AGC output
Figure 11
Figure 12
RF AGC OUT
RF GND
RF ground
SCL
Serial clock input
Figure 13
Figure 14
Figure 15
Figure 15
Figure 16
Figure 16
SDA
Serial data input/output
UHF oscillator 1
UHF OSC1
UHF OSC2
UHF RF IN1
UHF RF IN2
VCC
4
UHF oscillator 2
37
36
13
2
UHF RF input 1
UHF RF input 2
Supply voltage
VHI OSC
VHI RF IN
VLO OSC
VLO RF IN
VTU
VHF HIGH oscillator
VHF HIGH RF input
VHF LOW oscillator
VHF LOW RF input
Tuning voltage amplifier output
Crystal oscillator
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 22
35
1
34
7
XTAL1
20
21
XTAL2
Crystal oscillator
10 W
22
9
Figure 1. AIF OUT
Figure 2. AS
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SLES262 –SEPTEMBER 2010
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25 W
25 W
25
26
27
38
10 W
6
50 kW
Figure 3. BS1, BS2, BS3, BS4
Figure 4. CP
500 W
16
10 W
100 kW
10
11
Figure 5. DIF OUT1, DIF OUT2
Figure 6. IF GCA CTRL
Vbias
1 kW
1 kW
14
15
15 W
18
19
Figure 7. IF GCA IN1, IF GCA IN2
Figure 8. IF GCA OUT1, IF GCA OUT2
25 W
32
2 kW
25 W 1 kW
31
A
25 W
A
25 W 1 kW
30
1 kW
Figure 9. IF IN
Figure 10. MIXOUT1, MIXOUT2
25 W 50 W
25 W
12
28
Figure 11. P5/ADC
Figure 12. RF AGC OUT
4
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SLES262 –SEPTEMBER 2010
25 W
1 kW
1 kW
24
23
Figure 13. SCL
Figure 14. SDA
Vref1
Vref2
36
37
3 kW
3
4
Figure 15. UHF OSC 1, UHF OSC 2
Figure 16. UHF RF IN1, UHF RF IN2
Vref2
Vref1
35
3 kW
2
Figure 17. VHI OSC
Figure 18. VHI RF IN
Vref2
Vref1
34
3 kW
1
Figure 19. VLO OSC
Figure 20. VLO RF IN
7
21
20
20 W
10 W
50 kW
Figure 21. VTU
Figure 22. XTAL1, XTAL2
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SLES262 –SEPTEMBER 2010
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MAX UNIT
ABSOLUTE MAXIMUM RATINGS(1)
over recommended operating free-air temperature range (unless otherwise noted)
MIN
–0.4
–0.4
–0.4
–0.4
(2)
VCC
Supply voltage range
VCC
6.5
0.4
35
V
V
V
V
(2)
(2)
(2)
VGND Input voltage range 1
RF GND, OSC GND, BUS GND
VTU
VIN
PD
Input voltage range 2
Input voltage range 3
VTU
Other pins
6.5
(3)
Continuous total dissipation
TA ≤ 25°C
1277 mW
TA
Operating free-air temperature range
Storage temperature range
–20
–65
85
150
150
°C
°C
°C
Tstg
TJ
Maximum junction temperature
tSC(max
)
Maximum short-circuit time
Each pin to VCC or to GND
10
s
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Voltage values are with respect to the IF GND of the circuit.
(3) Derating factor is 10.2 mW/°C for TA > 25°C.
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX UNIT
VCC
VTU
IBS
Supply voltage
VCC
4.5
5
5.3
33
10
–5
85
V
V
Tuning supply voltage
Output current of band switch
Output current of port 5
Operating free-air temperature
VTU
30
BS1 to BS4, one band switch on
P5
mA
mA
°C
IP5
TA
–20
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
IF IN1, MIX OUT 1, and MIX OUT 2 (pins 30, 31, and 32, respectively) withstand 1.5 kV, and all other pins
withstand 2 kV, according to the Human-Body Model (1.5 kΩ, 100 pF).
6
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SLES262 –SEPTEMBER 2010
ELECTRICAL CHARACTERISTICS
Total Device and Serial Interface
VCC = 4.5 V to 5.3 V, TA = –20°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
90
MAX UNIT
ICC
1
2
Supply current 1
BS[1:4] = 0100, IFGCA disabled
BS[1:4] = 0100, IFGCA enabled
BS[1:4] = 1100
mA
mA
mA
V
ICC
Supply current 2
110
9
ICC-STBY
VIH
Standby supply current
High-level input voltage (SCL, SDA)
Low-level input voltage (SCL, SDA)
High-level input current (SCL, SDA)
Low-level input current (SCL, SDA)
2.3
VIL
1.05
10
V
IIH
µA
µA
IIL
–10
2.1
Power-on-reset supply voltage (threshold of supply
voltage between reset and operation mode)
VPOR
2.8
3.5
V
I2C Interface
VADC
IADH
ADC input voltage
See Table 11
VADC = VCC
0
VCC
10
V
ADC high-level input current
ADC low-level input current
Low-level output voltage (SDA)
High-level output leakage current (SDA)
Clock frequency (SCL)
Data hold time
µA
µA
V
IADL
VADC = 0 V
–10
VOL
VCC = 5 V, IOL = 3 mA
VSDA = 5.3 V
0.4
10
lSDAH
fSCL
tHD-DAT
tBUF
tHD-STA
tLOW
µA
100
400 kHz
See Figure 23
0
1.3
0.6
1.3
0.6
0.6
0.1
3.45
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
Bus free time
Start hold time
SCL-low hold time
tHIGH
tSU-STA
tSU-DAT
tr
SCL-high hold time
Start setup time
Data setup time
Rise time (SCL, SDA )
Fall time (SCL, SDA)
Stop setup time
1
tf
0.3
tSU-STO
0.6
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PLL and Band Switch
VCC = 4.5 V to 5.3 V, TA = –20°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
32767
N
Divider ratio
15-bit frequency word
512
fXTAL
ZXTAL
VVTUL
IVTUOFF
ICP000
ICP001
ICP010
ICP011
ICP100
ICP101
ICP110
VCP
Crystal oscillator frequency
Crystal oscillator input impedance
Tuning amplifier low-level output voltage
Tuning amplifier leakage current
RXTAL = 25 Ω to 300 Ω
4-MHz crystal, VCC = 5 V, TA = 25°C
RL = 20 kΩ, VTU = 33 V
Tuning amplifier = off, VTU = 33 V
CP[2:0] = 000
4
2
16 MHz
kΩ
0.2
0.45
0.6
10
V
µA
35
70
CP[2:0] = 001
CP[2:0] = 010
140
210
280
350
420
1.95
Charge-pump current
CP[2:0] = 011
µA
CP[2:0] = 100
CP[2:0] = 101
CP[2:0] = 110
Charge-pump output voltage
PLL locked
V
ICPOFF
IBS
Charge-pump leakage current
VCP = 2 V, TA = 25°C
–15
15
10
nA
mA
Band switch driver output current (BS1–BS4)
VBS1
IBS = 10 mA
2.9
3.4
Band switch driver output voltage (BS1–BS4)
V
VBS2
IBS = 10 mA, VCC = 5 V, TA = 25°C
VBS = 0 V
3.6
IBSOFF
IP5
Band switch driver leakage current (BS1–BS4)
Band switch port sink current (P5/ADC)
Band switch port output voltage (P5/ADC)
8
µA
mA
V
–5
VP5ON
IP5 = –2 mA, VCC = 5 V, TA = 25°C
0.6
RF AGC(1)
VCC = 5 V, TA = 25°C, measured in Figure 24 reference measurement circuit at 50-Ω system, IF = 36.15 MHz (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
300
9
MAX UNIT
IOAGC0
IOAGC1
ATC = 0
ATC = 1
ATC = 0
ATC = 1
ATC = 1
nA
µA
µA
RF AGC output source current
IOAGCSINK RF AGC peak sink current
100
4.2
VOAGCH
RFAGCOUT output high voltage (max level)
3.7
4.7
V
V
VOAGCL
RFAGCOUT output low voltage (min level)
0.3
VAGCSP00
VAGCSP01
VAGCSP02
VAGCSP03
VAGCSP04
VAGCSP05
VAGCSP06
ATP[2:0] = 000
ATP[2:0] = 001
ATP[2:0] = 010
ATP[2:0] = 011
ATP[2:0] = 100
ATP[2:0] = 101
ATP[2:0] = 110
114
112
110
108
106
104
102
Start-point IF output level
AISL = 0
dBµV
(1) When AISL = 1, RF AGC function is not available at VHF-L band.
8
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Mixer, Oscillator, IF Amplifier (DIF OUT)
VCC = 5 V, TA = 25°C, measured in Figure 24 reference measurement circuit at 50-Ω system, IF = 36.15 MHz (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
fIN = 50.85 MHz(1)
fIN = 149.85 MHz(1)
fIN = 156.85 MHz(1)
fIN = 425.85 MHz(1)
fIN = 433.85 MHz(1)
fIN = 857.85 MHz(1)
fIN = 50.85 MHz
MIN
TYP
35
MAX
UNIT
dB
GC1D
Conversion gain (mixer - IF amplifier), VHF-LOW
GC3D
35
dB
GC4D
35
dB
Conversion gain (mixer - IF amplifier), VHF-HIGH
Conversion gain (mixer - IF amplifier), UHF
Noise figure, VHF-LOW
GC6D
35
dB
GC7D
35
dB
GC9D
35
dB
NF1D
9
dB
NF3D
fIN = 149.85 MHz
fIN = 156.85 MHz
fIN = 425.85 MHz
fIN = 433.85 MHz
fIN = 857.85 MHz
fIN = 50.85 MHz(2)
fIN = 149.85 MHz(2)
fIN = 156.85 MHz(2)
fIN = 425.85 MHz(2)
fIN = 433.85 MHz(2)
fIN = 857.85 MHz(2)
fIN = 50.85 MHz
9
dB
NF4D
9
dB
Noise figure, VHF-HIGH
NF6D
10
dB
NF7D
10
dB
Noise figure, UHF
NF9D
11
dB
CM1D
CM3D
CM4D
CM6D
CM7D
CM9D
VIFO1D
VIFO3D
VIFO4D
VIFO6D
VIFO7D
VIFO9D
ΦPLVL1D
ΦPLVL3D
ΦPLVL4D
ΦPLVL6D
ΦPLVL7D
ΦPLVL9D
92
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Input voltage causing 1% cross modulation distortion,
VHF-LOW
92
92
Input voltage causing 1% cross modulation distortion,
VHF-HIGH
92
92
Input voltage causing 1% cross modulation distortion, UHF
IF output voltage, VHF-LOW
IF output voltage, VHF-HIGH
IF output voltage, UHF
92
117
117
117
117
117
117
-92
-91
-86
-83
-79
-77
fIN = 149.85 MHz
fIN = 156.85 MHz
fIN = 425.85 MHz
fIN = 433.85 MHz
fIN = 857.85 MHz
fIN = 50.85 MHz(3)
fIN = 149.85 MHz(4)
fIN = 156.85 MHz(3)
fIN = 425.85 MHz(4)
fIN = 433.85 MHz(3)
fIN = 857.85 MHz(4)
Phase noise, VHF-LOW
Phase noise, VHF-HIGH
Phase noise, UHF
(1) RF input level = 70 dBµV, differential output
(2) fundes = fdes ± 7 MHz, Pin = 70 dBµV, AM 1 kHz, 30%, DES/CM = S/I = 46 dB
(3) Offset = 1 kHz, CP current = 70 µA, reference divider = 24
(4) Offset = 1 kHz, CP current = 420 µA, reference divider = 24
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Mixer, Oscillator, IF Amplifier (AIF OUT)
VCC = 5 V, TA = 25°C, measured in Figure 24 reference measurement circuit at 50-Ω system, IF = 36.15 MHz (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
29
MAX
UNIT
dB
(1)
GC1A
f IN = 50.85 MHz
Conversion gain (mixer - IF amplifier), VHF-LOW
(1)
(1)
(1)
(1)
(1)
GC3A
f IN = 149.85 MHz
f IN = 156.85 MHz
f IN = 425.85 MHz
f IN = 433.85 MHz
f IN = 857.85 MHz
f IN = 50.85 MHz
f IN = 149.85 MHz
f IN = 156.85 MHz
f IN = 425.85 MHz
f IN = 433.85 MHz
f IN = 857.85 MHz
29
dB
GC4A
29
dB
Conversion gain (mixer - IF amplifier), VHF-HIGH
Conversion gain (mixer - IF amplifier), UHF
Noise figure, VHF-LOW
GC6A
29
dB
GC7A
29
dB
GC9A
29
dB
NF1A
9
dB
NF3A
9
dB
NF4A
9
dB
Noise figure, VHF-HIGH
NF6A
10
dB
NF7A
10
dB
Noise figure, UHF
NF9A
11
dB
(2)
CM1A
CM3A
CM4A
CM6A
CM7A
CM9A
VIFO1A
VIFO3A
VIFO4A
VIFO6A
VIFO7A
VIFO9A
ΦPLVL1A
ΦPLVL3A
ΦPLVL4A
ΦPLVL6A
ΦPLVL7A
ΦPLVL9A
f IN = 50.85 MHz
f IN = 149.85 MHz
f IN = 156.85 MHz
f IN = 425.85 MHz
f IN = 433.85 MHz
f IN = 857.85 MHz
f IN = 50.85 MHz
f IN = 149.85 MHz
f IN = 156.85 MHz
f IN = 425.85 MHz
f IN = 433.85 MHz
f IN = 857.85 MHz
87
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Input voltage causing 1% cross modulation distortion,
VHF-LOW
(2)
(2)
(2)
(2)
(2)
87
87
Input voltage causing 1% cross modulation distortion,
VHF-HIGH
87
87
Input voltage causing 1% cross modulation distortion, UHF
IF output voltage, VHF-LOW
IF output voltage, VHF-HIGH
IF output voltage, UHF
87
117
117
117
117
117
117
-92
-96
-85
-88
-80
-85
(3)
f IN = 50.85 MHz
f IN = 149.85 MHz
f IN = 156.85 MHz
f IN = 425.85 MHz
f IN = 433.85 MHz
f IN = 857.85 MHz
Phase noise, VHF-LOW
(3)
(3)
(3)
(3)
(3)
Phase noise, VHF-HIGH
Phase noise, UHF
(1) RF input level = 70 dBµV
(2) fundes = fdes ± 7 MHz, Pin = 70 dBµV, AM 1 kHz, 30%, DES/CM = S/I = 46 dB
(3) Offset = 10 kHz, CP current = 35 µA, reference divider = 64
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IF Gain Controlled Amplifier
VCC = 5 V, TA = 25°C, measured in Figure 24 reference measurement circuit at 50-Ω system, IF = IF = 36.15 MHz (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIFGCA = 3 V
MIN
TYP
MAX UNIT
IIFGCA
Input current (IF GCA CTRL)
60
90
VCC
0.2
µA
V
VIFGCAMAX Maximum gain control voltage
VIFGCAMIN Minimum gain control voltage
GIFGCAMAX Maximum gain
Gain maximum
Gain minimum
VIFGCA = 3 V
3
0
V
67
3
dB
dB
dB
GIFGCAMIN Minimum gain
VIFGCA = 0 V
GCRIFGCA Gain control range
VIFGCA = 0 V to 3 V
64
Single-ended output,
VIFGCA = 3 V
VIFGCAOUT Output voltage
2.1
11
Vpp
dB
NFIFGCA
Noise figure
VIFGCA = 3 V
fIFGCAIN1 = 35.65 MHz,
fIFGCAIIN2 = 36.65 MHz,
VIFGCAOUT = –2 dBm,
VIFGCA = 3 V
IM3IFGCA
Third order intermodulation distortion
–50
dBc
IIP3IFGCA
RIFGCAIN
Input intercept point
VIFGCA = 0 V
11
1
dBm
kΩ
Ω
Input resistance (IF GCA IN1, IF GCA IN2)
RIFGCAOUT Output resistance (IF GCA OUT1, IF GCA OUT2)
25
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FUNCTIONAL DESCRIPTION
Table 1. Write Data Format
I2C Bus Mode
I2C Write Mode (R/W = 0)
MSB
1
LSB
R/W = 0
N8
Address Byte (ADB)
Divider Byte 1 (DB1)
Divider Byte 2 (DB2)
Control Byte 1 (CB1)
Band Switch Byte (BB)
Control Byte 2 (CB2)
1
N14
N6
0
0
0
N12
N4
0
N11
0
MA
N9
A(1)
A(1)
A(1)
A(1)
A(1)
A(1)
0
N13
N5
N10
N2
N7
1
N3
N1
N0
ATP2
AISL
ATC
ATP1
P5
ATP0
BS4
RS2
BS3
IFDA
RS1
BS2
CP2
RS0
CP1
1
CP0
1
BS1
MODE
DISGCA
IXD4
(1) A = acknowledge
Table 2. Write Data Symbol Description
SYMBOL
DESCRIPTION
DEFAULT
Address set bit
MA = 0 : AS pin = 0 V (connection to GND)
MA
MA = 1 : AS pin = Open
Programmable counter set bits
N[14:0]
N14 = N13 = N12 = ... = N0 = 0
N = N14 x 214+ N13 x 213 + ... + N1 x 2 + N0
ATP[2:0]
RS[2:0]
CP[2:0]
RF AGC start-point control bits (see Table 3)
Reference divider ratio-selection bits (see Table 4)
Charge-pump current set bits (see Table 5)
Port output / ADC input control bit
P5 = 0 : ADC input
ATP[2:0] = 000
RS[2:0] = 000
CP[2:0] = 000
P5
P5 = 0
P5 = 1 : Tr = ON
Band-switch driver output control bits
BSn = 0: Tr = OFF
BSn = 1: Tr = ON
Band selection and standby function control bits
BS[4:1]
BS2
0
BS1
1
BS[4:1] = 0000
VHF-LO
1
0
VHF-HI
0
0
UHF
1
1
Standby mode / stop MOP function
RFAGC output current-set bit
ATC = 0: Source current = 300nA
ATC = 1: Source current = 9uA
Device mode selection bit
ATC
ATC = 0
MODE
MODE = 0 : Test mode
MODE = 0
MODE = 1 : Normal operation
Other control bits
DISGCA
IFDA
DISGCA
IFDA
IF GCA control bit (see Table 6)
DISGCA = 0
IFDA = 0
AISL = 0
AIF/DIF OUT selection bit (see Table 7)
RFAGC detector input selection bit (see Table 8)
Reference divider control bit (see Table 4)
AISL
AISL
IXD4
IXD4
IXD4 = 0
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Table 3. RF AGC Start Point
IFOUT LEVEL
MODE
ATP2
ATP1
ATP0
(dBmV)
114
(mVp-p)
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1417
1126
894
710
564
448
356
112
110
108
106
104
102
Disabled
Table 4. Reference Divider Ratio
REFERENCE DIVIDER
RATIO
MODE
IXD4
RS2
RS1
RS0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
X
0
0
0
0
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
96
112
128
256
512
320
24
28
32
64
128
80
Forbidden
Table 5. Charge-Pump Current
CHARGE PUMP CURRENT
(µA)
MODE
CP2
CP1
CP0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
35
70
140
210
280
350
420
Forbidden
Table 6. IF GCA Control
MODE
DISGCA
IF GCA FUNCTION
IF GCA enabled
IF GCA disabled
1
1
0
1
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Table 7. AIF / DIF OUT Selection
MODE
IFDA
IF OUT FUNCTION
DIF OUT 1,2 selected
AIF OUT selected
1
1
0
1
Table 8. RF AGC Detector Input Selection
MODE
AISL
RF AGC DETECTOR INPUT
IF amplifier selected
Mixer selected
1
1
0
1(1)
(1) When AISL = 1, RF AGC function is not available at VHF-L band
(output level is undefined).
I2C Read Mode (R/W = 1)
Table 9. Read Data Format
MSB
LSB
R/W = 1
A0
Address byte (ADB)
Status byte (SB)
1
1
0
1
0
1
0
1
0
MA
A1
A(1)
–
POR
FL
A2
(1) A = acknowledge
Table 10. Read Data Symbol Description
SYMBOL
DESCRIPTION
DEFAULT
MA
Address set bit
MA = 0 : VLO OSC/AS pin = 0 V (connection to GND)
MA = 1 : VLO OSC/AS pin = Open
POR
FL
Power-on-reset flag
POR = 1
POR set: power on
POR reset: end-of-data transmission procedure
In-lock flag(1)
FL = 0 : PLL unlocked
FL = 1 : PLL locked
A[2:0]
Digital data of ADC (see Table 11)
Bit P5 must be set to 0.
(1) Lock detector works by using phase error pulse at the phase detector. Lock flag (FL) is set or reset according to this pulse-width
disciminator. Hence, instability of the PLL may cause the lock detection circuit to malfunction. To stablize the PLL, it is required to
evaluate application circuit in various condition of loop-gain (loop filter, CP current) and to verify under operation of the actual
application.
Table 11. ADC Level(1)
A2
1
A1
0
A0
0
VOLTAGE APPLIED ON ADC INPUT
0.6 VCC to VCC
0
1
1
0.45 VCC to 0.6 VCC
0.3 VCC to 0.45 VCC
0.15 VCC to 0.3 VCC
0 V to 0.15 VCC
0
1
0
0
0
1
0
0
0
(1) Accuracy is 0.03 × VCC
.
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Example I2C Data Write Sequences
Telegram examples:
Start - ADB - DB1 - DB2 - CB1 – BB - CB2 - Stop
Start - ADB - DB1 - DB2 - Stop
Start - ADB - CB1 - BB - CB2 - Stop
Start - ADB - CB1 - BB - Stop
Start - ADB - CB2 - Stop
Abbreviations:
ADB: Address byte
BB: Band switch byte
CB1: Control byte 1
CB2: Control byte 2
DB1: Divider byte 1
DB2: Divider byte 2
Start: Start condition
Stop: Stop condition
t HD-STA
t SU-STA
t F
t HIGH
SCL
t SU-STO
t SU-DAT
t LOW
t R
SDA
t HD-DAT
t BUF
Figure 23. I2C Timing
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APPLICATION INFORMATION
C17
L7
R11
VC1
C15 R9
R13
VC2 C18 R12
BS4
1
2
38
BS4
VLO OSC
VHI OSC
C20
C1
C4
C2
C3
UHF RF IN1 37
UHF RF IN2 36
VHI RF IN 35
VLO RF IN 34
RF GND 33
UHF RF IN1
L8
C21 R14
R1
3
UHF OSC 1
UHF OSC 2
L9
R16
C25
VC3
C23
C22 R15
4
VHI RF IN
VLO RF IN
R17
R2
R3
5
OSC GND
C27
R18
C26
6
CP
R19
L1
R20
C29
L2
L4
VTU
7
VTU
MIX OUT2 32
C6
R5
C28
R4
C5
8
IF GND
MIX OUT1 31
IF IN 30
L3
C30
C7
AIF OUT
9
AIF OUT
R21 C31
R24 C32
L5
DIF OUT1
DIF OUT1
10
11
29
BUS GND
R22
RF AGC OUT
RF AGC OUT 28
DIF OUT2
R25
R40
C10
BS3
BS2
BS1
SDA
SCL
P5/ADC
VCC
12 P5/ADC
13 VCC
27
26
BS3
BS2
C33
IF GCA IN1
IF GCA IN1
14
15
16
17
18
19
BS1 25
SDA 24
SCL 23
AS 22
R28
R30
C35
C36
R39
IF GCA IN2
R8
R38
R41
C42
C40
IF GCA CTRL
IF
GCA CTRL
C12
IF GCA GND
IF GCA OUT2
IF GCA OUT1
R32
R33
C38
XTAL2 21
XTAL1 20
C13
X1
R35
C39
IF GCA OUT1
C14
R36
NOTE: This application information is advisory and performance-check is required at actual application circuits. TI assumes
no responsibility for the consequences of use of this circuit, such as an infringement of intellectual property rights or
other rights, including patents, of third parties.
Figure 24. Reference Measurement Circuit
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Crystal X1
Capacitors
C13 C14
20
21
Frequency
4 MHz
Type
X1
HC49SFNB04000H0 (Kyocera)
CX3225GB16000D0 (Kyocera)
27 pF
14 pF
27 pF
14 pF
16 MHz
C14
C13
Figure 25. Reference Crystal Oscillation Circuit
Table 12. Component Values for Measurement Circuit
PART NAME
VALUE
PART NAME
R1 (UHF RFIN1)
VALUE
Open (51Ω)
C1 (UHF RFIN1)
C2 (VHI RFIN)
C3 (VLO RFIN)
C4 (UHF RFIN)
C5 (MIXOUT)
C6 (MIXOUT)
C7 (IF IN)
2.2nF
2.2nF
2.2nF
2.2nF
5.5pF
2.2nF
0Ω
R2 (VHI RFIN)
R3 (VLO RFIN)
R4 (MIXOUT)
Open (51Ω)
Open (51Ω)
Open
0Ω
R5 (MIXOUT)
R8 (IF GCA CTRL)
R9 (VLO OSC)
R11 (VLO OSC)
R12 (VHI OSC)
R13 (VHI OSC)
R14 (UHF OSC)
R15 (UHF OSC)
R16 (UHF OSC)
R17 (UHF OSC)
R18 (VTU)
0Ω
0Ω
C10 (RF AGC OUT)
0.15µF
0.1µF
27pF
3.3kΩ
10Ω
C12 (IF GCA CTRL)
C13 (XTAL2)
3.3kΩ
4.7Ω
C14 (XTAL1)
27pF
C15 (VLO OSC)
C17 (VLO OSC)
C18 (VHI OSC)
C20 (VHI OSC)
C21 (UHF OSC)
C22 (UHF OSC)
C23 (UHF OSC)
C25 (VTU)
4pF
4.7Ω
68pF
1kΩ
10pF
2.2kΩ
3.3kΩ
82kΩ
22kΩ
200Ω
Open
200Ω
51Ω
130pF
6pF
R19 (CP)
6pF
R20 (VTU)
20pF
R21 (DIF OUT1)
R22 (DIF OUT1)
R24 (DIF OUT2)
R25 (DIF OUT2)
R28 (IF GCA IN1)
R30 (IF GCA IN2)
R32 (IF GCA OUT2)
R33 (IF GCA OUT2)
R35 (IF GCA OUT1)
R36 (IF GCA OUT1)
R38 (SCL)
2.2nF/50V
3.9nF/50V
10pF/50V
150pF/50V
2.2nF/50V
2.2nF
2.2nF
2.2nF
0.1µF
2.2nF
2.2nF
2.2nF
2.2nF
Open
C26 (CP)
C27 (CP)
C28 (VTU)
(51Ω)
(0Ω)
C29 (VTU)
C30 (AIF OUT)
C31 (DIF OUT1)
C32 (DIF OUT2)
C33 (VCC)
200Ω
51Ω
200Ω
Open
330Ω
330Ω
Open
Open
C35 (IF GCA IN1)
C36 (IF GCA IN2)
C38 (IF GCA OUT2)
C39 (IF GCA OUT1)
C40 (SCL)
R39 (SDA)
R40 (P5)
R41 (AS)
C42 (SDA)
Open
VC1 (VLO OSC)
VC2 (VHI OSC)
VC3 (UHF OSC)
X1
KDV270E
KDV270E
KDV216E
4MHz crystal
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Table 12. Component Values for Measurement Circuit (continued)
PART NAME
L1 (MIXOUT)
L2 (MIXOUT)
L3 (MIXOUT)
L4 (MIXOUT)
L5 (IFIN)
VALUE
PART NAME
VALUE
470nH (LK1608R47KT Taiyo Yuden)
560nH (LK1608R56KT Taiyo Yuden)
470nH (LK1608R47KT Taiyo Yuden)
560nH (LK1608R56KT Taiyo Yuden)
Open
L7 (VLO OSC)
L8 (VHI OSC)
L9 (UHF OSC)
f3.0mm, 9T, wire0.32mm
f1.8mm, 4T, wire0.4mm
f1.8mm, 2T, wire0.4mm
IF frequency:
36 MHz
Local frequency range:
VHF-LOW: 87 to 186 MHz
VHF-HIGH: 193 to 462 MHz
UHF: 470 to 894 MHz
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Test Circuits
Spectrum
Analyzer
SG
DUT
Vout diff
200Ω
VLO RFIN
(VHI RFIN)
DIFOUT1
DIFOUT2
Gv=20log(Vout diff/Vin)
=20log(Vout/Vin)+6+14.0
50Ω
50Ω
Vin
Vout
50Ω
250Ω
Figure 26. VHF Conversion Gain Measurement Circuit (at DIFOUT)
SG
Spectrum
Analyzer
DUT
Gv=20log(Vout/Vin)
VLO RFIN
(VHI RFIN)
AIFOUT
50Ω
50Ω
Vin
50Ω
Vout
Figure 27. VHF Conversion Gain Measurement Circuit (at AIFOUT)
Spectrum
Analyzer
SG
DUT
Vout diff 200Ω
Gv=20log(Vout diff/Vin)
=20log(Vout/Vin)+6+14.0
UHFRF IN1
UHFRF IN2
DIFOUT1
DIFOUT2
50Ω
50Ω
Vin
Vout
50Ω
250Ω
Figure 28. UHF Conversion Gain Measurement Circuit (at DIFOUT)
Spectrum
Analyzer
SG
DUT
Gv=20log(Vout/Vin)
UHFRF IN1
UHFRF IN2
AIFOUT
50Ω
50Ω
Vin
Vout
50Ω
Figure 29. UHF Conversion Gain Measurement Circuit (at AIFOUT)
DUT
SG
Spectrum
Analyzer
Vout difft
200Ω
IFGCAIN1
IFGCAIN2
IFGCAOUT1
Gv=20log(Vout diff/Vin)
=20log(Vout/Vin)+6+14.0
50Ω
50Ω
Vin
50Ω
Vout
IFGCAOUT2
IFGCACTRL
250Ω
DC Power
Source
Figure 30. IF GCA Gain Measurement Circuit
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NF
Meter
Noise
Source
DUT
Figure 31. Noise Figure Measurement Circuit
Signal
Generator
fdes:P=70dBuV
Mix
Pad
Modulation
Analyzer
DUT
fdes+/-7Mhz
AM30%,1kHz
Signal
Generator
Figure 32. 1% Cross Modulation Distortion Measurement Circuit
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TYPICAL CHARACTERISTICS
Band Switch Driver Output Voltage (BS1-BS4)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VCC = 5.3 V
VCC = 5.0 V
VCC = 4.5 V
0
2
4
6
8
10
12
14
16
18
20
Band Switch Current (mA)
Figure 33. Band Switch Driver Output Voltage
S-Parameter
40MHz
400MHz
500MHz
900MHz
Figure 34. VLO, VHI RFIN
Figure 35. UHF RFIN
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TYPICAL CHARACTERISTICS (continued)
60MHz
30MHz
60MHz
30MHz
Figure 36. DIFOUT
Figure 37. AIFOUT
60MHz
30MHz
60MHz
30MHz
Figure 38. IF GCA IN
Figure 39. IF GCAOUT
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TYPICAL CHARACTERISTICS (continued)
IF GCA Gain vs Control Voltage
70
60
50
40
VCC = 5.3 V
VCC = 5 V
VCC = 4.5 V
30
20
10
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
IF GCA CTRL Voltage (V)
Figure 40. IF GCA Gain vs Control Voltage
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PACKAGE OPTION ADDENDUM
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31-Mar-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
SN761645DBTR
NRND
TSSOP
DBT
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN761645DBTR
TSSOP
DBT
38
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP DBT 38
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
SN761645DBTR
2000
Pack Materials-Page 2
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