SN888C [TI]

总线极性借助 IEC-ESD 保护校正 RS-485 收发器;


型号：	SN888C
厂家：	TEXAS INSTRUMENTS
描述：	总线极性借助 IEC-ESD 保护校正 RS-485 收发器
文件：	总23页 (文件大小：700K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN888C

www.ti.com.cn

ZHCSC10 –SEPTEMBER 2013

针对静电计 (E-Meter) 的总线极性纠正 RS-485 收发器

查询样片: SN888C

特性

应用范围

•

超过 EIA-485 标准的要求

•

静电计

76ms 内的总线极性纠正

数据速率：300bps 至 250kbps

具有两个工作配置：

说明

SN888C 是一款低功耗 RS-485 收发器，此收发器具

有总线极性纠正和瞬态保护功能。热插拔时，此器件

在总线闲置的头 76ms 内检测并纠正总线极性。片载

瞬态保护功能保护此器件不受 IEC61000 静电放电

(ESD) 和瞬态放电 (EFT) 瞬态的影响。

–

只作为故障安全电阻器

故障安全和端接电阻器

•

一条总线上多达 256 个节点

小外形尺寸集成电路 (SOIC)-8 封装以实现向后兼

容性

SN888C 采用 SOIC-8 封装。此器件额定温度范围介

于 -40°C 和 85°C 之间。

•

总线引脚保护：

–

±16kV 的人体模型 (HBM) 保护

±12kV IEC61000-4-2 接触放电

+4kV IEC61000-4-4 快速瞬态突发

Cross-wire

Vcc

fault

1kꢀꢀ

120ꢀꢀ

1kꢀꢀ

Master

SN65HVD82

Slave

SN888C

POLCOR

RE DE

POLCOR

RE DE

Slave

SN888C

图 1. 支持极性纠正 (POLCOR) 的典型网络应用

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

English Data Sheet: SLLSEI4

SN888C

ZHCSC10 –SEPTEMBER 2013

www.ti.com.cn

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

SOIC-8

Block Diagram

(TOP VIEW)

Vcc

GND

DRIVER PIN FUNCTIONS

INPUT

ENABLE

OUTPUTS

DESCRIPTION

NORMAL MODE

Actively drives bus high

Actively drives bus low

Driver disabled

OPEN

Driver disabled by default

Actively drives bus high

POLARITY-CORRECTING MODE⁽¹⁾

Actively drives bus low

Actively drives bus high

Driver disabled

OPEN

Driver disabled by default

Actively drives bus low

OPEN

(1) The polarity-correcting mode is entered when V_ID< V_IT–and t > t_FSand DE = low. This state is latched when /RE turns from low to high.

RECEIVER PIN FUNCTIONS

DIFFERENTIAL

ENABLE

/RE

OUTPUT

INPUT

DESCRIPTION

V_ID= V_A– V_B

NORMAL MODE

Receive valid bus high

Indeterminate bus state

Receive valid bus low

Receiver disabled

V_IT+< V_ID

V_IT–< V_ID< V_IT+

V_ID< V_IT–

OPEN

Receiver disabled

Open, short, idle bus

Indeterminate bus state

POLARITY-CORRECTING MODE⁽¹⁾

V_IT+< V_ID

Receive valid bus low

V_IT–< V_ID< V_IT+

Indeterminate bus state

Receive polarity corrected bus high

Receiver disabled

V_ID< V_IT–

OPEN

Receiver disabled

Open, short, idle bus

Indeterminate bus state

(1) The polarity-correcting mode is entered when V_ID< V_IT–and t > t_FSand DE = low. This state is latched when /RE turns from low to high.

SN888C

www.ti.com.cn

ZHCSC10 –SEPTEMBER 2013

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

VALUE

UNIT

MIN

–0.5

–0.3

–100

–18

MAX

V_CC

Supply voltage

Input voltage range at any logic pin

5.7

100

Voltage input range, transient pulse, A and B, through 100 Ω

Voltage range at A or B inputs

Receiver output current

–24

Continuous total-power dissipation

See THERMAL INFORMATION table

IEC 61000-4-2 ESD (Contact Discharge), bus terminals and GND

IEC 61000-4-4 EFT (Fast transient or burst) bus terminals and GND

IEC 60749-26 ESD (HBM), bus terminals and GND

Test Method A114 (HBM), all pins

±12

±4

±16

±8

JEDEC Standard 22

Test Method C101 (Charged Device Model), all pins

Test Method A115 (Machine Model), all pins

±1.5

±200

170

150

T_J

Junction temperature

Storage temperature

°C

T_STG

–65

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

THERMAL INFORMATION

SN888C

THERMAL METRIC⁽¹⁾

UNITS

PACKAGE SOIC

(D)

θ_JA

Junction-to-ambient thermal resistance

116.1

60.8

57.1

13.9

56.5

θ_JCtop

θ_JB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance⁽²⁾

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

°C/W

ψ_JT

ψ_JB

θ_JCbot

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

POWER DISSIPATION

PARAMETER

TEST CONDITIONS

R_L= 300 Ω,

C_L= 50 pF (driver)

VALUE

UNITS

164

Unterminated

RS-422 load

RS-485 load

Power dissipation

Driver and receiver enabled,

V_CC= 5.5 V, T_J= 150°C

50% duty cycle square-wave signal at

250-kbps signaling rate:

R_L= 100 Ω,

C_L= 50 pF (driver)

247

316

R_L= 54 Ω,

C_L= 50 pF (driver)

SN888C

ZHCSC10 –SEPTEMBER 2013

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RECOMMENDED OPERATING CONDITIONS

MIN

4.5

–12

–7

NOM

MAX

UNIT

V_CC

V_ID

V_I

Supply voltage

5.5

Differential input voltage

Input voltage at any bus terminal (separate or common mode)⁽¹⁾

High-level input voltage (driver, driver-enable, and receiver-enable inputs)

Low-level input voltage (driver, driver-enable, and receiver-enable inputs)

V_IH

V_IL

V_CC

0.8

Driver

–60

–8

I_O

Output current

Receiver

C_L

Differential load capacitance

Differential load resistance

Signaling rate

R_L

1/t_UI

T_J

0.3

–40

250

150

kbps

Junction temperature

(2)

°C

T_A

Operating free-air temperature (see THERMAL INFORMATION for additional

information)

(1) The algebraic convention in which the least positive (most negative) limit is designated as minimum is used in this data sheet.

(2) Operation is specified for internal (junction) temperatures up to 150°C. Self-heating due to internal power dissipation should be

considered for each application. Maximum junction temperature is internally limited by the thermal shut-down (TSD) circuit which

disables the driver outputs when the junction temperature reaches 170°C.

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RL = 60 Ω, 375 Ω on each

See Figure 2

See Figure 3

1.5

2.5

output from –7 to +12 V

RL = 54 Ω (RS-485)

RL = 100 Ω (RS-422)

RL = 54 Ω, CL = 50 pF

Driver differential-output

voltage magnitude

│V_OD│

1.5

2.5

Change in magnitude of

driver differential-output

voltage

–0.2

0.2

Δ│V_OD

│

Steady-state common-mode

output voltage

V_CC/ 2

V_OC(SS)

Change in differential driver

common-mode output

voltage

–0.2

0.2

Center of two 27-Ω load

resistors

ΔV_OC

See Figure 3

Peak-to-peak driver common-

mode output voltage

850

V_OC(PP)

C_OD

Differential output

capacitance

Positive-going receiver

differential-input voltage

threshold

100

V_IT+

Negative-going receiver

differential-input voltage

threshold

–100

–35

V_IT–

Receiver differential-input

voltage threshold hysteresis

(1)

V_HYS

(V_IT+ – V_IT–

)

Receiver high-level output

voltage

I_OH= –8 mA

I_OL= 8 mA

2.4

V_CC– 0.3

0.2

V_OH

V_OL

Receiver low-level output

voltage

0.4

Driver input, driver enable,

and receiver enable input

current

–2

I_I

µA

(1) Under any specific conditions, V_IT+is ensured to be at least V_HYShigher than V_IT–

SN888C

www.ti.com.cn

ZHCSC10 –SEPTEMBER 2013

ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VO = 0 V or VCC, /RE at VCC

MIN

TYP

MAX

UNIT

Receiver high-impedance

output current

–10

I_OZ

µA

Driver short-circuit output

current

│I_OS│ with V_Aor V_Bfrom –7 to +12 V

150

125

│I_OS

│

µA

V_CC= 4.5 to 5.5 V or

V_I= 12 V

Bus input current (driver

disabled)

I_I

V_CC= 0 V, DE at 0 V

V_I= –7 V

–100

–40

750

Driver and receiver enabled

DE = V_CC, /RE =

GND, No load

900

650

750

Driver enabled, receiver

disabled

DE = V_CC, /RE = V_CC

No load

I_CC

Supply current (quiescent)

Supply current (dynamic)

µA

Driver disabled, receiver

enabled

DE = GND, /RE =

GND, No load

Driver and receiver disabled DE = GND, D = GND

/RE = VCC, No load

0.4

See

SWITCHING CHARACTERISTICS

3.3 ms > bit time > 4 μs (unless otherwise noted)

PARAMETER

DRIVER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t_r, t_f

Driver differential-output rise and

fall times

400

700

1200

RL = 54 Ω, CL = 50

See Figure 4

t_PHL, t_PLH

t_SK(P)

t_PHZ, t_PLZ

Driver propagation delay

700

500

1000

200

500

1000

Driver pulse skew, |t_PHL– t_PLH

Driver disable time

µs

See Figure 5 and

Figure 6

Driver enable time

Receiver enabled

Receiver disabled

RECEIVER

t_r, t_f

Receiver output rise and fall times

Receiver propagation delay time

195

t_PHL, t_PLH

t_SK(P)

CL = 15 pF

See Figure 7

Receiver pulse skew, |t_PHL– t_PLH

t_PHZ, t_PLZ

Receiver disable time

500

130

t_PZL(1)

t_PZH(1)

t_PZL(2)

t_PZH(2)

Driver enabled

Driver disabled

See Figure 8

See Figure 9

µs

Receiver enable time

Bus failsafe time

t_FS

Driver disabled

See Figure 10

SN888C

ZHCSC10 –SEPTEMBER 2013

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PARAMETER MEASUREMENT INFORMATION

DRIVER

Vcc

375

-7V < V_test< 12 V

0V or 5 V

V_OD

375

Figure 2. Measurement of Driver Differential-Output Voltage With Common-Mode Load

V_A

RL/2

V_B

0V or 5 V

V_OD

V_OC(PP)

ûV_OC(SS)

V_OC

C_L

V_OC

Figure 3. Measurement of Driver Differential and Common-Mode Output With RS-485 Load

Vcc

50%

V_I

t_PLH

t_PHL

C_L=

50 pF

§ꢀ2V

V_OD

90%

50%

10%

Input

Generator

V_I

V_OD

§ꢀ-2V

t_r

t_f

Figure 4. Measurement of Driver Differential-Output Rise and Fall Times and Propagation Delays

V_O

50%

V_I

R_L=

110

t_PZH

C_L=

50 pF

V_OH

Input

Generator

90%

V_I

50%

V_O

§ꢀ0V

t_PHZ

Figure 5. Measurement of Driver Enable and Disable Times With Active-High Output and Pull-Down Load

50%

R_L= 110

V_I

t_PZL

V_O

t_PLZ

§ꢀ5V

C_L=

50%

Input

Generator

50 pF

10%

V_I

V_OL

Figure 6. Measurement of Driver Enable and Disable Times With Active-Low Output and Pull-Up Load

SN888C

www.ti.com.cn

ZHCSC10 –SEPTEMBER 2013

PARAMETER MEASUREMENT INFORMATION (continued)

RECEIVER

50%

V_I

t_PLH

V_O

t_PHL

Input

Generator

V_I

1.5V

V_OH

90%

50%

10%

C_L= 15 pF

V_OD

V_OL

t_r

t_f

Figure 7. Measurement of Receiver Output Rise and Fall Times and Propagation Delays

Vcc

V_I

t_PZH(1)

50%

1 k

t_PHZ

V_O

D at 5V

S1 to GND

0V or 5 V

V_OH

§ꢀ0V

V_CC

V_OL

90%

V_O

50%

C_L= 15 pF

t_PZL(1)

t_PLZ

D at 0V

S1 to V_CC

Input

Generator

V_I

V_O

50%

10%

Figure 8. Measurement of Receiver Enable and Disable Times With Driver Enabled

Vcc

V_I

t_PZH(2)

50%

1 k

0V or 1.5 V

1.5 V or 0 V

V_O

V_OH

§ꢀ0V

V_CC

V_OL

A at 1.5V

B at 0V

S1 to GND

V_O

50%

C_L= 15 pF

t_PZL(2)

Input

Generator

A at 0V

B at 1.5V

S1 to V_CC

V_I

V_O

50%

Figure 9. Measurement of Receiver Enable Times With Driver Disabled

V_I

50%

V_O

10 k

Input

Generator

t_PHL

t_FS

V_I

1.5V

V_CC

V_O

50%

(DE = Low)

Figure 10. Measurement of Receiver Polarity-Correction Time With Driver Disabled

SN888C

ZHCSC10 –SEPTEMBER 2013

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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS

D and RE Inputs

DE Input

R Output

Vcc

100k

D,RE

100k

Driver Outputs

Vcc

16V

Receiver Inputs

Vcc

16V

SN888C

www.ti.com.cn

ZHCSC10 –SEPTEMBER 2013

DEVICE INFORMATION

Low-Power Standby Mode

When the driver and the receiver are both disabled (DE = low and RE = high) the device enters standby mode. If

the enable inputs are in the disabled state for only a brief time (for example: less than 100 ns), the device does

not enter standby mode, preventing the SN888C device from entering standby mode during driver or receiver

enabling. Only when the enable inputs are held in the disabled state for a duration of 300 ns or more does the

device enter low-power standby mode. In this mode most internal circuitry is powered down, and the steady-state

supply current is typically less than 400 nA. When either the driver or the receiver is re-enabled, the internal

circuitry becomes active. During V_CCpower-up, when the device is set for both driver and receiver disabled

mode, the device may consume more than 5-µA of ICC disabled current because of capacitance charging

effects. This condition occurs only during V_CCpower-up.

Bus Polarity Correction

The SN888C device automatically corrects a wrong bus-signal polarity caused by a cross-wire fault. In order to

detect the bus polarity, all three of the following conditions must be met:

•

A failsafe-biasing network (commonly at the master node) must define the signal polarity of the bus.

A slave node must enable the receiver and disable the driver (/RE = DE = low).

The bus must idle for the failsafe time, t_FS-max

After the failsafe time has passed, the polarity correction is complete and applied to both the receive and transmit

channels. The status of the bus polarity latches within the transceiver and maintains for subsequent data

transmissions.

NOTE

Avoid data string durations of consecutive 0s or 1s exceeding t_FS-min, which can accidently

trigger a wrong polarity correction.

Figure 11 shows a simple point-to-point data link between a master node and a slave node. Because the master

node with the failsafe biasing network determines the signal polarity on the bus, an RS-485 transceiver without

polarity correction, such as SN65HVD82, suffices. All other bus nodes, typically performing as slaves, require the

SN888C transceiver with polarity correction.

V_S-Master

V_S-Slave

Master

node

Slave

node

V_SM

Vdd

Vcc

Vdd

RxD

R_FS

MCU

R_T

(opt.)

DIR

TxD

DIR

TxD

(opt.)

R_FS

DGND

GND

DGND

Figure 11. Point-To-Point Data Link With Cross-Wire Fault

Prior to initiating data transmission the master transceiver must idle for a time span that exceeds the maximum

failsafe time, t_FS-max, of a slave transceiver. To accomplish this idle time, drive the direction control line, DIR, low.

After a time, t > t_FS-max, the master begins transmitting data.

Because of the indicated cross-wire fault between master and slave, the slave node receives bus signals with

reversed polarity. Assuming the slave node has just been connected to the bus, the direction-control pin is

pulled-down during power-up, and then is actively driven low by the slave MCU. The polarity correction begins as

soon as the slave supply is established and ends after approximately 44 to 76 ms.

SN888C

ZHCSC10 –SEPTEMBER 2013

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Low due to pull-down

or actively driven

DIR_m

D_m

high Z

Master

signals

V_Am

V_FS

-Vod

+Vid

+Vod

-Vid

V_Bm

V_Bs

V_FS

V_As

V_Ss

Slave

signals

Low due to pull-down and then actively driven

DIR_s

R_s

t_FS

Uncorrected R output:

R is in phase with

wrong V polarity

Corrected R output:

R is reversed to

wrong V polarity

Figure 12. Polarity Correction Timing Prior to a Data Transmission

Initially the slave receiver assumes that the correct bus polarity is applied to the inputs and performs no polarity

reversal. Because of the reversed polarity of the bus-failsafe voltage, the output of the slave receiver, R_S, turns

low. After t_FShas passed and the receiver has detected the wrong bus polarity, the internal POLCOR logic

reverses the input signal and R_Sturns high.

At this point, all incoming bus data with reversed polarity are polarity-corrected within the transceiver. Because

polarity correction is also applied to the transmit path, the data sent by the slave MCU are reversed by the

POLCOR logic, then fed into the driver.

The reversed data from the slave MCU are reversed again by the cross-wire fault in the bus, and the correct bus

polarity is reestablished at the master end.

This process repeats each time the device powers up and detects an incorrect bus polarity.

SN888C

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ZHCSC10 –SEPTEMBER 2013

APPLICATION INFORMATION

Device Configuration

The SN888C device is a half-duplex RS-485 transceiver operating from a single 5-V ±10% supply. The driver

and receiver enable pins that allow for the configuration of different operating modes.

Vcc

GND

c) Receiver always on

b) Combined enable signals for

use as directional control pin

a) Independent driver and

receiver enable signals

Figure 13. Transceiver Configurations

Using independent enable lines provides the most flexible control as the lines allow for the driver and the

receiver to be turned on and off individually. While this configuration requires two control lines, it allows for

selective listening to the bus traffic, whether the driver is transmitting data or not. Only this configuration allows

the SN888C device to enter low-power standby mode because it allows both the driver and receiver to be

disabled simultaneously.

Combining the enable signals simplifies the interface to the controller by forming a single direction-control signal.

Thus, when the direction-control line is high, the transceiver is configured as a driver, while when low, the device

operates as a receiver.

Tying the receiver enable to ground and controlling only the driver-enable input also uses only one control line. In

this configuration, a node not only receives the data on the bus sent by other nodes, but also receives the data

sent on the bus, enabling the node to verify the correct data has been transmitted.

Bus Design

An RS-485 bus consists of multiple transceivers connected in parallel to a bus cable. To eliminate line

reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic

impedance, Z0, of the cable. This method, known as parallel termination, allows for relatively high data rates over

long cable length.

Common cables used are unshielded twisted pair (UTP), such as low-cost CAT-5 cable with Z0 = 100 Ω, and

RS-485 cable with Z0 = 120 Ω. Typical cable sizes are AWG 22 and AWG 24.

The maximum bus length is typically given as 4000 ft or 1200 m, and represents the length of an AWG 24 cable

whose cable resistance approaches the value of the termination resistance, thus reducing the bus signal by half

or 6 dB. Actual maximum usable cable length depends on the signaling rate, cable characteristics, and

environmental conditions.

Table 1. VID With a Failsafe Network and Bus Termination

V_CC

R_LDifferential

Termination

R_FSPull-Up

R_FSPull-Down

V_ID

560 Ω

1 KΩ

560 Ω

1 KΩ

230 mV

131 mV

29 mV

13 mV

5 V

54 Ω

4.7 KΩ

10 KΩ

4.7 KΩ

10 KΩ

An external failsafe-resistor network must be used to ensure failsafe operation during an idle bus state. When the

bus is not actively driven, the differential receiver inputs could float allowing the receiver output to assume a

random output. A proper failsafe network forces the receiver inputs to exceed the VIT threshold, thus forcing the

SN888C receiver output into the failsafe (high) state. Table 1 shows the differential input voltage (V_ID) for various

failsafe networks with a 54-Ω differential bus termination.

SN888C

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Cable Length Versus Data Rate

There is an inverse relationship between data rate and cable length, which means the higher the data rate, the

shorter the cable length; and conversely, the lower the data rate, the longer the cable length. While most RS-485

systems use data rates between 10 kbps and 100 kbps, applications such as e-metering often operate at rates of

up to 250 kbps even at distances of 4000 ft and longer. Longer distances are possible by allowing for small

signal jitter of up to 5 or 10%.

CABLE LENGTH (FT)

DATA RATE (BPS)

10000

5,10,20 % Jitter

1000

Conservative

Characteristics

100

10k

100k

10M

100M

DATA RATE - bps

Stub Length

When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as

the stub, should be as short as possible. The reason for the short distance is because a stub presents a non-

terminated piece of bus line, which can introduce reflections if the distance is too long. As a general guideline,

the electrical length or round-trip delay of a stub should be less than one-tenth of the rise time of the driver, thus

leading to a maximum physical stub length as shown in Equation 1.

L_Stub≤ 0.1 × t_r× v × c

where

•

t_ris the 10 / 90 rise time of the driver

c is the speed of light (3 × 10⁸m/s or 9.8 × 10⁸ft/s)

v is the signal velocity of the cable (v = 78%) or trace (v = 45%) as a factor of c

(1)

Based on Equation 1, with a minimum rise time of 400 ns, Equation 2 shows the maximum cable-stub length of

the SN888C device.

_Stub≤ 0.1 × 400 × 10^-9× 3 × 10⁸× 0.78 = 9,4 m (or 30.6 ft)

(2)

RE DE

Figure 14. Stub Length

SN888C

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ZHCSC10 –SEPTEMBER 2013

3-V to 5-V Interface

Interfacing the SN888C device to a 3-V controller is easy. Because the 5-V logic inputs of the transceiver accept

3-V input signals, they can be directly connected to the controller I/O. The 5-V receiver output, R, however, must

be level-shifted by a Schottky diode and a 10-k resistor to connect to the controller input (see Figure 15). When

R is high, the diode is reverse biased and the controller supply potential lies at the controller RxD input. When R

is low, the diode is forward biased and conducts. Only in this case, the diode forward voltage of 0.2 V lies at the

controller RxD input.

3.3V

10k

BAS70

RxD

RCV

DRV

TxD

Vcc

0.1µF

MCU

XCVR

GND

Figure 15. 3-V to 5-V Interface

Noise Immunity

The input sensitivity of a standard RS-485 transceiver is ±200 mV. When the differential input voltage, V_ID, is

greater than +200 mV, the receiver output turns high, for V_ID< –200 mV the receiver outputs low.

The SN888C transceiver implements high receiver noise-immunity by providing a typical positive-going input

threshold of 35 mV and a minimum hysteresis of 40 mV. In the case of a noisy input condition, a differential

noise voltage of up to 40 mV_PPcan be present without causing the receiver output to change states from high to

low.

Transient Protection

The bus terminals of the SN888C transceiver family possess on-chip ESD protection against ±16 kV HBM and

±12 kV IEC61000-4-2 contact discharge. The International Electrotechnical Commision (IEC) ESD test is far

more severe than the HBM ESD test. The 50% higher charge capacitance, C_S, and 78% lower discharge

resistance, R_Dof the IEC model produce significantly higher discharge currents than the HBM model.

As stated in the IEC 61000-4-2 standard, contact discharge is the preferred transient protection test method.

Although IEC air-gap testing is less repeatable than contact testing, air discharge protection levels are inferred

from the contact discharge test results.

50M

(1M)

330Ω

(1.5k)

10kV IEC

High-Voltage

Pulse

Generator

Device

Under

Test

150pF

(100pF)

10kV HBM

100

150

200

250

300

Time - ns

Figure 16. HBM and IEC-ESD Models and Currents in Comparison (HBM Values in Parenthesis)

SN888C

ZHCSC10 –SEPTEMBER 2013

www.ti.com.cn

The on-chip implementation of IEC ESD protection significantly increases the robustness of equipment. Common

discharge events occur because of human contact with connectors and cables. Designers may choose to

implement protection against longer duration transients, typically referred to as surge transients. Figure 10

suggests two circuit designs providing protection against short and long-duration surge transients, in addition to

ESD and Electrical Fast Transients (EFT) transients. Table 2 lists the bill of materials for the external protection

devices.

EFTs are generally caused by relay-contact bounce, or the interruption of inductive loads. Surge transients often

result from lightning strikes (direct strike or an indirect strike which induces voltages and currents), or the

switching of power systems, including load changes and short circuits switching. These transients are often

encountered in industrial environments, such as in factory automation and power-grid systems.

Figure 17 compares the pulse-power of the EFT and surge transients with the power caused by an IEC ESD

transient. In the diagram on the left of Figure 17, the tiny blue blip in the bottom left corner represents the power

of a 10-kV ESD transient, which is low compared to the significantly higher EFT power spike, and certainly lower

than the 500-V surge transient. This type of transient power is well representative of factory environments in

industrial and process automation. The diagram on the right of Figure 17 compares the enormous power of a 6-

kV surge transient, most likely occurring in e-metering applications of power generating and power grid systems,

with the aforementioned 500-V surge transient.

NOTE

The unit of the pulse-power changes from kW to MW, thus making the power of the 500-V

surge transient almost disappear from the scale.

3.0

2.8

2.6

2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

6kV Surge

0.5kV Surge

4kV EFT

0.5kV Surge

10kV ESD

10 15 20 25 30 35 40

Time - μs

Figure 17. Power Comparison of ESD, EFT, and Surge Transients

In the case of surge transients, hgih-energy content is signified by long pulse duration and slow-decaying pulse

power

The electrical energy of a transient that is dumped into the internal protection cells of the transceiver is converted

into thermal energy. This thermal energy heats the protection cells and literally destroys them, thus destroying

the transceiver. Figure 18 shows the large differences in transient energies for single ESD, EFT, and surge

transients as well as for an EFT pulse train, commonly applied during compliance testing.

SN888C

www.ti.com.cn

ZHCSC10 –SEPTEMBER 2013

1000

100

Surge

EFT Pulse Train

0.1

0.01

10^-3

10^-4

10^-5

10^-6

EFT

ESD

0.5

8 10

Peak Pulse Voltage - kV

Figure 18. Comparison of Transient Energies

Table 2. Bill of Materials

Device

XCVR

Function

5-V, 250-kbps RS-485 Transceiver

10-Ω, Pulse-Proof Thick-Film Resistor

Bidirectional 400-W Transient Suppressor

Bidirectional.

Order Number

Manufacturer

SN888C

R1, R2

CRCW0603010RJNEAHP

CDSOT23-SM712

Vishay

TVS

Bourns

TBU1, TBU2

TBU-CA-065-200-WH

200mA Transient Blocking Unit 200-V, Metal-

Oxide Varistor

MOV1, MOV2

MOV-10D201K

Bourns

Vcc

10k

Vcc

10k

0.1μF

TBU1

RxD

MCU

Vcc

RxD

MCU

DIR

TxD

Vcc

MOV1

TVS

XCVR

DIR

TxD

MOV2

GND

TBU2

10k

Figure 19. Transient Protections Against ESD, EFT, and Surge Transients

The left circuit shown in Figure 19 provides surge protection of ≥ 500-V transients, while the right protection

circuits can withstand surge transients of 5 kV.

SN888C

ZHCSC10 –SEPTEMBER 2013

www.ti.com.cn

Design and Layout Considerations for Transient Protection

Because ESD and EFT transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high-

frequency layout techniques must be applied during PCB design.

In order for PCB design to be successful, begin with the design of the protection circuit in mind.

1. Place the protection circuitry close to the bus connector to prevent noise transients from penetrating your

board.

2. Use V_ccand ground planes to provide low-inductance. Note that high-frequency currents follow the path of

least inductance, not the path of least impedance.

3. Design the protection components into the direction of the signal path. Do not force the transients currents to

divert from the signal path to reach the protection device.

4. Apply 100-NF to 220-nF bypass capacitors as close as possible to the V_CC-pins of transceiver, UART,

controller ICs on the board.

5. Use at least two vias for V_CCand ground connections of bypass capacitors and protection devices to

minimize effective via-inductance.

6. Use 1-k to 10-k pull-up or pull-down resistors for enable lines to limit noise currents in these lines during

transient events.

7. Insert pulse-proof resistors into the A and B bus lines, if the TVS clamping voltage is higher than the

specified maximum voltage of the transceiver bus terminals. These resistors limit the residual clamping

current into the transceiver and prevent it from latching up.

–

While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-

oxide varistors (MOVs), which reduce the transients to a few-hundred volts of clamping voltage, and

transient blocking units (TBUs) that limit transient current to 200 mA.

SN888C

www.ti.com.cn

ZHCSC10 –SEPTEMBER 2013

Isolated Bus Node Design

Many RS-485 networks use isolated bus nodes to prevent the creation of unintended ground loops and their

disruptive impact on signal integrity. An isolated bus node typically includes a micro controller that connects to

the bus transceiver through a multi-channel, digital isolator (Figure 20).

0.1μF

MBR0520L

1:1.33

3.3V

ISO

Vcc

OUT

TLV70733

EN GND

SN6501

10μF 0.1μF

10μF

GND

4,5

10μF

MBR0520L

ISO-BARRIER

3.3V

0.1μF

PSU

0.1μF

4.7k

Vcc1

Vcc2

EN1 ISO7241 EN2

DVcc

Vcc

OUTD

INA

IND

OUTA

OUTB

UCA0RXD

P3.0

XOUT

XIN

MSP430

F2132

SN888C

INB

P3.1

INC

OUTC

GND2

9,15

UCA0TXD

DVss

GND2

GND1

2,8

TVS

Short thick earth wire or chassis

island

Protective Earth Ground,

Equipment Safety Ground

R1,R2, TVS: see A. below

= 1MΩ, 2kV high-voltageresistor, TT electronics, HVC 2010 1M0 G T3

= 4.7nF, 2kV high-voltagecapacitor, NOVACAP, 1812 B 472 K 202 N T

Floating RS-485 Common

A. See Table 2.

Figure 20. Isolated Bus Node With Transient Protection

Power isolation is accomplished using the push-pull transformer driver SN6501 and a low-cost LDO, TLV70733.

Signal isolation uses the quadruple digital isolator ISO7241. Notice that both enable inputs, EN1 and EN2, are

pulled-up via 4.7-k resistors to limit input currents during transient events.

While the transient protection is similar to the one in Figure 19 (left circuit), an additional high-voltage capacitor

diverts transient energy from the floating RS-485 common further towards protective earth (PE) ground. This

diversion is necessary as noise transients on the bus are usually referred to earth potential.

R_VHrefers to a high-voltage resistor, and in some applications, even a varistor. This resistance is applied to

prevent charging of the floating ground to dangerous potentials during normal operation.

Occasionally varistors are used instead of resistors in order to rapidly discharge C_HV, if expecting that fast

transients might charge C_HVto high-potentials.

Note that the PE island represents a copper island on the PCB for the provision of a short, thick earth wire

connecting this island to PE ground at the entrance of the power supply unit (PSU).

In equipment designs using a chassis, the PE connection is usually provided through the chassis itself. Typically

the PE conductor is tied to the chassis at one end, while the high-voltage components, C_HVand R_HV, connect to

the chassis at the other end.

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

SN888CD

ACTIVE

SOIC

RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 85

RS485N

EESA

SN888CDR

ACTIVE

2500 RoHS & Green

NIPDAU

RS485N

EESA

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE OUTLINE

D0008A

SOIC - 1.75 mm max height

SCALE 2.800

SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE

.228-.244 TYP

[5.80-6.19]

.004 [0.1] C

PIN 1 ID AREA

6X .050

[1.27]

.189-.197

[4.81-5.00]

NOTE 3

.150

[3.81]

4X (0 -15 )

8X .012-.020

[0.31-0.51]

.150-.157

[3.81-3.98]

NOTE 4

.069 MAX

[1.75]

.010 [0.25]

C A B

.005-.010 TYP

[0.13-0.25]

4X (0 -15 )

SEE DETAIL A

.010

[0.25]

.004-.010

[0.11-0.25]

0 - 8

.016-.050

[0.41-1.27]

DETAIL A

TYPICAL

(.041)

[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

SEE

DETAILS

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

6X (.050 )

[1.27]

(.213)

[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED

METAL

EXPOSED

METAL

.0028 MAX

[0.07]

.0028 MIN

[0.07]

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

6X (.050 )

[1.27]

(.213)

[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

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SN888C [TI]

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