SNJ54ABT18245AWDR [TI]

ABT SERIES, DUAL 9-BIT BOUNDARY SCAN TRANSCEIVER, TRUE OUTPUT, CDFP56, 0.380 INCH, CERAMIC, DFP-56;


型号：	SNJ54ABT18245AWDR
厂家：	TEXAS INSTRUMENTS
描述：	ABT SERIES, DUAL 9-BIT BOUNDARY SCAN TRANSCEIVER, TRUE OUTPUT, CDFP56, 0.380 INCH, CERAMIC, DFP-56 CD 信息通信管理输出元件逻辑集成电路
文件：	总35页 (文件大小：1004K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN54ABT18245A, SN74ABT18245A

SCAN TEST DEVICES

WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUARY 1999

SN54ABT18245A . . . WD PACKAGE

SN74ABT18245A . . . DGG OR DL PACKAGE

(TOP VIEW)

Members of the Texas Instruments

SCOPE Family of Testability Products

Members of the Texas Instruments

Widebus Family

1DIR

1B1

1B2

GND

1B3

1B4

56 1OE

Compatible With the IEEE Standard

1149.1-1990 (JTAG) Test Access Port and

Boundary-Scan Architecture

1A1

1A2

GND

1A3

1A4

SCOPE Instruction Set

– IEEE Standard 1149.1-1990 Required

Instructions, CLAMP and HIGHZ

– Parallel-Signature Analysis at Inputs

– Pseudo-Random Pattern Generation

From Outputs

– Sample Inputs/Toggle Outputs

– Binary Count From Outputs

– Device Identification

1B5

1B6

1B7

GND

1B8

1B9

2B1

2B2

2B3

2B4

GND

2B5

2B6

2B7

1A5

1A6

1A7

GND

1A8

1A9

2A1

2A2

2A3

2A4

GND

2A5

2A6

2A7

– Even-Parity Opcodes

State-of-the-Art EPIC-ΙΙB BiCMOS Design

Significantly Reduces Power Dissipation

Packaged in Plastic Shrink Small-Outline

(DL) and Thin Shrink Small-Outline (DGG)

Packages and 380-mil Fine-Pitch Ceramic

Flat (WD) Packages

description

2B8

2B9

GND

2DIR

TDO

TMS

2A8

2A9

GND

2OE

TDI

The’ABT18245Ascantestdeviceswith18-bitbus

transceivers are members of the Texas

Instruments SCOPE

testability integrated-

circuit family. This family of devices supports IEEE

Standard 1149.1-1990 boundary scan to facilitate

testing of complex circuit-board assemblies. Scan

access to the test circuitry is accomplished via the

4-wire test access port (TAP) interface.

TCK

In the normal mode, these devices are 18-bit noninverting bus transceivers. They can be used either as two

9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot

samples of the data appearing at the device pins or to perform a self-test on the boundary-test cells. Activating

the TAP in the normal mode does not affect the functional operation of the SCOPE bus transceivers.

Data flow is controlled by the direction-control (DIR) and output-enable (OE) inputs. Data transmission is

allowed from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at DIR. OE can

be used to disable the device so that the buses are effectively isolated.

In the test mode, the normal operation of the SCOPE bus transceivers is inhibited and the test circuitry is

enabled to observe and control the input/output (I/O) boundary of the device. When enabled, the test circuitry

performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCOPE, Widebus, and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT18245A, SN74ABT18245A

SCAN TEST DEVICES

WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUARY 1999

description (continued)

Four dedicated test pins observe and control the operation of the test circuitry: test-data input (TDI), test-data

output(TDO), test-modeselect(TMS), andtestclock(TCK). Additionally, thetestcircuitryperformsothertesting

functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation

(PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

The SN54ABT18245A is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74ABT18245A is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(normal mode, each 9-bit section)

INPUTS

OPERATION

DIR

B data to A bus

A data to B bus

Isolation

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT18245A, SN74ABT18245A

SCAN TEST DEVICES

WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUARY 1999

functional block diagram

Boundary-Scan Register

1DIR

1OE

1B1

1A1

One of Nine Channels

2DIR

2OE

2A1

2B1

One of Nine Channels

Bypass Register

Boundary-Control

Identification

TDO

Instruction Register

TDI

TMS

TCK

TAP

Controller

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT18245A, SN74ABT18245A

SCAN TEST DEVICES

WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUARY 1999

Terminal Functions

TERMINAL

NAME

DESCRIPTION

1A1–1A9,

2A1–2A9

Normal-function A-bus I/O ports. See function table for normal-mode logic.

Normal-function B-bus I/O ports. See function table for normal-mode logic.

1B1–1B9,

2B1–2B9

1DIR, 2DIR

GND

Normal-function direction controls. See function table for normal-mode logic.

Ground

1OE, 2OE

Normal-function output enables. See function table for normal-mode logic.

Test clock. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous to

TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK.

TCK

TDI

Test data input. One of four terminals required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data through

the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.

Test data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data

through the instruction register or selected data register.

TDO

TMS

Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through its TAP

controller states. An internal pullup forces TMS to a high level if left unconnected.

Supply voltage

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT18245A, SN74ABT18245A

SCAN TEST DEVICES

WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUARY 1999

test architecture

Serial-test information is conveyed by means of a 4-wire test bus, or TAP, that conforms to IEEE Standard

1149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The

TAP controller monitors two signals from the test bus, TCK and TMS. The TAP controller extracts the

synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip

control signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram.

The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and

output data changes on the falling edge of TCK. This scheme ensures that data to be captured is valid for fully

one-half of the TCK cycle.

The functional block diagram illustrates the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan

architecture and the relationship among the test bus, the TAP controller, and the test registers. As illustrated,

the device contains an 8-bit instruction register and four test-data registers: a 44-bit boundary-scan register, a

3-bit boundary-control register, a 1-bit bypass register, and a 32-bit device-identification register.

Test-Logic-Reset

TMS = H

TMS = L

TMS = H

Run-Test/Idle

Select-DR-Scan

TMS = L

Select-IR-Scan

TMS = L

TMS = H

Capture-DR

TMS = L

Capture-IR

TMS = L

Shift-DR

Shift-IR

TMS = L

TMS = H

Exit1-IR

TMS = H

Exit1-DR

TMS = L

Pause-DR

TMS = H

Pause-IR

TMS = H

Exit2-IR

TMS = L

Exit2-DR

TMS = H

Update-DR

Update-IR

TMS = H

TMS = L

TMS = H

TMS = L

Figure 1. TAP-Controller State Diagram

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT18245A, SN74ABT18245A

SCAN TEST DEVICES

WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUARY 1999

state diagram description

The TAP controller is a synchronous finite-state machine that provides test control signals throughout the

device. The state diagram shown in Figure 1 is in accordance with IEEE Standard 1149.1-1990. The TAP

controller proceeds through its states based on the level of TMS at the rising edge of TCK.

As shown, the TAP controller consists of 16 states. There are six stable states (indicated by a looping arrow in

the state diagram) and ten unstable states. A stable state is a state the TAP controller can retain for consecutive

TCK cycles. Any state that does not meet this criterion is an unstable state.

There are two main paths through the state diagram: one to access and control the selected data register and

one to access and control the instruction register. Only one register can be accessed at a time.

Test-Logic-Reset

The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset

and is disabled so that the normal logic function of the device is performed. The instruction register is reset to

an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data

registers also can be reset to their power-up values.

The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more

than five TCK cycles if TMS is left high. TMS has an internal pullup resistor that forces it high if left unconnected

or if a board defect causes it to be open circuited.

For the ’ABT18245A, the instruction register is reset to the binary value 10000001, which selects the IDCODE

instruction. Bits 43–40 in the boundary-scan register are reset to logic 0, ensuring that these cells, which control

the A-port and B-port outputs are set to benign values (i.e., if test mode were invoked, the outputs would be at

the high-impedance state). Reset values of other bits in the boundary-scan register should be considered

indeterminate. The boundary-control register is reset to the binary value 010, which selects the PSA test

operation.

Run-Test/Idle

The TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test

operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans.

Run-Test/Idle is a stable state in which the test logic actively can be running a test or can be idle. The test

operations selected by the boundary-control register are performed while the TAP controller is in the

Run-Test/Idle state.

Select-DR-Scan, Select-lR-Scan

No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits

either of these states on the next TCK cycle. These states allow the selection of either data-register scan or

instruction-register scan.

Capture-DR

When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the

Capture-DR state, the selected data register can capture a data value as specified by the current instruction.

Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the Capture-DR

state.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT18245A, SN74ABT18245A

SCAN TEST DEVICES

WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUARY 1999

Shift-DR

Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO. On the first

falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic level

present in the least significant bit of the selected data register.

While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle.

The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during

the TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR).

The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.

Exit1-DR, Exit2-DR

The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return

to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register. On the first falling

edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state.

Pause-DR

No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain

indefinitely. The Pause-DR state suspends and resumes data-register scan operations without loss of data.

Update-DR

If the current instruction calls for the selected data register to be updated with current data, such updates occur

on the falling edge of TCK, following entry to the Update-DR state.

Capture-IR

When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In

the Capture-IR state, the instruction register captures its current status value. This capture operation occurs

on the rising edge of TCK, upon which the TAP controller exits the Capture-IR state. For the ’ABT18245A, the

status value loaded in the Capture-IR state is the fixed binary value 10000001.

Shift-IR

Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO. On

the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the

logic level present in the least significant bit of the instruction register.

While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK

cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs

during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to

Shift-IR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-IR state.

Exit1-IR, Exit2-IR

The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to

return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register. On the

first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance state.

Pause-IR

No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain

indefinitely. The Pause-IR state suspends and resumes instruction-register scan operations without loss of

data.

Update-IR

The current instruction is updated and takes effect on the falling edge of TCK, following entry to the Update-IR

state.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT18245A, SN74ABT18245A

SCAN TEST DEVICES

WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUARY 1999

With the exception of the bypass and device-identification registers, any test register can be thought of as a

serial-shift register with a shadow latch on each bit. The bypass and device-identification registers differ in that

they contain only a shift register. During the appropriate capture state (Capture-IR for instruction register,

Capture-DR for data registers), the shift register can be parallel loaded from a source specified by the current

instruction. During the appropriate shift state (Shift-IR or Shift-DR), the contents of the shift register are shifted

out from TDO while new contents are shifted in at TDI. During the appropriate update state (Update-IR or

Update-DR), the shadow latches are updated from the shift register.

instruction register description

The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information

contained in the instruction includes the mode of operation (either normal mode, in which the device performs

itsnormallogicfunction, ortestmode, inwhichthenormallogicfunctionisinhibitedoraltered), thetestoperation

to be performed, which of the four data registers is to be selected for inclusion in the scan path during

data-register scans, and the source of data to be captured into the selected data register during Capture-DR.

Table 3 lists the instructions supported by the ’ABT18245A. The even-parity feature specified for SCOPE

devices is supported in this device. Bit 7 of the instruction opcode is the parity bit. Any instructions that are

defined for SCOPE devices but are not supported by this device default to BYPASS.

During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted

out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value

that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated

and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the

binary value 10000001, which selects the IDCODE instruction. The IR order of scan is shown in Figure 2.

Bit 7

Parity

(MSB)

Bit 0

(LSB)

TDI

TDO

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Figure 2. Instruction Register Order of Scan

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT18245A, SN74ABT18245A

SCAN TEST DEVICES

WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUARY 1999

data register description

boundary-scan register

The boundary-scan register (BSR) is 44 bits long. It contains one boundary-scan cell (BSC) for each

normal-function input pin, one BSC for each normal-function I/O pin (one single cell for both input data and

output data), and one BSC for each of the internally decoded output-enable signals (1OEA, 2OEA, 1OEB,

2OEB). The BSR is used to store test data that is to be applied externally to the device output pins, and/or to

capture data that appears internally at the outputs of the normal on-chip logic and/or externally at the device

input pins.

The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The

contents of the BSR can change during Run-Test/Idle, as determined by the current instruction. At power up

or in Test-Logic-Reset, BSCs 43–40 are reset to logic 0, ensuring that these cells, which control A-port and

B-port outputs, are set to benign values (i.e., if test mode were invoked, the outputs would be at the

high-impedance state). Reset values of other BSCs should be considered indeterminate.

When external data is to be captured, the BSCs for signals 1OEA, 2OEA, 1OEB, and 2OEB capture logic values

determined by the following positive-logic equations: 1OEA = 1OE • 1DIR, 2OEA = 2OE • 2DIR,

1OEB = 1OE • DIR, and 2OEB = 2OE • DIR. When data is to be applied externally, these BSCs control the

drive state (active or high impedance) of their respective outputs.

The BSR order of scan is from TDI through bits 43–0 to TDO. Table 1 shows the BSR bits and their associated

device pin signals.

Table 1. Boundary-Scan Register Configuration

BSR BIT

NUMBER

DEVICE

SIGNAL

BSR BIT

NUMBER

DEVICE

SIGNAL

BSR BIT

NUMBER

DEVICE

SIGNAL

BSR BIT

NUMBER

DEVICE

SIGNAL

BSR BIT

NUMBER

DEVICE

SIGNAL

2OEB

1OEB

2OEA

1OEA

2DIR

1DIR

2OE

2A9-I/O

2A8-I/O

2A7-I/O

2A6-I/O

2A5-I/O

2A4-I/O

2A3-I/O

2A2-I/O

2A1-I/O

1A9-I/O

1A8-I/O

1A7-I/O

1A6-I/O

1A5-I/O

1A4-I/O

1A3-I/O

1A2-I/O

1A1-I/O

2B9-I/O

2B8-I/O

2B7-I/O

2B6-I/O

2B5-I/O

2B4-I/O

2B3-I/O

2B2-I/O

2B1-I/O

1B9-I/O

1B8-I/O

1B7-I/O

1B6-I/O

1B5-I/O

1B4-I/O

1B3-I/O

1B2-I/O

1B1-I/O

1OE

boundary-control register

The boundary-control register (BCR) is three bits long. The BCR is used in the context of the boundary-run test

(RUNT) instruction to implement additional test operations not included in the basic SCOPE instruction set.

Such operations include PRPG, PSA, and binary count up (COUNT). Table 4 shows the test operations that

are decoded by the BCR.

During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is

reset to the binary value 010, which selects the PSA test operation. The BCR order of scan is shown in

Figure 3.

Bit 2

(MSB)

Bit 0

(LSB)

TDI

TDO

Bit 1

Figure 3. Boundary-Control Register Order of Scan

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT18245A, SN74ABT18245A

SCAN TEST DEVICES

WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUARY 1999

bypass register

The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path,

reducing the number of bits per test pattern that must be applied to complete a test operation. During

Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is shown in

Figure 4.

TDI

TDO

Bit 0

Figure 4. Bypass Register Order of Scan

device-identification register

The device-identification register (IDR) is 32 bits long. It can be selected and read to identify the manufacturer,

part number, and version of this device.

During Capture-DR, the binary value 00010000000000000101000000101111 (1000502F, hex) is captured in

the IDR to identify this device as Texas Instruments SN54/74ABT18245A. The IDR order of scan is from TDI

through bits 31–0 to TDO. Table 2 shows the IDR bits and their significance.

Table 2. Device-Identification Register Configuration

IDR BIT

NUMBER

IDENTIFICATION

SIGNIFICANCE

IDR BIT

NUMBER

IDENTIFICATION

SIGNIFICANCE

IDR BIT

NUMBER

IDENTIFICATION

SIGNIFICANCE

†

VERSION3

VERSION2

VERSION1

VERSION0

PARTNUMBER15

PARTNUMBER14

PARTNUMBER13

PARTNUMBER12

PARTNUMBER11

PARTNUMBER10

PARTNUMBER09

PARTNUMBER08

PARTNUMBER07

PARTNUMBER06

PARTNUMBER05

PARTNUMBER04

PARTNUMBER03

PARTNUMBER02

PARTNUMBER01

PARTNUMBER00

MANUFACTURER10

MANUFACTURER09

MANUFACTURER08

MANUFACTURER07

MANUFACTURER06

MANUFACTURER05

MANUFACTURER04

MANUFACTURER03

MANUFACTURER02

MANUFACTURER01

MANUFACTURER00

†

LOGIC1

†

Note that for TI products, bits 11–0 of the device-identification register always contain the binary value 000000101111

(02F, hex).

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT18245A, SN74ABT18245A

SCAN TEST DEVICES

WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUARY 1999

instruction-register opcode description

The instruction-register opcodes are shown in Table 3. The following descriptions detail the operation of each

instruction.

Table 3. Instruction-Register Opcodes

†

BINARY CODE

BIT 7 → BIT 0

MSB → LSB

SELECTED DATA

SCOPE OPCODE

DESCRIPTION

MODE

00000000

10000001

10000010

00000011

10000100

00000101

00000110

10000111

10001000

00001001

00001010

10001011

00001100

10001101

10001110

00001111

All others

EXTEST

IDCODE

Boundary scan

Identification read

Boundary scan

Device identification

Boundary scan

Bypass

Test

Normal

Modified test

Test

SAMPLE/PRELOAD

Sample boundary

‡

BYPASS

HIGHZ

Bypass scan

Bypass

Bypass scan

Bypass

Control boundary to high impedance

Control boundary to 1/0

Bypass scan

Bypass

CLAMP

Bypass

‡

BYPASS

Bypass

Normal

Test

RUNT

Boundary-run test

Bypass

READBN

READBT

CELLTST

TOPHIP

SCANCN

SCANCT

BYPASS

Boundary read

Boundary scan

Bypass

Normal

Test

Boundary read

Boundary self test

Boundary toggle outputs

Boundary-control register scan

Bypass scan

Normal

Test

Boundary control

Bypass

Normal

Test

Normal

†

‡

Bit 7 is used to maintain even parity in the 8-bit instruction.

The BYPASS instruction is executed in lieu of a SCOPE instruction that is not supported in the ’ABT18245A.

boundary scan

This instruction conforms to the IEEE Standard 1149.1-1990 EXTEST instruction. The BSR is selected in the

scan path. Data appearing at the device input and I/O pins is captured in the associated BSCs. Data that has

been scanned into the input BSCs is applied to the inputs of the normal on-chip logic, while data scanned into

the I/O BSCs for pins in the output mode is applied to the device I/O pins. Data present at the device I/O pins

is passed through the I/O BSCs to the normal on-chip logic. For I/O pins, the operation of a pin as input or output

is determined by the contents of the output-enable BSCs (bits 43–40 of the BSR). When a given output enable

is active (logic 1), the associated I/O pins operate in the output mode. Otherwise, the I/O pins operate in the

input mode. The device operates in the test mode.

identification read

This instruction conforms to the IEEE Standard 1149.1-1990 IDCODE instruction. The IDR is selected in the

scan path. The device operates in the normal mode.

sample boundary

This instruction conforms to the IEEE Standard 1149.1-1990 SAMPLE/PRELOAD instruction. The BSR is

selected in the scan path. Data appearing at the device input pins and I/O pins in the input mode is captured

in the associated BSCs, while data appearing at the outputs of the normal on-chip logic is captured in the BSCs

associated with I/O pins in the output mode. The device operates in the normal mode.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT18245A, SN74ABT18245A

SCAN TEST DEVICES

WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUARY 1999

bypass scan

This instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register is

selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device

operates in the normal mode.

control boundary to high impedance

This instruction conforms to the IEEE Standard 1149.1a-1993 HIGHZ instruction. The bypass register is

selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device

operates in a modified test mode in which all device I/O pins are placed in the high-impedance state, the device

input pins remain operational, and the normal on-chip logic function is performed.

control boundary to 1/0

This instruction conforms to the IEEE Standard 1149.1a-1993 CLAMP instruction. The bypass register is

selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the input

BSCs is applied to the inputs of the normal on-chip logic, while data in the I/O BSCs for pins in the output mode

is applied to the device I/O pins. The device operates in the test mode.

boundary-run test

The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during

Capture-DR. The device operates in the test mode. The test operation specified in the BCR is executed during

Run-Test/Idle. The five test operations decoded by the BCR are: sample inputs/toggle outputs (TOPSIP),

PRPG, PSA, simultaneous PSA and PRPG (PSA/PRPG), and simultaneous PSA and binary count up

(PSA/COUNT).

boundary read

The BSR is selected in the scan path. The value in the BSR remains unchanged during Capture-DR. This

instruction is useful for inspecting data after a PSA operation.

boundary self test

The BSR is selected in the scan path. All BSCs capture the inverse of their current values during Capture-DR.

In this way, the contents of the shadow latches can be read out to verify the integrity of both shift-register and

shadow-latch elements of the BSR. The device operates in the normal mode.

boundary toggle outputs

The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during

Capture-DR. Data in the shift-register elements of the selected output-mode BSCs is toggled on each rising

edge of TCK in Run-Test/Idle, updated in the shadow latches, and applied to the associated device I/O pins on

each falling edge of TCK in Run-Test/Idle. Data in the input-mode BSCs remains constant. Data appearing at

the device input or I/O pins is not captured in the input-mode BSCs. The device operates in the test mode.

boundary-control-register scan

The BCR is selected in the scan path. The value in the BCR remains unchanged during Capture-DR. This

operation must be performed before a boundary-run test operation to specify which test operation is to be

executed.

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boundary-control-register opcode description

TheBCRopcodesaredecodedfromBCRbits2–0asshowninTable4. Theselectedtestoperationisperformed

while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail the operation

of each BCR instruction and illustrate the associated PSA and PRPG algorithms.

Table 4. Boundary-Control Register Opcodes

BINARY CODE

BIT 2 → BIT 0

MSB → LSB

DESCRIPTION

X00

X01

X10

011

111

Sample inputs/toggle outputs (TOPSIP)

Pseudo-random pattern generation/36-bit mode (PRPG)

Parallel-signature analysis/36-bit mode (PSA)

Simultaneous PSA and PRPG/18-bit mode (PSA/PRPG)

Simultaneous PSA and binary count up/18-bit mode (PSA/COUNT)

While the control input BSCs (bits 43–36) are not included in the toggle, PSA, PRPG, or COUNT algorithms,

theoutput-enableBSCs(bits43–40oftheBSR)controlthedrivestate(activeorhighimpedance)oftheselected

device output pins. These BCR instructions are valid only when both bytes of the device are operating in one

direction of data flow (i.e., 1OEA ≠ 1OEB and 2OEA ≠ 2OEB) and in the same direction of data flow

(i.e.,1OEA = 2OEA and 1OEB = 2OEB). Otherwise, the bypass instruction is operated.

sample inputs/toggle outputs (TOPSIP)

Data appearing at the selected device input-mode I/O pins is captured in the shift-register elements of the

associated BSCs on each rising edge of TCK. Data in the shift-register elements of the selected output-mode

BSCs is toggled on each rising edge of TCK, updated in the shadow latches, and applied to the associated

device I/O pins on each falling edge of TCK.

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pseudo-random pattern generation (PRPG)

A pseudo-random pattern is generated in the shift-register elements of the selected BSCs on each rising edge

of TCK, updated in the shadow latches, and applied to the associated device output-mode I/O pins on each

falling edge of TCK. Figures 5 and 6 illustrate the 36-bit linear-feedback shift-register algorithms through which

the patterns are generated. An initial seed value should be scanned into the BSR before performing this

operation. A seed value of all zeroes does not produce additional patterns.

2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O

1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O

2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O

1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O

Figure 5. 36-Bit PRPG Configuration (1OEA = 2OEA = 0, 1OEB = 2OEB = 1)

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pseudo-random pattern generation (PRPG) (continued)

2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O

1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O

2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O

1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O

Figure 6. 36-Bit PRPG Configuration (1OEA = 2OEA = 1, 1OEB = 2OEB = 0)

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parallel-signature analysis (PSA)

Data appearing at the selected device input-mode I/O pins is compressed into a 36-bit parallel signature in the

shift-register elements of the selected BSCs on each rising edge of TCK. Data in the shadow latches of the

selected output-mode BSCs remains constant and is applied to the associated device I/O pins. Figures 7 and 8

illustrate the 36-bit linear-feedback shift-register algorithms through which the signature is generated. An initial

seed value should be scanned into the BSR before performing this operation.

2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O

1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O

2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O

1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O

Figure 7. 36-Bit PSA Configuration (1OEA = 2OEA = 0, 1OEB = 2OEB = 1)

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parallel-signature analysis (PSA) (continued)

2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O

1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O

2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O

1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O

Figure 8. 36-Bit PSA Configuration (1OEA = 2OEA = 1, 1OEB = 2OEB = 0)

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simultaneous PSA and PRPG (PSA/PRPG)

Data appearing at the selected device input-mode I/O pins is compressed into an 18-bit parallel signature in

the shift-register elements of the selected input-mode BSCs on each rising edge of TCK. At the same time, an

18-bit pseudo-random pattern is generated in the shift-register elements of the selected output-mode BSCs on

each rising edge of TCK, updated in the shadow latches, and applied to the associated device I/O pins on each

falling edge of TCK. Figures 9 and 10 illustrate the 18-bit linear-feedback shift-register algorithms through which

the signature and patterns are generated. An initial seed value should be scanned into the BSR before

performing this operation. A seed value of all zeroes does not produce additional patterns.

2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O

1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O

2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O

1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O

Figure 9. 18-Bit PSA/PRPG Configuration (1OEA = 2OEA = 0, 1OEB = 2OEB = 1)

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simultaneous PSA and PRPG (PSA/PRPG) (continued)

2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O

1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O

2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O

1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O

Figure 10. 18-Bit PSA/PRPG Configuration (1OEA = 2OEA = 1, 1OEB = 2OEB = 0)

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simultaneous PSA and binary count up (PSA/COUNT)

Data appearing at the selected device input-mode I/O pins is compressed into an 18-bit parallel signature in

the shift-register elements of the selected input-mode BSCs on each rising edge of TCK. At the same time, an

18-bit binary count-up pattern is generated in the shift-register elements of the selected output-mode BSCs on

each rising edge of TCK, updated in the shadow latches, and applied to the associated device I/O pins on each

falling edge of TCK. Figures 11 and 12 illustrate the 18-bit linear-feedback shift-register algorithms through

which the signature is generated. An initial seed value should be scanned into the BSR before performing this

operation.

2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O

1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O

MSB

2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O

LSB

1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O

Figure 11. 18-Bit PSA/COUNT Configuration (1OEA = 2OEA = 0, 1OEB = 2OEB = 1)

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simultaneous PSA and binary count up (PSA/COUNT) (continued)

2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O

1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O

MSB

2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O

LSB

1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O

Figure 12. 18-Bit PSA/COUNT Configuration (1OEA = 2OEA = 1, 1OEB = 2OEB = 0)

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timing description

All test operations of the ’ABT18245A are synchronous to TCK. Data on the TDI, TMS, and normal-function

inputs is captured on the rising edge of TCK. Data appears on the TDO and normal-function output pins on the

falling edge of TCK. The TAP controller is advanced through its states (as shown in Figure 1) by changing the

value of TMS on the falling edge of TCK and then applying a rising edge to TCK.

A simple timing example is shown in Figure 13. In this example, the TAP controller begins in the

Test-Logic-Reset state and is advanced through its states, as necessary, to perform one instruction-register

scan and one data-register scan. While in the Shift-IR and Shift-DR states, TDI is used to input serial data and

TDO is used to output serial data. The TAP controller is then returned to the Test-Logic-Reset state. Table 5

details the operation of the test circuitry during each TCK cycle.

Table 5. Explanation of Timing Example

TCK

CYCLE(S)

TAP STATE

AFTER TCK

DESCRIPTION

TMS is changed to a logic 0 value on the falling edge of TCK to begin advancing the TAP controller toward

the desired state.

Test-Logic-Reset

Run-Test/Idle

Select-DR-Scan

Select-IR-Scan

The IR captures the 8-bit binary value 10000001 on the rising edge of TCK as the TAP controller exits the

Capture-IR state.

Capture-IR

Shift-IR

TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP

on the rising edge of TCK as the TAP controller advances to the next state.

One bit is shifted into the IR on each TCK rising edge. With TDI held at a logic 1 value, the 8-bit binary value

11111111 is seriallyscannedintotheIR.Atthesametime,the8-bitbinaryvalue10000001isseriallyscanned

out of the IR via TDO. In TCK cycle 13, TMS is changed to a logic 1 value to end the IR scan on the next

TCK cycle. The last bit of the instruction is shifted as the TAP controller advances from Shift-IR to Exit1-IR.

7–13

Shift-IR

Exit1-IR

Update-IR

TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.

The IR is updated with the new instruction (BYPASS) on the falling edge of TCK.

Select-DR-Scan

The bypass register captures a logic 0 value on the rising edge of TCK as the TAP controller exits the

Capture-DR state.

Capture-DR

Shift-DR

TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP

on the rising edge of TCK as the TAP controller advances to the next state.

19–20

Shift-DR

Exit1-DR

The binary value 101 is shifted in via TDI, while the binary value 010 is shifted out via TDO.

TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.

The selected data register is updated with the new data on the falling edge of TCK.

Update-DR

Select-DR-Scan

Select-IR-Scan

Test-Logic-Reset

Test operation completed

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10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

TCK

TMS

TDI

TDO

TAP

Controller

State

3-State (TDO) or Don’t Care (TDI)

Figure 13. Timing Example

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V

Input voltage range, V (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V

Input voltage range, V (I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V

Voltage range applied to any output in the high state or power-off state, V

. . . . . . . . . . . . . . –0.5 V to 5.5 V

Current into any output in the low state, I : SN54ABT18245A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA

SN74ABT18245A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA

Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA

Output clamp current, I

(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA

Continuous current through V

Continuous current through GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1152 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 mA

Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W

DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings can be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

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recommended operating conditions (see Note 3)

SN54ABT18245A SN74ABT18245A

UNIT

MIN

4.5

MAX

MIN

4.5

MAX

Supply voltage

5.5

High-level input voltage

Low-level input voltage

Input voltage

0.8

High-level output current

Low-level output current

Input transition rise or fall rate

Operating free-air temperature

–24

–32

ns/V

°C

∆t/∆v

–55

125

–40

NOTE 3: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

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electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

= 25°C

SN54ABT18245A SN74ABT18245A

PARAMETER

TEST CONDITIONS

UNIT

†

MIN TYP

MAX

MIN

MAX

MIN

MAX

= 4.5 V,

= 5 V,

I = –18 mA

–1.2

= –3 mA

= –24 mA

= –32 mA

= 48 mA

= 64 mA

2.5

= 4.5 V,

0.55

0.55*

±1

0.55

= 4.5 V

0.55

±1

DIR, OE, TCK

±1

= 5.5 V,

µA

V = V

or GND

A or B ports

±100

= 5.5 V,

V = V

TDI, TMS

µA

= 5.5 V,

V = GND

TDI, TMS

–40

–150

–40

–150

–40

–150

‡

= 5.5 V,

= 2.7 V

µA

OZH

‡

= 5.5 V,

= 0.5 V

OE = 0.8 V

–50

OZL

= 0 to 2 V,

= 2.7 V or 0.5 V

±50

µA

OZPU

= 2 V to 0,

= 2.7 V or 0.5 V

±50

±100

±50

±450

±50

±100

µA

OZPD

= 0,

V or V ≤ 4.5 V

off

= 5.5 V,

= 5.5 V

Outputs high

= 2.5 V

CEX

= 5.5 V,

–50

–110

3.5

–200

–50

–200

–50

–200

Outputs high

Outputs low

= 5.5 V,

= 0,

A or

V = V

or GND ports

Outputs disabled

2.9

4.5

= 5.5 V,

One input at 3.4 V,

µA

∆I

Other inputs at V or GND

V = 2.5 V or 0.5 V

Control inputs

A or B ports

TDO

9.8

12.6

11.4

= 2.5 V or 0.5 V

* On products compliant to MIL-PRF-38535, this parameter does not apply.

†

‡

All typical values are at V

= 5 V.

and I

The parameters I

include the input leakage current.

OZH

OZL

Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

This is the increase in supply current for each input that is at the specified TTL voltage level rather than V

or GND.

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timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (test mode) (see Figure 14)

SN54ABT18245A SN74ABT18245A

UNIT

MIN

MAX

MIN

MAX

Clock frequency

Pulse duration

TCK

MHz

clock

TCK high or low

8.1

9.5

4.5

3.6

0.7

8.1

A, B, DIR, or OE before TCK↑

TDI before TCK↑

TMS before TCK↑

A, B, DIR, or OE after TCK↑

TDI after TCK↑

Setup time

Hold time

4.5

3.6

TMS after TCK↑

0.5

50*

0.5

Delay time

Rise time

Power up to TCK↑

power up

µs

* On products compliant to MIL-PRF-38535, these parameters are not production tested.

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (normal mode) (see Figure 14)

= 5 V,

= 25°C

SN54ABT18245A SN74ABT18245A

FROM

(INPUT)

(OUTPUT)

PARAMETER

UNIT

MIN

1.5

TYP

2.8

3.1

4.7

4.5

5.8

4.8

MAX

4.1

4.6

5.8

6.2

6.8

MIN

1.5

MAX

5.1

5.8

8.1

8.5

9.5

8.5

MIN

1.5

MAX

4.8

5.4

7.5

PLH

PHL

PZH

PZL

PHZ

PLZ

A or B

B or A

2.5

8.5

7.5

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (test mode) (see Figure 14)

= 5 V,

= 25°C

SN54ABT18245A SN74ABT18245A

FROM

(INPUT)

(OUTPUT)

PARAMETER

UNIT

MIN

TYP

MAX

MIN

2.8

MAX

MIN

MAX

TCK↓

MHz

max

PLH

PHL

PLH

PHL

PZH

PZL

PZH

PZL

PHZ

PLZ

PHZ

PLZ

7.1

10.1

13.8

6.4

13.1

12.8

6.1

A or B

TDO

3.4

3.9

7.5

7.6

3.8

TCK↓

5.6

6.5

10.6

10.5

5.5

14.1

14.3

13.4

13.6

6.6

A or B

TDO

2.5

3.5

2.5

5.7

2.3

2.9

2.5

7.3

14.4

13.8

7.5

6.7

2.5

3.5

2.5

6.9

7.7

7.1

3.9

3.5

10.8

10.1

5.7

13.6

12.7

7.2

A or B

TDO

1.5

5.4

1.5

6.3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT18245A, SN74ABT18245A

SCAN TEST DEVICES

WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUARY 1999

PARAMETER MEASUREMENT INFORMATION

7 V

Open

TEST

500 Ω

From Output

Under Test

Open

7 V

PLH PHL

GND

PLZ PZL

t /t

PHZ PZH

Open

= 50 pF

500 Ω

(see Note A)

3 V

0 V

LOAD CIRCUIT

1.5 V

Timing Input

Data Input

3 V

0 V

3 V

Input

1.5 V

0 V

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

3 V

0 V

3 V

0 V

Input

Output

Control

1.5 V

PLZ

PLH

PHL

PZL

Output

Waveform 1

S1 at 7 V

3.5 V

1.5 V

Output

+ 0.3 V

(see Note B)

PHL

PLH

PZH

PHZ

Output

Waveform 2

S1 at Open

(see Note B)

– 0.3 V

1.5 V

0 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

NOTES: A.

C includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

Figure 14. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

25-Sep-2013

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

5962-9460102QXA

ACTIVE

CFP

TBD

A42

N / A for Pkg Type

-55 to 125

5962-9460102QX

SNJ54ABT18245A

74ABT18245ADGGRE4

74ABT18245ADGGRG4

SN74ABT18245ADGGR

SN74ABT18245ADL

ACTIVE

TSSOP

SSOP

CFP

DGG

2000

Green (RoHS

& no Sb/Br)

CU NIPDAU

A42

Level-1-260C-UNLIM

N / A for Pkg Type

-40 to 85

-55 to 125

ABT18245A

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

SN74ABT18245ADLG4

SN74ABT18245ADLR

SN74ABT18245ADLRG4

SNJ54ABT18245AWD

Green (RoHS

& no Sb/Br)

1000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

TBD

5962-9460102QX

SNJ54ABT18245A

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

25-Sep-2013

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54ABT18245A, SN74ABT18245A :

Catalog: SN74ABT18245A

•

Military: SN54ABT18245A

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Military - QML certified for Military and Defense Applications

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Jan-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

SN74ABT18245ADGGR TSSOP

SN74ABT18245ADLR SSOP

DGG

2000

1000

330.0

24.4

32.4

8.6

15.6

1.8

3.1

12.0

16.0

24.0

32.0

11.35 18.67

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Jan-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

SN74ABT18245ADGGR

SN74ABT18245ADLR

TSSOP

SSOP

DGG

2000

1000

367.0

45.0

55.0

Pack Materials-Page 2

MECHANICAL DATA

MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997

WD (R-GDFP-F**)

CERAMIC DUAL FLATPACK

48 LEADS SHOWN

0.120 (3,05)

0.075 (1,91)

0.009 (0,23)

0.004 (0,10)

1.130 (28,70)

0.870 (22,10)

0.370 (9,40)

0.250 (6,35)

0.390 (9,91)

0.370 (9,40)

0.250 (6,35)

0.025 (0,635)

0.014 (0,36)

0.008 (0,20)

NO. OF

LEADS**

0.740

0.640

(16,26) (18,80)

A MAX

A MIN

0.610 0.710

(15,49) (18,03)

4040176/D 10/97

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

D. Index point is provided on cap for terminal identification only

E. Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO-146AA

GDFP1-F56 and JEDEC MO-146AB

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998

DGG (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0,27

0,17

0,08

0,50

6,20

6,00

8,30

7,90

0,15 NOM

Gage Plane

0,25

0°–8°

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

DIM

A MAX

12,60

12,40

14,10

13,90

17,10

16,90

A MIN

4040078/F 12/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

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TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the

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Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered

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No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

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non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

SNJ54ABT18245AWDR [TI]

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