SNJ54ACT534FK [TI]

ACT SERIES, 8-BIT DRIVER, INVERTED OUTPUT, CQCC20, CERAMIC, LCC-20;


型号：	SNJ54ACT534FK
厂家：	TEXAS INSTRUMENTS
描述：	ACT SERIES, 8-BIT DRIVER, INVERTED OUTPUT, CQCC20, CERAMIC, LCC-20 驱动输出元件逻辑集成电路触发器
文件：	总8页 (文件大小：186K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

54ACT534

54ACT534 Octal D Flip-Flop with TRI-STATE Outputs

Literature Number: SNOS108

July 1998

54ACT534

Octal D Flip-Flop with TRI-STATE^®Outputs

n Edge-triggered D-type inputs

n Buffered positive edge-triggered clock

n TRI-STATE outputs for bus-oriented applications

n Outputs source/sink 24 mA

n ’ACT534 has TTL-compatible inputs

n Inverted output version of ’ACT374

n Standard Microcircuit Drawing (SMD) 5962-8965801

General Description

The ’ACT534 is

a high-speed, low-power octal D-type

flip-flop featuring separate D-type inputs for each flip-flop

and TRI-STATE outputs for bus-oriented applications. A buff-

ered Clock (CP) and Output Enable (OE) are common to all

flip-flops. The ’ACT534 is the same as the ’ACT374 except

that the outputs are inverted.

Features

n I_CCand I_OZreduced by 50%

Logic Symbols

IEEE/IEC

DS100292-1

DS100292-2

Pin Names

D₀–D₇

Description

Data Inputs

Clock Pulse Input

TRI-STATE Output Enable Input

Complementary TRI-STATE Outputs

O₀–O₇

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

™

FACT is a trademark of Fairchild Semiconductor Corporation.

DS100292

www.national.com

Connection Diagrams

Pin Assignment

for DIP and Flatpak

Pin Assignment

for LCC

DS100292-4

DS100292-3

Functional Description

The ’ACT534 consists of eight edge-triggered flip-flops with

individual D-type inputs and TRI-STATE complementary out-

puts. The buffered clock and buffered Output Enable are

common to all flip-flops. The eight flip-flops will store the

state of their individual D inputs that meet the setup and hold

times requirements on the LOW-to-HIGH Clock (CP) transi-

tion. With the Output Enable (OE) LOW, the contents of the

eight flip-flops are available at the outputs. When the OE is

HIGH, the outputs go to the high impedance state. Operation

of the OE input does not affect the state of the flip-flops.

Logic Diagram

DS100292-5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Function Table

Inputs

Output

O₀

HIGH Voltage Level

LOW Voltage Level

Immaterial

N =

LOW-to-HIGH Clock Transition

High Impedance

Value stored from previous clock cycle

www.national.com

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Junction Temperature (T_J)

CDIP

175˚C

Recommended Operating

Conditions

Supply Voltage (V_CC

)

−0.5V to +7.0V

DC Input Diode Current (I_IK

)

Supply Voltage (V_CC

)

V_I−0.5V

−20 mA

+20 mA

’ACT

4.5V to 5.5V

0V to V_CC

V_IV_CC+ 0.5V

Input Voltage (V_I)

DC Input Voltage (V_I)

−0.5V to V_CC+ 0.5V

Output Voltage (V_O

)

DC Output Diode Current (I_OK

)

Operating Temperature (T_A)

54ACT

V_O−0.5V

−20 mA

+20 mA

−55˚C to +125˚C

V_OV_CC+ 0.5V

Minimum Input Edge Rate (∆V/∆t)

’ACT Devices

DC Output Voltage (V_O

DC Output Source

)

−0.5V to V_CC+ 0.5V

V_INfrom 0.8V to 2.0V

or Sink Current (I_O

)

50 mA

V_CC4.5V, 5.5V

125 mV/ns

DC V_CCor Ground Current

per Output Pin (I_CCor I_GND

Note 1: Absolute maximum ratings are those values beyond which damage

to the device may occur. The databook specifications should be met, without

exception, to ensure that the system design is reliable over its power supply,

temperature, and output/input loading variables. National does not recom-

)

50 mA

Storage Temperature (T_STG

)

−65˚C to +150˚C

™

mend operation of FACT circuits outside databook specifications.

DC Characteristics for ’ACT Family Devices

54ACT

Symbol

Parameter

V_CC

(V)

T_A

Units

Conditions

−55˚C to +125˚C

Guaranteed Limits

V_IH

V_IL

Minimum High Level

Input Voltage

4.5

5.5

4.5

5.5

4.5

5.5

2.0

0.8

4.4

5.4

V_OUT0.1V

or V_CC− 0.1V

Maximum Low Level

Input Voltage

V_OUT0.1V

or V_CC− 0.1V

V_OH

Minimum High Level

Output Voltage

I_OUT−50 µA

(Note 2)

V_INV_ILor V_IH

4.5

5.5

4.5

5.5

3.70

4.70

0.1

I_OH= −24 mA

V_OL

Maximum Low Level

Output Voltage

I_OUT50 µA

0.1

(Note 2)

V_INV_ILor V_IH

4.5

5.5

0.50

I_OL= 24 mA

I_IN

Maximum Input Leakage

Current

1.0

µA

V_IV_CC, GND

I_OZ

Maximum TRI-STATE

Current

5.5

5.0

V_IV_IL, V_IH

V_OV_CC, GND

V_IV_CC− 2.1V

I_CCT

I_OLD

I_OHD

I_CC

Maximum I_CC/Input

Minimum Dynamic

Output Current (Note 3)

Maximum Quiescent

Supply Current

5.5

1.6

µA

V_OLD1.65V Max

V_OHD3.85V Min

−50

80.0

V_INV_CC

or GND

Note 2: All outputs loaded; thresholds on input associated with output under test.

Note 3: Maximum test duration 2.0 ms, one output loaded at a time.

@ @

I for 54ACT 25˚C is identical to 74ACT 25˚C.

Note 4:

www.national.com

AC Electrical Characteristics

54ACT

V_CC

(V)

T_A−55˚C

Fig.

No.

Symbol

Parameter

to +125˚C

Units

(Note 5)

C_L50 pF

Min

Max

f_max

Maximum Clock

5.0

MHz

Frequency

t_PLH

Propagation Delay

CP to Q_n

1.5

14.0

13.0

t_PHL

Propagation Delay

CP to Q_n

t_PZH

t_PZL

t_PHZ

t_PLZ

Output Enable Time

Output Disable Time

5.0

1.5

14.0

13.0

14.5

11.5

Note 5: Voltage Range 5.0 is 5.0V 0.5V

AC Operating Requirements

54ACT

V_CC

(V)

T_A−55˚C

Fig.

No.

Symbol

Parameter

to +125˚C

Units

C_L50 pF

(Note 6)

Guaranteed Minimum

t_s

Setup Time, HIGH or LOW

D_nto CP

5.0

t_h

Hold Time, HIGH or LOW

D_nto CP

3.0

5.0

t_w

CP Pulse Width

HIGH or LOW

Note 6: Voltage Range 5.0 is 5.0V 0.5V

Capacitance

Symbol

Parameter

Input Capacitance

Power Dissipation

Capacitance

Typ

4.5

Units

Conditions

V_CCOPEN

C_IN

V_CC5.0V

C_PD

40.0

www.national.com

Physical Dimensions inches (millimeters) unless otherwise noted

20 Terminal Ceramic Leadless Chip Carrier (L)

NS Package Number E20A

16 Lead Ceramic Dual-In-Line Package (D)

NS Package Number J16A

www.national.com

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16 Lead Ceramic Flatpak (F)

NS Package Number W16A

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VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-

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1. Life support devices or systems are devices or sys-

tems which, (a) are intended for surgical implant into

the body, or (b) support or sustain life, and whose fail-

ure to perform when properly used in accordance

with instructions for use provided in the labeling, can

be reasonably expected to result in a significant injury

to the user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

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Tel: 1-800-272-9959

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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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SNJ54ACT534FK [TI]

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