SNJ54ALS191AW [TI]
同步 4 位加/减二进制计数器 | W | 16 | -55 to 125;
| 型号： | SNJ54ALS191AW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 同步 4 位加/减二进制计数器 | W | 16 | -55 to 125 计数器 |
| 文件： | 总8页 (文件大小：135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ALS191A, SN74ALS191A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDAS210C – DECEMBER 1982 – REVISED JULY 1996
SN54ALS191A . . . J PACKAGE
SN74ALS191A . . . D OR N PACKAGE
Single Down/Up Count-Control Line
Look-Ahead Circuitry Enhances Speed of
Cascaded Counters
(TOP VIEW)
Fully Synchronous in Count Modes
B
V
A
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC
Q
Q
Asynchronously Presettable With Load
Control
B
A
CLK
RCO
MAX/MIN
LOAD
C
CTEN
D/U
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
Q
C
Q
D
GND
D
description
SN54ALS191A . . . FK PACKAGE
(TOP VIEW)
The ’ALS191A are synchronous 4-bit reversible
up/down binary counters. Synchronous counting
operation is provided by having all flip-flops
clocked simultaneously so that the outputs
change coincidentally with each other when
instructed by the steering logic. This mode of
operation eliminates the output counting spikes
3
2
1
20 19
18
CLK
Q
4
5
6
7
8
A
RCO
CTEN
NC
17
16
15
14
NC
normally
associated
with
asynchronous
MAX/MIN
LOAD
D/U
(ripple-clock) counters.
Q
C
The outputs of the four flip-flops are triggered on
a low-to-high-level transition of the clock (CLK)
input if the count enable (CTEN) input is low. A
high at CTEN inhibits counting. The direction of
the count is determined by the level of the
down/up (D/U) input. When D/Uislow, thecounter
counts up, and when D/U is high, the counter
counts down.
9 10 11 12 13
NC – No internal connection
These counters feature a fully independent clock circuit. Changes at the control inputs (CTEN and D/U) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter is dictated solely by the conditions meeting the stable setup and hold times.
These counters are fully programmable. Each output can be preset to either level by placing a low on the LOAD
input and entering the desired data at the data inputs. The output changes to agree with the data inputs
independently of the level of the clock input. This feature allows the counters to be used as modulo-N dividers
by simply modifying the count length with the preset inputs.
CLK, D/U, and LOAD are buffered to lower the drive requirement, which significantly reduces the loading on
(current required by) clock drivers, for long parallel words.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS191A, SN74ALS191A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDAS210C – DECEMBER 1982 – REVISED JULY 1996
description (continued)
Two outputs are available to perform the cascading function: ripple clock and maximum/minimum count. The
latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of
the clock while the count is minimum (0) counting down or maximum (15) counting up. The ripple-clock output
(RCO) produces a low-level output pulse under those same conditions, but only while the clock input is low. The
counter easily can be cascaded by feeding the ripple-clock output to the enable input of the succeeding counter
if parallel clocking is used, or to the clock input if parallel enabling is used. The maximum/minimum count
(MAX/MIN) output can be used to accomplish look ahead for high-speed operation.
The SN54ALS191A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ALS191A is characterized for operation from 0°C to 70°C.
†
logic symbol
4
CTRDIV16
CTEN
D/U
G1
12
13
5
2(CT=0)Z6
MAX/MIN
RCO
M2 [DOWN]
M3 [UP]
3(CT=15)Z6
14
CLK
1,2– / 1,3+
G4
6,1,4
11
LOAD
C5
15
1
3
2
[1]
Q
A
A
B
C
D
5D
[2]
[4]
[8]
Q
B
10
9
6
7
Q
Q
C
D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS191A, SN74ALS191A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDAS210C – DECEMBER 1982 – REVISED JULY 1996
logic diagram (positive logic)
12
13
MAX/
MIN
4
CTEN
RCO
5
D/U
14
CLK
11
LOAD
15
A
3
S
Q
A
C1
1D
R
1
B
2
S
Q
B
C1
1D
R
10
C
6
S
Q
C
C1
1D
R
9
D
7
Q
D
S
C1
1D
R
Pin numbers shown are for the D, J, and N packages.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS191A, SN74ALS191A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDAS210C – DECEMBER 1982 – REVISED JULY 1996
typical load, count, and inhibit sequences
The following sequence is illustrated below:
1. Load (preset) to binary 13
2. Count up to 14, 15 (maximum), 0, 1, and 2
3. Inhibit
4. Count down to 1, 0 (minimum), 15, 14, and 13
LOAD
A
B
Data
Inputs
C
D
CLK
D/U
CTEN
Q
Q
Q
Q
A
B
C
D
MAX/MIN
RCO
13
14
15
0
1
2
2
2
1
0
15
14
13
Count Up
Inhibit
Count Down
Load
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS191A, SN74ALS191A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDAS210C – DECEMBER 1982 – REVISED JULY 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Operating free-air temperature range, T : SN54ALS191A . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
A
SN74ALS191A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54ALS191A
MIN NOM MAX
SN74ALS191A
MIN NOM MAX
UNIT
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Clock frequency
IH
0.7
–0.4
4
0.8
–0.4
8
V
IL
I
I
f
mA
mA
MHz
OH
OL
clock
0
20
25
25
45
30
20
5
20
0
16.5
20
20
20
20
20
5
30
CLK high or low
t
w
Pulse duration
ns
LOAD low
Data before LOAD↑
CTEN before CLK↑
D/U before CLK↑
LOAD inactive before CLK↑
Data after LOAD↑
CTEN after CLK↑
D/U after CLK↑
t
su
Setup time
ns
t
h
Hold time
0
0
ns
0
0
T
A
Operating free-air temperature
–55
125
0
70
°C
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS191A, SN74ALS191A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDAS210C – DECEMBER 1982 – REVISED JULY 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS191A
SN74ALS191A
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 4.5 V,
I = –18 mA
–1.5
–1.5
V
IK
CC
I
= 4.5 V to 5.5 V,
I
I
I
= –0.4 mA
= 4 mA
V
CC
– 2
V
CC
– 2
OH
CC
OH
OL
OL
0.25
0.4
0.25
0.35
0.4
0.5
V
V
OL
V
CC
= 4.5 V
= 8 mA
I
I
V
V
= 5.5 V,
= 5.5 V,
V = 7 V
0.2
20
0.1
mA
I
CC
I
V = 2.7 V
I
20
µA
IH
IL
CC
CTEN or CLK
All others
–0.2
–0.2
–112
22
–0.2
–0.1
– 112
22
I
V
CC
= 5.5 V,
V = 0.4 V
I
mA
‡
I
I
V
V
= 5.5 V,
= 5.5 V,
V = 2.25 V
O
–20
–30
mA
mA
O
CC
All inputs at 0
12
12
CC
CC
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
switching characteristics (see Figure 1)
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
= 500 Ω,
FROM
TO
(OUTPUT)
§
PARAMETER
(OUTPUT)
UNIT
T
A
= MIN to MAX
SN54ALS191A SN74ALS191A
MIN
20
7
MAX
MIN
30
7
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
37
34
25
25
24
25
26
22
37
34
45
36
35
30
21
23
30
30
21
21
20
20
18
18
31
31
37
28
25
25
18
18
Any Q
Any Q
LOAD
A, B, C, D
CLK
8
8
3
3
ns
ns
ns
ns
ns
ns
ns
4
4
5
5
RCO
5
5
3
3
CLK
Any Q
3
3
8
8
CLK
MAX/MIN
8
8
8
8
D/U
D/U
RCO
10
8
10
8
MAX/MIN
8
8
4
4
CTEN
RCO
4
4
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS191A, SN74ALS191A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDAS210C – DECEMBER 1982 – REVISED JULY 1996
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7 V
R
= R1 = R2
V
CC
L
S1
R1
R
L
Test
Point
From Output
Under Test
From Output
Under Test
Test
Point
Test
Point
From Output
Under Test
C
C
L
R
L
R2
L
C
L
(see Note A)
(see Note A)
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
3.5 V
Timing
Input
High-Level
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
0.3 V
t
h
t
w
t
su
3.5 V
3.5 V
0.3 V
Data
Input
Low-Level
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
0.3 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
3.5 V
t
PZL
Input
1.3 V
1.3 V
t
PLZ
0.3 V
PHL
3.5 V
t
Waveform 1
S1 Closed
(see Note B)
t
PLH
1.3 V
V
OH
In-Phase
Output
1.3 V
1.3 V
1.3 V
V
OL
0.3 V
V
OL
t
PHZ
t
PLH
t
PZH
t
PHL
V
OH
V
Waveform 2
S1 Open
(see Note B)
OH
OL
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
0.3 V
V
0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%.
r
f
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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