SNJ54ALS323W [TI]
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS;
| 型号： | SNJ54ALS323W |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS 输入元件 输出元件 逻辑集成电路 触发器 |
| 文件： | 总13页 (文件大小：391K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SDAS267A − DECEMBER 1982 − REVISED DECEMBER 1994
SN54ALS323 . . . J PACKAGE
SN74ALS323 . . . DW OR N PACKAGE
(TOP VIEW)
• Multiplexed I/O Ports Provide Improved Bit
Density
• Four Modes of Operation:
− Hold (Store)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
S0
OE1
OE2
V
CC
− Shift Right
− Shift Left
− Load Data
S1
SL
Q
G/Q
G
H′
• Operate With Outputs Enabled or at High
E/Q
H/Q
E
H
Impedance
C/Q
F/Q
C
F
• 3-State Outputs Drive Bus Lines Directly
• Can Be Cascaded for n-Bit Word Lengths
• Synchronous Clear
A/Q
Q
D/Q
B/Q
A
D
A′
B
CLR
GND
CLK
SR
• Applications:
− Stacked or Push-Down Registers
− Buffer Storage
SN54ALS323 . . . FK PACKAGE
(TOP VIEW)
− Accumulator Registers
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) 300-mil DIPs
3
2
1
20 19
18
4
5
6
7
8
G/Q
SL
Q
G
17
16
15
14
E/Q
E
H′
description
C/Q
H/Q
C
H
F
A/Q
Q
F/Q
A
These 8-bit universal shift/storage registers
feature multiplexed input/output (I/O) ports to
achieve full 8-bit data handling in a 20-pin
package. Two function-select (S0, S1) inputs and
two output-enable (OE1, OE2) inputs can be used
to choose the modes of operation listed in the
function table.
D/Q
A′
D
9 10 11 12 13
Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs
in the high-impedance state and permits data applied on the I/O ports to be clocked into the register. Reading
out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs
synchronously when the clear (CLR) input is low. Taking either OE1 or OE2 high disables the outputs but has
no effect on clearing, shifting, or storing data.
The SN54ALS323 is characterized for operation over the full military temperature range of −55°C to 125°C. The
SN74ALS323 is characterized for operation from 0°C to 70°C.
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Copyright 1994, Texas Instruments Incorporated
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ꢥ ꢩ ꢦ ꢥꢞ ꢟꢳ ꢡꢠ ꢤ ꢬꢬ ꢪꢤ ꢢ ꢤ ꢣ ꢩ ꢥ ꢩ ꢢ ꢦ ꢮ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢀꢆ ꢇ ꢆꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅ ꢀꢆ ꢇ ꢆ
ꢋ ꢌꢍ ꢎ ꢏ ꢉꢐ ꢁ ꢎ ꢑꢒ ꢓꢀ ꢄꢅꢉ ꢀ ꢔꢎ ꢕꢏ ꢖ ꢀꢏꢗ ꢓꢄꢘ ꢒ ꢉꢓꢒ ꢘ ꢎꢀꢏ ꢒꢓ ꢀ
ꢙꢎ ꢏ ꢔ ꢉꢀ ꢚꢁ ꢛꢔ ꢓꢗꢁ ꢗꢐ ꢀ ꢉꢛ ꢅ ꢒꢄ ꢓꢉꢄꢁ ꢜꢉꢆ ꢌꢀ ꢏꢄꢏ ꢒꢉ ꢗꢐ ꢏꢝ ꢐꢏꢀ
SDAS267A − DECEMBER 1982 − REVISED DECEMBER 1994
FUNCTION TABLE
INPUTS
MODE
I/O PORTS
OUTPUTS
†
†
OE2
CLR S1 S0 OE1
CLK SL SR A/Q
B/Q
C/Q
D/Q
E/Q
F/Q
G/Q
H/Q
Q
Q
A
B
C
D
E
F
G
H
A′
H′
L
L
L
X
L
H
L
X
H
L
L
X
L
L
X
↑
↑
↑
X
X
X
X
X
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
L
L
L
L
Clear
Hold
H
H
L
X
L
X
L
L
L
L
X
L
X
X
X
X
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
A0
A0
B0
B0
C0
C0
D0
D0
E0
E0
F0
F0
G0
G0
H0
H0
A0
A0
H0
H0
Shift
Right
H
H
L
L
H
H
L
L
L
L
↑
↑
X
X
H
L
H
L
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
H
L
Q
Q
An
An
Bn
Bn
Cn
Cn
Dn
Dn
En
En
Fn
Fn
Gn
Gn
Gn
Gn
Shift
Left
H
H
H
H
L
L
L
L
L
L
↑
↑
H
L
X
X
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
H
L
Q
Q
H
L
Bn
Bn
Cn
Cn
Dn
Dn
En
En
Fn
Fn
Gn
Gn
Hn
Hn
Bn
Bn
Load
H
H
H
X
X
↑
X
X
a
b
c
d
e
f
g
h
a
h
NOTE: a . . . h = the level of the steady-state input at inputs A through H, respectively. This data is loaded into the flip-flops while the flip-flop outputs
are isolated from the I/O terminals.
†
When one or both output-enable inputs are high, the eight I/O terminals are disabled to the high-impedance state; however, sequential operation
or clearing of the register is not affected.
‡
logic symbol
9
2
3
SRG8
4R
&
CLR
OE1
OE2
S0
3EN13
0
1
0
1
19
12
M
3
S1
CLK
C4/1→/2←
11
7
8
SR
1,4D
3,4D
5, 13
3, 4D
6, 13
Q
A′
A/Q
B/Q
A
Z5
Z6
13
B
6
C/Q
D/Q
C
D
14
5
E/Q
E
15
4
F/Q
F
G/Q
G
16
H/Q
3, 4D
12, 13
2, 4D
H
Z12
17
18
SL
Q
H′
‡
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SDAS267A − DECEMBER 1982 − REVISED DECEMBER 1994
logic diagram (positive logic)
9
CLR
1
S0
19
S1
18
SL
(shift left
serial input)
11
SR
(shift right
serial input)
Six
Identical
Channels
Not
†
Shown
12
CLK
1D
C1
1D
C1
17
8
Q
Q
A′
H′
2
OE1
3
OE2
7
16
H/Q
A/Q
A
H
†
I/O ports not shown: B/Q (13), C/Q (6), D/Q (14), E/Q (5), F/Q (15), and G/Q (4).
B
C
D
E
F
G
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V : All inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range, T : SN54ALS323 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
A
SN74ALS323 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢀꢆ ꢇ ꢆꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅ ꢀꢆ ꢇ ꢆ
ꢋ ꢌꢍ ꢎ ꢏ ꢉꢐ ꢁ ꢎ ꢑꢒ ꢓꢀ ꢄꢅꢉ ꢀ ꢔꢎ ꢕꢏ ꢖ ꢀꢏꢗ ꢓꢄꢘ ꢒ ꢉꢓꢒ ꢘ ꢎꢀꢏ ꢒꢓ ꢀ
ꢙꢎ ꢏ ꢔ ꢉꢀ ꢚꢁ ꢛꢔ ꢓꢗꢁ ꢗꢐ ꢀ ꢉꢛ ꢅ ꢒꢄ ꢓꢉꢄꢁ ꢜꢉꢆ ꢌꢀ ꢏꢄꢏ ꢒꢉ ꢗꢐ ꢏꢝ ꢐꢏꢀ
SDAS267A − DECEMBER 1982 − REVISED DECEMBER 1994
recommended operating conditions
SN54ALS323
SN74ALS323
MIN NOM MAX
UNIT
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
0.7
−0.4
−1
0.8
−0.4
−2.6
8
Q
Q
Q
Q
or Q
H′
A′
A
I
High-level output current
mA
OH
OL
thru Q
H
or Q
4
A′
A
H′
I
Low-level output current
mA
thru Q
12
24
H
T
A
Operating free-air temperature
−55
125
0
70
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS323
SN74ALS323
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 4.5 V,
I = −18 mA
−1.5
−1.5
V
IK
CC
I
Any output
= 4.5 V to 5.5 V,
I
I
I
I
I
I
I
= − 0.4 mA
= − 1 mA
= − 2.6 mA
= 4 mA
V
−2
CC
2.4
V
−2
CC
OH
OH
OH
OL
OL
OL
OL
CC
3.3
0.25
0.25
V
OH
Q
Q
Q
thru Q
V
CC
V
CC
V
CC
= 4.5 V
= 4.5 V
= 4.5 V
A
H
2.4
3.2
0.25
0.35
0.25
0.35
0.4
0.4
0.4
0.5
or Q
A′
A
H′
= 8 mA
V
OL
V
= 12 mA
= 24 mA
0.4
thru Q
H
0.5
A thru H
V = 5.5 V
0.1
0.1
0.1
I
I
I
I
V
V
= 5.5 V
= 5.5 V,
mA
I
CC
Any others
V = 7 V
I
0.1
‡
V = 2.7 V
I
20
20
µA
CC
IH
S0, S1, SR, SL
Any others
−0.2
−0.1
−70
−112
28
−0.2
−0.1
−70
−112
28
‡
V
= 5.5 V,
= 5.5 V,
V = 0.4 V
I
mA
mA
IL
CC
CC
Q
Q
or Q
H′
thru Q
−15
−20
−15
−30
A′
§
V
V
O
= 2.25 V
I
I
OS
A
H
Outputs high
Outputs low
15
22
23
15
22
23
38
38
V
CC
= 5.5 V
mA
CC
Outputs disabled
40
40
†
‡
§
All typical values are at V
CC
= 5 V, T = 25°C.
A
For I/O ports (Q thru Q ), the parameters I and I include the off-state output current.
A
H
IH IL
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SDAS267A − DECEMBER 1982 − REVISED DECEMBER 1994
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
SN54ALS323 SN74ALS323
UNIT
MIN
0
MAX
MIN
0
MAX
f
t
Clock frequency (at 50% duty cycle)
Pulse duration
17
17
MHz
ns
clock
CLK high or low
S0 or S1
22
25
18
15
25
18
0
16.5
20
16
6
w
High
Low
Serial or parallel data
Setup time before CLK↑
t
su
ns
ns
20
16
0
CLR active
CLR
†
Inactive-state setup time before CLK↑
S0 or S1
Hold time after CLK↑
t
h
0
0
Serial or parallel data
†
Inactive-state setup time is also referred to as recovery time.
switching characteristics (see Figure 1)
V
C
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
R1 = 500 Ω,
R2 = 500 Ω,
T
A
FROM
TO
(OUTPUT)
PARAMETER
(INPUT)
UNIT
‡
= MIN to MAX
SN54ALS323 SN74ALS323
MIN
17
2
MAX
MIN
17
4
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PLH
PHL
PZH
PZL
PZH
PZL
PHZ
PLZ
PHZ
PLZ
19
25
21
25
22
27
27
27
15
38
16
34
13
19
15
18
16
22
17
22
8
CLK
CLK
Q
thru Q
or Q
A
H
4
7
2
5
Q
ns
ns
ns
ns
ns
A′
H′
4
8
5
6
OE1, OE2
S0, S1
Q
Q
Q
Q
thru Q
A
H
H
H
H
6
8
5
7
thru Q
thru Q
thru Q
A
A
A
6
8
1
1
OE1, OE2
S0, S1
4
5
15
12
25
1
1
4
8
‡
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢀꢆ ꢇ ꢆꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅ ꢀꢆ ꢇ ꢆ
ꢋ ꢌꢍ ꢎ ꢏ ꢉꢐ ꢁ ꢎ ꢑꢒ ꢓꢀ ꢄꢅꢉ ꢀ ꢔꢎ ꢕꢏ ꢖ ꢀꢏꢗ ꢓꢄꢘ ꢒ ꢉꢓꢒ ꢘ ꢎꢀꢏ ꢒꢓ ꢀ
ꢙꢎ ꢏ ꢔ ꢉꢀ ꢚꢁ ꢛꢔ ꢓꢗꢁ ꢗꢐ ꢀ ꢉꢛ ꢅ ꢒꢄ ꢓꢉꢄꢁ ꢜꢉꢆ ꢌꢀ ꢏꢄꢏ ꢒꢉ ꢗꢐ ꢏꢝ ꢐꢏꢀ
SDAS267A − DECEMBER 1982 − REVISED DECEMBER 1994
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7 V
R
= R1 = R2
V
CC
L
S1
R1
R
L
Test
Point
From Output
Under Test
From Output
Under Test
Test
Point
Test
Point
From Output
Under Test
C
C
L
R
L
R2
L
C
L
(see Note A)
(see Note A)
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
3.5 V
Timing
Input
High-Level
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
0.3 V
t
t
w
h
t
su
3.5 V
3.5 V
0.3 V
Data
Input
Low-Level
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
0.3 V
3.5 V
t
PZL
Input
1.3 V
1.3 V
t
PLZ
0.3 V
PHL
[3.5 V
t
Waveform 1
S1 Closed
(see Note B)
t
PLH
1.3 V
V
OH
In-Phase
Output
1.3 V
1.3 V
1.3 V
V
OL
V
OL
0.3 V
t
PHZ
t
PLH
t
PZH
t
PHL
V
OH
V
Waveform 2
S1 Open
(see Note B)
OH
OL
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
0.3 V
V
[0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%.
r
f
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
83021022A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
83021022A
SNJ54ALS
323FK
8302102RA
8302102SA
ACTIVE
ACTIVE
ACTIVE
CDIP
CFP
J
20
20
20
1
1
TBD
TBD
A42
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
0 to 70
8302102RA
SNJ54ALS323J
W
N
Call TI
8302102SA
SNJ54ALS323W
SN74ALS323N
PDIP
20
Pb-Free
(RoHS)
CU NIPDAU
SN74ALS323N
SN74ALS323N3
SN74ALS323NE4
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
20
20
TBD
Call TI
Call TI
0 to 70
0 to 70
20
1
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74ALS323N
SNJ54ALS323FK
ACTIVE
LCCC
FK
20
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
83021022A
SNJ54ALS
323FK
SNJ54ALS323J
SNJ54ALS323W
ACTIVE
ACTIVE
CDIP
CFP
J
20
20
1
1
TBD
TBD
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
8302102RA
SNJ54ALS323J
W
Call TI
8302102SA
SNJ54ALS323W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54ALS323, SN74ALS323 :
Catalog: SN74ALS323
•
Military: SN54ALS323
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 2
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