SNJ54ALS996W [TI]
8-Bit D-type Edge-Triggered Read-Back Latches 24-CFP -55 to 125;
| 型号： | SNJ54ALS996W |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-Bit D-type Edge-Triggered Read-Back Latches 24-CFP -55 to 125 驱动 输入元件 逻辑集成电路 |
| 文件： | 总19页 (文件大小：692K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄꢅ ꢀ ꢆꢆ ꢇ ꢈ ꢉꢀ ꢁꢊꢃ ꢄꢅ ꢀꢆ ꢆꢇ
ꢉ ꢋ ꢌꢍꢎ ꢏꢉ ꢐꢌꢏ ꢑꢒꢓ ꢉꢓ ꢐꢔ ꢓꢌꢏ ꢕꢎ ꢔꢔ ꢓꢕ ꢓꢐꢉꢕ ꢓꢄꢐꢌꢍ ꢄꢖꢗꢉꢅ ꢄꢏꢖ ꢘ ꢓꢀ
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SDAS098B − OCTOBER 1984 − REVISED JANUARY 1995
SN54ALS996 . . . JT PACKAGE
SN74ALS996 . . . DW OR NT PACKAGE
(TOP VIEW)
• 3-State I/O-Type Read-Back Inputs
• Bus-Structured Pinout
• T/C Determines True or Complementary
Data at Q Outputs
1D
2D
3D
4D
5D
6D
7D
8D
EN
V
CC
1
2
3
4
5
6
7
8
9
24
23 1Q
22 2Q
21 3Q
20 4Q
19 5Q
18 6Q
17 7Q
16 8Q
15 OE
14 T/C
13 CLR
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
(NT) and Ceramic (JT) 300-mil DIPs
description
These 8-bit latches are designed specifically for
storing the contents of the input data bus and
providing the capability of reading back the stored
data onto the input data bus. The Q outputs are
designed with bus-driving capability.
RD 10
CLK 11
GND 12
The edge-triggered flip-flops enter the data on the
low-to-high transition of the clock (CLK) input
when the enable (EN) input is low. Data can be
read back onto the data inputs by taking the read
(RD) input low, in addition to having EN low. When
EN is high, both the read-back and write modes
are disabled. Transitions on EN should only be
made with CLK high to prevent false clocking.
SN54ALS996 . . . FK PACKAGE
(TOP VIEW)
4
3
2
1
28 27 26
25
4D
5D
6D
NC
7D
8D
EN
3Q
4Q
5Q
NC
6Q
7Q
8Q
5
24
23
22
21
20
19
6
7
The polarity of the Q outputs can be controlled by
the polarity (T/C) input. When T/C is high, Q is the
same as is stored in the flip-flops. When T/C is low,
the output data is inverted. The Q outputs can be
placed in the high-impedance state by taking the
output-enable (OE) input high. OE does not affect
the internal operation of the register. Old data can
be retained or new data can be entered while the
outputs are off.
8
9
10
11
12 13 14 15 16 17 18
NC − No internal connection
A low level at the clear (CLR) input resets the
internal registers low. The clear function is
asynchronous and overrides all other register
functions.
The -1 version of the SN74ALS996 is identical to the standard version, except that the recommended maximum
for the -1 version is increased to 48 mA. There is no -1 version of the SN54ALS996.
I
OL
The SN54ALS996 is characterized for operation over the full military temperature range of −55°C to 125°C. The
SN74ALS996 is characterized for operation from 0°C to 70°C.
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Copyright 1995, Texas Instruments Incorporated
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2−1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢀꢆ ꢆ ꢇꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅ ꢀꢆ ꢆ ꢇ
ꢉ ꢋ ꢌꢍꢎ ꢏ ꢉ ꢐ ꢌꢏ ꢑꢒ ꢓ ꢉ ꢓꢐ ꢔꢓ ꢌꢏ ꢕꢎ ꢔꢔ ꢓ ꢕꢓ ꢐꢉ ꢕ ꢓꢄꢐꢌꢍ ꢄꢖꢗꢉ ꢅꢄꢏ ꢖꢘꢓꢀ
ꢙ
SDAS098B − OCTOBER 1984 − REVISED JANUARY 1995
†
logic symbol
15
OE
EN4
N3
14
T/C
13
R
&
CLR
10
RD
9
EN2
EN
≥ 1
C1
11
CLK
1
1D
1D
2
23
3,4
1Q
2
2D
3
22
21
20
19
18
17
16
2Q
3Q
4Q
5Q
6Q
7Q
8Q
3D
4
4D
5
5D
6
6D
7
7D
8
8D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.
logic diagram (positive logic)
15
OE
14
T/C
13
CLR
10
RD
9
EN
11
CLK
1
1D
C1
1D
23
1Q
R
To Seven Other Channels
Pin numbers shown are for the DW, JT, and NT packages.
2−2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢀ ꢆꢆ ꢇ ꢈ ꢉꢀ ꢁꢊ ꢃꢄ ꢅꢀ ꢆꢆ ꢇ
ꢉ ꢋ ꢌꢍꢎ ꢏꢉ ꢐꢌꢏ ꢑꢒꢓ ꢉꢓ ꢐꢔ ꢓꢌꢏ ꢕꢎ ꢔꢔ ꢓꢕ ꢓꢐꢉꢕ ꢓꢄꢐꢌꢍ ꢄꢖꢗꢉ ꢅꢄꢏꢖ ꢘ ꢓꢀ
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SDAS098B − OCTOBER 1984 − REVISED JANUARY 1995
timing diagram
(T/C = H)
CLR
D
Input Data
Read-Back Data
t
su
t
h
t
w
CLK
EN
t
en
t
dis
t
su
†
t
h
t
t
en
dis
RD
Q
t
p
Output
Output Data
t
t
dis
en
OE
Async
Clear
Write
Read
Back
†
This hold time ensures that the read-back circuit will not create a conflict on the input data bus.
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V (OE, RD, EN, CLK, CLR, and T/C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Voltage applied to D inputs and to disabled 3-state outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range, T : SN54ALS996 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
A
SN74ALS996 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2−3
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢀꢆ ꢆ ꢇꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅ ꢀꢆ ꢆ ꢇ
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SDAS098B − OCTOBER 1984 − REVISED JANUARY 1995
recommended operating conditions
SN54ALS996
SN74ALS996
MIN NOM MAX
UNIT
MIN NOM
MAX
V
CC
Supply voltage
4.5
5
5.5
4.5
2
5
5.5
V
All inputs
All inputs except OE, RD
OE, RD
2
V
V
High-level input voltage
V
IH
2.2
Low-level input voltage
High-level output current
0.8
−1
0.8
−2.6
−0.4
24
V
IL
Q
D
I
mA
OH
−0.4
12
Q
D
†
48
I
f
Low-level output current
Clock frequency
mA
OL
8
8
0
10
35
0
10
14.5
14.5
15
10
15
10
0
35
MHZ
clock
CLR low
CLK low
14.5
14.5
15
t
w
t
su
t
h
Pulse duration
ns
CLK high
Data before CLK↑
EN low before CLK↑
10
Setup time
ns
‡
CLK high before EN↑
15
CLR high (inactive) before CLK↑
Data after CLK↑
10
1
EN low after CLK↑
5
5
Hold time
ns
§
RD high after CLK↑
5
5
T
A
Operating free-air temperature
−55
125
0
70
°C
†
‡
§
Applies only to the -1 version and only if V
CC
This setup time ensures that EN will not false clock the data register.
This hold time ensures that there will be no conflict on the input data bus.
is maintained between 4.75 V and 5.25 V
2−4
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢉ ꢋ ꢌꢍꢎ ꢏꢉ ꢐꢌꢏ ꢑꢒꢓ ꢉꢓ ꢐꢔ ꢓꢌꢏ ꢕꢎ ꢔꢔ ꢓꢕ ꢓꢐꢉꢕ ꢓꢄꢐꢌꢍ ꢄꢖꢗꢉ ꢅꢄꢏꢖ ꢘ ꢓꢀ
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SDAS098B − OCTOBER 1984 − REVISED JANUARY 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS996
SN74ALS996
PARAMETER
TEST CONDITIONS
I = −18 mA
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 4.5 V,
−1.2
−1.2
V
IK
CC
I
All outputs
Q
= 4.5 V to 5.5 V,
I
I
I
I
I
I
I
I
= − 0.4 mA
= − 1 mA
= − 2.6 mA
= 4 mA
V
−2
V
−2
CC
OH
OH
OH
OL
OL
OL
OL
OL
CC
2.4
CC
3.2
0.25
0.25
V
V
OH
V
= 4.5 V
= 4.5 V
CC
CC
2.4
3.2
0.4
0.4
D
Q
V
= 8 mA
0.35
0.25
0.35
0.35
0.5
0.4
0.5
0.5
20
= 12 mA
= 24 mA
V
OL
V
= 4.5 V
CC
‡
= 48 mA
= 2.7 V
= 0.4 V
I
I
Q
V
V
= 5.5 V,
= 5.5 V,
V
V
20
−20
0.1
µA
µA
OZH
CC
O
Q
−20
0.1
0.1
20
OZL
CC
O
D inputs
All others
V = 5.5 V
I
I
I
V
V
= 5.5 V
= 5.5 V,
mA
CC
V = 7 V
I
0.1
§
D inputs
All others
20
I
V = 2.7 V
I
µA
IH
IL
CC
20
20
§
D inputs
−0.1
−0.1
−0.1
−0.1
I
V
V
= 5.5 V,
= 5.5 V,
V = 0.4 V
I
mA
mA
CC
All others
V
O
= 2.25 V
CC
¶
−20
−112
−30
−112
I
O
CLR = 2.5 V
Outputs high
Outputs low
35
55
42
55
85
65
35
55
42
55
85
65
V
= 5.5 V,
CC
EN, RD low
I
mA
CC
Outputs disabled
†
All typical values are at V
= 5 V, T = 25°C.
A
CC
‡
§
¶
Applies only to the -1 version and only if V
is maintained between 4.75 V and 5.25 V
For I/O ports (Q thru Q ), the parameters I and I include the off-state output current.
CC
IH
A
H
IL
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
2−5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢉ ꢋ ꢌꢍꢎ ꢏ ꢉ ꢐ ꢌꢏ ꢑꢒ ꢓ ꢉ ꢓꢐ ꢔꢓ ꢌꢏ ꢕꢎ ꢔꢔ ꢓ ꢕꢓ ꢐꢉ ꢕ ꢓꢄꢐꢌꢍ ꢄꢖꢗꢉ ꢅꢄꢏ ꢖꢘꢓꢀ
ꢙ
SDAS098B − OCTOBER 1984 − REVISED JANUARY 1995
switching characteristics (see Figure 1)
V
C
T
A
= 4.5 V to 5.5 V,
= 50 pF,
= MIN to MAX
CC
L
†
FROM
TO
(OUTPUT)
PARAMETER
(INPUT)
UNIT
SN54ALS996 SN74ALS996
MIN
35
5
MAX
MIN
35
5
MAX
f
t
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PHL
30
24
27
23
23
23
30
28
28
27
23
23
23
30
CLK
(T/C = H or L)
Q
Q
5
5
CLR (T/C = L)
CLR (T/C = H)
5
7
ns
5
7
4
5
ns
ns
T/C
Q
D
5
5
CLR
5
8
‡
2
1
2
1
2
1
18
19
17
19
15
11
3
3
3
3
4
1
16
19
16
19
15
10
t
t
t
t
t
t
en
ns
ns
ns
RD
EN
OE
D
D
Q
§
dis
‡
en
§
dis
‡
en
§
dis
†
‡
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
t
= t
or t
en PZH PZL
t = t
dis PHZ
or t
PLZ
2−6
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢙ
SDAS098B − OCTOBER 1984 − REVISED JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
7 V
7 V
S1
S1
500 Ω
1 kΩ
Test
Point
Test
Point
From Output
Under Test
From Output
Under Test
C
C
L
L
1 kΩ
500 Ω
(see Note A)
(see Note A)
LOAD CIRCUIT FOR Q OUTPUTS
LOAD CIRCUIT FOR D OUTPUTS
3.5 V
0.3 V
3.5 V
Timing
Input
High-Level
Pulse
1.3 V
1.3 V
1.3 V
0.3 V
t
t
w
h
t
su
3.5 V
0.3 V
3.5 V
0.3 V
Data
Input
Low-Level
Pulse
1.3 V
1.3 V
1.3 V
1.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
Output
Control
1.3 V
1.3 V
(low-level
enabling)
0.3 V
3.5 V
t
PZL
Input
1.3 V
1.3 V
t
PLZ
0.3 V
PHL
[3.5 V
t
Waveform 1
S1 Closed
(see Note C)
t
PLH
1.3 V
V
OH
In-Phase
Output
1.3 V
1.3 V
1.3 V
V
OL
V
OL
0.3 V
t
PHZ
t
PLH
t
PZH
t
PHL
V
OH
V
OH
OL
Waveform 2
S1 Open
(see Note C)
Out-of-Phase
Output
1.3 V
1.3 V
0.3 V
V
(see Note B)
[0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. C includes probe and jig capacitance.
L
B. When measuring propagation delay times of 3-state outputs, switch S1 is open.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%.
r
f
Figure 1. Load Circuits and Voltage Waveforms
2−7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
2−8
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
5962-89945013A
ACTIVE
LCCC
FK
28
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
5962-
89945013A
SNJ54ALS
996FK
5962-8994501LA
ACTIVE
CDIP
JT
24
1
TBD
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8994501LA
SNJ54ALS996JT
SN74ALS996-1DWR
SN74ALS996-1NT
OBSOLETE
ACTIVE
SOIC
PDIP
DW
NT
24
24
Call TI
Call TI
0 to 70
0 to 70
15
15
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74ALS996-1NT
SN74ALS996-1NT
ALS996
SN74ALS996-1NTE4
SN74ALS996DW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
NT
DW
DW
DW
DW
DW
NT
24
24
24
24
24
24
24
Pb-Free
(RoHS)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
25
Green (RoHS
& no Sb/Br)
SN74ALS996DWG4
SN74ALS996DWR
SN74ALS996DWRE4
SN74ALS996DWRG4
SN74ALS996NT
25
Green (RoHS
& no Sb/Br)
ALS996
2000
2000
2000
15
Green (RoHS
& no Sb/Br)
ALS996
Green (RoHS
& no Sb/Br)
ALS996
Green (RoHS
& no Sb/Br)
ALS996
Pb-Free
(RoHS)
SN74ALS996NT
SN74ALS996NT3
SN74ALS996NTE4
OBSOLETE
ACTIVE
PDIP
PDIP
NT
NT
24
24
TBD
Call TI
Call TI
0 to 70
0 to 70
15
1
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74ALS996NT
SNJ54ALS996FK
ACTIVE
LCCC
FK
28
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
5962-
89945013A
SNJ54ALS
996FK
SNJ54ALS996JT
SNJ54ALS996W
ACTIVE
CDIP
CFP
JT
W
24
24
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
5962-8994501LA
SNJ54ALS996JT
OBSOLETE
5962-8994501KA
SNJ54ALS996W
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54ALS996, SN74ALS996 :
Catalog: SN74ALS996
•
Military: SN54ALS996
•
NOTE: Qualified Version Definitions:
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Catalog - TI's standard catalog product
•
•
Military - QML certified for Military and Defense Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74ALS996DWR
SOIC
DW
24
2000
330.0
24.4
10.75 15.7
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 24
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
SN74ALS996DWR
2000
Pack Materials-Page 2
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUARY 1997
JT (R-GDIP-T**)
CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
PINS **
A
24
28
DIM
13
24
1.280
(32,51) (37,08)
1.460
A MAX
1.240
(31,50) (36,58)
1.440
B
A MIN
B MAX
B MIN
0.300
(7,62)
0.291
(7,39)
1
12
0.070 (1,78)
0.030 (0,76)
0.245
(6,22)
0.285
(7,24)
0.320 (8,13)
0.290 (7,37)
0.015 (0,38) MIN
0.100 (2,54) MAX
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.014 (0,36)
0.008 (0,20)
0.100 (2,54)
4040110/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MCFP007 – OCTOBER 1994
W (R-GDFP-F24)
CERAMIC DUAL FLATPACK
0.375 (9,53)
0.340 (8,64)
Base and Seating Plane
0.006 (0,15)
0.004 (0,10)
0.045 (1,14)
0.026 (0,66)
0.090 (2,29)
0.045 (1,14)
0.395 (10,03)
0.360 (9,14)
0.360 (9,14)
0.240 (6,10)
0.360 (9,14)
0.240 (6,10)
0.019 (0,48)
0.015 (0,38)
1
24
0.050 (1,27)
0.640 (16,26)
0.490 (12,45)
0.030 (0,76)
0.015 (0,38)
12
13
30° TYP
1.115 (28,32)
0.840 (21,34)
4040180-5/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD
E. Index point is provided on cap for terminal identification only.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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