SNJ54BCT541FK [TI]

OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS; 八路缓冲器/驱动器,具有三态输出
SNJ54BCT541FK
型号: SNJ54BCT541FK
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
八路缓冲器/驱动器,具有三态输出

驱动器 输出元件
文件: 总15页 (文件大小:530K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
SN54BCT541, SN74BCT541A  
OCTAL BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCBS011E – JULY 1988 – REVISED MARCH 2003  
Operating Voltage Range of 4.5 V to 5.5 V  
State-of-the-Art BiCMOS Design  
P-N-P Inputs Reduce DC Loading  
Data Flow-Through Pinout (All Inputs on  
Opposite Side From Outputs)  
Significantly Reduces I  
CCZ  
3-State Outputs Drive Bus Lines or Buffer  
Memory Address Registers  
SN54BCT541 . . . J OR W PACKAGE  
SN74BCT541A . . . DW, N, OR NS PACKAGE  
(TOP VIEW)  
SN54BCT541 . . . FK PACKAGE  
(TOP VIEW)  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE1  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
V
CC  
3
2
1
20 19  
18  
OE2  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
Y7  
Y8  
Y1  
Y2  
A3  
A4  
A5  
A6  
A7  
4
5
6
7
8
17  
16 Y3  
15  
Y4  
Y5  
14  
9 10 11 12 13  
GND  
description/ordering information  
The SN54BCT541 and SN74BCT541A octal buffers and line drivers are ideal for driving bus lines or buffering  
memory-address registers. The devices feature inputs and outputs on opposite sides of the package to facilitate  
printed-circuit-board layout.  
The3-statecontrolgateisa2-inputANDgatewithactive-lowinputssothat, ifeitheroutput-enable(OE1orOE2)  
input is high, all eight outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP – N  
Tube  
SN74BCT541AN  
SN74BCT541ADW  
SN74BCT541ADWR  
SN74BCT541ANSR  
SNJ54BCT541J  
SN74BCT541AN  
Tube  
0°C to 70°C  
SOIC – DW  
BCT541A  
Tape and reel  
Tape and reel  
Tube  
SOP – NS  
CDIP – J  
BCT541A  
SNJ54BCT541J  
SNJ54BCT541W  
SNJ54BCT541FK  
–55°C to 125°C  
CFP – W  
LCCC – FK  
Tube  
SNJ54BCT541W  
SNJ54BCT541FK  
Tube  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54BCT541, SN74BCT541A  
OCTAL BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCBS011E JULY 1988 REVISED MARCH 2003  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Y
OE1  
L
OE2  
L
A
L
L
H
Z
Z
L
L
H
X
X
H
X
X
H
logic diagram (positive logic)  
1
OE1  
OE2  
19  
2
18  
A1  
Y1  
To Seven Other Channels  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V  
CC  
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V  
I
Voltage range applied to any output in the disabled or power-off state, V . . . . . . . . . . . . . . . . 0.5 V to 5.5 V  
O
Voltage range applied to any output in the high state, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to V  
O
CC  
Current into any output in the low state: SN54BCT541 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA  
SN74BCT541A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA  
Package thermal impedance, θ (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W  
JA  
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W  
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W  
Storage temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C  
stg  
Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditionsis not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
2. The package thermal impedance is calculated in accordance with JESD 51-7.  
recommended operating conditions (see Note 3)  
SN54BCT541  
MIN NOM MAX  
SN74BCT541A  
UNIT  
MIN NOM  
MAX  
V
V
V
Supply voltage  
4.5  
2
5
5.5  
4.5  
2
5
5.5  
V
V
CC  
IH  
IL  
High-level input voltage  
Low-level input voltage  
Input clamp current  
0.8  
18  
12  
48  
0.8  
18  
15  
64  
V
I
I
I
mA  
mA  
mA  
°C  
IK  
High-level output current  
Low-level output current  
Operating free-air temperature  
OH  
OL  
T
A
55  
125  
0
70  
NOTE 3: All unused inputs of the device must be held at V  
or GND to ensure proper device operation. Refer to the TI application report,  
CC  
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54BCT541, SN74BCT541A  
OCTAL BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCBS011E JULY 1988 REVISED MARCH 2003  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
SN54BCT541  
SN74BCT541A  
PARAMETER  
TEST CONDITIONS  
UNIT  
MIN TYP  
MAX  
MIN TYP  
MAX  
V
V
V
= 4.5 V,  
= 4.5 V  
I = 18 mA  
1.2  
1.2  
V
IK  
CC  
I
I
I
I
I
I
= 3 mA  
= 12 mA  
= 15 mA  
= 48 mA  
= 64 mA  
2.4  
2
3.3  
3.2  
2.4  
2
3.3  
3.1  
OH  
OH  
OH  
OL  
OL  
V
OH  
V
CC  
0.38  
0.55  
V
V
CC  
= 4.5 V  
V
OL  
0.42  
0.55  
0.1  
20  
I
I
I
I
I
I
I
I
I
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
= 5.5 V,  
= 5.5 V,  
= 5.5 V,  
= 5.5 V,  
= 5.5 V,  
= 5.5 V,  
= 5.5 V  
= 5.5 V  
= 5.5 V  
= 5 V,  
V = 7 V  
I
0.1  
20  
mA  
µA  
I
V = 2.7 V  
I
IH  
V = 0.5 V  
I
0.6  
50  
0.6  
50  
mA  
µA  
IL  
V
O
V
O
V
O
= 2.7 V  
= 0.5 V  
= 0  
OZH  
OZL  
50  
225  
40  
50  
225  
40  
µA  
100  
100  
mA  
mA  
mA  
mA  
pF  
OS  
27  
47  
5
27  
47  
5
CCH  
CCL  
CCZ  
72  
72  
7
7
C
C
V = 2.5 V or 0.5 V  
I
5
5
i
= 5 V,  
V
O
= 2.5 V or 0.5 V  
10  
10  
pF  
o
All typical values are at V  
= 5 V, T = 25°C.  
A
CC  
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.  
switching characteristics (see Figure 1)  
V
C
= 5 V,  
= 50 pF,  
V
C
= 4.5 V to 5.5 V,  
CC  
L
CC  
L
= 50 pF,  
R1 = 500 ,  
R2 = 500 ,  
T
A
R1 = 500 ,  
R2 = 500 ,  
§
T = MIN to MAX  
A
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
UNIT  
= 25°C  
BCT541  
TYP  
3.7  
SN54BCT541 SN74BCT541A  
MIN  
2.1  
3.7  
4.5  
5
MAX  
5.3  
MIN  
1.7  
3.2  
4.4  
5.4  
3
MAX  
6.3  
MIN  
1.7  
3.4  
3.9  
4.4  
3
MAX  
6
t
t
t
t
t
t
PLH  
PHL  
PZH  
PZL  
PHZ  
PLZ  
A
Y
Y
Y
ns  
ns  
ns  
5.5  
7.5  
8.7  
8.2  
7.2  
9.3  
11  
10.7  
11.5  
8.6  
OE  
OE  
8
10.4  
7.6  
12.4  
9.1  
3.5  
3.4  
5.6  
5.2  
7.2  
3
9.4  
3
8.6  
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.  
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54BCT541, SN74BCT541A  
OCTAL BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCBS011E JULY 1988 REVISED MARCH 2003  
PARAMETER MEASUREMENT INFORMATION  
7 V (t  
, t  
, O.C.)  
PZL PLZ  
Open  
(all others)  
S1  
From Output  
Under Test  
Test  
Point  
C
L
R1  
R1  
(see Note A)  
From Output  
Under Test  
Test  
Point  
C
L
R2  
(see Note A)  
LOAD CIRCUIT FOR  
TOTEM-POLE OUTPUTS  
R
= R1 = R2  
L
LOAD CIRCUIT FOR  
3-STATE AND OPEN-COLLECTOR OUTPUTS  
High-Level  
Pulse  
(see Note B)  
3 V  
0 V  
1.5 V  
1.5 V  
3 V  
Timing Input  
(see Note B)  
1.5 V  
t
w
0 V  
3 V  
0 V  
3 V  
0 V  
t
h
Low-Level  
Pulse  
t
1.5 V  
su  
1.5 V  
Data Input  
(see Note B)  
1.5 V  
1.5 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
3 V  
0 V  
Output  
Control  
(low-level enable)  
3 V  
1.5 V  
1.5 V  
Input  
(see Note B)  
1.5 V  
1.5 V  
0 V  
PHL  
t
t
PZL  
t
t
PLZ  
t
PLH  
3.5 V  
In-Phase  
Output  
(see Note D)  
V
OH  
1.5 V  
Waveform 1  
(see Notes C and D)  
1.5 V  
1.5 V  
1.5 V  
t
V
OL  
V
OL  
0.3 V  
t
PHZ  
PLH  
t
PHL  
PZH  
V
OH  
V
OH  
Out-of-Phase  
Output  
(see Note D)  
Waveform 2  
(see Notes C and D)  
1.5 V  
1.5 V  
0.3 V  
0 V  
V
OL  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES (see Note D)  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS  
NOTES: A.  
C includes probe and jig capacitance.  
L
B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, t = t 2.5 ns, duty cycle = 50%.  
r
f
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.  
D. The outputs are measured one at a time with one transition per measurement.  
E. When measuring propagation delay times of 3-state outputs, switch S1 is open.  
F. All parameters and waveforms are not applicable to all devices.  
Figure 1. Load Circuit and Voltage Waveforms  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-May-2007  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
LCCC  
CDIP  
CFP  
Drawing  
5962-9074901M2A  
5962-9074901MRA  
5962-9074901MSA  
SN74BCT541ADW  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
FK  
J
20  
20  
20  
20  
1
1
1
TBD  
TBD  
TBD  
POST-PLATE N / A for Pkg Type  
A42 SNPB  
A42  
N / A for Pkg Type  
N / A for Pkg Type  
W
SOIC  
DW  
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74BCT541ADWE4  
SN74BCT541ADWG4  
SN74BCT541ADWR  
SN74BCT541ADWRE4  
SN74BCT541ADWRG4  
SN74BCT541AN  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
PDIP  
PDIP  
SO  
DW  
DW  
DW  
DW  
DW  
N
20  
20  
20  
20  
20  
20  
20  
20  
20  
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
20  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
SN74BCT541ANE4  
SN74BCT541ANSR  
SN74BCT541ANSRE4  
N
20  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
NS  
NS  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SO  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SNJ54BCT541FK  
SNJ54BCT541J  
SNJ54BCT541W  
ACTIVE  
ACTIVE  
ACTIVE  
LCCC  
CDIP  
CFP  
FK  
J
20  
20  
20  
1
1
1
TBD  
TBD  
TBD  
POST-PLATE N / A for Pkg Type  
A42 SNPB  
A42  
N / A for Pkg Type  
N / A for Pkg Type  
W
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-May-2007  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
19-May-2007  
TAPE AND REEL INFORMATION  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
19-May-2007  
Device  
Package Pins  
Site  
Reel  
Reel  
A0 (mm)  
B0 (mm)  
K0 (mm)  
P1  
W
Pin1  
Diameter Width  
(mm) (mm) Quadrant  
(mm)  
330  
(mm)  
24  
SN74BCT541ADWR  
SN74BCT541ANSR  
DW  
NS  
20  
20  
MLA  
MLA  
10.8  
8.2  
13.0  
13.0  
2.7  
2.5  
12  
12  
24  
24  
Q1  
Q1  
330  
24  
TAPE AND REEL BOX INFORMATION  
Device  
Package  
Pins  
Site  
Length (mm) Width (mm) Height (mm)  
SN74BCT541ADWR  
SN74BCT541ANSR  
DW  
NS  
20  
20  
MLA  
MLA  
333.2  
333.2  
333.2  
333.2  
31.75  
31.75  
Pack Materials-Page 2  
MECHANICAL DATA  
MLCC006B – OCTOBER 1996  
FK (S-CQCC-N**)  
LEADLESS CERAMIC CHIP CARRIER  
28 TERMINAL SHOWN  
A
B
NO. OF  
TERMINALS  
**  
18 17 16 15 14 13 12  
MIN  
MAX  
MIN  
MAX  
0.342  
(8,69)  
0.358  
(9,09)  
0.307  
(7,80)  
0.358  
(9,09)  
19  
20  
11  
10  
9
20  
28  
44  
52  
68  
84  
0.442  
(11,23)  
0.458  
(11,63)  
0.406  
(10,31)  
0.458  
(11,63)  
21  
B SQ  
22  
0.640  
(16,26)  
0.660  
(16,76)  
0.495  
(12,58)  
0.560  
(14,22)  
8
A SQ  
23  
0.739  
(18,78)  
0.761  
(19,32)  
0.495  
(12,58)  
0.560  
(14,22)  
7
24  
25  
6
0.938  
(23,83)  
0.962  
(24,43)  
0.850  
(21,6)  
0.858  
(21,8)  
5
1.141  
(28,99)  
1.165  
(29,59)  
1.047  
(26,6)  
1.063  
(27,0)  
26 27 28  
1
2
3
4
0.080 (2,03)  
0.064 (1,63)  
0.020 (0,51)  
0.010 (0,25)  
0.020 (0,51)  
0.010 (0,25)  
0.055 (1,40)  
0.045 (1,14)  
0.045 (1,14)  
0.035 (0,89)  
0.045 (1,14)  
0.035 (0,89)  
0.028 (0,71)  
0.022 (0,54)  
0.050 (1,27)  
4040140/D 10/96  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. This package can be hermetically sealed with a metal lid.  
D. The terminals are gold plated.  
E. Falls within JEDEC MS-004  
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