SNJ54BCT646FK_技术文档

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ꢊ ꢅꢆꢋꢌ ꢄꢍꢀ ꢆ ꢎꢋꢁꢀ ꢅꢏꢐ ꢑꢏꢎꢀ ꢋꢁꢒ ꢎꢏꢓ ꢐ ꢀ ꢆꢏ ꢎ

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ꢔ ꢐꢆ ꢕ ꢖ ꢗꢀꢆꢋꢆ ꢏ ꢊ ꢍꢆ ꢘꢍ ꢆ

SCBS037D − AUGUST 1989 − REVISED MAY 2004

D

State-of-the-Art BiCMOS Design

Significantly Reduces I

D

Multiplexed Real-Time and Stored Data

CCZ

D

ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

D

Bus Transceivers/Registers

D

Independent Registers and Enables for

A and B Buses

SN54BCT646 . . . JT OR W PACKAGE

SN74BCT646 . . . DW OR NT PACKAGE

(TOP VIEW)

SN54BCT646 . . . FK PACKAGE

(TOP VIEW)

CLKAB

SAB

DIR

A1

A2

A3

A4

A5

A6

A7

A8

GND

V

CC

1

24

23

22

21

20

19

18

17

16

15

14

13

CLKBA

SBA

OE

B1

B2

B3

B4

B5

B6

B7

2

3

4

3

2

1 28 27 26

25

A1

A2

A3

NC

A4

A5

A6

OE

B1

B2

NC

B3

B4

B5

5

4

24

23

22

21

20

19

6

5

7

6

8

7

9

8

10

11

9

10

11

12

12 13 14 15 16 17 18

B8

NC − No internal connection

description/ordering information

These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed

transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked

into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1

illustrates the four fundamental bus-management functions that can be performed with the ’BCT646 devices.

Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the

transceiver mode, data present at the high-impedance port can be stored in either register or in both.

The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The

direction control (DIR) determines which bus will receive data when OE is low. In the isolation mode (OE high),

A data can be stored in one register and/or B data can be stored in the other register.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

T

A

PDIP − NT

SOIC − DW

Tube

SN74BCT646NT

SN74BCT646DW

SN74BCT646DWR

SNJ54BCT646JT

SNJ54BCT646W

SNJ54BCT646FK

SN74BCT646NT

Tube

0°C to 70°C

BCT646

Tape and reel

Tube

CDIP − JT

CFP − W

SNJ54BCT646JT

SNJ54BCT646W

SNJ54BCT646FK

−55°C to 125°C

Tube

LCCC − FK

Tube

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Copyright  2004, Texas Instruments Incorporated

ꢊ ꢚ ꢥ ꢝ ꢜꢨ ꢣꢢ ꢠꢡ ꢢꢜ ꢞꢥ ꢧꢙ ꢟꢚ ꢠ ꢠꢜ ꢯꢐ ꢌꢗ ꢘꢎ ꢰ ꢗꢖꢱꢂ ꢖꢂꢈ ꢟꢧꢧ ꢥꢟ ꢝ ꢟ ꢞꢤ ꢠꢤꢝ ꢡ ꢟ ꢝ ꢤ ꢠꢤ ꢡꢠꢤ ꢨ

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢃ ꢇꢈ ꢀꢁꢉ ꢃ ꢄꢅ ꢆꢇ ꢃ ꢇ

ꢊꢅ ꢆꢋ ꢌ ꢄ ꢍ ꢀ ꢆ ꢎ ꢋꢁ ꢀꢅ ꢏꢐ ꢑ ꢏ ꢎꢀ ꢋꢁ ꢒ ꢎꢏ ꢓ ꢐꢀ ꢆꢏ ꢎꢀ

ꢔꢐ ꢆ ꢕ ꢖ ꢗꢀꢆꢋꢆ ꢏ ꢊꢍꢆ ꢘ ꢍꢆꢀ

SCBS037D − AUGUST 1989 − REVISED MAY 2004

description/ordering information(continued)

When an output function is disabled, the input function still is enabled and can be used to store and transmit

data. Only one of the two buses, A or B, can be driven at a time.

To ensure the high-impedance state during power up or power down, OE should be tied to V

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

through a pullup

CC

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCBS037D − AUGUST 1989 − REVISED MAY 2004

21

OE

L

3

1

23

2

22

SBA

21

OE

L

3

DIR

1

23

2

22

SBA

DIR CLKAB CLKBA SAB

CLKAB CLKBA SAB

L

X

L

H

X

L

X

REAL-TIME TRANSFER

BUS B TO BUS A

REAL-TIME TRANSFER

BUS A TO BUS B

21

3

1

23

2

22

21

OE

L

3

DIR

L

1

23

2

22

SBA

H

DIR CLKAB CLKBA SAB

SBA

X

CLKAB CLKBA SAB

OE

X

↑

X

↑

X

H or L

X

H

X

H

X

L

H

H or L

X

↑

STORAGE FROM

A, B, OR A AND B

TRANSFER STORED DATA

TO A AND/OR B

Pin numbers shown are for the DW, JT, NT, and W packages.

Figure 1. Bus-Management Functions

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢊꢅ ꢆꢋ ꢌ ꢄ ꢍ ꢀ ꢆ ꢎ ꢋꢁ ꢀꢅ ꢏꢐ ꢑ ꢏ ꢎꢀ ꢋꢁ ꢒ ꢎꢏ ꢓ ꢐꢀ ꢆꢏ ꢎꢀ

ꢔꢐ ꢆ ꢕ ꢖ ꢗꢀꢆꢋꢆ ꢏ ꢊꢍꢆ ꢘ ꢍꢆꢀ

SCBS037D − AUGUST 1989 − REVISED MAY 2004

FUNCTION TABLE

DATA I/O

INPUTS

OPERATION OR FUNCTION

OE

X

H

L

DIR

X

CLKAB

CLKBA

SAB

X

SBA

X

A1 THRU A8

B1 THRU B8

†

↑

X

Input

Unspecified

Store A, B unspecified

†

X

↑

X

Unspecified

Input

Store B, A unspecified

X

↑

H or L

X

↑

H or L

X

Input

Input disabled

Output

Input

Store A and B data

Isolation, hold storage

Real-time B data to A bus

Stored B data to A bus

Real-time A data to B bus

Stored A data to B bus

X

Input disabled

Input

L

X

L

X

H or L

X

H

Output

Input

L

H

X

L

X

Input

Output

L

H or L

X

H

X

Input

Output

†

The data output functions can be enabled or disabled by various signals at the OE and DIR inputs. Data input functions always are enabled, i.e.,

data at the bus pins is stored on every low-to-high transition of the clock inputs.

logic diagram (positive logic)

21

OE

3

DIR

23

CLKBA

22

SBA

1

CLKAB

2

SAB

One of Eight

Channels

1D

C1

4

A1

20

B1

1D

C1

To Seven Other Channels

Pin numbers shown are for the DW, JT, NT, and W packages.

4

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SCBS037D − AUGUST 1989 − REVISED MAY 2004

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

CC

Input voltage range: Control inputs (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V

Voltage range applied to any output in the disabled or power-off state, V . . . . . . . . . . . . . . . . . −0.5 V to 7 V

O

Voltage range applied to any output in the high state, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V

O

CC

Current into any output in the low state: SN54BCT646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA

SN74BCT646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA

Package thermal impedance, θ (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W

JA

(see Note 3): NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W

Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

3. The package thermal impedance is calculated in accordance with JESD 51-3.

recommended operating conditions (see Note 4)

SN54BCT646

MIN NOM MAX

SN74BCT646

UNIT

MIN NOM

MAX

V

Supply voltage

4.5

2

5

5.5

4.5

2

5

5.5

V

CC

IH

IL

High-level input voltage

Low-level input voltage

Input clamp current

0.8

−18

−12

48

0.8

−18

−15

64

V

I

mA

°C

IK

High-level output current

Low-level output current

Operating free-air temperature

OH

OL

T

A

−55

125

0

70

NOTE 4: All unused control inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

CC

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢃ ꢇꢈ ꢀꢁꢉ ꢃ ꢄꢅ ꢆꢇ ꢃ ꢇ

ꢊꢅ ꢆꢋ ꢌ ꢄ ꢍ ꢀ ꢆ ꢎ ꢋꢁ ꢀꢅ ꢏꢐ ꢑ ꢏ ꢎꢀ ꢋꢁ ꢒ ꢎꢏ ꢓ ꢐꢀ ꢆꢏ ꢎꢀ

ꢔꢐ ꢆ ꢕ ꢖ ꢗꢀꢆꢋꢆ ꢏ ꢊꢍꢆ ꢘ ꢍꢆꢀ

SCBS037D − AUGUST 1989 − REVISED MAY 2004

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN54BCT646

SN74BCT646

PARAMETER

TEST CONDITIONS

I = −18 mA

UNIT

†

MIN TYP

MAX

MIN TYP

MAX

V

= 4.5 V,

= 4.5 V

−1.2

V

IK

CC

I

= −3 mA

= −12 mA

= −15 mA

= 48 mA

= 64 mA

2.4

2

3.3

3.2

2.4

2

3.3

3.1

OH

OL

V

OH

CC

0.38

0.55

V

OL

V

CC

V

CC

V

CC

V

CC

= 4.5 V

= 5.5 V,

V

0.42

0.55

1

A or B port

1

I

V = 5.5 V

I

mA

µA

mA

I

Control inputs

A or B port

1

70

‡

V = 2.7 V

I

IH

Control inputs

A or B port

20

−0.7

−225

67

‡

V = 0.5 V

I

IL

Control inputs

§

I

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

= 5.5 V,

= 5 V,

V = 0

O

−100

−225 −100

mA

pF

OS

A or B port

V = GND

I

42

5.6

10

6

67

9

42

5.6

10

6

CCL

CCH

CCZ

A or B port

Control inputs

A or B port

V = 4.5 V

I

9

V = GND

I

16

C

V = 2.5 V or 0.5 V

I

i

= 5 V,

V

O

= 2.5 V or 0.5 V

12

14

pF

io

†

‡

§

All typical values are at V

For I/O ports, the parameters I and I include the off-state output current.

Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

= 5 V, T = 25°C.

A

CC

IH

IL

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

V

T

= 5 V,

= 25°C

CC

A

SN54BCT646

SN7BCT646

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

f

t

Clock frequency

83

MHz

ns

clock

Pulse duration, CLK high or low

Setup time, A or B before CLKAB↑ or CLKBA↑

Hold time, A or B after CLKAB↑ or CLKBA↑

6

7

6

w

ns

su

h

0.5

ns

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢊ ꢅꢆꢋꢌ ꢄꢍꢀ ꢆ ꢎꢋꢁꢀ ꢅꢏꢐ ꢑꢏꢎꢀ ꢋꢁꢒ ꢎꢏꢓ ꢐ ꢀ ꢆꢏ ꢎ

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ꢔ ꢐꢆ ꢕ ꢖ ꢗꢀꢆꢋꢆ ꢏ ꢊ ꢍꢆ ꢘ ꢍꢆ

SCBS037D − AUGUST 1989 − REVISED MAY 2004

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature, C = 50 pF (unless otherwise noted) (see Figure 2)

L

V

T

= 5 V,

= 25°C

CC

A

SN54BCT646 SN74BCT646

FROM

(INPUT)

TO

(OUTPUT)

PARAMETER

UNIT

MIN

83

TYP

MAX

MIN

83

MAX

MIN

83

MAX

f

t

MHz

ns

max

PLH

PHL

PLH

PHL

PLH

PHL

PLH

PHL

PZH

PZL

PHZ

PLZ

PZH

PZL

PHZ

PLZ

3.6

3.9

3.1

3.7

4.5

3.3

3.9

4.7

4

7

9.4

9.2

3.6

3.9

3.1

3.7

4.5

3.3

3.9

4.7

4

12.4

11.5

11.1

12.1

15.2

9.8

3.6

3.9

3.1

3.7

4.5

3.3

3.9

4.7

4

11.2

10.6

9.5

CLKBA or CLKAB

A or B

B or A

A or B

6

8.1

ns

6.8

8.8

6

8.9

10.5

13.8

9.1

11.2

8.1

†

SAB or SBA

(with A or B high)

7.7

8.3

7.9

8.8

7.2

7

10.2

10.8

10.7

11.8

9.4

13.3

13.7

14

12

†

SAB or SBA

(with A or B low)

12.9

13.2

14.4

10.9

10.5

13.1

14.6

12.6

11.8

OE

4.6

4

4.6

4

15.4

12

4.6

4

OE

DIR

3.4

2.8

3.8

3.2

9.3

3.4

2.8

3.8

3.2

11.6

14

3.4

2.8

3.8

3.2

7.8

8.9

8.4

7.3

10.7

11.9

10.7

9.9

15.6

13.2

12.6

†

These parameters are measured with the internal output state of the storage register opposite that of the bus input.

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢃ ꢇꢈ ꢀꢁꢉ ꢃ ꢄꢅ ꢆꢇ ꢃ ꢇ

ꢊꢅ ꢆꢋ ꢌ ꢄ ꢍ ꢀ ꢆ ꢎ ꢋꢁ ꢀꢅ ꢏꢐ ꢑ ꢏ ꢎꢀ ꢋꢁ ꢒ ꢎꢏ ꢓ ꢐꢀ ꢆꢏ ꢎꢀ

ꢔꢐ ꢆ ꢕ ꢖ ꢗꢀꢆꢋꢆ ꢏ ꢊꢍꢆ ꢘ ꢍꢆꢀ

SCBS037D − AUGUST 1989 − REVISED MAY 2004

PARAMETER MEASUREMENT INFORMATION

7 V (t

, t

, O.C.)

PZL PLZ

Open

(all others)

S1

From Output

Under Test

Test

Point

C

L

R1

(see Note A)

From Output

Under Test

Test

Point

C

L

R2

(see Note A)

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

R

= R1 = R2

L

LOAD CIRCUIT FOR

3-STATE AND OPEN-COLLECTOR OUTPUTS

High-Level

Pulse

(see Note B)

3 V

0 V

1.5 V

3 V

Timing Input

(see Note B)

1.5 V

t

w

0 V

3 V

0 V

3 V

0 V

t

h

Low-Level

Pulse

t

1.5 V

su

1.5 V

Data Input

(see Note B)

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

3 V

0 V

Output

Control

(low-level enable)

3 V

1.5 V

Input

(see Note B)

1.5 V

0 V

PHL

t

PZL

t

PLZ

t

PLH

3.5 V

In-Phase

Output

(see Note D)

V

OH

1.5 V

Waveform 1

(see Notes C and D)

1.5 V

t

V

OL

V

OL

0.3 V

t

PHZ

PLH

t

PHL

PZH

V

OH

V

OH

Out-of-Phase

Output

(see Note D)

Waveform 2

(see Notes C and D)

1.5 V

0.3 V

0 V

V

OL

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES (see Note D)

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A.

C includes probe and jig capacitance.

L

B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, t = t ≤ 2.5 ns, duty cycle = 50%.

r

f

C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

D. The outputs are measured one at a time, with one transition per measurement.

E. When measuring propagation delay times of 3-state outputs, switch S1 is open.

F. All parameters and waveforms are not applicable to all devices.

Figure 2. Load Circuit and Voltage Waveforms

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

10-May-2007

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

LCCC

CFP

Drawing

5962-9155501M3A

5962-9155501MKA

5962-9155501MLA

SN74BCT646DW

ACTIVE

FK

28

24

1

TBD

POST-PLATE N / A for Pkg Type

W

A42

N / A for Pkg Type

CDIP

SOIC

JT

A42 SNPB

DW

25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74BCT646DWE4

SN74BCT646DWG4

SN74BCT646DWR

SN74BCT646DWRE4

SN74BCT646DWRG4

SN74BCT646NT

ACTIVE

SOIC

PDIP

DW

NT

24

25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

15

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

POST-PLATE N / A for Pkg Type

SN74BCT646NTE4

NT

15

Pb-Free

(RoHS)

SNJ54BCT646FK

SNJ54BCT646JT

SNJ54BCT646W

ACTIVE

LCCC

CDIP

CFP

FK

JT

W

28

24

1

TBD

A42 SNPB

A42

N / A for Pkg Type

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-May-2007

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

19-May-2007

TAPE AND REEL INFORMATION

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

19-May-2007

Device

Package Pins

Site

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) (mm) Quadrant

(mm)

SN74BCT646DWR

DW

24

TAI

330

24

10.75

15.7

2.7

12

24

Q1

TAPE AND REEL BOX INFORMATION

Device

Package

Pins

Site

TAI

Length (mm) Width (mm) Height (mm)

SN74BCT646DWR

DW

24

346.0

41.0

Pack Materials-Page 2

MECHANICAL DATA

MCER004A – JANUARY 1995 – REVISED JANUARY 1997

JT (R-GDIP-T**)

CERAMIC DUAL-IN-LINE

24 LEADS SHOWN

PINS **

A

24

28

DIM

13

24

1.280

(32,51) (37,08)

1.460

A MAX

1.240

(31,50) (36,58)

1.440

B

A MIN

B MAX

B MIN

0.300

(7,62)

0.291

(7,39)

1

12

0.070 (1,78)

0.030 (0,76)

0.245

(6,22)

0.285

(7,24)

0.320 (8,13)

0.290 (7,37)

0.015 (0,38) MIN

0.100 (2,54) MAX

0.200 (5,08) MAX

Seating Plane

0.130 (3,30) MIN

0.023 (0,58)

0.015 (0,38)

0°–15°

0.014 (0,36)

0.008 (0,20)

0.100 (2,54)

4040110/C 08/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

D. Index point is provided on cap for terminal identification.

E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MCFP007 – OCTOBER 1994

W (R-GDFP-F24)

CERAMIC DUAL FLATPACK

0.375 (9,53)

0.340 (8,64)

Base and Seating Plane

0.006 (0,15)

0.004 (0,10)

0.045 (1,14)

0.026 (0,66)

0.090 (2,29)

0.045 (1,14)

0.395 (10,03)

0.360 (9,14)

0.240 (6,10)

0.360 (9,14)

0.240 (6,10)

0.019 (0,48)

0.015 (0,38)

1

24

0.050 (1,27)

0.640 (16,26)

0.490 (12,45)

0.030 (0,76)

0.015 (0,38)

12

13

30° TYP

1.115 (28,32)

0.840 (21,34)

4040180-5/B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

D. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD

E. Index point is provided on cap for terminal identification only.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**)

LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

A

B

NO. OF

TERMINALS

**

18 17 16 15 14 13 12

MIN

MAX

MIN

MAX

0.342

(8,69)

0.358

(9,09)

0.307

(7,80)

0.358

(9,09)

19

20

11

10

9

20

28

44

52

68

84

0.442

(11,23)

0.458

(11,63)

0.406

(10,31)

0.458

(11,63)

21

B SQ

22

0.640

(16,26)

0.660

(16,76)

0.495

(12,58)

0.560

(14,22)

8

A SQ

23

0.739

(18,78)

0.761

(19,32)

0.495

(12,58)

0.560

(14,22)

7

24

25

6

0.938

(23,83)

0.962

(24,43)

0.850

(21,6)

0.858

(21,8)

5

1.141

(28,99)

1.165

(29,59)

1.047

(26,6)

1.063

(27,0)

26 27 28

1

2

3

4

0.080 (2,03)

0.064 (1,63)

0.020 (0,51)

0.010 (0,25)

0.020 (0,51)

0.010 (0,25)

0.055 (1,40)

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

4040140/D 10/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a metal lid.

D. The terminals are gold plated.

E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MPDI004 – OCTOBER 1994

NT (R-PDIP-T**)

PLASTIC DUAL-IN-LINE PACKAGE

24 PINS SHOWN

A

PINS **

24

28

DIM

24

13

1.260

(32,04) (36,20)

1.425

A MAX

1.230

(31,24) (35,18)

1.385

A MIN

B MAX

B MIN

0.280 (7,11)

0.250 (6,35)

0.310

(7,87)

0.315

(8,00)

1

12

0.290

(7,37)

0.295

(7,49)

0.070 (1,78) MAX

B

0.020 (0,51) MIN

0.200 (5,08) MAX

Seating Plane

0.125 (3,18) MIN

0.100 (2,54)

0.010 (0,25)

0°–15°

0.021 (0,53)

0.015 (0,38)

M

0.010 (0,25) NOM

4040050/B 04/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,

improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.

Customers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s

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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

applications using TI components. To minimize the risks associated with customer products and applications, customers should

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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask

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Products

Amplifiers

Data Converters

DSP

Applications

Audio

amplifier.ti.com

dataconverter.ti.com

dsp.ti.com

www.ti.com/audio

Automotive

Broadband

Digital Control

Military

www.ti.com/automotive

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

interface.ti.com

logic.ti.com

Logic

Power Mgmt

Microcontrollers

RFID

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/lpw

Telephony

Low Power

Wireless

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	SNJ54BCT646FK
厂家：	TEXAS INSTRUMENTS
描述：	OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS 八路总线收发器和寄存器具有三态输出总线收发器输出元件
文件：	总18页 (文件大小：386K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SNJ54BCT646FK [TI]

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