SNJ54HCT377J [TI]
OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE; 八路D型触发器与时钟使能
| 型号： | SNJ54HCT377J |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE |
| 文件： | 总9页 (文件大小：273K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54HCT377, SN74HCT377
OCTAL D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCLS067D – NOVEMBER 1988 – REVISED MARCH 2003
Operating Voltage Range of 4.5 V to 5.5 V
Outputs Can Drive Up To 10 LSTTL Loads
Contain Eight Flip-Flops With Single-Rail
Outputs
Clock Enable Latched to Avoid False
Clocking
Low Power Consumption, 80-µA Max I
CC
Typical t = 12 ns
pd
±4-mA Output Drive at 5 V
Applications Include:
– Buffer/Storage Registers
– Shift Registers
Low Input Current of 1 µA Max
Inputs Are TTL-Voltage Compatible
– Pattern Generators
SN54HCT377 . . . FK PACKAGE
(TOP VIEW)
SN54HCT377 . . . J OR W PACKAGE
SN74HCT377 . . . DW OR N PACKAGE
(TOP VIEW)
CLKEN
1Q
V
CC
1
2
3
4
5
6
7
8
9
20
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 CLK
3
2
1
20 19
18
1D
8D
7D
7Q
2D
2Q
3Q
3D
4D
4
5
6
7
8
2D
17
16
2Q
3Q
15 6Q
14
9 10 11 12 13
3D
6D
4D
4Q
GND 10
description/ordering information
These devices are positive-edge-triggered D-type flip-flops. The ’HCT377 devices are similar to the ’HCT273
devices, but feature a latched clock-enable (CLKEN) input instead of a common clear.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the
positive-going edge of the clock (CLK) pulse if CLKEN is low. Clock triggering occurs at a particular voltage level
and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or
low level, the D input has no effect at the output. These devices are designed to prevent false clocking by
transitions at CLKEN.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP – N
Tube
SN74HCT377N
SN74HCT377N
–40°C to 85°C
–55°C to 125°C
Tube
SN74HCT377DW
SN74HCT377DWR
SNJ54HCT377J
SNJ54HCT377W
SNJ54HCT377FK
SOIC – DW
HCT377
Tape and reel
Tube
CDIP – J
CFP – W
LCCC – FK
SNJ54HCT377J
SNJ54HCT377W
SNJ54HCT377FK
Tube
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT377, SN74HCT377
OCTAL D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCLS067D – NOVEMBER 1988 – REVISED MARCH 2003
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
CLKEN CLK
D
X
H
L
H
L
X
↑
Q
0
H
L
↑
L
X
L
X
Q
0
logic diagram (positive logic)
1
CLKEN
11
CLK
C1
1D
2
5
6
3
1Q
2Q
3Q
1D
C1
1D
4
2D
C1
1D
7
3D
C1
1D
9
12
15
16
19
8
4Q
5Q
6Q
7Q
8Q
4D
C1
1D
13
5D
C1
1D
14
6D
C1
1D
17
7D
C1
1D
18
8D
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT377, SN74HCT377
OCTAL D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCLS067D – NOVEMBER 1988 – REVISED MARCH 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HCT377
MIN NOM MAX
SN74HCT377
UNIT
MIN NOM
MAX
V
V
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
IL
I
High-level input voltage
Low-level input voltage
Input voltage
V
V
= 4.5 V to 5.5 V
= 4.5 V to 5.5 V
CC
0.8
0.8
V
CC
0
0
V
V
0
0
V
V
V
CC
CC
Output voltage
V
O
CC
CC
t
Input transition (rise and fall) times
Operating free-air temperature
500
125
500
85
ns
°C
t
T
–55
–40
A
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HCT377 SN74HCT377
A
PARAMETER
TEST CONDITIONS
V
UNIT
V
CC
MIN
TYP
MAX
MIN
4.4
MAX
MIN
4.4
MAX
I
I
I
I
= –20 µA
= –4 mA
= 20 µA
= 4 mA
4.5 V
4.5 V
4.5 V
4.5 V
5.5 V
5.5 V
4.4 4.499
OH
OH
OL
OL
V
V
V = V or V
IH
OH
I
IL
3.98
4.30
0.001
0.17
3.7
3.84
0.1
0.26
±100
8
0.1
0.4
0.1
0.33
V = V or V
V
OL
I
IH
IL
I
I
V = V
I
or 0
±0.1
±1000
160
±1000
80
nA
I
CC
CC
V = V
I
or 0,
I
O
= 0
µA
CC
One input at 0.5 V or 2.4 V,
Other inputs at GND or V
‡
∆I
CC
5.5 V
1.4
3
2.4
10
3
2.9
10
mA
pF
CC
4.5 V to
5.5 V
C
10*
i
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
‡
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or V
CC
.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT377, SN74HCT377
OCTAL D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCLS067D – NOVEMBER 1988 – REVISED MARCH 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HCT377 SN74HCT377
A
V
UNIT
MHz
ns
CC
MIN
MAX
25
MIN
MAX
17
MIN
MAX
20
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
f
t
Clock frequency
Pulse duration
clock
30
19
22
20
18
12
10
12
10
3
30
28
18
17
18
17
3
25
23
15
14
15
14
3
CLK high or low
Data
w
t
t
Setup time before CLK↑
Hold time data after CLK↑
ns
ns
su
CLKEN high or low
Data
3
3
3
h
4.5 V
5.5 V
5
5
5
5
5
5
CLKEN inactive or active
switching characteristics over recommended operating free-air temperature range, C = 50 pF (unless
L
otherwise noted) (see Figure 1)
SN54HCT377
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
T
A
= 25°C
TYP
31
UNIT
CC
MIN
MAX
MIN
25
MAX
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
17
19
f
t
t
MHz
ns
max
pd
t
30
37
15
30
28
15
14
45
40
22
21
Any
Any
CLK
12
8
ns
6
switching characteristics over recommended operating free-air temperature range, C = 50 pF (unless
L
otherwise noted) (see Figure 1)
SN74HCT377
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
T
A
= 25°C
TYP
31
UNIT
CC
MIN
MAX
MIN
25
MAX
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
20
22
f
t
t
MHz
ns
max
pd
t
30
37
15
30
28
15
14
38
35
19
17
Any
Any
CLK
12
8
ns
6
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance
No load
30
pF
pd
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT377, SN74HCT377
OCTAL D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCLS067D – NOVEMBER 1988 – REVISED MARCH 2003
PARAMETER MEASUREMENT INFORMATION
3 V
0 V
From Output
Under Test
Test
Point
High-Level
Pulse
1.3 V
1.3 V
C
= 50 pF
L
t
w
(see Note A)
3 V
0 V
Low-Level
Pulse
1.3 V
1.3 V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
0 V
Input
1.3 V
1.3 V
t
t
PLH
PHL
90%
3 V
0 V
V
V
OH
In-Phase
Output
Reference
Input
90%
t
1.3 V
1.3 V
10%
1.3 V
10%
OL
t
r
f
f
t
t
h
su
t
t
PLH
PHL
90%
3 V
0 V
Out-of-
Phase
Output
V
V
Data
Input
OH
2.7 V
2.7 V
90%
t
1.3 V
0.3 V
1.3 V
0.3 V
1.3 V
10%
1.3 V
10%
OL
t
t
t
r
f
r
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
NOTES: A.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
C includes probe and test-fixture capacitance.
L
O
r
f
C. The outputs are measured one at a time with one input transition per measurement.
D. For clock inputs, f is measured when the input duty cycle is 50%.
max
are the same as t
E.
t
and t
.
pd
PLH
PHL
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
5-Sep-2005
PACKAGING INFORMATION
Orderable Device
SN74HCT377DW
SN74HCT377DWE4
SN74HCT377DWR
SN74HCT377DWRE4
SN74HCT377N
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
DW
20
20
20
20
20
20
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
SOIC
SOIC
PDIP
PDIP
DW
DW
DW
N
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74HCT377NE4
N
20
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
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Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
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