SNJ54LS125AFK [TI]
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS; 具有三态输出翻两番总线缓冲器
| 型号： | SNJ54LS125AFK |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS |
| 文件： | 总18页 (文件大小：578K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied.
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
SN54125, SN54126, SN54LS125A,
SN54LS126A . . . J OR W PACKAGE
SN74125, SN74126 . . . N PACKAGE
SN74LS125A, SN74LS126A . . . D, N, OR NS PACKAGE
(TOP VIEW)
Quad Bus Buffers
3-State Outputs
Separate Control for Each Channel
description
1G, 1G*
1A
1Y
2G, 2G*
2A
V
CC
4G, 4G*
1
2
3
4
5
6
7
14
13
12
11
10
9
These bus buffers feature three-state outputs
that, when enabled, have the low impedance
characteristics of a TTL output with additional
drive capability at high logic levels to permit
driving heavily loaded bus lines without external
pullup resistors. When disabled, both output
4A
4Y
3G, 3G*
3A
3Y
2Y
GND
8
transistors are turned off, presenting
a
high-impedance state to the bus so the output will
actneitherasasignificantloadnorasadriver. The
’125 and ’LS125A devices’ outputs are disabled
when G is high. The ’126 and ’LS126A devices’
outputs are disabled when G is low.
*G on ’125 and ’LS125A devices;
G on 126 and ’LS126A devices
SN54LS125A, SN54LS126A . . . FK PACKAGE
(TOP VIEW)
3
2
1
20 19
18
4A
NC
4Y
NC
1Y
NC
4
5
6
7
8
17
16
15
2G, 2G*
NC
14 3G, 3G*
9 10 11 12 13
2A
*G on ’125 and ’LS125A devices;
G on 126 and ’LS126A devices
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied.
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
ORDERING INFORMATION
ORDERABLE
TOP-SIDE
MARKING
†
PACKAGE
T
A
PART NUMBER
SN74LS125AN
SN74LS126AN
SN74LS125AD
SN74LS125ADR
SN74LS126AD
SN74LS126ADR
SN74LS125ANSR
SN74LS126ANSR
SN54LS125AJ
Tube
SN74LS125AN
SN74LS126AN
PDIP – N
SOIC – D
Tube
Tube
LS125A
LS126A
Tape and reel
Tube
0°C to 70°C
Tape and reel
Tape and reel
Tape and reel
Tube
74LS125A
SOP – NS
CDIP – J
74LS126A
SN54LS125AJ
SNJ54LS125AJ
SNJ54LS125AW
SNJ54LS125AFK
Tube
SNJ54LS125AJ
SNJ54LS125AW
SNJ54LS125AFK
–55°C to 125°C
CFP – W
Tube
LCCC – FK
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
logic diagram (each gate)
’125, ’LS125A
’126, ’LS126A
G
A
Y
Y
G
A
Y = A
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied.
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
schematics (each gate)
’125 CIRCUITS
V
CC
4 k
2.5 k
4 k
1 k
85
2.5 k
OUTPUT Y
GND
4 k
CONTROL
INPUT G
1.6 k
1.6 k
625
DATA
INPUT A
’126 CIRCUITS
V
CC
2.5 k
4.25 k
4 k
4 k
1 k
2.5 k
85
4 k
OUTPUT Y
GND
CONTROL
INPUT G
1.6 k
625
1.6 k
DATA
INPUT A
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
(’125 and ’126)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
I
Package thermal impedance, θ (see Note 2):N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
JA
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. The package termal impedance is calculated in accordance with JESD 51-7.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied.
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
schematics (each gate)
’LS125A CIRCUITS
V
CC
10 k
8 k
18 k
6 k
4 k
50
4 k
OUTPUT
INPUT G
20 k
1.5 k
750
5 k
GND
INPUT A
’LS126A CIRCUITS
V
CC
18 k
12 k
8 k
18 k
4 k
50
6 k
INPUT G
4 k
OUTPUT
20 k
750
1.5 k
5 k
GND
INPUT A
Resistor values shown are nominal.
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
(’LS125A and ’LS126A)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Package thermal impedance, θ (see Note 2):D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. The package termal impedance is calculated in accordance with JESD 51-7.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied.
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
recommended operating conditions
SN54125
SN54126
SN74125
SN74126
UNIT
MIN NOM
MAX
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.75
2
5
5.25
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
IH
0.8
–2
0.8
–5.2
16
V
IL
I
I
mA
mA
°C
OH
16
OL
T
A
–55
125
0
70
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54125
SN54126
SN74125
SN74126
†
PARAMETER
UNIT
TEST CONDITIONS
‡
‡
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
V
V
= MIN,
= MIN,
I = –12 mA
–1.5
–1.5
V
V
IK
CC
I
V
IH
V
IH
V
IH
= 2 V,
= 2 V,
= 2 V,
I
= –2 mA
= –5.2 mA
= 0.8 V,
2.4
3.3
CC
OH
OH
= 0.8 V
I
2.4
3.1
IL
OH
= MIN,
V
CC
IL
V
OL
0.4
0.4
V
I
= 16 mA
OL
V
V
V
V
V
V
= MAX
V
V
= 2.4 V
= 0.4 V
40
–40
1
40
–40
1
CC
O
µA
I
OZ
= 0.8 V
IL
O
I
I
I
I
= MAX,
= MAX,
= MAX,
= MAX
V = 6.5 V
I
mA
µA
I
CC
CC
CC
CC
V = 2.4 V
I
40
40
IH
IL
OS
V = 0.4 V
I
–1.6
–70
54
–1.6
–70
54
mA
mA
§
–30
–28
’125
’126
32
36
32
36
V
CC
= MAX
I
mA
CC
(see Note 3)
62
62
†
‡
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at V = 5 V, T = 25°C.
Not more than one output should be shorted at a time.
CC
A
NOTE 3: Data inputs = 0 V; output control = 4.5 V for ’125 and 0 V for ’126.
switching characteristics, V
= 5 V, T = 25°C (see Figure 1)
A
CC
SN54125
SN74125
SN54126
SN74126
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
8
MAX
13
MIN
TYP
8
MAX
13
t
PLH
R
R
R
= 400 Ω,
C
C
= 50 pF
= 50 pF
= 5 pF
ns
ns
ns
L
L
L
L
L
t
t
t
t
t
12
18
12
18
PHL
PZH
PZL
PHZ
PLZ
11
16
17
25
11
16
18
25
= 400 Ω,
= 400 Ω,
5
7
8
10
12
16
18
C
L
12
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied.
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
recommended operating conditions
SN54LS125A
SN54LS126A
SN74LS125A
SN74LS126A
UNIT
MIN NOM
MAX
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.75
2
5
5.25
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
IH
0.7
–1
0.8
–2.6
24
V
IL
I
I
mA
mA
°C
OH
12
OL
T
A
–55
125
0
70
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LS125A
SN54LS126A
SN74LS125A
SN74LS126A
†
PARAMETER
UNIT
TEST CONDITIONS
‡
‡
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
V
= MIN,
= MIN,
I = –18 mA
–1.5
–1.5
V
V
IK
CC
I
V
IL
V
IL
V
IL
V
IL
V
IL
= 0.7 V,
= 0.8 V
= 0.7 V,
= 0.8 V,
= 0.8 V,
I
I
I
I
I
= –1 mA
= –2.6 mA
= 12 mA
= 12 mA
= 24 mA
= 2.4 V
2.4
CC
OH
OH
OL
OL
OL
OH
= 2 V
2.4
IH
0.25
0.4
V
V
= MIN,
= 2 V
CC
IH
V
OL
0.25
0.35
0.4
0.5
V
V
V
V
V
20
O
O
O
O
V
= 0.7 V
= 0.8 V
IL
IL
= 0.4 V
–20
V
V
= MAX,
= 2 V,
CC
IH
µA
I
OZ
= 2.4 V
20
–20
0.1
V
= 0.4 V
I
I
V
CC
V
CC
V
CC
= MAX,
= MAX,
= MAX,
V = 7 V
I
0.1
20
mA
µA
I
V = 2.7 V
I
20
IH
’LS125A-G inputs
–0.2
–0.4
–225
20
–0.2
–0.4
–225
20
mA
mA
mA
I
IL
V = 0.4 V
I
’LS125A-A inputs; ’LS126A All inputs
§
V
CC
= MAX
–40
–40
I
OS
’LS125A
’LS126A
11
12
11
12
V
CC
= MAX
I
mA
CC
(see Note 4)
22
22
†
‡
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at V = 5 V, T = 25°C.
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
CC
A
NOTE 4: Data inputs = 0 V; output control = 4.5 V for ’LS125A and 0 V for ’LS126A.
switching characteristics, V
= 5 V, T = 25°C (see Figure 1)
A
CC
SN54LS125A
SN74LS125A
SN54LS126A
SN74LS126A
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
9
MAX
MIN
TYP
9
MAX
t
15
18
15
18
PLH
R
R
R
= 667 Ω,
C
C
= 45 pF
= 45 pF
= 5 pF
ns
ns
ns
L
L
L
L
L
t
t
t
t
t
7
8
PHL
PZH
PZL
PHZ
PLZ
12
15
20
25
16
21
25
35
= 667 Ω,
= 667 Ω,
20
20
25
25
C
L
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied.
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
PARAMETER MEASUREMENT INFORMATION
SERIES 54/74 DEVICES
V
CC
Test
Point
R
L
Test
Point
S1
V
CC
From Output
Under Test
V
CC
(see Note B)
R
L
C
L
(see Note A)
From Output
Under Test
1 kΩ
R
L
(see Note B)
From Output
Under Test
C
Test
Point
C
L
(see Note A)
L
(see Note A)
S2
LOAD CIRCUIT
LOAD CIRCUIT
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
FOR OPEN-COLLECTOR OUTPUTS
FOR 3-STATE OUTPUTS
3 V
High-Level
Timing
Input
1.5 V
1.5 V
1.5 V
1.5 V
Pulse
0 V
t
t
h
w
t
su
3 V
0 V
Low-Level
Pulse
Data
Input
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
3 V
0 V
Input
1.5 V
1.5 V
t
t
PLZ
PZL
t
t
PHL
PLH
Waveform 1
(see Notes C
and D)
≈1.5 V
In-Phase
1.5 V
V
OH
Output
(see Note D)
V
OL
+ 0.5 V
1.5 V
1.5 V
1.5 V
V
OL
V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
V
OH
Waveform 2
(see Notes C
and D)
V
OH
– 0.5 V
Out-of-Phase
Output
V
V
OH
1.5 V
1.5 V
≈1.5 V
(see Note D)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C
includes probe and jig capacitance.
L
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for t
, t
, t
, and t
; S1 is open and S2 is closed for t
PLZ PZH
; S1 is closed and S2 is open for t .
PZL
PLH PHL PHZ
E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z ≈ 50 Ω; t and t ≤ 7 ns for Series
O
r
f
54/74 devices and t and t ≤ 2.5 ns for Series 54S/74S devices.
r
f
F. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied.
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
PARAMETER MEASUREMENT INFORMATION
SERIES 54LS/74LS DEVICES
V
CC
Test
Point
R
L
Test
Point
S1
V
CC
From Output
Under Test
V
CC
(see Note B)
R
L
C
L
(see Note A)
From Output
Under Test
5 kΩ
R
L
(see Note B)
From Output
Under Test
C
Test
Point
C
L
(see Note A)
L
(see Note A)
S2
LOAD CIRCUIT
LOAD CIRCUIT
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
FOR OPEN-COLLECTOR OUTPUTS
FOR 3-STATE OUTPUTS
3 V
High-Level
Timing
Input
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0 V
t
t
h
w
t
su
3 V
0 V
Low-Level
Pulse
Data
Input
1.3 V
1.3 V
1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
3 V
0 V
Control
(low-level
enabling)
1.3 V
1.3 V
3 V
0 V
Input
1.3 V
1.3 V
t
t
PLZ
PZL
t
t
PHL
PLH
Waveform 1
(see Notes C
and D)
≈1.5 V
In-Phase
Output
(see Note D)
1.3 V
V
V
OH
V
OL
+ 0.5 V
1.3 V
1.3 V
1.3 V
V
OL
t
PHZ
OL
t
PZH
t
t
PLH
PHL
V
OH
Waveform 2
(see Notes C
and D)
V
OH
– 0.5 V
Out-of-Phase
Output
(see Note D)
V
V
OH
1.3 V
1.3 V
≈1.5 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C
includes probe and jig capacitance.
L
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for t
, t
, t
, and t
; S1 is open and S2 is closed for t
PLZ PZH
; S1 is closed and S2 is open for t .
PLH PHL PHZ
PZL
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z ≈ 50 Ω, t ≤ 1.5 ns, t ≤ 2.6 ns.
O
r
f
G. The outputs are measured one at a time with one input transition per measurement.
Figure 2. Load Circuits and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
JM38510/32301B2A
JM38510/32301BCA
JM38510/32301BDA
JM38510/32301SCA
JM38510/32301SDA
SN54126J
ACTIVE
ACTIVE
FK
J
20
14
14
14
14
14
14
14
14
14
14
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Call TI
ACTIVE
W
J
ACTIVE
CDIP
CFP
ACTIVE
W
J
OBSOLETE
ACTIVE
CDIP
CDIP
PDIP
PDIP
PDIP
SOIC
SN54LS125AJ
SN74125N
J
1
Level-NC-NC-NC
Call TI
OBSOLETE
OBSOLETE
OBSOLETE
ACTIVE
N
N
N
D
SN74125N3
Call TI
SN74126N
Call TI
SN74LS125AD
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LS125ADBR
SN74LS125ADBRE4
SN74LS125ADE4
SN74LS125ADR
SN74LS125ADRE4
SN74LS125AN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SOIC
SOIC
SOIC
PDIP
DB
DB
D
14
14
14
14
14
14
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
N
25
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74LS125AN3
SN74LS125ANE4
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
14
14
TBD
Call TI
Call TI
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74LS125ANSR
SN74LS125ANSRE4
SN74LS125ANSRG4
SN74LS126AD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SO
SO
NS
NS
NS
D
14
14
14
14
14
14
14
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
SOIC
SOIC
SOIC
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LS126ADE4
SN74LS126ADR
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LS126ADRE4
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LS126AJ
SN74LS126AN
OBSOLETE
ACTIVE
CDIP
PDIP
J
14
14
TBD
Call TI
Call TI
N
25
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74LS126ANE4
SN74LS126ANSR
ACTIVE
ACTIVE
PDIP
SO
N
14
14
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
NS
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
no Sb/Br)
SN74LS126ANSRE4
ACTIVE
SO
NS
14
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SNJ54126J
SNJ54126W
OBSOLETE
OBSOLETE
ACTIVE
CDIP
CFP
J
W
FK
J
14
14
20
14
14
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
SNJ54LS125AFK
SNJ54LS125AJ
SNJ54LS125AW
LCCC
CDIP
CFP
1
1
1
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
ACTIVE
ACTIVE
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明