SNJ54LV161AFK [TI]
4-BIT SYNCHRONOUS BINARY COUNTERS; 4位同步二进制计数器型号: | SNJ54LV161AFK |
厂家: | TEXAS INSTRUMENTS |
描述: | 4-BIT SYNCHRONOUS BINARY COUNTERS |
文件: | 总20页 (文件大小:437K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢆ ꢈꢉ ꢀꢁꢊ ꢃꢄꢅ ꢆꢇ ꢆꢈ
ꢃ ꢋꢌꢍ ꢎ ꢀꢏ ꢁꢐꢑꢒꢓ ꢁꢓ ꢔꢀ ꢌꢍ ꢁꢈꢒꢏ ꢐꢓ ꢔ ꢁꢎ ꢕꢒ ꢀ
SCLS404E − APRIL 1998 − REVISED APRIL 2005
SN54LV161A . . . J OR W PACKAGE
SN74LV161A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
D
D
D
D
D
D
D
D
D
D
2-V to 5.5-V V
Operation
CC
Max t of 9.5 ns at 5 V
pd
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
= 3.3 V, T = 25°C
CLR
CLK
A
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
RCO
A
Typical V
>2.3 V at V
(Output V
Undershoot)
OHV
CC
OH
Q
= 3.3 V, T = 25°C
A
A
B
C
D
Q
Q
Q
B
C
D
Support Mixed-Mode Voltage Operation on
All Ports
Internal Look-Ahead for Fast Counting
Carry Output for n-Bit Cascading
Synchronous Counting
ENP
GND
ENT
LOAD
Synchronously Programmable
SN54LV161A . . . FK PACKAGE
(TOP VIEW)
I
Supports Partial-Power-Down Mode
off
Operation
D
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
3
2
1 20 19
18
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
A
B
Q
Q
4
5
6
7
8
A
B
17
16
15
14
NC
C
NC
− 1000-V Charged-Device Model (C101)
Q
Q
C
D
D
9 10 11 12 13
description/ordering information
The ’LV161A devices are 4-bit synchronous
binary counters designed for 2-V to 5.5-V V
operation.
CC
NC − No internal connection
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube of 40
SN74LV161AD
SOIC − D
LV161A
Reel of 2500
Reel of 2000
Reel of 2000
Tube of 90
SN74LV161ADR
SN74LV161ANSR
SN74LV161ADBR
SN74LV161APW
SN74LV161APWR
SN74LV161APWT
SN74LV161ADGVR
SNJ54LV161AJ
SOP − NS
74LV161A
LV161A
SSOP − DB
−40°C to 85°C
Reel of 2000
Reel of 250
Reel of 2000
Tube of 25
TSSOP − PW
LV161A
TVSOP − DGV
CDIP − J
LV161A
SNJ54LV161AJ
SNJ54LV161AW
SNJ54LV161AFK
−55°C to 125°C CFP − W
Tube of 150
Tube of 55
SNJ54LV161AW
SNJ54LV161AFK
LCCC − FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
ꢔ ꢁ ꢄꢕꢀꢀ ꢓ ꢎꢑ ꢕꢒꢖ ꢍꢀ ꢕ ꢁ ꢓꢎꢕꢗ ꢘꢙ ꢚꢛ ꢜꢝꢞ ꢟꢠꢡ ꢢꢘ ꢞꢝ ꢢꢘꢣ ꢚꢢꢛ ꢤꢒ ꢓ ꢗ ꢔ ꢐꢎ ꢍꢓ ꢁ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢆꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆ ꢇꢆ ꢈ
ꢃꢋ ꢌꢍ ꢎ ꢀꢏ ꢁꢐ ꢑ ꢒ ꢓꢁ ꢓꢔ ꢀ ꢌꢍ ꢁ ꢈꢒꢏ ꢐꢓ ꢔꢁ ꢎꢕꢒ ꢀ
SCLS404E − APRIL 1998 − REVISED APRIL 2005
description/ordering information (continued)
These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed
counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the
outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and
internal gating. This mode of operation eliminates the output counting spikes that normally are associated with
synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising
(positive-going) edge of the clock waveform.
These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As
presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs
to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function for the ’LV161A devices is asynchronous. A low level at the clear (CLR) input sets all four
of the flip-flop outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO).
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 or 15 with Q high). This high-level overflow ripple-carry pulse
A
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the
level of CLK.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the
off
off
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
INPUTS
OUTPUTS
FUNCTION
LOAD
ENP
X
ENT
X
CLK
QB
L
QC
L
QD
L
CLR
L
QA
L
X
L
X
Reset to “0”
Preset Data
No Count
No Count
Count
H
X
X
A
B
C
D
H
H
H
H
X
X
L
No Change
No Change
Count up
H
L
X
H
H
H
H
X
X
No Change
No Count
2
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ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢆ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢆꢈ
ꢃ ꢋꢌꢍ ꢎ ꢀꢏ ꢁꢐꢑꢒꢓ ꢁꢓ ꢔꢀ ꢌꢍ ꢁꢈꢒꢏ ꢐꢓ ꢔ ꢁꢎ ꢕꢒ ꢀ
SCLS404E − APRIL 1998 − REVISED APRIL 2005
logic diagram (positive logic)
9
LOAD
10
ENT
15
RCO
†
LD
7
ENP
†
CK
2
CLK
CK
LD
1
CLR
R
M1
G2
14
1, 2T/1C3
G4
Q
Q
A
B
3
3D
4R
A
M1
G2
13
12
11
1, 2T/1C3
G4
3D
4R
4
B
M1
G2
1, 2T/1C3
Q
C
G4
3D
4R
5
C
M1
G2
1, 2T/1C3
Q
D
G4
3D
4R
6
D
†
For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown
on the logic diagram of the D/T flip-flops.
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
3
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ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢆꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆ ꢇꢆ ꢈ
ꢃꢋ ꢌꢍ ꢎ ꢀꢏ ꢁꢐ ꢑ ꢒ ꢓꢁ ꢓꢔ ꢀ ꢌꢍ ꢁ ꢈꢒꢏ ꢐꢓ ꢔꢁ ꢎꢕꢒ ꢀ
SCLS404E − APRIL 1998 − REVISED APRIL 2005
logic symbol, each D/T flip-flop
LD (Load)
M1
G2
TE (Toggle Enable)
CK (Clock)
1, 2T/1C3
G4
Q (Output)
D (Inverted Data)
R (Inverted Reset)
3D
4R
logic diagram, each D/T flip-flop (positive logic)
CK
LD
TE
†
TG
TG
LD
TG
Q
TG
†
LD
†
CK
D
R
†
CK
TG
TG
†
†
CK
CK
†
The origins of LD and CK are shown in the overall logic diagram of the device.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢆ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢆꢈ
ꢃ ꢋꢌꢍ ꢎ ꢀꢏ ꢁꢐꢑꢒꢓ ꢁꢓ ꢔꢀ ꢌꢍ ꢁꢈꢒꢏ ꢐꢓ ꢔ ꢁꢎ ꢕꢒ ꢀ
SCLS404E − APRIL 1998 − REVISED APRIL 2005
typical clear, preset, count, and inhibit sequence
The following sequence is illustrated below:
1. Clear outputs to zero (asynchronous)
2. Preset to binary 12
3. Count to 13, 14, 15, 0, 1, and 2
4. Inhibit
CLR
LOAD
A
B
Data
Inputs
C
D
CLK
ENP
ENT
Q
A
Q
Q
Q
B
C
D
Data
Outputs
RCO
12
13
14
15
0
1
2
Count
Inhibit
Sync Preset
Clear
Async
Clear
5
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ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢆꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆ ꢇꢆ ꢈ
ꢃꢋ ꢌꢍ ꢎ ꢀꢏ ꢁꢐ ꢑ ꢒ ꢓꢁ ꢓꢔ ꢀ ꢌꢍ ꢁ ꢈꢒꢏ ꢐꢓ ꢔꢁ ꢎꢕꢒ ꢀ
SCLS404E − APRIL 1998 − REVISED APRIL 2005
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Output voltage range applied in high or low state, V (see Notes 1 and 2) . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Voltage range applied to any output in the power-off state, V (see Note 1) . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
OK
O
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢆ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢆꢈ
ꢃ ꢋꢌꢍ ꢎ ꢀꢏ ꢁꢐꢑꢒꢓ ꢁꢓ ꢔꢀ ꢌꢍ ꢁꢈꢒꢏ ꢐꢓ ꢔ ꢁꢎ ꢕꢒ ꢀ
SCLS404E − APRIL 1998 − REVISED APRIL 2005
recommended operating conditions (see Note 4)
SN54LV161A
SN74LV161A
UNIT
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
5.5
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
1.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
V
V
× 0.7
V
V
V
× 0.7
CC
CC
CC
CC
CC
CC
High-level input voltage
V
V
IH
× 0.7
× 0.7
× 0.7
× 0.7
0.5
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
× 0.3
× 0.3
× 0.3
5.5
V
× 0.3
× 0.3
× 0.3
5.5
CC
CC
CC
CC
CC
CC
V
IL
Low-level input voltage
V
V
V
V
V
V
Input voltage
0
0
0
0
V
V
I
Output voltage
V
V
CC
O
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
−50
−2
−50
−2
−6
−12
50
2
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
I
High-level output current
Low-level output current
OH
OL
−6
mA
−12
50
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
2
I
6
6
mA
12
12
200
100
20
85
0
0
0
200
100
20
0
0
0
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
−55
125
−40
°C
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV161A
SN74LV161A
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
TYP
MAX
MIN
TYP
MAX
I
I
I
I
I
I
I
I
= −50 µA
2 V to 5.5 V
2.3 V
V
−0.1
2
V
CC
−0.1
2
OH
OH
OH
OH
OL
OL
OL
OL
CC
= −2 mA
= −6 mA
= −12 mA
= 50 µA
= 2 mA
V
V
V
OH
3 V
2.48
3.8
2.48
3.8
4.5 V
2 V to 5.5 V
2.3 V
0.1
0.4
0.44
0.55
1
0.1
0.4
0.44
0.55
1
V
OL
= 6 mA
3 V
= 12 mA
4.5 V
I
I
I
V = 5.5 V or GND
0 to 5.5 V
5.5 V
µA
µA
µA
pF
I
I
V = V
CC
or GND,
I = 0
O
20
20
CC
off
I
V or V = 0 to 5.5 V
0
5
5
I
O
C
V = V
or GND
3.3 V
1.8
1.8
i
I
CC
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ꢞ
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ꢡ
ꢢ
ꢞ ꢙꢣ ꢢ ꢮꢡ ꢝꢦ ꢜꢚ ꢛ ꢞ ꢝꢢ ꢘꢚ ꢢꢟꢡ ꢘ ꢙꢡ ꢛ ꢡ ꢧꢦ ꢝꢜ ꢟꢞꢘ ꢛ ꢬ ꢚꢘꢙ ꢝꢟꢘ ꢢꢝꢘ ꢚꢞꢡ ꢪ
ꢘ
ꢛ
ꢦ
ꢡ
ꢛ
ꢡ
ꢦ
ꢯ
ꢡ
ꢛ
ꢘ
ꢙ
ꢡ
ꢦ
ꢚ
ꢮ
ꢙ
ꢘ
ꢘ
ꢝ
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢆꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆ ꢇꢆ ꢈ
ꢃꢋ ꢌꢍ ꢎ ꢀꢏ ꢁꢐ ꢑ ꢒ ꢓꢁ ꢓꢔ ꢀ ꢌꢍ ꢁ ꢈꢒꢏ ꢐꢓ ꢔꢁ ꢎꢕꢒ ꢀ
SCLS404E − APRIL 1998 − REVISED APRIL 2005
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 2.5 V 0.2 V
CC
T
= 25°C
SN54LV161A SN74LV161A
A
UNIT
MIN
7
MAX
MIN
7
MAX
MIN
7
MAX
CLK high or low
CLR low
t
w
Pulse duration
ns
7
7
7
CLR
4.5
7.5
9.5
10
1.5
4.5
8.5
11
4.5
8.5
11
Data (A, B, C, and D)
ENP, ENT
t
t
ns
ns
Setup time before CLK↑
su
LOAD low
11.5
1.5
11.5
1.5
Hold time, all synchronous inputs after CLK↑
h
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 3.3 V 0.3 V
CC
T
= 25°C
SN54LV161A SN74LV161A
A
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
CLK high or low
CLR low
t
w
Pulse duration
ns
5
5
5
CLR
2.5
5.5
7.5
8
2.5
6.5
9
2.5
6.5
9
Data (A, B, C, and D)
ENP, ENT
t
t
ns
ns
Setup time before CLK↑
su
LOAD low
9.5
1
9.5
1
Hold time, all synchronous inputs after CLK↑
1
h
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V 0.5 V
CC
T
= 25°C
SN54LV161A SN74LV161A
A
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
CLK high or low
CLR low
t
w
Pulse duration
ns
5
5
5
CLR
1.5
4.5
5
1.5
4.5
6
1.5
4.5
6
Data (A, B, C, and D)
ENP, ENT
t
t
ns
ns
Setup time before CLK↑
su
LOAD low
5
6
6
Hold time, all synchronous inputs after CLK↑
1
1
1
h
ꢤ
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ꢎ
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ꢥ
ꢝ
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ꢠ
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ꢘ
ꢚ
ꢝ
ꢢ
ꢞ
ꢝ
ꢢ
ꢞ
ꢡ
ꢦ
ꢢ
ꢛ
ꢧ
ꢦ
ꢝ
ꢜ
ꢟ
ꢞ
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ꢘ
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ꢥ
ꢝ
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ꢚ
ꢞ
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ꢮ
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ꢧ
ꢙ
ꢢ
ꢜ
ꢣ
ꢛ
ꢛ
ꢞ
ꢡ
ꢣ
ꢝ
ꢝ
ꢥ
ꢜ
ꢡ
ꢢ
ꢯ
ꢡ
ꢮ
ꢛ
ꢩ
ꢝ
ꢝ
ꢣ
ꢡ
ꢧ
ꢩ
ꢧ
ꢠ
ꢡ
ꢎ
ꢜ
ꢢ
ꢡ
ꢟ
ꢘ
ꢪ
ꢫ
ꢞ
ꢐ
ꢙ
ꢢ
ꢚ
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ꢛ
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ꢙ
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ꢞ
ꢘ
ꢠ
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ꢦ
ꢡ
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ꢚ
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ꢛ
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ꢝ
ꢘ
ꢛ
ꢘ
ꢚ
ꢞ
ꢦ
ꢞ
ꢜ
ꢣ
ꢦ
ꢘ
ꢯ
ꢣ
ꢡ
ꢣ
ꢢ
ꢡ
ꢜ
ꢝ
ꢘ
ꢙ
ꢘ
ꢡ
ꢦ
ꢛ
ꢧ
ꢚ
ꢥ
ꢚ
ꢞ
ꢣ
ꢘ
ꢚ
ꢝ
ꢦ
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ꢜ
ꢡ
ꢟ
ꢛ
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ꢮ
ꢛ
ꢪ
ꢣ
ꢘ
ꢛ
ꢍ
ꢦ
ꢟ
ꢡ
ꢛ
ꢡ
ꢛ
ꢘ
ꢙ
ꢦ
ꢚ
ꢮ
ꢙ
ꢘ
ꢝ
ꢞ
ꢙ
ꢮ
ꢡ
ꢝ
ꢦ
ꢚ
ꢛ
ꢢ
ꢘ
ꢚ
ꢢ
ꢡ
ꢘ
ꢙ
ꢡ
ꢦ
ꢝ
ꢛ
ꢬ
ꢝ
ꢟ
ꢘ
ꢚ
ꢡ
ꢪ
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢆ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢆꢈ
ꢃ ꢋꢌꢍ ꢎ ꢀꢏ ꢁꢐꢑꢒꢓ ꢁꢓ ꢔꢀ ꢌꢍ ꢁꢈꢒꢏ ꢐꢓ ꢔ ꢁꢎ ꢕꢒ ꢀ
SCLS404E − APRIL 1998 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range,
V
= 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
125*
95
SN54LV161A SN74LV161A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
50*
30
MAX
MIN
40*
25
MAX
MIN
40
25
1
MAX
C
C
= 15 pF
= 50 pF
L
L
f
MHz
max
pd
7.9* 16.2*
1* 19.5*
19.5
20.5
Q
RCO
(count mode)
8.9* 17*
1* 20.5*
1
1
CLK
t
RCO
(preset mode)
11.9* 20.6*
8.3* 15.7*
1* 24.5*
24.5
C
= 15 pF
ns
L
1*
19*
1
1
1
1
19
20.5
20
ENT
CLR
RCO
Q
8.8*
17*
1* 20.5*
t
t
t
PHL
9.8* 16.6*
1*
1
20*
RCO
Q
10.5
11.7
19.2
20
22.5
22.5
RCO
(count mode)
1
1
23.5
27.5
1
1
23.5
27.5
CLK
pd
RCO
(preset mode)
14.5
23.6
C
= 50 pF
ns
L
11
11.4
12.6
18.7
20
1
1
1
22
23.5
23
1
1
1
22
23.5
23
ENT
CLR
RCO
Q
PHL
19.6
RCO
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
ꢤ
ꢒ
ꢓ
ꢗ
ꢔ
ꢐ
ꢎ
ꢤ
ꢒ
ꢕ
ꢅ
ꢍ
ꢕ
ꢖ
ꢚ
ꢢ
ꢥ
ꢝ
ꢦ
ꢠ
ꢣ
ꢘ
ꢚ
ꢝ
ꢢ
ꢞ
ꢝ
ꢢ
ꢞ
ꢡ
ꢦ
ꢢ
ꢛ
ꢧ
ꢦ
ꢝ
ꢜ
ꢟ
ꢜꢡ ꢛ ꢚ ꢮꢢ ꢧꢙ ꢣ ꢛ ꢡ ꢝꢥ ꢜꢡ ꢯ ꢡ ꢩꢝ ꢧꢠꢡ ꢢꢘꢪ ꢐ ꢙꢣ ꢦꢣ ꢞꢘ ꢡꢦ ꢚꢛ ꢘꢚ ꢞ ꢜꢣ ꢘꢣ ꢣꢢ ꢜ ꢝꢘ ꢙꢡꢦ
ꢞ
ꢘ
ꢛ
ꢚ
ꢢ
ꢘ
ꢙ
ꢡ
ꢥ
ꢝ
ꢦ
ꢠ
ꢣ
ꢘ
ꢚ
ꢯ
ꢡ
ꢝ
ꢦ
ꢛ
ꢧ
ꢡ
ꢞ
ꢚ
ꢥ
ꢚ
ꢞ
ꢣ
ꢘ
ꢚ
ꢝ
ꢢ
ꢛ
ꢣ
ꢦ
ꢡ
ꢜ
ꢡ
ꢛ
ꢚ
ꢮ
ꢢ
ꢮ
ꢝ
ꢣ
ꢩ
ꢛ
ꢪ
ꢎ
ꢡ
ꢫ
ꢣ
ꢛ
ꢍ
ꢢ
ꢛ
ꢘ
ꢦ
ꢟ
ꢠ
ꢡ
ꢢ
ꢞ ꢙꢣ ꢢ ꢮꢡ ꢝꢦ ꢜꢚ ꢛ ꢞ ꢝꢢ ꢘꢚ ꢢꢟꢡ ꢘ ꢙꢡ ꢛ ꢡ ꢧꢦ ꢝꢜ ꢟꢞꢘ ꢛ ꢬ ꢚꢘꢙ ꢝꢟꢘ ꢢꢝꢘ ꢚꢞꢡ ꢪ
ꢘ
ꢛ
ꢦ
ꢡ
ꢛ
ꢡ
ꢦ
ꢯ
ꢡ
ꢛ
ꢘ
ꢙ
ꢡ
ꢦ
ꢚ
ꢮ
ꢙ
ꢘ
ꢘ
ꢝ
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢆꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆ ꢇꢆ ꢈ
ꢃꢋ ꢌꢍ ꢎ ꢀꢏ ꢁꢐ ꢑ ꢒ ꢓꢁ ꢓꢔ ꢀ ꢌꢍ ꢁ ꢈꢒꢏ ꢐꢓ ꢔꢁ ꢎꢕꢒ ꢀ
SCLS404E − APRIL 1998 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
165*
125
SN54LV161A SN74LV161A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
80*
55
MAX
MIN
70*
50
MAX
MIN
70
50
1
MAX
C
= 15 pF*
= 50 pF
L
f
MHz
max
C
L
L
6
12.8
13.6
1*
15*
16*
15
16
Q
RCO
(count mode)
6.7
8.6
1*
1*
1
1
CLK
t *
pd
RCO
(preset mode)
17.2
20*
20
C
= 15 pF
ns
6.2
6.5
7.2
7.8
12.3
13.6
13.2
16.3
1* 14.5*
1* 16*
1* 15.5*
1
1
1
1
14.5
16
ENT
CLR
RCO
Q
t
t
t
*
PHL
15.5
18.5
RCO
Q
1
1
18.5
19.5
RCO
(count mode)
8.7
17.1
20.7
1
1
19.5
23.5
CLK
pd
RCO
(preset mode)
10.6
1
23.5
C
= 50 pF
ns
L
8.3
8.4
9.2
15.8
17.1
16.7
1
1
1
18
19.5
19
1
1
1
18
19.5
19
ENT
CLR
RCO
Q
PHL
RCO
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢆ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢆꢈ
ꢃ ꢋꢌꢍ ꢎ ꢀꢏ ꢁꢐꢑꢒꢓ ꢁꢓ ꢔꢀ ꢌꢍ ꢁꢈꢒꢏ ꢐꢓ ꢔ ꢁꢎ ꢕꢒ ꢀ
SCLS404E − APRIL 1998 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range,
V
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
220
SN54LV161A SN74LV161A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
135*
95
MAX
MIN
115*
85
MAX
MIN
115
85
MAX
C
C
= 15 pF
= 50 pF
L
L
f
MHz
max
pd
165
4.5*
8.1*
8.1*
1*
9.5*
9.5*
1
9.5
9.5
Q
RCO
(count mode)
5.1*
1*
1
1
CLK
t
RCO
(preset mode)
6.3* 10.3*
1*
1*
12*
12
C
= 15 pF
ns
L
4.8*
4.9*
5.5*
5.9
8.1*
9*
9.5*
1
1
1
1
9.5
10.5
10
ENT
CLR
RCO
Q
1* 10.5*
t
t
t
PHL
8.6*
10.1
1*
1
10*
RCO
Q
11.5
11.5
RCO
(count mode)
6.6
7.8
10.1
12.3
1
1
11.5
14
1
1
11.5
14
CLK
pd
RCO
(preset mode)
C
= 50 pF
ns
L
6.1
6.3
6.9
10.1
11
1
1
1
11.5
12.5
12
1
1
1
11.5
12.5
12
ENT
CLR
RCO
Q
PHL
10.6
RCO
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, V
= 3.3 V, C = 50 pF, T = 25°C (see Note 5)
CC
L
A
SN74LV161A
PARAMETER
UNIT
MIN
TYP
0.3
−0.2
3
MAX
V
V
V
V
V
Quiet output, maximum dynamic V
0.8
V
V
V
V
V
OL(P)
OL(V)
OH(V)
IH(D)
IL(D)
OL
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
−0.8
OL
OH
2.31
0.99
NOTE 5: Characteristics are for surface-mount packages only.
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
= 50 pF, f = 10 MHz
L
V
TYP
23.6
25.8
UNIT
CC
3.3 V
C
Power dissipation capacitance
C
pF
pd
5 V
ꢤ
ꢒ
ꢓ
ꢗ
ꢔ
ꢐ
ꢎ
ꢤ
ꢒ
ꢕ
ꢅ
ꢍ
ꢕ
ꢖ
ꢚ
ꢢ
ꢥ
ꢝ
ꢦ
ꢠ
ꢣ
ꢘ
ꢚ
ꢝ
ꢢ
ꢞ
ꢝ
ꢢ
ꢞ
ꢡ
ꢦ
ꢢ
ꢛ
ꢧ
ꢦ
ꢝ
ꢜ
ꢟ
ꢜꢡ ꢛ ꢚ ꢮꢢ ꢧꢙ ꢣ ꢛ ꢡ ꢝꢥ ꢜꢡ ꢯ ꢡ ꢩꢝ ꢧꢠꢡ ꢢꢘꢪ ꢐ ꢙꢣ ꢦꢣ ꢞꢘ ꢡꢦ ꢚꢛ ꢘꢚ ꢞ ꢜꢣ ꢘꢣ ꢣꢢ ꢜ ꢝꢘ ꢙꢡꢦ
ꢞ
ꢘ
ꢛ
ꢚ
ꢢ
ꢘ
ꢙ
ꢡ
ꢥ
ꢝ
ꢦ
ꢠ
ꢣ
ꢘ
ꢚ
ꢯ
ꢡ
ꢝ
ꢦ
ꢛ
ꢧ
ꢡ
ꢞ
ꢚ
ꢥ
ꢚ
ꢞ
ꢣ
ꢘ
ꢚ
ꢝ
ꢢ
ꢛ
ꢣ
ꢦ
ꢡ
ꢜ
ꢡ
ꢛ
ꢚ
ꢮ
ꢢ
ꢮ
ꢝ
ꢣ
ꢩ
ꢛ
ꢪ
ꢎ
ꢡ
ꢫ
ꢣ
ꢛ
ꢍ
ꢢ
ꢛ
ꢘ
ꢦ
ꢟ
ꢠ
ꢡ
ꢢ
ꢞ ꢙꢣ ꢢ ꢮꢡ ꢝꢦ ꢜꢚ ꢛ ꢞ ꢝꢢ ꢘꢚ ꢢꢟꢡ ꢘ ꢙꢡ ꢛ ꢡ ꢧꢦ ꢝꢜ ꢟꢞꢘ ꢛ ꢬ ꢚꢘꢙ ꢝꢟꢘ ꢢꢝꢘ ꢚꢞꢡ ꢪ
ꢘ
ꢛ
ꢦ
ꢡ
ꢛ
ꢡ
ꢦ
ꢯ
ꢡ
ꢛ
ꢘ
ꢙ
ꢡ
ꢦ
ꢚ
ꢮ
ꢙ
ꢘ
ꢘ
ꢝ
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢆꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆ ꢇꢆ ꢈ
ꢃꢋ ꢌꢍ ꢎ ꢀꢏ ꢁꢐ ꢑ ꢒ ꢓꢁ ꢓꢔ ꢀ ꢌꢍ ꢁ ꢈꢒꢏ ꢐꢓ ꢔꢁ ꢎꢕꢒ ꢀ
SCLS404E − APRIL 1998 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
GND
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
CC
Timing Input
0 V
t
w
t
h
t
V
CC
su
V
CC
50% V
CC
50% V
CC
Input
Input
50% V
CC
50% V
CC
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
CC
50% V
50% V
CC
50% V
CC
CC
0 V
0 V
t
t
t
t
t
PLH
PHL
PZL
PLZ
Output
Waveform 1
V
≈V
OH
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
V
V
+ 0.3 V
S1 at V
(see Note B)
OL
CC
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
− 0.3 V
OH
50% V
CC
50% V
50% V
CC
CC
≈0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PLH
are the same as t
.
dis
PLZ
PZL
PHL
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
9-Aug-2005
PACKAGING INFORMATION
Orderable Device
SN74LV161AD
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV161ADBR
SN74LV161ADBRE4
SN74LV161ADE4
SN74LV161ADGVR
SN74LV161ADGVRE4
SN74LV161ADR
SSOP
SSOP
SOIC
DB
DB
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TVSOP
TVSOP
SOIC
DGV
DGV
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV161ADRE4
SN74LV161ANSR
SN74LV161ANSRE4
SN74LV161APW
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
NS
NS
PW
PW
PW
PW
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV161APWG4
SN74LV161APWR
SN74LV161APWRG4
SN74LV161APWT
SN74LV161APWTE4
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Aug-2005
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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