SNJ55LBC173J [TI]

QUADRUPLE LOW-POWER DIFFERENTIAL RECEIVER; 翻两番低功耗差分接收器
SNJ55LBC173J
型号: SNJ55LBC173J
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

QUADRUPLE LOW-POWER DIFFERENTIAL RECEIVER
翻两番低功耗差分接收器

线路驱动器或接收器 驱动程序和接口 接口集成电路 信息通信管理
文件: 总12页 (文件大小:312K)
中文:  中文翻译
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SN55LBC173  
QUADRUPLE LOW-POWER DIFFERENTIAL RECEIVER  
SGLS081A – MARCH 1995 – REVISED JUNE 2000  
J OR W PACKAGE  
Meets EIA Standards RS-422-A, RS-423-A,  
RS-485, and CCITT V.11  
(TOP VIEW)  
Designed to Operate With Pulse Durations  
as Short as 20 ns  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
1B  
1A  
CC  
4B  
4A  
4Y  
G
Designed for Multipoint Bus Transmission  
on Long Bus Lines in Noisy Environments  
1Y  
G
Input Sensitivity . . . ±200 mV  
2Y  
3Y  
3A  
3B  
Low-Power Consumption . . . 20 mA Max  
Open-Circuit Fail-Safe Design  
2A  
2B  
GND  
Pin Compatible With SN75173 and  
AM26LS32  
FK PACKAGE  
(TOP VIEW)  
description  
The SN55LBC173 is a monolithic quadruple  
differential line receiver with 3-state outputs  
designed to meet the requirements of the EIA  
standards RS-422-A, RS-423-A, RS-485, and  
CCITT V.11. This device is optimized for balanced  
multipointbustransmissionatdataratesuptoand  
exceeding 10 million bits per second. The four  
receivers share two ORed enable inputs, one  
active when high, the other active when low. Each  
receiver features high input impedance, input  
hysteresis for increased noise immunity, and input  
sensitivityof±200mVoveracommon-modeinput  
voltage range of 12 V to –7 V. Fail-safe design  
ensures that if the inputs are open circuited, the  
output is always high. The SN55LBC173 is  
designed using the Texas Instruments proprietary  
LinBiCMOS technology that provides low power  
consumption, high switching speeds, and  
robustness.  
3
4
2
1
20 19  
1Y  
G
4A  
4Y  
NC  
G
18  
17  
16  
15  
14  
5
6
7
NC  
2Y  
2A  
3Y  
8
9
10 11 12 13  
NC – No internal connection  
This device offers optimum performance when used with the SN55LBC172M quadruple line driver. The  
SN55LBC173 is available in the 16-pin CDIP (J), the 16-pin CPAK (W), or the 20-pin LCCC (FK) packages.  
The SN55LBC173 is characterized over the military temperature range of 55°C to 125°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
LinBiCMOS is a trademark of Texas Instruments.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN55LBC173  
QUADRUPLE LOW-POWER DIFFERENTIAL RECEIVER  
SGLS081A – MARCH 1995 – REVISED JUNE 2000  
FUNCTION TABLE  
(each receiver)  
ENABLES  
DIFFERENTIAL INPUTS  
A–B  
OUTPUT  
Y
G
G
H
X
X
L
H
H
V
ID  
0.2 V  
H
X
X
L
?
?
0.2 V < V < 0.2 V  
ID  
H
X
X
L
L
L
V
ID  
0.2 V  
X
L
H
Z
H
X
X
L
H
H
Open circuit  
H = high level, L = low level, X = irrelevant,  
Z = high impedance (off), ? = indeterminate  
logic diagram (positive logic)  
logic symbol  
4
G
4
G
1  
12  
12  
G
G
2
1A  
2
1A  
1
3
3
5
1Y  
1
1Y  
2Y  
3Y  
4Y  
1B  
1B  
6
2A  
7
2B  
10  
3A  
9
3B  
14  
4A  
15  
4B  
5
11  
13  
6
2A  
2Y  
3Y  
4Y  
7
2B  
10  
3A  
9
11  
13  
3B  
This symbol is in accordance with ANSI/IEEE Std 91-1984  
and IEC Publication 617-12.  
14  
4A  
15  
Pin numbers shown are for the J or W package.  
4B  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN55LBC173  
QUADRUPLE LOW-POWER DIFFERENTIAL RECEIVER  
SGLS081A – MARCH 1995 – REVISED JUNE 2000  
schematics of inputs and outputs  
EQUIVALENT OF A AND B INPUTS  
TYPICAL OF ALL OUTPUTS  
TYPICAL OF G AND G INPUTS  
V
CC  
V
CC  
V
CC  
100 k  
3 kΩ  
A Only  
Receiver  
Input  
Input  
18 kΩ  
Y Output  
100 kΩ  
B Only  
12 kΩ  
1 kΩ  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range, V  
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 7 V  
CC  
Input voltage, V (A or B inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V  
I
Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V  
ID  
Data and control voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 7 V  
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table  
Operating free-air temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C to 125°C  
A
Storage temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C  
stg  
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. All voltage values are with respect to GND.  
2. Differential input voltage is measured at the noninverting input with respect to the corresponding inverting input.  
DISSIPATION RATING TABLE  
T
25°C  
DERATING FACTOR  
T = 125°C  
A
POWER RATING  
A
PACKAGE  
POWER RATING  
ABOVE T = 25°C  
A
FK  
J
1375 mW  
11.0 mW/°C  
11.0 mW/°C  
8.0 mW/°C  
275 mW  
1375 mW  
275 mW  
W
1000 mW  
200 mW  
recommended operating conditions  
MIN NOM  
4.75  
MAX  
5.25  
12  
UNIT  
V
Supply voltage, V  
CC  
5
Common-mode input voltage, V  
IC  
–7  
V
Differential input voltage, V  
±6  
V
ID  
High-level input voltage, V  
IH  
2
V
G inputs  
Low-level input voltage, V  
0.8  
–8  
V
IL  
High-level output current, I  
mA  
mA  
°C  
OH  
OL  
Low-level output current, I  
16  
Operating free-air temperature, T  
55  
125  
A
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN55LBC173  
QUADRUPLE LOW-POWER DIFFERENTIAL RECEIVER  
SGLS081A – MARCH 1995 – REVISED JUNE 2000  
electrical characteristics over recommended ranges of supply voltage and operating free-air  
temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN TYP  
MAX  
UNIT  
V
V
V
V
V
V
Positive-going input threshold voltage  
Negative-going input threshold voltage  
I
I
= 8 mA  
= 8 mA  
0.2  
IT+  
IT–  
hys  
IK  
O
0.2  
V
O
Hysteresis voltage (V  
IT+  
– V  
)
45  
0.9  
4.5  
mV  
V
IT–  
Enable input clamp voltage  
High-level output voltage  
I = 18 mA  
1.5  
I
V
V
V
V
V
V
V
V
= 200 mV,  
I
I
I
= 8 mA  
= 8 mA  
3.5  
V
OH  
ID  
ID  
ID  
O
OH  
OL  
OL  
= 200 mV,  
= 200 mV,  
0.3  
0.5  
0.7  
±20  
1
V
OL  
Low-level output voltage  
V
= 8 mA,  
T = 125°C  
A
I
High-impedance-state output current  
= 0 V to V  
= 12 V,  
µA  
OZ  
CC  
V
V
V
V
= 5 V, Other inputs at 0 V  
= 0 V, Other inputs at 0 V  
= 5 V, Other inputs at 0 V  
= 0 V, Other inputs at 0 V  
0.7  
0.8  
IH  
IH  
IH  
IH  
CC  
CC  
CC  
CC  
= 12 V,  
1
I
I
Bus input current  
A or B inputs  
mA  
= 7 V,  
= 7 V,  
0.5  
0.4  
0.8  
0.8  
High-level input  
current  
I
IH  
V
IH  
= 5 V  
±20  
µA  
I
I
Low-level input current  
V
V
= 0 V  
= 0  
20  
µA  
IL  
IL  
Short-circuit output current  
80 120  
mA  
OS  
O
Outputs enabled,  
Outputs disabled  
I
O
= 0,  
V
ID  
= 5 V  
11  
20  
I
Supply current  
mA  
CC  
0.9  
1.4  
All typical values are at V  
= 5 V and T = 25°C.  
CC  
A
switching characteristics, V  
= 5 V, C = 15 pF  
L
CC  
PARAMETER  
TEST CONDITIONS  
T
MIN  
11  
TYP  
MAX  
30  
35  
35  
35  
40  
45  
30  
35  
40  
55  
40  
45  
6
UNIT  
A
25°C  
22  
V
= 1.5 V to 1.5 V,  
ID  
See Figure 1  
t
t
t
t
t
t
t
Propagation delay time, high-to-low-level output  
Propagation delay time, low-to-high-level output  
Output enable time to high level  
ns  
PHL  
PLH  
PZH  
PZL  
PHZ  
PLZ  
sk(p)  
55°C to 125°C  
25°C  
11  
11  
22  
17  
18  
30  
25  
0.5  
V
= 1.5 V to 1.5 V,  
See Figure 1  
ID  
ns  
ns  
ns  
ns  
ns  
ns  
55°C to 125°C  
25°C  
11  
See Figure 2  
55°C to 125°C  
25°C  
Output enable time to low level  
See Figure 3  
See Figure 2  
See Figure 3  
See Figure 1  
55°C to 125°C  
25°C  
Output disable time from high level  
Output disable time from low level  
55°C to 125°C  
25°C  
55°C to 125°C  
25°C  
Pulse skew (|t  
– t |)  
PHL PLH  
55°C to 125°C  
25°C  
7
5
10  
16  
t
t
Transition time  
See Figure 1  
ns  
55°C to 125°C  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN55LBC173  
QUADRUPLE LOW-POWER DIFFERENTIAL RECEIVER  
SGLS081A – MARCH 1995 – REVISED JUNE 2000  
PARAMETER MEASUREMENT INFORMATION  
1.5 V  
Generator  
(see Note A)  
Input  
t
0 V  
0 V  
50 Ω  
Output  
= 15 pF  
– 1.5 V  
C
t
L
PLH  
PHL  
(see Note B)  
V
OH  
OL  
90%  
10%  
Output  
1.3 V  
1.3 V  
V
t
t
t
t
2 V  
VOLTAGE WAVEFORMS  
TEST CIRCUIT  
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle 50%, t 6 ns,  
r
t 6 ns, Z = 50 .  
f
O
B.  
C
includes probe and jig capacitance.  
L
Figure 1. t and t Test Circuit and Voltage Waveforms  
pd  
t
V
CC  
2 kΩ  
Input  
Output  
1.5 V  
S1  
3 V  
1.3 V  
1.3 V  
C
= 15 pF  
0 V  
L
(see Note B)  
t
t
PHZ  
PZH  
5 kΩ  
See Note C  
0.5 V  
V
OH  
Output  
S1 Open  
1.3 V  
S1 Closed  
2 V  
1.4 V  
0 V  
Generator  
(see Note A)  
VOLTAGE WAVEFORMS  
50 Ω  
(see Note D)  
TEST CIRCUIT  
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle 50%, t 6 ns,  
r
t 6 ns, Z = 50 .  
f
O
B.  
C
includes probe and jig capacitance.  
L
C. All diodes are 1N916 or equivalent.  
D. To test the active-low enable G, ground G and apply an inverted input waveform to G.  
Figure 2. t  
and t  
Test Circuit and Voltage Waveforms  
PHZ  
PZH  
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN55LBC173  
QUADRUPLE LOW-POWER DIFFERENTIAL RECEIVER  
SGLS081A – MARCH 1995 – REVISED JUNE 2000  
PARAMETER MEASUREMENT INFORMATION  
V
CC  
2 kΩ  
Output  
1.5 V  
3 V  
0 V  
Input  
t
C
= 15 pF  
1.3 V  
1.3 V  
L
(see Note B)  
5 kΩ  
See Note C  
t
PZL  
PLZ  
S2 Closed  
1.4 V  
S2 Open  
2 V  
Output  
1.3 V  
Generator  
V
OL  
(see Note A)  
S2  
0.5 V  
VOLTAGE WAVEFORMS  
50 Ω  
(see Note D)  
TEST CIRCUIT  
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle 50%, t 6 ns,  
r
t 6 ns, Z = 50 .  
f
O
B.  
C
includes probe and jig capacitance.  
L
C. All diodes are 1N916 or equivalent.  
D. To test the active-low enable G, ground G and apply an inverted input waveform to G.  
Figure 3. t  
and t  
Test Circuit and Voltage Waveforms  
PZL  
PLZ  
TYPICAL CHARACTERISTICS  
OUTPUT VOLTAGE  
vs  
HIGH-LEVEL OUTPUT VOLTAGE  
vs  
DIFFERENTIAL INPUT VOLTAGE  
HIGH-LEVEL OUTPUT CURRENT  
5.5  
5
4.5  
4
V
T
A
= 5 V  
= 25°C  
CC  
V = 5.25 V  
CC  
4.5  
4
3.5  
3
V
CC  
= 5 V  
3.5  
3
V
CC  
= 4.75 V  
2.5  
2
2.5  
2
1.5  
1
1.5  
1
0.5  
0
V
T
A
= 0.2 V  
ID  
= 25°C  
0.5  
0
0
10 20 30 40 50 60 70 80 90 100  
0
– 4 – 8 – 12 – 16 – 20 – 24 – 28 – 32 – 36 – 40  
V
ID  
– Differential Input Voltage – mV  
I
– High-Level Output Current – mA  
OH  
Figure 4  
Figure 5  
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN55LBC173  
QUADRUPLE LOW-POWER DIFFERENTIAL RECEIVER  
SGLS081A – MARCH 1995 – REVISED JUNE 2000  
TYPICAL CHARACTERISTICS  
AVERAGE SUPPLY CURRENT  
LOW-LEVEL OUTPUT VOLTAGE  
vs  
LOW-LEVEL OUTPUT CURRENT  
vs  
FREQUENCY  
14  
12  
10  
8
660  
600  
540  
480  
420  
360  
300  
240  
180  
120  
60  
T
V
CC  
= 25°C  
= 5 V  
A
T
V
V
= 25°C  
A
= 5 V  
= 200 mV  
CC  
ID  
6
4
2
0
0
10 K  
100 K  
2 M  
10 M  
100 M  
0
3
6
9
12 15 18 21 24 27 30  
f – Frequency – Hz  
I
– Low-Level Output Current – mA  
OL  
Figure 6  
Figure 7  
BUS INPUT CURRENT  
vs  
PROPAGATION DELAY TIME  
vs  
INPUT VOLTAGE  
(COMPLEMENTARY INPUT AT 0 V)  
FREE-AIR TEMPERATURE  
1
0.8  
24.5  
24  
V
C
= 5 V  
= 15 pF  
= ±1.5 V  
T
V
= 25°C  
CC  
L
A
= 5 V  
CC  
V
IO  
0.6  
0.4  
t
PHL  
0.2  
23.5  
23  
0
– 0.2  
– 0.4  
– 0.6  
– 0.8  
– 1  
t
PLH  
22.5  
22  
The shaded region of this graph represents  
more than 1 unit load per RS-485.  
– 40 – 20  
0
20  
40  
60  
80  
100  
– 8 – 6 – 4 – 2  
0
2
4
6
8
10 12  
T
A
– Free-Air Temperature – °C  
V – Input Voltage – V  
I
Figure 8  
Figure 9  
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
18-Jul-2006  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
LCCC  
CDIP  
CFP  
Drawing  
5962-9076604Q2A  
5962-9076604QEA  
5962-9076604QFA  
SNJ55LBC173FK  
SNJ55LBC173J  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
FK  
J
20  
16  
16  
20  
16  
16  
1
1
1
1
1
1
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
POST-PLATE N / A for Pkg Type  
A42 SNPB  
A42 SNPB  
N / A for Pkg Type  
N / A for Pkg Type  
W
FK  
J
LCCC  
CDIP  
CFP  
POST-PLATE N / A for Pkg Type  
A42 SNPB  
A42 SNPB  
N / A for Pkg Type  
N / A for Pkg Type  
SNJ55LBC173W  
W
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
MECHANICAL DATA  
MLCC006B – OCTOBER 1996  
FK (S-CQCC-N**)  
LEADLESS CERAMIC CHIP CARRIER  
28 TERMINAL SHOWN  
A
B
NO. OF  
TERMINALS  
**  
18 17 16 15 14 13 12  
MIN  
MAX  
MIN  
MAX  
0.342  
(8,69)  
0.358  
(9,09)  
0.307  
(7,80)  
0.358  
(9,09)  
19  
20  
11  
10  
9
20  
28  
44  
52  
68  
84  
0.442  
(11,23)  
0.458  
(11,63)  
0.406  
(10,31)  
0.458  
(11,63)  
21  
B SQ  
22  
0.640  
(16,26)  
0.660  
(16,76)  
0.495  
(12,58)  
0.560  
(14,22)  
8
A SQ  
23  
0.739  
(18,78)  
0.761  
(19,32)  
0.495  
(12,58)  
0.560  
(14,22)  
7
24  
25  
6
0.938  
(23,83)  
0.962  
(24,43)  
0.850  
(21,6)  
0.858  
(21,8)  
5
1.141  
(28,99)  
1.165  
(29,59)  
1.047  
(26,6)  
1.063  
(27,0)  
26 27 28  
1
2
3
4
0.080 (2,03)  
0.064 (1,63)  
0.020 (0,51)  
0.010 (0,25)  
0.020 (0,51)  
0.010 (0,25)  
0.055 (1,40)  
0.045 (1,14)  
0.045 (1,14)  
0.035 (0,89)  
0.045 (1,14)  
0.035 (0,89)  
0.028 (0,71)  
0.022 (0,54)  
0.050 (1,27)  
4040140/D 10/96  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. This package can be hermetically sealed with a metal lid.  
D. The terminals are gold plated.  
E. Falls within JEDEC MS-004  
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