SNLVDS9638DGNG4 [TI]
HIGH-SPEED DIFFERENTIAL LINE DRIVERS; 高速差分线路驱动器
| 型号： | SNLVDS9638DGNG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH-SPEED DIFFERENTIAL LINE DRIVERS |
| 文件： | 总29页 (文件大小：1057K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN55LVDS31, SN65LVDS31
SN65LVDS3487, SN65LVDS9638
www.ti.com
SLLS261L–JULY 1997–REVISED JULY 2007
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
FEATURES
SN55LVDS31 . . . J OR W
SN65LVDS31 . . . D OR PW
(Marked as LVDS31 or 65LVDS31)
(TOP VIEW)
•
Meet or Exceed the Requirements of ANSI
TIA/EIA-644 Standard
•
Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and 100-Ω
Load
1A
1Y
1Z
VCC
4A
4Y
4Z
G
1
2
3
4
5
6
7
8
16
15
14
13
12
11
•
Typical Output Voltage Rise and Fall Times of
500 ps (400 Mbps)
G
2Z
2Y
3Z
•
•
•
Typical Propagation Delay Times of 1.7 ns
Operate From a Single 3.3-V Supply
2A
GND
10 3Y
3A
9
Power Dissipation 25 mW Typical Per Driver
at 200 MHz
SN55LVDS31FK
(TOP VIEW)
•
Driver at High Impedance When Disabled or
With VCC = 0
•
•
•
Bus-Terminal ESD Protection Exceeds 8 kV
Low-Voltage TTL (LVTTL) Logic Input Levels
3
2
1
20 19
1Z
G
4Y
4Z
NC
G
4
5
6
7
8
18
Pin Compatible With AM26LS31, MC3487, and
μA9638
17
16
15
14
NC
2Z
2Y
•
Cold Sparing for Space and High Reliability
Applications Requiring Redundancy
3Z
9
10 11 12 13
DESCRIPTION
The SN55LVDS31, SN65LVDS31, SN65LVDS3487,
and SN65LVDS9638 are differential line drivers that
implement the electrical characteristics of low-voltage
differential signaling (LVDS). This signaling
technique lowers the output voltage levels of 5-V
differential standard levels (such as TIA/EIA-422B) to
reduce the power, increase the switching speeds,
and allow operation with a 3.3-V supply rail. Any of
the four current-mode drivers will deliver a minimum
differential output voltage magnitude of 247 mV into
a 100-Ω load when enabled.
SN65LVDS3487D
(Marked as LVDS3487 or 65LVDS3487)
(TOP VIEW)
1A
1Y
1Z
VCC
4A
4Y
1
2
3
4
5
6
7
8
16
15
14
13
12
11
1,2EN
2Z
4Z
3,4EN
3Z
2Y
2A
GND
10 3Y
3A
9
The intended application of these devices and
signaling technique is both point-to-point and
multidrop (one driver and multiple receivers) data
transmission over controlled impedance media of
approximately 100 Ω. The transmission media may
be printed-circuit board traces, backplanes, or
cables. The ultimate rate and distance of data
transfer is dependent upon the attenuation
characteristics of the media and the noise coupling
to the environment.
SN65LVDS9638D (Marked as DK638 or LVDS38)
SN65LVDS9638DGN (Marked as L38)
SN65LVDS9638DGK (Marked as AXG)
(TOP VIEW)
VCC
1A
2A
1Y
1Z
2Y
2Z
1
2
3
4
8
7
6
5
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1997–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN55LVDS31, SN65LVDS31
SN65LVDS3487, SN65LVDS9638
www.ti.com
SLLS261L–JULY 1997–REVISED JULY 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The SN65LVDS31, SN65LVDS3487, and SN65LVDS9638 are characterized for operation from –40°C to 85°C.
The SN55LVDS31 is characterized for operation from –55°C to 125°C.
AVAILABLE OPTIONS
PACKAGE(1)
TA
SMALL OUTLINE
CHIP CARRIER
(FK)
CERAMIC DIP
(J)
FLAT PACK
(W)
MSOP
(D)
(PW)
SN65LVDS31D
SN65LVDS3487D
SN65LVDS9638D
—
SN65LVDS31PW
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
–40°C to 85°C
–55°C to 125°C
SN65LVDS9638DGN
SN65LVDS9638DGK
SNJ55LVDS31W
SN55LVDS31W
—
—
—
SNJ55LVDS31FK
SNJ55LVDS31J
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
logic symbol†
’LVDS31 logic diagram (positive logic)
SN55LVDS31, SN65LVDS31
≥ 1
4
G
12
4
G
2
3
G
G
EN
1
1Y
1Z
12
1A
6
5
2
3
1Y
1Z
7
2Y
2Z
1
2A
3A
4A
1A
10
11
6
5
2Y
2Z
3Y
3Z
4Y
4Z
9
3Y
3Z
7
2A
3A
4A
10
11
14
13
14
13
9
15
4Y
4Z
15
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
2
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SN55LVDS31, SN65LVDS31
SN65LVDS3487, SN65LVDS9638
www.ti.com
SLLS261L–JULY 1997–REVISED JULY 2007
logic symbol†
SN65LVDS3487 logic diagram
(positive logic)
SN65LVDS3487
EN
4
2
3
1Y
1Z
1
1,2EN
1A
2
3
6
5
1
1Y
1Z
2Y
2Z
4
7
1A
1,2EN
2A
6
5
2Y
2Z
7
2A
10
11
9
3Y
3Z
12
3A
3,4EN
EN
10
11
14
13
12
15
3,4EN
4A
9
3Y
3Z
4Y
4Z
3A
14
13
4Y
4Z
15
4A
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
logic symbol†
SN65LVDS9638 logic diagram
(positive logic)
SN65LVDS9638
8
8
1Y
2
1A
7
2
3
1Y
1Z
2Y
2Z
1Z
1A
2A
7
6
5
6
2Y
2Z
3
2A
5
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
3
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SN55LVDS31, SN65LVDS31
SN65LVDS3487, SN65LVDS9638
www.ti.com
SLLS261L–JULY 1997–REVISED JULY 2007
FUNCTION TABLES
SN55LVDS31, SN65LVDS31(1)
ENABLES
OUTPUTS
INPUT
A
G
H
H
X
X
L
G
X
X
L
Y
H
L
Z
L
H
L
H
L
H
H
L
L
L
H
Z
H
H
X
H
X
L
Z
L
Open
Open
H
X
L
(1) H = high level, L = low level, X = irrelevant, Z = high impedance
(off)
SN65LVDS3487(1)
OUTPUTS
INPUT A
ENABLE EN
Y
H
L
Z
L
H
L
H
H
L
H
Z
H
X
Z
L
Open
H
(1) H = high level, L = low level, X = irrelevant, Z = high impedance
(off)
SN65LVDS9638(1)
OUTPUTS
INPUT A
Y
H
L
Z
L
H
L
H
H
Open
L
(1) H = high level, L = low level
4
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SN55LVDS31, SN65LVDS31
SN65LVDS3487, SN65LVDS9638
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SLLS261L–JULY 1997–REVISED JULY 2007
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
EQUIVALENT OF EACH A INPUT
EQUIVALENT OF G, G, 1,2EN OR 3,4EN INPUTS
TYPICAL OF ALL OUTPUTS
V
CC
V
CC
V
CC
50 Ω
50 Ω
Input
Input
7 V
10 kΩ
5 Ω
Y or Z
Output
7 V
300 kΩ
7 V
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
UNIT
VCC
VI
Supply voltage range(2)
–0.5 V to 4 V
Input voltage range
–0.5 V to VCC + 0.5 V
See Dissipation Rating Table
260°C
Continuous total power dissipation
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
Storage temperature range
Tstg
–65°C to 150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages, except differential I/O bus voltages, are with respect to the network ground terminal.
DISSIPATION RATING TABLE
T
A ≤ 25°C
DERATING FACTOR(1)
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
PACKAGE
POWER RATING
D (8)
D (16)
DGK
DGN(2)
FK
725 mW
5.8 mW/°C
7.6 mW/°C
3.4 mW/°C
17.1 mW/°C
11.0 mW/°C
11.0 mW/°C
6.2 mW/°C
8.0 mW/°C
464 mW
608 mW
272 mW
1.37 W
377 mW
494 mW
221 mW
1.11 W
—
—
950 mW
425 mW
—
2.14 W
—
1375 mW
1375 mW
774 mW
880 mW
880 mW
496 mW
640 mW
715 mW
715 mW
402 mW
520 mW
275 mW
275 mW
—
J
PW (16)
W
1000 mW
200 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
(2) The PowerPAD™ must be soldered to a thermal land on the printed-circuit board. See the application note PowerPAD Thermally
Enhanced Package (SLMA002).
5
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SN55LVDS31, SN65LVDS31
SN65LVDS3487, SN65LVDS9638
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SLLS261L–JULY 1997–REVISED JULY 2007
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX UNIT
VCC
VIH
VIL
Supply voltage
3
2
3.3
3.6
V
V
V
High-level input voltage
Low-level input voltage
0.8
85
SN65 prefix
SN55 prefix
–40
–55
TA
Operating free-air temperature
°C
125
SN55LVDS31 ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
VOD
Differential output voltage magnitude
RL = 100 Ω,
RL = 100 Ω,
See Figure 2
See Figure 2
247
–50
340
454
50
mV
mV
ΔVOD
Change in differential output voltage
magnitude between logic states
VOC(SS)
ΔVOC(SS)
VOC(PP)
Steady-state common-mode output voltage
See Figure 3
See Figure 3
See Figure 3
1.125
–50
1.2 1.375
50
V
Change in steady-state common-mode output
voltage between logic states
mV
mV
Peak-to-peak common-mode output voltage
50
9
150
20
35
1
VI = 0.8 V or 2 V, Enabled, No load
ICC
Supply current
VI = 0.8 or 2 V,
RL = 100 Ω, Enabled
25
mA
VI = 0 or VCC
,
Disabled
0.25
4
IIH
IIL
High-level input current
Low-level input current
VIH = 2
20
10
–24
±12
±1
μA
μA
VIL = 0.8 V
0.1
–4
VO(Y) or VO(Z) = 0
VOD = 0
IOS
Short-circuit output current
mA
IOZ
High-impedance output current
Power-off output current
Input capacitance
VO = 0 or 2.4 V
VCC = 0,
μA
μA
pF
IO(OFF)
Ci
VO = 2.4 V
±4
3
(1) All typical values are at TA = 25°C and with VCC = 3.3 V.
SN55LVDS31 SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
tPLH
tPHL
tr
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Differential output signal rise time (20% to 80%)
Differential output signal fall time (80% to 20%)
Pulse skew (|tPHL – tPLH|)
0.5
1
1.4
1.7
0.5
0.5
0.3
0.3
5.4
2.5
8.1
7.3
4
4.5
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.4
0.4
RL = 100 Ω, CL = 10 pF,
See Figure 2
tf
1
tsk(p)
tsk(o)
tPZH
tPZL
tPHZ
tPLZ
0.6
0.6
15
15
17
15
Channel-to-channel output skew(2)
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
See Figure 4
(1) All typical values are at TA = 25°C and with VCC = 3.3 V.
(2) tsk(o) is the maximum delay time difference between drivers on the same device.
6
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SN65LVDS3487, SN65LVDS9638
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SLLS261L–JULY 1997–REVISED JULY 2007
SN65LVDSxxxx ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
SN65LVDS31
SN65LVDS3487
SN65LVDS9638
PARAMETER
TEST CONDITIONS
UNIT
MIN TYP(1) MAX
VOD
Differential output voltage magnitude
RL = 100 Ω,
RL = 100 Ω,
See Figure 2
See Figure 2
247
340 454
mV
mV
Change in differential output voltage
magnitude between logic states
ΔVOD
–50
50
1.37
VOC(SS) Steady-state common-mode output voltage
See Figure 3
See Figure 3
1.125
–50
1.2
5
V
ΔVOC(S Change in steady-state common-mode output
50
mV
mV
voltage between logic states
S)
VOC(PP) Peak-to-peak common-mode output voltage
See Figure 3
50 150
VI = 0.8 V or 2 V,
VI = 0.8 or 2 V,
Enabled, No load
RL = 100 Ω, Enabled
Disabled
9
25
20
35
1
SN65LVDS31,
SN65LVDS3487
mA
ICC
Supply current
VI = 0 or VCC
,
0.25
4.7
9
No load
8
SN65LVDS9638 VI = 0.8 V or 2 V
mA
RL = 100 Ω
13
20
10
IIH
IIL
High-level input current
Low-level input current
VIH = 2
4
μA
μA
VIL = 0.8 V
VO(Y) or VO(Z) = 0
VOD = 0
0.1
–4 –24
IOS
Short-circuit output current
mA
±12
IOZ
High-impedance output current
Power-off output current
Input capacitance
VO = 0 or 2.4 V
VCC = 0,
±1
μA
μA
pF
IO(OFF)
Ci
VO = 2.4 V
±1
3
(1) All typical values are at TA = 25°C and with VCC = 3.3 V.
SN65LVDSxxxx SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
SN65LVDS31
SN65LVDS3487
SN65LVDS9638
PARAMETER
TEST CONDITIONS
UNIT
MIN TYP(1)
MAX
tPLH
tPHL
tr
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Differential output signal rise time (20% to 80%)
Differential output signal fall time (80% to 20%)
Pulse skew (|tPHL – tPLH|)
0.5
1
1.4
1.7
0.5
0.5
0.3
0
2
2.5
0.6
0.6
0.6
0.3
800
15
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
0.4
0.4
RL = 100 Ω, CL = 10 pF,
See Figure 2
tf
tsk(p)
tsk(o)
Channel-to-channel output skew(2)
tsk(pp) Part-to-part skew(3)
tPZH
tPZL
tPHZ
tPLZ
Propagation delay time, high-impedance-to-high-level output
5.4
2.5
8.1
7.3
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
15
See Figure 4
15
15
(1) All typical values are at TA = 25°C and with VCC = 3.3 V.
(2) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, same temperature, and have identical packages and test circuits.
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SN65LVDS3487, SN65LVDS9638
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SLLS261L–JULY 1997–REVISED JULY 2007
PARAMETER MEASUREMENT INFORMATION
I
OY
Y
Z
I
I
A
V
V
OD
I
OZ
V
OY
V
OC
(V + V )/2
V
I
OY
OZ
OZ
Figure 1. Voltage and Current Definitions
2 V
Input
1.4 V
0.8 V
t
t
PLH
PHL
Y
Z
Input
(see Note A)
100 Ω
± 1%
100%
80%
V
OD
V
OD
C
= 10 pF
L
0
(2 Places)
(see Note B)
20%
0%
t
f
t
r
NOTES: A. All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
r
f
pulse width = 10 ± 0.2 ns.
B. C includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
L
Figure 2. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
49.9 Ω ± 1% (2 Places)
3 V
Y
A
Input
(see Note A)
A
0
V
OC(PP)
(see Note C)
Z
V
OC(SS)
V
OC
C
L
= 10 pF
V
OC
(2 Places)
(see Note B)
NOTES: A. All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
r
f
pulse width = 10 ± 0.2 ns.
B. C includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
L
C. The measurement of V
is made on test equipment with a –3-dB bandwidth of at least 300 MHz.
OC(PP)
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
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SN65LVDS3487, SN65LVDS9638
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SLLS261L–JULY 1997–REVISED JULY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
49.9 Ω ± 1% (2 Places)
Y
Z
0.8 V or 2 V
Inputs
(see Note A)
1.2 V
G
C
= 10 pF
V
OY
V
OZ
L
G
(2 Places)
(see Note B)
1,2EN or 3,4EN
2 V
1.4 V
G, 1,2EN,
OR 3,4EN
0.8 V
2 V
1.4 V
0.8 V
G
t
t
t
PZH
PHZ
V
OY
or
A at 2 V, G at V and Input to G
CC
or
G at GND and Input to G for ’LVDS31 Only
100%, 1.4 V
50%
V
OZ
0%, 1.2 V
t
PZL
PLZ
A at 0.8 V, G at V and Input to G
CC
or
G at GND and Input to G for ’LVDS31 Only
100%, 1.2 V
50%
0%, 1 V
V
OZ
or
V
OY
NOTES: A. All input pulses are supplied by a generator having the following characteristics: t or t < 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
r
f
pulse width = 500 ± 10 ns.
B. C includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
L
Figure 4. Enable-/Disable-Time Circuit and Definitions
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SN65LVDS3487, SN65LVDS9638
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SLLS261L–JULY 1997–REVISED JULY 2007
TYPICAL CHARACTERISTICS
SN55LVDS31, SN65LVDS31
SUPPLY CURRENT
vs
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREQUENCY
FREE-AIR TEMPERATURE
35
33
31
29
27
25
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
Four Drivers Loaded Per
Figure 3 and Switching
Simultaneously
V
= 3.6 V
CC
V
CC
= 3.3 V
V
CC
= 3 V
V
= 3 V
CC
V
CC
= 3.3 V
23
21
V
= 3.6 V
CC
19
1.1
1
17
15
50
100
150
200
−40 −20
0
20
40
60
80
100
f − Frequency − MHz
T
A
− Free-Air Temperature − °C
Figure 5.
Figure 6.
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
V
CC
= 3 V
V
= 3.3 V
CC
V
= 3.6 V
CC
1.1
1
−40 −20
0
20
40
60
80
100
T
A
− Free-Air Temperature − °C
Figure 7.
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SN65LVDS3487, SN65LVDS9638
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SLLS261L–JULY 1997–REVISED JULY 2007
APPLICATION INFORMATION
The devices are generally used as building blocks for high-speed point-to-point data transmission where ground
differences are less than 1 V. Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/receivers
approach ECL speeds without the power and dual supply requirements.
TRANSMISSION DISTANCE
vs
SIGNALING RATE
100
30% Jitter
(see Note A)
10
5% Jitter
(see Note A)
1
24 AWG UTP 96 Ω
(PVC Dielectric)
0.1
10
100
1000
Signaling Rate − Mbps
A. This parameter is the percentage of distortion of the unit interval (UI) with a pseudorandom data pattern.
Figure 8. Typical Transmission Distance Versus Signaling Rate
3.3 V
1
16
1A
V
CC
0.1 µF
0.001 µF
(see Note A)
(see Note A)
2
3
15
14
1Y
1Z
G
4A
4Y
4Z
G
Z
= 100 Ω
= 100 Ω
O
O
Z
O
= 100 Ω
4
5
13
12
V
CC
2Z
See Note B
Z
6
7
11
10
9
2Y
3Z
3Y
Z
O
= 100 Ω
2A
8
GND
3A
NOTES: A. Place a 0.1-µF and a 0.001-µF Z5U ceramic, mica, or polystyrene dielectric, 0805 size, chip capacitor between V and the ground
CC
plane. The capacitors should be located as close as possible to the device terminals.
B. Unused enable inputs should be tied to V or GND, as appropriate.
CC
Figure 9. Typical Application Circuit Schematic
11
Submit Documentation Feedback
SN55LVDS31, SN65LVDS31
SN65LVDS3487, SN65LVDS9638
www.ti.com
SLLS261L–JULY 1997–REVISED JULY 2007
APPLICATION INFORMATION (continued)
1/4 ’LVDS31
Strb/Data_TX
Tp Bias on
Twisted-Pair A
Strb/Data_Enable
TP
TP
’LVDS32
55 Ω
5 kΩ
Data/Strobe
55 Ω
3.3 V
20 kΩ
500 Ω
500 Ω
VG on
Twisted-Pair B
1 Arb_RX
20 kΩ
3.3 V
20 kΩ
500 Ω
500 Ω
2 Arb_RX
20 kΩ
3.3 V
Twisted-Pair B Only
Port_Status
7 kΩ
7 kΩ
10 kΩ
3.3 kΩ
NOTES: A. Resistors are leadless, thick film (0603), 5% tolerance.
B. Decoupling capacitance is not shown, but recommended.
C.
V
CC
is 3 V to 3.6 V.
D. The differential output voltage of the ’LVDS31 can exceed that specified by IEEE1394.
Figure 10. 100-Mbps IEEE 1394 Transceiver
12
Submit Documentation Feedback
SN55LVDS31, SN65LVDS31
SN65LVDS3487, SN65LVDS9638
www.ti.com
SLLS261L–JULY 1997–REVISED JULY 2007
APPLICATION INFORMATION (continued)
0.01 µF
≈3.6 V
1
16
1A
V
CC
5 V
0.1 µF
1N645
(see Note A)
(2 places)
2
3
15
14
1Y
1Z
G
4A
4Y
4Z
G
Z
Z
= 100 Ω
= 100 Ω
O
Z
O
= 100 Ω
4
5
13
12
V
CC
2Z
See Note B
O
6
7
11
10
2Y
3Z
3Y
Z
O
= 100 Ω
2A
9
8
GND
3A
A. Place a 0.1-μF Z5U ceramic, mica, or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground
plane. The capacitor should be located as close as possible to the device terminals.
B. Unused enable inputs should be tied to VCC or GND, as appropriate.
Figure 11. Operation With 5-V Supply
COLD SPARING
Systems using cold sparing have a redundant device electrically connected without power supplied. To support
this configuration, the spare must present a high-input impedance to the system so that it does not draw
appreciable power. In cold sparing, voltage may be applied to an I/O before and during power up of a device.
When the device is powered off, VCC must be clamped to ground and the I/O voltages applied must be within the
specified recommended operating conditions.
RELATED INFORMATION
IBIS modeling is available for this device. Contact the local TI sales office or the TI Web site at www.ti.com for
more information.
For more application guidelines, see the following documents:
•
•
•
•
•
•
Low-Voltage Differential Signaling Design Notes (SLLA014)
Interface Circuits for TIA/EIA-644 (LVDS) (SLLA038)
Reducing EMI With LVDS (SLLA030)
Slew Rate Control of LVDS Circuits (SLLA034)
Using an LVDS Receiver With RS-422 Data (SLLA031)
Evaluating the LVDS EVM (SLLA033)
13
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
5962-9762101Q2A
5962-9762101QEA
5962-9762101QFA
5962-9762101VFA
SN55LVDS31W
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
J
20
16
16
16
16
16
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
W
W
W
D
CFP
CFP
SN65LVDS31D
SOIC
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS31DG4
SN65LVDS31DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
D
16
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS31DRG4
SN65LVDS31NSR
SN65LVDS31NSRG4
SN65LVDS31PW
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
NS
NS
PW
PW
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS31PWG4
SN65LVDS31PWR
SN65LVDS31PWRG4
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS31QPWQ1
SN65LVDS31QPWRQ1
SN65LVDS3487D
OBSOLETE TSSOP
OBSOLETE TSSOP
PW
PW
D
16
16
16
TBD
TBD
Call TI
Call TI
Call TI
Call TI
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS3487DG4
SN65LVDS3487DR
SOIC
D
D
16
16
16
8
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS3487DRG4
SN65LVDS9638D
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS9638DG4
SN65LVDS9638DGK
SN65LVDS9638DGKG4
SN65LVDS9638DGKR
SN65LVDS9638DGKRG4
SN65LVDS9638DGN
SOIC
D
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP
MSOP
MSOP
MSOP
MSOP-
DGK
DGK
DGK
DGK
DGN
8
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
8
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
8
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
Power
PAD
no Sb/Br)
SN65LVDS9638DGNR
ACTIVE
ACTIVE
MSOP-
Power
PAD
DGN
DGN
8
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS9638DGNRG4
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS9638DR
ACTIVE
ACTIVE
SOIC
D
D
8
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS9638DRG4
SOIC
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SNJ55LVDS31FK
SNJ55LVDS31J
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
16
16
8
1
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
SNJ55LVDS31W
SNLVDS9638DGNG4
W
MSOP-
Power
PAD
DGN
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Nov-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
330
330
330
330
330
330
(mm)
16
SN65LVDS31DR
SN65LVDS31NSR
SN65LVDS31PWR
SN65LVDS3487DR
SN65LVDS9638DGKR
SN65LVDS9638DGNR
SN65LVDS9638DR
D
NS
PW
D
16
16
16
16
8
SITE 27
SITE 41
SITE 60
SITE 60
SITE 35
SITE 35
SITE 60
6.5
8.2
6.67
6.5
5.3
5.3
6.4
10.3
10.5
5.4
2.1
2.5
1.6
2.1
1.4
1.4
2.1
8
12
8
16
16
12
16
12
12
12
Q1
Q1
Q1
Q1
Q1
Q1
Q1
16
12
16
10.3
3.4
8
DGK
DGN
D
12
8
8
12
3.4
8
8
12
5.2
8
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Nov-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN65LVDS31DR
SN65LVDS31NSR
SN65LVDS31PWR
SN65LVDS3487DR
SN65LVDS9638DGKR
SN65LVDS9638DGNR
SN65LVDS9638DR
D
NS
PW
D
16
16
16
16
8
SITE 27
SITE 41
SITE 60
SITE 60
SITE 35
SITE 35
SITE 60
342.9
346.0
346.0
346.0
358.0
358.0
346.0
336.6
346.0
346.0
346.0
335.0
335.0
346.0
28.58
33.0
29.0
33.0
35.0
35.0
29.0
DGK
DGN
D
8
8
Pack Materials-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Wireless
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