Si5447DC [TI]
Triple-Supply Power Management IC for Powering FPGAs and DSPs; 三供应电源管理IC用于为FPGA和DSP
| 型号： | Si5447DC |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Triple-Supply Power Management IC for Powering FPGAs and DSPs |
| 文件： | 总29页 (文件大小：1312K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS75003-EP
www.ti.com
SGLS311A –DECEMBER 2006–REVISED MARCH 2011
Triple-Supply Power Management IC for Powering FPGAs and DSPs
Check for Samples: TPS75003-EP
1
FEATURES
APPLICATIONS
•
•
•
•
FPGA/DSP/ASIC Supplies
Set-Top Boxes
DSL Modems
Plasma TV Display Panels
2
•
Two 95% Efficient, 3-A Buck Controllers and
One 300-mA LDO
•
Tested and Endorsed by Xilinx for Powering
the Spartan™-3, Spartan-3E, and Spartan-3L
FPGAs
DESCRIPTION
•
Adjustable (1.2 V to 6.5 V for Bucks, 1 V to 6.5
V for LDO) Output Voltages on All Channels
The TPS75003 is a complete power management
solution for FPGA, DSP and other multi-supply
applications. The device has been tested with and
meets all of the Xilinx Spartan-3, Spartan-3E, and
Spartan-3L start-up profile requirements, including
monotonic voltage ramp and minimum voltage rail
rise time. Independent Enables for each output allow
sequencing to minimize demand on the power supply
at start-up. Soft-start on each supply limits inrush
current during start-up. Two integrated buck
controllers allow efficient, cost-effective voltage
conversion for both low and high current supplies
such as core and I/O. A 300-mA LDO is integrated to
provide an auxiliary rail such as VCCAUX on the Xilinx
Spartan-3 FPGA. All three supply voltages are
offered in user-programmable options for maximum
flexibility.
•
•
•
Input Voltage Range: 2.2 V to 6.5 V
Independent Soft-Start for Each Supply
Independent Enable for Each Supply for
Flexible Sequencing
•
•
LDO Stable with 2.2-μF Ceramic Output
Capicitor
Small, Low-Profile 4,5 mm x 3,5 mm x 0,9 mm
QFN Package
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
The TPS75003 is fully specified from –55°C to
+125°C and is offered in a QFN package, yielding a
highly compact total solution size with high power
dissipation capability.
Available in Military (–55°C/125°C)
Temperature Range(1)
•
•
•
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
(1) Additional temperature ranges available - contact factory
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
Spartan is a trademark of Xilinx, Inc.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2011, Texas Instruments Incorporated
TPS75003-EP
SGLS311A –DECEMBER 2006–REVISED MARCH 2011
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
PRODUCT
VOUT
Buck1: Adjustable
Buck2: Adjustable
LDO: Adjustable
TPS75003MRHLREP
(1) For the most current specifications and package information, see the Package Option Addendum located at the end of this document or
see the Texas Instruments website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
TPS75003
-0.3 to +7
UNIT
V
VINX range (IN1, IN2, IN3)
VENX range (EN1, EN2, EN3)
VSWX range (SW1, SW2, SW3)
VISX range (IS1, IS2, IS3)
VOUT3 range
-0.3 to VINX + 0.3
-0.3 to VINX + 0.3
-0.3 to VINX + 0.3
-0.3 to +7
V
V
V
V
VSSX range (SS1, SS2, SS3)
VFBX range (FB1, FB2, FB3)
Peak LDO output current (IOUT3
-0.3 to VINX + 0.3
-0.3 to +3.3
V
V
)
Internally limited
See the Thermal Information Table
-55 to +150
—
—
°C
°C
kV
V
Continuous total power dissipation
Junction temperature range, TJ
Storage temperature range
ESD rating, HBM
-65 to +150
1
ESD rating, CDM
500
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
2
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SGLS311A –DECEMBER 2006–REVISED MARCH 2011
Figure 1. Wirebond Plot
THERMAL INFORMATION
TPS75003-EP
UNITS
THERMAL METRIC(1)
RHL (20 PINS)
θJA
Junction-to-ambient thermal resistance
42.6
51.8
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
39.5
°C/W
0.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
14.2
2.8
θJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2006–2011, Texas Instruments Incorporated
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TPS75003-EP
SGLS311A –DECEMBER 2006–REVISED MARCH 2011
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ELECTRICAL CHARACTERISTICS
VEN1 = VIN1, VEN2 = VIN2, VEN3 = VIN3, VIN1 = VIN2 = 2.2 V, VIN3 = 3 V, VOUT3 = 2.5V, COUT1 = COUT2 = 47 μF, COUT3 = 2.2 μF,
TA = -55°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Supply and Logic
Input voltage range (IN1, IN2,
IN3)(1)
VINX
2.2
6.5
V
Quiescent current, IQ = IDGND
IAGND
+
IQ
IOUT1 = IOUT2 = IOUT3= 0 mA
75
150
3
μA
μA
ISHDN
Shutdown supply current
VEN1 = VEN2 = VEN3 = 0 V
TA = 25°C
0.05
1.4
1.45
1.14
1.2
Enable high, enabled
(EN1, EN2)
VIH1, 2
V
V
TA = Full Range
TA = 25°C
VIH3
VILX
IENX
Enable High, enabled (EN3)
TA = Full Range
Enable low, shutdown
(EN1, EN2, EN3)
0
0.3
0.5
V
Enable pin current (EN1, EN2,
EN3)
0.01
μA
Buck Controllers 1 and 2
VOUT1,2
Adjustable output voltage Range(2)
VFB1,2
VFBX
VINX
V
V
Feedback voltage (FB1, FB2)
1.22
±2%
0.01
Feedback voltage accuracy(1)
(FB1, FB2)
IFB1,2
VIS1,2
Current into FB1, FB2 pins
0.5
120
125
0.5
μA
TA = 25°C
80
75
Reference voltage for current
sense
100
mV
TA = Full Range
IIS1,2
Current into IS1, IS2 pins
Line regulation(1)
0.01
0.1
μA
Measured with the circuit in Figure 2,
VOUT + 0.5 V ≤ VIN ≤ 6.5 V
ΔVOUT%/ΔVIN
% / V
Measured with the circuit in Figure 2,
30 mA ≤ I OUT ≤ 2 A
ΔVOUT%/ΔIOUT Load regulation
0.6
% / A
Measured with the circuit in Figure 2,
IOUT = 1 A
n 1,2
Efficiency(3)
94%
Measured with the circuit in Figure 2,
RL = 6 Ω, COUT = 100 μF, CSS = 2.2
nF
tSTR1,2
Startup time(3)
5
ms
V
IN1,2 > 2.5 V
4
6
Gate driver P-Channel and
N-Channel MOSFET on-resistance
RDS,ON1,2
ISW1,2
Ω
VIN1,2 = 2.2 V
Gate Driver P-Channel and
N-Channel MOSFET drive current
100
mA
tON
Minimum on time
Minimum off time
1.36
0.44
1.55
0.65
1.84
0.86
μs
μs
tOFF
(1) To be in regulation, minimum VIN1 (or VIN2) must be greater than VOUT1,NOM (or VOUT2,NOM) by an amount determined by external
components. Minimum VIN3 = VOUT3 + VDO or 2.2 V, whichever is greater.
(2) Maximum VOUT is dependent on external components and will be less than VIN. Parameter is not production tested.
(3) Depends on external components.
4
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SGLS311A –DECEMBER 2006–REVISED MARCH 2011
ELECTRICAL CHARACTERISTICS (continued)
VEN1 = VIN1, VEN2 = VIN2, VEN3 = VIN3, VIN1 = VIN2 = 2.2 V, VIN3 = 3 V, VOUT3 = 2.5V, COUT1 = COUT2 = 47 μF, COUT3 = 2.2 μF,
TA = -55°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
LDO
VOUT3
VFB3
(4)
Output voltage range
Feedback pin voltage
1
6.5 - VDO
V
V
0.507
2.95 V ≤ VIN3 ≤ 6.5 V
Feedback pin voltage accuracy(5)
Line regulation(5)
±4%
1 mA ≤ IOUT3 ≤ 300 mA
VOUT3 + 0.5V ≤ VIN3 ≤ 6.5 V
10 mA ≤ IOUT3 ≤ 300 mA
ΔVOUT%/ΔVIN
0.075
0.01
% / V
ΔVOUT%/ΔIOUT Load regulation
% / mA
Dropout voltage
VDO
IOUT3 = 300 mA
250
350
mV
(VIN = VOUT(NOM) - 0.1)(6)
ICL3
IFB3
Current limit
VOUT = 0.9 x VOUT(NOM)
375
600
1000
0.1
mA
Current into FB3 pin
0.03
μA
BW = 100 Hz - 100 kHz,
IOUT3 = 300 mA
Vn
Output noise
400
μVRMS
°C
Shutdown, temperature increasing
Reset, temperature decreasing
VIN rising
175
160
1.8
Thermal shutdown temperature for
LDO
tSD
Undervoltage lockout threshold
Undervoltage lockout hysteresis
V
UVLO
VIN falling
100
mV
(4) Maximum VOUT is dependent on external components and will be less than VIN. Parameter is not production tested.
(5) To be in regulation, minimum VIN1 (or VIN2) must be greater than VOUT1,NOM (or VOUT2,NOM) by an amount determined by external
components. Minimum VIN3 = VOUT3 + VDO or 2.2 V, whichever is greater.
(6) VDO does not apply when VOUT + VDO < 2.2 V.
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SGLS311A –DECEMBER 2006–REVISED MARCH 2011
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DEVICE INFORMATION
Functional Block Diagram
6
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SGLS311A –DECEMBER 2006–REVISED MARCH 2011
IN3
FB1
FB2
OUT3
PIN FUNCTIONS
PIN
DESCRIPTION
NAME
RHL
Ground connection for BUCK1 and BUCK2 converters. Pins 6 and 15 should be connected to the back side
exposed pad by a short metal trace as shown in the PCB Layout section of this data sheet.
DGND
6, 15, PAD
AGND
IN1
18
13
8
Ground connection for LDO
Input supply to BUCK1
Input supply to BUCK2
Input supply to LDO
IN2
IN3
20
Driving the enable pin (ENx) high turns on BUCK1 regulator. Driving this pin low puts it into shutdown mode,
reducing operating current. The enable pin does not trigger on fast negative going transients.
EN1
17
EN2
EN3
4
3
Same as EN1 but for BUCK2 controller
Same as EN1 but for LDO
Connecting a capacitor between this pin and ground increases start-up time of the BUCK1 regulator by slowing
the ramp-up of current limit. This high-impedance pin is noise-sensitive; careful layout is important. See the
Typical Characteristics, Applications, and PCB Layout sections for details.
SS1
16
SS2
SS3
5
Same as SS1 but for BUCK2 regulator.
Connecting a capacitor from this pin to ground slows the start-up time of the LDO reference, therby slowing
output voltage ramp-up. See the Applications section for details.
19
Current sense input for BUCK1 regulator. The voltage difference between this pin and IN1 is compared to an
internal reference to set current limit. For a robust output start-up ramp, careful layout and bypassing are
required. See the Applications section for details.
IS1
12
IS2
SW1
SW2
FB1
FB2
FB3
9
14
7
Same as IS1, but compared to IN2 and used for BUCK2 controller
Gate drive pin for external BUCK1 P-channel MOSFET
Same as SW1, but for BUCK2 controller
11
10
2
Feedback pin. Used to set the output voltage of BUCK1 regulator
Same as FB1, but for BUCK2 controller
Same as FB1, but for LDO
Regulated LDO output. A small ceramic capacitor (≥ 2.2 μF) is needed from this pin to ground to ensure
stability.
OUT3
1
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Typical Application Circuit for Powering the Xilinx Spartan-3 FPGA
15 mH
100 mF
0.01 mF
33 mW
0.1 mF
1 mF
100 mF
10 mF
61.9 kW
36.5 kW
61.9 kW
0.1 mF
15.4 kW
33 mW
5 mH
100 mF
Figure 2.
TYPICAL CHARACTERISTICS
Measured using circuit in Figure 2
Buck Converter
BUCK LOAD REGULATION
BUCK LOAD REGULATION
Figure 3.
Figure 4.
8
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SGLS311A –DECEMBER 2006–REVISED MARCH 2011
TYPICAL CHARACTERISTICS (continued)
Measured using circuit in Figure 2
BUCK LINE REGULATION
BUCK LINE REGULATION
Figure 5.
Figure 6.
BUCK SWITCHING FREQUENCY
BUCK SWITCHING FREQUENCY
vs
vs
IOUT, TA
IOUT
Figure 7.
Figure 8.
EFFICIENCY vs
IOUT
BUCK OUTPUT VOLTAGE RIPPLE
Figure 9.
Figure 10.
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TYPICAL CHARACTERISTICS (continued)
Measured using circuit in Figure 2
BUCK START-UP
BUCK START-UP
vs
vs
VIN and IOUT
VIN and COUT
Figure 11.
Figure 12.
BUCK START-UP
vs
BUCK START-UP
vs
VIN and CSS
IOUT and CSS
Figure 13.
Figure 14.
LDO Converter
LDO LOAD REGULATION
LDO LINE REGULATION
Figure 15.
Figure 16.
10
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SGLS311A –DECEMBER 2006–REVISED MARCH 2011
TYPICAL CHARACTERISTICS (continued)
Measured using circuit in Figure 2
LDO DROPOUT
LDO DROPOUT
vs
IOUT
vs
TA
Figure 17.
Figure 18.
RDS,ON PMOS
RDS,ON NMOS
vs
vs
VIN
VIN
Figure 19.
Figure 20.
LDO VOUT
vs
TA
Figure 21.
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APPLICATION INFORMATION
The TPS75003 is an integrated power management IC designed specifically to power DSPs and FPGAs such as
the Xilinx Spartan-3, Spartan-3E and Spartan-3L. Two non-synchronous buck controllers can be configured to
supply up to 3 A for both CORE and I/O rails. A low dropout linear regulator powers auxiliary rails up to 300 mA.
All channels have independent enable and soft-start, allowing control of inrush current and output voltage ramp
time as required by the application.
Figure 2 shows a typical application circuit for powering the Xilinx Spartan-3 FPGA. Table 1 through Table 4
show component values that have been tested for use with 2-A and 3-A load currents. Other similar external
components can be substituted as desired; however, in all cases the circuits that are used should be tested for
compliance to application requirements.
Table 1. Inductors Tested with the TPS75003
PART NUMBER
SLF7032T−100M1R4
SLF6025−150MR88
CDRH6D28−5R0
CDRH6D38-5R0
CDRH103R−100
CDRH4D28−100
CDRH8D43-150
CDRH5D18−6R2
DO3316P−472
DT3316P−153
MANUFACTURER
TDK
INDUCTANCE
10 μH ±20%
15 μH ±20%
5 μH
DC RESISTANCE
53 mΩ ±20%
85 mΩ ±20%
23 mΩ
SATURATION CURRENT
1.4 A
0.88 A
2.4 A
2.9 A
2.4 A
1 A
TDK
Sumida
Sumida
Sumida
Sumida
Sumida
Sumida
Coilcraft
Coilcraft
Coilcraft
Wurth
5 μH
18 mΩ
10 μH
45 mΩ
10 μH
96 mΩ
15 μH
42 mΩ
2.9 A
1.4 A
5.4 A
1.8 A
1.5 A
1.45 A
0.8 A
6.2 μH
71 mΩ
4.7 μH
18 mΩ
15 μH
60 mΩ
DT3316P−223
22 μH
84 mΩ
744052006
6.2 μH
80 mΩ
74451115
Wurth
15 μH
90 mΩ
Table 2. PMOS Transistors Tested with the TPS75003
PART NUMBER
Si5447DC
MANUFACTURER
Vishay Siliconix
Vishay Siliconix
Vishay Siliconix
Vishay Siliconix
Vishay Siliconix
Fairchild
RDS,ON (TYP)
VDS
ID
PACKAGE
0.11 Ω at VGS = −2.5 V
0.041 Ω at VGS = −2.5 V
0.052 Ω at VGS = −2.5 V
0.19 Ω at VGS = −2.5 V
0.41 Ω at VGS = −2.5 V
0.17 Ω at VGS = −2.5 V
−20 V
−12 V
−20 V
−20 V
−20 V
−20 V
−3.5 A at +25°C
−6.6 A at +25°C
−4.1 A at +25°C
−1.4 A at +25°C
−4.1 A at +25°C
−1.5 A
1206
1206
Si5475DC
Si2323DS
SOT23
SOT23
SOT23
SC70
Si2301ADS
Si2323DS
FDG326P
Table 3. Diodes Tested with the TPS75003
PART NUMBER
MBRM120LT3
MBR0530T1
ZHCS2000TA
B320
MANUFACTURER
VR
IF
PACKAGE
DO216AA
SOD123
SOT23−6
SMA
ON Semiconductor
ON Semiconductor
Zetex
20 V
30 V
40 V
20 V
20 V
1 A
1.5 A
2 A
Diodes Inc.
3 A
SS32
Fairchild
3 A
DO214AB
12
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Table 4. Capacitors Tested with the TPS75003
PART NUMBER
MANUFACTURER
Sanyo
CAPACITANCE
47 μF
ESR
0.1 Ω
VOLTAGE RATING
6TPB47M (PosCap)
T491D476M010AS
B45197A
6.3 V
10 V
16 V
6.3 V
16 V
6.3 V
6.3 V
6.3 V
Kemet
47 μF
0.8 Ω
Epco
47 μF
0.175 Ω
0.045 Ω
0.11 Ω
0.085 Ω
0.15 Ω
0.45 Ω
B45294−R1107−M40
594D476X0016C2
594D127X96R3C2
TPSC107K006R0150
6TPS100MC
Epco
100 μF
47 μF
Vishay
Vishay
AVX
120 μF
100 μF
100 μF
Sanyo
OPERATION (BUCK CONTROLLERS)
Channels 1 and 2 contain two identical non-synchronous buck controllers that use minimum on-time/minimum
off-time hysteretic control. (See Figure 2.) For clarity, BUCK1 is used throughout the discussion of device
operation. When VOUT1 is below its target, an external PMOS (Q1) is turned on for at least the minimum on-time,
increasing current through the inductor (L1) until VOUT1 reaches its target value or the current limit (set by R1) is
reached. Once either of these conditions is met, the PMOS is switched off for at least the minimum off-time of
the device. After the minimum off-time has passed, the output voltage is monitored and the switch is turned on
again when necessary.
When output current is low, the buck controllers operate in discontinuous mode. In this mode, each switching
cycle begins at zero inductor current, rises to a maximum value, then falls back to zero current. When current
reaches zero on the falling edge, ringing occurs at the resonant frequency of the inductor and stray switch node
capacitance. This is normal operation; it does not affect circuit performance, and can be minimized if desired by
using an RC snubber and/or a resistor in series with the gate of the PMOS, as shown in Figure 22.
0.1 mF
R = 2pfL
Figure 22. RC Snubber and Series Gate Resistor Used to Minimize Ringing
At higher output currents, the TPS75003 operates in continuous mode. In continuous mode, there is no ringing at
the switch node and VOUT is equal to VIN times the duty cycle of the switching waveform.
When VIN approaches or falls below VOUT, the buck controllers operate in 100% duty cycle mode, fully turning on
the external PMOS to allow regulation at lower dropout than would otherwise be possible.
Enable (Buck Controllers)
The enable pins (EN1 and EN2) for the buck controllers are active high. When the enable pin is driven low and
input voltage is present at IN1 or IN2, an on-chip FET is turned on to discharge the soft-start pin SS1 or SS2,
respectively. If the soft-start feature is being used, enable should be driven high at least 10μs after VIN is applied
to ensure this discharge cycle occurs.
UVLO (Buck Controllers)
An under-voltage lockout circuit is present to prevent turning on the external PMOS (Q1 or Q2) until a reliable
operating voltage is reached on the appropriate regulator (IN1 or IN2). This prevents the buck controllers from
mis-operation at low input voltages.
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Current Limit (Buck Controllers)
An external resistor (R1 or R2) is used to set the current limit for the external PMOS transistor (Q1 or Q2). These
resistors are connected between IN1 and IS1 (or IN2 and IS2) to provide a reference voltage across these pins
that is proportional to the current flowing through the PMOS transistor. This reference voltage is compared to an
internal reference to determine if an over-current condition exists. When current limit is exceeded, the external
PMOS is turned off for the minimum off-time. Current limit detection is disabled for 10 ns any time the PMOS is
turned on to avoid triggering on switching noise. In 100% duty cycle mode, current limit is always enabled.
Current limit is calculated using the VIS1 or VIS2 specification in the Electrical Characteristics section, shown in
Equation 1.
V
IS1,2
I
=
LIMIT
R1,2
(1)
The current limit resistor must be appropriately rated for the dissipated power determined by its RMS current
calculated by Equation 2.
VOUT
IRMS = IOUT D = IOUT
V
IN
2
P
= I
(
´ R
)
DISS
RMS
(2)
For low-cost applications the IS1,2 pin can be connected to the drain of the PMOS, using RDS,ON instead of R1 or
R2 to set current limit. Variations in the PMOS RDS,ON must be taken into account to ensure that current limit will
protect external components such as the inductor, the diode, and the switch itself from damage as a result of
overcurrent.
Short-Circuit Protection (Buck Controllers)
In an overload condition, the current rating of the external components (PMOS, diode, and inductor) can be
exceeded. To help guard against this, the TPS75003 increases its minimum off-time when the voltage at the
feedback pin is lower than the reference voltage. When the output is shorted (VFB is zero), minimum off-time is
increased to approximately 4 μs. The increase in off-time is proportional to the difference between the voltage at
the feedback pin and the internal reference.
Soft-Start (Buck Controllers)
The buck controllers each have independent soft-start capability to limit inrush during start-up and to meet timing
requirements of the Xilinx Spartan-3 FPGA. Limiting inrush current by using soft-start, or by staggering the
turn-on of power rails, also guards against voltage drops at the input source due to its output impedance. See the
soft-start circuitry shown in Figure 23 and the soft-start timing diagram shown in Figure 24. BUCK 1 will be
discussed in this section; it is identical to BUCK2. Note that pins SS1 and SS2 are high-impedance and cannot
be probed using a typical oscilloscope setup. When input voltage is applied at IN1 and EN1 is driven low, any
charge on the SS pin is discharged by an on-chip pulldown transistor. When EN1 is driven high, an on-chip
current source starts charging the external soft-start capacitor CSS1. The voltage on the capacitor is compared to
the voltage across the current sense resistor R1 to determine if an over-current condition exists. If the voltage
drop across the sense resistor goes above the reference voltage, then the external PMOS is shut off for the
minimum off-time. This implementation provides a cycle-by-cycle current limit and allows the user to program the
soft-start time over a wide range for most applications. For detailed information on choosing CSS1 and CSS2, see
the section, Selecting the Soft-Start Cap.
14
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Figure 23. Soft-Start Circuitry
Figure 24. Soft-Start Timing Diagram
Input Capacitor CIN1, CIN2 Selection (Buck Controllers)
It is good analog design practice to place input capacitors near the inputs of the device in order to ensure a low
impedance input supply. A capacitance of 10 μF to 22 μF for each buck converter is adequate for most
applications, and should be placed within 100 mils (0.001 in) of the IN1 and IN2 pins to minimize the effects of
pulsed current switching noise on the soft-start circuitry during the first ~1 V of output voltage ramp. Low ESR
capacitors also help to minimize noise on the supply line. The minimum value of capacitance can be estimated
using Equation 3.
2
2
)
(1/2)L ´ DI
1/2 L ´ 0.3 ´ I
OUT
( ) ( )
L
(
C , MIN =
IN
»
VRIPPLE ´ V
V RIPPLE ´ V
IN
IN
(
)
(3)
Note that the capacitors must be able to handle the RMS current in continuous conduction mode, which can be
calculated using Equation 4.
æ
ç
è
VOUT
ö
÷
ø
IC,IN(RMS)
»
V ,MIN
IN
(4)
15
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Inductor Value Selection (Buck Controllers)
The inductor is chosen based on inductance value and maximum current rating. Larger inductors reduce current
ripple (and therefore, output voltage ripple) but are physically larger and more expensive. Inductors with lower
DC resistance typically improve efficiency, but also have higher cost and larger physical size. The buck
converters work well with inductor values between 4.7 μH and 47 μH in most applications. When selecting an
inductor, the current rating should exceed the current limit set by RIS or RDS,ON (see Current Limit section). To
determine the minimum inductor size, first determine if the device will operate in minimum on-time or minimum
off-time mode. The device will operate in minimum on-time mode if Equation 5 is satisfied.
t(OFF,min)
´
V
+ VSCHOTTKY + RL ´ IOUT
(
)
OUT
V
IN
- VOUT - IOUT ´ rDS(on) - RL ´ IOUT ³
tON,MIN
(5)
where RL = the inductor's DC resistance.
Minimum inductor size needed when operating in minimum on-time mode is given by Equation 6.
- V - I ´ r - R ´ I ´ t ,MIN
V
(
)
IN
OUT
OUT
DS(on)
L
OUT
ON
L
=
MIN
DI
(6)
(7)
Minimum inductor size needed when operating in minimum off-time mode is given by Equation 7.
V
+ VSCHOTTKY + RL ´ IOUT ´ tOFF,MIN
)
DI
(
OUT
LMIN
=
External PMOS Transistor Selection (Buck Controllers)
The external PMOS transistor is selected based on threshold voltage (VT), on-resistance (RDS,ON), gate
capacitance (CG) and voltage rating. The PMOS VT magnitude must be much lower than the lowest voltage at
IN1 or IN2 that will be used. A VT magnitude that is 0.5 V less than the lowest input voltage is normally sufficient.
The PMOS gate will see voltages from 0 V to the maximum input voltage, so gate-to-source breakdown should
be a few volts higher than the maximum input supply. The drain-to-source of the device will also see this full
voltage swing, and should therefore be a few volts higher than the maximum input supply. The RMS current in
the PMOS can be estimated by using Equation 8.
VOUT
IPMOS(RMS) » IOUT D = IOUT
V
IN
(8)
The power dissipated in the PMOS is comprised of both conduction and switching losses. Switching losses are
typically insignificant. The conduction losses are a function of the RMS current and the RDS,ON of the PMOS, and
are calculated by Equation 9.
2
P
= I
(
D
´ r
´
1 + TC ´
(
T
- 25°C
»
I
(
D
´ r
DS(on)
[
])
)
)
(cond)
OUT
DS(on)
J
OUT
(9)
16
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Diode Selection (Buck Controllers)
The diode is off when the PMOS is on, and on when the PMOS is off. Since it will be turned on and off at a
relatively high frequency, a Schottky diode is recommended for good performance. The peak current rating of the
diode should exceed the peak current limit set by the sense resistor RIS1,2. A diode with low reverse leakage
current and low forward voltage at operating current will optimize efficiency. Equation 10 calculates the estimated
average power dissipation.
æ
ö
÷
ø
VOUT
I(diode)(RMS) » IOUT (1 - D) = IOUT ç1 -
V
è
IN
(10)
Output Capacitor Selection (Buck Controllers)
The output capacitor is selected based on output voltage ripple and transient response requirements. As a result
of the nature of the hysteretic control loop, a minimum ESR of a few tens of mΩ should be maintained for good
operation unless a feed-forward resistor is used. Low ESR bulk tantalum or PosCap capacitors work best in most
applications. A 1-μF ceramic capacitor can be used in parallel with this capacitor to filter higher frequency spikes.
The output voltage ripple can be estimated by Equation 11.
é
1
ù
ö
æ
DV = DI ´ ESR +
»1.1DI ´ ESR
PP
ê
ç
÷ú
8 ´ COUT ´ f
è
ø
ë
û
(11)
To calculate the capacitance needed to achieve a given voltage ripple as a result of a load transient from zero
output to full current, use Equation 12.
2
L ´ ΔIOUT
COUT
=
V
- VOUT ´ ΔV
)
(
IN
(12)
If only ceramic or other very low ESR output capacitor configurations are desired, additional voltage ripple must
be passed to the feedback pin. See Application Note, Using Ceramic Output Capacitors with the TPS6420x Buck
Controllers (SLVA210), for detailed application information.
Output Voltage Ripple Effect on VOUT (Buck Controllers)
Output voltage ripple causes VOUT to be higher or lower than the target value by half of the peak-to-peak voltage
ripple. For minimum on-time, the ripple adds to the voltage; for minimum off-time, it subtracts from the voltage.
Soft-Start Capacitor Selection (Buck Controllers)
BUCK1 is discussed in this section; it is identical to BUCK2. Soft-start is implemented on the buck controllers by
ramping current limit from 0 to its target value (set by R1) over a user-defined time. This time is set by the
external soft-start cap connected to pin SS1. If SS1 is left open, a small on-chip capacitor will provide a current
limit ramp time of approximately 250 μs. Figure 25 shows the effects of R1 and SS1 on the current limit start-up
ramp.
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R1 = 33 mW
C
= 0.01 mF
SS1
C
= 0.022 mF
SS1
R1 = 143 mW
C
= 0.022 mF
SS1
C
= 0.01 mF
SS1
Figure 25. Effects of CSS1 and R1 on Current Ramp Limit
This soft-start current limit ramo can be used to provide inrush current control or output voltage ramp control.
While the current limit ramp can be easily understood by looking at Figure 25, the output voltage ramp is a
complex function of many variables. The dominant variables in this process are VOUT1, CSS1, IOUT1, and R1. Less
important variables are VIN1 and L1.
The best way to set a target start-up time is through bench measurement under target conditions, adjusting CSS1
to get the desired startup profile. To stay above a minimum start-up time, set the nominal start-up time to
approximately five times the minimum. To stay below a maximum time, set the nominal start-up time at one-fifth
of the maximum. Fastest start-up times occur at maximum VIN1, with minimum VOUT1, L1, COUT1, CSS1, and IOUT1
.
Slowest start-up times occur under opposite conditions.
See Figure 11 to Figure 14 for characterization curves showing how the start-up profile is affected by these
critical parameters.
Output Voltage Setting Selection (Buck Controllers)
Output voltage is set using two resistors as shown for Buck2 in Figure 2. Output voltage is then calculated using
Equation 13.
æ
ö
÷
ø
R5
R6
VOUT = VFB ç
+1
è
(13)
where VFB = 1.24V.
LDO OPERATION
The TPS75003 LDO uses a PMOS pass element and is offered in an adjustable version for ease of
programming to any output voltage. When used to power VCC,AUX it is set to 2.5 V; it can optionally be set to
other output voltages to power other circuitry. The LDO has integrated soft-start, independent enable, and
short-circuit and thermal protection. The LDO can be used to power VCC,AUX on the Xilinx Spartan-3 FPGA when
3.3-V JTAG signals are used as described in Application Note SLVA159 (available for download from
www.ti.com).
Input Capacitor Selection (LDO)
Although an input capacitor is not required, it is good analog design practice to connect a 0.1-μF to 10-μF low
ESR capacitor across the input supply near the regulator. This capacitor counteracts reactive input sources and
improves transient response, stability, and ripple rejection. A higher value capacitor may be needed if large, fast
rise-time load transients are anticipated, or if the device is located far from its power source.
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Output Capacitor Selection (LDO)
A 2.2 μF or greater capacitor is required near the output of the device to ensure stability. The LDO is stable with
any capacitor type, including ceramic. If improved transient response or ripple rejection is required, larger and/or
lower ESR output capacitors can be used.
Soft-Start (LDO)
The LDO uses an external soft-start capacitor, CSS3, to provide an RC-ramped reference voltage to the control
loop. (See the Functional Block Diagram.) This is a voltage-controlled soft-start, as compared to the
current-controlled soft-start used by the buck controllers.
Setting Output Voltage (LDO)
Output voltage is set using two resistors as shown in Figure 2. Output voltage is then calculated using
Equation 14.
æ
ö
÷
ø
R3
R4
VOUT = VFB ç
+1
è
(14)
where VFB = 0.507 V.
Internal Current Limit (LDO)
The internal current limit of the LDO helps protect the regulator during fault conditions. When an over-current
condition is detected, the output voltage will be reduced until the current falls to a level that will not damage the
device. For good device reliability, the LDO should not operate at current limit.
Enable Pin (LDO)
The active high enable pin (EN3) can be used to put the device into shutdown mode. If shutdown and soft-start
capability are not required, EN3 can be tied to IN3.
Dropout Voltage (LDO)
The LDO uses a PMOS transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage
(VDO), the pass device is in its linear region of operation, and the input-output resistance is the RDS,ON of the pass
transistor. In this region, the regulator is said to be out of regulation; ripple rejection, line regulation, and load
regulation degrade as (VIN – VOUT) falls much below 0.5 V.
Transient Response (LDO)
The LDO does not have an on-chip pulldown circuit for output is over-voltage conditions. This feature permits
applications that connect higher voltage sources such as an alternate power supply to the output. This design
also results in an output overshoot of several percent if the load current quickly drops to zero. The amplitude of
overshoot can be reduced by increasing COUT; the duration of overshoot can be reduced by adding a load
resistor.
Thermal Protection (LDO)
Thermal protection disables the output when the junction temperature, TJ, reaches unsafe levels. When the
junction cools, the output is again enabled. Depending on power dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the
regulator, protecting it from damage. For good long term reliability, the device should not be continuously
operated at or near thermal shutdown.
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Power Dissipation (LDO)
The TPS75003 comes in a QFN-style package with an exposed lead frame on the package underside. The
exposed lead frame is the primary path for removing heat and should be soldered to a PC board that is
configured to remove the amount of power dissipated by the LDO, as calculated by Equation 15.
PD =
V
- VOUT3 ´ IOUT3
)
(
IN3
(15)
Power dissipation can be minimized by using the lowest possible input voltage necessary to assure the required
output voltage. The two buck converters do not contribute a significant amount of dissipated power. Using
heavier copper increases the overall effectiveness of removing heat from the device. The addition of plated
through-holes to heat-dissipating layers also improves the heatsink effectiveness.
PCB Layout Considerations
As with any switching regulators, careful attention must be paid to board layout. A typical application circuit and
corresponding recommended printed circuit board (PCB) layout with emphasis on the most sensitive areas are
shown in Figure 26 through Figure 28.
Note: Most sensitive areas are highlighted by bold lines.
Figure 26. Typical Application Circuit
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Note: Most sensitive areas are highlighted in green.
Figure 27. Recommended PCB Layout, Component Side, Top View
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Note: Most sensitive areas are highlighted in green.
Figure 28. Recommended PCB Layout, Bottom Side, Top View
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REVISION HISTORY
Changes from Original (December 2006) to Revision A
Page
•
Replaced the DISSIPATION RATINGS table with the Thermal Information Table .............................................................. 3
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PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS75003MRHLREP
QFN
RHL
20
3000
330.0
12.4
3.8
4.8
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
QFN RHL 20
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
TPS75003MRHLREP
3000
Pack Materials-Page 2
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