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TAS3251

ZHCSIA0A –MAY 2018–REVISED NOVEMBER 2018

TAS3251 具有高级 DSP 处理功能的 175W 立体声、350W 单声道超高清

数字输入 D 类放大器

1 特性

2 应用

1

•

灵活的音频输入

•

蓝牙和WiFi 无线音箱

I²S、TDM、左平衡、右平衡

条形音箱

–

低音炮

32kHz、44.1kHz、48kHz、96kHz

支持 3 线数字输入（无 MCLK）

书架立体声系统

专业和公共广播 (PA) 扬声器和

有源分频器和双向扬声器

THD+N 为 10% 时的总输出功率

–

175W/4Ω，桥接负载 (BTL) 立体声配置

220W/3Ω，桥接负载 (BTL) 立体声配置

350W/2Ω，并行桥接负载 (PBTL) 单声道配置

3 说明

TAS3251 是一款数字输入高性能 D 类音频放大器，可

实现真正的高端音质和 D 类效率。数字前端采用具有

集成 DSP 的高性能 Burr-Brown™DAC，可实现高级

音频处理，同时采用了 SmartAmp 和 SmartEQ。该首

款高功率单芯片解决方案降低了总体系统解决方案的尺

寸和成本。DSP 由 TI PurePath™控制台图形调节软

件提供支持，可以快速轻松地调节和控制扬声器。D

类功率级具有高级集成式反馈和专有高速栅极驱动器

错误校正功能，可以在音频频带内实现超低失真和噪

声。该器件在 AD 模式下运行，最多可驱动 2 个

175W/4Ω 负载和 2 个 220W/3Ω 负载。

THD+N 为 1% 时的总输出功率

–

140W/4Ω，BTL 立体声配置

175W/3Ω，BTL 立体声配置

285W/2Ω，PBTL 单声道配置

高级集成式闭环设计

–

1W/4Ω 时具有 0.01% 的超低 THD+N

削波小于 0.01% THD+N

60dB PSRR（BTL，无输入信号）

输出噪声（A 加权）< 95µV

SNR（A 加权）> 108dB

•

固定功能处理特性

–

SmartEQ（每个通道多达 15 个双二阶）

分频器 EQ（2x 5 个双二阶）

器件信息

器件编号

TAS3251

封装

封装尺寸（标称值）

HSSOP (56)

18.41mm × 7.49mm

三波段高级动态范围压缩 (DRC) + 自动增益限

制 (AGL)

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

–

动态均衡和 SmartBass

采样率转换

简化原理图

•

控制特性

–

I²C 软件模式控制

BST_A+

地址选择引脚

DAC_MUTE

SPK_OUTA+

•

90% 高效 D 类操作 (4Ω)

MCLK

DAC

LC

Filter

12V 至 36V 宽电源电压工作范围

Processin

g

LRCLK

I2S / TDM

Audio Port

SCLK

SDIN

EQ

SPK_OUTA-

BST_A-

具有错误报告功能的集成式保护：欠压、逐周期电

流限制、短路、削波检测、过热警告和关断以及直

流扬声器保护

32, 44.1, 48, 96kHz

ꢀCDSP Core

High /_PL_ao_ssw

EQ, High

Speaker Enhancement Protection

/

Filter,

Pa^Ls^os^wFilt_&er

DAC

Speaker

Enhancem

ent &

SDOUT

Ultra-Low Distortion

Protection

24-bit, Up to 96kHz

Closed-Loop

Class-D Amplifiers

BST_B+

SPK_OUTB+

SDA

SCL

ADR

LC

Filter

I²

Software Control Port

C

SPK_OUTB-

BST_B-

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLASEG6

TAS3251

ZHCSIA0A –MAY 2018–REVISED NOVEMBER 2018

www.ti.com.cn

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 4

Specifications......................................................... 7

7.1 Absolute Maximum Ratings ...................................... 7

7.2 ESD Ratings.............................................................. 7

7.3 Recommended Operating Conditions....................... 8

7.4 Thermal Information.................................................. 8

7.5 Amplifier Electrical Characteristics............................ 9

7.6 DAC Electrical Characteristics ................................ 11

7.7 Audio Characteristics (BTL) .................................... 12

7.8 Audio Characteristics (PBTL).................................. 12

7.9 MCLK Timing .......................................................... 13

7.10 Serial Audio Port Timing – Slave Mode................ 13

7.11 Serial Audio Port Timing – Master Mode.............. 13

7.12 I²C Bus Timing –Standard .................................... 14

7.13 I²C Bus Timing –Fast............................................ 14

7.14 Timing Diagrams................................................... 15

7.15 Typical Characteristics.......................................... 17

8

9

Detailed Description ............................................ 21

8.1 Overview ................................................................. 21

8.2 Functional Block Diagram ....................................... 21

8.3 Feature Description................................................. 22

8.4 Device Functional Modes........................................ 51

8.5 Programming........................................................... 53

8.6 Register Maps......................................................... 64

Application and Implementation ...................... 101

9.1 Typical Applications ............................................. 101

10 Power Supply Recommendations ................... 108

10.1 Power Supplies ................................................... 108

11 Layout................................................................. 111

11.1 Layout Guidelines ............................................... 111

11.2 Layout Examples................................................. 112

12 器件和文档支持 ................................................... 115

12.1 器件支持.............................................................. 115

12.2 接收文档更新通知 ............................................... 115

12.3 社区资源.............................................................. 116

12.4 商标..................................................................... 116

12.5 静电放电警告....................................................... 116

12.6 术语表 ................................................................. 116

13 机械、封装和可订购信息..................................... 116

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (May 2018) to Revision A

Page

•

将文件状态从预告信息更改成了生产数据.............................................................................................................................. 1

2

TAS3251

www.ti.com.cn

ZHCSIA0A –MAY 2018–REVISED NOVEMBER 2018

5 Device Comparison Table

AUDIO INPUT

INTERFACE

PAD

LOCATION

DEVICE NAME

DESCRIPTION

175-W Stereo, 350-W Mono Ultra-HD Digital-Input Class-D Amplifier with Advanced

DSP Processing

TAS3251

TAS3245

Digital

Top

115-W Stereo, 230-W Mono Ultra-HD Digital-Input Class-D Amplifier with Advanced

DSP Processing

30-W Stereo, 60-W Mono Digital-Input Class-D Amplifier with Advanced DSP

Processing

TAS5782M

Bottom

TPA3244

TPA3245

TPA3250

TPA3251

TPA3255

60-W Stereo, 100-W Peak Ultra-HD Pad-Down Class-D Amplifier

115-W Stereo, 230-W Mono Ultra-HD Analog-Input Class-D Amplifier

70-W Stereo, 130-W Peak Ultra-HD Pad-Down Class-D Amplifier

175-W Stereo, 350-W Mono Ultra-HD Analog-Input Power Stage

315-W Stereo, 600-W Mono Ultra-HD Analog-Input Class-D Amplifier

Analog

Bottom

Top

Bottom

Top

3

TAS3251

ZHCSIA0A –MAY 2018–REVISED NOVEMBER 2018

www.ti.com.cn

6 Pin Configuration and Functions

DKQ Package

56-Pin HSSOP with PowerPAD™

Top View

DAC_OUTB+

DAC_OUTB-

DAC_OUTA-

DAC_OUTA+

CPVSS

1

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

DAC_AVDD

AGND

2

3

SDA

4

SCL

5

XPU

CN

6

SDOUT

MCLK

GND

7

CP

8

SCLK

DAC_DVDD

DGND

9

SDIN

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

LRCK

DVDD_REG

GVDD_A

GND

ADR

DAC_MUTE

BST_A+

BST_A-

GND

MODE

Thermal

Pad

SPK_INA+

SPK_INA-

OC_ADJ

FREQ_ADJ

OSC_IOM

OSC_IOP

DVDD

SPK_OUTA+

PVDD_A

SPK_OUTA-

GND

SPK_OUTB+

PVDD_B

SPK_OUTB-

GND

AVDD

C_START

SPK_INB+

SPK_INB-

RESET_AMP

FAULT

BST_B+

BST_B-

GVDD_B

CLIP_OTW

Not to scale

4

TAS3251

www.ti.com.cn

ZHCSIA0A –MAY 2018–REVISED NOVEMBER 2018

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NO.

NAME

1

2

3

4

DAC_OUTB+

DAC_OUTB-

DAC_OUTA-

DAC_OUTA+

O

Differential DAC output B+.

Differential DAC output B-.

Differential DAC output A-.

Differential DAC output A+.

–3.3 V negative charge pump supply output for DAC. Connect 1 µF ceramic capacitor to GND. Refer to section:

Power Supply Recommendations

5

CPVSS

P

Negative pin for capacitor connection used in the line-driver charge pump. Connect 1 µF ceramic capacitor from

CN to CP. Refer to section: Power Supply Recommendations

6

7

8

CN

GND

CP

P

G

P

Ground pin for device.

Positive pin for capacitor connection used in the line-driver charge pump. Connect 1 µF capacitor from CN to

CP. Refer to section: Power Supply Recommendations

DAC power supply input for digital logic and charge pump. Connect 3.3 V and a 1 uF ceramic capacitor to GND.

Refer to section: DAC_DVDD and DAC_AVDD Supplies

9

DAC_DVDD

DGND

P

10

G

Ground reference for digital circuitry. Connect this pin to the system ground.

DAC voltage regulator output derived from DAC_DVDD supply for use for internal digital circuitry (1.8 V). This

pin is provided as a connection point for filtering capacitors for this supply and must not be used to power any

external circuitry. Connect 1 µF ceramic capacitor to GND. Refer to section: DAC_DVDD and DAC_AVDD

Supplies

11

DVDD_REG

P

Gate drive supply input for amplifier channel A. Connect 12 V and a 0.1 µF capacitor to GND. Refer to section:

GVDD_X Supply

12

GVDD_A

P

13

14

15

16

17

18

GND

G

Ground pin for device.

MODE

I

Output configuration mode selection. BTL = 0, PBTL = 1. Refer to table: Mode Selection Pins

Input signal for half-bridge A+.

SPK_INA+

SPK_INA-

OC_ADJ

FREQ_ADJ

I

Input signal for half-bridge A-.

I / O

Over-Current threshold programming pin. Refer to section: Overload and Short Circuit Current Protection

Oscillator frequency programming pin. Refer to section: Oscillator for Output Power Stage

PWM switching oscillator synchronization interface. Optional. Do not connect if unused. Refer to section:

Oscillator Synchronization and Slave Mode

19

20

OSC_IOM

OSC_IOP

I / O

O

PWM switching oscillator synchronization interface. Optional. Do not connect if unused. Refer to section:

Oscillator Synchronization and Slave Mode

Internal voltage regulator, amplifier digital section. Connect 1 µF ceramic capacitor to GND. Refer to section:

VDD Supply

21

22

23

DVDD

GND

P

G

P

Ground pin for device.

Internal voltage regulator, amplifier analog section. Connect 1 µF ceramic capacitor to GND. Refer to section:

VDD Supply

AVDD

Startup ramp, requires a charging capacitor to GND. Connect 10 nF to GND for best pop prevention. Refer to

section: Pop and Click Free Startup and Shutdown

24

C_START

O

25

26

27

SPK_INB+

SPK_INB-

I

Input signal for half-bridge B+.

Input signal for half-bridge B-.

RESET_AMP

Device reset, active low. Use for amplifier reset and mute. Refer to section: Output Power Stage Reset

Shutdown signal, open drain; active low. Internal pull-up resistor to DVDD. Do not connect if unused. Refer to

section: Device Output Stage Protection System

28

29

30

FAULT

CLIP_OTW

GVDD_B

O

P

Clipping warning and over-temperature warning; open drain; active low. Internal pull-up resistor to DVDD. Do not

connect if unused. Refer to section: Device Output Stage Protection System

Gate drive supply input for amplifier channel B. Connect 12 V and a 0.1 µF capacitor to GND. Refer to section:

GVDD_X Supply

31

32

33

34

BST_B-

BST_B+

GND

P

HS bootstrap supply (BST), external 0.033 μF capacitor to SPK_OUTB-. Refer to section: BST Supply

HS bootstrap supply (BST), external 0.033 μF capacitor to SPK_OUTB+. Refer to section: BST Supply

Ground pin for device.

G

O

SPK_OUTB-

Output, half bridge B-.

PVDD supply for channel B. Connect large bulk capacitor and 1 µF ceramic decoupling capacitor to GND and

place near pin. Refer to section: PVDD Supply

35

PVDD_B

P

36

37

38

SPK_OUTB+

GND

O

G

Output, half bridge B+.

Ground pin for device.

GND

(1) I=Input, O=Output, I/O= Input/Output, P=Power, G=Ground

5

TAS3251

ZHCSIA0A –MAY 2018–REVISED NOVEMBER 2018

www.ti.com.cn

Pin Functions (continued)

TYPE⁽¹⁾

DESCRIPTION

NO.

NAME

39

SPK_OUTA-

O

P

Output, half bridge A-.

PVDD supply for channel A. Connect large bulk capacitor and 1 µF ceramic decoupling capacitor to GND and

place near pin. Refer to section: PVDD Supply

40

PVDD_A

41

42

43

44

SPK_OUTA+

GND

O

G

P

Output, half bridge A+.

Ground pin for device.

BST_A-

BST_A+

HS bootstrap supply (BST), external 0.033 μF capacitor to SPK_OUTA-. Refer to section: BST Supply

HS bootstrap supply (BST), external 0.033 μF capacitor to SPK_OUTA+. Refer to section: BST Supply

Hardware controlled DAC mute function. Pull low (connected to DGND) to mute the device and pull high

(connected to DAC_DVDD) to unmute the device. Refer to section: Mute with DAC_MUTE or Clock Error

45

46

DAC_MUTE

ADR

I

Sets the LSB of the I²C address to 0 if pulled to GND, to 1 if pulled to DAC_DVDD. Refer to table: Slave

Address Select

Left-Right Word (I²S) or Frame (TDM) select clock for digital audio signal. In I²S, LJ, and RJ, this corresponds to

the left channel and right channel boundary. In TDM mode, this corresponds to the frame sync boundary. Refer

to section: Serial Audio Port

47

LRCK

I

48

49

SDIN

SCLK

I

Audio data serial port, data in. Refer to section: Serial Audio Port

Serial or bit clock for the digital signal that is active on the input data line of the serial data port. Refer to section:

Serial Audio Port

Master clock used for internal clock tree and sub-circuit and state machine clocking. Refer to section: Serial

Audio Port

50

51

52

MCLK

SDOUT

XPU

I

I / O

I

Audio data serial port, data output. Refer to section: SDOUT Port and Hardware Control Pin

External pull-up, logic level pin. For normal operation, this pin should be connected directly to 3.3 V (DAC_DVDD

or DAC_AVDD).

I²C serial control port clock. Refer to section: I2C Communication Port

I²C serial control port data. Refer to section: I2C Communication Port

Ground reference for analog circuitry. Connect to system ground.

53

54

55

SCL

SDA

I

I / O

G

AGND

DAC power supply input for DAC internal analog circuitry. Connect 3.3 V and a 1 uF ceramic capacitor to GND.

Refer to section: DAC_DVDD and DAC_AVDD Supplies

56

DAC_AVDD

PowerPAD™

P

G

Ground, connect to grounded heat sink.

Table 1. Mode Selection Pins

Output

Configuration

SPK_INB+

Input Mode

MODE Pin

SPK_INB- Pin

Description

2 x BTL

2N + 1

0

X

Stereo BTL output configuration

Paralleled BTL configuration pre-filter or

post-filter. Connect SPK_INB+ and

INPUT_B- to GND with no DC blocking

capacitor.

1 x PBTL

2N + 1

1

0

Table 2. I²C Device Slave Address

ADR Pin

Hex

0x4A

0x94

0x95

0x4B

0x96

0x97

Binary

7-bit Address

1001 010

1001 0100

1001 0101

1001 011

1001 0110

1001 0111

0

7-bit Address + Write Bit

7-bit Address + Read Bit

7-bit Address

1

7-bit Address + Write Bit

7-bit Address + Read Bit

6

TAS3251

www.ti.com.cn

ZHCSIA0A –MAY 2018–REVISED NOVEMBER 2018

7 Specifications

7.1 Absolute Maximum Ratings

Free-air room temperature 25°C (unless otherwise noted)⁽¹⁾

MIN

-0.3

MAX

50

UNIT

V

PVDD_X to GND⁽²⁾

BST_X to GVDD_X⁽²⁾

BST_X to GND⁽²⁾

50

V

62.5

13.2

4.2

8.5

3.9

50

V

VDD to GND

Supply Voltage

V

GVDD_X to GND⁽²⁾

V

DVDD to GND

V

AVDD to GND

V

DAC_DVDD, DAC_AVDD

SPK_OUTX to GND⁽²⁾

V

Analog Interface Pins

SPK_INX to GND

7

V

OC_ADJ, MODE, OSC_IOP, OSC_IOM, FREQ_ADJ, C_START to

GND

-0.3

4.2

V

RESET_AMP, FAULT, CLIP_OTW to GND

4.2

9

V

Digital Interface Pins

Continuous sink current RESET_AMP, FAULT, CLIP_OTW to GND

mA

ADR, DAC_MUTE, LRCK, MCLK, SCL, SCLK, SDA, SDIN, SDOUT,

XPU to GND

V_{DAC_DVDD +}

-0.5

V

0.5

Operating junction temperature range, power die

Operating junction temperature, digital die

Storage temperature range

-40

165

°C

T_J

125

150

T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings

only, and functional operation of the device at these or any other conditionsbeyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions forextended periods may affect device reliability.

(2) These voltages represents the DC voltage + peak AC waveformmeasured at the terminal of the device in all conditions..

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

Electrostatic

discharge

V_(ESD)

V

(1) JEDEC document JEP155 states that 2000-V HBM allows safemanufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 500-V CDM allows safemanufacturing with a standard ESD control process.

7

TAS3251

ZHCSIA0A –MAY 2018–REVISED NOVEMBER 2018

www.ti.com.cn

7.3 Recommended Operating Conditions

Free-air room temperature 25°C (unless otherwise noted)

MIN

TYP

MAX

UNIT

PVDD_X

GVDD_X

Half-bridge supply

DC supply voltage

12

36

38

V

Supply for logic regulators and gate-drive

circuitry

10.8

12

13.2

V

VDD

Digital regulator supply voltage

10.8

2.9

12

13.2

3.63

V

DAC_AVDD

Power supply for DAC internal analog circuitry. DC supply voltage

3.3

DAC digital power supply and power supply for

DC supply voltage

DAC_DVDD⁽¹⁾

2.9

3.3

3.63

V

charge pump

R_L(BTL)

2.7

1.6

5

4

2

Output filter inductance within

recommended value range

Load impedance

Ω

R_L(PBTL)

L_OUT(BTL)

L_OUT(PBTL)

Minimum output inductance at

IOC

Output filter inductance

μH

5

Nominal

575

475

430

9.9

19.8

29.7

1.0

22

600

500

450

10

625

525

470

10.1

20.2

30.3

PWM frame resistor tolerance selectable for

AM interference avoidance; 1% Resistor

tolerance

F_PWM

AM1

kHz

AM2

Nominal; Master mode

AM1; Master mode

AM2; Master mode

R_{(FREQ_ADJ)}

PWM frame rate programming resistor

20

kΩ

30

C_PVDD

PVDD close decoupling capacitors

Over-current programming resistor

μF

kΩ

R_OC

Resistor tolerance = 5%

30

64

R_OC(LATCHED)

47

Voltage on FREQ_ADJ pin for slave mode

operation

V_{(FREQ_ADJ)}

V_IH(DigIn)

V_IL(DigIn)

T_J

Slave mode

3.3

0

V

Input logic high for DAC_DVDD referenced

0.9 ×

V_{DAC_DVDD}

(2)

digital inputs⁽¹⁾

Input logic low for DAC_DVDD referenced

0.1 ×

V_{DAC_DVDD}

0

V

(3)

digital inputs⁽¹⁾

Junction temperature

125

°C

(1) DAC_DVDD referenced digital pins include: ADR, LRCK, MCLK, DAC_MUTE, SCL, SCLK, SDA, SDIN, SDOUT and XPU.

(2) Front-end (DAC and DSP) pins should be referenced to DAC_DVDD. Power stage digital pins should be referenced to DVDD.

(3) All TAS3251 ground pins should be referenced to the system ground.

7.4 Thermal Information

TAS3251

DKQ 56-PIN (HSSOP)

THERMAL METRIC⁽¹⁾

UNIT

JEDEC STANDARD 4-

LAYER PCB

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

47.8

0.3

°C/W

R_θJC(top)

R_θJB

°C/W

24.2

0.2

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

20.6

n/a

R_θJC(bot)

(1) For more information about traditional and new thermalmetrics, see the Semiconductor and ICPackage Thermal Metrics application

report.

8

TAS3251

www.ti.com.cn

ZHCSIA0A –MAY 2018–REVISED NOVEMBER 2018

7.5 Amplifier Electrical Characteristics

PVDD_X = 36 V, GVDD_X = 12 V, VDD = 12 V, T_C(Case temperature) = 75°C, f_s= 600 kHz, unless otherwise specified.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

AMPLIFIER INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION

DVDD

AVDD

Voltage regulator for internal use

VDD = 12 V

50% duty cycle

Reset mode

3

3.3

7.8

90

3.6

V

mA

I_{GVDD_A + GVDD_B + VDD}

GVDD and VDD supply current

PVDD idle current

19

50% duty cycle with recommended

output filter

20

mA

I_{PVDD_X}

Reset mode, no switching

0.0048

ANALOG INPUTS

R_IN

Input resistance

24

7

kΩ

Maximum input voltage swing,

SPK_INx pins

V_IN

V

Maximum input current, SPK_INx

pins

I_IN

G

1

mA

dB

Inverting voltage gain

Amplifier VOUT/VIN

20

AMPLIFIER OSCILLATOR

Nominal, Master Mode

F_PWM× 6

3.45

2.85

2.58

1.86

3.6

3

3.75

3.15

2.82

MHz

V

f_OSC(IO+)

AM1, Master Mode

AM2, Master Mode

2.7

V_IH

V_IL

High level input voltage

Low level input voltage

1.45

V

OUTPUT-STAGE MOSFETs

Drain-to-source resistance, low-side

T_J= 25°C, Includes metallization

resistance, GVDD = 12 V

60

100

mΩ

(LS)

R_DS(on)

Drain-to-source resistance, high-side T_J= 25°C, Includes metallization

(HS) resistance, GVDD = 12 V

AMPLIFIER I/O PROTECTION

Undervoltage protection limit,

GVDD_X and VDD

V_uvp,VDD,GVDD

V_{uvp,VDD, GVDD,hyst}

OTW

9.5

0.6

125

25

V

Undervoltage protection hysteresis,

GVDD_X and VDD

Over-temperature warning,

115

145

135

165

°C

(1)

CLIP_OTW

Temperature drop required to remove

OTW event on CLIP_OTW

OTW_hyst

OTE

Over-temperature error

OTE - OTW differential

155

30

°C

OTE-OTW_{(differential)}

A reset is required to clear an OTE

event

OTE_hyst

OLPC

25

°C

Overload protection counter for CB3C F_PWM= 600 kHz (1024 PWM cycles

mode

1.7

ms

for all F_PWM)

Resistor – programmable, nominal

peak current in 1Ω load, R_OCP= 22

kΩ

I_OC

Overcurrent limit for CB3C mode

14

A

Resistor – programmable, peak

current in 1Ω load, R_OCP= 47kΩ

I_OC(LATCHED)

I_DCspkr

I_OCT

Overcurrent limit for latched mode

14

1.5

150

3

A

DC speaker protection current

threshold

BTL current imbalance threshold

Time from switching transition to

flip-state induced by overcurrent

Overcurrent response time

ns

mA

Output pulldown current of each half- Connected when RESET is active to

bridge provide bootstrap charge

I_PD

(1) Specified by design.

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Amplifier Electrical Characteristics (continued)

PVDD_X = 36 V, GVDD_X = 12 V, VDD = 12 V, T_C(Case temperature) = 75°C, f_s= 600 kHz, unless otherwise specified.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

AMPLIFIER STATIC DIGITAL SPECIFICATIONS

MODE, OSC_IOP, OSC_IOM,

RESET_AMP

V_IH

V_IL

I_lkg

High-level input voltage

Low-level input voltage

Input leakage current

1.9

V

MODE, OSC_IOP, OSC_IOM,

RESET_AMP

0.8

MODE, OSC_IOP, OSC_IOM,

RESET_AMP

100

μA

AMPLIFIER OTW/SHUTDOWN (FAULT)

Internal pullup resistance, CLIP_OTW

R_{INT_PU}

20

3

26

32

kΩ

to DVDD, FAULT to DVDD

High-level output voltage

Low-level output voltage

CLIP_OTW, FAULT

V_OH

Internal pullup resistor

IO = 4 mA

3.3

200

30

3.6

V

V_OL

500

mV

Device fanout

No external pullup

devices

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ZHCSIA0A –MAY 2018–REVISED NOVEMBER 2018

7.6 DAC Electrical Characteristics

Free-air room temperature 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL I/O

Input logic high threshold for

DAC_DVDD referenced digital

inputs⁽¹⁾

V_IH1

70%

V_{DAC_DVDD}

µA

Input logic low threshold for

DAC_DVDD referenced digital

inputs⁽¹⁾

V_IL1

I_IH1

I_IL1

30%

10

Input logic high current level for

DAC_DVDD referenced digital

input pins⁽¹⁾

V_IN(DigIn)= V_{DAC_DVDD}

Input logic low current level for

DAC_DVDD referenced digital

input pins⁽¹⁾

V_IN(DigIn)= 0 V

–10

µA

V_OH(DigOut)

V_OL(DigOut)

I²C CONTROL PORT

Output logic high voltage level⁽¹⁾

Output logic low voltage level⁽¹⁾

I_OH= 4 mA

80%

V_{DAC_DVDD}

I_OH= –4 mA

22%

400

Allowable load capacitance for

C_L(I2C)

pF

each I²C Line

f_SCL(fast)

f_SCL(slow)

Support SCL frequency

No wait states, fast mode

No wait states, slow mode

400

100

kHz

Noise margin at High level for

each connected device (including

hysteresis)

0.2 ×

V_{DAC_DVDD}

V_NH

V

MCLK AND PLL SPECIFICATIONS

D_MCLKAllowable MCLK duty cycle

f_MCLK

40%

128

60%

512

(2)

Supported MCLK frequencies

Up to 50 MHz

f_S

Clock divider uses fractional divide

D > 0, P = 1

6.7

1

20

f_PLL

PLL input frequency

MHz

Clock divider uses integer divide

D = 0, P = 1

SERIAL AUDIO PORT

Required LRCK/FS to SCLK rising

edge delay

t_DLY

5

ns

D_SCLK

f_S

f_SCLK

Allowable SCLK duty cycle

Supported input sample rates

Supported SCLK frequencies

SCLK frequency

40%

8

60%

96

kHz

(2)

32

64

f_S

Either master mode or slave mode

24.576

MHz

(1) DAC_DVDD referenced digital pins include: ADR, LRCK, MCLK, DAC_MUTE, SCL, SCLK, SDA, SDIN, SDOUT and XPU.

(2) A unit of f_Sindicates that the specification is the value listed in the table multiplied by the sample rate of the audio used in the TAS3251

device.

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7.7 Audio Characteristics (BTL)

PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 36 V,

GVDD_X = 12 V, R_L= 4 Ω, f_S= 600 kHz, R_OC= 22 kΩ, T_C= 75°C, Output Filter: L_DEM= 10 μH, C_DEM= 1 µF, MODE = 0,

AES17 + AUX-0025 measurement filters, unless otherwise noted.

PARAMETER

TEST CONDITIONS

R_L= 3 Ω, 10% THD+N

R_L= 4 Ω, 10% THD+N

R_L= 3 Ω, 1% THD+N

R_L= 4 Ω, 1% THD+N

1 W

MIN

TYP

220

MAX

UNIT

175

P_O

Power output per channel

W

175

140

THD+N

V_n

Total harmonic distortion + noise

Output integrated noise

0.008

%

A-weighted, AES17 filter,

input capacitor grounded

95

μV

|V_OS

|

Output offset voltage

Signal-to-noise ratio⁽¹⁾

Inputs AC coupled to GND

20

60

mV

dB

SNR

DNR

108

110

Dynamic range

Power dissipation due to Idle losses

P_O= 0, 4 channels

switching⁽²⁾

P_idle

0.75

W

(I_{PVDD_X}

)

(1) SNR is calculated relative to 1% THD+N outputlevel.

(2) Actual system idle losses also are affected by core losses of output inductors.

7.8 Audio Characteristics (PBTL)

PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 36 V,

GVDD_X = 12 V, R_L= 2 Ω, f_S= 600 kHz, R_OC= 22 kΩ, T_C= 75°C, Output Filter: L_DEM= 10 μH, C_DEM= 1 µF, MODE = 1,

outputs paralleled after LC filter, AES17 + AUX-0025 measurement filters, unlessotherwise noted.

PARAMETER

TEST CONDITIONS

R_L= 2 Ω, 10% THD+N

R_L= 3 Ω, 10% THD+N

R_L= 4 Ω, 10% THD+N

R_L= 2 Ω, 1% THD+N

R_L= 3 Ω, 1% THD+N

R_L= 4 Ω, 1% THD+N

1 W

MIN

TYP

355

MAX

UNIT

250

195

P_O

Power output per channel

W

285

200

155

THD+N

V_n

Total harmonic distortion + noise

Output integrated noise

0.009

%

A-weighted, AES17 filter,

input capacitor grounded

95

μV

SNR

DNR

Signal to noise ratio⁽¹⁾

Dynamic range

A-weighted

108

dB

Power dissipation due to idle losses

(IPVDD_X)

P_O= 0, 4 channels

switching⁽²⁾

P_idle

0.75

W

(1) SNR is calculated relative to 1% THD+N output level.

(2) Actual system idle losses are affected by core losses of output inductors.

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ZHCSIA0A –MAY 2018–REVISED NOVEMBER 2018

7.9 MCLK Timing

See 图 1.

PARAMETER

MIN

20

9

MAX

UNIT

ns

t_MCLK

MCLK period

MCLK pulse width, high

MCLK pulse width, low

1000

t_MCLKH

t_MCLKL

ns

9

ns

7.10 Serial Audio Port Timing – Slave Mode

See 图 2.

PARAMETER

MIN

1.024

40

16

8

MAX

UNIT

MHz

ns

f_SCLK

t_SCLK

t_SCLKL

t_SCLKH

t_SL

SCLK frequency

SCLK period

SCLK pulse width, low

ns

SCLK pulse width, high

ns

SCLK rising to LRCK/FS edge

LRCK/FS Edge to SCLK rising edge

Data setup time, before SCLK rising edge

Data hold time, after SCLK rising edge

Data delay time from SCLK falling edge

ns

t_LS

8

ns

t_SU

8

ns

t_DH

8

ns

t_DFS

15

ns

7.11 Serial Audio Port Timing – Master Mode

See 图 3.

PARAMETER

MIN

40

16

–10

8

MAX

UNIT

ns

t_SCLK

t_SCLKL

t_SCLKH

t_LRD

SCLK period

SCLK pulse width, low

ns

SCLK pulse width, high

ns

LRCK/FS delay time from to SCLK falling edge

Data setup time, before SCLK rising edge

Data hold time, after SCLK rising edge

Data delay time from SCLK falling edge

20

15

ns

t_SU

ns

t_DH

8

ns

t_DFS

ns

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7.12 I²C Bus Timing –Standard

MIN

MAX

UNIT

kHz

µs

f_SCL

SCL clock frequency

400

t_BUF

Bus free time between a STOP and START condition

Low period of the SCL clock

High period of the SCL clock

Setup time for (repeated) START condition

Hold time for (repeated) START condition

Data setup time

4.7

t_LOW

t_HI

4.7

µs

4

µs

t_RS-SU

t_S-HD

t_D-SU

t_D-HD

t_SCL-R

4.7

µs

4

µs

250

0

ns

Data hold time

900

ns

Rise time of SCL signal

20 + 0.1C_B

1000

ns

Rise time of SCL signal after a repeated START condition and after an

acknowledge bit

t_SCL-R1

20 + 0.1C_B

1000

ns

t_SCL-F

t_SDA-R

t_SDA-F

t_P-SU

Fall time of SCL signal

20 + 0.1C_B

4

1000

ns

µs

Rise time of SDA signal

Fall time of SDA signal

Setup time for STOP condition

7.13 I²C Bus Timing –Fast

See 图 4.

MIN

MAX

UNIT

kHz

µs

f_SCL

SCL clock frequency

400

t_BUF

Bus free time between a STOP and START condition

Low period of the SCL clock

High period of the SCL clock

Setup time for (repeated)START condition

Hold time for (repeated)START condition

Data setup time

1.3

t_LOW

t_HI

µs

600

ns

t_RS-SU

t_RS-HD

t_D-SU

t_D-HD

t_SCL-R

600

ns

600

ns

100

ns

Data hold time

0

900

300

ns

Rise time of SCL signal

20 + 0.1C_B

ns

Rise time of SCL signal after a repeated START condition and after an

acknowledge bit

t_SCL-R1

20 + 0.1C_B

300

ns

t_SCL-F

t_SDA-R

t_SDA-F

t_P-SU

t_SP

Fall time of SCL signal

20 + 0.1C_B

600

300

ns

Rise time of SDA signal

Fall time of SDA signal

Setup time for STOP condition

Pulse width of spike suppressed

50

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7.14 Timing Diagrams

This section contains timing diagrams for I²C and I²S / TDM.

t

MCLKH

"H"

"L"

0.7 × V

DVDD

0.3 × V

DVDD

t

MCLKL

MCLK

图 1. Timing Requirements for MCLK Input

LRCK/FS

(Input)

0.5 × DVDD

t

SCLKL

SCLKH

t

LS

SCLK

(Input)

t

SL

SCLK

DATA

(Input)

0.5 × DVDD

t

DH

SU

t

DFS

DATA

(Output)

图 2. MCLK Timing Diagram in Slave Mode

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ZHCSIA0A –MAY 2018–REVISED NOVEMBER 2018

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Timing Diagrams (接下页)

t_BCL

t

BCL

t

SCLK.

SCLK

(Input)

0.5 × DVDD

t

LRD

SCLK

LRCK/FS

(Input)

t

DFS

DATA

(Input)

0.5 × DVDD

t

DH

SU

DATA

(Output)

0.5 × DVDD

图 3. MCLK Timing Diagram in Master Mode

Repeated

START

STOP

t

P-SU

t

D-SU

D-HD

SDA-F

SDA-R

t

BUF.

SDA

t

SP

SCL-R.

RS-HD

t

LOW.

SCL

t

HI.

t

RS-SU

t

SCL-F.

S-HD.

图 4. I²C Communication Port Timing Diagram

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7.15 Typical Characteristics

7.15.1 BTL Configuration

All Measurements taken at audio frequency = 1 kHz, PVDD_X = 36 V, GVDD_X = 12 V, R_L= 4 Ω, f_S= 600 kHz,

R_OC= 22 kΩ, T_C= 75°C, Output Filter: L_DEM= 10 μH, C_DEM= 1 µF, MODE = 0, AES17 + AUX-0025

measurement filters, unless otherwise noted.

10

1

10

1

1 W

20 W

75 W

3 W

4 W

8 W

0.1

0.01

0.1

0.01

0.001

0.0005

10m

100m

1

10

100 300

20

100

1k

10k 20k

Po - Output Power - W

f - Frequency - Hz

D001

D002

T_C= 75°C

R_L= 4 Ω

T_C= 75°C

图 5. Total Harmonic Distortion+Noise vs Output Power

图 6. Total Harmonic Distortion+Noise vs Frequency

240

3 W

4 W

200

3 W

4 W

200

8 W

160

120

80

40

0

120

80

40

0

10

15

20

25

30

35

40

10

15

20

25

30

35

40

PVDD - Supply Voltage - V

D004

D005

THD+N = 10%

T_C= 75°C

THD+N = 1%

T_C= 75°C

图 7. Output Power vs Supply Voltage

图 8. Output Power vs Supply Voltage

100

10

1

75

50

25

0

3 W

4 W

8 W

3 W

4 W

8 W

10m

100m

1

10

100

500

2 Channel Output Power - W

0

100

200

300

400 450

D006

2 Channel Output Power - W

D007

T_C= 75°C

图 9. Efficiency vs Output Power

T_C= 75°C

图 10. Power Loss vs Output Power

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BTL Configuration (接下页)

0

-20

250

4 W

200

150

100

-40

-60

-80

-100

-120

-140

-160

50

3 W

4 W

8 W

0

25

50

75

100

0

5k 10k 15k 20k 25k 30k 35k 40k 45k48k

f - Frequency - Hz

T_C- Case Temperature - èC

D008

D009

THD+N = 10%

T_C= 75°C

V_REF= 25.46 V FFT = 16384

80 kHz analyzer BW

AUX-0025 filter

图 11. Output Power vs Temperature

图 12. Noise vs Frequency

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7.15.2 PBTL Configuration

All Measurements taken at audio frequency = 1 kHz, PVDD_X = 36 V, GVDD_X = 12 V, R_L= 2 Ω, f_S= 600 kHz,

R_OC= 22 kΩ, T_C= 75 °C, Output Filter: L_DEM= 10 μH, C_DEM= 1 µF, MODE = 1, outputs paralleled after LC filter,

AES17 + AUX-0025 measurement filters, unless otherwise noted.

10

1

10

1

2 W

3 W

4 W

1 W

50 W

150 W

0.1

0.01

0.001

10m

100m

1

10

100

400

20

100

1k

10k 20k

Po - Output Power - W

f - Frequency - Hz

D010

D011

T_C= 75°C

R_L= 3 Ω

T_C= 75°C

图 13. Total Harmonic Distortion+Noise vs Output Power

图 14. Total Harmonic Distortion+Noise vs Frequency

360

300

2 W

3 W

2 W

3 W

4 W

320

280

240

200

160

120

80

250

4 W

200

150

100

50

40

0

10

15

20

25

30

35

40

10

15

20

25

30

35

40

PVDD - Supply Voltage - V

D013

D014

THD+N = 10%

T_C= 75°C

THD+N = 1%

T_C= 75°C

图 16. Output Power vs Supply Voltage

图 15. Output Power vs Supply Voltage

100

10

1

75

50

25

0

2 W

3 W

4 W

2 W

3 W

4 W

T_C= 75èC

10m

100m

1

10

100

500

0

100

200

300

400

Output Power - W

D015

D016

T_C= 75°C

图 17. Efficiency vs Output Power

T_C= 75°C

图 18. Power Loss vs Output Power

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PBTL Configuration (接下页)

350

300

250

200

150

100

0

-20

2 W

-40

-60

-80

-100

-120

-140

-160

2

3

4

W

50

0

25

50

75

100

0

5k

10k 15k 20k 25k 30k 35k 40k 45k48k

f - Frequency - Hz

T_C- Case Temperature - èC

D0127

D018

THD+N = 10%

图 19. Output Power vs Temperature

T_C= 75°C

V_REF= 25.46 V FFT = 16384

80 kHz analyzer BW

AUX-0025 filter

图 20. Noise vs Frequency

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ZHCSIA0A –MAY 2018–REVISED NOVEMBER 2018

8 Detailed Description

8.1 Overview

The TAS3251 device integrates four main building blocks into a single cohesive device that maximizes sound

quality, flexibility, and ease of use. These include:

•

Burr-Brown™ stereo audio DAC with a highly flexible serial audio port

µCDSP, TI's latest audio processing core with a pre-programmed DSP audio process flows

High-Performance, Ultra-HD Closed-loop Class-D amplifier capable of operating in stereo or mono

An I²C control port for communication and control of the device

The device requires three power supplies for proper operation. A 3.3 V rail for the low voltage circuitry and DAC,

a 12 V rail for the amplifier gate-drive, and PVDD which is required to provide power to the output stage of the

audio amplifier. The operating range for these supplies is shown in the Recommended Operating Conditions.

The communication and control interface for the device uses I²C. A speaker amplifier fault output is also provided

to notify a system controller of the occurrence of an overtemperature, overcurrent or undervoltage event.

The µCDSP audio processing core is pre-programmed with configurable DSP programs. The PurePath™

Console 3 software with the TAS3251 App available on TI.com provides the tools to control and tune the pre-

programmed audio process flows.

8.2 Functional Block Diagram

Internal

Voltage

Supplies

Charge

Pump

Oscillator

Sync

1.8-V

Regulator

Internal Voltage

Supplies

Closed Loop Class D Amplifier

Gate

SPK_OUTA+

SPK_OUTA-

SPK_OUTB+

SPK_OUTB-

Full Bridge

Power Stage

A

µCDSP

Output

Current

Monitoring

and

Drives

Analog

to

MCLK

SCLK

PWM

Selectable

Process

Flows

Modulator

Full Bridge

Power Stage

B

Gate

Protection

DAC

Drives

Serial

Audio

Port

LRCK/FS

SDIN

Clock Monitoring and

Error Protection

Die Temperature

Monitoring and Protection

Error Reporting

SDOUT

Control Registers & Error Reporting

Internal Control Registers and State Machines

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8.3 Feature Description

8.3.1 Power-on-Reset (POR) Function

The TAS3251 device has a power-on reset function. The power-on reset feature resets all of the registers to their

default configuration as the device is powering up. When the low-voltage power supply used to power DVDD,

AVDD, and CPVDD exceeds the POR threshold, the device sets all of the internal registers to their default

values and holds them there until the device receives valid MCLK, SCLK, and LRCK/FS toggling for a period of

approximately 4 ms. After the toggling period has passed, the internal reset of the registers is removed and the

registers can be programmed via the I²C Control Port.

8.3.2 Enable Device

To enable the device and play audio after power is applied write the following to the device over I2C. book 0x00,

page 0x00, register 0x02 to 0x00. The following is a sample script for enabling the device:

w 90 00 00 # Go to page 0

w 90 7f 00 # Go to book 0

w 90 02 00 # Enable device

8.3.3 DAC and DSP Clocking

The TAS3251 front-end (DAC and DSP) has flexible systems for clocking. Internally, the device requires a

number of clocks, mostly at related clock rates to function correctly. All of these clocks can be derived from the

Serial Audio Interface in one form or another. See section Oscillator for Output Power Stagefor setting the output

stage oscillator and switching frequency.

f_S

(24-bit)

16 f_S

(24-bit)

128 f_S

(~8-bit)

Serial Audio

Interface

(Input)

µCDSP

(including

interpolator)

Delta

Sigma

Modulator

I to V

Line

Driver

Current

Segments

+

Audio

In

Audio

Out

Charge Pump

CPCK

DSPCK

OSRCK

DACCK

LRCK/FS

Figure 21. Audio Flow with Respective Clocks

Figure 21 shows the basic data flow at basic sample rate (f_S). When the data is brought into the serial audio

interface, the data is processed, interpolated and modulated to 128 × f_Sbefore arriving at the current segments

for the final digital to analog conversion.

Figure 22 shows the clock tree.

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ZHCSIA0A –MAY 2018–REVISED NOVEMBER 2018

Feature Description (continued)

PLLEN

(P0-R4)

MCLK

SREF

Divider

(P0-R13)

DDSP (P0-R27)

SCLK

GPIO

MCLK

SDAC

(P0-R14)

PLL

K × R/P

PLLCKIN

PLLCK

K = J.D

J = 1,2,3,…..,62,63

D= 0000,0001,….,9998,9999

R= 1,2,3,4,….,15,16

DACCK (DAC Clock )

MCLK

GPIO

Divider

CPCK (Charge Pump Clock )

DNCP (P0-R29)

P= 1,2,….,127,128

DDAC

(P0-R28)

Divider

OSRCK

(Oversampling

Ratio Clock )

Divider

MUX

DOSR

(P0-R30)

Divide

by 2

I16E (P0-R34)

Figure 22. TAS3251 Clock Distribution Tree

The Serial Audio Interface typically has 4 connection pins which are listed as follows:

•

MCLK (System Master Clock)

SCLK (Serial or Bit Clock)

LRCK/FS (Left-Right Word Clock and Frame Sync)

SDIN (Input Data)

SDOUT can be used to output pre- or post-processed DSP data for use externally (See the SDOUT Port and

Hardware Control Pins section)

The device has an internal PLL that is used to take either MCLK or SCLK and create the higher rate clocks

required by the DSP and the DAC clock.

In situations where the highest audio performance is required, bringing MCLK to the device along with SCLK and

LRCK/FS is recommended. The device should be configured so that the PLL is only providing a clock source to

the DSP. All other clocks are then a division of the incoming MCLK. To enable the MCLK as the main source

clock, with all others being created as divisions of the incoming MCLK, set the DAC CLK source mux (SDAC in

Figure 22) to use MCLK as a source, rather than the output of the MCLK/PLL mux.

8.3.3.1 Internal Clock Error Notification (CLKE)

When a clock error is detected on the incoming data clock, the TAS3251 device switches to an internal oscillator

and continues to the drive the DAC, while attenuating the data from the last known value. Once this process is

complete, the DAC outputs will be hard muted to the ground and the Class-D PWM output will stop switching.

The clock error can be monitored at B0-P0-R94 and R95. The clock error status bits are non-latching, except for

MCLK halted B0-P0-R95-D[4] which is cleared when read.

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Feature Description (continued)

8.3.4 Serial Audio Port

8.3.4.1 Clock Master Mode from Audio Rate Master Clock

In Master Mode, the device generates bit clock and left-right and frame sync clock and outputs them on the

appropriate pins. To configure the device in master mode, first put the device into reset, then use registers

SCLKO and LRKO (P0-R9). Then reset the LRCK/FS and SCLK divider counters using bits RSCLK and RLRK

(P0-R12). Finally, exit reset.

Figure 23 shows a simplified serial port clock tree for the device in master mode.

Audio Related System Clock (MCLK)

MCLK

SCLKO (Bit Clock Output In Master Mode)

Divider

Q1 = 1...128

SCLK

LRCK/FS (LR Clock or Frame Sync Output In

Master Mode

Divider

LRCK/FS

Q1 = 1...128

Figure 23. Simplified Clock Tree for MCLK Sourced Master Mode

In master mode, MCLK is an input and SCLK and LRCK/FS are outputs. SCLK and LRCK/FS are integer

divisions of MCLK. Master mode with a non-audio rate master clock source requires external GPIO’s to use the

PLL in standalone mode. The PLL should be configured to ensure that the on-chip processor can be driven at

the maximum clock rate. The master mode of operation is described in the section.

When used with audio rate master clocks, the register changes that should be done include switching the device

into master mode, and setting the divider ratio. An example of the master mode of operations is using 24.576

MHz MCLK as a master clock source and driving the SCLK and LRCK/FS with integer dividers to create 48 kHz

sample rate clock output. In master mode, the DAC section of the device is also running from the PLL output.

The TAS3251 device is able to meet the specified audio performance while using the internal PLL. However,

using the MCLK CMOS oscillator source will have less jitter than the PLL.

To switch the DAC clocks (SDAC in the Figure 22) the following registers should be modified

•

Clock Tree Flex Mode (P253-R63 and P253-R64)

DAC and OSR Source Clock Register (P0-R14). Set to 0x30 (MCLK input, and OSR is set to whatever the

DAC source is)

•

The DAC clock divider should be 16 f_S.

–

16 × 48 kHz = 768 kHz

24.576 MHz (MCLK in) / 768 kHz = 32

Therefore, the divide ratio for register DDAC (P0-R28) should be set to 32. The register mapping gives

0x00 = 1, therefore 32 must be converter to 0x1F (31dec).

8.3.4.2 Clock Slave Mode with 4-Wire Operation (SCLK, MCLK, LRCK/FS, SDIN)

The TAS3251 device requires a system clock to operate the digital interpolation filters and advanced segment

DAC modulators. The system clock is applied at the MCLK input and supports up to 50 MHz. The TAS3251

device system-clock detection circuit automatically senses the system-clock frequency. Common audio sampling

frequencies in the bands of 32 kHz, (44.1 – 48 kHz), (88.2 – 96 kHz) are supported.

NOTE

Values in the parentheses are grouped when detected, for example, 88.2 kHz and 96 kHz

are detected as double rate, 32 kHz, 44.1 kHz and 48 kHz are detected as single rate and

so on.

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Feature Description (continued)

In the presence of a valid bit MCLK, SCLK and LRCK/FS, the device automatically configures the clock tree and

PLL to drive the miniDSP as required.

The sampling frequency detector sets the clock for the digital filter, Delta Sigma Modulator (DSM) and the

Negative Charge Pump (NCP) automatically. Table 3 shows examples of system clock frequencies for common

audio sampling rates.

MCLK rates that are not common to standard audio clocks, between 1 MHz and 50 MHz, are supported by

configuring various PLL and clock-divider registers directly. In slave mode, auto clock mode should be disabled

using P0-R37. Additionally, the user can be required to ignore clock error detection if external clocks are not

available for some time during configuration, or if the clocks presented on the pins of the device are invalid. The

extended programmability allows the device to operate in an advanced mode in which the device becomes a

clock master and drive the host serial port with LRCK/FS and SCLK, from a non-audio related clock (for

example, using a setting of 12 MHz to generate 44.1 kHz [LRCK/FS] and 2.8224 MHz [SCLK]).

Table 3 shows the timing requirements for the system clock input. For optimal performance, use a clock source

with low phase jitter and noise. For MCLK timing requirements, refer to the Serial Audio Port Timing – Master

Mode section.

Table 3. System Master Clock Inputs for Audio Related Clocks

SYSTEM CLOCK FREQUENCY (f_MCLK) (MHz)

SAMPLING

FREQUENCY

64 f_S

128 f_S

1.024

192 f_S

1.536

256 f_S

2.048

384 f_S

3.072

512 f_S

4.096

8 kHz

16 kHz

32 kHz

44.1 kHz

48 kHz

88.2 kHz

96 kHz

2.048

3.072

4.096

6.144

8.192

4.096

6.144

8.192

12.288

16.9344

18.432

33.8688

36.864

16.384

22.5792

24.576

45.1584

49.152

See

5.6488

6.144

8.4672

9.216

11.2896

12.288

22.5792

24.576

11.2896

12.288

16.9344

18.432

8.3.4.3 Clock Slave Mode with SCLK PLL to Generate Internal Clocks (3-Wire PCM)

8.3.4.3.1 Clock Generation Using the PLL

The TAS3251 device supports a wide range of options to generate the required clocks as shown in Figure 22.

The clocks for the PLL require a source reference clock. This clock is sourced as the incoming SCLK or MCLK, a

GPIO can also be used.

The source reference clock for the PLL reference clock is selected by programming the SRCREF value on P0-

R13, D[6:4]. The TAS3251 device provides several programmable clock dividers to achieve a variety of sampling

rates. See Figure 22.

If PLL functionality is not required, set the PLLEN value on P0-R4, D[0] to 0. In this situation, an external master

clock is required.

Table 4. PLL Configuration Registers

CLOCK MULTIPLEXER

REGISTER

SREF

FUNCTION

PLL Reference

BITS

B0-P0-R13-D[6:4]

DDSP

clock divider

B0-P0-R27-D[6:0]

B0-P0-R32-D[6:0]

B0-P0-R33-D[7:0]

DSCLK

DLRK

External SCLK Div

External LRCK/FS Div

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8.3.4.3.2 PLL Calculation

The TAS3251 device has an on-chip PLL with fractional multiplication to generate the clock frequency required

by the Digital Signal Processing blocks. The programmability of the PLL allows operation from a wide variety of

clocks that may be available in the system. The PLL input (PLLCKIN) supports clock frequencies from 1 MHz to

50 MHz and is register programmable to enable generation of required sampling rates with fine precision.

The PLL is enabled by default. The PLL can be enabled by writing to P0-R4, D[0]. When the PLL is enabled, the

PLL output clock PLLCK is given by Equation 1:

PLLCKIN x R x J.D

P

PLLCKIN x R x K

P

PLLCK =

or PLLCK =

where

•

R = 1, 2, 3,4, ... , 15, 16

J = 4,5,6, . . . 63, and D = 0000, 0001, 0002, . . . 9999

K = [J value].[D value]

P = 1, 2, 3, ... 15

(1)

R, J, D, and P are programmable. J is the integer portion of K (the numbers to the left of the decimal point), while

D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of precision).

8.3.4.3.2.1 Examples:

•

If K = 8.5, then J = 8, D = 5000

If K = 7.12, then J = 7, D = 1200

If K = 14.03, then J = 14, D = 0300

If K = 6.0004, then J = 6, D = 0004

When the PLL is enabled and D = 0000, the following conditions must be satisfied:

•

1 MHz ≤ ( PLLCKIN / P ) ≤ 20 MHz

64 MHz ≤ (PLLCKIN x K x R / P ) ≤ 100 MHz

1 ≤ J ≤ 63

When the PLL is enabled and D ≠ 0000, the following conditions must be satisfied:

•

6.667 MHz ≤ PLLCLKIN / P ≤ 20 MHz

64 MHz ≤ (PLLCKIN x K x R / P ) ≤ 100 MHz

4 ≤ J ≤ 11

R = 1

When the PLL is enabled,

•

f_S= (PLLCLKIN × K × R) / (2048 × P)

The value of N is selected so that f_S× N = PLLCLKIN x K x R / P is in the allowable range.

Example: MCLK = 12 MHz and f_S= 44.1 kHz, (N=2048)

Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264

Example: MCLK = 12 MHz and f_S= 48.0 kHz, (N=2048)

Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920

Values are written to the registers in Table 5.

Table 5. PLL Registers

DIVIDER

PLLE

FUNCTION

PLL enable

PLL P

BITS

P0-R4, [0]

PPDV

PJDV

P0-R20, [3:0]

P0-R21, [5:0]

P0-R22, [5:0]

P0-R23, [7:0]

P0-R24, [3:0]

PLL J

PDDV

PRDV

PLL D

PLL R

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Table 6. PLL Configuration Recommendations

EQUATIONS

f_S(kHz)

DESCRIPTION

Sampling frequency

R_MCLK

Ratio between sampling frequency and MCLK frequency (MCLK frequency = RMCLK x sampling frequency)

System master clock frequency at MCLK input (pin 20)

MCLK (MHz)

PLL VCO (MHz) PLL VCO frequency as PLLCK in Figure 22

One of the PLL coefficients in Equation 1

PLL REF (MHz) Internal reference clock frequency which is produced by MCLK / P

P

M = K × R

K = J.D

R

The final PLL multiplication factor computed from K and R as described in Equation 1

One of the PLL coefficients in Equation 1

PLL f_S

DSP f_S

NMAC

Ratio between f_Sand PLL VCO frequency (PLL VCO / f_S)

Ratio between operating clock rate and f_S(PLL f_S/ NMAC)

The clock divider value in Table 4

DSP CLK (MHz) The operating frequency as DSPCK in Figure 22

MOD f_S

Ratio between DAC operating clock frequency and f_S(PLL f_S/ NDAC)

MOD f (kHz)

NDAC

DAC operating frequency as DACCK in

DAC clock divider value in Table 4

OSR clock divider value in Table 4 for generating OSRCK in Figure 22. DOSR must be chosen so that MOD f_S/ DOSR =

16 for correct operation.

DOSR

NCP

CP f

NCP (negative charge pump) clock divider value in Table 4

Negative charge pump clock frequency (f_S× MOD f_S/ NCP)

Percentage of error between PLL VCO / PLL f_Sand f_S(mismatch error).

% Error

•

This value is typically zero but can be non-zero especially when K is not an integer (D is not zero).

This value can be non-zero only when the TAS3251 device acts as a master.

The previous equations explain how to calculate all necessary coefficients and controls to configure the PLL.

Table 7 provides for easy reference to the recommended clock divider settings for the PLL as a Master Clock.

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8.3.4.4 Serial Audio Port – Data Formats and Bit Depths

The serial audio interface port is a 3-wire serial port with the signals LRCK/FS (pin 25), SCLK (pin 23), and SDIN

(pin 24). SCLK is the serial audio bit clock, used to clock the serial data present on SDIN into the serial shift

register of the audio interface. Serial data is clocked into the TAS3251 device on the rising edge of SCLK.The

LRCK/FS pin is the serial audio left/right word clock or frame sync when the device is operated in TDM Mode.

Table 8. TAS3251 device Audio Data Formats, Bit Depths and Clock Rates

MAXIMUM LRCK/FS

FREQUENCY (kHz)

FORMAT

DATA BITS

MCLK RATE (f_S)

SCLK RATE (f_S)

I²S/LJ/RJ

32, 24, 20, 16

Up to 96

128 to 3072 (≤ 50 MHz)

128 to 3072

64, 48, 32

125, 256

Up to 48

TDM/DSP

32, 24, 20, 16

96

128 to 512

The TAS3251 device requires the synchronization of LRCK/FS and system clock, but does not require a specific

phase relation between LRCK/FS and system clock.

If the relationship between LRCK/FS and system clock changes more than ±5 MCLK, internal operation is

initialized within one sample period and analog outputs are forced to the bipolar zero level until re-

synchronization between LRCK/FS and system clock is completed.

If the relationship between LRCK/FS and SCLK are invalid more than 4 LRCK/FS periods, internal operation is

initialized within one sample period and analog outputs are forced to the bipolar zero level until re-

synchronization between LRCK/FS and SCLK is completed.

8.3.4.4.1 Data Formats and Master/Slave Modes of Operation

The TAS3251 device supports industry-standard audio data formats, including standard I²S and left-justified.

Data formats are selected via Register (P0-R40). All formats require binary two's complement, MSB-first audio

data; up to 32-bit audio data is accepted. The data formats are detailed in Figure 24 through Figure 29.

The TAS3251 device also supports right-justified and TDM/DSP data. I²S, LJ, RJ, and TDM/DSP are selected

using Register (P0-R40). All formats require binary 2s complement, MSB-first audio data. Up to 32 bits are

accepted. Default setting is I²S and 24 bit word length. The I²S slave timing is shown in 图 3.

shows a detailed timing diagram for the serial audio interface.

In addition to acting as a I²S slave, the TAS3251 device can act as an I²S master, by generating SCLK and

LRCK/FS as outputs from the MCLK input. Table 9 lists the registers used to place the device into Master or

Slave mode. Please refer to the Serial Audio Port Timing – Master Mode section for serial audio Interface timing

requirements in Master Mode. For Slave Mode timing, please refer to to the Serial Audio Port Timing – Slave

Mode section.

Table 9. I²S Master Mode Registers

REGISTER

FUNCTION

P0-R9-B0, B4, and B5

P0-R32-D[6:0]

I²S Master mode select

SCLK divider and LRCK/FS divider

P0-R33-D[7:0]

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1 t_{S .}

Right-channel

Left-channel

LRCK/FS

SLCK

…

Audio data word = 16-bit, SLCK = 32, 48, 64f_S

…

1

2

15 16

1

2

15 16

DATA

LSB

MSB

Audio data word = 24-bit, SLCK = 48, 64f_S

…

2

1

2

24

2

23 24

DATA

LSB

MSB

Audio data word = 32-bit, SLCK = 64f_S

…

1

2

31 32

1

2

31 32

DATA

MSB

LSB

MSB

LSB

Figure 24. Left Justified Audio Data Format

1 t_{S .}

LRCK/FS

SLCK

Left-channel

Right-channel

…

Audio data word = 16-bit, SLCK = 32, 48, 64f_S

…

1

2

15 16

1

2

15 16

DATA

LSB

MSB

Audio data word = 24-bit, SLCK = 48, 64f_S

…

2

23 24

1

23 24

DATA

LSB

MSB

LSB

MSB

Audio data word = 32-bit, SLCK = 64f_S

…

1

2

31 32

1

2

31 32

DATA

MSB

LSB

MSB

LSB

I²S Data Format; L-channel = LOW, R-channel = HIGH

Figure 25. I²S Audio Data Format

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1 /f_{S .}

Right-channel

Left-channel

LRCK/FS

SLCK

…

Audio data word = 16-bit, SLCK = 32, 48, 64f_S

DATA

…

1

2

15 16

1

2

15 16

LSB

MSB

Audio data word = 24-bit, SLCK = 48, 64f_S

…

2

1

2

24

1

2

23 24

DATA

MSB

LSB

MSB

LSB

Audio data word = 32-bit, SLCK = 64f_S

…

1

2

31 32

1

2

31 32

DATA

MSB

LSB

MSB

LSB

Right Justified Data Format; L-channel = HIGH, R-channel = LOW

Figure 26. Right Justified Audio Data Format

1 /f_{S .}

LRCK/FS

SLCK

…

Audio data word = 16-bit, Offset = 0

…

1

2

15 16

1

2

15 16

1

DATA

Data Slot 1

Data Slot 2

LSB

MSB

LSB

MSB

Audio data word = 24-bit, Offset = 0

-

,

…

1

2

23 24

1

2

23 24

LSB

DATA

Data Slot 1

LSB

MSB

Audio data word = 32-bit, Offset = 0

…

1

2

31 32

LSB

1

2

31 32

LSB

DATA

MSB

TDM/DSP Data Format with OFFSET = 0

In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.

Figure 27. TDM/DSP 1 Audio Data Format

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1 /f_{S .}

OFFSET = 1

LRCK/FS

…

SLCK

Audio data word = 16-bit, Offset = 1

…

1

2

15 16

1

2

15 16

1

DATA

Data Slot 1

LSB

Data Slot 2

LSB

MSB

Audio data word = 24-bit, Offset = 1

…

1

2

23 24

1

2

23 24

LSB

DATA

Data Slot 1

Data Slot 2

LSB

MSB

Audio data word = 32-bit, Offset = 1

…

1

2

31 32

LSB

1

2

31 32

DATA

Data Slot 1

Data Slot 2

LSB

MSB

TDM/DSP Data Format with OFFSET = 1

In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.

Figure 28. TDM/DSP 2 Audio Data Format

1 /f_{S .}

OFFSET = n

LRCK/FS

SLCK

…

Audio data word = 16-bit, Offset = n

…

1

2

15 16

1

2

15 16

DATA

Data Slot 1

LSB

Data Slot 2

LSB

MSB

Audio data word = 24-bit, Offset = n

…

1

2

23 24

1

2

23 24

LSB

DATA

Data Slot 1

Data Slot 2

LSB

MSB

Audio data word = 32-bit, Offset = n

…

1

2

31 32

LSB

1

2

31 32

LSB

DATA

Data Slot 1

Data Slot 2

MSB

TDM/DSP Data Format with OFFSET = N

In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is considered frame start.

Figure 29. TDM/DSP 3 Audio Data Format

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8.3.4.5 Input Signal Sensing (Power-Save Mode)

The TAS3251 device has a zero-detect function. The zero-detect function can be applied to both channels of

data as an AND function or an OR function, via controls provided in the control port in P0-R65-D[2:1].Continuous

Zero data cycles are counted by LRCK/FS, and the threshold of decision for analog mute can be set by P0-R59,

D[6:4] for the data which is clocked in on the left frame of an I²S signal or Slot 1 of a TDM signal and P0-R59,

D[2:0] for the data which is clocked in on the right frame of an I²S signal or Slot 2 of a TDM signal as shown in

Table 11. Default values are 0 for both channels.

Table 10. Zero Detection Mode

ATMUTECTL

VALUE

FUNCTION

Zero data triggers for the two channels for zero detection are

ORed together.

0

Bit : 2

Zero data triggers for the two channels for zero detection are

ANDed together.

1 (Default)

0

Zero detection and analog mute are disabled for the data

clocked in on the right frame of an I²S signal or Slot 2 of a

TDM signal.

Bit : 1

Bit : 0

Zero detection analog mute are enabled for the data clocked in

on the right frame of an I²S signal or Slot 2 of a TDM signal.

1 (Default)

0

Zero detection analog mute are disabled for the data clocked

in on the left frame of an I²S signal or Slot 1 of a TDM signal.

Zero detection analog mute are enabled for the data clocked in

on the left frame of an I²S signal or Slot 1 of a TDM signal.

1 (Default)

Table 11. Zero Data Detection Time

ATMUTETIML OR ATMA

NUMBER OF LRCK/FS CYCLES

TIME at 48 kHz

21 ms

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

1024

5120

106 ms

10240

25600

51200

102400

256000

512000

213 ms

533 ms

1.066 secs

2.133 secs

5.333 secs

10.66 secs

8.3.5 Volume Control

8.3.5.1 DAC Digital Gain Control

A basic DAC digital gain control with range between 24 dB and –103 dB and mute is available on each channels

by P0-R61-D[7:0] for SPK_OUTB± and P0-R62-D[7:0] for SPK_OUTA±. These volume controls all have 0.5 dB

step programmability over most gain and attenuation ranges. Table 12 lists the detailed gain versus programmed

setting for the basic volume control. Volume can be changed for both SPK_OUTB± and SPK_OUTA± at the

same time or independently by P0-R61-D[1:0] . When D[1:0] set 00 (default), independent control is selected.

When D[1:0] set 01, SPK_OUTA± accords with SPK_OUTB± volume. When D[1:0] set 10, SPK_OUTA± volume

controls the volume for both channels. To set D[1:0] to 11 is prohibited.

Table 12. DAC Digital Gain Control Settings

GAIN

SETTING

GAIN

(dB)

BINARY DATA

COMMENTS

0

1

0000-0000

0000-0001

24.0

23.5

Positive maximum

.

46

0010-1110

1.0

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Table 12. DAC Digital Gain Control

Settings (continued)

GAIN

SETTING

GAIN

(dB)

BINARY DATA

COMMENTS

47

48

49

50

51

0010-1111

0011-0000

0011-0001

0011-0010

0011-0011

0.5

0.0

No attenuation (default)

–0.5

–1.0

–1.5

.

253

254

255

1111-1101

1111-1110

1111-1111

–102.5

–103

Negative maximum

–

Negative infinite (Mute)

∞

Ramp-up frequency and ramp-down frequency can be controlled by P0-R63, D[7:6] and D[3:2] as shown in

Table 13. Also ramp-up step and ramp-down step can be controlled by P0-R63, D[5:4] and D[1:0] as shown in

Table 14.

Table 13. Ramp Up or Down Frequency

RAMP UP

SPEED

RAMP DOWN

FREQUENCY

EVERY N f_S

COMMENTS

EVERY N f_S

COMMENTS

00

01

10

11

1

Default

00

01

10

11

1

Default

2

4

Direct change

Table 14. Ramp Up or Down Step

RAMP UP

STEP

RAMP DOWN

COMMENTS

STEP dB

COMMENTS

STEP

00

01

10

11

4.0

2.0

1.0

0.5

00

01

–4.0

–2.0

–1.0

–0.5

Default

10

11

Default

8.3.5.1.1 Emergency Volume Ramp Down

Emergency ramp down of the volume is provided for situations such as I²S clock error and power supply failure.

Ramp-down speed is controlled by P0-R64-D[7:6]. Ramp-down step can be controlled by P0-R64-D[5:4]. Default

is ramp-down by every f_Scycle with –4dB step.

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8.3.6 SDOUT Port and Hardware Control Pin

The TAS3251 device contains a versatile GPIO port (SDOUT pin), allowing signals to be passed from the system

to the device or sent from the device to the system. This pin can be used for advanced clocking features, to pass

internal signals to the system or accept signals from the system for use inside the device by a given process

flow. The SDOUT pin supports serial data out and the features described in Figure 30. The register map can be

used to configure the function of the SDOUT pin.

Here are a few key registers to enable the SDOUT pin:

•

Page 0, Register 7, Bit 0 (SDSL) - select if SDOUT data is pre-DSP or post-DSP processing.

Page 0, Register 9, Bit 5 (SDDIR) - select the SDOUT pin as input or output.

See register map for more details to configure the SDOUT pin function.

Internal Data

(P0-R82)

GPIOx Output Enable

P0-R8

GPIOx Output Inversion

P0-R87

GPIOx Output Selection

P0-R82

Off (low)

DSP GPIOx output

Register GPIOx output (P0-R86)

Auto mute flag (Both A and B)

Auto mute flag (Channel B)

Auto mute flag (Channel A)

Clock invalid flag

Mux

GPIOx

Mux

Serial Audio Data Output

Analog mute flag for B

Analog mute flag for A

PLL lock flag

Charge Pump Clock

Under voltage flag 1

Under voltage flag 2

PLL output/4

GPIOx Input State

Monitoring

(P0-R119)

To µCDSP

To Clock Tree

Figure 30. SDOUT GPIO Port

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8.3.7 I²C Communication Port

The TAS3251 device supports the I²C serial bus and the data transmission protocol for standard and fast mode

as a slave device. Because the TAS3251 register map spans several books and pages, the user must select the

correct book and page before writing individual register bits or bytes. Changing from book to book is

accomplished by first changing to page 0x00 by writing 0x00 to register 0x00 and then writing the book number

to register 0x7f of page 0. Changing from page to page is accomplished via register 0x00 on each page. The

register value selects the register page, from 0 to 255.

8.3.7.1 Slave Address

Table 15. I²C Slave Address

MSB

1

LSB

0

1

0

1

ADR

R/ W

The TAS3251 device has 7 bits for the slave address. The last bit of the address byte is the device select bit

which can be selected by setting the ADR pin either high or low. A maximum of two devices can be connected

on the same bus at one time, which gives two options: 0x94 and 0x96. See table Table 16 for more details. Each

TAS3251 device responds when it receives the slave address.

Table 16. I²C Address Configuration using ADR Pin

ADR Pin / Bit

I²C SLAVE ADDRESS + [R/W]

0

1

0x94

0x96

8.3.7.2 Register Address Auto-Increment Mode

Auto-increment mode allows multiple sequential register locations to be written to or read back in a single

operation, and is especially useful for block write and read operations. The TAS3251 device supports auto-

increment mode automatically. Auto-increment stops at page boundries.

8.3.7.3 Packet Protocol

A master device must control packet protocol, which consists of start condition, slave address, read/write bit,

data if write or acknowledge if read, and stop condition. The TAS3251 device supports only slave receivers and

slave transmitters.

SDA

SCL

9

1–7

8

9

1–8

9

1–8

9

Sp

St

Slave address

R/W

ACK

DATA

ACK

DATA

ACK

Start

condition

Stop

condition

R/W: Read operation if 1; otherwise, write operation

ACK: Acknowledgement of a byte if 0

DATA: 8 bits (byte)

Figure 31. Packet Protocol

Table 17. Write Operation - Basic I²C Framework

Transmitter

Data Type

M

S

M

S

M

S

M

St

slave address

R/

ACK

DATA

ACK

DATA

ACK

Sp

Table 18. Read Operation - Basic I²C Framework

Transmitter

Data Type

M

S

M

S

M

St

slave address

R/

ACK

DATA

ACK

DATA

ACK

NACK

Sp

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M = Master Device; S = Slave Device; St = Start Condition Sp = Stop Condition

8.3.7.4 Write Register

A master can write to any TAS3251 device registers using single or multiple accesses. The master sends a

TAS3251 device slave address with a write bit, a register address with auto-increment bit, and the data. If auto-

increment is enabled, the address is that of the starting register, followed by the data to be transferred. When the

data is received properly, the index register is incremented by 1 automatically. When the index register reaches

0x7F, the next value is 0x0. Table 19 shows the write operation.

Table 19. Write Operation

Transmitter

Data Type

M

S

M

S

M

S

M

S

M

reg

addr

write

data 1

write

data 2

St

slave addr

W

ACK

inc

ACK

Sp

M = Master Device; S = Slave Device; St = Start Condition Sp = Stop Condition; W = Write; ACK = Acknowledge

8.3.7.5 Read Register

A master can read the TAS3251 device register. The value of the register address is stored in an indirect index

register in advance. The master sends a TAS3251 device slave address with a read bit after storing the register

address. Then the TAS3251 device transfers the data which the index register points to. When auto-increment is

enabled, the index register is incremented by 1 automatically. When the index register reaches 0x7F, the next

value is 0x0. Table 20 lists the read operation.

Table 20. Read Operation

Transmitter

Data Type

M

S

M

S

M

S

M

slave

addr

reg

addr

slave

addr

St

W

ACK

inc

ACK

Sr

R

ACK

data

ACK

NACK

Sp

M = Master Device; S = Slave Device; St = Start Condition; Sr = Repeated start condition; Sp = Stop Condition;

W = Write; R = Read; NACK = Not acknowledge

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8.3.7.6 DSP Book, Page, and Register Update

The DSP memory is arranged in books, pages, and registers. Each book has several pages and each page has

several registers.

8.3.7.6.1 Book and Page Change

To change the book, the user must be on page 0x00. In register 0x7f on page 0x00 you can change the book.

On page 0x00 of each book, register 0x7f is used to change the book. Register 0x00 of each page is used to

change the page. To change a book first write 0x00 to register 0x00 to switch to page 0 then write the book

number to register 0x7f on page 0. To change between pages in a book, simply write the page number to

register 0x00.

8.3.7.6.2 Swap Flag

The swap flag is used to copy the audio coefficient from the host memory to the DSP memory. The swap flag

feature is important to maintain the stability of the BQs. A BQ is a closed-loop system with 5 coefficients. To

avoid instability in the BQ in an update transition between two different filters, update all five parameters within

one audio sample. The interal swap flag insures all 5 coefficients for each filter are transferred from host memory

to DSP memory occurs within an audio sample. The swap flag stays high until the full host buffer is transferred to

DSP memory. Updates to the Host buffer should not be made while the swap flag is high.

All writes to book 0x8C at pages above page 0x1B and register 0x58 require the swap flag. The swap flag is

located in book 0x8C, page 0x05page 0x01, and register 0x7C and must be set to 0x00 00 00 01 for a swap.

8.3.7.6.3 Example Use

The following is a sample script for using the DSP host memory to change the fine volume on the device on I²C

slave address 0x90 to the default value of 0 dB:

w 90 00 00 #Go to page 0

w 90 7f 8C #Change the book to 0x8C

w 90 00 21 #Go to page 0x21

w 90 34 40 00 00 00 #Fine volume Left

w 90 38 40 00 00 00 #Fine volume Rights

#Run the swap flag for the DSP to work on the new coefficients

w 90 00 00 #Go to page 0

w 90 7f 8C #Change the book to 0x8C

w 90 00 05 #Go to page 0x05

w 90 7C 00 00 00 01 #Swap flag

8.3.8 Pop and Click Free Startup and Shutdown

The output power stage PWM generator minimizes pop and click with a unique turn on and turn off behavior. The

sequence ramps up the PWM switching to the full PVDD voltage using the timing capacitor on the C_START pin.

It is recommended to use a 10 nF capacitor from the C_START pin to GND for best pop and click performance.

The startup time can be lengthened by increasing the capacitance up to 470 nF.

8.3.9 Integrated Oscillator for Output Power Stage

The amplifier power stage of the uses a built in oscillator that can be trimmed by an external resistor from the

FREQ_ADJ pin to GND. Changes in the oscillator frequency should be made with resistor values specified in

Recommended Operating Conditions while RESET is low. See section DAC and DSP Clocking for configuring

the clocks for the digital front-end (DAC and DSP).

To reduce interference problems while using a radio receiver tuned within the AM band, the switching frequency

can be changed from nominal to lower or higher values. These values should be chosen such that the nominal

and the alternate switching frequencies together result in the fewest cases of interference throughout the AM

band. The oscillator frequency can be selected by the value of the FREQ_ADJ resistor connected to GND in

master mode.

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8.3.9.1 Oscillator Synchronization and Slave Mode

The TAS3251 supports synchronizing the internal oscillator and output switching frequency of multiple TAS3251

devices for managing the power supply, electro-magnetic interference and preventing audio beating. For slave

mode operation, turn off the oscillator of the slave by pulling the FREQ_ADJ pin to DVDD. This configures the

OSC_IOM and OSC_IOP pins as inputs to be slaved from an external differential clock. In a master/slave system

inter-channel delay is automatically added to the PWM between audio channels, which can be seen with all

channels switching at different times. This will not influence the audio output, but only the switch timing to

minimize noise coupling between audio channels through the power supply. Inter-channel delay is needed to

optimize audio performance and to get better operating conditions for the power supply. The inter-channel delay

will be set up for a slave device depending on the polarity of the OSC_IOM and OSC_IOP connection as follows:

•

Slave 1 Mode has positive polarity with the master device. Master OSC_IOP and the slave OSC_IOP are

connected. Master OSC_IOM and the slave OSC_IOM are connected.

•

Slave 2 Mode has reverse polarity with the master device. Master OSC_IOP and the slave OSC_IOM are

connected. Master OSC_IOM and the slave OSC_IOP are connected.

Multiple slaves can be connected to one master TAS3251. If more than 2 slaves are used it is best to alternate

the slave modes so that adjacent devices are configured in different slave modes. The inter-channel delay for

interleaved channel idle switching is given in the table below for the master/slave and output configuration modes

in degrees relative to the PWM frame.

Table 21. Master/Slave Inter Channel Delay Settings

Master

MODE = 0, 2 x BTL mode

MODE = 1, 1 x PBTL mode

SPK_OUTA+

SPK_OUTA-

SPK_OUTB+

SPK_OUTB-

Slave 1

0°

180°

0°

180°

60°

240°

180°

SPK_OUTA+

SPK_OUTA-

SPK_OUTB+

SPK_OUTB-

Slave 2

60°

240°

60°

240°

120°

300°

240°

SPK_OUTA+

SPK_OUTA-

SPK_OUTB+

SPK_OUTB-

30°

210°

90°

30°

210°

30°

270°

210°

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8.3.10 Device Output Stage Protection System

The TAS3251 contains advanced protection circuitry carefully designed to facilitate system integration and ease

of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as

short circuits, overload, overtemperature, and undervoltage. The TAS3251 responds to a fault by immediately

setting the power stage in a high-impedance (Hi-Z) state and asserting the FAULT pin low. In situations other

than overload and overtemperature error (OTE), the device automatically recovers when the fault condition has

been removed, that is, the supply voltage has increased.

The device will handle errors, as shown in Table 22.

Table 22. Device Protection

BTL MODE

LOCAL ERROR IN

PBTL MODE

LOCAL ERROR IN

TURNS OFF

SPK_OUTA+

SPK_OUTA-

SPK_OUTB+

SPK_OUTB-

SPK_OUTA+

SPK_OUTA-

SPK_OUTB+

SPK_OUTB-

A+ and A-

A+, A-, B+, and B-

B+ and B-

Bootstrap UVP does not shutdown according to the table, it shuts down the respective halfbridge (non-latching,

does not assert FAULT).

8.3.10.1 Error Reporting

The FAULT, and CLIP_OTW, pins are active-low, open-drain outputs. Each pin has a 26 kΩ pull-up resistor

reference to DVDD and does not need an external pull-up resistor. The function is for protection-mode signaling

to a system-control device.

Any fault resulting in device shutdown is signaled by the FAULT pin going low. Also, CLIP_OTW goes low when

the device junction temperature exceeds 125°C (see Table 23).

Table 23. Error Reporting

FAULT

CLIP_OTW

DESCRIPTION

Overtemperature (OTE), overload (OLP) or undervoltage (UVP) Junction temperature

higher than 125°C (overtemperature warning)

0

1

0

1

Overload (OLP) or undervoltage (UVP). Junction temperature lower than 125°C

Junction temperature higher than 125°C (overtemperature warning)

Junction temperature lower than 125°C and no OLP or UVP faults (normal operation)

Note that asserting RESET low forces the FAULT signal high, independent of faults being present. TI

recommends monitoring the CLIP_OTW signal using the system microcontroller and responding to an

overtemperature warning signal by turning down the volume to prevent further heating of the device resulting in

device shutdown (OTE).

To reduce external component count, an internal pullup resistor to 3.3 V is provided on both FAULT and

CLIP_OTW outputs.

8.3.10.2 Overload and Short Circuit Current Protection

TAS3251 has fast reacting current sensors with a programmable trip threshold (OC threshold) on all high-side

and low-side FETs. To prevent output current from increasing beyond the programmed threshold, TAS3251 has

the option of either limiting the output current for each switching cycle (Cycle By Cycle Current Control, CB3C) or

to perform an immediate shutdown of the output in case of excess output current (Latching Shutdown). CB3C

prevents premature shutdown due to high output current transients caused by high level music transients and a

drop of real speaker’s load impedance, and allows the output current to be limited to a maximum programmed

level. If the maximum output current persists, i.e. the power stage being overloaded with too low load impedance,

the device will shut down the affected output channel and the affected output is put in a high-impedance (Hi- Z)

state until a RESET cycle is initiated. CB3C works individually for each half bridge output. If an over current

event is triggered, CB3C performs a state flip of the half bridge output that is cleared upon beginning of next

PWM frame.

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PWM_X

RISING EDGE PWM

SETS CB3C LATCH

HS PWM

LS PWM

OC EVENT RESETS

CB3C LATCH

OC THRESHOLD

OUTPUT CURRENT

OCH

HS GATE-DRIVE

LS GATE-DRIVE

Figure 32. CB3C Timing Example

During CB3C an over load counter increments for each over current event and decrease for each non-over

current PWM cycle. This allows full amplitude transients into a low speaker impedance without a shutdown

protection action. In the event of a short circuit condition, the over current protection limits the output current by

the CB3C operation and eventually shut down the affected output if the overload counter reaches its maximum

value. If a latched OC operation is required such that the device shuts down the affected output immediately

upon first detected over current event, this protection mode should be selected. The over current threshold and

mode (CB3C or Latched OC) is programmed by the OC_ADJ resistor value. The OC_ADJ resistor needs to be

within its intentional value range for either CB3C operation or Latched OC operation.

I_OC

IOC_max

IOC_min

Not Defined

ROC_ADJ

Figure 33. OC Threshold versus OC ADJ Resistor Value Example

OC_ADJ values outside specified value range for either CB3C or latched OC operation will result in minimum OC

threshold.

Table 24. Device Protection

OC_ADJ Resistor Value

Protection Mode

CB3C

OC Threshold

16.3 A

22 kΩ

24 kΩ

27 kΩ

30 kΩ

CB3C

15.1 A

CB3C

13.5 A

CB3C

12.3 A

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Table 24. Device Protection (continued)

OC_ADJ Resistor Value

Protection Mode

Latched OC

OC Threshold

16.3 A

47 kΩ

51 kΩ

56 kΩ

64 kΩ

15.1 A

13.5 A

12.3 A

8.3.10.3 Signal Clipping and Pulse Injector

A built in activity detector monitors the PWM activity of the SPK_OUTx pins. TAS3251 is designed to drive

unclipped output signals all the way to PVDD and GND rails. In case of audio signal clipping when applying

excessive input signal voltage, or in case of CB3C current protection being active, the amplifier feedback

loop of the audio channel will respond to this condition with a saturated state, and the output PWM signals

will stop unless special circuitry is implemented to handle this situation. To prevent the output PWM signals

from stopping in a clipping or CB3C situation, narrow pulses are injejcted to the gate drive to maintain output

activity. The injected narrow pulses are injected at every 4^thPWM frame, and thus the effective switching

frequency during this state is reduced to 1/4 of the normal switching frequency.

Signal clipping is signalled on the CLIP_OTW pin and is self clearing when signal level reduces and the

device reverts to normal operation. The CLIP_OTW pulses starts at the onset to output clipping, typically at a

THD level around 0.01%, resulting in narrow CLIP_OTW pulses starting with a pulse width of ~500ns.

Figure 34. Signal Clipping PWM and Speaker Output Signals

8.3.10.4 DC Speaker Protection

The output DC protection scheme protects a speaker from excess DC current in case one terminal of the

speaker is connected to the amplifier while the other is accidentally shorted to the chassis ground. Such a short

circuit results in a DC voltage of PVDD/2 across the speaker, which potentially can result in destructive current

levels. The output DC protection detects any unbalance of the output and input current of a BTL output, and in

the event of the unbalance exceeding a programmed threshold, the overload counter increments until its

maximum value and the affected output channel is shut down. DC Speaker Protection is disabled in PBTL and

SE mode operation.

8.3.10.5 Pin-to-Pin Short Circuit Protection (PPSC)

The PPSC detection system protects the device from permanent damage in the case that a power output pin

(SPK_OUTx) is shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an

overcurrent after the demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC

detection is performed at startup i.e. when VDD is supplied, consequently a short to either GND_X or PVDD_X

after system startup does not activate the PPSC detection system. When PPSC detection is activated by a short

on the output, all half bridges are kept in a Hi-Z state until the short is removed; the device then continues the

startup sequence and starts switching. The detection is controlled globally by a two step sequence. The first step

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ensures that there are no shorts from SPK_OUTx to GND_X, the second step tests that there are no shorts from

SPK_OUTx to PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output

LC filter. The typical duration is < 15 ms/μF. While the PPSC detection is in progress, FAULT is kept low, and the

device will not react to changes applied to the RESET pin. If no shorts are present the PPSC detection passes,

and FAULT is released. A device reset will not start a new PPSC detection. PPSC detection is enabled in BTL

and PBTL output configurations, the detection is not performed in SE mode. To make sure not to trip the PPSC

detection system it is recommended not to insert a resistive load to GND_X or PVDD_X.

8.3.10.6 Overtemperature Protection OTW and OTE

TAS3251 has a two-level temperature-protection system that asserts an active-low warning signal (CLIP_OTW)

when the device junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds

155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-

impedance (Hi-Z) state and FAULT being asserted low. OTE is latched in this case. To clear the OTE latch,

RESET must be asserted. Thereafter, the device resumes normal operation.

8.3.10.7 Undervoltage Protection (UVP) and Power-on Reset (POR)

The UVP and POR circuits of the TAS3251 fully protect the device in any power-up/down and brownout situation.

While powering up, the POR circuit ensures that all circuits are fully operational when the GVDD_X and VDD

supply voltages reach values stated in the Electrical Characteristics table. Although GVDD_X and VDD are

independently monitored, a supply voltage drop below the UVP threshold on any VDD or GVDD_X pin results in

all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and FAULT being asserted low.

The device automatically resumes operation when all supply voltages have increased above the UVP threshold.

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8.3.10.8 Fault Handling

If a fault situation occurs while in operation, the device acts accordingly to the fault being a global or a channel

fault. A global fault is a chip-wide fault situation and causes all PWM activity of the device to be shut down, and

will assert FAULT low. A global fault is a latching fault and clearing FAULT and restarting operation requires

resetting the device by toggling RESET. Deasserting RESET should never be allowed with excessive system

temperature, so it is advised to monitor RESET by a system microcontroller and only allow releasing RESET

(RESET high) if the CLIP_OTW signal is cleared (high). A channel fault results in shutdown of the PWM activity

of the affected channel(s). Note that asserting RESET low forces the FAULT signal high, independent of faults

being present.

Table 25. Error Reporting

Fault/Event

Description

Latched/Self

Clearing

Action needed to

Clear

Output

FETs

Fault/Event

Global or Channel

Reporting Method

PVDD_X UVP

VDD UVP

Increase affected

supply voltage

Voltage Fault

Global

FAULT pin

Self Clearing

HI-Z

AVDD UVP

POR (DVDD UVP)

Power On Reset

Voltage Fault

Self Clearing

Allow DVDD to rise

HI-Z

Allow BST cap to

recharge (lowside

ON, VDD 12V)

BST_X UVP

OTW

Channel (Half Bridge) None

HighSide off

Cool below OTW

threshold

Normal

operation

Thermal Warning

Global

OTW pin

Self Clearing

OTE

Thermal Shutdown

OC Shutdown

Global

FAULT pin

Latched

Toggle RESET

HI-Z

OLP (CB3C>1.7ms)

Channel

Latched OC

(47kΩ<ROC_ADJ<68kΩ)

OC Shutdown

OC Limiting

Channel

Global

FAULT pin

None

Latched

Toggle RESET

HI-Z

Flip state,

cycle by

cycle at fs/3

CB3C

Reduce signal level

or remove short

Self Clearing

(22kΩ<ROC_ADJ<30kΩ)

No OSC_IO activity

in Slave Mode

Resume OSC_IO

activity

Stuck at Fault⁽¹⁾

None

HI-Z

(1) Stuck at Fault occurs when input OSC_IO input signal frequency drops below minimum frequency given in the Electrical Characteristics

table of this data sheet.

8.3.10.9 Output Power Stage Reset

Asserting RESET low initiates the device ramp down. The output FETs go into a Hi-Z state after the ramp down

is complete. Output pull downs are active both in SE mode and BTL mode with RESET low.

In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables

weak pulldown of the half-bridge outputs.

Asserting reset input low removes any fault information to be signaled on the FAULT output, that is, FAULT is

forced high. A rising-edge transition on reset input allows the device to resume operation after a fault. To ensure

thermal reliability, the rising edge of reset must occur no sooner than 4 ms after the falling edge of FAULT.

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8.3.11 Initialization, Startup and Shutdown

This section provides common procedures for power up, operation and power down sequencing.

8.3.11.1 Power Up and Startup Sequence

The device analog front-end, including the DAC and DSP, are controlled independently of the output power

stage. Follow the sequence below to power up the digital front-end and power stage to begin playing audio.

1. Apply power to DAC_DVDD, DAC_AVDD, GVDD_x, and PVDD_x. The power supplies do not have a power

on sequence and can be powered on in any order.

2. Apply I2S or TDM clocks to the device to enable the internal system clocks.

3. Mute the left and right DAC channels, by setting Register 0x03, Bits 0 (right) and 4 (left) to '1'.

4. Set DSP coefficients and configuration settings through I²C (optional). The DSP will pass-through audio if no

registers are changed.

5. Bring the DSP out of standby by setting Register 0x02, Bit 7 (DSPR) to '1'.

6. Unmute the left and right DAC channels, by setting Register 0x03, Bits 0 (right) and 4 (left) to '0'.

7. Enable the amplifier output stage by setting the RESET_AMP pin high.

8. Play audio through I2S or TDM.

8.3.11.2 Power Down and Shutdown Sequence

Follow the sequence below to initiate standby and power down the digital front-end and power stage.

1. Stop audio playback.

2. Disable the amplifier output stage by setting the RESET_AMP pin low.

3. Mute the left and right DAC channels by setting Register 0x03, Bits 0 (right) and 4 (left) to '1'.

4. Optional: Put the DAC into a low-power mode register 0x02.

5. Optional: Remove voltage from all power supply rails.

8.3.11.3 Device Mute

1. Optional: Disable the amplifier output stage by setting the RESET_AMP pin low.

2. Mute the left and right DAC channels by setting Register 0x03, Bits 0 (right) and 4 (left) to '1'.

8.3.11.4 Device Unmute

1. Unmute the left and right DAC channels, by setting Register 0x03, Bits 0 (right) and 4 (left) to '0'.

2. Optional: If the amplifier output stage is powered down, enable the amplifier output stage by setting the

RESET_AMP pin high.

8.3.11.5 Device Reset

8.3.11.6 Mute with DAC_MUTE or Clock Error

Under certain conditions, the TAS3251 can exhibit some pop on power down if the device does not have enough

time to detect power loss and initiate the muting process. The TAS3251has two auto-mute functions to mute the

device upon power loss (intentional or unintentional).

•

DAC_MUTE - when the DAC_MUTE pin is pulled low, the incoming serial port data is attenuated to 0, closely

followed by a hard analog mute. This process takes 150 samples + 0.2 ms.

•

Clock Error Detect - when a clock error is detected on the incoming serial port data, the TAS3251 switches

to an internal oscillator and continues to drive the DAC outputs while attenuating the data from the last known

good value. Once this process completes, the TAS3251 DAC outputs are hard muted to ground.

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8.3.11.6.1 Mute using DAC_MUTE

Deassert DAC_MUTE low 150 samples + 0.2 ms before power is removed.

3.3V

VDD

0V

150t_S+ 0.2ms

High

XSMT

Low

High

2

I S Clocks

SCK, BCK, LRCK

Low

Time

Figure 35. DAC_MUTE Timing Diagram

8.3.11.7 Mute using Serial Audio Port Clock

Stop I²S clocks (SCLK, MCLK, LRCK) 3 ms before power-down as shown in the figure below.

3.3V

VDD

0V

High

XSMT

Low

3 ms

High

I2S Clocks

SCK, BCK, LRCK

Low

Time

Figure 36. Serial Port Muting Timing Diagram

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8.3.11.8 Muting before an Unplanned Shutdown with DAC_MUTE

Many systems use a low-noise regulator to provide 3.3 V to the DAC_AVDD and DAC_DVDD. The DAC_MUTE

pin can take advantage of such a feature to measure the pre-regulated output (3.3 V) from the system power

supply to mute the output before the PVDD power supply discharges. Figure 37 shows how to configure the

system to use the DAC_MUTE pin. The DAC_MUTE pin can also be used in parallel with a GPIO pin from the

system microcontroller, DSP or power supply.

“mute” signal

MCU GPIO

GND

XSMT

110V / 220V

Linear

Regulator

PCM5xxx

Audio DAC

6V

3.3V

SMPS

10

F

GND

Figure 37. Application Diagram for DAC_MUTE

8.3.11.9 Output Power Stage Startup Timing

The TAS3251 output power stage does not require a specific power-up sequence, but it is recommended to hold

RESET low for a minimum of 400 ms after PVDD supply voltage is powered on. The outputs of the half-bridges

remain in a high-impedance state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the

undervoltage protection (UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). This

allows an internal circuit to charge the external bootstrap capacitors by enabling a weak pull-down of the half-

bridge output as well as initiating a controlled ramp up sequence of the output voltage.

PVDD

VDD

GVDD

DVDD

/RESET

AVDD

C 70µs

t

Precharge

C 200ms

/FAULT

VIN_X

OUT_X

VOUT_X

t

Startup ramp

V_CSTART

Figure 38. Power Stage Startup Timing

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When RESET is released to turn on TAS3251, FAULT signal will output low and AVDD voltage regulator will be

enabled. FAULT will stay low until AVDD reaches the undervoltage protection (UVP) voltage threshold (see the

Electrical Characteristics table of this data sheet). Next a pre-charge time begins to stabilize the DC voltage

across the input AC coupling capacitors, followed by the ramp up output power stage sequence .

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8.4 Device Functional Modes

Because the TAS3251 device is a highly configurable device, numerous modes of operation can exist for the

device. For the sake of succinct documentation, these modes are divided into two modes:

•

Fundamental operating modes

Secondary usage modes

Fundamental operating modes are the primary modes of operation that affect the major operational

characteristics of the device, which are the most basic configurations that are chosen to ensure compatibility with

the intended application or the other components that interact with the device in the final system. Some

examples of the operating modes are the communication protocol used by the control port, the output

configuration of the amplifier, or the Master/Slave clocking configuration.

The fundamental operating modes are described starting in the Serial Audio Port Operating Modes section.

Secondary usage modes are best described as modes of operation that are used after the fundamental operating

modes are chosen to fine tune how the device operates within a given system. These secondary usage modes

can include selecting between left justified and right justified Serial Audio Port data formats, or enabling some

slight gain/attenuation within the DAC path. Secondary usage modes are accomplished through manipulation of

the registers and controls in the I²C control port. Those modes of operation are described in their respective

register/bit descriptions and, to avoid redundancy, are not included in this section.

8.4.1 Serial Audio Port Operating Modes

The serial audio port in the TAS3251 device supports industry-standard audio data formats, including I²S, Time

Division Multiplexing (TDM), Left-Justified (LJ), and Right-Justified (RJ) formats. To select the data format that

will be used with the device, controls are provided on P0-R40. The timing diagrams for the serial audio port are

shown in the Serial Audio Port Timing – Slave Mode section, and the data formats are shown in the Serial Audio

Port – Data Formats and Bit Depths section.

8.4.1.1 Master and Slave Mode Clocking for Digital Serial Audio Port

The digital audio serial port in the TAS3251 device can be configured to receive clocks from another device as a

serial audio slave device. The slave mode of operation is described in the Clock Slave Mode with SCLK PLL to

Generate Internal Clocks (3-Wire PCM) section. If no system processor is available to provide the audio clocks,

the TAS3251 device can be placed into Master Mode. In master mode, the TAS3251 device provides the clocks

to the other audio devices in the system. For more details regarding the Master and Slave mode operation within

the TAS3251 device, see the Serial Audio Port Operating Modes section.

8.4.2 Communication Port Operating Modes

The TAS3251 device is configured via an I²C communication port. The device does not support a hardware only

mode of operation, nor Serial Peripheral Interface (SPI) communication. The I²C Communication Protocol is

detailed in the I²C Communication Port section. The I²C timing requirements are described in the I²C Bus Timing

–Standard and I²C Bus Timing –Fast sections.

8.4.3 Speaker Amplifier Operating Modes

The TAS3251 device can be used in two different amplifier configurations:

•

Stereo Mode

Mono Mode

8.4.3.1 Stereo Mode

The familiar stereo mode of operation uses the TAS3251 device to amplify two independent signals, which

represent the left and right portions of a stereo signal. These amplified left and right audio signals are presented

on differential output pairs shown as SPK_OUTA± and SPK_OUTB±. The routing of the audio data which is

presented on the SPK_OUTx outputs can be changed according to the Audio Process Flow which is used and

the configuration of registers P0-R42-D[5:4] and P0-R42-D[1:0]. The familiar stereo mode of operation is shown

in .

By default, the TAS3251 device is configured to output the Right frame of a I²S input on the Channel A output

and the left frame on the Channel B output.

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Device Functional Modes (continued)

8.4.3.2 Mono Mode

The mono mode of operation is used to describe operation in which the two outputs of the device are placed in

parallel with one another to increase the power sourcing capabilities of the audio output channel. This is also

known as Parallel Bridge Tied Load (PBTL).

On the output side of the TAS3251 device, the summation of the devices can be done before the filter in a

configuration called Pre-Filter PBTL. However, the two outputs may be required to merge together after the

inductor portion of the output filter. Doing so does require two additional inductors, but allows smaller, less

expensive inductors to be used because the current is divided between the two inductors. This process is called

Post-Filter PBTL. Both variants of mono operation are shown in Figure 39 and Figure 40.

SPK_OUTA+

SPK_OUTA-

Class-D

Amplifier

Class-D

Amplifier

SPK_OUTB+

SPK_OUTB-

Figure 39. Pre-Filter PBTL

Figure 40. Post-Filter PBTL

On the input side of the TAS3251 device, the input signal to the mono amplifier can be selected from the any slot

in a TDM stream or the left or right frame from an I²S, LJ, or RJ signal. The TAS3251 device can also be

configured to amplify some mixture of two signals, as in the case of a subwoofer channel which mixes the left

and right channel together and sends the mixture through a low-pass filter to create a mono, low-frequency

signal.

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8.5 Programming

8.5.1 Audio Processing Features

The TAS3251 device includes audio processing to optimize the audio performance of the audio system into

which they are integrated. The TAS3251 device has 12 Biquad Filters for speaker response tuning, One dual

band DPEQ to dynamically adjust the equalization curve that is applied to low-level signal and the curve that is

applied to high level signals. A 2-band advanced DRC + AGL structure limits the output power of the amplifier for

two regions while controlling the peaking that can occur in the crossover region during compression. A fine

volume control is provided to finely adjust the output level of the amplifier based upon the system level

considerations faced by the product development engineer.

The TAS3251 device has two signal monitoring options available, the level meter and the serial data out signal.

The level meter monitors the signal level through an alpha filter and presents the signal in an I²C register. The

level meter signal is taken before the 4x interpolation which occurs before the digital-to-analog conversion.

The details of the audio processing flow, including the I²C control port registers associated with each block, are

shown in .

Audio Path

32 Bit Data Path & Coefficients

High level

BQ

Band-Split

High (1BQ)

Main

EQ

Input Scale

& Mix

SRC

Adv.

DRC

Gain

Audio Input

from Serial

Port

1.31

32/48k

to

96kHz

DAC w/

1.31

Gain

Scale

DPEQ

Control

Fine

Volume

4x

Int.

Analog Out

to Amp

5.27

Sense

BQ

Up to 15

BQS

AGL

L&R or

L+R

2

+

Gain Cntrl

Log.

Style

Band-Split

Low (1BQ)

Gain

Low

level BQ

Level

Meter

Mux

Bypass

I²C Register

Audio Out to

Serial Port

Figure 41. Fixed-Function Process Flow found in the TAS3251

8.5.2 Processing Block Description

The processing block shown in the above is comprised of the following major blocks:

•

Input scale and mixer

Sample Rate Converter (SRC)

Parametric Equalizers (PEQs)

BQs Gain Scale

Dynamic Parametric Equalizer (DPEQ)

Two-Band Dynamic Ranger Control (DRC)

Automatic Gain Limiter (AGL)

Fine Volume

Level Meter

8.5.2.1 Input Scale and Mixer

The input mixer can be used to mix the left and right channel input signals as shown in Figure 42. The input

mixer has four coefficients, which control the mixing and gains of the input signals. When mixing and scaling the

input signals, ensure that at maximum input level the input mixer outputs don't exceed 0 dBFs, which will

overdrive the SRC inputs.

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Programming (continued)

L2L

Gain

Audio left in

Audio left out

+

L2R

Gain

R2L

Gain

R2R

Gain

Audio right in

Audio right out

+

Figure 42. Input Scale and Mixer

8.5.2.1.1 Example

The following is a sample script for setting up the both left and right channels for (½L + ½R) or (L + R) / 2:

w 90 00 00 # Go to page 0

w 90 7f 8C #Change the book to 0x8C

w 90 00 21 #Go to page 0x21

w 90 3C 00 40 26 E7 #Input mixer left in to left out gain

w 90 40 00 40 26 E7 #Input mixer right in to left out gain

w 90 44 00 40 26 E7 #Input mixer left in to right out gain

w 90 48 00 40 26 E7 #Input mixer right in to right out gain

#Run the swap flag for the DSP to work on the new coefficients

w 90 00 00 #Go to page 0

w 90 7f 8C #Change the book to 0x8C

w 90 00 05 #Go to page 0x05

w 90 7C 00 00 00 01 #Swap flag

8.5.2.2 Sample Rate Converter

The sample rate converter supports 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz and 96 kHz input sample rates. These

input sample rates are converted to 88.2 or 96 kHz sample rate. The sample rate detection doesn’t distinguish

between sample rates from 32 to 48 kHz. These sample rates are treated as 48 kHz by the sample rate

converter. The detected sample rate can be read at book 0x78 page 0x0C register 0x5C. The input sample rate

is 88.2 or 96 kHz at register 0x5C which reads 0x00 00 00 01. The input sample rate is 32 to 48 kHz at register

0x5C which reads 0x00 00 00 02. Input sample rate 32 kHz requires changing the interpolation setting from 2x to

3x by writing B0-P0-R37-D7 to 1. The device must be placed in standby mode for this change to take effect.

Table 26. Sample Rate Detection

SAMPLING RATE (KHZ)

B0-P0-R91-D[6:4]

8

16

001

010

011

100

101

110

32 – 48

88.2 – 96

176.4 – 192

384

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Even though the sample rate converter supports 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz and 96 kHz input sample

rates, the TAS3251 device supports all input sample rates shown in Table 26 in 1x interpolation mode, base rate

processing.

The SRC input should not be overdriven. Making the maximum signal level into the SRC –0.5dBFs is

recommended to prevent overdriving the SRC and causing audio artifacts. The input scale and mixer can be

used to attenuate or boost the maximum input signal to –0.5dBFs. The processing block has several blocks after

the SRC where the signal can be compensate for any gain attenuation done in the input mixer and scale block to

prevent over driving the SRC.

8.5.2.3 Parametric Equalizers (PEQ)

The device supports up to 15 individual tuned PEQs for left channel and up to 15 individual tuned PEQs for the

right channel. The PEQs are implemented using cascaded “direct form 1” BQs structures as shown in Figure 43.

Inst1_B0

Inst2_B0

Inst3_B0

BIQUADIN_D

X

+

2*Inst1_B1

X

2*Inst1_A1

2*Inst2_B1

X

2*Inst2_A1

2*Inst3_B1

z^-1

X

z^-1

Inst1_B2

X

Inst1_A2

Inst2_B2

X

Inst2_A2

Inst3_B2

X

Instance 1

Instance 2

Figure 43. Cascaded BQ Structure

Instance 3

b₀+ b Z^-1+ b₂Z^-2

a₀+ a₁Z^-1+ a₂Z^-2

1

H(z) =

(2)

All BQ coefficients are normalized with a0 to insure that a0 is equal to 1. The structure requires 5 BQ coefficients

as shown in Table 27. Any BQ with coefficients greater than 1 undergoes gain scaling as described in BQ Gain

Scale.

Table 27. BQ Coefficients Normalization

BQ COEFFICIENT FOR TAS3251

COEFFICIENT CALCULATION

B0_DSP

B1_DSP

B2_DSP

A1_DSP

A2_DSP

b0 / a0

b1 / (a0 × 2)

b2 / a0

–a1 / (a0 × 2)

–a2 / a0

8.5.2.4 BQ Gain Scale

Main EQ

12-15 BQs

Gain

Scale

Figure 44. PEQs and BQs Gain Scale Block

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The BQ coefficients format is as follows: The first BQ has B0 = 5.x, B1 = 6.x, B2 = 5.x, A1 = 2.x, and A2 = 1.x.

The rest of the BQ have this format: B0 = 1.x, B1 = 2.x, B2 = 1.x, A1 = 2.x, and A2 = 1.x. This formatting

maintains the highest possible resolution and noise performance. The 1.31 format restricts the ability to do high

gains within the BQs and as a result requires gain compensation for the restriction. When generating BQ

coefficients, ensure none of the BQ coefficients is greater than 1 by implementing gain compensation. The Gain

compensation reduces the BQ coefficients gain to ensure all BQ coefficients are less than 1. The reduced gain is

then reapplied in the subsequent gain scale block.

Gain compensation takes the maximum value of B0_DSP, B1_DSP, and B2_DSP after the BQ normalization

shown in Table 27 is implemented. All the B coefficients are divided by maximum B coefficient value then

multiplied by 0.999999999534339 (the nearest two’s complement 32-bit number to 1). The following calculations

are done for each BQ in the PEQ block:

Max _ k = max(B0 _ DSP, B1_ DSP, B2 _ DSP)

k _ BQX = Max _ k

(3)

(4)

B0 _ DSP

B0 _ DSP =

k _ BQX

(5)

(6)

(7)

B1_ DSP

B1_ DSP =

k _ BQX

B2 _ DSP

B2 _ DSP =

k _ BQX

The calculations above insure all DSP BQ coefficients are in a 1.31 format. The reduced gains in the BQ 1.31

format is compensation for in the gain scale block. The following calculation is done for each channel.

k_BQ = k_BQ1 × k_BQ2 × k_BQ3 × k_BQ4 × k_BQ5 × k_BQ6 × k_BQ7 × k_BQ8 × k_BQ9 × k_BQ10 × k_BQ11 ×

k_BQ12

(8)

The calculated k_BQ compensation value is then applied to the BQ gain scale in an 8.24 format. The BQ gain

scale can also be used for volume control before the DRCs. The block can be considered as BQ gain scale and

volume gain block. When the BQ gain scale block is used for volume control the coefficient value must be

calculated as follows:

Volume

20

Gain _ BQ _V =10

´k _ BQ

where

•

Volume is in dB

(9)

The BQ gain scale coefficients are located in book 0x8C, page 0x21 register 0x4C for left and register 0x50 for

right.

The Bypass EQ Mux allows the user to bypass all processing. The Bypass EQ mux is at Page 0x21, Register

0x64. The Gang Left / Right mux forces the left processing to be the same as the right processing. The Gang

Left / Right Mux is located at Page 0x21, Register 0x68.

8.5.2.5 Dynamic Parametric Equalizer (DPEQ)

The dynamic parametric equalizer mixes the audio signals routed through two paths containing one BQ each

based upon the signal level detected by the sense path, as shown in Figure 45. The sense path contains one

BQ, which can be used to focus the DPEQ sensing on a specific frequency bandwidth. An alpha filter structure is

used to sense the energy in the sense path and setting the dynamic mixing ratios.

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High level

BQ

DPEQ

Control

Sense

BQ

+

Low level

BQ

Figure 45. DPEQ Signal Path

The dynamic mixing is controlled by offset, gain, and alpha coefficients in a 1.31 format. The alpha coefficient

controls the average time constant in ms of the signal data in the sense path. The offset and gain coefficients

control the dynamic mixing thresholds shown in Figure 46.

GAIN

Low Path Mix

1

High Path Mix

0

T1

T2

FS

SENSE LEVEL

Figure 46. Dynamic Mixing

The offset, gain and alpha coefficients are calculated as follows:

T1

T1_ Linear =10²⁰

(10)

(11)

T 2-6

20

T2 _ Linear =10

where

•

T2 ≥ –20 dB

T 2

T2 _ Linear =10²⁰

where

•

T2 < –20 dB

(12)

(13)

Offset = -T1_ Linear

1

Gain =

32(T2 _ Linear -T1_ Linear)

-1000

(14)

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where

•

T1 and T2 are in dB

The time constant is in ms

(15)

The DPEQ control coefficients are located in book 0x8C, page0x20. Register 0x44 is alpha coefficient, register

0x48 is gain coefficient and register 0x4C is offset coefficient.

The high level path BQ, low level path BQ, and sense path BQ coefficients use a 1.31 format as shown in

Table 29. The DPEQ BQs don't have a gain scale to compensate for any BQ gain reduction due to the

requirements of the 1.31 format. During tuning, the reduced gain can be compensated by using the BQ gain

scale or the DRC offset coefficient.

The DPEQ sense gain scale is located in the sensing path. The DPEQ sense gain scale can be used to shift the

dynamic mixing thresholds by changing the signal level in the sensing path. A positive dB gain shifts the dynamic

mixing thresholds down by the gain amount and a negative dB gain shifts the dynamic mixing thresholds up by

the gain amount.

8.5.2.6 Two-Band Dynamic Range Control

The Dynamic Range Control (DRC) is a feed-forward mechanism that can be used to automatically control the

audio signal amplitude or the dynamic range within specified limits. The dynamic range control is done by

sensing the audio signal level using an estimate of the alpha filter energy then adjusting the gain based on the

region and slope parameters that are defined. The Dynamic Range Control is shown in Figure 47.

Adv.

DRC

Mixer

gain

Band-Split

High (1BQ)

+

Log.

Style

Band-Split

Low (1BQ)

Mixer

gain

Figure 47. Dynamic Range Control

The DRCs have seven programmable transfer function parameters each: k0, k1, k2, T1, T2, OFF1, and OFF2.

The T1 and T2 parameters specify thresholds or boundaries of the three compression or expansion regions in

terms of input level. The Parameters k0, k1, and k2 define the gains or slopes of curves for each of the three

regions. The parameters OFF1 and OFF2 specify the offset shift relative 1:1 transfer function curve at the

thresholds T1 and T2 respectively shown in Figure 48.

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0

OFF2

OFF1

-25

K2

K1

-50

K0

-75

-100

T1

T2

-125

-100

-75

-50

-25

0

Input (dB)

Figure 48. DRC Transfer Function Example Plot

The two-band dynamic range control is comprised of two DRCs that can be spilt into two bands using the BQ at

the input of each band. The frequency where the two bands are spilt is referred to as the crossover frequency.

The crossover frequency is the cut off frequency for the low pass filter used to create the low band and the cut

off frequency for the high pass filter used to create the high band. It is inherent of parallel two-band DRC to have

a hump at the crossover region due to the overlap of energy going through both bands of the DRC being

summed in the two-band DRC output mixer.

Attack

Decay

time

Gain

t1

t2

Time

Figure 49. DRC Attack and Decay

The DRC in each band is equipped with individual energy, attack, and decay time constants. The DRC time

constants control the transition time of changes and decisions in the DRC gain during compression or expansion.

The energy, attack, and decay time constants affect the sensitivity level of the DRC. The shorter the time

constant, the more aggressive the DRC response and vice versa.

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8.5.2.7 Automatic Gain Limiter

The Automatic Gain Limiter (AGL) is a feedback mechanism that can be used to automatically control the audio

signal amplitude or dynamic range within specified limits. The automatic gain limiting is done by sensing the

audio signal level using an alpha filter energy structure shown in Figure 51 at the output of the AGL then

adjusting the gain based on the whether the signal level is above or below the defined threshold. Three decisions

made by the AGL are engage, disengage, or do nothing. The rate at which the AGL engages or disengages

depends on the attack and release settings, respectively.

1:1 Transfer Function

Implemented Transfer Function

T

Input Level (dB)

M0091-04

Figure 50. AGL Transfer Function Example Plot

Alpha Filter Structure

S

α

–1

ω

Z

Figure 51. AGL Alpha Filter Structure

8.5.2.7.1 Softening Filter Alpha (AEA)

•

AEA = 1 – e^{–1000 / (fs × User_AE)}

e ≈ 2.718281828

Fs = sampling frequency

User_AE = user input step size

8.5.2.7.2 Softening Filter Omega (AEO)

•

AEO = 1 – AEA

8.5.2.7.3 Attack Rate

•

Attack rate = 2 (AA + Release rate)

AA = 1000 × User_Ad / Fs

User_Ad = user input attack step size

8.5.2.7.4 Release Rate

•

Release rate = 1000 × User_Rd / Fs

User_Rd = user input release step size

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NOTE

The release duration (User_Rd) should be longer than the attack duration (User_Ad).

8.5.2.7.5 Attack Threshold

•

Attack Threshold = user input level in dB

Threshold

INPUT

Threshold

OUTPUT

Attack Rate

Release Rate

W0003-01

Figure 52. AGL Attack and Release

The Attack Threshold AGL coefficients are shown in .

8.5.2.8 Fine Volume

The fine volume block after the AGL can be used to provide additional fine volume steps from –192 dB to 6 dB in

a 2.30 format. The Fine Coefficients are shown in .

8.5.2.9 THD Boost

A boost scaler and fine volume together can be used for clipping. The THD boost block allows the user to

programmatically increase the THD by clipping at an operating point earlier than that defined by the supply rails.

8.5.2.10 Level Meter

The level meter uses an energy estimator with a programmable time constant to adjust the sensitivity level based

on signal frequency and desired accuracy level. The level meter outputs of both left and right channels are

written to a 32-bit sub address location in a 1.31 format as shown in Table 28. The BypassTo Level Meter Bit in

Book 8C, Page 0x21, Register 0x70 can be used to switch the input to the Level Meter from the audio before

processing to audio post-processing.

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8.5.3 Other Processing Block Features

8.5.3.1 Number Format

The data processing path is 32 bits with 32-bit coefficients. The coefficients use the two’s complement digital

number format.

Table 28. Two’s Complement Format

BITS

TWO'S COMPLEMENT VALUE

0111 1111

0111 1110

0000 0010

0000 0001

0000 0000

1111 1111

1111 1110

1000 0010

1000 0001

1000 0000

127

126

2

1

0

–1

–2

–126

–127

–128

8.5.3.1.1 Coefficient Format Conversion

The device uses 32 bit two’s complement number formats. The calculated 4 byte register values are shown

below in an 8 digit hex value.

Table 29. Sample Calculations for 1.31 Format

dB

0

Linear

1

Decimal

Hex (1.31 Format)

7FFFFFFF

2147483648

1073741824

214748364

–6

–20

0.5

40000000

0.1

0CCCCCCC

D = 2³¹× L, D < 2³¹

x

L = 10^(x/20)

Dec2Hex(D, 8)⁽¹⁾

D = 2³¹, D ≥ 2³¹

(1) Dec2Hex(D, 8), where 8 represents 8 nibbles or 38 bits.

Please note that for a 1.31 format the linear value cannot be greater than 1 or decimal value 232.

Table 30. Sample Calculations for B.A Format

dB

Linear

Decimal

Hex (1.31 Format)

D = 2^A× L, D < 2^{(B + A - 1)}

x

L = 10^(x/20)

Dec2Hex(D, 8)

D = 2^{(B + A - 1)}, D ≥ 2^{(B + A - 1)}

8.5.4 Checksum

The TAS3251 device supports two different check sum schemes, a cyclic redundancy check (CRC) checksum

and an Exclusive (XOR) checksum. Both checksums work on every register write, except for book switch register

and page switching register, 0x7F and 0x00, respectively. Register reads do not change checksum, but writes to

even nonexistent registers will change the checksum. Both checksums are 8-bit checksums and both are

available together simultaneously. The checksums can be reset by writing a starting value (eg. 0x 00 00 00 00)

to their respective 4-byte register locations.

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8.5.4.1 Cyclic Redundancy Check (CRC) Checksum

The 8-bit CRC checksum used is the 0x7 polynomial (CRC-8-CCITT I.432.1; ATM HEC, ISDN HEC and cell

delineation, (1 + x¹+ x²+ x⁸). A major advantage of the CRC checksum is that it is input order sensitive.

The CRC supports all I²C transactions, excluding book and page switching. The CRC checksum is read from

register 0x7E on any page of book 0x00 (B0_Page x_Reg 126). If the book isn’t Book 0, the CRC checksum is

only valid on page 0x00 register 0x7E (Page 0_Reg 126). The CRC checksum can be reset by writing 0x00 00

00 00 to the same register locations where the CRC checksum is valid.

8.5.4.2 Exclusive or (XOR) Checksum

The Xor checksum is a simpler checksum scheme. It performs sequential XOR of each register byte write with

the previous 8-bit checksum register value. XOR supports only YMEM, which is located in Book 0x8C and

excludes page switching and all registers in Page 0x00 of Book 0x8C. XOR checksum is read from location

register 0x7D on page 0x00 of book 0x8C (B140_Page 0_Reg 125). The XOR Checksum can be reset by writing

0x00 00 00 00 to the same register location where it is read.

Table 31. XOR Truth Table

INPUT

OUTPUT

A

0

1

B

0

1

0

1

0

1

0

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8.6 Register Maps

8.6.1 Registers - Page 0

8.6.1.1 Register 1 (0x01)

Figure 53. Register 1 (0x01)

7

6

5

4

3

2

1

0

Reserved

R/W

RSTM

R/W

Reserved

R/W

RSTR

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 32. Register 1 (0x01) Field Descriptions

Bit

7-5

4

Field

Type

Reset

Description

Reserved

RSTM

Reserved

R/W

0

Reset Modules – This bit resets the interpolation filter and the DAC modules. Since the

DSP is also reset, the coeffient RAM content will also be cleared by the DSP. This bit

is auto cleared and can be set only in standby mode.

0: Normal

1: Reset modules

3-1

0

Reserved

RSTR

Reserved

R/W

0

Reset Registers – This bit resets the mode registers back to their initial values. The

RAM content is not cleared, but the execution source will be back to ROM. This bit is

auto cleared and must be set only when the DAC is in standby mode (resetting

registers when the DAC is running is prohibited and not supported).

0: Normal

1: Reset mode registers

8.6.1.2 Register 2 (0x02)

Figure 54. Register 2 (0x02)

7

6

5

4

3

2

1

0

DSPR

R/W

Reserved

R/W

RQST

R/W

Reserved

R/W

RQPD

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 33. Register 2 (0x02) Field Descriptions

Bit

Field

Type

Reset

Description

7

DSPR

R/W

1

DSP reset – When the bit is made 0, DSP will start powering up and send out data.

This needs to be made 0 only after all the input clocks are (ASI,MCLK,PLLCLK) are

settled so that DMA channels do not go out of sync.

0: Normal operation

1: Reset the DSP

6-5

4

Reserved

RQST

R/W

Reserved

0

Standby Request – When this bit is set, the DAC will be forced into a system standby

mode, which is also the mode the system enters in the case of clock errors. In this

mode, most subsystems will be powered down but the charge pump and digital power

supply.

0: Normal operation

1: Standby mode

3-1

Reserved

R/W

Reserved

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Table 33. Register 2 (0x02) Field Descriptions (continued)

Bit

Field

RQPD

Type

Reset

Description

0

R/W

0

Powerdown Request – When this bit is set, the DAC will be forced into powerdown

mode, in which the power consumption would be minimum as the charge pump is also

powered down. However, it will take longer to restart from this mode. This mode has

higher precedence than the standby mode, i.e. setting this bit along with bit 4 for

standby mode will result in the DAC going into powerdown mode.

0: Normal operation

1: Powerdown mode

8.6.1.3 Register 3 (0x03)

Figure 55. Register 3 (0x03)

7

6

5

4

3

2

1

0

Reserved

RO

RQML

R/W

Reserved

R/W

RQMR

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 34. Register 3 (0x03) Field Descriptions

Bit

7-5

4

Field

Type

RO

Reset

Description

Reserved

RQML

Reserved

R/W

0

Mute Left Channel – This bit issues soft mute request for the left channel. The volume

will be smoothly ramped down/up to avoid pop/click noise.

0: Normal volume

1: Mute

3-1

0

Reserved

RQMR

R/W

Reserved

0

Mute Right Channel – This bit issues soft mute request for the right channel. The

volume will be smoothly ramped down/up to avoid pop/click noise.

0: Normal volume

1: Mute

8.6.1.4 Register 4 (0x04)

Figure 56. Register 4 (0x04)

7

6

5

4

PLCK

R

3

2

1

0

Reserved

R/W

Reserved

R/W

PLLE

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 35. Register 4 (0x04) Field Descriptions

Bit

7-5

4

Field

Type

R/W

R

Reset

Description

Reserved

PLCK

Reserved

0

PLL Lock Flag – This bit indicates whether the PLL is locked or not. When the PLL is

disabled this bit always shows that the PLL is not locked.

0: The PLL is locked

1: The PLL is not locked

3-1

0

Reserved

PLLE

R/W

Reserved

1

PLL Enable – This bit enables or disables the internal PLL. When PLL is disabled, the

master clock will be switched to the MCLK.

0: Disable PLL

1: Enable PLL

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8.6.1.5 Register 6 (0x06)

Figure 57. Register 6 (0x06)

7

6

5

4

3

2

1

0

Reserved

R/W

DBPG

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 36. Register 6 (0x06) Field Descriptions

Bit

7-4

3

Field

Type

Reset

Description

Reserved

DBPG

0

Reserved

R/W

Page auto increment disable – Disable page auto increment mode. for non -zero

books. When end of page is reached it goes back to 8th address location of next page

when this bit is 0. When this bit is 1 it goes to 0 th location of current page itself like in

older part.

0: Enable Page auto increment

1: Disable Page auto increment

2-0

Reserved

R/W

0

Reserved

8.6.1.6 Register 7 (0x07)

Figure 58. Register 7 (0x07)

7

6

5

4

3

2

1

0

Reserved

R/W

DEMP

R/W

Reserved

R/W

SDSL

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 37. Register 7 (0x07) Field Descriptions

Bit

7-5

4

Field

Type

R/W

Reset

Description

Reserved

DEMP

0

Reserved

De-Emphasis Enable – This bit enables or disables the de-emphasis filter. The default

coefficients are for 44.1 kHz sampling rate, but can be changed by reprogramming the

appropriate coeffients in RAM.

0: De-emphasis filter is disabled

1: De-emphasis filter is enabled

3-1

0

Reserved

SDSL

R/W

0

1

Reserved

SDOUT Select – This bit selects what is being output as SDOUT via the SDOUT pin.

0: SDOUT is the DSP output (post-processing)

1: SDOUT is the DSP input (pre-processing)

8.6.1.7 Register 8 (0x08)

Figure 59. Register 8 (0x08)

7

6

5

4

3

2

1

0

Reserved

R/W

G2OE

R/W

MUTEOE

R/W

Reserved

R/W

Table 38. Register 8 (0x08) Field Descriptions

Bit

7-6

5

Field

Type

R/W

Reset

Description

Reserved

G2OE

Reserved

0

SDOUT Output Enable – This bit sets the direction of the

SDOUT pin

0: SDOUT is input

1: SDOUT is output

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Table 38. Register 8 (0x08) Field Descriptions (continued)

Bit

Field

Type

Reset

Description

4

MUTEOE

R/W

0

MUTE Control Enable – This bit sets an enable of MUTE control

from PCM to TPA

0: MUTE control disable

1: MUTE control enable

Reserved

3-0

Reserved

R/W

0

8.6.1.8 Register 9 (0x09)

Figure 60. Register 9 (0x09)

7

6

5

4

3

2

1

0

Reserved

R/W

SCLKP

R/W

SCLKO

R/W

Reserved

R/W

LRCLKFSO

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 39. Register 9 (0x09) Field Descriptions

Bit

7-6

5

Field

Type

Reset

Description

Reserved

SCLKP

Reserved

R/W

0

SCLK Polarity – This bit sets the inverted SCLK mode. In inverted SCLK mode, the

DAC assumes that the LRCLK and DIN edges are aligned to the rising edge of the

SCLK. Normally they are assumed to be aligned to the falling edge of the SCLK.

0: Normal SCLK mode

1: Inverted SCLK mode

4

SCLKO

R/W

0

SCLK Output Enable – This bit sets the SCLK pin direction to output for I2S master

mode operation. In I2S master mode the PCM51xx outputs the reference SCLK and

LRCLK, and the external source device provides the DIN according to these clocks.

Use P0-R32 to program the division factor of the MCLK to yield the desired SCLK rate

(normally 64 FS)

0: SCLK is input (I2S slave mode)

1: SCLK is output (I2S master mode)

3-1

0

Reserved

LRKO

Reserved

R/W

0

LRCLK Output Enable – This bit sets the LRCLK pin direction to output for I2S master

mode operation. In I2S master mode the PCM51xx outputs the reference SCLK and

LRCLK, and the external source device provides the DIN according to these clocks.

Use P0-R33 to program the division factor of the SCLK to yield 1 FS for LRCLK.

0: LRCLK is input (I2S slave mode)

1: LRCLK is output (I2S master mode)

8.6.1.9 Register 12 (0x0C)

Figure 61. Register 12 (0x0C)

7

6

5

4

3

2

1

0

Reserved

R/W

RSCLK

R/W

RLRK

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 40. Register 12 (0x0C) Field Descriptions

Bit

Field

Type

Reset

Description

7-2

Reserved

R/W

Reserved

1

RSCLK

R/W

0

Master Mode SCLK Divider Reset – This bit, when set to 0, will reset the MCLK divider

to generate SCLK clock for I2S master mode. To use I2S master mode, the divider

must be enabled and programmed properly.

0: Master mode SCLK clock divider is reset

1: Master mode SCLK clock divider is functional

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Table 40. Register 12 (0x0C) Field Descriptions (continued)

Bit

Field

Type

Reset

Description

0

RLRK

R/W

1

Master Mode LRCLK Divider Reset – This bit, when set to 0, will reset the SCLK

divider to generate LRCLK clock for I2S master mode. To use I2S master mode, the

divider must be enabled and programmed properly.

0: Master mode LRCLK clock divider is reset

1: Master mode LRCLK clock divider is functional

8.6.1.10 Register 13 (0x0D)

Figure 62. Register 13 (0x0D)

7

6

5

4

3

2

1

0

Reserved

R/W

SREF

R/W

Reserved

R/W

SDSP

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 41. Register 13 (0x0D) Field Descriptions

Bit

7-5

4

Field

Type

R/W

Reset

Description

Reserved

SREF

Reserved

0

DSP clock source – This bit select the source clock for internal PLL. This bit is ignored

and overriden in clock auto set mode.

0: The PLL reference clock is MCLK

1: The PLL reference clock is SCLK

010: The PLL reference clock is oscillator clock

011: The PLL reference clock is GPIO (selected using P0-R18)

Others: Reserved (PLL reference is muted)

3

Reserved

SDSP

R/W

Reserved

2-0

0

DAC clock source – These bits select the source clock for DSP clock divider.

000: Master clock (PLL/MCLK and OSC auto-select)

001: PLL clock

010: OSC clock

011: MCLK clock

100: SCLK clock

101: GPIO (selected using P0-R16)

Others: Reserved (muted)

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8.6.1.11 Register 14 (0x0E)

Figure 63. Register 14 (0x0E)

7

6

5

4

3

2

1

0

Reserved

R/W

SDAC

R/W

Reserved

R/W

SOSR

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 42. Register 14 (0x0E) Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

Reserved

SDAC

0

Reserved

6-4

DAC clock source – These bits select the source clock for DAC clock divider.

000: Master clock (PLL/MCLK and OSC auto-select)

001: PLL clock 010: OSC clock

011: MCLK clock

100: SCLK clock

101: GPIO (selected using P0-R16)

Others: Reserved (muted)

3

Reserved

SOSR

R/W

0

Reserved

2-0

OSR clock source – These bits select the source clock for OSR clock divider.

000: DAC clock

001: Master clock (PLL/MCLK and OSC auto-select)

010: PLL clock

011: OSC clock

100: MCLK clock

101: SCLK clock

110: GPIO (selected using P0-R17)

Others: Reserved (muted)

8.6.1.12 Register 15 (0x0F)

Figure 64. Register 15 (0x0F)

7

6

5

4

3

2

1

0

Reserved

R/W

SNCP

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 43. Register 15 (0x0F) Field Descriptions

Bit

7-3

2-0

Field

Type

R/W

Reset

Description

Reserved

SNCP

Reserved

0

NCP clock source – These bits select the source clock for CP clock divider.

000: DAC clock

001: Master clock (PLL/MCLK and OSC auto-select)

010: PLL clock

011: OSC clock

100: MCLK clock

101: SCLK clock

110: GPIO (selected using P0-R17)

Others: Reserved (muted)

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8.6.1.13 Register 16 (0x10)

Figure 65. Register 16 (0x10)

7

6

5

4

3

2

1

0

Reserved

R/W

GDSP

R/W

Reserved

R/W

GDAC

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 44. Register 16 (0x10) Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

Reserved

GDSP

0

Reserved

6-4

GPIO Source for uCDSP clk – These bits select the SDOUT pin as clock input source

when GPIO is selected as DSP clock divider source.

000: N/A

001: N/A

010: N/A

011: N/A

100: N/A

101: SDOUT

Others: Reserved (muted)

3

Reserved

GDAC

R/W

0

Reserved

2-0

GPIO Source for DAC clk – These bits select the SDOUT pin as clock input source

when GPIO is selected as DAC clock divider source.

000: N/A

001: N/A

010: N/A

011: N/A

100: N/A

101: SDOUT

Others: Reserved (muted)

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8.6.1.14 Register 17 (0x11)

Figure 66. Register 17 (0x11)

7

6

5

4

3

2

1

0

Reserved

R/W

GNCP

R/W

Reserved

R/W

GOSR

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 45. Register 17 (0x11) Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

Reserved

GNCP

0

Reserved

6-4

GPIO Source for NCP clk – These bits select the SDOUT pin as clock input source

when GPIO is selected as CP clock divider source

000: N/A

001: N/A

010: N/A

011: N/A

100: N/A

101: SDOUT

Others: Reserved (muted)

3

Reserved

GOSR

R/W

0

Reserved

2-0

GPIO Source for OSR clk – These bits select the SDOUT pin as clock input source

when GPIO is selected as OSR clock divider source.

000: N/A

001: N/A

010: N/A

011: N/A

100: N/A

101: SDOUT

Others: Reserved (muted)

8.6.1.15 Register 18 (0x12)

Figure 67. Register 18 (0x12)

7

6

5

4

3

2

1

0

Reserved

R/W

GREF

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 46. Register 18 (0x12) Field Descriptions

Bit

7-3

2-0

Field

Type

R/W

Reset

Description

Reserved

GREF

0

Reserved

GPIO Source for PLL reference clk – These bits select the SDOUT pin as clock input

source when GPIO is selected as the PLL reference clock source.

000: N/A

001: N/A

010: N/A

011: N/A

100: N/A

101: SDOUT

Others: Reserved (muted)

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8.6.1.16 Register 20 (0x14)

Figure 68. Register 20 (0x14)

7

6

5

4

3

2

1

0

Reserved

R/W

PPDV

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 47. Register 20 (0x14) Field Descriptions

Bit

7-4

3-0

Field

Type

R/W

Reset

Description

Reserved

PPDV

0

Reserved

PLL P – These bits set the PLL divider P factor. These bits are ignored in clock auto

set mode.

0000: P=1

0001: P=2

...

1110: P=15

1111: Prohibited (do not set this value)

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8.6.1.17 Register 21 (0x15)

Figure 69. Register 21 (0x15)

7

6

5

4

3

2

1

0

Reserved

R/W

PJDV

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 48. Register 21 (0x15) Field Descriptions

Bit

7-6

5-0

Field

Type

Reset

0

Description

Reserved

PJDV

Reserved

R/W

001000

PLL J – These bits set the J part of the overall PLL multiplication factor J.D * R.

These bits are ignored in clock auto set mode.

000000: Prohibited (do not set this value)

000001: J=1

000010: J=2

...

111111: J=63

8.6.1.18 Register 22 (0x16)

Figure 70. Register 22 (0x16)

7

6

5

4

3

2

1

0

Reserved

R/W

PDDV

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 49. Register 22 (0x16) Field Descriptions

Bit

7-6

5-0

Field

Type

R/W

Reset

Description

Reserved

PDDV

Reserved

0

PLL D (MSB) – These bits set the D part of the overall PLL multiplication factor J.D * R.

These bits are ignored in clock auto set mode.

0 (in decimal): D=0000

1 (in decimal): D=0001

...

9999 (in decimal): D=9999

Others: Prohibited (do not set)

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8.6.1.19 Register 23 (0x17)

Figure 71. Register 23 (0x17)

7

6

5

4

3

2

1

0

PDDV

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 50. Register 23 (0x17) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

PDDV

R/W

0

PLL D (LSB) – These bits set the D part of the overall PLL multiplication factor J.D * R.

These bits are ignored in clock auto set mode.

0 (in decimal): D=0000

1 (in decimal): D=0001

...

9999 (in decimal): D=9999

Others: Prohibited (do not set)

8.6.1.20 Register 24 (0x18)

Figure 72. Register 24 (0x18)

7

6

5

4

3

2

1

0

Reserved

R/W

PRDV

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 51. Register 24 (0x18) Field Descriptions

Bit

7-4

3-0

Field

Type

R/W

Reset

Description

Reserved

PRDV

Reserved

0

PLL R – These bits set the R part of the overall PLL multiplication factor J.D * R. These

bits are ignored in clock auto set mode.

0000: R=1

0001: R=2

...

1111: R=16

8.6.1.21 Register 27 (0x1B)

Figure 73. Register 27 (0x1B)

7

6

5

4

3

2

1

0

Reserved

R/W

DDSP

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 52. Register 27 (0x1B) Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

Reserved

DDSP

Reserved

6-0

0

DSP Clock Divider – These bits set the source clock divider value for the DSP clock.

These bits are ignored in clock auto set mode.

0000000: Divide by 1

0000001: Divide by 2

...

1111111: Divide by 128

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8.6.1.22 Register 28 (0x1C)

Figure 74. Register 28 (0x1C)

7

6

5

4

3

2

1

0

Reserved

R/W

DDAC

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 53. Register 28 (0x1C) Field Descriptions

Bit

7

Field

Type

Reset

Description

Reserved

DDAC

Reserved

6-4

3-0

R/W

0

1

DAC Clock Divider – These bits set the source clock divider value for the DAC clock.

These bits are ignored in clock auto set mode.

0000000: Divide by 1

0000001: Divide by 2

...

1111111: Divide by 128

8.6.1.23 Register 29 (0x1D)

Figure 75. Register 29 (0x1D)

7

6

5

4

3

2

1

0

Reserved

R/W

DNCP

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 54. Register 29 (0x1D) Field Descriptions

Bit

7

Field

Type

Reset

Description

Reserved

DNCP

Reserved

6-2

1-0

R/W

0

1

NCP Clock Divider – These bits set the source clock divider value for the CP clock.

These bits are ignored in clock auto set mode.

0000000: Divide by 1

0000001: Divide by 2

...

1111111: Divide by 128

8.6.1.24 Register 30 (0x1E)

Figure 76. Register 30 (0x1E)

7

6

5

4

3

2

1

0

Reserved

R/W

DOSR

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 55. Register 30 (0x1E) Field Descriptions

Bit

7

Field

Type

Reset

Description

Reserved

DOSR

Reserved

6-4

3-0

R/W

0

1

OSR Clock Divider – These bits set the source clock divider value for the OSR clock.

These bits are ignored in clock auto set mode.

0000000: Divide by 1

0000001: Divide by 2

...

1111111: Divide by 128

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8.6.1.25 Register 32 (0x20)

Figure 77. Register 32 (0x20)

7

6

5

4

3

2

1

0

Reserved

R/W

DSCLK

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 56. Register 32 (0x20) Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

Reserved

DSCLK

Reserved

6-0

0

Master Mode SCLK Divider – These bits set the MCLK divider value to generate I2S

master SCLK clock.

0000000: Divide by 1

0000001: Divide by 2

...

1111111: Divide by 128

8.6.1.26 Register 33 (0x21)

Figure 78. Register 33 (0x21)

7

6

5

4

3

2

1

0

DLRK

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 57. Register 33 (0x21) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DLRK

R/W

0

Master Mode LRCLK Divider – These bits set the I2S master SCLK clock divider value

to generate I2S master LRCLK clock

00000000: Divide by 1

00000001: Divide by 2

...

11111111: Divide by 256

76

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8.6.1.27 Register 34 (0x22)

Figure 79. Register 34 (0x22)

7

6

5

4

3

2

1

0

Reserved

R/W

I16E

R/W

Reserved

R/W

FSSP

R/W

FSSP

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 58. Register 34 (0x22) Field Descriptions

Bit

7-5

4

Field

Type

R/W

Reset

Description

Reserved

I16E

Reserved

0

16x Interpolation – This bit enables or disables the 16x interpolation mode

0: 8x interpolation

1: 16x interpolation

3

2

Reserved

FSSP

R/W

Reserved

1

0

FS Speed Mode – These bits select the FS operation mode, which must be set

according to the current audio sampling rate. These bits are ignored in clock auto set

mode.

1-0

000: Reserved

001: Reserved

010: Reserved

011: 48 kHz

100: 88.2-96 kHz

101: Reserved

110: Reserved

111: 32kHz

77

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8.6.1.28 Register 37 (0x25)

Figure 80. Register 37 (0x25)

7

6

5

4

3

2

1

0

Reserved

R/W

IDFS

R/W

IDBK

R/W

IDSK

R/W

IDCH

R/W

IDCM

R/W

DCAS

R/W

IPLK

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 59. Register 37 (0x25) Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

Reserved

IDFS

Reserved

6

0

Ignore FS Detection – This bit controls whether to ignore the FS detection. When

ignored, FS error will not cause a clock error.

0: Regard FS detection

1: Ignore FS detection

5

4

3

2

IDBK

IDSK

IDCH

IDCM

R/W

0

Ignore SCLK Detection – This bit controls whether to ignore the SCLK detection

against LRCLK. The SCLK must be stable between 32 FS and 256 FS inclusive or an

error will be reported. When ignored, a SCLK error will not cause a clock error.

0: Regard SCLK detection

1: Ignore SCLK detection

Ignore MCLK Detection – This bit controls whether to ignore the MCLK detection

against LRCLK. Only some certain MCLK ratios within some error margin are allowed.

When ignored, an MCLK error will not cause a clock error.

0: Regard MCLK detection

1: Ignore MCLK detection

Ignore Clock Halt Detection – This bit controls whether to ignore the MCLK halt (static

or frequency is lower than acceptable) detection. When ignored an MCLK halt will not

cause a clock error.

0: Regard MCLK halt detection

1: Ignore MCLK halt detection

Ignore LRCLK/SCLK Missing Detection – This bit controls whether to ignore the

LRCLK/SCLK missing detection. The LRCLK/SCLK need to be in low state (not only

static) to be deemed missing. When ignored an LRCLK/SCLK missing will not cause

the DAC go into powerdown mode.

0: Regard LRCLK/SCLK missing detection

1: Ignore LRCLK/SCLK missing detection

1

DCAS

R/W

0

Disable Clock Divider Autoset – This bit enables or disables the clock auto set mode.

When dealing with uncommon audio clock configuration, the auto set mode must be

disabled and all clock dividers must be set manually.

Addtionally, some clock detectors might also need to be disabled. The clock autoset

feature will not work with PLL enabled in VCOM mode. In this case this feature has to

be disabled and the clock dividers must be set manually.

0: Enable clock auto set

1: Disable clock auto set

0

IPLK

R/W

0

Ignore PLL Lock Detection – This bit controls whether to ignore the PLL lock detection.

When ignored, PLL unlocks will not cause a clock error. The PLL lock flag at P0-R4, bit

4 is always correct regardless of this bit.

0: PLL unlocks raise clock error

1: PLL unlocks are ignored

78

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8.6.1.29 Register 40 (0x28)

Figure 81. Register 40 (0x28)

7

6

5

4

3

2

1

0

Reserved

R/W

AFMT

R/W

Reserved

R/W

ALEN

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 60. Register 40 (0x28) Field Descriptions

Bit

7-6

5-4

Field

–

Type

Reset

Description

AFMT

R/W

0

I2S Data Format – These bits control both input and output audio interface formats for

DAC operation.

00: I2S

01: DSP

10: RTJ

11: LTJ

3-2

1

Reserved

ALEN

R/W

Reserved

1

0

I2S Word Length – These bits control both input and output audio interface sample

word lengths for DAC operation.

0

00: 16 bits

01: 20 bits

10: 24 bits

11: 32 bits

8.6.1.30 Register 41 (0x29)

Figure 82. Register 41 (0x29)

7

6

5

4

3

2

1

0

AOFS

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 61. Register 41 (0x29) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

AOFS

R/W

0

I2S Shift – These bits control the offset of audio data in the audio frame for both input

and output. The offset is defined as the number of SCLK from the starting (MSB) of

audio frame to the starting of the desired audio sample.

00000000: offset = 0 SCLK (no offset)

00000001: ofsset = 1 SCLK

00000010: offset = 2 SCLKs

…

11111111: offset = 256 SCLKs

79

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ZHCSIA0A –MAY 2018–REVISED NOVEMBER 2018

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8.6.1.31 Register 42 (0x2A)

Figure 83. Register 42 (0x2A)

7

6

5

4

3

2

1

0

Reserved

R/W

AUPL

R/W

Reserved

R/W

AUPR

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 62. Register 42 (0x2A) Field Descriptions

Bit

7-6

5

Field

Type

R/W

Reset

Description

Reserved

AUPL

Reserved

0

1

Left DAC Data Path – These bits control the left channel audio data path connection.

00: Zero data (mute)

01: Left channel data

10: Right channel data

11: Reserved (do not set)

4

3-2

1

Reserved

AUPR

R/W

Reserved

0

1

Right DAC Data Path – These bits control the right channel audio data path

connection.

0

00: Zero data (mute)

01: Right channel data

10: Left channel data

11: Reserved (do not set)

8.6.1.32 Register 43 (0x2B)

Figure 84. Register 43 (0x2B)

7

6

5

4

3

2

1

0

Reserved

R/W

PSEL

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 63. Register 43 (0x2B) Field Descriptions

Bit

7-5

4-1

0

Field

Type

R/W

Reset

Description

Reserved

PSEL

Reserved

0

1

DSP Program Selection – These bits select the DSP program to use for audio

processing.

00000: Reserved

00001: Rom Mode 1

00010: Reserved

00011: Reserved

80

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8.6.1.33 Register 44 (0x2C)

Figure 85. Register 44 (0x2C)

7

6

5

4

3

2

1

0

Reserved

R/W

CMDP

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 64. Register 44 (0x2C) Field Descriptions

Bit

7-3

2-0

Field

Type

Reset

Description

Reserved

CMDP

Reserved

R/W

0

Clock Missing Detection Period – These bits set how long both SCLK and LRCLK keep

low before the audio clocks deemed missing and the DAC transitions to powerdown

mode.

000: about 1 second

001: about 2 seconds

010: about 3 seconds

...

111: about 8 seconds

8.6.1.34 Register 59 (0x3B)

Figure 86. Register 59 (0x3B)

7

6

5

4

3

2

1

0

Reserved

R/W

AMTL

R/W

Reserved

R/W

AMTR

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 65. Register 59 (0x3B) Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

Reserved

AMTL

Reserved

6-4

0

Auto Mute Time for Left Channel – These bits specify the length of consecutive zero

samples at left channel before the channel can be auto muted. The times shown are

for 96 kHz sampling rate and will scale with other rates.

000: 11.5 ms

001: 53 ms

010: 106.5 ms

011: 266.5 ms

100: 0.535 sec

101: 1.065 sec

110: 2.665 sec

111: 5.33 sec

3

Reserved

AMTR

R/W

Reserved

2-0

0

Auto Mute Time for Right Channel – These bits specify the length of consecutive zero

samples at right channel before the channel can be auto muted. The times shown are

for 96 kHz sampling rate and will scale with other rates.

000: 11.5 ms

001: 53 ms

010: 106.5 ms

011: 266.5 ms

100: 0.535 sec

101: 1.065 sec

110: 2.665 sec

111: 5.33 sec

81

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ZHCSIA0A –MAY 2018–REVISED NOVEMBER 2018

www.ti.com.cn

8.6.1.35 Register 60 (0x3C)

Figure 87. Register 60 (0x3C)

7

6

5

4

3

2

1

0

Reserved

R/W

PCTL

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 66. Register 60 (0x3C) Field Descriptions

Bit

7-2

1-0

Field

Type

R/W

Reset

Description

Reserved

PCTL

0

Reserved

Digital Volume Control – These bits control the behavior of the digital volume.

00: The volume for Left and right channels are independent

01: Right channel volume follows left channel setting

8.6.1.36 Register 61 (0x3D)

Figure 88. Register 61 (0x3D)

7

6

5

4

3

2

1

0

VOLL

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 67. Register 61 (0x3D) Field Descriptions

Bit

Field

Type

Reset

00110000

Description

7-0

VOLL

R/W

Left Digital Volume – These bits control the left channel digital volume. The

digital volume is 24 dB to –103 dB in –0.5 dB step.

00000000: +24.0 dB

00000001: +23.5 dB

…

00101111: +0.5 dB

00110000: 0.0 dB

00110001: –0.5 dB

...

11111110: –103 dB

11111111: Mute

8.6.1.37 Register 62 (0x3E)

Figure 89. Register 62 (0x3E)

7

6

5

4

3

2

1

0

VOLR

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

82

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ZHCSIA0A –MAY 2018–REVISED NOVEMBER 2018

Table 68. Register 62 (0x3E) Field Descriptions

Bit

Field

VOLR

Type

Reset

Description

7-0

R/W

0011000 Right Digital Volume – These bits control the right channel digital volume. The digital

0

volume is 24 dB to –103 dB in –0.5 dB step.

00000000: +24.0 dB

00000001: +23.5 dB

…

00101111: +0.5 dB

00110000: 0.0 dB

00110001: –0.5 dB

...

11111110: –103 dB

11111111: Mute

8.6.1.38 Register 63 (0x3F)

Figure 90. Register 63 (0x3F)

7

6

5

4

3

2

1

0

VNDF

R/W

VNDS

R/W

VNUF

R/W

VNUS

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 69. Register 63 (0x3F) Field Descriptions

Bit

Field

Type

Reset

Description

7-6

VNDF

R/W

00

Digital Volume Normal Ramp Down Frequency – These bits control the frequency of

the digital volume updates when the volume is ramping down. The setting here is

applied to soft mute request, asserted by XSMUTE pin or P0-R3.

00: Update every 1 FS period

01: Update every 2 FS periods

10: Update every 4 FS periods

11: Directly set the volume to zero (Instant mute)

5-4

3-2

1-0

VNDS

VNUF

VNUS

R/W

11

00

11

Digital Volume Normal Ramp Down Step – These bits control the step of the digital

volume updates when the volume is ramping down.

The setting here is applied to soft mute request, asserted by XSMUTE pin or P0-R3.

00: Decrement by 4 dB for each update

01: Decrement by 2 dB for each update

10: Decrement by 1 dB for each update

11: Decrement by 0.5 dB for each update

Digital Volume Normal Ramp Up Frequency – These bits control the frequency of the

digital volume updates when the volume is ramping up.

The setting here is applied to soft unmute request, asserted by XSMUTE pin or P0-R3.

00: Update every 1 FS period

01: Update every 2 FS periods

10: Update every 4 FS periods

11: Directly restore the volume (Instant unmute)

Digital Volume Normal Ramp Up Step – These bits control the step of the digital

volume updates when the volume is ramping up.

The setting here is applied to soft unmute request, asserted by XSMUTE pin or P0-R3.

00: Increment by 4 dB for each update

01: Increment by 2 dB for each update

10: Increment by 1 dB for each update

11: Increment by 0.5 dB for each update

83

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8.6.1.39 Register 64 (0x40)

Figure 91. Register 64 (0x40)

7

6

5

4

3

2

1

0

VEDF

R/W

VEDS

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 70. Register 64 (0x40) Field Descriptions

Bit

Field

Type

Reset

Description

7-6

VEDF

R/W

0

Digital Volume Emergency Ramp Down Frequency – These bits control the frequency

of the digital volume updates when the volume is ramping down due to clock error or

power outage, which usually needs faster ramp down compared to normal soft mute.

00: Update every 1 FS period

01: Update every 2 FS periods

10: Update every 4 FS periods

11: Directly set the volume to zero (Instant mute)

5-4

3-0

VEDS

R/W

1

Digital Volume Emergency Ramp Down Step – These bits control the step of the digital

volume updates when the volume is ramping down due to clock error or power outage,

which usually needs faster ramp down compared to normal soft mute.

00: Decrement by 4 dB for each update

01: Decrement by 2 dB for each update

10: Decrement by 1 dB for each update

11: Decrement by 0.5 dB for each update

Reserved

8.6.1.40 Register 65 (0x41)

Figure 92. Register 65 (0x41)

7

6

5

4

3

2

1

0

Reserved

R/W

ACTL

R/W

AMLE

R/W

AMRE

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 71. Register 65 (0x41) Field Descriptions

Bit

7-3

2

Field

Type

R/W

Reset

Description

Reserved

ACTL

Reserved

1

Auto Mute Control**NOBUS** – This bit controls the behavior of the auto mute upon

zero sample detection. The time length for zero detection is set with P0-R59.

0: Auto mute left channel and right channel independently.

1: Auto mute left and right channels only when both channels are about to be auto

muted.

1

0

AMLE

AMRE

R/W

1

Auto Mute Left Channel**NOBUS** – This bit enables or disables auto mute on right

channel. Note that when right channel auto mute is disabled and the P0-R65, bit 2 is

set to 1, the left channel will also never be auto muted.

0: Disable right channel auto mute

1: Enable right channel auto mute

Auto Mute Right Channel**NOBUS** – This bit enables or disables auto mute on left

channel. Note that when left channel auto mute is disabled and the P0-R65, bit 2 is set

to 1, the right channel will also never be auto muted.

0: Disable left channel auto mute

1: Enable left channel auto mute

84

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8.6.1.41 Register 67 (0x43)

Figure 93. Register 67 (0x43)

7

6

5

4

3

2

1

0

DLPA

R/W

DRPA

R/W

DLPM

R/W

DRPM

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 72. Register 67 (0x43) Field Descriptions

Bit

Field

Type

Reset

Description

7-6

DLPA

R/W

0

Left DAC primary AC dither gain – These bits control the AC dither gain for left channel

primary DAC modulator.

00: AC dither gain = 0.125

01: AC dither gain = 0.25

5-4

3-2

DRPA

DLPM

R/W

0

Right DAC primary AC dither gain – These bits control the AC dither gain for right

channel primary DAC modulator.

00: AC dither gain = 0.125

01: AC dither gain = 0.25

Left DAC primary DEM dither gain – These bits control the dither gain for left channel

primary Galton DEM.

00: DEM dither gain = 0.5

01: DEM dither gain = 1.0

Others: Reserved (do not set)

1-0

DRPM

R/W

0

Right DAC primary DEM dither gain – These bits control the dither gain for right

channel primary Galton DEM.

00: DEM dither gain = 0.5

01: DEM dither gain = 1.0

Others: Reserved (do not set)

8.6.1.42 Register 68 (0x44)

Figure 94. Register 68 (0x44)

7

6

5

4

3

2

1

0

Reserved

R/W

DLPD

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 73. Register 68 (0x44) Field Descriptions

Bit

7-3

2-0

Field

Type

R/W

Reset

Description

Reserved

DLPD

Reserved

0

Left DAC primary DC dither – These bits control the DC dither amount to be added to

the lower part of the left channel primary DAC modulator. The DC dither is expressed

is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input.

00000000000 : No DC dither

00000000001 : 2^-11× 1/32 FS

00000000010 : 2^-10× 1/32 FS

85

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www.ti.com.cn

8.6.1.43 Register 69 (0x45)

Figure 95. Register 69 (0x45)

7

6

5

4

3

2

1

0

DLPD

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 74. Register 69 (0x45) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DLPD

R/W

0

Left DAC primary DC dither – These bits control the DC dither amount to be added to

the lower part of the left channel primary DAC modulator. The DC dither is expressed

is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input.

00000000000 : No DC dither

00000000001 : 2^-11× 1/32 FS

00000000010 : 2^-10× 1/32 FS

8.6.1.44 Register 70 (0x46)

Figure 96. Register 70 (0x46)

7

6

5

4

3

2

1

0

DRPD

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 75. Register 70 (0x46) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DRPD

R/W

0

Right DAC primary DC dither – These bits control the DC dither amount to be added to

the lower part of the right channel primary DAC modulator. The DC dither is expressed

is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input.

00000000000 : No DC dither

00000000001 : 2^-11× 1/32 FS

00000000010 : 2^-10× 1/32 FS

8.6.1.45 Register 71 (0x47)

Figure 97. Register 71 (0x47)

7

6

5

4

3

2

1

0

DRPD

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 76. Register 71 (0x47) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DRPD

R/W

0

Right DAC primary DC dither – These bits control the DC dither amount to be added to

the lower part of the right channel primary DAC modulator. The DC dither is expressed

is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input.

00000000000 : No DC dither

00000000001 : 2^-11× 1/32 FS

00000000010 : 2^-10× 1/32 FS

86

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8.6.1.46 Register 72 (0x48)

Figure 98. Register 72 (0x48)

7

6

5

4

3

2

1

0

DLSA

R/W

DRSA

R/W

DLSM

R/W

RSM

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 77. Register 72 (0x48) Field Descriptions

Bit

Field

Type

Reset

Description

7-6

DLSA

R/W

01

Left DAC secondary AC dither gain – These bits control the AC dither gain for left

channel secondary DAC.

00: AC dither gain = 0.125

01: AC dither gain = 0.25

5-4

DRSA

R/W

01

Right DAC secondary AC dither gain – These bits control the AC dither gain for right

channel secondary DAC modulator.

00: AC dither gain = 0.125

01: AC dither gain = 0.25

10: AC dither gain = 0.5

11: no AC dither

3-2

1-0

DLSM

DRSM

R/W

01

Left DAC secondary DEM dither gain – These bits control the dither gain for left

channel secondary Galton DEM.

00: DEM dither gain = 0.5

01: DEM dither gain = 1.0

Others: Reserved (do not set)

Right DAC secondary DEM dither gain – These bits control the dither gain for right

channel secondary Galton DEM.

00: DEM dither gain = 0.5

01: DEM dither gain = 1.0

Others: Reserved (do not set)

87

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www.ti.com.cn

8.6.1.47 Register 73 (0x49)

Figure 99. Register 73 (0x49)

7

6

5

4

3

2

1

0

DLSD

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 78. Register 73 (0x49) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DLSD

R/W

0

Left DAC secondary DC dither – These bits control the DC dither amount to be added

to the lower part of the left channel secondary DAC modulator. The DC dither is

expressed is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input.

00000000000 : No DC dither

00000000001 : 2^–11× 1/32 FS

00000000010 : 2^–10× 1/32 FS

8.6.1.48 Register 74 (0x4A)

Figure 100. Register 74 (0x4A)

7

6

5

4

3

2

1

0

DLSD

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 79. Register 74 (0x4A) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DLSD

R/W

0

Left DAC secondary DC dither – These bits control the DC dither amount to be added

to the lower part of the left channel secondary DAC modulator. The DC dither is

expressed is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input.

00000000000 : No DC dither

00000000001 : 2^–11× 1/32 FS

00000000010 : 2^–10× 1/32 FS

88

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8.6.1.49 Register 75 (0x4B)

Figure 101. Register 75 (0x4B)

7

6

5

4

3

2

1

0

DRSD

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 80. Register 75 (0x4B) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DRSD

R/W

0000000 Right DAC secondary DC dither – These bits control the DC dither amount to be added

0

to the lower part of the right channel secondary DAC modulator. The DC dither is

expressed is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input.

00000000000 : No DC dither

00000000001 : 2^–11× 1/32 FS

00000000010 : 2^–10× 1/32 FS

8.6.1.50 Register 76 (0x4C)

Figure 102. Register 76 (0x4C)

7

6

5

4

3

2

1

0

DRSD

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 81. Register 76 (0x4C) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DRSD

R/W

0000000 Right DAC secondary DC dither – These bits control the DC dither amount to be added

0

to the lower part of the right channel secondary DAC modulator. The DC dither is

expressed is Q0.11 format, with 1.0 equals to 1/32 fullscale modulator input.

00000000000 : No DC dither

00000000001 : 2^–11× 1/32 FS

00000000010 : 2^–10× 1/32 FS

89

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8.6.1.51 Register 78 (0x4E)

Figure 103. Register 78 (0x4E)

7

6

5

4

3

2

1

0

OLOF

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 82. Register 78 (0x4E) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

OLOF

R/W

0000000 Left OFSCAL offset – These bits controls the amount of manual DC offset to be added

0

to the left channel DAC output. The additional offset would be approximately the

negative of the decimal value of this register divided by 4 in mV.

01111111 : –31.75 mV

01111110 : –31.50 mV

…

00000010 : –0.50 mV

00000001 : –0.25 mV

00000000 : 0.0 mV

11111111 : +0.25 mV

11111110 : +0.50 mV

…

10000000 : +32.0 mV

8.6.1.52 Register 79 (0x4F)

Figure 104. Register 79 (0x4F)

7

6

5

4

3

2

1

0

OROF

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 83. Register 79 (0x4F) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

OROF

R/W

0

Right OFSCAL offset – These bits controls the amount of manual DC offset to be

added to the right channel DAC output. The additional offset would be approximately

the negative of the decimal value of this register divided by 4 in mV.

01111111 : –31.75 mV

01111110 : –31.50 mV

…

00000010 : –0.50 mV

00000001 : –0.25 mV

00000000 : 0.0 mV

11111111 : +0.25 mV

11111110 : +0.50 mV

…

10000000 : +32.0 mV

90

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8.6.1.53 Register 85 (0x55)

Figure 105. Register 85 (0x55)

7

6

5

4

3

2

1

0

Reserved

R/W

G2SL

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 84. Register 85 (0x55) Register Field Descriptions

Bit

7-5

4-0

Field

Type

R/W

Reset

Description

Reserved

G2SL

0

Reserved

SDOUT Output Selection – These bits select the signal to output to SDOUT. To

actually output the selected signal, the SDOUT must be set to output mode at P0-R8.

0000: off (low)

0001: DSP SDOUT output

0010: Register SDOUT output (P0-R86, bit 5)

0011: Auto mute flag (asserted when both L and R channels are auto muted)

0100: Auto mute flag for left channel

0101: Auto mute flag for right channel

0110: Clock invalid flag (clock error or clock changing or clock missing)

0111: Serial audio interface data output (SDOUT)

1000: Analog mute flag for left channel (low active)

1001: Analog mute flag for right channel (low active)

1010: PLL lock flag

1011: Charge pump clock

1100: Reserved

1101: Reserved

1110: Under voltage flag, asserted when XSMUTE voltage is higher than 0.7 DVDD

1111: Under voltage flag, asserted when XSMUTE voltage is higher than 0.3 DVDD **

INTERNAL **

1100: Short detection flag for left channel

1101: Short detection flag for right channel

10000: PLL clock/4 10001: Oscillator clock/4

10010: Impedance sense flag for left channel

10011: Impedance sense flag for right channel

10100: Internal UVP flag, becomes low when VDD falls below roughly 2.7V

10101: Offset calibration flag, asserted when the system is offset calibrating itself.

10110: Clock error flag

10111: Clock changing flag

11000: Clock missing flag

11001: Clock halt detection flag

11010: DSP boot done flag

11011: Charge pump voltage output valid flag (low active)

Others: N/A (zero)

91

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8.6.1.54 Register 86 (0x56)

Figure 106. Register 86 (0x56)

7

6

5

4

3

2

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 85. Register 86 (0x56) Register Field Descriptions

Bit

7-6

5

Field

Type

R/W

Reset

Description

Reserved

GOUT2

0

Reserved

GPIO Output Control – This bit controls the SDOUT pin output when the selection at

P0-R85 is set to 0010 (register output)

0: Output low

1: Output high

4

MUTE

R/W

0

This bit controls the MUTE output when the selection at P0-R84 is set to 0010 (register

output).

0: Output low

1: Output high

3-0

Reserved

8.6.1.55 Register 87 (0x57)

Figure 107. Register 87 (0x57)

7

6

5

4

3

2

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 86. Register 87 (0x57) Field Descriptions

Bit

7-6

5

Field

Type

R/W

Reset

Description

Reserved

GINV2

0

Reserved

GPIO Output Inversion – This bit controls the polarity of the SDOUT pin output. When

set to 1, the output will be inverted for any signal being selected.

0: Non-inverted

1: Inverted

4

MUTE

R/W

0

This bit controls the polarity of MUTE output. When set to 1, the output will be inverted

for any signal being selected.

0: Non-inverted

1: Inverted

3-0

Reserved

8.6.1.56 Register 88 (0x58)

Figure 108. Register 88 (0x58)

7

6

5

4

3

2

1

0

DIEI

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 87. Register 88 (0x58) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DIEI

RO

0x84

Die ID, Device ID = 0x84

92

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8.6.1.57 Register 91 (0x5B)

Figure 109. Register 91 (0x5B)

7

6

5

DTFS

R

4

3

2

1

0

Reserved

R/W

DTSR

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 88. Register 91 (0x5B) Field Descriptions

Bit

7

Field

Type

R/W

R

Reset

Description

Reserved

DTFS

0

Reserved

6-4

Detected FS – These bits indicate the currently detected audio sampling rate.

000: Error (Out of valid range)

001: 8 kHz

010: 16 kHz

011: 32-48 kHz

100: 88.2-96 kHz

101: 176.4-192 kHz

110: 384 kHz

3-0

DTSR

R

0

Detected MCLK Ratio – These bits indicate the currently detected MCLK ratio. Note

that even if the MCLK ratio is not indicated as error, clock error might still be flagged

due to incompatible combination with the sampling rate. Specifically the MCLK ratio

must be high enough to allow enough DSP cycles for minimal audio processing when

PLL is disabled. The absolute MCLK frequency must also be lower than 50 MHz.

0000: Ratio error (The MCLK ratio is not allowed)

0001: MCLK = 32 FS

0010: MCLK = 48 FS

0011: MCLK = 64 FS

0100: MCLK = 128 FS

0101: MCLK = 192 FS

0110: MCLK = 256 FS

0111: MCLK = 384 FS

1000: MCLK = 512 FS

1001: MCLK = 768 FS

1010: MCLK = 1024 FS

1011: MCLK = 1152 FS

1100: MCLK = 1536 FS

1101: MCLK = 2048 FS

1110: MCLK = 3072 FS

93

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8.6.1.58 Register 92 (0x5C)

Figure 110. Register 92 (0x5C)

7

6

5

4

3

2

1

0

DTBR

R

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 89. Register 92 (0x5C) Field Descriptions

Bit

7-1

0

Field

Type

R/W

R

Reset

Description

Reserved

DTBR

0

Reserved

Detected SCLK Ratio (MSB)

8.6.1.59 Register 93 (0x5D)

Figure 111. Register 93 (0x5D)

7

6

5

4

3

2

1

0

DTBR

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 90. Register 93 (0x5D) Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DTBR

R/W

Detected SCLK Ratio (LSB) – These bits indicate the currently detected SCLK

ratio, i.e. the number of SCLK clocks in one audio frame. Note that for extreme

case of SCLK = 1 FS (which is not usable anyway), the detected ratio will be

unreliable

94

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8.6.1.60 Register 94 (0x5E)

Figure 112. Register 94 (0x5E)

7

6

CDST6

R

5

CDST5

R

4

CDST4

R

3

CDST3

R

2

CDST2

R

1

CDST1

R

0

CDST0

R

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 91. Register 94 (0x5E) Field Descriptions

Bit

7

Field

Type

R/W

R

Reset

Description

Reserved

CDST6

0

Reserved

6

Clock Detector Status – This bit indicates whether the MCLK clock is present or not.

0: MCLK is present

1: MCLK is missing (halted)

5

CDST5

R

This bit indicates whether the PLL is locked or not. The PLL will be reported as

unlocked when it is disabled.

0: PLL is locked

1: PLL is unlocked

4

3

CDST4

CDST3

R

This bit indicates whether the both LRCLK and SCLK are missing (tied low) or not.

0: LRCLK and/or SCLK is present 1: LRCLK and SCLK are missing

This bit indicates whether the combination of current sampling rate and MCLK ratio is

valid for clock auto set.

0: The combination of FS/MCLK ratio is valid

1: Error (clock auto set is not possible)

2

CDST2

R

This bit indicates whether the MCLK is valid or not. The MCLK ratio must be detectable

to be valid. There is a limitation with this flag, that is, when the low period of LRCLK is

less than or equal to five SCLKs, this flag will be asserted (MCLK invalid reported).

0: MCLK is valid

1: MCLK is invalid

1

0

CDST1

CDST0

R

This bit indicates whether the SCLK is valid or not. The SCLK ratio must be stable and

in the range of 32-256FS to be valid.

0: SCLK is valid

1: SCLK is invalid

This bit indicated whether the audio sampling rate is valid or not. The sampling rate

must be detectable to be valid. There is a limitation with this flag, that is when this flag

is asserted and P0-R37 is set to ignore all asserted error flags such that the DAC

recovers, this flag will be de-asserted (sampling rate invalid not reported anymore).

0: Sampling rate is valid

1: Sampling rate is invalid

95

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www.ti.com.cn

8.6.1.61 Register 95 (0x5F)

Figure 113. Register 95 (0x5F)

7

6

5

4

LTSH

R

3

2

CKMF

R

1

CSRF

R

0

CERF

R

Reserved

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 92. Register 95 (0x5F) Field Descriptions

Bit

7-5

4

Field

Type

R/W

R

Reset

Description

Reserved

LTSH

0

Reserved

Latched Clock Halt – This bit indicates whether MCLK halt has occurred. The bit is

cleared when read.

0: MCLK halt has not occurred

1: MCLK halt has occurred since last read

3

2

Reserved

CKMF

R/W

R

0

Reserved

Clock Missing – This bit indicates whether the LRCLK and SCLK are missing (tied low).

0: LRCLK and/or SCLK is present

1: LRCLK and SCLK are missing

1

0

CSRF

CERF

R

Clock Resync Request – This bit indicates whether the clock resynchronization is in

progress.

0: Not resynchronizing

1: Clock resynchronization is in progress

Clock Error – This bit indicates whether a clock error has occurred. The bit is cleared

when read

0: Clock error has not occurred

1: Clock error has occurred.

96

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8.6.1.62 Register 108 (0x6C)

Figure 114. Register 108 (0x6C)

7

6

5

4

3

2

1

AMLM

R

0

AMRM

R

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 93. Register 108 (0x6C) Field Descriptions

Bit

7-2

1

Field

Type

R/W

R

Reset

Description

Reserved

AMLM

0

Reserved

Left Analog Mute Monitor – This bit is a monitor for left channel analog mute status.

0: Mute

1: Unmute

0

AMRM

R

Right Analog Mute Monitor – This bit is a monitor for right channel analog mute status.

0: Mute

1: Unmute

8.6.1.63 Register 119 (0x77)

Figure 115. Register 119 (0x77)

7

6

5

GPIN2

R

4

MUTE

R

3

2

1

0

Reserved

R/W

Reserved

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 94. Register 119 (0x77) Field Descriptions

Bit

7-6

5

Field

Type

R/W

R

Reset

Description

Reserved

GPIN2

0

Reserved

GPIO Input States – This bit indicates the logic level at SDOUT pin.

0: Low

1: High

4

MUTE

R

0

This bit indicates the logic level at MUTE pin.

0: Low

1: High

3-0

Reserved

Reserved bits. Data on these bits may vary.

0: Low

1: High

97

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8.6.1.64 Register 120 (0x78)

Figure 116. Register 120 (0x78)

7

6

5

4

AMFL

R

3

2

1

0

AMFR

R

Reserved

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 95. Register 120 (0x78) Field Descriptions

Bit

7-5

4

Field

Type

R/W

R

Reset

Description

Reserved

AMFL

0

Reserved

Auto Mute Flag for Left Channel – This bit indicates the auto mute status for left

channel.

0: Not auto muted

1: Auto muted

3-1

0

Reserved

AMFR

R/W

R

0

Reserved

Auto Mute Flag for Right Channel – This bit indicates the auto mute status for right

channel.

0: Not auto muted

1: Auto muted

8.6.2 Registers - Page 1

8.6.2.1 Register 1 (0x01)

Figure 117. Register 1 (0x01)

7

6

5

4

3

2

1

0

Reserved

R/W

OSEL

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 96. Register 1 (0x01) Field Descriptions

Bit

Field

Type

Reset

Description

7-1

Reserved

R/W

0

Reserved

Output Amplitude Type - This bit selects the output amplitude type. The clock autoset

feature will not work with PLL enabled in VCOM mode.

In this case this feature has to be disabled via P0-R37 and the clock dividers must be

set manually.

0

OSEL

R/W

0

0: VREF mode (Constant output amplitude against AVDD variation)

1: VCOM mode (Output amplitude is proportional to AVDD variation)

98

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8.6.2.2 Register 2 (0x02)

Figure 118. Register 2 (0x02)

7

6

5

4

3

2

1

0

Reserved

R/W

LAGN

R/W

Reserved

R/W

RAGN

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 97. Register 2 (0x02) Field Descriptions

Bit

Field

Type

Reset

Description

7-5

Reserved

R/W

0

Reserved

Analog Gain Control for Left Channel - This bit controls the left channel analog gain.

4

3-1

0

LAGN

R/W

0

0: 0 dB

1: -6 dB

Reserved

RAGN

Reserved

Analog Gain Control for Right Channel - This bit controls the right channel analog gain.

0: 0 dB

1: -6 dB

8.6.2.3 Register 6 (0x06)

Figure 119. Register 6 (0x06)

7

6

5

4

3

2

1

0

Reserved

R/W

AMCT

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 98. Register 6 (0x06) Field Descriptions

Bit

Field

Type

Reset

Description

7-1

Reserved

R/W

0

Reserved

Analog Mute Control -This bit enables or disables analog mute following digital mute.

0

AMCT

R/W

1

0: Disabled

1: Enabled

99

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8.6.2.4 Register 7 (0x07)

Figure 120. Register 7 (0x07)

7

6

5

4

3

2

1

0

Reserved

R/W

AGBL

R/W

Reserved

R/W

AGBR

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 99. Register 7 (0x07) Field Descriptions

Bit

Field

Type

Reset

Description

7-5

Reserved

R/W

0

Reserved

Analog +10% Gain for Left Channel - This bit enables or disables amplitude boost

mode for left channel.

0: Normal amplitude

4

3-1

0

AGBL

R/W

0

1: +10% (+0.8 dB) boosted amplitude

Reserved

AGBR

Reserved

Analog +10% Gain for Right Channel - This bit enables or disables amplitude boost

mode for right channel.

0: Normal amplitude

1: +10% (+0.8 dB) boosted amplitude

8.6.2.5 Register 9 (0x09)

Figure 121. Register 9 (0x09)

7

6

5

4

3

2

1

0

Reserved

R/W

DEME

R/W

VCPD

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 100. Register 9 (0x09) Field Descriptions

Bit

Field

Type

Reset

Description

7-2

Reserved

R/W

0

Reserved

VCOM Pin as De-emphasis Control - This bit controls whether to use the

DEEMP/VCOM pin as De-emphasis control.

0: Disabled (DEEMP/VCOM is not used to control De-emphasis)

1: Enabled (DEEMP/VCOM is used to control De-emphasis)

1

0

DEME

VCPD

R/W

0

1

Power down control for VCOM - This bit controls VCOM powerdown switch.

0: VCOM is powered on

1: VCOM is powered down

100

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9 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Typical Applications

The TAS3251 device supports both 2-channel, bridge-tied load (BTL) and mono, parallel bridge-tied load output

configurations. This allows flexibility to configure and program the device for a number of different applications:

•

2.0, Stereo Systems - this is a standard stereo configuration. Use either one TAS3251 device in stereo, BTL

or two TTAS3251 devices in PBTL.

•

0.1, Mono Speaker - the TAS3251 can be used as a 1-channel amplifier when configured in PBTL.

Two-Way (1.1) Powered Speaker - the TAS3251 processing and amplifier support two-way or active

crossover systems with a tweeter and woofer driven by independent amplifiers. This allows for the removal of

passive crossover components in the speaker. This can either be accomplished using one TAS3251 device in

BTL or two TAS3251 devices in PBTL.

•

Three-Way Powered Speaker - the TAS3251 processing and amplifier support a three-way active speaker

with a tweeter, mid-range and woofer each driven by independent amplifiers. This allows the removal of

passive crossover components in the speaker. This can be accomplished by using two TAS3251 devices (2x

BTL + 1x PBTL) or three TAS3251 devices each configured in PBTL.

2.1 Systems - the TAS3251 can be configured to support a 2.1 to support stereo, 2-channels (2x BTL) and a

subwoofer (1x PBTL).

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Typical Applications (接下页)

9.1.1 Stereo, Bridge Tied Load (BTL) Application

Bridge-tied load (BTL) is a 2-channel amplifier configuration that can be used for stereo systems or two-way

powered speakers. See design details below.

SDOUT

3.3 V

SCLK LRCLK

SDA SCL

/DAC_MUTE

SDIN

MCLK

1 …F

1

2

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

DAC_AVDD

DAC_OUTB+

DAC_OUTB-

DAC_OUTA-

DAC_OUTA+

CPVSS

499

1 nF

10 k

AGND

SDA

3

499

4

SCL

5

XPU

100 k

100 k 100 k

100 k

1 ꢀF

6

CN

SDOUT

MCLK

1 ꢀF

7

GND

3.3 V

8

CP

SCLK

9

DAC_DVDD

DGND

SDIN

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

1 µF

LRCK

DVDD_REG

GVDD_A

GND

ADR

33 nF

12V

L_FILTER

1 ꢀF

DAC_MUTE

BST_A+

BST_A-

GND

330 nF

33 nF

C_FILTER

MODE

TAS3251

SPK_INA+

SPK_INA-

OC_ADJ

FREQ_ADJ

OSC_IOM

OSC_IOP

DVDD

10 ꢀF

1 …F

470 mF

SPK_OUTA+

PVDD_A

SPK_OUTA-

GND

10 ꢀF

C_FILTER

L_FILTER

R_{OC_ADJ}

R_{FREQ_ADJ}

PVDD

GND

L_FILTER

SPK_OUTB+

PVDD_B

SPK_OUTB-

GND

1 ꢀF

GND

C_FILTER

1 …F

AVDD

470 …F

C_START

SPK_INB+

SPK_INB-

RESET_AMP

FAULT

33 nF

10 nF

BST_B+

BST_B-

GVDD_B

CLIP_OTW

10 µF

C_FILTER

L_FILTER

10 µF

/RESET_AMP

/FAULT

33nF

/CLIP_OTW

12 V

100 nF

图 122. Bridge-Tied Load (BTL) Application Diagram

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Typical Applications (接下页)

9.1.2 Mono, Parallel Bridge-Tied Load (PBTL) Application

Parallel bridge-tied load (PBTL) is a mono, one-channel amplifier configuration that provides twice the current of

a single BTL channel. The TAS3251 supports both pre-filter PBTL and post-filter PBTL, which allows the Class-D

output terminals to be paralleled before or after the LC filter. Paralleling the outputs after the LC filter requires

four inductors and paralleling the outputs before the LC filter requires only two inductors.

9.1.2.1 Parallel Bridge-Tied Load (PBTL), Pre-Filter

The following diagram shows an application using pre-filter PBTL, which requires only two inductors. Note that

the inductor should have a saturation current that is equal to the maximum current during an output short

condition.

•

SPK_OUTA+ and SPK_OUTB+ are connected before L_FILTERfor the positive amplifier output.

SPK_OUTA- and SPK_OUTB- are connected before L_FILTERfor the negative amplifier output.

SDOUT

3.3 V

SCLK LRCK

SDIN

SDA SCL

MCLK

/DAC_MUTE

1 …F

1

2

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

DAC_AVDD

DAC_OUTB+

DAC_OUTB-

DAC_OUTA-

DAC_OUTA+

CPVSS

10 k

AGND

SDA

3

499

1 nF

4

SCL

5

XPU

100 k

1 ꢀF

6

CN

SDOUT

MCLK

1 ꢀF

7

GND

3.3V

8

CP

SCLK

9

DAC_DVDD

DGND

SDIN

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

1 µF

LRCK

DVDD_REG

GVDD_A

GND

ADR

33 nF

12V

1 ꢀF

DAC_MUTE

BST_A+

BST_A-

GND

330 nF

33 nF

MODE

TAS3251

SPK_INA+

SPK_INA-

OC_ADJ

FREQ_ADJ

OSC_IOM

OSC_IOP

DVDD

10 ꢀF

PVDD

1 …F

470 mF

SPK_OUTA+

PVDD_A

SPK_OUTA-

GND

L_FILTER

10 ꢀF

R_{OC_ADJ}

C_FILTER

R_{FREQ_ADJ}

GND

C_FILTER

SPK_OUTB+

PVDD_B

SPK_OUTB-

GND

1 ꢀF

L_FILTER

GND

1 …F

AVDD

470 …F

1 ꢀF

C_START

SPK_INB+

SPK_INB-

RESET_AMP

FAULT

33 nF

10 nF

BST_B+

BST_B-

GVDD_B

CLIP_OTW

GND

/RESET_AMP

/FAULT

33nF

/CLIP_OTW

12 V

100 nF

图 123. Pre-Filter Parallel Bridge-Tied Load (PBTL) Application Diagram

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Typical Applications (接下页)

9.1.2.2 Parallel Bridge-Tied Load, Post-Filter

The following diagram shows an application using post-filter PBTL, which requires four inductors. The positive

and negative output current are shared between two inductors.

•

SPK_OUTA+, SPK_OUTA-, SPK_OUTB+ and SPK_OUTB- are each connected to L_FILTERfirst.

The speaker side of the inductors are connected A+ and B+ and A- and B-. See diagram below.

3.3 V

SDOUT

SCLK LRCK

SDIN

SDA SCL

MCLK

/DAC_MUTE

1 …F

1

2

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

DAC_AVDD

DAC_OUTB+

DAC_OUTB-

DAC_OUTA-

DAC_OUTA+

CPVSS

10 k

AGND

SDA

3

499

1 nF

4

SCL

5

XPU

100 k

1 ꢀF

6

CN

SDOUT

MCLK

1 ꢀF

7

GND

3.3V

8

CP

SCLK

9

DAC_DVDD

DGND

SDIN

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

1 µF

LRCK

DVDD_REG

GVDD_A

GND

ADR

33 nF

12V

L_FILTER

1 ꢀF

DAC_MUTE

BST_A+

BST_A-

GND

330 nF

33 nF

MODE

TAS3251

PVDD

SPK_INA+

SPK_INA-

OC_ADJ

FREQ_ADJ

OSC_IOM

OSC_IOP

DVDD

10 ꢀF

1 …F

470 mF

SPK_OUTA+

PVDD_A

SPK_OUTA-

GND

R_{OC_ADJ}

10 ꢀF

L_FILTER

C_FILTER

R_{FREQ_ADJ}

GND

L_FILTER

SPK_OUTB+

PVDD_B

SPK_OUTB-

GND

C_FILTER

1 ꢀF

GND

1 …F

AVDD

470 …F

1 ꢀF

C_START

SPK_INB+

SPK_INB-

RESET_AMP

FAULT

33 nF

10 nF

GND

BST_B+

BST_B-

GVDD_B

CLIP_OTW

L_FILTER

/RESET_AMP

/FAULT

33nF

/CLIP_OTW

12 V

100 nF

图 124. Post-Filter Parallel Bridge-Tied Load (PBTL) Application Diagram

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9.1.3 Design Requirements

The following are required for operating and controlling the TAS3251.

•

Power Supplies

–

Analog and Digital: 3.3-V supply

Gate Drive: 12-V supply

PVDD: 12-V to 36-V supply

•

Communication: Host processor serving as I²C compliant master

Memory: The TAS3251 has a volatile register map that will reset when power is removed. The host processor

should have adequate memory to initialize the device to the desired configuration.

9.1.4 Detailed Design Procedure

9.1.4.1 Step One: Schematic and Layout Design

Begin by designing the hardware for the TAS3251. Use the Typical Application Schematic and Pin Function

Table as a guide for configuring the hardware pins. Follow the component placement and board layout from the

TAS3251EVM. The most critical sections of the circuit are the power supply inputs, the amplifier output signals,

and the high-frequency clock and data signals. Give precedence to these traces and connections when making

design trade-offs.

1. First select the operating mode based on the application requirement: BTL, pre-filter PBTL (2-inductors) or

post-filter PBTL (4-inductors).

2. Design the output stage including the LC filter based on the output configuration selected. Use the

TAS3251EVM as reference. The LC Filter Design Guide and LC Filter Designer tool should be used to

calculate the cutoff frequency and component values.

3. Select the switching frequency by configuring the resistor on pin 18, FREQ_ADJ.

4. Select the over-current threshold by configuring the resistor on pin 17, OC_ADJ.

5. Apply bypass and decoupling capacitors to power pins according to the Pin Function Table and the Typical

Application Schematic.

9.1.4.1.1 Decoupling Capacitor Recommendations

To design an amplifier that has robust performance, passes regulatory requirements, and exhibits good audio

performance, good quality decoupling capacitors should be used. Ceramic type X7R should be used in this

application.

Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the

selection of the 1 μF that is placed on the PVDD power supply pins to each full-bridge. It must withstand the

voltage overshoot of the PWM switching, the heat generated by the amplifier during high power output and the

ripple current created by high power output. A minimum voltage rating of 50 V is required for use with a 36 V

power supply.

9.1.4.1.2 PVDD Capacitor Recommendations

The large capacitors used in conjunction with each full-bridge, are referred to as the PVDD Capacitors. These

capacitors should be selected for proper voltage margin and adequate capacitance to support the power

requirements. In practice, with a well designed system power supply, 470 μF, 50 V supports most applications.

The PVDD capacitors should be low ESR type because they are used in a circuit associated with high-speed

switching.

9.1.4.1.3 BST Capacitors

To ensure large enough bootstrap energy storage for the high side gate drive to work correctly with all audio

source signals, 33 nF / 25V X7R BST capacitors are recommended.

9.1.4.1.4 Heatsink

The heat sink should be attached to the device using a thermally conductive paste and have a good connection

to board ground.

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9.1.4.2 Step Two: Configure the Fixed-Function Process Flow for Use with the Target System

Use the TAS3251EVM and PurePath™ Console 3 to characterize, tune and test the speaker system.

1. Use the TAS3251 Evaluation Module (TAS3251EVM) and PurePath™ Console 3 software to configure the

device settings and audio processing. PurePath Console 3 can be requested and downloaded from TI.com.

2. Once the appropriate configuration has been finalized using the TAS3251EVM, use the In-System

Programming mode in PurePath™ Console 3 to load the configuration to a TAS3251 in the final system (not

on the TAS3251EVM). Connect the I2C traces from the TAS3251EVM to the final system for programming.

Ensure the I2C lines have compatible voltages and resistor pull-ups.

9.1.4.3 Step Three: Software Integration

1. Use the export feature in PurePath™ Console 3 software to generate a register map configuration file to be

used to initialize the TAS3251at system startup.

2. Include the configuration file in the main processor program to load during the TAS3251 initialization.

3. Integrate dynamic control commands (such as volume controls, mute commands, and mode-based EQ

curves) into the main system program.

9.1.5 Two TAS3251 Device Configurations

This section describes hardware design requirements for systems using two TAS3251devices.

9.1.5.1 2 x PBTL Application

In this configuration both devices are configured in parallel bridge-tied load (PBTL) mode. Example use cases for

a 2 x PBTL hardware configuration include:

•

Stereo Speaker Pair, with left and right channel audio. This can be implemented in one of two ways:

–

Send left channel I²S or TDM data to one device and send right channel I²S or TDM data to the other

device.

–

Or, send both left and right channel to one device and send the post-processed data through the

SDOUT pin to the other device.

•

2-Way, Active Crossover Speaker, with one amplifier driving a tweeter and the other driving a woofer.

–

Send the same audio channel to both devices and use the DSP in one device for the high-pass filter

and the other device for the low-pass filter to form a 2-way, crossover.

–

Or, send the audio to one primary device, do the high-pass and low-pass processing in the primary

device, and then send either the high-pass or low-pass data only to the other device using the SDOUT

pin.

9.1.5.2 2 x BTL + 1 x PBTL Application

In this configuration one device is configured in two bridge-tied load (BTL) mode and the other device is

configured in mono, parallel bridge-tied load (PBTL) mode. Example use cases for a 2 x BTL and 1 x PBTL

hardware configuration include:

•

2.1 Speaker System, with left, right and subwoofer audio channels. In this setup, process left, right and

subwoofer audio in one device and then send the subwoofer data from SDOUT to another device.

•

3-Way, Active Crossover Speaker, with one amplifier driving a tweeter and a mid-range speaker (BTL),

and another (PBTL) driving a woofer or subwoofer. In this configuration, process everything in one device

and send the subwoofer data from SDOUT to another device.

9.1.6 Three or More TAS3251 Device Configurations

This section describes hardware design requirements and considerations for systems using three or more

TAS3251devices.

With three or more devices in a system, the processing power of a signle TAS3251 may be insufficient. To create

a complex system, map out the audio path using multiple DSPs and use a combination of daisy-chained DSPs or

paralleled DSPs to process the audio and create the speaker signal path.

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9.1.7 Application Curves

表 101. Application Curves

Configuration

BTL

Performance Graph

图 5 Total Harmonic Distortion+Noise vs Output Power

图 6 Total Harmonic Distortion+Noise vs Frequency

图 13 Total Harmonic Distortion+Noise vs Output Power

图 14 Total Harmonic Distortion+Noise vs Frequency

BTL

PBTL

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10 Power Supply Recommendations

10.1 Power Supplies

The device requires three power supplies for proper operation. A 3.3 V rail for the low voltage circuitry and DAC,

a 12 V rail for the amplifier gate-drive, and PVDD which is required to provide power to the output stage of the

audio amplifier. The operating range for these supplies is shown in the Recommended Operating Conditions. TI

recommends waiting 100 ms to 240 ms for the DVDD power supplies to stabilize before starting I²C

communication and providing stable I²S clock before enabling the device outputs.

Front-End Power Supplies (DAC + DSP)

DAC_AVDD

Internal Analog Circuitry

Internal Mixed

Signal Circuitry

Internal Digital

Circuitry

+

3.3V

DAC_DVDD

DVDD_REG

External Filtering/Decoupling

œ

LDO

CPVSS

External Filtering/Decoupling

Charge

Pump

DAC Output Stage

(Positive)

DAC Output Stage

(Negative)

Gate Drive

Voltage

Analog Internal

Circuitry

AVDD

DVDD

GVDD

Linear

Regulator

External Decoupling

+

GVDD

Digital Internal

Circuitry

œ

Linear

Regulator

External Decoupling

PVDD

Output Stage

Power Supply

+

PVDD

Output Stage Power Supplies

œ

图 125. Power Supply Functional Block Diagram

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Power Supplies (接下页)

10.1.1 DAC_DVDD and DAC_AVDD Supplies

The DAC_DVDD supply is required from the system to power several portions of the device. As shown in 图 125,

it provides power to the DVDD_REG pin and the CPVDD pin. Proper connection, routing, and decoupling

techniques are highlighted in the EVM User's Guide (as well as the Application and Implementation section and

the Layout Examples section) and must be followed as closely as possible for proper operation and performance.

Deviation from the guidance offered in the TAS3251EVM User's Guide, which follows the same techniques as

those shown in the Application and Implementation section, can result in reduced performance, errant

functionality, or even damage to the TAS3251 device.

Some portions of the device also require a separate power supply that is a lower voltage than the external

DAC_DVDD supply. To simplify the power supply requirements for the system, the TAS3251 device includes an

integrated low-dropout (LDO) linear regulator to create this supply. This linear regulator is internally connected to

the DAC_DVDD supply and its output is presented on the DVDD_REG pin, providing a connection point for an

external bypass capacitor. It is important to note that the linear regulator integrated in the device has only been

designed to support the current requirements of the internal circuitry, and should not be used to power any

additional external circuitry. Additional loading on this pin could cause the voltage to sag, negatively affecting the

performance and operation of the device.

The outputs of the high-performance DACs used in the TAS3251 device are ground centered, requiring both a

positive low-voltage supply and a negative low-voltage supply. The positive power supply for the DAC output

stage is taken from the DAC_AVDD pin, which can be connected to the DAC_DVDD supply provided by the

system. A charge pump is integrated in the TAS3251 device to generate the negative low-voltage supply. The

power supply input for the charge pump is the CPVDD pin. The CPVSS pin is provided to allow the connection of

a filter capacitor on the negative low-voltage supply. As is the case with the other supplies, the component

selection, placement, and routing of the external components for these low voltage supplies are shown in the

TAS3251 EVM User's Guide and should be followed as closely as possible to ensure proper operation of the

device.

10.1.1.1 CPVSS, CN and CP Charge Pump

The TAS3251 has an integrated charge pump for generating the negative supply voltage for the DAC output

stage. Connect a 1µF ceramic capacitor between CN and CP and connect a 1 µF ceramic capacitor from

CPVSS to GND.

10.1.2 VDD Supply

The VDD supply required from the system is used to power several portions of the device. It provides power to

internal regulators DVDD and AVDD that are used to power digital and analog sections of the device output

power stage. Connect a 1 µF ceramic capacitor to GND and ensure capacitor voltage rating is sufficient for

AVDD and DVDD. See DVDD and AVDD typical voltages in Amplifier Electrical Characteristics. Proper

connection, routing, and decoupling techniques are highlighted in the Layout Section and the TAS3251EVM

User's Guide, which must be followed as closely as possible for proper operation and performance. Deviation

from the guidance offered in the section may result in reduced performance, errant functionality, or even damage

to the TAS3251 device.

Some portions of the device also require a separate power supply which is a lower voltage than the VDD supply.

To simplify the power supply requirements for the system, the TAS3251 device includes integrated low-dropout

(LDO) linear regulators to create these supplies. These linear regulators are internally connected to the VDD

supply and their outputs are presented on AVDD and DVDD pins, providing a connection point for an external

bypass capacitors. It is important to note that the linear regulators integrated in the device have only been

designed to support the current requirements of the internal circuitry, and should not be used to power any

additional external circuitry. Additional loading on these pins could cause the voltage to sag and increase noise

injection, which negatively affects the performance and operation of the device.

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Power Supplies (接下页)

10.1.3 GVDD_X Supply

The GVDD_X supply required from the system is used to power the gate-drives for the output H-bridges.

Connect 0.1 µF ceramic capacitor from pin to GND and place as close to pin as possible. The ceramic capacitor

should have a voltage rating of at least 25V. Proper connection, routing, and decoupling techniques are

highlighted in the Layout Section and the TAS3251EVM User's Guide and must be followed as closely as

possible for proper operation and performance. Deviation from the guidance offered in the these sections may

result in reduced performance, errant functionality, or even damage to the TAS3251 device.

10.1.4 PVDD Supply

The output stage of the amplifier drives the load using the PVDD supply. This is the power supply which provides

the drive current to the load during playback. Proper connection, routing, and decoupling techniques are

highlighted in the section and section and must be followed as closely as possible for proper operation and

performance. Due to the high-voltage switching of the output stage, it is particularly important to properly

decouple the output power stages. The lack of proper decoupling can results in voltage spikes which can

damage the device, or cause poor audio performance and device shutdown faults. See the TAS3251EVM for

proper component selection, placement and layout for best performance.

10.1.5 BST Supply

TAS3251 has built-in bootstrap supply for each half bridge gate drive to supply the high side MOSFETs, only

requiring a single capacitor per half bridge. The capacitors are connected to each half bridge output and charged

by the GVDD supply via an internal diode while the PWM outputs are in low state. The high side gate drive is

supplied by the voltage across the BST capacitor while the output PWM is high. It is recommended to place the

BST capacitors close to the TAS3251 device and keep the length of PCB traces to a minimum. Connect a 0.033

µF ceramic capacitor with a rating of at least 25V between BST_xx pin and the corresponding output stage

SPK_OUTxx pin.

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11 Layout

11.1 Layout Guidelines

11.1.1 General Guidelines for TAS3251

Audio amplifiers which incorporate switching output stages require special attention to the device layout and

supporting component layout. The system level performance, including electromagnetic compliance (EMC),

device reliability and audio performance are all affected by the layout. See the section Layout Examples for

layout recommendations based on amplifier output configuration. The list below provides general guidelinese to

follow when placing components and routing.

•

Use an unbroken ground plan for low impedance and low inductance return path to the power supply for

power and audio signals.

•

Keep the routing between the DAC and the amplifier inputs as short as possible. Maintain good grounding

around these traces to prevent noise.

•

The small bypass capacitors on the PVDD lines should be placed as close to the PVDD pins as possible.

Reference all bypass and decoupling components to the TAS3251 ground by connecting the ground of the

component directly to the ground of the device.

•

Maintain a contiguous ground plane from the ground pins to the PCB area surrounding the device for as

many ground pins as possible. This will help conduct heat through the pins of the package.

11.1.2 Importance of PVDD Bypass Capacitor Placement

Placing the bypass and decoupling capacitors close to supply pins is required for stability and best performance.

This applies to DVDD, AVDD, CPVDD, and PVDD.

The small bypass capacitors on the PVDD lines of the TAS3251 must be placed as close to the PVDD pins as

possible. Not only does placing these devices far away from the pins increase the electromagnetic interference in

the system, but doing so can also negatively affect the reliability of the device. Placement of these components

too far from the TAS3251 device can cause ringing on the output pins that can cause the voltage on the output

pin to exceed the maximum allowable ratings shown in the Absolute Maximum Ratings table, damaging the

device. For that reason, the capacitors on the PVDD net must be no further away from their associated PVDD

pins than what is shown in the example layouts in the Layout Examples section

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11.2 Layout Examples

11.2.1 Bridge-Tied Load (BTL) Layout Example

This section shows an example layout when operating in bridge-tied load (BTL) mode.

3.3V

1

2

56

55

54

53

52

3

4

5

6

7

8

3.3V

51

50

49

48

47

46

45

44

43

9

3.3V

12V

10

11

12

13

14

15

16

17

18

42

41

40

39

38

37

36

35

34

33

32

31

30

29

0

19

20

21

22

23

24

25

26

27

28

0

Bottom Layer Signal Traces

Pad to top layer ground pour

Pin not connected

Bottom to top layer connection via

Top Layer Signal Traces

图 126. BTL Layout Example

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Layout Examples (接下页)

11.2.2 Parallel Bridge-Tied Load (PBTL), Pre-Filter

This section shows an example layout when operating in parallel bridge-tied load (PBTL) mode and connecting

the output traces before the LC filter using two inductors. This layout requires fewer inductors compared with

post-filter PBTL.

3.3V

1

2

56

55

54

53

52

3

4

5

6

7

8

3.3V

51

50

49

48

47

46

45

44

43

9

3.3V

12V

10

11

12

13

14

15

16

17

18

42

41

40

39

38

37

36

35

34

33

32

31

30

29

0

19

20

21

22

23

24

25

26

27

28

0

Bottom Layer Signal Traces

Pad to top layer ground pour

Pin not connected

Bottom to top layer connection via

Top Layer Signal Traces

图 127. Pre-Filter PBTL Layout Example

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Layout Examples (接下页)

11.2.3 Parallel Bridge-Tied Load (PBTL), Post-Filter

This section shows an example layout when operating in parallel bridge-tied load (PBTL) mode and connecting

the output traces after the LC filter using four inductors. This layout requires fewer inductors compared with post-

filter PBTL.

3.3V

1

2

56

55

54

53

52

3

4

5

6

7

8

3.3V

51

50

49

48

47

46

45

44

43

9

3.3V

12V

10

11

12

13

14

15

16

17

18

42

41

40

39

38

37

36

35

34

33

32

31

30

29

0

19

20

21

22

23

24

25

26

27

28

0

Bottom layer signal traces

Pad to top layer ground pour

Pin not connected

Bottom to top layer connection via

Top layer signal traces

图 128. Post-Filter PBTL Layout Example

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12 器件和文档支持

12.1 器件支持

12.1.1 器件命名规则

术语表部分列出的是一个通用的术语表，其中包括常用的缩写和词语，它们都是根据一个范围广泛的 TI 计划定义

的，符合 JEDEC、IPC、IEEE 等行业标准。本部分提供的术语表定义了特定于本产品和文档、附属产品或本产品

使用的支持工具和软件的词语和缩写。如对定义和术语有其他疑问，请访问 e2e 音频放大器论坛。

桥接式负载 (BTL) 是一种输出配置，其中扬声器的两端分别连接一个半桥。

DUT 是指被测器件，用于区分不同的器件。

闭环架构是一种拓扑结构，其中放大器监视输出端子、对比输出信号与输入信号，并尝试修正输出信号的非线性。

动态控件是指系统或最终用户在正常使用时可更改的控件。

GPIO 是通用输入/输出引脚。该引脚是一个高度可配置的双向数字引脚，可执行系统所需的多种功能。

主机处理器（也称系统处理器、标量、主机或系统控制器）是指用作中央系统控制器的器件，可为与其连接的器件

提供控制信息，还可以从上游器件采集音频源数据并将其分配给其他器件。该器件通常配置音频路径中音频处理器

件（如 TAS3251）的控件，从而根据频率响应、时间校准、目标声压级、系统安全工作区域和用户偏好优化扬声

器的音频输出。

HybridFlow 通过搭配使用 RAM 内置的元件和 ROM 内置的元件构成一款可配置器件，与完全可编程器件相比更

加易于使用，而且还能保持足够的灵活性以适应多种应用

最大持续输出功率是指放大器在 25°C 运行环境温度下可持续（不关断）提供的最大输出功率。测试该参数时，要

求温度达到热平衡点且不再升高

并联桥接式负载 (PBTL) 是一种输出配置，其中扬声器的两端分别连接一对并行放置的半桥

r_DS(on)是指放大器输出级中所用 MOSFET 的导通电阻。

静态控件/静态配置是指系统正常使用时不发生变化的控件。

过孔是指 PCB 中的镀铜通孔。

12.1.2 开发支持

•

TAS3251 评估模块 TAS3251EVM (TAS3251EVM)

PurePath™ 控制台 3 软件 (PUREPATHCONSOLE)

用于 PurePath™ 音频智能放大器的扬声器特性鉴定板 (PP-SALB-EVM)

TAS3251 工艺流程 (SLAA799)

12.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录

115

TAS3251

ZHCSIA0A –MAY 2018–REVISED NOVEMBER 2018

www.ti.com.cn

12.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.4 商标

Burr-Brown, PurePath, PowerPAD, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.6 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查看左侧的导航栏。

116

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示

担保。

所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用

所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权

许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。

TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约

束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122

PACKAGE OUTLINE

DKQ0056B

PowerPAD^TMSSOP - 2.475 mm max height

S

C

A

L

E

1

.

0

PLASTIC SMALL OUTLINE

C

10.67

10.03

PIN 1 ID AREA

A

TYP

SEATING PLANE

(1.74)

0.1 C

(1.18)

54X 0.635

56

1

(2.455)

(4.455)

(3.04)

18.54

18.29

NOTE 3

2X

17.15

(3)

(6.34)

2X

(0.23)

28

29

0.37

56X

0.17

0.13

(2.29)

(1.26)

C A B

EXPOSED

(5.14)

THERMAL PAD

7.59

7.39

B

NOTE 4

2.475

2.240

NOTE 6

0.25

2.29 0.05

GAGE PLANE

0.25

0.13

TYP

SEE DETAIL A

0.08

0.00

1.02

0.51

0 - 8

DETAIL A

TYPICAL

4223602/A 04/2017

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. The exposed thermal pad is designed to be attached to an external heatsink.

6. For clamped heatsink design, refer to overall package height above the seating plane as 2.325 +/- 0.075 and molded body

thickness dimension.

www.ti.com

EXAMPLE BOARD LAYOUT

DKQ0056B

PowerPAD^TMSSOP - 2.475 mm max height

PLASTIC SMALL OUTLINE

56X (1.9)

SEE DETAILS

SYMM

1

56

56X (0.4)

54X (0.635)

SYMM

28

29

(R0.05) TYP

(9.5)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:6X

METAL UNDER

SOLDER MASK

OPENING

METAL

OPENING

EXPOSED METAL

0.05 MIN

AROUND

0.05 MAX

AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4223602/A 04/2017

NOTES: (continued)

7. Publication IPC-7351 may have alternate designs.

8. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

9. Size of metal pad may vary due to creepage requirement.

www.ti.com

EXAMPLE STENCIL DESIGN

DKQ0056B

PowerPAD^TMSSOP - 2.475 mm max height

PLASTIC SMALL OUTLINE

56X (1.9)

SYMM

1

56

56X (0.4)

54X (0.635)

SYMM

28

29

(R0.05) TYP

(9.5)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE:6X

4223602/A 04/2017

NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

11. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示

担保。

所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用

所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权

许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。

TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约

束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122


型号：	TAS3251DKQR
厂家：	TEXAS INSTRUMENTS
描述：	175W 立体声、350W 单声道、12V 至 38V 电源电压、数字输入 D 类智能音频放大器 \| DKQ \| 56 \| 0 to 70 放大器音频放大器
文件：	总123页 (文件大小：2144K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TAS3251DKQR [TI]

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