TAS5121I [TI]
DIGITAL AMPLIIFIER POWER STAGE; 数字AMPLIIFIER功率级
| 型号： | TAS5121I |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DIGITAL AMPLIIFIER POWER STAGE |
| 文件： | 总18页 (文件大小：391K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TAS5121I
www.ti.com
SLES122–SEPTEMBER 2004
TM
DIGITAL AMPLIFIER POWER STAGE
•
•
Mini/Micro Component Systems
Internet Music Appliance
FEATURES
•
100-W RMS Power (BTL) Into 4 Ω With Less
Than 10% THD+N
DESCRIPTION
•
80-W RMS Power (BTL) Into 4 Ω With Less
Than 0.2% THD+N
The TAS5121I is a high-performance, digital-amplifier
power stage designed to drive a 4-Ω speaker up to
100 W. The TAS5121I is rated for operation at
industrial temperatures. The device incorporates
PurePath Digital™ technology and can be used with
a TI audio pulse-width modulation (PWM) processor
and a simple passive demodulation filter to deliver
high-quality, high-efficiency, digital-audio amplifi-
cation.
•
•
0.09% THD+N at 1 W Into 4 Ω
Power Stage Efficiency Greater Than 90% Into
4-Ω Load
•
•
•
•
•
Self-Protecting Design
Industrial Temperature Rating
36-Pin PSOP3 Package
3.3-V Digital Interface
The efficiency of this digital amplifier can be greater
than 90%, depending on the system design.
Overcurrent protection, overtemperature protection,
and undervoltage protection are built into the
TAS5121I, safeguarding the device and speakers
against fault conditions that could damage the sys-
tem.
EMI Compliant When Used With
Recommended System Design
APPLICATIONS
•
•
DVD Receiver
Home Theatre
TOTAL HARMONIC DISTORTION + NOISE
UNCLIPPED OUTPUT POWER
vs
vs
POWER
H-BRIDGE VOLTAGE
10
90
80
R = 4 Ω
L
T
C
= 75°C
Gain = 3 dB
70
60
50
40
30
20
10
0
4 Ω
1
6 Ω
6 Ω
4 Ω
0.1
8 Ω
8 Ω
0.01
0
4
8
12
16
20
24
28
32
0.1
1
10
100
P − Power − W
PVDD_X − H-Bridge Voltage − V
G001
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PurePath Digital, PowerPAD are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004, Texas Instruments Incorporated
TAS5121I
www.ti.com
SLES122–SEPTEMBER 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
GENERAL INFOMATION
Terminal Assignment
The TAS5121I is offered in a thermally enhanced 36-pin PSOP3 (DKD) package. The DKD package has the
thermal pad on top.
DKD PACKAGE
(TOP VIEW)
GND
PWM_BP
GND
GVDD_B
GVDD_B
GND
BST_B
PVDD_B
PVDD_B
OUT_B
OUT_B
GND
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
2
3
RESET
DREG_RTN
GVDD
M3
4
5
6
7
DREG
DGND
M1
M2
DVDD
SD
DGND
OTW
GND
8
9
GND
10
11
12
13
14
15
16
17
18
OUT_A
OUT_A
PVDD_A
PVDD_A
BST_A
GND
PWM_AP
GND
GVDD_A
GVDD_A
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
DVDD TO DGND
–0.3 V to 4.2 V
GVDD_x TO GND
14.2 V
33.5 V
PVDD_X TO GND (dc voltage)
PVDD_X TO GND(2)
48 V
OUT_X TO GND (dc voltage)
OUT_X TO GND(2)
33.5 V
48 V
BST_X TO GND (dc voltage)
BST_X TO GND(2)
46 V
53 V
PWM_XP, RESET, M1, M2, M3, SD, OTW
–0.3 V to DVDD + 0.3 V
–40°C to 150°C
–40°C to 125°C
TJ
Maximum junction temperature range
Storage temperature
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The duration should be less than 100 ns (see application note SLEA025).
2
TAS5121I
www.ti.com
SLES122–SEPTEMBER 2004
ORDERING INFORMATION
TA
PACKAGE
TRANSPORT MEDIA
DESCRIPTION
36-pin PSOP3
36-pin PSOP3
–40°C to 85°C
–40°C to 85°C
TAS5121IDKD
Tube
TAS5121IDKDR
Tape and reel
PACKAGE DISSIPATION RATINGS
RθJC
(°C/W)
RθJA
(°C/W)
PACKAGE
(1)
36-Pin DKD PSOP3
0.85
See
(1) The TAS5121I package is thermally enhanced for conductive cooling using an exposed metal pad area. It is impractical to use the
devices with the pad exposed to ambient air as the only heat sinking of the device.
Therefore RθJA, a system parameter that characterizes the thermal treatment, is provided in the Thermal Information section. This
information should be used as a reference to calculate the heat dissipation ratings for a specific application.
Terminal Functions
TERMINAL
FUNCTION(1)
DESCRIPTION
NAME
BST_A
DKD
22
P
P
P
P
P
P
High-side bootstrap (BST) supply, external resistor and capacitor to OUT_A required
High-side bootstrap (BST) supply, external resistor and capacitor to OUT_B required
I/O reference ground
BST_B
DGND
33
9, 14
8
DREG
Digital supply-voltage regulator-decoupling pin, 1-µF capacitor connected to DREG_RTN
Decoupling return pin
DREG_RTN
DVDD
5
12
I/O reference supply input: 100 Ω to DREG, decoupled to GND, 0.1-µF capacitor connected to
GND
GND
1, 3, 16,
18, 21,
27, 28,
34
P
Power ground, connected to system GND
GVDD
GVDD_A
GVDD_B
M1
6
19, 20
35, 36
10
P
P
P
I
Local GVDD decoupling pin
Gate-drive input voltage
Gate-drive input voltage
Protection-mode selection pin, connect to GND
Protection-mode selection pin, connect to DREG
Output-mode selection pin; connect to GND
M2
11
I
M3
7
I
OTW
15
O
Overtemperature warning output, open-drain with internal pullup, asserted low when tempera-
ture exceeds 115°C
OUT_A
OUT_B
PVDD_A
PVDD_B
PWM_AP
PWM_BP
RESET
SD
25, 26
29, 30
23, 24
31, 32
17
O
O
P
P
I
Output, half-bridge A
Output, half-bridge B
Power supply input for half-bridge A
Power supply input for half-bridge B
PWM input signal, half-bridge A
PWM input signal, half-bridge B
Reset signal, active-low
2
I
4
I
13
O
Shutdown signal for half-bridges A and B (open-drain with internal pullup)
(1) I = input, O = Output, P = Power
3
TAS5121I
www.ti.com
SLES122–SEPTEMBER 2004
FUNCTIONAL BLOCK DIAGRAM
GVDD_A
BST_A
GVDD_A
PVDD_A
OCH
DREG
Gate
DVDD DREG
Drive
Timing
Control
and
PWM_AP
OUT_A
PWM
Receiver
GVDD_A
Protection
DGND
Gate
Drive
GND
OCL
OCH
GVDD_B
BST_B
RESET
GVDD_B
PVDD_B
DREG
DVDD
DREG
DVDD
Gate
Drive
Timing
Control
and
PWM_BP
DGND
OUT_B
PWM
Receiver
GVDD_B
Protection
Gate
Drive
GND
OCL
GVDD
DREG
OTW
SD
DREG
Protection
Logic
DREG
DREG
M1
M2
M3
OT
and
UVP
Internally
Connected
to GVDD_x
DREG_RTN
4
TAS5121I
www.ti.com
SLES122–SEPTEMBER 2004
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
DVDD
Digital supply(1)
Relative to DGND
3
3.3
3.6
V
Supply for internal gate drive and logic regu-
lators
GVDD_x
Relative to GND
10.8
12
13.2
V
PVDD_x Half-bridge supply
TJ Junction temperature
Relative to GND, RL= 4 Ω
0
0
30.5
32
V
125
°C
(1) It is recommended for DVDD to be connected to DREG via a 100-Ω resistor.
ELECTRICAL CHARACTERISTICS
PVDD_X = 30.5 V, GVDD_x = 12 V, DVDD connected to DREG via a 100-Ω resistor, RL = 4 Ω, 8X fs= 384 kHz, TAS5026
PWM processor, unless otherwise noted
TYPICAL
OVER TEMPERATURE
SYMBOL
PARAMETER
TEST CONDITIONS
TCase
75°C
=
MIN/TYP/
MAX
TA=25°C TA=25°C
UNITS
AC PERFORMANCE, BTL Mode, 1 kHz
RL = 4 Ω, THD = 10%, AES17 filter
100
80
W
W
Typ
Typ
RL = 4 Ω, THD = unclipped, AES17
filter
PO
Output power
RL = 8 Ω, THD = unclipped,
AD mode
44
W
%
%
%
Typ
Typ
Typ
Typ
PO = 1 W/channel, RL = 4 Ω,
AES17 filter
0.09
0.15
0.19
PO = 10 W/channel, RL = 4 Ω,
AES17 filter
THD+N
Total harmonic distortion + noise
PO = 80 W/channel, RL = 4 Ω,
AES17 filter
A-weighted, RL = 4 Ω, 20 Hz to
20 kHz, AES17 filter
Vn
Output-integrated noise voltage
Signal-to-noise ratio
300
95
µV
dB
dB
Max
Typ
Typ
SNR
DR
A-weighted, AES17 filter
f = 1 kHz, –60 dB, A-weighted,
AES17 filter
Dynamic range
95
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
V
V
Min
DREG
Voltage regulator
Io = 1 mA
3.3
Max
Total GVDD supply current,
operating
fS = 384 kHz, no load, 50% duty
cycle
IGVDD_x
IDVDD
24
1
30
5
mA
mA
Max
Max
DVDD supply current, operating
fS = 384 kHz, no load
OUTPUT STAGE MOSFETs
RDSon,LS Forward on-resistance, low side
RDSon,HS Forward on-resistance, high side
INPUT/OUTPUT PROTECTION
TJ = 25°C
TJ = 25°C
120
120
132
132
mΩ
mΩ
Max
Max
7
V
V
Min
Max
Typ
Typ
Min
Undervoltage protection limit,
Vuvp,G
GVDD
7.6
8.2
OTW
OTE
OC
Overtemperature warning
Overtemperature error
Overcurrent protection
Static
115
150
9.5
°C
°C
A
Static
(1)
See
.
(1) To optimize device performance and prevent overcurrent (OC) protection activation, the demodulation filter must be designed with
special care. See Demodulation Filter Design in the Application Information section of this data sheet and consider the recommended
inductors and capacitors for optimal performance. It is also important to consider PCB design and layout for optimum performance of the
TAS5121I.
5
TAS5121I
www.ti.com
SLES122–SEPTEMBER 2004
ELECTRICAL CHARACTERISTICS (continued)
PVDD_X = 30.5 V, GVDD_x = 12 V, DVDD connected to DREG via a 100-Ω resistor, RL = 4 Ω, 8X fs= 384 kHz, TAS5026
PWM processor, unless otherwise noted
TYPICAL
OVER TEMPERATURE
SYMBOL
PARAMETER
TEST CONDITIONS
TCase
75°C
=
MIN/TYP/
MAX
TA=25°C TA=25°C
UNITS
STATIC DIGITAL INPUT SPECIFICATION, PWM, PROTECTION MODE SELECTION PINS, AND OUTPUT MODE SELECTION PINS
2
DVDD
0.8
V
V
Min
Max
Max
Min
VIH
VIL
High-level input voltage
Low-level input voltage
V
–10
10
µA
µA
Leakage Input leakage current
Max
OTW/SHUTDOWN (SD)
Internal pullup resistor from OTW
and SD to DVDD
32
22
kΩ
Min
VOL
Low-level output voltage
IO = 1 mA
0.4
V
Max
TYPICAL APPLICATION CONFIGURATION USED WITH TAS5026 PWM PROCESSOR
TAS5121IDKD
1 µF
Gate-Drive
Power Supply
1
2
36
35
34
33
32
31
30
29
28
27
26
GND
GVDD_B
GVDD_B
GND
22 Ω
PWM_AP_1
PWM_BP
GND
3
1 Ω
4
100 nF
2.7 Ω
RESET
DREG_RTN
GVDD
M3
BST_B
PVDD_B
PVDD_B
OUT_B
OUT_B
GND
5
6
‡
75 nH L
PCB
33 nF
7
10 µH
100
nF
8
H-Bridge
Power Supply
DREG
DGND
M1
4.7 kΩ
4.7 kΩ
1 µF
1 µF
9
†
†
TVS Zener
1 µF
10
TVS Zener
GND
1000 µF
11
12
13
14
15
16
17
18
10 µH
M2
OUT_A
OUT_A
100 Ω
25
24
23
22
DVDD
33 nF
‡
75 nH L
PCB
SD
PVDD_A
PVDD_A
BST_A
100 nF
DGND
OTW
2.7 Ω
100 nF
1 Ω
21
20
19
GND
GND
22 Ω
PWM_BP_1
GVDD_A
PWM_AP
GND
33 µF
GVDD_A
1 µF
Micro-
controller
†
Voltage suppressor diodes: 1SMA33CAT3
‡
L
PCB
: Track in the PCB (1 mm wide and 50 mm long)
S0015−01
6
TAS5121I
www.ti.com
SLES122–SEPTEMBER 2004
TOTAL HARMONIC DISTORTION + NOISE
UNCLIPPED OUTPUT POWER
vs
vs
POWER
H-BRIDGE VOLTAGE
10
90
80
70
60
50
40
30
20
10
0
R = 4 Ω
L
T
C
= 75°C
Gain = 3 dB
4 Ω
1
6 Ω
6 Ω
4 Ω
0.1
8 Ω
8 Ω
0.01
0
4
8
12
16
20
24
28
32
0.1
1
10
100
P − Power − W
PVDD_X − H-Bridge Voltage − V
G001
Figure 1.
Figure 2.
POWER LOSS
vs
TOTAL OUTPUT POWER
UNCLIPPED OUTPUT POWER
vs
CASE TEMPERATURE
14
12
10
8
100
90
80
70
60
50
40
30
20
10
0
6
4
2
0
0
10
20
30
40
50
60
70
80
−40 −20
0
20
40
60
80
100 120
P
− Total Output Power − W
T
C
− Case Temperature − °C
O(Total)
G004
Figure 3.
Figure 4.
7
TAS5121I
www.ti.com
SLES122–SEPTEMBER 2004
EFFICIENCY
vs
TOTAL OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
100
90
80
70
60
50
40
30
20
10
0
10
R
T
= 4 Ω
= 75°C
L
C
1
75 W
0.1
10 W
1 W
0.01
0
10
20
30
40
50
60
70
80
20
100
1k
10k 20k
P
− Total Output Power − W
f − Frequency − Hz
O(Total)
G006
Figure 5.
Figure 6.
AMPLITUDE
vs
FREQUENCY
AMPLITUDE
vs
FREQUENCY
0.5
0.4
0
−20
P
T
= 1 W
= 75°C
O
C
0.3
8 Ω
6 Ω
−40
0.2
−60
0.1
−80
0.0
−0.1
−0.2
−0.3
−0.4
−0.5
−100
−120
−140
−160
4 Ω
0
2
4
6
8
10 12 14 16 18 20 22
10
100
1k
10k 20k
f − Frequency − Hz
f − Frequency − kHz
Figure 7.
Figure 8.
8
TAS5121I
www.ti.com
SLES122–SEPTEMBER 2004
THEORY OF OPERATION
POWER SUPPLIES
This power device requires only two power supply voltages: GVDD_x and PVDD_x.
GVDD_x is the gate drive supply for the device, which is usually supplied from an external 12-V power supply.
GVDD_x is also connected to an internal LDR that regulates the GVDD_x voltage down to the logic power
supply, 3.3 V, for the TAS5121I internal logic blocks. Each GVDD_x pin is decoupled to system ground by a 1-µF
capacitor.
PVDD_x is the H-bridge power supply. Two power pins are provided for each half-bridge due to the high current
density. It is important to follow the circuit and PCB layout recommendations for the design of the PVDD_x
connection. For component suggestions, see the Typical Application Configuration Used With TAS5026 PWM
Processor section in this document. Following these recommendations is important because they influence key
system parameters such as EMI, idle current, and audio performance.
When GVDD_x is applied, while RESET is held low, the error latches are cleared, SHUTDOWN is set high, and
the outputs are held in a high-impedance state. The bootstrap (BST) capacitor is charged by the current path
through the internal BST diode and external resistors placed on the PCB from each OUT_x pin to ground.
Ideally, PVDD_x is applied after GVDD_x. When GVDD_x and PVDD_x are applied, the TAS5121I is ready for
operation. PWM input signals can then be applied any time during the power-on sequence, but they must be
active and stable before RESET is set high.
Recommendations for Powering Up
> 1 ms
> 1 ms
RESET
GVDD
PVDD_X
PWM_xP
Table 1 describes the input conditions and the output states of the device.
Table 1. Input/Output States
INPUTS
OUTPUTS
OUT_A
CONDITION
DESCRIPTION
RESET
PWM_AP
PWM_BP
SHUTDOWN
OUT_B
Hi-Z
X
0
1
1
1
1
X
X
0
0
0
1
X
X
0
0
1
1
0
1
1
1
1
1
Hi-Z
Hi-Z
Shutdown
Reset
Hi-Z
GND
PVDD
GND
PVDD
GND
PVDD
PVDD
PVDD
Normal
Normal
Reserved
After the previously mentioned conditions are met, the device output begins. If PWM_AP is equal to a high and
PMW_BP is equal to a low, the high-side MOSFET in the A half-bridge of the output H-bridge conducts while the
9
TAS5121I
www.ti.com
SLES122–SEPTEMBER 2004
THEORY OF OPERATION (continued)
low-side MOSFET in the A half-bridge is not conducting. Because the source of the high-side MOSFET is
referenced to the drain of the low-side MOSFET, a bootstrapped capacitor is used to eliminate the need for
additional high-voltage power supplies. Under this condition, the opposite is true for the B half-bridge of the
output H-bridge. The low-side MOSFET in the B half-bridge conducts while the high-side MOSFET is not
conducting; therefore, the load connected between the OUT_A and OUT_B pins has PVDD applied to it from the
A side while ground is applied from the B side for the period of time PWM_AP is high and PWM_BP is low.
Furthermore, when the PWM signals change to the condition where PWM_AP is low and PWM_BP is high, the
opposite condition exists.
A constant high level is not permitted on the PWM inputs. This condition causes the BST capacitors to discharge
and can cause device damage.
A digitally controlled dead-time circuit controls the transitions between the high-side and low-side MOSFETs to
ensure that both devices in each half-bridge are not conducting simultaneously.
POWERING DOWN
For power down of the TAS5121I, an opposite approach is necessary. The RESET must be asserted LOW
before the valid PWM signal is removed.
PRECAUTION
The TAS5121I must always start up in the high-impedance (Hi-Z) state. In this state, the BST capacitor is
precharged by a resistor on each PWM output node to ground. See Typical Application Configuration Used With
TAS5026 PWM Processor. This ensures that the TAS5121I is ready for receiving PWM pulses, indicating either
HIGH- or LOW-side turnon after RESET is deasserted to the power stage.
With the following pulldown resistor and BST capacitor size, the BST charge time is:
•
•
C = 33 nF, R = 4.7 kΩ
R × C × 5 = 775.5 µs
After GVDD has been applied, it takes approximately 800 µs to fully charge the BST capacitor. During this time,
RESET must be kept low. After approximately 1 ms, the power-stage BST is charged and ready. RESET can
now be released if the PWM modulator is ready and is streaming valid PWM signals to the device. Valid PWM
signals are switching PWM signals with a frequency between 350-400 kHz. A constant HIGH level on PWM+
forces the high-side MOSFET ON until it eventually runs out of BST capacitor energy. Putting the device in this
condition should be avoided.
In practice, this means that the DVDD-to-PWM processor (modulator) should be stable, and initialization should
be completed before RESET is deasserted to the TAS5121I.
CONTROL I/O
SHUTDOWN PIN: SD
The SD pin functions as an output pin and is intended for protection-mode signaling to, for example, a controller
or other front-end device. The pin is open-drain with an internal pullup to DVDD.
The logic output is, as shown in Table 2, a combination of the device state and RESET input.
Table 2. Error Indication
SD
0
RESET
DESCRIPTION
0
1
0
1
Reserved
0
1(1)
Device in protection mode, i.e., UVP and/or OC and/or OT error
Device set high-impedance (Hi-Z), SD forced high
Normal operation
1
(1) SD is independent from RESET. This is desirable to maintain compatibility with some TI PWM modulators.
10
TAS5121I
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SLES122–SEPTEMBER 2004
OVERTEMPERATURE WARNING PIN: OTW
The OTW pin gives a temperature warning signal when temperature exceeds the set limit, as shown in Table 3.
The pin is of the open-drain type with an internal pullup to DVDD.
Table 3. OTW Temperature Indication
OTW
DESCRIPTION
0
1
Junction temperature higher than 115°C
Junction temperature lower than 115°C
OVERALL REPORTING
The SD pin, together with the OTW pin, gives chip state information as described in Table 4.
Table 4. Error Signal Decoding
OTW
SD
0
DESCRIPTION
0
0
1
1
Overtemperature error (OTE)
1
Overtemperature warning (OTW)
0
Overcurrent (OC) or undervoltage (UVP) error
Normal operation, no errors/warnings
1
CHIP PROTECTION
The TAS5121I protection function is generally implemented in a closed-loop control system with, for example, a
system controller. The TAS5121I contains three individual systems protecting the device against fault conditions.
All of the error events result in the output stage being set in a high-impedance state (Hi-Z) for maximum
protection of the device and connected equipment.
The device can be recovered by toggling RESET low and then high, after all errors are cleared. It is
recommended that if the error persists, the device is held in reset until user intervention clears the error.
OVERCURRENT (OC) PROTECTION
The device has individual current protection on both high-side and low-side power-stage FETs. The OC
protection works only with the demodulation filter present at the output. See Filter Demodulation Design in the
Application Information section of this data sheet for design constraints.
OVERTEMPERATURE (OT) PROTECTION
A dual-temperature protection system asserts a warning signal when the device junction temperature exceeds
115°C and shuts down the device when the junction temperature exceeds 150°C. The OT protection circuit is
shared by both half-bridges.
UNDERVOLTAGE PROTECTION (UVP)
Undervoltage lockout occurs when GVDD is insufficient for proper device operation. The UV protection system
protects the device under fault power-up and power-down situations by shutting the device down. The UV
protection circuits are shared by both half-bridges.
RESET FUNCTION
The reset has two functions:
•
•
Reset the power stage after a latched error event.
Hard mute—when RESET is asserted, the power stage stops switching.
In protection modes where the reset input functions as the means to re-enable operation after an error event, the
error latch is cleared on the falling edge of RESET, and normal operation is resumed on the rising edge of
RESET.
11
TAS5121I
www.ti.com
SLES122–SEPTEMBER 2004
PROTECTION MODE
LATCHED SHUTDOWN ON ALL ERRORS
In latched shutdown mode, all error situations result in a permanent shutdown (output stage Hi-Z). Re-enabling
can be done by toggling the RESET pin.
MODE PINS SELECTION
The protection mode is selected by connecting M1/M2 to DREG or DGND according to Table 5.
Table 5. Protection Mode Selection
M1
0
M2
0
PROTECTION MODE
Reserved
0
1
Latched shutdown on all errors
Reserved
1
0
1
1
Reserved
The output configuration mode is selected by connecting the M3 pin to DREG or DGND according to Table 6.
Table 6. Output Mode Selection
M3
0
OUTPUT MODE
Bridge-tied load output stage (BTL)
Reserved
1
12
TAS5121I
www.ti.com
SLES122–SEPTEMBER 2004
APPLICATION INFORMATION
DEMODULATION FILTER DESIGN
The TAS5121I amplifier outputs are driven by high-current DMOS transistors in an H-bridge configuration. These
transistors are either off or fully on.
The result is a square-wave output signal with a duty cycle that is proportional to the amplitude of the audio
signal. It is recommended that a second-order LC filter be used to recover the audio signal.
TAS5121I
L
Output A
R
(Load)
C1
C2
L
Output B
S0016−01
Figure 9. Demodulation Filter
The main purpose of the demodulation filter is to attenuate the high-frequency components of the output signals
that are out of the audio band.
Design of the demodulation filter significantly affects the audio performance of the power amplifier. Therefore, to
ensure proper operation of the OC protection circuit and meet the device THD+N specification, the selection of
the inductors used in the output filter should be carefully considered. The rule is that the inductance should
remain stable within the range of peak current seen at maximum output power and deliver approximately 5 µH of
inductance at 15 A.
If this rule is observed, the TAS5121I should not have distortion issues due to the output inductors. This prevents
device damage due to overcurrent conditions because of inductor saturation in the output filter.
Another parameter to be considered is the idle current loss in the inductor. This can be measured or specified as
inductor dissipation (D). The target specification for dissipation is less than 0.05. If this specification is not met,
idle current increases.
In general, 10-µH inductors suffice for most applications. The frequency response of the amplifier is slightly
altered by the change in output load resistance; however, unless tight control of frequency response is necessary
(better than 0.5 dB), it is not necessary to deviate from 10 µH.
The graphs in Figure 10 display the inductance-versus-current characteristics of two inductors that are suggested
for use with the TAS5121I.
13
TAS5121I
www.ti.com
SLES122–SEPTEMBER 2004
APPLICATION INFORMATION (continued)
INDUCTANCE
vs
CURRENT
11
10
9
DBF1310A
DASL983XX−1023
8
7
6
5
4
0
5
10
I − Current − A
15
Figure 10. Inductance Saturation
The selection of the capacitors that are placed from the output of each inductor to ground is simple. To complete
the output filter, use a 1-µF capacitor with a voltage rating at least twice the voltage applied to the output stage
(PVDD_x).
This capacitor should be a good quality polyester dielectric.
THERMAL INFORMATION
The following information is provided as an example.
The thermally enhanced package provided with the TAS5121I is designed to be interfaced directly to a heatsink
using a thermal interface compound (for example, Wakefield Engineering type 126 thermal grease.) The heatsink
then absorbs heat from the ICs and transfers it to the ambient air. If the heatsink is carefully designed, this
process can reach equilibrium and heat can be continually removed from the ICs without device overtemperature
shutdown. Because of the efficiency of the TAS5121I, heatsinks are smaller than those required for linear
amplifiers of equivalent performance.
RθJA is a system thermal resistance from junction to ambient air. As such, it is a system parameter with roughly
the following components:
•
•
•
RθJC (the thermal resistance from junction to case, or in this case the metal pad)
Heatsink compound thermal resistance
Heatsink thermal resistance
The thermal grease thermal resistance can be calculated from the exposed pad area and the thermal grease
manufacturer's area thermal resistance (expressed in °C-in2/W). The area thermal resistance of the example
thermal grease with a 0.001-inch-thick layer is about 0.054 °C-in2/W. The approximate exposed pad area is as
follows:
36-pin PSOP3
0.116 in2
Dividing the example thermal grease area resistance by the area of the pad gives the actual resistance through
the thermal grease for the device:
14
TAS5121I
www.ti.com
SLES122–SEPTEMBER 2004
APPLICATION INFORMATION (continued)
36-pin PSOP3
0.47 °C/W
The thermal resistance of thermally conductive pads is generally higher than a thin thermal grease layer.
Thermal tape has an even higher thermal resistance and should not be used with this package.
Heatsink thermal resistance is generally predicted by the heatsink vendor, modeled using a continuous flow
dynamics (CFD) model, or measured.
Thus, for a single monaural IC, the system RθJA = RθJC + thermal grease resistance + heatsink resistance.
Table 7 indicates modeled parameters for one TAS5121I IC on a heatsink. The junction temperature is set at
110°C while delivering 70 W RMS into 4-Ω loads with no clipping. It is assumed that the thermal grease is about
0.001 inch thick (this is critical).
Table 7. Example of Thermal Simulation
36-PIN PSOP3
Ambient temperature
Power to load
25°C
70 W
Delta T inside package
Delta T through thermal grease
Required heatsink thermal resistance
Junction temperature
System RθJA
5.5°C
3.2°C
11.0°C/W
110°C
12.3°C/W
85°C
RθJA * power dissipation
RθJC
0.85°C/W
As an indication of the importance of keeping the thermal grease layer thin, if the thermal grease layer increases
to 0.002 inches thick, the required heatsink thermal resistance increases to 5.2°C/W for the PSOP3 package.
REFERENCES
1. Digital Audio Measurements application report – TI (SLAA114)
2. PowerPAD™ Thermally Enhanced Package technical brief – TI (SLMA002)
3. System Design Considerations for True Digital Audio Power Amplifiers application report – TI (SLAA117)
4. Voltage Spike Measurement Technique and Specification application note – TI (SLEA025)
15
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2007
PACKAGING INFORMATION
Orderable Device
TAS5121IDKD
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DKD
36
36
36
36
29
Pb-Free
(RoHS)
CU NIPDAU Level-4-260C-72 HR/
Level-2-220C-1 YEAR
TAS5121IDKDE4
TAS5121IDKDR
TAS5121IDKDRE4
SSOP
SSOP
SSOP
DKD
DKD
DKD
29
Pb-Free
(RoHS)
CU NIPDAU Level-4-260C-72 HR/
Level-2-220C-1 YEAR
500
500
Pb-Free
(RoHS)
CU NIPDAU Level-4-260C-72 HR/
Level-2-220C-1 YEAR
Pb-Free
(RoHS)
CU NIPDAU Level-4-260C-72 HR/
Level-2-220C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to
discontinue any product or service without notice. Customers should obtain the latest relevant information
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subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent
TI deems necessary to support this warranty. Except where mandated by government requirements, testing
of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible
for their products and applications using TI components. To minimize the risks associated with customer
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Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not
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solutions:
Products
Amplifiers
Data Converters
DSP
Interface
Applications
Audio
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amplifier.ti.com
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interface.ti.com
logic.ti.com
www.ti.com/audio
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Logic
Power Mgmt
Microcontrollers
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power.ti.com
microcontroller.ti.com
www.ti.com/lpw
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www.ti.com/opticalnetwork
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www.ti.com/wireless
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Post Office Box 655303 Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated
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