TAS5342ADDVR [TI]
100 W STEREO DIGITAL AMPLIFIER POWER STAGE; 100瓦立体声数字放大器功率级
| 型号： | TAS5342ADDVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 100 W STEREO DIGITAL AMPLIFIER POWER STAGE |
| 文件： | 总27页 (文件大小：852K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
TAS5342A
www.ti.com ........................................................................................................................................................................................... SLAS623–NOVEMBER 2008
100 W STEREO DIGITAL AMPLIFIER POWER STAGE
1
FEATURES
DESCRIPTION
23
•
Total Power Output (Bridge Tied Load)
–
–
–
2 × 100 W at 10% THD+N Into 4 Ω
2 × 80 W at 10% THD+N Into 6 Ω
2 × 65 W at 10% THD+N Into 8 Ω
The TAS5342A is a high-performance, integrated
stereo digital amplifier power stage designed to drive
a 4-Ω bridge-tied load (BTL) at up to 100 W per
channel with low harmonic distortion, low integrated
noise, and low idle current.
•
Total Power Output (Single Ended)
–
–
4 × 40 W at 10% THD+N Into 3 Ω
4 × 30 W at 10% THD+N Into 4 Ω
The TAS5342A has a complete protection system
integrated on-chip, safeguarding the device against a
wide range of fault conditions that could damage the
system. These protection features are short-circuit
protection, over-current protection, under voltage
protection, over temperature protection, and a loss of
PWM signal (PWM activity detector).
•
•
Total Power Output (Parallel Mode)
–
–
1 × 200 W at 10% THD+N Into 2 Ω
1 × 160 W at 10% THD+N Into 3 Ω
>110 dB SNR (A-Weighted With TAS5518
Modulator)
A power-on-reset (POR) circuit is used to eliminate
power-supply sequencing that is required for most
power-stage designs.
•
•
<0.1% THD+N (1 W, 1 kHz)
Supports PWM Frame Rates of 192 kHz to
432 kHz
BTL OUTPUT POWER
vs
•
•
Resistor-Programmable Current Limit
SUPPLY VOLTAGE
130
125
Integrated Self-Protection Circuitry, Including:
T
= 75°C
120
115
110
105
100
95
–
–
–
–
–
Under Voltage Protection
Overtemperature Warning and Error
Overload Protection
C
THD+N at 10%
Short-Circuit Protection
PWM Activity Detector
90
85
80
75
4 Ω
70
•
•
Standalone Protection Recovery
65
60
55
50
45
40
35
30
25
20
Power-On Reset (POR) to Eliminate System
Power-Supply Sequencing
•
•
High-Efficiency Power Stage (>90%) With
80-mΩ Output MOSFETs
Ω
6
Thermally Enhanced Package 44-Pin HTSSOP
(DDV)
15
10
5
8 Ω
•
•
Error Reporting, 3.3-V and 5.0-V Compliant
0
EMI Compliant When Used With
Recommended System Design
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
PVDD – Supply Voltage – V
APPLICATIONS
PurePath Digital™
•
•
•
Mini/Micro Audio System
DVD Receiver
Home Theater
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
PurePath Digital, PowerPad are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
TAS5342A
SLAS623–NOVEMBER 2008 ........................................................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
GENERAL INFORMATION
Terminal Assignment
The TAS5342A is available in a thermally enhanced package 44-pin HTSSOP PowerPad™ package (DDV)
This package contains a thermal pad that is located on the top side of the device for convenient thermal coupling
to the heatsink.
DDV PACKAGE
(TOP VIEW)
GVDD_B
OTW
GVDD_A
BST_A
NC
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
NC
NC
SD
3
PVDD_A
PVDD_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
PVDD_D
PVDD_D
NC
4
5
PWM_A
RESET_AB
PWM_B
OC_ADJ
GND
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
AGND
VREG
M3
M2
M1
PWM_C
RESET_CD
PWM_D
NC
NC
VDD
GVDD_C
BST_D
GVDD_D
P0016-02
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Protection MODE Selection Pins
Protection modes are selected by shorting M1, M2, and M3 to VREG or GND.
MODE PINS
Mode Name
PWM Input(1)
Description
M3
0
M2
0
M1
0
BTL mode 1
BTL mode 2
BTL mode 3
PBTL mode
SE mode 1
SE mode 2
2N
2N
All protection systems enabled
0
0
1
Latching shudown on, PWM activity detector and OLP disabled
All protection systems enabled
0
1
0
1N
0
1
1
1N / 2N(2)
All protection systems enabled
1
0
0
1N
All protection systems enabled(3)
1
0
1
1N
Latching shudown on, PWM activity detector and OLP disabled(3)
1
1
0
Reserved
1
1
1
(1) The 1N and 2N naming convention is used to indicate the number of PWM lines to the power stage per channel in a specific mode.
(2) PWM_D is used to select between the 1N and 2N interface in PBTL mode (Low = 1N; High = 2N). PWM_D is internally pulled low in
PBTL mode. PWM_A is used as the PWM input in 1N mode and PWM_A and PWM_B are used as inputs for the 2N mode.
(3) PPSC detection system disabled.
Package Heat Dissipation Ratings(1)
PARAMETER
TAS5342ADDV
R
θJC (°C/W)—2 BTL or 4 SE channels
1.3
2.6
RθJC (°C/W)—1 BTL or 2 SE channel(s)
RθJC (°C/W)—1 SE channel
5.0
Power Pad area(2)
36 mm2
(1) JC is junction-to-case, CH is case-to-heatsink.
(2) θCH is an important consideration. Assume a 2-mil thickness of high performance grease with a thermal conductivity at 2.5W/m-K
between the pad area and the heat sink. The RθCH with this condition is 0.6°C/W for the DDV package.
R
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
TAS5342A
VDD to AGND
–0.3 V to 13.2 V
–0.3 V to 13.2 V
–0.3 V to 53 V
–0.3 V to 53 V
–0.3 V to 66.2 V
–0.3 V to 53 V
–0.3 V to 4.2 V
–0.3 V to 0.3 V
–0.3 V to 0.3 V
–0.3 V to 0.3 V
–0.3 V to 4.2 V
–0.3 V to 7 V
9 mA
GVDD_X to AGND
PVDD_X to GND_X
(2)
(2)
OUT_X to GND_X
BST_X to GND_X
BST_X to GVDD_X
VREG to AGND
GND_X to GND
GND_X to AGND
GND to AGND
(2)
(2)
PWM_X, OC_ADJ, M1, M2, M3 to AGND
RESET_X, SD, OTW to AGND
Maximum continuous sink current (SD, OTW)
Maximum operating junction temperature range, TJ
Storage temperature
0°C to 125°C
–40°C to 125°C
260°C
Lead temperature, 1,6 mm (1/16 inch) from case for 10 seconds
Minimum pulse duration, low
30 ns
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.
ORDERING INFORMATION(1)
TA
PACKAGE(1)
DESCRIPTION
0°C to 70°C
TAS5342ADDV
44-pin HTSSOP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
4
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Terminal Functions
TERMINAL
(1)
FUNCTION
DESCRIPTION
NAME
AGND
DDV NO.
11
P
P
P
P
P
P
P
P
P
P
P
P
P
P
I
Analog ground
BST_A
BST_B
BST_C
BST_D
GND
43
Bootstrap pin, A-Side
Bootstrap pin, B-Side
Bootstrap pin, C-Side
Bootstrap pin, D-Side
Ground
34
33
24
10
GND_A
GND_B
GND_C
GND_D
GVDD_A
GVDD_B
GVDD_C
GVDD_D
M1
38
Power ground for half-bridge A
Power ground for half-bridge B
Power ground for half-bridge C
Power ground for half-bridge D
37
30
29
44
Gate-drive voltage supply; A-Side
Gate-drive voltage supply; B-Side
Gate-drive voltage supply; C-Side
Gate-drive voltage supply; D-Side
Mode selection pin (LSB)
1
22
23
15
M2
14
I
Mode selection pin
M3
13
I
Mode selection pin (MSB)
NC
3, 4, 19, 20, 25, 42
–
O
O
O
O
O
O
P
P
P
P
I
No connect. Pins may be grounded.
Analog overcurrent programming pin
Overtemperature warning signal, open-drain, active-low
Output, half-bridge A
OC_ADJ
OTW
9
2
OUT_A
OUT_B
OUT_C
OUT_D
PVDD_A
PVDD_B
PVDD_C
PVDD_D
PWM_A
PWM_B
PWM_C
PWM_D
RESET_AB
RESET_CD
SD
39
36
31
28
40, 41
35
32
26, 27
6
Output, half-bridge B
Output, half-bridge C
Output, half-bridge D
Power supply input for half-bridge A
Power supply input for half-bridge B
Power supply input for half-bridge C
Power supply input for half-bridge D
PWM Input signal for half-bridge A
PWM Input signal for half-bridge B
PWM Input signal for half-bridge C
PWM Input signal for half-bridge D
Reset signal for half-bridge A and half-bridge B, active-low
Reset signal for half-bridge C and half-bridge D, active-low
Shutdown signal, open-drain, active-low
Input power supply
8
I
16
18
7
I
I
I
17
5
I
O
P
P
VDD
21
12
VREG
Internal voltage regulator
(1) I = input, O = output, P = power
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TYPICAL SYSTEM BLOCK DIAGRAM
OTW
System
Microcontroller
SD
I2C
TAS5518
BST_A
BST_B
Bootstrap
Capacitors
RESET_AB
RESET_CD
VALID
PWM_A
PWM_B
OUT_A
OUT_B
2nd-Order L-C
Output Filter
for Each
Left-
Channel
Output
Output
H-Bridge 1
Input
H-Bridge 1
Half-Bridge
2-Channel
H-Bridge
BTL Mode
OUT_C
OUT_D
PWM_C
PWM_D
2nd-Order L-C
Output Filter
for Each
Output
H-Bridge 2
Right-
Channel
Output
Input
H-Bridge 2
Half-Bridge
M1
M2
M3
BST_C
BST_D
Hardwire
Mode
Control
Bootstrap
Capacitors
4
4
4
PVDD
Power
Supply
GVDD
VDD
VREG
PVDD
GND
31.5 V
Hardwire
OC Limit
System
Power
Supply
Decoupling
Power Supply
Decoupling
GND
12 V
GVDD (12 V)/VDD (12 V)
VAC
B0047-02
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FUNCTIONAL BLOCK DIAGRAM
VDD
4
Under-
voltage
Protection
OTW
4
Internal Pullup
VREG
VREG
AGND
GND
Resistors to VREG
SD
M1
M2
M3
Power
On
Reset
Protection
and
I/O Logic
Temp.
Sense
RESET_AB
RESET_CD
Overload
I
OC_ADJ
sense
Protection
GVDD_D
BST_D
PVDD_D
OUT_D
PWM
Rcv.
Gate
PWM_D
PWM_C
PWM_B
PWM_A
Ctrl.
Ctrl.
Ctrl.
Ctrl.
Timing
Timing
Timing
Timing
Drive
BTL/PBTL−Configuration
Pulldown Resistor
GND_D
GVDD_C
BST_C
PVDD_C
OUT_C
PWM
Rcv.
Gate
Drive
BTL/PBTL−Configuration
Pulldown Resistor
GND_C
GVDD_B
BST_B
PVDD_B
OUT_B
PWM
Rcv.
Gate
Drive
BTL/PBTL−Configuration
Pulldown Resistor
GND_B
GVDD_A
BST_A
PVDD_A
OUT_A
PWM
Rcv.
Gate
Drive
BTL/PBTL−Configuration
Pulldown Resistor
GND_A
B0034-03
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RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX UNIT
PVDD_X
GVDD_X
Half-bridge supply voltage
0
31.5
34
13.2
13.2
V
V
V
Supply voltage for logic regulators and
gate-drive circuitry
10.8
12
VDD
Digital regulator supply voltage
10.8
3
12
4
RL (BTL)
RL (SE)
RL (PBTL)
LOutput (BTL)
LOutput (SE)
LOutput (PBTL)
fS
Resistive load impedance (no Cycle-by_Cycle
current control), recommended demodulation
filter
2.25
1.5
5
3
Ω
2
10
10
10
384
Minimum output inductance under
short-circuit condition
Output-filter inductance
PWM frame rate
5
µH
5
192
432
kHz
nS
µF
nF
kΩ
kΩ
°C
tLOW
Minimum low-state pulse duration per PWM
Frame, noise shaper enabled
30
CPVDD
CBST
PVDD close decoupling capacitors
0.1
33
Bootstrap capacitor, selected value supports
PWM frame rates from 192 kHz to 432 kHz
ROC
Over-current programming resistor
Resistor tolerance = 5%
27
3.3
0
27
47
REXT-PULLUP
External pull-up resistor to +3.3V to +5.0V for
SD or OTW
4.7
TJ
Junction temperature
125
AUDIO SPECIFICATIONS (BTL)
Audio performance is recorded as a chipset consisting of a TAS5518 pwm processor (modulation index limited to 97.7%) and
a TAS5342A power stage. PCB and system configuraton are in accordance with recommended guidelines. Audio frequency =
1 kHz, PVDD_x = 31.5 V, GVDD_x = 12 V, RL = 4 Ω, fS = 384 kHz, ROC = 27 kΩ, TC = 75°C, Output Filter: LDEM = 10 µH,
CDEM = 470 nF, unless otherwise noted.
TAS5342A
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
100
80
MAX
RL = 4 Ω, 10% THD+N, clipped input signal
RL = 6 Ω, 10% THD+N, clipped input signal
RL = 8 Ω, 10% THD+N, clipped input signal
RL = 4 Ω, 0 dBFS, unclipped input signal
RL = 6 Ω, 0 dBFS, unclipped input signal
RL = 8 Ω, 0 dBFS, unclipped input signal
0 dBFS; AES17 filter
POMAX
Maximum Power Output
65
W
80
PO
Unclipped Power Output
64
50
0.4%
0.09%
45
THD+N
Total harmonic distortion + noise
Output integrated noise
1 W; AES17 filter
Vn
A-weighted, AES17 filter, Auto mute disabled
A-weighted, AES17 filter, Auto mute disabled
µV
(1)
SNR
Signal-to-noise ratio
110
dB
A-weighted, input level = –60 dBFS, AES17
filter
DNR
Dynamic range
110
dB
DC Offset
Pidle
Output offset voltage
±15
2
mV
W
Power dissipation due to idle losses
(IPVDD_X)
PO = 0 W, all halfbridges switching(2)
(1) SNR is calculated relative to 0-dBFS input level.
(2) Actual system idle losses are affected by core losses of output inductors.
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AUDIO SPECIFICATIONS (Single-Ended Output)
Audio performance is recorded as a chipset consisting of a TAS5086 pwm processor (modulation index limited to 97.7%) and
a TAS5342A power stage. PCB and system configuraton are in accordance with recommended guidelines. Audio frequency =
1 kHz, PVDD_x = 31.5 V, GVDD_x = 12 V, RL = 4 Ω, fS = 384 kHz, ROC = 27 kΩ, TC = 75°C, Output Filter: LDEM = 20 µH,
CDEM = 1.0 µF, unless otherwise noted.
TAS5342A
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP MAX
RL = 3 Ω, 10% THD+N, clipped input
signal
40
POMAX
Maximum Power Output
RL = 4 Ω, 10% THD+N, clipped input
30
W
signal
RL = 3 Ω, 0 dBFS, unclipped input signal
RL = 4 Ω, 0 dBFS, unclipped input signal
0 dBFS; AES17 filter
30
20
PO
Unclipped Power Output
0.2%
0.1%
35
THD+N
Vn
Total harmonic distortion + noise
1 W; AES17 filter
A-weighted, AES17 filter, Auto mute
disabled
µV
Output integrated noise
Signal-to-noise ratio(1)
SNR
A-weighted, AES17 filter, Auto mute
disabled
109
dB
A-weighted, input level = –60 dBFS
AES17 filter
PO = 0 W, all half bridges switching(2)
DNR
Pidle
Dynamic range
109
2
dB
W
Power dissipation due to idle losses (IPVDD_X)
(1) SNR is calculated relative to 0-dBFS input level.
(2) Actual system idle losses are affected by core losses of output inductors.
AUDIO SPECIFICATIONS (PBTL)
Audio performance is recorded as a chipset consisting of a TAS5518 pwm processor (modulation index limited to 97.7%) and
a TAS5342A power stage. PCB and system configuraton are in accordance with recommended guidelines. Audio frequency =
1kHz, PVDD_x = 31.5 V, GVDD_x = 12 V, RL = 3 Ω, fS = 384 kHz, ROC = 27 kΩ, TC = 75°C, Output Filter: LDEM = 10 µH, CDEM
= 1.0 uF, unless otherwise noted.
TAS5342A
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP MAX
200
RL = 2 Ω, 10% THD+N, clipped input signal
RL = 3 Ω, 10% THD+N, clipped input signal
RL = 2 Ω, 0 dBFS, unclipped input signal
RL = 3 Ω, 0 dBFS, unclipped input signal
0 dBFS; AES17 filter
POMAX
Maximum Power Output
Unclipped Power Output
Total harmonic distortion + noise
160
W
150
PO
120
0.4%
0.09%
45
THD+N
1 W; AES17 filter
Vn
Output integrated noise
Signal-to-noise ratio(1)
A-weighted, AES17 filter, Auto mute disabled
A-weighted, AES17 filter, Auto mute disabled
µV
SNR
110
dB
A-weighted, input level = –60 dBFS AES17
filter
DNR
Dynamic range
110
±15
2
dB
mV
W
DC Offset
Pidle
Outuput offset voltage
Power dissipation due to idle losses
(IPVDD_X)
PO = 0 W, all half bridges switching(2)
(1) SNR is calculated relative to 0-dBFS input level.
(2) Actual system idle losses are affected by core losses of output inductors.
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ELECTRICAL CHARACTERISTICS
PVDD_x = 31.5 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 25°C, fS = 384 kHz, unless otherwise specified.
TAS5342A
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
Internal Voltage Regulator and Current Consumption
Voltage regulator, only used as a
reference node
VREG
VDD = 12 V
3
3.3
3.6
V
Operating, 50% duty cycle
Idle, reset mode
50% duty cycle
7.2
5.54
8
17
11
16
1.8
25
IVDD
VDD supply current
mA
IGVDD_X
Gate supply current per half-bridge
mA
mA
Reset mode
1
50% duty cycle, with 10 uH and 470 nF output
filter
16.3
IPVDD_X
Half-bridge idle current
Reset mode, no switching
465
558
µA
Output Stage MOSFETs
Drain-to-source resistance, Low
Side
RDSon,LS
TJ = 25°C, excludes metallization resistance,
TJ = 25°C, excludes metallization resistance,
80
80
89
89
mΩ
mΩ
Drain-to-source resistance, High
Side
RDSon,HS
I/O Protection
Vuvp,G
Undervoltage protection limit,
GVDD_X
9.5
V
(1)
Vuvp,hyst
Undervoltage protection limit,
GVDD_X
250
mV
BSTuvpF
BSTuvpR
OTW(1)
Puts device into RESET when BST
voltage falls below limit
5.85
7
V
V
Brings device out of RESET when
BST voltage rises above limit
Overtemperature warning
115
145
125
25
135
165
°C
°C
Temperature drop needed below
OTW temp. for OTW to be inactive
after the OTW event
(1)
OTWHYST
OTE(1)
OTE-
Overtemperature error threshold
155
30
°C
°C
ms
A
OTE - OTW differential, temperature
delta between OTW and OTE
(1)
OTWdifferential
OLPC
Overload protection counter
Overcurrent limit protection
Overcurrent response time
fS = 384 kHz
1.25
10.1
150
13.2
Resistor—programmable, high-end,
ROC = 27 kΩ with 1 ms pulse
IOC
IOCT
ns
µS
tACTIVITY
DETECTOR
Time for PWM activity detector to
activite when no PWM is present
Lack of transistion of any PWM input
Connected when RESET is active to provide
bootstrap capacitor charge. Not used in SE
mode.
Output pulldown current of each
half-bridge
IPD
3
mA
Static Digital Specifications
VIH
High-level input voltage
2
V
V
PWM_A, PWM_B, PWM_C, PWM_D, M1,
M2, M3, RESET_AB, RESET_CD
VIL
Low-level input voltage
Input leakage current
0.8
ILeakage
100
µA
OTW/SHUTDOWN (SD)
Internal pullup resistance, OTW to
RINT_PU
20
26
32
kΩ
VREG, SD to VREG
Internal pullup resistor
3
3.3
3.6
5
VOH
High-level output voltage
V
External pullup of 4.7 kΩ to 5 V
4.5
(1) Specified by design
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ELECTRICAL CHARACTERISTICS (continued)
PVDD_x = 31.5 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 25°C, fS = 384 kHz, unless otherwise specified.
TAS5342A
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
0.2
30
MAX
VOL
Low-level output voltage
Device fanout OTW, SD
IO = 4 mA
No external pullup
0.4
V
FANOUT
Devices
TYPICAL CHARACTERISTICS, BTL CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
OUTPUT POWER
vs
SUPPLY VOLTAGE
130
125
120
115
110
105
100
95
10
T
= 75°C
C
THD+N at 10%
T
= 75°C
C
5
2
THD+N at 10%
90
1
4
Ω
85
4 W
80
0.5
75
70
65
0.2
0.1
60
55
50
45
40
0.05
35
6 Ω
30
6 W
25
8 W
0.02
0.01
20
15
8 Ω
10
5
0
0.005
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
PVDD – Supply Voltage – V
20m 100m 200m
1
2
5
10 20 50 100 200
P
- Output Power - W
O
Figure 1.
Figure 2.
UNCLIPPED OUTPUT POWER
SYSTEM EFFICIENCY
vs
OUTPUT POWER
vs
SUPPLY VOLTAGE
100
95
90
85
80
75
100
95
90
85
80
75
70
65
60
55
T
= 75°C
C
4 W
6
W
4
W
8
W
70
65
60
55
6 W
50
45
50
45
40
40
35
30
25
35
30
25
20
15
10
20
15
10
5
T
= 25°C
8 W
C
THD+N at 10%
5
0
0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
0
20 40 60 80 100 120 140 160 180 200 220 240
- Output Power - W
P
O
PVDD – Supply Voltage – V
Figure 3.
Figure 4.
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
SYSTEM POWER LOSS
vs
SYSTEM OUTPUT POWER
vs
CASE TEMPERATURE
OUTPUT POWER
30
28
26
24
22
20
18
16
150
140
130
120
110
100
90
T
= 25°C
C
THD+N at 10%
4
W
6
W
4
W
80
14
12
10
8
70
60
50
40
6
W
8
W
6
30
4
2
0
THD+N at 10%
20
10
0
8 W
20 40 60 80 100 120 140 160 180 200 220 240
0
10 20 30 40 50 60 70 80 90 100 110 120
P
- Output Power - W
T
- Case Temperature - °C
O
C
Figure 5.
Figure 6.
NOISE AMPLITUDE
vs
FREQUENCY
0
V
= 19.5 V
-10
ref
= 75°C
T
C
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k
f - Frequency - Hz
Figure 7.
12
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TYPICAL CHARACTERISTICS, SE CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE
OUTPUT POWER
vs
SUPPLY VOLTAGE
vs
OUTPUT POWER
10
5
48
44
40
36
T
= 75°C
T
= 75°C
C
THD+N at 10%
C
THD+N at 10%
2
1
32
28
4 W
0.5
4 W
24
20
16
12
0.2
0.1
0.05
8
5
W
8 W
0.02
0.01
8
4
0
0.005
0
2
4
6
8 10 12 14 16 18 20 22 24 26 28 30
PVDD - Supply Voltage - V
100m 200m
10
50
20m
1
2
20
P
O
- Output Power - W
Figure 8.
Figure 9.
OUTPUT POWER
vs
CASE TEMPERATURE
48
44
40
36
32
4 W
28
24
8 W
20
16
12
8
THD+N at 10%
4
0
10 20 30 40 50 60 70 80 90 100 110 120
T
- Case Temperature - °C
C
Figure 10.
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TYPICAL CHARACTERISTICS, PBTL CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE
OUTPUT POWER
vs
SUPPLY VOLTAGE
vs
OUTPUT POWER
10
5
240
220
200
180
160
140
120
T = 75°C
C
THD+N at 10%
T
= 75°C
C
THD+N at 10%
8
W
2
1
2
W
0.5
3 W
2
W
0.2
100
80
60
40
20
0
0.1
4
W
0.05
3
W
0.02
8 W
6 8 10 12 14 16 18 20 22 24 26 28 30
0.01
4
W
0.005
0
2
4
20m 100m 200m
1
2
5 10 20 50 100 300
PVDD - Supply Voltage - V
P
- Output Power - W
O
Figure 11.
Figure 12.
SYSTEM OUTPUT POWER
vs
CASE TEMPERATURE
260
240
220
200
2 W
180
160
140
120
100
80
3 W
4
W
60
8 W
40
THD+N at 10%
20
0
10 20 30 40 50 60 70 80 90 100 110 120
- Case Temperature - °C
T
C
Figure 13.
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APPLICATION INFORMATION
PCB Material Recommendation
FR-4 Glass Epoxy material with 2 oz. (70 µm) is recommended for use with the TAS5342A. The use of this
material can provide for higher power output, improved thermal performance, and better EMI margin (due to
lower PCB trace inductance.
PVDD Capacitor Recommendation
The large capacitors used in conjunction with each full-birdge, are referred to as the PVDD Capacitors. These
capacitors should be selected for proper voltage margin and adequate capacitance to support the power
requirements. In practice, with a well designed system power supply, 1000 µF, 50-V will support more
applications. The PVDD capacitors should be low ESR type because they are used in a circuit associtated with
high-speed switching.
Decoupling Capacitor Recommendations
In order to design an amplifier that has robust performance, passes regulatory requirements, and exhibits good
audio performance, good quality decoupling capacitors should be used. In practice, X7R should be used in this
application.
The voltage of the decoupling capactors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the
selection of the 0.1µF that is placed on the power supply to each half-bridge. It must withstand the voltage
overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the ripple
current created by high power power output. A minimum voltage rating of 50-V is required for use with a 31.5-V
power supply.
System Design Recommendations
The following schematics and PCB layouts illustrate "best practices" in the use of the TAS5342A.
GVDD (+12 V)
PVDD
2.2 W
2.2 W
3.3 W
470 µF
50 V
100 nF
GND
100 nF
10 nF
50 V
TAS5342ADDV
GVDD_A
GND
GND
GVDD_B
GND
10 µH
Microcontroller
I2C
BST_A
NC
OTW
33 nF 25 V
GND
3.3 W
NC
1 nF
50 V
PVDD_A
PVDD_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
PVDD_D
PVDD_D
NC
NC
10 nF
50 V
100 nF
50 V
SD
100 nF
50 V
PWM1_P
PWM_A
RESET_AB
PWM_B
OC_ADJ
GND
470 nF
VALID
100 nF
50 V
10 nF
50 V
GND
GND
100 nF
50 V
PWM1_M
1 nF
50 V
27 k
GND
3.3 W
10 µH
10 µH
33 nF 25 V
GND
AGND
VREG
M3
25V
33 nF
3.3 W
100 nF
1 nF
50 V
M2
100 nF
50 V
10 nF
50 V
100 nF
50 V
GND
M1
PWM2_P
PWM2_M
PWM_C
RESET_CD
PWM_D
NC
470 nF
10 nF
50 V
100 nF
50 V
GND
100 nF
50 V
1 nF
50 V
GND
GND
3.3 W
NC
10 µH
TAS5508/18
0 W
GND
BST_D
GVDD_D
VDD
33 nF 25 V
100 nF
GVDD_C
PVDD
3.3 W
GND
470 µF
50 V
10 nF
50 V
100 nF
GND
100 nF
2.2 W
2.2 W
GND
GND
GVDD (+12 V)
VDD (+12 V)
Figure 14. Typical Differential (2N) BTL Application With AD Modulation Filters
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GVDD (+12 V)
PVDD
2.2 W
2.2 W
3.3 W
470 µF
50 V
100 nF
GND
100 nF
10 nF
50 V
TAS5342ADDV
GVDD_A
GND
GND
GVDD_B
GND
10 µH
Microcontroller
I2C
BST_A
NC
OTW
33 nF 25 V
GND
3.3 W
NC
1 nF
50 V
PVDD_A
PVDD_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
PVDD_D
PVDD_D
NC
NC
10 nF
50 V
100 nF
50 V
SD
100 nF
50 V
PWM1_P
VALID
PWM_A
RESET_AB
PWM_B
OC_ADJ
GND
470 nF
100 nF
50 V
GND
10 nF
50 V
GND
100 nF
50 V
1 nF
50 V
27 k
GND
3.3 W
10 µH
10 µH
33 nF 25 V
GND
AGND
VREG
M3
25V
33 nF
3.3 W
100 nF
1 nF
50 V
M2
100 nF
50 V
10 nF
50 V
100 nF
50 V
GND
M1
PWM2_P
PWM_C
RESET_CD
PWM_D
NC
470 nF
10 nF
50 V
100 nF
50 V
GND
100 nF
50 V
1 nF
50 V
GND
GND
3.3 W
NC
10 µH
TAS5508/18
0 W
GND
BST_D
GVDD_D
VDD
33 nF 25 V
GVDD_C
100 nF
PVDD
3.3 W
GND
470 µF
50 V
10 nF
50 V
100 nF
GND
100 nF
2.2 W
2.2 W
GND
GND
GVDD (+12 V)
VDD (+12 V)
Figure 15. Typical Non-Differential (1N) BTL Application With AD Modulation Filters
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GVDD (+12V)
PVDD
2.2R
2.2R
3.3R
470uF
50V
100nF
100nF
10nF
50V
TAS5342ADDV
GND
GND
1
2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
GVDD_B
OTW
GVDD_A
BST_A
Microcontroller
20uH
GND
1
2
1
2
A
33nF 25V
GND
3
NC
NC
I2C
4
NC
PVDD_A
PVDD_A
OUT_A
GND_A
GND_B
OUT_B
GND
5
SD
100nF
50V
PWM1_P
6
PWM_A
RESET_AB
PWM_B
OC_ADJ
GND
7
VALID
GND
8
PWM2_P
100nF
50V
22k
1
1
2
2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
PVDD_B
BST_B
33nF 25V
20uH
20uH
GND
1
2
1
1
2
2
B
AGND
VREG
M3
1
2
C
BST_C
100nF
33nF 25V
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
PVDD_D
PVDD_D
NC
M2
100nF
50V
GND
M1
PWM3_P
PWM4_P
PWM_C
RESET_CD
PWM_D
NC
100nF
50V
TAS5508/18
NC
GND
GND
20uH
0R
1
2
1
2
1
2
D
VDD
BST_D
33nF 25V
100nF
GVDD_C
GVDD_D
PVDD
3.3R
GND
470uF
50V
10nF
50V
100nF
100nF
2.2R
2.2R
GND
GND
GND
VDD (+12V)
GVDD (+12V)
10nF
50V
10nF
50V
1
2
1
2
GND
GND
3.3R
3.3R
A
B
100nF
50V
100nF
50V
1uF
1uF
10k
10k
PVDD
PVDD
10k
1%
10k
1%
470uF
50V
100nF
50V
GND
470uF
50V
100nF
50V
GND
10k
1%
10k
1%
470uF
50V
470uF
50V
3.3R
1
3.3R
1
2
2
GND
GND
50V
50V
10nF
10nF
GND
GND
10nF
50V
10nF
50V
1
2
1
2
GND
GND
3.3R
3.3R
C
D
100nF
50V
100nF
50V
1uF
1uF
10k
10k
PVDD
PVDD
10k
1%
10k
1%
470uF
50V
100nF
50V
GND
470uF
50V
100nF
50V
GND
10k
1%
10k
1%
470uF
50V
470uF
50V
3.3R
3.3R
1
2
1
2
GND
GND
50V
10nF
50V
10nF
GND
GND
Figure 16. Typical SE Application
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GVDD (+12 V)
PVDD
2.2 W
2.2 W
3.3 W
470 µF
50 V
100 nF
GND
100 nF
10 nF
50 V
TAS5342ADDV
GVDD_A
GND
GND
GVDD_B
GND
10 µH
Microcontroller
I2C
BST_A
NC
OTW
33 nF 25 V
GND
NC
PVDD_A
PVDD_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
PVDD_D
PVDD_D
NC
NC
SD
100 nF
PWM1_P
PWM_A
RESET_AB
PWM_B
OC_ADJ
GND
VALID
3.3 W
GND
100 nF
50 V
PWM1_M
1 nF
50 V
27 k
1R
10 nF
50 V
100 nF
50 V
10 µH
10 µH
33 nF 25 V
GND
AGND
VREG
M3
1 µF
100 nF
50 V
10 nF
50 V
25V
33 nF
1 nF
50 V
100 nF
GND
M2
100 nF
50 V
GND
3.3 W
M1
PWM_C
RESET_CD
PWM_D
NC
100 nF
50 V
GND
NC
10 µH
TAS5508/18
0 W
GND
BST_D
GVDD_D
VDD
33 nF 25 V
100 nF
GVDD_C
PVDD
3.3 W
GND
470 µF
50 V
10 nF
50 V
100 nF
GND
100 nF
2.2 W
2.2 W
GND
GND
GVDD (+12 V)
VDD (+12 V)
Figure 17. Typical Differential (2N) PBTL Application With AD Modulation Filters
GVDD (+12 V)
PVDD
2.2 W
2.2 W
3.3 W
470 µF
50 V
100 nF
GND
100 nF
10 nF
50 V
TAS5342ADDV
GVDD_A
GND
GND
GVDD_B
GND
10 µH
Microcontroller
I2C
BST_A
NC
OTW
33 nF 25 V
GND
NC
PVDD_A
PVDD_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
PVDD_D
PVDD_D
NC
NC
SD
100 nF
50 V
PWM1_P
PWM_A
RESET_AB
PWM_B
OC_ADJ
GND
VALID
3.3 W
GND
100 nF
50 V
PWM1_M
1 nF
50 V
27 k
1R
10 nF
50 V
100 nF
50 V
10 µH
10 µH
33 nF 25 V
GND
AGND
VREG
M3
1 µF
100 nF
50 V
10 nF
50 V
25V
33 nF
1 nF
50 V
100 nF
GND
M2
100 nF
50 V
GND
3.3 W
M1
PWM_C
RESET_CD
PWM_D
NC
100 nF
50 V
GND
NC
10 µH
TAS5508/18
0 W
GND
BST_D
GVDD_D
VDD
33 nF 25 V
100 nF
GVDD_C
PVDD
3.3 W
GND
470 µF
50 V
10 nF
50 V
100 nF
GND
100 nF
2.2 W
2.2 W
GND
GND
GVDD (+12 V)
VDD (+12 V)
Figure 18. Typical Non-Differential (1N) PBTL Application
18
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THEORY OF OPERATION
Special attention should be paid to the power-stage
POWER SUPPLIES
power supply; this includes component selection,
PCB placement, and routing. As indicated, each
half-bridge has independent power-stage supply pins
(PVDD_X). For optimal electrical performance, EMI
compliance, and system reliability, it is important that
each PVDD_X pin is decoupled with a 100-nF
ceramic capacitor placed as close as possible to
each supply pin. It is recommended to follow the PCB
layout of the TAS5342A reference design. For
additional information on recommended power supply
and required components, see the application
diagrams given previously in this data sheet.
To facilitate system design, the TAS5342A needs
only a 12-V supply in addition to the (typical) 31.5-V
power-stage supply. An internal voltage regulator
provides suitable voltage levels for the digital and
low-voltage analog circuitry. Additionally, all circuitry
requiring a floating voltage supply, e.g., the high-side
gate drive, is accommodated by built-in bootstrap
circuitry requiring only an external capacitor for each
half-bridge.
In order to provide outstanding electrical and
acoustical characteristics, the PWM signal path
including gate drive and output stage is designed as
identical, independent half-bridges. For this reason,
each half-bridge has separate gate drive supply
(GVDD_X), bootstrap pins (BST_X), and power-stage
supply pins (PVDD_X). Furthermore, an additional pin
(VDD) is provided as supply for all common circuits.
Although supplied from the same 12-V source, it is
highly recommended to separate GVDD_A,
GVDD_B, GVDD_C, GVDD_D, and VDD on the
printed-circuit board (PCB) by RC filters (see
application diagram for details). These RC filters
provide the recommended high-frequency isolation.
Special attention should be paid to placing all
decoupling capacitors as close to their associated
pins as possible. In general, inductance between the
power supply pins and decoupling capacitors must be
avoided. (See reference board documentation for
additional information.)
The 12-V supply should be from
a low-noise,
low-output-impedance voltage regulator. Likewise, the
31.5-V power-stage supply is assumed to have low
output impedance and low noise. The power-supply
sequence is not critical as facilitated by the internal
power-on-reset circuit. Moreover, the TAS5342A is
fully protected against erroneous power-stage turnon
due to parasitic gate charging. Thus, voltage-supply
ramp rates (dV/dt) are non-critical within the specified
range (see the Recommended Operating Conditions
section of this data sheet).
SYSTEM POWER-UP/POWER-DOWN
SEQUENCE
Powering Up
The TAS5342A does not require
a
power-up
sequence. The outputs of the H-bridges remain in a
high-impedance state until the gate-drive supply
voltage (GVDD_X) and VDD voltage are above the
undervoltage protection (UVP) voltage threshold (see
the Electrical Characteristics section of this data
sheet). Although not specifically required, it is
recommended to hold RESET_AB and RESET_CD in
a low state while powering up the device. This allows
an internal circuit to charge the external bootstrap
capacitors by enabling a weak pulldown of the
half-bridge output.
For a properly functioning bootstrap circuit, a small
ceramic capacitor must be connected from each
bootstrap pin (BST_X) to the power-stage output pin
(OUT_X). When the power-stage output is low, the
bootstrap capacitor is charged through an internal
diode connected between the gate-drive power--
supply pin (GVDD_X) and the bootstrap pin. When
the power-stage output is high, the bootstrap
capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply
for the high-side gate driver. In an application with
PWM switching frequencies in the range from 352
kHz to 384 kHz, it is recommended to use 33-nF
ceramic capacitors, size 0603 or 0805, for the
bootstrap supply. These 33-nF capacitors ensure
sufficient energy storage, even during minimal PWM
duty cycles, to keep the high-side power stage FET
(LDMOS) fully turned on during the remaining part of
the PWM cycle. In an application running at a
reduced switching frequency, generally 192 kHz, the
bootstrap capacitor might need to be increased in
value.
When the TAS5342A is being used with TI PWM
modulators such as the TAS5518, no special
attention to the state of RESET_AB and RESET_CD
is required, provided that the chipset is configured as
recommended.
Powering Down
The TAS5342A does not require a power-down
sequence. The device remains fully operational as
long as the gate-drive supply (GVDD_X) voltage and
VDD voltage are above the undervoltage protection
(UVP) voltage threshold (see the Electrical
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Characteristics section of this data sheet). Although
not specifically required, it is a good practice to hold
RESET_AB and RESET_CD low during power down,
thus preventing audible artifacts including pops or
clicks.
signal using the system microcontroller and
responding to an overtemperature warning signal by,
e.g., turning down the volume to prevent further
heating of the device resulting in device shutdown
(OTE).
When the TAS5342A is being used with TI PWM
modulators such as the TAS5518, no special
attention to the state of RESET_AB and RESET_CD
is required, provided that the chipset is configured as
recommended.
To reduce external component count, an internal
pullup resistor to 3.3 V is provided on both SD and
OTW outputs. Level compliance for 5-V logic can be
obtained by adding external pullup resistors to 5 V
(see the Electrical Characteristics section of this data
sheet for further specifications).
Mid Z Sequence Compatability
DEVICE PROTECTION SYSTEM
The TAS5342A is compatable with the Mid
Z
sequence of the TAS5086 Modulator. The Mid Z
Sequence is a series of pulses that is generated by
the modulator. This sequence causes the power
stage to slowly enable its outputs as it begins to
switch.
The TAS5342A contains advanced protection circuitry
carefully designed to facilitate system integration and
ease of use, as well as to safeguard the device from
permanent failure due to a wide range of fault
conditions such as short circuits, overload,
overtemperature, and undervoltage. The TAS5342A
responds to a fault by immediately setting the power
stage in a high-impedance (Hi-Z) state and asserting
the SD pin low. In situations other than overload and
By slowly starting the PWM switching, the impulse
response created by the onset of switching is
reduced. This impulse response is the acoustic
artifact that is heard in the output transducers
(loudspeakers) and is commonly termed "click" or
"pop".
over-temperature
error
(OTE),
the
device
automatically recovers when the fault condition has
been removed, i.e., the supply voltage has increased.
The low acoustic artifact noise of the TAS5342A will
be further decreased when used in conjunction with
the TAS5086 modulator with the Mid Z Sequence
enabled.
The device will function on errors, as shown in the
following table.
BTL MODE
Local
Error Turns Off Error
PBTL MODE
SE MODE
Local
Local
The Mid Z sequence is primarily used for the
single-ended output configuration. It facilitates a
"softer" PWM output start after the split cap output
configuration is charged.
Turns Off
Error
In
Turns Off
In
A
B
C
D
In
A
B
C
D
A
B
C
D
A + B
C + D
A + B
C + D
A + B + C
+ D
ERROR REPORTING
The SD and OTW pins are both active-low,
open-drain
outputs.
Their
function
is
for
Bootstrap UVP does not shutdown according to the
table, it shutsdown the respective halfbridge.
protection-mode signaling to a PWM controller or
other system-control device.
Use of TAS5342A in High-Modulation-Index
Capable Systems
Any fault resulting in device shutdown is signaled by
the SD pin going low. Likewise, OTW goes low when
the device junction temperature exceeds 125°C (see
the following table).
This device requires at least 30 ns of low time on the
output per 384-kHz PWM frame rate in order to keep
the bootstrap capacitors charged. As an example, if
the modulation index is set to 99.2% in the TAS5508,
this setting allows PWM pulse durations down to 10
ns. This signal, which does not meet the 30-ns
requirement, is sent to the PWM_X pin and this
low-state pulse time does not allow the bootstrap
capacitor to stay charged. The TAS5342A device
requires limiting the TAS5508 modulation index to
97.7% to keep the bootstrap capacitor charged under
all signals and loads.
SD OTW
DESCRIPTION
Overtemperature (OTE) or overload (OLP) or
undervoltage (UVP)
0
0
1
0
1
0
Overload (OLP) or undervoltage (UVP)
Junction temperature higher than 125°C
(overtemperature warning)
Junction temperature lower than 125°C and no
OLP or UVP faults (normal operation)
1
1
Note that asserting either RESET_AB or RESET_CD
low forces the SD signal high, independent of faults
being present. TI recommends monitoring the OTW
The TAS5342A contains a bootstrap capacitor under
voltage protection circuit (BST_UVP) that monitors
the voltage on the bootstrap capacitors. When the
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voltage on the bootstrap capacitors is less than
required for proper control of the High-Side
MOSFETs, the device will initiate bootstrap capacitor
recharge sequences until the bootstrap capacitors are
properly charged for robust operation. This function
may be activated with PWM pulses less than 30 nS.
In general, it is recommended to follow closely the
external component selection and PCB layout as
given in the Application section.
For added flexibility, the OC threshold is
programmable within a limited range using a single
external resistor connected between the OC_ADJ pin
and AGND. (See the Electrical Characteristics section
of this data sheet for information on the correlation
between programming-resistor value and the OC
Therefore, TI strongly recommends using a TI PWM
processor, such as TAS5518, TAS5086 or TAS5508,
with the modulation index set at 97.7% to interface
with TAS5342A.
threshold.) It should be noted that
a properly
functioning overcurrent detector assumes the
presence of a properly designed demodulation filter at
the power-stage output. Short-circuit protection is not
provided directly at the output pins of the power stage
but only on the speaker terminals (after the
demodulation filter). It is required to follow certain
guidelines when selecting the OC threshold and an
appropriate demodulation inductor:
Overcurrent (OC) Protection With Current
Limiting and Overload Detection
The device has independent, fast-reacting current
detectors with programmable trip threshold (OC
threshold) on all high-side and low-side power-stage
FETs. See the following table for OC-adjust resistor
values. The detector outputs are closely monitored by
two protection systems. The first protection system
controls the power stage in order to prevent the
output current from further increasing, i.e., it performs
a current-limiting function rather than prematurely
shutting down during combinations of high-level
music transients and extreme speaker load
impedance drops. If the high-current situation
persists, i.e., the power stage is being overloaded, a
OC-Adjust Resistor Values Max. Current Before OC Occurs
(kΩ)
(A), TC=75°C
27
10.1
9.1
33
47
7.1
The reported max peak current in the table above is
measured with continuous current in 1 Ω, one
channel active and the other one muted.
second protection system triggers
a
latching
shutdown, resulting in the power stage being set in
the high-impedance (Hi-Z) state. Current limiting and
overload protection are independent for half-bridges
A and B and, respectively, C and D. That is, if the
bridge-tied load between half-bridges A and B causes
an overload fault, only half-bridges A and B are shut
down.
Pin-To-Pin Short Circuit Protection System
(PPSC)
The PPSC detection system protects the device from
permanent damage in the case that a power output
pin (OUT_X) is shorted to GND_X or PVDD_X. For
comparison the OC protection system detects an over
current after the demodulation filter where PPSC
detects shorts directly at the pin before the filter.
PPSC detection is performed at startup i.e. when
VDD is supplied, consequently a short to either
GND_X or PVDD_X after system startup will not
activate the PPSC detection system. When PPSC
detection is activated by a short on the output, all half
bridges are kept in a Hi-Z state until the short is
removed, the device then continues the startup
sequence and starts switching. The detection is
controlled globally by a two step sequence. The first
step ensures that there are no shorts from OUT_X to
GND_X, the second step tests that there are no
shorts from OUT_X to PVDD_X. The total duration of
this process is roughly proportional to the capacitance
of the output LC filter. The typical duration is < 15
ms/µF. While the PPSC detection is in progress, SD
is kept low, and the device will not react to changes
applied to the RESET pins. If no shorts are present
the PPSC detection passes, and SD is released. A
device reset will not start a new PPSC detection.
•
For the lowest-cost bill of materials in terms of
component selection, the OC threshold measure
should be limited, considering the power output
requirement and minimum load impedance.
Higher-impedance loads require
threshold.
a lower OC
•
The demodulation-filter inductor must retain at
least 5 µH of inductance at twice the OC threshold
setting.
Unfortunately, most inductors have decreasing
inductance with increasing temperature and
increasing current (saturation). To some degree, an
increase in temperature naturally occurs when
operating at high output currents, due to core losses
and the dc resistance of the inductor's copper
winding. A thorough analysis of inductor saturation
and thermal properties is strongly recommended.
Setting the OC threshold too low might cause issues
such as lack of enough output power and/or
unexpected shutdowns due to too-sensitive overload
detection.
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PPSC detection is enabled in BTL and PBTL output
configurations, the detection is not performed in SE
mode. To make sure not to trip the PPSC detection
system it is recommended not to insert resistive load
to GND_X or PVDD_X.
VDD or GVDD_X pin results in all half-bridge outputs
immediately being set in the high-impedance (Hi-Z)
state and SD being asserted low. The device
automatically resumes operation when all supply
voltages have increased above the UVP threshold.
Overtemperature Protection
DEVICE RESET
The
TAS5342A
has
a
two-level
Two reset pins are provided for independent control
of half-bridges A/B and C/D. When RESET_AB is
asserted low, all four power-stage FETs in half--
bridges A and B are forced into a high-impedance
(Hi-Z) state. Likewise, asserting RESET_CD low
forces all four power-stage FETs in half-bridges C
and D into a high-impedance state. Thus, both reset
pins are well suited for hard-muting the power stage if
needed.
temperature-protection system that asserts an
active-low warning signal (OTW) when the device
junction temperature exceeds 125°C (nominal) and, if
the device junction temperature exceeds 155°C
(nominal), the device is put into thermal shutdown,
resulting in all half-bridge outputs being set in the
high-impedance (Hi-Z) state and SD being asserted
low. OTE is latched in this case. To clear the OTE
latch, either RESET_AB or RESET_CD must be
asserted. Thereafter, the device resumes normal
operation.
In BTL modes, to accommodate bootstrap charging
prior to switching start, asserting the reset inputs low
enables weak pulldown of the half-bridge outputs. In
the SE mode, the weak pulldowns are not enabled,
and it is therefore recommended to ensure bootstrap
capacitor charging by providing a low pulse on the
PWM inputs when reset is asserted high.
Undervoltage Protection (UVP) and Power-On
Reset (POR)
The UVP and POR circuits of the TAS5342A fully
protect the device in any power-up/down and
brownout situation. While powering up, the POR
circuit resets the overload circuit (OLP) and ensures
that all circuits are fully operational when the
GVDD_X and VDD supply voltages reach stated in
the Electrical Characteristics Table. Although
GVDD_X and VDD are independently monitored, a
supply voltage drop below the UVP threshold on any
Asserting either reset input low removes any fault
information to be signalled on the SD output, i.e., SD
is forced high.
A rising-edge transition on either reset input allows
the device to resume operation after an overload
fault. To ensure thermal reliability, the rising edge of
reset must occur no sooner than 4ms after the falling
edge of SD.
22
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PACKAGE MATERIALS INFORMATION
www.ti.com
22-Dec-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TAS5342ADDVR
HTSSOP DDV
44
2000
330.0
24.4
8.6
15.6
1.8
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Dec-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP DDV 44
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 41.0
TAS5342ADDVR
2000
Pack Materials-Page 2
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