TAS5414B-Q1 [TI]
FOUR-CHANNEL AUTOMOTIVE DIGITAL AMPLIFIERS; 四通道车载数字放大器
| 型号： | TAS5414B-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | FOUR-CHANNEL AUTOMOTIVE DIGITAL AMPLIFIERS |
| 文件： | 总39页 (文件大小：1009K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TAS5414B-Q1
TAS5424B-Q1
www.ti.com
SLOS673 –DECEMBER 2011
FOUR-CHANNEL AUTOMOTIVE DIGITAL AMPLIFIERS
Check for Samples: TAS5414B-Q1, TAS5424B-Q1
1
FEATURES
•
•
•
•
•
TAS5414B-Q1 – Single-Ended Input
•
•
•
36-Pin PSOP3 (DKD) Power SOP Package With
Heat Slug Up for the TAS5414B-Q1
TAS5424B-Q1 – Differential Input
44-Pin PSOP3 (DKD) Power SOP Package With
Heat Slug Up for the TAS5424B-Q1
Four-Channel Digital Power Amplifier
Four Analog Inputs, Four BTL Power Outputs
Typical Output Power at 10% THD+N
44-Pin PSOP3 (DKE) Low-Standoff Power SOP
Package With Heat Slug Up for the
TAS5424B-Q1
–
–
–
–
28 W/Ch Into 4 Ω at 14.4 V
50 W/Ch Into 2 Ω at 14.4 V
79 W/Ch Into 4 Ω at 24 V
•
64-Pin QFP (PHD) Power Package With Heat
Slug Up for TAS5414B-Q1
150 W/Ch Into 2 Ω at 24 V (PBTL)
•
•
•
•
Designed for Automotive EMC Requirements
Qualified According to AEC-Q100
•
Channels Can Be Paralleled (PBTL) for High
Current Applications
ISO9000:2002 TS16949 Certified
•
•
THD+N < 0.02%, 1 kHz, 1 W Into 4 Ω
–40°C to 105°C Ambient Temperature Range
Patented Pop- and Click-Reduction
Technology
APPLICATIONS
–
–
Soft Muting With Gain Ramp Control
Common-Mode Ramping
•
OEM/Retail Head Units and Amplifier Modules
Where Feature Densities and System
Configurations Require Reduction in Heat
From the Audio Power Amplifier
•
•
•
•
Patented AM Interference Avoidance
Patented Cycle-by-Cycle Current Limit
75-dB PSRR
Four-Address I2C Serial Interface for Device
Configuration and Control
DESCRIPTION
The
TAS5414B-Q1
and
TAS5424B-Q1
are
four-channel digital audio amplifiers designed for use
in automotive head units and external amplifier
modules. They provide four channels at 23 W
continuously into 4 Ω at less than 1% THD+N from a
14.4-V supply. Each channel can also deliver 38 W
into 2 Ω at 1% THD+N. The TAS5414B-Q1 uses
single-ended analog inputs, while the TAS5424B-Q1
employs differential inputs for increased immunity to
common-mode system noise. The digital PWM
topology of the device provides dramatic
improvements in efficiency over traditional linear
amplifier solutions. This reduces the power dissipated
by the amplifier by a factor of ten under typical music
playback conditions. The device incorporates all the
functionality needed to perform in the demanding
OEM applications area. They have built-in load
diagnostic functions for detecting and diagnosing
misconnected outputs to help to reduce test time
during the manufacturing process.
•
•
Channel Gains: 12-dB, 20-dB, 26-dB, 32-dB
Load Diagnostic Functions:
–
–
–
Output Open and Shorted Load
Output-to-Power and -to-Ground Shorts
Patented Tweeter Detection
•
Protection and Monitoring Functions:
–
–
–
Short-Circuit Protection
Load-Dump Protection to 50 V
Fortuitous Open Ground and Power
Tolerant
–
Patented Output DC Level Detection While
Music Playing
–
–
–
Over-temperature Protection
Over- and Undervoltage Conditions
Clip Detection
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
TAS5414B-Q1
TAS5424B-Q1
SLOS673 –DECEMBER 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
2
Copyright © 2011, Texas Instruments Incorporated
TAS5414B-Q1
TAS5424B-Q1
www.ti.com
SLOS673 –DECEMBER 2011
PIN ASSIGNMENTS AND FUNCTIONS
The pin assignments are shown as follows.
TAS5414B
DKD Package
(Top View)
TAS5424B
DKD Package
(Top View)
OSC_SYNC
OSC_SYNC
I2C_ADDR
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
PVDD
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
PVDD
I2C_ADDR
SDA
2
PVDD
2
PVDD
OUT1_M
OUT1_P
3
SDA
SCL
3
PVDD
OUT1_M
OUT1_P
SCL
4
4
5
GND
5
FAULT
MUTE
FAULT
MUTE
GND
OUT2_M
OUT2_P
CPC_TOP
6
6
GND
7
7
GND
STANDBY
D_BYP
OUT2_M
OUT2_P
CPC_TOP
8
8
STANDBY
D_BYP
CLIP_OTW
GND
9
CP
9
CPC_BOT
10
11
12
13
14
15
16
17
18
CLIP_OTW
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
GND
GND
CP
OUT3_M
OUT3_P
CP_BOT
REXT
A_BYP
IN1_P
IN2_P
IN_M
GND
REXT
GND
A_BYP
IN1_P
IN1_M
IN2_P
IN2_M
IN3_P
IN3_M
IN4_P
IN4_M
OUT3_M
OUT3_P
GND
OUT4_M
OUT4_P
GND
IN3_P
IN4_P
PVDD
PVDD
GND
OUT4_M
OUT4_P
PVDD
PVDD
PVDD
Copyright © 2011, Texas Instruments Incorporated
3
TAS5414B-Q1
TAS5424B-Q1
SLOS673 –DECEMBER 2011
www.ti.com
TAS5414B
PHD Package
(Top View)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
OUT1_M
OUT1_P
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
FAULT
MUTE
GND
2
3
GND
OUT2_M
OUT2_P
4
STANDBY
D_BYP
5
CLIP_OTW
GND
6
GND
CPC_TOP
7
GND
8
CP
CP_BOT
GND
9
REXT
10
11
12
13
14
15
16
GND
A_BYP
GND
OUT3_M
OUT3_P
GND
IN1_P
GND
GND
IN2_P
OUT4_M
OUT4_P
GND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
4
Copyright © 2011, Texas Instruments Incorporated
TAS5414B-Q1
TAS5424B-Q1
www.ti.com
SLOS673 –DECEMBER 2011
Table 1. PIN FUNCTIONS
PIN
DKD/DKE
PACKAGE
PHD PACKAGE
TYPE(1)
DESCRIPTION
NAME
TAS54 TAS54
14B-Q1 24B-Q1
TAS5414B-Q1
NO.
NO.
NO.
A_BYP
13
14
11
6
PBY
DO
Bypass pin for the AVDD analog regulator
Reports CLIP, OTW, or both. It also reports tweeter detection during
tweeter mode. Open-Drain.
CLIP_OTW
9
10
34
Top of main storage capacitor for charge pump (bottom goes to
PVDD)
CP
28
41
CP
CPC_BOT
CPC_TOP
D_BYP
27
29
8
33
35
9
40
42
5
CP
CP
Bottom of flying capacitor for charge pump
Top of flying capacitor for charge pump
PBY
DO
Bypass pin for DVDD regulator output
FAULT
5
5
1
Global fault output (open drain): UV, OV, OTSD, OCSD, DC
3, 7, 8, 9, 12, 14,
16, 17, 21, 22, 23,
12, 28, 24, 25, 26, 30, 31,
29, 32, 32, 35, 38, 39, 43,
38, 39 46, 49, 50, 51, 55,
56, 57, 58, 59, 60
7, 11,
10, 11,
23, 26,
32
GND
GND
Ground
I2C_ADDR
IN1_M
2
N/A
14
N/A
15
N/A
17
N/A
18
16
6
2
16
15
18
17
20
19
22
21
N/A
6
62
N/A
13
N/A
15
N/A
19
N/A
20
18
2
AI
AI
I2C address bit
Inverting analog input for channel 1 (TAS5424B-Q1 only)
Non-inverting analog input for channel 1
Inverting analog input for channel 2 (TAS5424B-Q1 only)
Non-inverting analog input for channel 2
Inverting analog input for channel 3 (TAS5424B-Q1 only)
Non-inverting analog input for channel 3
Inverting analog input for channel 4 (TAS5424B-Q1 only)
Non-inverting analog input for channel 4
Signal return for the 4 analog channel inputs (TAS5414B-Q1 only)
Gain ramp control: mute (low), play (high)
Oscillator input from master or output to slave amplifiers
– polarity output for bridge 1
IN1_P
AI
IN2_M
AI
IN2_P
AI
IN3_M
AI
IN3_P
AI
IN4_M
AI
IN4_P
AI
IN_M
ARTN
AI
MUTE
OSC_SYNC
OUT1_M
OUT1_P
OUT2_M
OUT2_P
OUT3_M
OUT3_P
OUT4_M
OUT4_P
1
1
61
48
47
45
44
37
36
34
33
DI/DO
PO
PO
PO
PO
PO
PO
PO
PO
34
33
31
30
25
24
22
21
41
40
37
36
31
30
27
26
+ polarity output for bridge 1
– polarity output for bridge 2
+ polarity output for bridge 2
– polarity output for bridge 3
+ polarity output for bridge 3
– polarity output for bridge 4
+ polarity output for bridge 4
23, 24,
25, 42,
43, 44
19, 20,
35, 36
27, 28, 29, 52, 53,
54
PVDD
PWR
PVDD supply
REXT
SCL
12
4
13
4
10
64
63
4
AI
DI
Precision resistor pin to set analog reference
I2C clock input from system I2C master
I2C data I/O for communication with system I2C master
SDA
3
3
DI/DO
DI
STANDBY
7
8
Active-low STANDBY pin. Standby (low), power up (high)
(1) DI = digital input, DO = digital output, AI = analog input, ARTN = analog signal return, PWR = power supply, PBY = power bypass, PO =
power output, GND = ground, CP = charge pump.
Copyright © 2011, Texas Instruments Incorporated
5
TAS5414B-Q1
TAS5424B-Q1
SLOS673 –DECEMBER 2011
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE
–0.3 to 30
–1 to 50
15
UNIT
V
PVDD
DC supply voltage range
Relative to GND
PVDDMAX
PVDDRAMP
IPVDD
Pulsed supply voltage range
t ≤ 100 ms exposure
V
Supply voltage ramp rate
V/ms
A
Externally imposed dc supply current per PVDD or GND pin
Pulsed supply current per PVDD pin (one shot)
Maximum allowed dc current per output pin
Pulsed output current per output pin (single pulse)
Maximum current, all digital and analog input pins(2)
Maximum current on MUTE pin
±12
IPVDD_MAX
IO
t < 100 ms
17
A
±13.5
±17
A
(1)
IO_MAX
t < 100 ms
A
IIN_MAX
DC or pulsed
DC or pulsed
±1
mA
mA
mA
IMUTE_MAX
IIN_ODMAX
±20
Maximum sink current for open-drain pins
7
Input voltage range for pin relative to GND (SCL, SDA,
I2C_ADDR pins)
Supply voltage range:
6V < PVDD < 24 V
VLOGIC
–0.3 to 6
V
Supply voltage range:
6 V < PVDD < 24 V
VMUTE
Voltage range for MUTE pin relative to GND
Input voltage range for STANDBY pin
–0.3 to 7.5
–0.3 to 5.5
V
V
Supply voltage range:
6 V < PVDD < 24 V
VSTANDBY
Supply voltage range:
6 V < PVDD < 24 V
VOSC_SYNC
VGND
Input voltage range for OSC_SYNC pin relative to GND
Maximum voltage between GND pins
–0.3 to 3.6
±0.3
V
V
Maximum ac-coupled input voltage for TAS5414B-Q1(2)
analog input pins
,
Supply voltage range:
6 V < PVDD < 24 V
VAIN_AC_MAX_5414
1.9
Vrms
Maximum ac-coupled differential input voltage for
TAS5424B-Q1(2), analog input pins
Supply voltage range:
6 V < PVDD < 24 V
VAIN_AC_MAX_5424
3.8
Vrms
TJ
Maximum operating junction temperature range
Storage temperature range
–55 to 150
–55 to 150
°C
°C
Tstg
(1) Pulsed current ratings are maximum survivable currents externally applied to the device. High currents may be encountered during
reverse battery, fortuitous open ground, and fortuitous open supply fault conditions.
(2) See Application Information section for information on analog input voltage and ac coupling.
THERMAL CHARACTERISTICS
PARAMETER
VALUE (Typical)
UNIT
Junction-to-case (heat slug) thermal
resistance, DKD package
RθJC
RθJC
RθJA
1.0
Junction-to-case (heat slug) thermal
resistance, PHD package
1.2
°C/W
This device is not intended to be used without a heatsink. Therefore, RθJA
is not specified. See the Thermal Information section.
Junction-to-ambient thermal resistance
Exposed pad dimensions, DKD package
Exposed pad dimensions, PHD package
13.8 × 5.8
8 × 8
mm
6
Copyright © 2011, Texas Instruments Incorporated
TAS5414B-Q1
TAS5424B-Q1
www.ti.com
SLOS673 –DECEMBER 2011
ELECTROSTATIC DISCHARGE (ESD)
PARAMETER
Package
Pins
VALUE
UNIT
(Typical)
Human Body Model
(HBM)
All
All
3000
AEC-Q100-002
Corner Pins excluding OSC_SYNC
1000
500
400
750
600
400
150
100
DKD/DKE
PHD
All other pins (including OSC_SYNC) except CP pin
CP Pin (Non-Corner Pin)
Charged Device Model
(CDM)
AEC-Q100-011
V
Corner Pins excluding SCL
All Pins (including SCL) except CP and CP_Top
CP and CP_Top Pins
DKD/DKE
PHD
Machine Model (MM)
AEC-Q100-003
RECOMMENDED OPERATING CONDITIONS(1)
MIN
6
TYP
MAX
UNIT
V
PVDDOP
VAIN_5414
VAIN_5424
TA
DC supply voltage range relative to GND
Analog audio input signal level (TAS5414B-Q1)
Analog audio input signal level (TAS5424B-Q1)
Ambient temperature
14.4
24
0.25–1(3)
0.5–2(3)
105
(2)
(2)
AC-coupled input voltage
AC-coupled input voltage
0
Vrms
Vrms
°C
0
–40
An adequate heat sink is required
to keep TJ within specified range.
TJ
Junction temperature
–40
115
°C
RL
Nominal speaker load impedance
2
3
4
Ω
VPU
Pullup voltage supply (for open-drain logic outputs)
3.3 or 5
5.5
50
10
V
Resistor connected between
open-drain logic output and VPU
supply
RPU_EXT
RPU_I2C
RI2C_ADD
External pullup resistor on open-drain logic outputs
I2C pullup resistance on SDA and SCL pins
10
1
kΩ
kΩ
4.7
20
Total resistance of voltage divider for I2C address
slave 1 or slave 2, connected between D_BYP and
GND pins
10
50
kΩ
RREXT
CD_BYP , CA_BYP
COUT
External resistance on REXT pin
1% tolerance required
19.8
10
20.2
120
680
kΩ
nF
nF
External capacitance on D_BYP and A_BYP pins
External capacitance to GND on OUT_X pins
150
External capacitance to analog input pin in series
with input signal
CIN
0.47
μF
CFLY
Flying capacitor on charge pump
Charge pump capacitor
0.47
0.47
100
1
1
1.5
1.5
μF
μF
nF
pF
CP
50V needed for Load Dump
CMUTE
MUTE pin capacitor
220
75
1000
COSCSYNC_MAX
Allowed loading capacitance on OSC_SYNC pin
(1) The Recommended Operating Conditions table specifies only that the device is functional in the given range. See the Electrical
Characteristics table for specified performance limits.
(2) Signal input for full unclipped output with gains of 32 dB, 26 dB, 20 dB, and 12 dB
(3) Maximum recommended input voltage is determined by the gain setting.
Copyright © 2011, Texas Instruments Incorporated
7
TAS5414B-Q1
TAS5424B-Q1
SLOS673 –DECEMBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.4 V, RL = 4 Ω, fS = 417 kHz, Pout = 1 W/ch, Rext = 20 kΩ,
AES17 Filter, default I2C settings, master mode operation (see application diagram)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
OPERATING CURRENT
IPVDD_IDLE
All four channels in MUTE mode
170
93
2
220
mA
PVDD idle current
IPVDD_Hi-Z
All four channels in Hi-Z mode
IPVDD_STBY
PVDD standby current
STANDBY mode, TJ ≤ 85°C
10
μA
OUTPUT POWER
4 Ω, PVDD = 14.4 V, THD+N ≤ 1%, 1 kHz, Tc = 75°C
4 Ω, PVDD = 14.4 V, THD+N = 10%, 1 kHz, Tc = 75°C
4 Ω, PVDD = 24 V, THD+N = 10%, 1 kHz, Tc = 75°C
2 Ω, PVDD = 14.4 V, THD+N = 1%, 1 kHz, Tc = 75°C
2 Ω, PVDD = 14.4 V, THD+N = 10%, 1 kHz, Tc = 75°C
23
28
79
38
50
25
63
POUT
Output power per channel
W
40
PBTL 2-Ω operation, PVDD = 24 V, THD+N = 10%,
1 kHz, Tc = 75°C
150
90
PBTL 1-Ω operation, PVDD = 14.4 V, THD+N = 10%,
1 kHz, Tc = 75°C
4 channels operating, 23-W output power/ch, L = 10 μH,
TJ ≤ 85°C
EFFP
Power efficiency
90%
AUDIO PERFORMANCE
VNOISE
Noise voltage at output
Zero input, and A-weighting
60
85
100
μV
P = 1W, f = 1 kHz, Enhanced Crosstalk Enabled via I2C
(reg 0x10)
Crosstalk
Channel crosstalk
70
dB
Common-mode rejection ratio
(TAS5424B-Q1)
CMRR5424
f = 1 kHz, 1 Vrms referenced to GND, G = 26 dB
60
60
75
dB
dB
PSRR
Power supply rejection ratio
PVDD = 14.4 Vdc + 1 Vrms, f = 1 kHz
P = 1W, f = 1 kHz
75
0.02%
357
THD+N
Total harmonic distortion + noise
0.1%
378
442
530
106
336
392
470
63
Switching frequency selectable for AM interference
avoidance
fS
Switching frequency
417
kHz
500
RAIN
Analog input resistance
Internal shunt resistance on each input pin
85
kΩ
Vrms
V
AC coupled common-mode input voltage (zero
differential input)
VIN_CM
VCM_INT
Common-mode input voltage
Internal common-mode input bias voltage
1.3
Internal bias applied to IN_M pin
3.3
12
20
26
32
0
11
19
25
31
–1
13
21
27
33
1
Source impedance = 0 Ω, gain measurement taken at 1
W of power per channel
G
Voltage gain (VO/VIN
)
dB
dB
GCH
Channel-to-channel variation
Any gain commanded
PWM OUTPUT STAGE
RDSon
FET drain-to-source resistance
Output offset voltage
Not including bond wire resistance, TJ = 25°C
65
90
mΩ
VO_OFFSET
Zero input signal, G = 26 dB
±10
±50
mV
PVDD OVERVOLTAGE (OV) PROTECTION
VOV_SET
PVDD overvoltage shutdown set
PVDD overvoltage shutdown clear
24.6
24.4
26.4
25.9
28.2
27.4
V
VOV_CLEAR
PVDD UNDERVOLTAGE (UV) PROTECTION
VUV_SET
PVDD undervoltage shutdown set
PVDD undervoltage shutdown clear
4.9
6.2
5.3
6.6
5.6
7.0
V
V
VUV_CLEAR
AVDD
VA_BYP
A_BYP pin voltage
A_BYP UV voltage
6.5
4.8
5.3
V
V
V
VA_BYP_UV_SET
VA_BYP_UV_CLEAR Recovery voltage A_BYP UV
DVDD
VD_BYP
D_BYP pin voltage
3.3
V
8
Copyright © 2011, Texas Instruments Incorporated
TAS5414B-Q1
TAS5424B-Q1
www.ti.com
SLOS673 –DECEMBER 2011
ELECTRICAL CHARACTERISTICS (continued)
Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.4 V, RL = 4 Ω, fS = 417 kHz, Pout = 1 W/ch, Rext = 20 kΩ,
AES17 Filter, default I2C settings, master mode operation (see application diagram)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER-ON RESET (POR)
I2C active above this voltage
VPOR
PVDD voltage for POR
3.5
V
V
VPOR_HY
REXT
VREXT
PVDD recovery hysteresis voltage for POR
0.1
Rext pin voltage
1.27
V
CHARGE PUMP (CP)
VCPUV_SET
CP undervoltage
Recovery voltage for CP UV
4.8
4.9
V
V
VCPUV_CLEAR
OVERTEMPERATURE (OT) PROTECTION
TOTW1_CLEAR
96
112
122
128
138
TOTW1_SET
/
106
TOTW2_CLEAR
Junction temperature for overtemperature
warning
TOTW2_SET
/
116
126
136
130
132
142
152
150
148
158
168
170
TOTW3_CLEAR
°C
TOTW3_SET
/
TOTSD_CLEAR
Junction temperature for overtemperature
shutdown
TOTSD
Junction temperature for overtemperature
foldback
TFB
Per channel
CURRENT LIMITING PROTECTION
Level 1
5.5
7.3
9.0
ILIM
Current limit (load current)
A
A
Level 2 (default)
10.6
12.7
15.0
OVERCURRENT (OC) SHUTDOWN PROTECTION
Level 1
7.8
9.8
12.2
17.7
IMAX
Maximum current (peak output current)
Level 2 (default), Any short to supply, ground, or other
channels
11.9
14.8
TWEETER DETECT
ITH_TW
Load current threshold for tweeter detect
330
2
445
2.1
560
mA
A
ILIM_TW
Load current limit for tweeter detect
STANDBY MODE
VIH_STBY
STANDBY input voltage for logic-level high
STANDBY input voltage for logic-level low
STANDBY pin current
V
V
VIL_STBY
0.7
0.2
ISTBY_PIN
0.1
100
25
μA
MUTE MODE
GMUTE
MUTE pin ≤ 0.5 V + 200mS or I2C Mute Enabled
Output attenuation
dB
DC DETECT
VTH_DC_TOL
DC detect threshold tolerance
%
s
DC detect step response time for four
channels
tDCD
5.3
CLIP_OTW REPORT
CLIP_OTW pin output voltage for logic level
high (open-drain logic output)
VOH_CLIPOTW
VOL_CLIPOTW
2.4
V
V
External 47-kΩ pullup resistor to 3 V–5.5 V
CLIP_OTW pin output voltage for logic level
low (open-drain logic output)
0.5
20
CLIP_OTW signal delay when output
clipping detected
tDELAY_CLIPDET
FAULT REPORT
VOH_FAULT
μs
FAULT pin output voltage for logic-level high
(open-drain logic output)
2.4
External 47-kΩ pullup resistor to 3 V–5.5 V
V
FAULT pin output voltage for logic-level low
(open-drain logic output)
VOL_FAULT
0.5
OPEN/SHORT DIAGNOSTICS
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9
TAS5414B-Q1
TAS5424B-Q1
SLOS673 –DECEMBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.4 V, RL = 4 Ω, fS = 417 kHz, Pout = 1 W/ch, Rext = 20 kΩ,
AES17 Filter, default I2C settings, master mode operation (see application diagram)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Maximum resistance to detect a short from
OUT pin(s) to PVDD or ground
RS2P, RS2G
200
1300
1.5
Ω
Ω
Ω
Minimum load resistance to detect open
circuit
ROPEN_LOAD
RSHORTED_LOAD
Including speaker wires
300
0.5
740
1.0
Maximum load resistance to detect short
circuit
Including speaker wires
I2C ADDRESS DECODER
Time delay to latch I2C address after POR
tLATCH_I2CADDR
300
0%
μs
Voltage on I2C_ADDR pin for address 0
Voltage on I2C_ADDR pin for address 1
Voltage on I2C_ADDR pin for address 2
Voltage on I2C_ADDR pin for address 3
Connect to GND
0%
25%
55%
85%
15%
45%
35%
65%
100%
External resistors in series between D_BYP and GND as
a voltage divider
VI2C_ADDR
VD_BYP
75%
Connect to D_BYP
100%
I2C
Power-on hold time before I2C
communication
tHOLD_I2C
STANDBY high
1
ms
fSCL
SCL clock frequency
400
5.5
1.1
kHz
V
VIH_SCL
VIL_SCL
SCL pin input voltage for logic-level high
SCL pin input voltage for logic-level low
2.1
RPU_I2C = 5-kΩ pullup, supply voltage = 3.3 V or 5 V
–0.5
V
I2C read, RI2C = 5-kΩ pullup,
supply voltage = 3.3 V or 5 V
VOH_SDA
VOL_SDA
VIH_SDA
SDA pin output voltage for logic-level high
SDA pin output voltage for logic-level low
SDA pin input voltage for logic-level high
2.4
V
V
V
I2C read, 3-mA sink current
0.4
5.5
I2C write, RI2C = 5-kΩ pullup,
supply voltage = 3.3 V or 5 V
2.1
I2C write, RI2C = 5-kΩ pullup,
supply voltage = 3.3 V or 5 V
VIL_SDA
SDA pin input voltage for logic-level low
Capacitance for SCL and SDA pins
–0.5
1.1
10
V
C i
pF
OSCILLATOR
OSC_SYNC pin output voltage for
logic-level high
VOH_OSCSYNC
VOL_OSCSYNC
VIH_OSCSYNC
VIL_OSCSYNC
2.4
2
V
V
V
V
I2C_ADDR pin set to MASTER mode
I2C_ADDR pin set to SLAVE mode
OSC_SYNC pin output voltage for
logic-level low
0.5
0.8
OSC_SYNC pin input voltage for logic-level
high
OSC_SYNC pin input voltage for logic-level
low
I2C_ADDR pin set to MASTER mode, fS = 500 kHz
I2C_ADDR pin set to MASTER mode, fS = 417 kHz
I2C_ADDR pin set to MASTER mode, fS = 357 kHz
3.76
3.13
2.68
4.0
3.33
2.85
4.24
3.63
3.0
fOSC_SYNC
OSC_SYNC pin clock frequency
MHz
10
Copyright © 2011, Texas Instruments Incorporated
TAS5414B-Q1
TAS5424B-Q1
www.ti.com
SLOS673 –DECEMBER 2011
TIMING REQUIREMENTS FOR I2C INTERFACE SIGNALS
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
300
UNIT
ns
tr
Rise time for both SDA and SCL signals
Fall time for both SDA and SCL signals
SCL pulse duration, high
tf
300
ns
tw(H)
tw(L)
tsu2
th2
0.6
1.3
0.6
0.6
100
0(1)
0.6
μs
SCL pulse duration, low
μs
Setup time for START condition
START condition hold time after which first clock pulse is generated
Data setup time
μs
μs
tsu1
th1
ns
Data hold time
ns
tsu3
CB
Setup time for STOP condition
Load capacitance for each bus line
μs
400
pF
(1) A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of
SCL.
tw(H)
tw(L)
tr
tf
SCL
tsu1
th1
SDA
T0027-01
Figure 1. SCL and SDA Timing
SCL
t(buf)
th2
tsu2
tsu3
SDA
Start
Condition
Stop
Condition
T0028-01
Figure 2. Timing for Start and Stop Conditions
Copyright © 2011, Texas Instruments Incorporated
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TAS5424B-Q1
SLOS673 –DECEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS
THD+N
vs
THD+N
vs
BTL OUTPUT POWER at 1kHz
PBTL OUTPUT POWER at 1kHz
Figure 3.
Figure 4.
TAS5424B-Q1
THD+N
vs
COMMON-MODE REJECTION RATIO
vs
FREQUENCY at 1 Watt
FREQUENCY
Figure 5.
Figure 6.
12
Copyright © 2011, Texas Instruments Incorporated
TAS5414B-Q1
TAS5424B-Q1
www.ti.com
SLOS673 –DECEMBER 2011
TYPICAL CHARACTERISTICS (continued)
CROSSTALK
vs
FREQUENCY
NOISE FFT
Figure 7.
Figure 8.
EFFICIENCY,
DEVICE POWER DISSIPATION
FOUR CHANNELS AT 4 Ω EACH
FOUR CHANNELS AT 4 Ω EACH
100
90
80
70
60
50
40
30
20
10
0
12
10
8
6
4
2
0
0
4
8
12
16
20
24
28
32
0
5
10
15
20
P − Power Per Channel − W
P − Power Per Channel − W
G007
G008
Figure 9.
Figure 10.
Copyright © 2011, Texas Instruments Incorporated
13
TAS5414B-Q1
TAS5424B-Q1
SLOS673 –DECEMBER 2011
www.ti.com
DESCRIPTION OF OPERATION
OVERVIEW
The TAS5414B-Q1 and TAS5424B-Q1 are single-chip, four-channel, analog-input audio amplifiers for use in the
automotive environment. The design uses an ultra-efficient class-D technology developed by Texas Instruments,
but with changes needed by the automotive industry. This technology allows for reduced power consumption,
reduced heat, and reduced peak currents in the electrical system. The device realizes an audio sound system
design with smaller size and lower weight than traditional class-AB solutions.
There are eight core design blocks:
•
•
•
•
•
•
•
•
Preamplifier
PWM
Gate drive
Power FETs
Diagnostics
Protection
Power supply
I2C serial communication bus
Preamplifier
The preamplifier is a high-input-impedance, low-noise, low-offset-voltage input stage with adjustable gain. The
high input impedance allows the use of low-cost input capacitors while still achieving extended low-frequency
response. The preamplifier is powered by a dedicated, internally regulated supply, which gives it excellent noise
immunity and channel separation. Also included in the preamp are:
1. Mute Pop-and-Click Control— The device ramps the gain gradually when a mute or play command is
received. Another form of click and pop can be caused by the start or stopping of switching in a class-D
amplifier. The TAS5414B-Q1 and TAS5424B-Q1 incorporate a patented method to reduce the pop energy
during the switching startup and shutdown sequence. Fault conditions require rapid protection response by
the TAS5414B-Q1 and the TAS5424B-Q1, which do not have time to ramp the gain down in a pop-free
manner. The device transitions into Hi-Z mode when an OV, UV, OC, OT, or DC fault is encountered. Also,
activation of the STANDBY pin may not be pop-free.
2. Gain Control—The four gain settings are set in the preamplifier via I2C control registers. The gain is set
outside of the global feedback resistors of the device, thus allowing for stability of the system at all gain
settings with properly loaded conditions.
Pulse-Width Modulator (PWM)
The PWM converts the analog signal from the preamplifier into a switched signal of varying duty cycle. This is
the critical stage that defines the class-D architecture. In the TAS5414B-Q1 and TAS5424B-Q1, the modulator is
an advanced design with high bandwidth, low noise, low distortion, excellent stability, and full 0–100%
modulation capability. The patented PWM uses clipping recovery circuitry to eliminate the deep saturation
characteristic of PWMs when the input signal exceeds the modulator waveform.
Gate Drive
The gate driver accepts the low-voltage PWM signal and level shifts it to drive a high-current, full-bridge, power
FET stage. The device uses proprietary techniques to optimize EMI and audio performance.
Power FETs
The BTL output for each channel comprises four rugged N-channel 30-V 65 mΩ FETs for high efficiency and
maximum power transfer to the load. These FETs are designed to handle large voltage transients during load
dump.
14
Copyright © 2011, Texas Instruments Incorporated
TAS5414B-Q1
TAS5424B-Q1
www.ti.com
SLOS673 –DECEMBER 2011
Load Diagnostics
The device incorporates load diagnostic circuitry designed to help pinpoint the nature of output misconnections
during installation. The TAS5414B-Q1 and the TAS5424B-Q1 include functions for detecting and determining the
status of output connections. The following diagnostics are supported:
•
•
•
•
•
Short to GND
Short to PVDD
Short across load
Open load
Tweeter detection
The presence of any of the short or open conditions is reported to the system via I2C register read. The tweeter
detect status can be read from the CLIP_OTW pin when properly configured.
1. Output Short and Open Diagnostics—The device contains circuitry designed to detect shorts and open
conditions on the outputs. The load diagnostic function can only be invoked when the output is in the Hi-Z
mode. There are four phases of test during load diagnostics and two levels of test. In the full level, all
channels must be in the Hi-Z state. All four phases are tested on each channel, all four channels at the same
time. When fewer than four channels are in Hi-Z, the reduced level of test is the only available option. In the
reduced level, only short to PVDD and short to GND can be tested. Load diagnostics can occur at power up
before the amplifier is moved out of Hi-Z mode. If the amplifier is already in play mode, it must Mute and then
Hi-Z before the load diagnostic can be performed. By performing the mute function, the normal pop- and
click-free transitions occur before the diagnostics begin. The diagnostics are performed as shown in
Figure 11. Figure 12 shows the impedance ranges for the open-load and shorted-load diagnostics. The
results of the diagnostic are read from the diagnostic register for each channel via I2C. With the default
settings and MUTE capacitor the S2G and S2P phase take ~20mS each, the OL phase takes ~100mS, and
the SL takes ~230mS.
Figure 11. Load Diagnostics Sequence of Events
Copyright © 2011, Texas Instruments Incorporated
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TAS5414B-Q1
TAS5424B-Q1
SLOS673 –DECEMBER 2011
www.ti.com
Figure 12. Open and Shorted Load Detection
2. Tweeter Detection—Tweeter detection is an alternate operating mode that is used to determine the proper
connection of a frequency dependent load (such as a speaker with a crossover). Tweeter detection is
invoked via I2C, and all four channels should be tested individually. Tweeter detection uses the average
cycle-by-cycle current limit circuit (see CBC section) to measure the current delivered to the load. The proper
implementation of this diagnostic function is dependent on the amplitude of a user-supplied test signal and
on the impedance versus frequency curve of the acoustic load. The system (external to the TAS5414B-Q1
and TAS5424B-Q1) must generate a signal to which the load will respond. The frequency and amplitude of
this signal must be calibrated by the user to result in a current draw that is greater than the tweeter detection
threshold when the load under test is present, and less than the detection threshold if the load is not properly
connected. The current level for the tweeter detection threshold, as well as the maximum current that can
safely be delivered to a load when in tweeter detection mode, can be found in the Electrical Characteristics
section of the datasheet. The tweeter detection results are reported on the CLIP_OTW pin during the
application of the test signal. When tweeter detection is activated (indicating that the tested load is present),
pulses on the CLIP_OTW pin begin to toggle. The pulses on the CLIP_OTW pins will report low whenever
the current detection threshold is exceeded, and the pin will remain low until the threshold is no longer
exceeded. The minimum low-pulse period that can be expected is equal to one period of the switching
frequency. Having an input signal that increases the amount of time that the detector is activated (e. g.
increasing the amplitude of the input signal) will increase the amount of time for which the pin reports low.
NOTE: Because tweeter detection is an alternate operating mode, the channels to be tested must be placed
in Play mode (via register 0x0C) after tweeter detection has been activated in order to commence the
detection process. Additionally, the CLIP_OTW pin must be set up via register 0x0A to report the results of
tweeter detection.
Protection and Monitoring
1. Cycle-By-Cycle Current Limit (CBC)—The CBC current-limiting circuit terminates each PWM pulse to limit
the output current flow when the average current limit (ILIM) threshold is exceeded. The overall effect on the
audio in the case of a current overload is quite similar to a voltage-clipping event, where power is temporarily
limited at the peaks of the musical signal and normal operation continues without disruption when the
overload is removed. The TAS5414B-Q1 and TAS5424B-Q1 do not prematurely shut down in this condition.
All four channels continue in play mode and pass signal.
2. Overcurrent Shutdown (OCSD)—Under severe short-circuit events, such as a short to PVDD or ground, a
peak-current detector is used, and the affected channel shuts down in 200 μs to 390 μs if the conditions are
severe enough. The shutdown speed depends on a number of factors, such as the impedance of the short
circuit, supply voltage, and switching frequency. Only the shorted channels are shut down in such a scenario.
16
Copyright © 2011, Texas Instruments Incorporated
TAS5414B-Q1
TAS5424B-Q1
www.ti.com
SLOS673 –DECEMBER 2011
The user may restart the affected channel via I2C. An OCSD event activates the fault pin, and the affected
channel(s) are recorded in the I2C fault register. If the supply or ground short is strong enough to exceed the
peak current threshold but not severe enough to trigger the OCSD, the peak current limiter prevents excess
current from damaging the output FETs, and operation returns to normal after the short is removed.
3. DC Detect—This circuit detects a dc offset continuously during normal operation at the output of the
amplifier. If the dc offset reaches the level defined in the I2C registers for the specified time period, the circuit
triggers. By default a dc detection event does not shut the output down. The shutdown function can be
enabled or disabled via I2C. If enabled, the triggered channel shuts down, but the others remain playing and
the FAULT pin is asserted. The dc level is defined in I2C registers.
4. Clip Detect—The clip detect circuit alerts the user to the presence of a 100% duty-cycle PWM due to a
clipped waveform. When this occurs, a signal is passed to the CLIP_OTW pin and it is asserted until the
100% duty-cycle PWM signal is no longer present. All four channels are connected to the same CLIP_OTW
pin. Through I2C, the CLIP_OTW signal can be changed to clip-only, OTW-only, or both. A fourth mode,
used only during diagnostics, is the option to report tweeter detection events on this pin (see the Tweeter
Detection section). The microcontroller in the system can monitor the signal at the CLIP_OTW pin and may
be configured to reduce the volume to all four channels in an active clipping-prevention circuit.
5. Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD) and Thermal Foldback—By
default, the CLIP_OTW pin is set to indicate an OTW. This can be changed via I2C commands. If selected to
indicate a temperature warning, the CLIP_OTW pin is asserted when the die temperature reaches warning
level 1 as shown in the electrical specs. The OTW has three temperature thresholds with a 10°C hysteresis.
Each threshold is indicated in I2C register 0x04 bits 5, 6, and 7. The device still functions until the
temperature reaches the OTSD threshold, at which time the outputs are placed into Hi-Z mode and the
FAULT pin is asserted. I2C is still active in the event of an OTSD and the registers can be read for faults, but
all audio ceases abruptly. After the OTSD resets the device can be turned back on through I2C. The OTW is
still indicated until the temperature drops below warning level 1. The Thermal Foldback decreases the
channel gain.
6. Undervoltage (UV) and Power-on-Reset (POR)—The undervoltage (UV) protection detects low voltages on
PVDD, AVDD, and CP. In the event of an undervoltage, the FAULT pin is asserted and the I2C register is
updated, depending on which voltage caused the event. Power-on-reset (POR) occurs when PVDD drops
low enough. A POR event causes the I2C to go into a high-impedance state. After the device recovers from
the POR event, the device must be re-initialized via I2C.
7. Overvoltage (OV) and Load Dump—The OV protection detects high voltages on PVDD. If PVDD reaches
the overvoltage threshold, the FAULT pin is asserted and the I2C register is updated. The device can
withstand 50-V load-dump voltage spikes. Also depicted in this graph are the voltage thresholds for normal
operation region, overvoltage operation region, and load-dump protection region. Figure 11 shows the
regions of operating voltage and the profile of the load dump event.
Power Supply
The power for the device is most commonly provided by a car battery that can have a large voltage range. PVDD
is a filtered battery voltage, and it is the supply for the output FETS and the low-side FET gate driver. The
high-side FET gate driver is supplied by a charge pump (CP) supply. The charge pump supplies the gate drive
voltage for all four channels. The analog circuitry is powered by AVDD, which is a provided by an internal linear
regulator. A 0.1μF/10V external bypass capacitor is needed at the A_BYP pin for this supply. It is recommended
that no external components except the bypass capacitor be attached to this pin. The digital circuitry is powered
by DVDD, which is provided by an internal linear regulator. A 0.1μF/10V external bypass capacitor is needed at
the D_BYP pin. It is recommended that no external components except the bypass capacitor be attached to this
pin.
The TAS5414B-Q1 and TAS5424B-Q1 can withstand fortuitous open ground and power conditions. Fortuitous
open ground usually occurs when a speaker wire is shorted to ground, allowing for a second ground path
through the body diode in the output FETs. The diagnostic capability allows the speakers and speaker wires to
be debugged, eliminating the need to remove the amplifier to diagnose the problem.
Copyright © 2011, Texas Instruments Incorporated
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TAS5414B-Q1
TAS5424B-Q1
SLOS673 –DECEMBER 2011
www.ti.com
I2C Serial Communication Bus
The device communicates with the system processor via the I2C serial communication bus as an I2C slave-only
device. The processor can poll the device via I2C to determine the operating status. All fault conditions and
detections are reported via I2C. There are also numerous features and operating conditions that can be set via
I2C.
The I2C bus allows control of the following configurations:
•
•
•
•
•
•
•
•
Independent gain control of each channel. The gain can be set to 12 dB, 20 dB, 26 dB, and 32 dB.
Select AM non-interference switching frequency
Select the function of OTW_CLIP pin
Enable or disable dc detect function with selectable threshold
Place channel in Hi-Z (switching stopped) mode (mute)
Select tweeter detect, set detect threshold and initiate function
Initiate open/short load diagnostic
Reset faults and return to normal switching operation from Hi-Z mode (unmute)
In addition to the standard SDA and SCL pins for the I2C bus, the TAS5414B-Q1 and the TAS5424B-Q1 include
a single pin that allows up to four devices to work together in a system with no additional hardware required for
communication or synchronization. The I2C_ADDR pin sets the device in master or slave mode and selects the
I2C address for that device. Tie I2C_ADDR to DGND for master, to 1.2 Vdc for slave 1, to 2.4 Vdc for slave 2,
and to D_BYP for slave 3. The OSC_SYNC pin is used to synchronize the internal clock oscillators and thereby
avoid beat frequencies. An external oscillator can also be applied to this pin for external control of the switching
frequency.
Table 2. Table 7. I2C_ADDR Pin Connection
DESCRIPTION
I2C_ADDR PIN CONNECTION
I2C ADDRESS
TAS5414B-Q1/5424 0 (OSC
MASTER)
To SGND pin
0xD8/D9
TAS5414B-Q1/5424 1 (OSC
SLAVE1)
35% DVDD (resistive voltage divider between D_BYP pin and SGND pin)(1)
65% DVDD (resistive voltage divider between D_BYP pin and SGND pin)(1)
To D_BYP pin
0xDA/DB
0xDC/DD
0xDE/DF
TAS5414B-Q1/5424 2 (OSC
SLAVE2)
TAS5414B-Q1/5424 3 (OSC
SLAVE3)
(1) RI2C_ADDR with 5% or better tolerance is recommended.
I2C Bus Protocol
The TAS5414B-Q1 and TAS5424B-Q1 have a bidirectional serial control interface that is compatible with the
Inter IC (I2C) bus protocol and supports 400-kbps data transfer rates for random and sequential write and read
operations. This is a slave-only device that does not support a multimaster bus environment or wait state
insertion. The control interface is used to program the registers of the device and to read device status.
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data is transferred on the bus serially, one bit at a time. The address and data are transferred in byte
(8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is
acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master
device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the data terminal (SDA) while the clock is HIGH to indicate a start and stop
conditions. A HIGH-to-LOW transition on SDA indicates a start, and a LOW-to-HIGH transition indicates a stop.
Normal data bit transitions must occur within the low time of the clock period. These conditions are shown in
Figure 13. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication
with another device and then wait for an acknowledge condition. The TAS5414B-Q1 and TAS5424B-Q1 hold
SDA LOW during the acknowledge-clock period to indicate an acknowledgment. When this occurs, the master
18
Copyright © 2011, Texas Instruments Incorporated
TAS5414B-Q1
TAS5424B-Q1
www.ti.com
SLOS673 –DECEMBER 2011
transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit
(1 byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An
external pullup resistor must be used for the SDA and SCL signals to set the HIGH level for the bus. There is no
limit on the number of bytes that can be transmitted between start and stop conditions. When the last word
transfers, the master generates a stop condition to release the bus.
8-Bit Register Data For
Address (N)
8-Bit Register Data For
Address (N)
R/
W
8-Bit Register Address (N)
7-Bit Slave Address
A
A
A
A
SDA
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SCL
Start
Stop
T0035-01
Figure 13. Typical I2C Sequence
Use the I2C_ADDR pin (pin 2) to program the device for one of four addresses. These four addresses are
licensed I2C addresses and do not conflict with other licensed I2C audio devices. To communicate with the
TAS5414B-Q1 and the TAS5424B-Q1, the I2C master uses addresses shown in Figure 13. Read and write data
can be transmitted using single-byte or multiple-byte data transfers.
Random Write
As shown in Figure 14, a single-byte data-write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct I2C device address
and the read/write bit, the TAS5414B-Q1 or TAS5424B-Q1 device responds with an acknowledge bit. Next, the
master transmits the address byte or bytes corresponding to the internal memory address being accessed. After
receiving the address byte, the TAS5414B-Q1 or TAS5424B-Q1 again responds with an acknowledge bit. Next,
the master device transmits the data byte to be written to the memory address being accessed. After receiving
the data byte, the TAS5414B-Q1 or TAS5424B-Q1 again responds with an acknowledge bit. Finally, the master
device transmits a stop condition to complete the single-byte data-write transfer.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
R/W
A6 A5 A4 A3 A2 A1 A0
ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
I2C Device Address and
Read/Write Bit
Subaddress
Data Byte
Stop
Condition
T0036-01
Figure 14. Random Write Transfer
Sequential Write
A sequential data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes are
transmitted by the master device to TAS5414B-Q1 or TAS5424B-Q1 as shown in Figure 14. After receiving each
data byte, the TAS5414B-Q1 or TAS5424B-Q1 responds with an acknowledge bit and the I2C subaddress is
automatically incremented by one.
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TAS5424B-Q1
SLOS673 –DECEMBER 2011
www.ti.com
Start
Condition
Acknowledge
Acknowledge
Acknowledge
D0 ACK D7
Acknowledge
D0 ACK D7
Acknowledge
A6 A5
A1 A0 R/W ACK A7 A6 A5 A4 A3
A1 A0 ACK D7
D0 ACK
I2C Device Address and
Read/Write Bit
Subaddress
First Data Byte
Last Data Byte
Stop
Condition
Other Data Bytes
T0036-02
Figure 15. Sequential Write Transfer
Random Read
As shown in Figure 16, a single-byte data-read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data-read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal
memory address to be read. As a result, the read/write bit is a 0. After receiving the address and the read/write
bit, the TAS5414B-Q1 or TAS5424B-Q1 responds with an acknowledge bit. In addition, after sending the internal
memory address byte or bytes, the master device transmits another start condition followed by the
TAS5414B-Q1 or TAS5424B-Q1 address and the read/write bit again. This time the read/write bit is a 1,
indicating a read transfer. After receiving the address and the read/write bit, the TAS5414B-Q1 or TAS5424B-Q1
again responds with an acknowledge bit. Next, the TAS5414B-Q1 or TAS5424B-Q1 transmits the data byte from
the memory address being read. After receiving the data byte, the master device transmits a not-acknowledge
followed by a stop condition to complete the single-byte data-read transfer.
Repeat Start
Condition
Not
Acknowledge
Start
Condition
Acknowledge
Acknowledge
A0 ACK
Acknowledge
A6 A5
A1 A0 R/W ACK A7 A6 A5 A4
A6 A5
A1 A0 R/W ACK D7 D6
D1 D0 ACK
I2C Device Address and
Read/Write Bit
Subaddress
I2C Device Address and
Read/Write Bit
Data Byte
Stop
Condition
T0036-03
Figure 16. Random Read Transfer
Sequential Read
A sequential data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes are
transmitted by the TAS5414B-Q1 or TAS5424B-Q1 to the master device as shown in Figure 17. Except for the
last data byte, the master device responds with an acknowledge bit after receiving each data byte and
automatically increments the I2C subaddress by one. After receiving the last data byte, the master device
transmits a not-acknowledge followed by a stop condition to complete the transfer.
Repeat Start
Condition
Not
Acknowledge
Start
Condition
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
D0 ACK D7
A6
A0 R/W ACK A7 A6 A5
A0 ACK
A6
A0 R/W ACK D7
D0 ACK D7
D0 ACK
I2C Device Address and
Read/Write Bit
Subaddress
I2C Device Address and First Data Byte
Read/Write Bit
Other Data Bytes
Last Data Byte
Stop
Condition
T0036-04
Figure 17. Sequential Read Transfer
20
Copyright © 2011, Texas Instruments Incorporated
TAS5414B-Q1
TAS5424B-Q1
www.ti.com
SLOS673 –DECEMBER 2011
Table 3. TAS5414B-Q1/5424 I2C Addresses
SELECTABLE WITH
FIXED ADDRESS
READ/WRITE
I2C
ADDRESS
ADDRESS PIN
BIT
DESCRIPTION
MSB
6
1
1
1
1
1
1
1
1
5
0
0
0
0
0
0
0
0
4
1
1
1
1
1
1
1
1
3
1
1
1
1
1
1
1
1
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
LSB
0
TAS5414B-Q1/5424B 0 I2C WRITE
1
1
1
1
1
1
1
1
0xD8
0xD9
0xDA
0xDB
0xDC
0xDD
0xDE
0xDF
(OSC MASTER)
I2C READ
1
TAS5414B-Q1/5424B 1 I2C WRITE
0
(OSC SLAVE1)
I2C READ
1
TAS5414B-Q1/5424B 2 I2C WRITE
0
(OSC SLAVE2)
I2C READ
1
TAS5414B-Q1/5424B 3 I2C WRITE
0
(OSC SLAVE3)
I2C READ
1
Table 4. I2C Address Register Definitions
ADDRESS
0x00
R/W
R
REGISTER DESCRIPTION
Latched fault register 1, global and channel fault
Latched fault register 2, dc offset and overcurrent detect
Latched diagnostic register 1, load diagnostics
Latched diagnostic register 2, load diagnostics
External status register 1, temperature and voltage detect
External status register 2, Hi-Z and low-low state
External status register 3, mute and play modes
External status register 4, load diagnostics
0x01
R
0x02
R
0x03
R
0x04
R
0x05
R
0x06
R
0x07
R
0x08
R/W
R/W
R/W
R/W
R/W
R/W
-
External control register 1, channel gain select
External control register 2, over current control
External control register 3, switching frequency and clip pin select
External control register 4, load diagnostic, master mode select
External control register 5, output state control
External control register 6, output state control
Not Used
0x09
0x0A
0x0B
0x0C
0x0D
0x0E, 0x0F
0x10
R/W
R
External control register 7, DC detect threshold selection
0x13
External status register 5, over temperature shutdown and thermal foldback
Table 5. Fault Register 1 (0x00) Protection
D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
No protection-created faults, default value
Overtemperature warning has occurred
DC offset has occurred in any channel
Overcurrent shutdown has occurred in any channel
Overtemperature shutdown has occurred
Charge pump undervoltage has occurred
AVDD, analog voltage, undervoltage has occurred
PVDD undervoltage has occurred
0
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
1
–
–
–
–
–
1
–
–
–
–
–
1
–
–
–
–
–
1
–
–
–
–
–
1
–
–
–
–
–
1
–
–
–
–
–
–
–
–
–
–
–
–
–
PVDD overvoltage has occurred
Table 6. Fault Register 2 (0x01) Protection
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
No protection-created faults, default value
Overcurrent shutdown channel 1 has occurred
–
–
–
–
–
–
–
1
Copyright © 2011, Texas Instruments Incorporated
21
TAS5414B-Q1
TAS5424B-Q1
SLOS673 –DECEMBER 2011
www.ti.com
Table 6. Fault Register 2 (0x01) Protection (continued)
D7
–
D6
–
D5
–
D4
–
D3
–
D2
–
D1
1
D0
–
FUNCTION
Overcurrent shutdown channel 2 has occurred
Overcurrent shutdown channel 3 has occurred
Overcurrent shutdown channel 4 has occurred
DC offset channel 1 has occurred
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
DC offset channel 2 has occurred
–
1
–
–
–
–
–
–
DC offset channel 3 has occurred
1
–
–
–
–
–
–
–
DC offset channel 4 has occurred
Table 7. Diagnostic Register 1 (0x02) Load Diagnostics
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
No load-diagnostic-created faults, default value
Output short to ground channel 1 has occurred
Output short to PVDD channel 1 has occurred
Shorted load channel 1 has occurred
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
Open load channel 1 has occurred
–
–
–
1
–
–
–
–
Output short to ground channel 2 has occurred
Output short to PVDD channel 2 has occurred
Shorted load channel 2 has occurred
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
–
Open load channel 2 has occurred
Table 8. Diagnostic Register 2 (0x03) Load Diagnostics
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
No load-diagnostic-created faults, default value
Output short to ground channel 3 has occurred
Output short to PVDD channel 3 has occurred
Shorted load channel 3 has occurred
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
Open load channel 3 has occurred
–
–
–
1
–
–
–
–
Output short to ground channel 4 has occurred
Output short to PVDD channel 4 has occurred
Shorted load channel 4 has occurred
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
–
Open load channel 4 has occurred
Table 9. External Status Register 1 (0x04) Fault Detection
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
No protection-created faults are present, default value
PVDD overvoltage fault is present
PVDD undervoltage fault is present
AVDD, analog voltage fault is present
Charge-pump voltage fault is present
Overtemperature shutdown is present
Overtemperature warning
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
1
–
–
–
–
–
Overtemperature warning level 1
1
0
1
–
–
–
–
–
Overtemperature warning level 2
1
1
1
–
–
–
–
–
Overtemperature warning level 3
22
Copyright © 2011, Texas Instruments Incorporated
TAS5414B-Q1
TAS5424B-Q1
www.ti.com
SLOS673 –DECEMBER 2011
Table 10. External Status Register 2 (0x05) Output State of Individual Channels
D7
0
D6
D5
0
D4
0
D3
1
D2
1
D1
1
D0
1
FUNCTION
0
–
–
–
–
–
–
1
–
Output is in Hi-Z mode, not in low-low mode(1), default value
–
–
–
–
–
–
0
Channel 1 Hi-Z mode (0 = not Hi-Z, 1 = Hi-Z)
–
–
–
–
–
0
–
Channel 2 Hi-Z mode (0 = not Hi-Z, 1 = Hi-Z)
–
–
–
–
0
–
–
Channel 3 Hi-Z mode (0 = not Hi-Z, 1 = Hi-Z)
–
–
–
0
–
–
–
Channel 4 Hi-Z mode (0 = not Hi-Z, 1 = Hi-Z)
–
–
1
–
–
–
–
Channel 1 low-low mode (0 = not low-low, 1 = low-low)(1)
Channel 2 low-low mode (0 = not low-low, 1 = low-low)(1)
Channel 3 low-low mode (0 = not low-low, 1 = low-low)(1)
Channel 4 low-low mode (0 = not low-low, 1 = low-low)(1)
–
1
–
–
–
–
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
(1) Low-low is defined as both outputs actively pulled to ground.
Table 11. External Status Register 3 (0x06) Play and Mute Modes
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
Mute mode is disabled, play mode disabled, default value, (Hi-Z mode)
Channel 1 play mode is enabled
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
Channel 2 play mode is enabled
–
–
–
–
–
1
–
–
Channel 3 play mode is enabled
–
–
–
–
1
–
–
–
Channel 4 play mode is enabled
–
–
–
1
–
–
–
–
Channel 1 mute mode is enabled
–
–
1
–
–
–
–
–
Channel 2 mute mode is enabled
–
1
–
–
–
–
–
–
Channel 3 mute mode is enabled
1
–
–
–
–
–
–
–
Channel 4 mute mode is enabled
Table 12. External Status Register 4 (0x07) Load Diagnostics
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
No channels are set in load diagnostics mode, default value
Channel 1 is in load diagnostics mode
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
Channel 2 is in load diagnostics mode
–
–
–
–
–
1
–
–
Channel 3 is in load diagnostics mode
–
–
–
–
1
–
–
–
Channel 4 is in load diagnostics mode
–
–
–
1
–
–
–
–
Channel 1 is in Over Temperature Foldback
Channel 2 is in Over Temperature Foldback
Channel 3 is in Over Temperature Foldback
Channel 4 is in Over Temperature Foldback
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
–
Table 13. External Control Register 1 (0x08) Gain Select
D7
1
D6
0
D5
1
D4
0
D3
1
D2
0
D1
1
D0
0
FUNCTION
Set gain for all channels to 26 dB, default value
Set channel 1 gain to 12 dB
–
–
–
–
–
–
0
0
–
–
–
–
–
–
0
1
Set channel 1 gain to 20 dB
–
–
–
–
–
–
1
1
Set channel 1 gain to 32 dB
–
–
–
–
0
0
–
–
Set channel 2 gain to 12 dB
–
–
–
–
0
1
–
–
Set channel 2 gain to 20 dB
–
–
–
–
1
1
–
–
Set channel 2 gain to 32 dB
–
–
0
0
–
–
–
–
Set channel 3 gain to 12 dB
–
–
0
1
–
–
–
–
Set channel 3 gain to 20 dB
–
–
1
1
–
–
–
–
Set channel 3 gain to 32 dB
Copyright © 2011, Texas Instruments Incorporated
23
TAS5414B-Q1
TAS5424B-Q1
SLOS673 –DECEMBER 2011
www.ti.com
Table 13. External Control Register 1 (0x08) Gain Select (continued)
D7
0
D6
0
D5
–
D4
–
D3
–
D2
–
D1
–
D0
–
FUNCTION
Set channel 4 gain to 12 dB
Set channel 4 gain to 20 dB
Set channel 4 gain to 32 dB
0
1
–
–
–
–
–
–
1
1
–
–
–
–
–
–
Table 14. External Control Register 2(0x09) Over Current Control
D7
D6
D5
D4
1
D3
D2
D1
D0
FUNCTION
Current Limit Level 2 for all channels
1
1
1
0
0
0
0
0
Set Channel 1 Over Current Limit ( 0 - level 1, 1 - level 2)
Set Channel 2Over Current Limit ( 0 - level 1, 1 - level 2)
Set Channel 3Over Current Limit ( 0 - level 1, 1 - level 2)
Set Channel 4Over Current Limit ( 0 - level 1, 1 - level 2)
Reserved
0
0
0
X
X
X
X
Table 15. External Control Register 3 (0x0A) Switching Frequency Select and Clip_OTW Configuration
D7
0
D6
0
D5
0
D4
0
D3
1
D2
1
D1
0
D0
1
FUNCTION
Set fS = 417 kHz, report clip and OTW, 45° phase, disable hard stop
Set fS = 500 kHz
–
–
–
–
–
–
0
0
–
–
–
–
–
–
1
0
Set fS = 357 kHz
–
–
–
–
–
–
1
1
Invalid frequency selection (do not set)
–
–
–
–
0
0
–
–
Configure CLIP_OTW pin to report tweeter detect only
Configure CLIP_OTW pin to report clip detect only
Configure CLIP_OTW pin to report overtemperature warning only
Enable hard-stop mode
–
–
–
–
0
1
–
–
–
–
–
–
1
0
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
Set fS to a 180° phase difference between adjacent channels
Send Sync Pulse from OSC_SYNC pin (Device must be in master mode)
Reserved
–
1
–
–
–
–
–
–
X
–
–
–
–
–
–
–
Table 16. External Control Register 4 (0x0B) Load Diagnostics and Master/Slave Control
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
1
0
1
0
0
0
0
Clock output disabled, Master clock mode, DC Detection Enabled, Load
diagnostics disabled
–
–
–
–
–
–
–
1
–
–
–
–
–
–
0
–
–
–
–
–
–
1
–
–
–
–
–
–
0
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
–
Run channel 1 load diagnostics
Run channel 2 load diagnostics
Run channel 3 load diagnostics
Run channel 4 load diagnostics
Disable dc detection on all channels
Enable tweeter-detect mode
Enable slave mode (external oscillator must be provided)
Enable clock output on OSC_SYNC pin (valid only in master mode)
Table 17. External Control Register 5 (0x0C) Output Control
D7
0
D6
0
D5
0
D4
1
D3
1
D2
1
D1
1
D0
1
FUNCTION
All channels, Hi-Z, mute, reset disabled
–
–
–
–
–
–
–
0
Set channel 1 to mute mode, non-Hi-Z
Set channel 2 to mute mode, non-Hi-Z
Set channel 3 to mute mode, non-Hi-Z
Set channel 4 to mute mode, non-Hi-Z
–
–
–
–
–
–
0
–
–
–
–
–
–
0
–
–
–
–
–
–
0
–
–
–
24
Copyright © 2011, Texas Instruments Incorporated
TAS5414B-Q1
TAS5424B-Q1
www.ti.com
SLOS673 –DECEMBER 2011
Table 17. External Control Register 5 (0x0C) Output Control (continued)
D7
–
D6
D5
–
D4
0
D3
–
D2
–
D1
–
D0
–
FUNCTION
Set non-Hi-Z channels to play mode, (unmute)
Reserved
–
1
–
–
1
–
–
–
–
–
1
–
–
–
–
–
–
Reset device
Table 18. External Control Register 6 (0x0D) Output Control
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
Low-low state disabled all channels
–
–
–
–
–
–
–
1
Set channel 1 to low-low state
Set channel 2 to low-low state
Set channel 3 to low-low state
Set channel 4 to low-low state
Reserved
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
X
X
X
X
–
–
–
–
Table 19. External Control Register 7 (0x10) Miscellaneous Selection
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
0
0
0
0
0
0
1
Normal speed CM ramp, normal S2P & S2G timing, no delay between
LDG phases, Crosstalk Enhancement Disabled, Default DC detect value
(1.6V)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
1
-
0
0
-
Minimum DC detect value (0.8V)
Maximum DC detect value (2.4V)
-
-
1
-
Enable Crosstalk Enhancement
-
1
-
-
-
Adds a 20mS delay between load diagnostic phases
1
-
-
-
Short-to-Power (S2P) and Short-to-Ground (S2G) Load Diagnostic
phases take 4x longer
1
-
-
-
-
-
-
-
Slower common mode (CM) ramp down from Mute mode
Reserved
X
X
Table 20. External Status Register 5 (0x13) Over Temperature and Thermal Foldback Status
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
Default Over temperature foldback status, no channel is in foldback
Channel 1 in thermal foldback
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
Channel 2 in thermal foldback
0
0
0
0
0
1
0
0
Channel 3 in thermal foldback
0
0
0
0
1
0
0
0
Channel 4 in thermal foldback
0
0
0
1
0
0
0
0
Channel 1 in Over temperature shutdown
Channel 2 in Over temperature shutdown
Channel 3 in Over temperature shutdown
Channel 4 in Over temperature shutdown
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Hardware Control Pins
There are four discrete hardware pins for real-time control and indication of device status.
FAULT pin: This active-low open-drain output pin indicates the presence of a fault condition that requires the
device to go into the Hi-Z mode or standby mode. When this pin is asserted, the device has protected itself
and the system from potential damage. The exact nature of the fault can be read via I2C with the exception
of PVDD under-voltage faults below POR in which case the I2C bus is no longer operational. However, the
fault is still indicated due to the fact that the FAULT pin is asserted.
Copyright © 2011, Texas Instruments Incorporated
25
TAS5414B-Q1
TAS5424B-Q1
SLOS673 –DECEMBER 2011
www.ti.com
CLIP_OTW pin: This active-low open-drain pin is configured via I2C to indicate one of the following
conditions: overtemperature warning, the detection of clipping, or the logical OR of both of these conditions.
During tweeter detect diagnostics, this pin also is asserted when a tweeter is present.
MUTE pin: This active-low pin is used for hardware control of the mute/unmute function for all four channels.
Capacitor CMUTE is used to control the time constant for the gain ramp needed to produce a pop- and
click-free mute function. For pop- and click-free operation, the mute function should be implemented through
I2C commands. The use of a hard mute with an external transistor does not ensure pop- and click-free
operation, and is not recommended unless an emergency hard mute function is required in case of a loss of
I2C control. The CMUTE capacitor may not be shared between multiple devices.
STANDBY pin: When this active-low pin is asserted, the device goes into a complete shutdown, and current
draw is limited to 2 μA, typical. It can be used to shut down the device rapidly. If all channels are in Hi-Z the
device will enter standby in ~1mS and if not a quick ramp down will occur that takes ~20mS. The outputs are
ramped down quickly if not already in Hi-Z so externally biasing the MUTE pin will prevent the device from
entering standby. All I2C register content is lost when this pin is asserted. The I2C bus goes into the
high-impedance state when the STANDBY pin is asserted.
EMI Considerations
Automotive level EMI performance depends on both careful integrated circuit design and good system level
design. Controlling sources of electromagnetic interference (EMI) was a major consideration in all aspects of the
design.
The design has minimal parasitic inductances due to the short leads on the package. This dramatically reduces
the EMI that results from current passing from the die to the system PCB. Each channel also operates at a
different phase. The phase between channels is I2C selectable to either 45° or 180°, to reduce EMI caused by
high-current switching. The design also incorporates circuitry that optimizes output transitions that cause EMI.
AM Radio Avoidance
To reduce interference in the AM radio band, the device has the ability to change the switching frequency via I2C
commands. The recommended frequencies are listed in Table 21. The fundamental frequency and its second
harmonic straddle the AM radio band listed. This eliminates the tones that can be present due to the switching
frequency being demodulated by the AM radio.
Table 21. Recommended Switching Frequencies for AM Mode Operation
US
EUROPEAN
SWITCHING
FREQUENCY
(kHz)
SWITCHING
FREQUENCY
(kHz)
AM FREQUENCY
(kHz)
AM FREQUENCY
(kHz)
540 - 670
680 - 980
417
500
417
500
417
500
522 - 675
676 - 945
417
500
417
500
417
500
990 - 1180
1190 - 1420
1430 - 1580
1590 – 1700
946 - 1188
1189 - 1422
1423 - 1584
1585 - 1701
Operating Modes and Faults
The operating modes and faults are depicted in the following tables.
Table 22. Operating Modes
STATE NAME
STANDBY
Hi-Z
OUTPUT FETS
Hi-Z, floating
CHARGE PUMP
Stopped
OSCILLATOR
Stopped
Active
I2C
AVDD and DVDD
Stopped
OFF
ON
Hi-Z, weak pulldown
Switching at 50%
Active
Active
Active
Mute
Active
Active
ON
26
Copyright © 2011, Texas Instruments Incorporated
TAS5414B-Q1
TAS5424B-Q1
www.ti.com
SLOS673 –DECEMBER 2011
Table 22. Operating Modes (continued)
STATE NAME
Normal operation
OUTPUT FETS
CHARGE PUMP
OSCILLATOR
I2C
AVDD and DVDD
Switching with audio
Active
Active
Active
ON
Table 23. Global Faults and Actions
LATCHED/
SELF-
CLEARING
FAULT/
EVENT
FAULT/EVENT
CATEGORY
MONITORING
REPORTING
METHOD
ACTION
TYPE
ACTION
RESULT
MODES
POR
UV
Voltage fault
All
FAULT pin
I2C + FAULT pin
Hard mute (no ramp)
Standby
Hi-Z
Self-clearing
Latched
Hi-Z, mute, normal
CP UV
OV
Load dump
OTW
All
FAULT pin
Standby
None
Self-clearing
Self-clearing
Latched
Thermal warning
Thermal fault
Hi-Z, mute, normal
Hi-Z, mute, normal
I2C + CLIP_OTW pin
I2C + FAULT pin
None
OTSD
Hard mute (no ramp)
Standby
Table 24. Channel Faults and Actions
LATCHED/
SELF-
CLEARING
FAULT/
EVENT
FAULT/EVENT
CATEGORY
MONITORING
MODES
REPORTING
METHOD
ACTION
TYPE
ACTION
RESULT
Open/short
diagnostic
Diagnostic
Hi-Z (I2C activated)
I2C
None
None
Latched
Clipping
Warning
Mute / Play
CLIP_OTW pin
None
None
Self-clearing
Self-clearing
CBC load current
limit
Online protection
Current Limit
Start OC
timer
OC fault
DC detect
Output channel fault
Warning
I2C + FAULT pin
Hard mute
Hard mute
Hi-Z
Hi-Z
Latched
Latched
OT Foldback
I2C + CLIP_OTW
pin
Reduce Gain
None
Self-clearing
Audio Shutdown and Restart Sequence
The gain ramp of the filtered output signal and the updating of the I2C registers correspond to the MUTE pin
voltage during the ramping process. The length of time that the MUTE pin takes to complete its ramp is dictated
by the value of the external capacitor on the MUTE pin. With the default 220nF capacitor the turn-on common
mode ramp takes ~26mS and the gain ramp takes ~76mS.
Copyright © 2011, Texas Instruments Incorporated
27
TAS5414B-Q1
TAS5424B-Q1
SLOS673 –DECEMBER 2011
www.ti.com
tCM
tCM
tGAIN
tGAIN
HIZ_Report_x
(All Channels)
LOW_LOW_Report_x
(All Channels)
MUTE_Report_x
(All Channels)
PLAY_Report_x
MUTE Pin
OUTx_P (Filtered)
(All Channels)
OUTx_M (Filtered)
(All Channels)
T0192-02
Figure 18. Click- and Pop-Free Shutdown and Restart Sequence Timing Diagram
28
Copyright © 2011, Texas Instruments Incorporated
TAS5414B-Q1
TAS5424B-Q1
www.ti.com
SLOS673 –DECEMBER 2011
Latched Fault Shutdown and Restart Sequence Control
tI2C_CL
tDEGLITCH
tCM
tDEGLITCH
tGAIN
PVDD Normal Operating Region
PVDD UV Hysteresis Region
UV
Detect
UV
Reset
PVDD
VUV + VUV_HY
VUV
VPOR
HIZ_x
Internal I2C Write
MUTE_Report
UV_DET
Cleared by
External I2C Read
External I2C Read
to Fault Register 1
UV_LATCH
FAULT Pin
MUTE Pin
Pop
OUTx_P (Filtered)
T0194-02
Figure 19. Latched Global Fault Shutdown and Restart Timing Diagram
(UV Shutdown and Recovery)
Copyright © 2011, Texas Instruments Incorporated
29
TAS5414B-Q1
TAS5424B-Q1
SLOS673 –DECEMBER 2011
www.ti.com
tI2C_CL
tDEGLITCH
tCM
tDEGLITCH
tGAIN
PVDD Normal Operating Region
UV
Detect
UV
Reset
PVDD
VUV + VUV_HY
PVDD UV Hysteresis Region
VUV
VPOR
Internal I2C Write
HIZ_Report_1
HIZ_Report_2,3,4
MUTE_Report
UV_DET
Cleared by
External I2C Read
External I2C Read
to Fault Register 1
UV_LATCH
FAULT Pin
MUTE Pin
Pop
Pop
Pop
OUT1_P (Filtered)
OUT2,3,4_P (Filtered)
T0195-02
Figure 20. Latched Global Fault Shutdown and Individual Channel Restart Timing Diagram
(UV Shutdown and Recovery)
30
Copyright © 2011, Texas Instruments Incorporated
TAS5414B-Q1
TAS5424B-Q1
www.ti.com
SLOS673 –DECEMBER 2011
APPLICATION INFORMATION
Figure 21. TAS5414B-Q1 Typical Application Schematic
Parallel Operation (PBTL)
The device can drive more current paralleling BTL channels on the load side of the LC output filter. For parallel
operation, identical I2C settings are required for any two paralleled channels in order to have reliable system
Copyright © 2011, Texas Instruments Incorporated
31
TAS5414B-Q1
TAS5424B-Q1
SLOS673 –DECEMBER 2011
www.ti.com
performance and even power dissipation on multiple channels. For smooth power up, power down, and mute
operation, the same control commands (such as mute, play, Hi-Z, etc.) should be sent to the paralleled channels
at the same time. Load diagnostic is also supported for parallel connection. Paralleling on the device side of the
LC output filter is not supported, and can result in device failure. When paralleling channels it is important to
monitor channels for thermal foldback and lower the system gain for paralleled channels.
Input Filter Design
For the TAS5424B-Q1 device, the input filter for a single channel's P and M inputs should be identical. For the
TAS5414B-Q1 the IN_M pin should have an impedance to GND that is equivalent to the parallel combination of
the input impedances of all IN_P channels combined, including any source impedance from the previous stage in
the system design. For example, if each of the 4 IN_P channels have a 1uF DC blocking capacitor, 1kΩ of series
resistance due to an input RC filter, and 1kΩ of source resistance from the DAC supplying the audio signal, then
the IN_M channel should have a 4uF capacitor in series with a 500Ω resistor to GND (4 x 1uF in parallel = 4uF;
4 x 2kΩ in parallel = 500Ω).
Demodulation Filter Design
The amplifier outputs are driven by high-current LDMOS transistors in an H-bridge configuration. These
transistors are either fully off or on. The result is a square-wave output signal with a duty cycle that is
proportional to the amplitude of the audio signal. It is recommended that a second-order LC filter be used to
recover the audio signal. The main purpose of the demodulation filter is to attenuate the high-frequency
components of the output signals that are out of the audio band. Design of the demodulation filter significantly
affects the audio performance of the power amplifier. Therefore, to meet the system THD+N needs, the selection
of the inductors used in the output filter should be carefully considered. The rule is that the inductance should
stay above 10% of the inductance value within the range of peak current seen at maximum output power in the
system design.
Line Driver Applications
In many automotive audio applications the end user would like to use the same head unit to drive either a
speaker (with several Ohms of impedance) or an external amplifier (with several kOhms of impedance). The
design is capable of supporting both applications; however, the output filter and system must be designed to
handle the expected output load conditions.
Thermal Information
The thermally augmented package is designed to interface directly to heat sinks using a thermal interface
compound (for example, Artic Silver, Ceramique thermal compound.) The heat sink then absorbs heat from the
ICs and couples it to the local air. If louvers or fans are supplied, this process can reach equilibrium and heat can
be continually removed from the ICs. Because of the device efficiency heat sinks can be smaller than those
required for linear amplifiers of equivalent performance.
RθJA is a system thermal resistance from junction to ambient air. As such, it is a system parameter with the
following components:
•
•
•
RθJC (the thermal resistance from junction to case, or in this case the heat slug)
Thermal grease thermal resistance
Heat sink thermal resistance
The thermal grease thermal resistance can be calculated from the exposed heat slug area and the thermal
grease manufacturer's area thermal resistance (expressed in °C-in2/W or °C-mm2/W). The area thermal
resistance of the example thermal grease with a 0.001-inch (0.0254-mm) thick layer is about 0.007°C-in2/W
(4.52°C-mm2/W). The approximate exposed heat slug size is as follows:
36/44-pin PSOP3
64-pin QFP
0.124 in2 (80 mm2)
0.099 in2 (64 mm2)
Dividing the example thermal grease area resistance by the area of the heat slug gives the actual resistance
through the thermal grease for both parts:
32
Copyright © 2011, Texas Instruments Incorporated
TAS5414B-Q1
TAS5424B-Q1
www.ti.com
SLOS673 –DECEMBER 2011
36/44-pin PSOP3
64-pin QFP
0.06°C/W
0.07°C/W
The thermal resistance of thermal pads is generally considerably higher than a thin thermal grease layer.
Thermal tape has an even higher thermal resistance and should not be used at all. Heat sink thermal resistance
generally is predicted by the heat sink vendor, modeled using a continuous flow dynamics (CFD) model, or
measured.
Thus, for a single monaural channel in the IC, the system RθJA = RθJC + thermal grease resistance + heat sink
resistance.
The following table indicates modeled parameters for one device on a heat sink. The junction temperature is set
at 115°C while delivering 20 Wrms per channel into 4-Ω loads with no clipping. It is assumed that the thermal
grease is about 0.001 inches (0.0254 mm) thick.
Device
Ambient temperature
36-Pin PSOP3
25°C
Power to load
20 W × 4
1.90 W × 4
7.6°C
Power dissipation
ΔT inside package
ΔT through thermal grease
Required heatsink thermal resistance
Junction temperature
System RθJA
0.46°C
10.78°C/W
115°C
11.85°C/W
90°C
RθJA × power dissipation
Electrical Connection of Heat Slug and Heat Sink
The heat sink connected to the heat slug of the device should be connected to GND or left floating. The heat
slug should not be connected to any other electrical node.
Copyright © 2011, Texas Instruments Incorporated
33
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TAS5414BTPHDQ1
TAS5414BTPHDRQ1
ACTIVE
ACTIVE
HTQFP
HTQFP
PHD
PHD
64
64
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TAS5414BTPHDRQ1
HTQFP
PHD
64
1000
330.0
24.4
17.0
17.0
1.5
20.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTQFP PHD 64
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
TAS5414BTPHDRQ1
1000
Pack Materials-Page 2
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