TAS5441-Q1 [TI]
具有负载突降保护和 I2C 诊断功能的 22W 模拟输入单通道汽车级 D 类音频放大器;
| 型号： | TAS5441-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有负载突降保护和 I2C 诊断功能的 22W 模拟输入单通道汽车级 D 类音频放大器 放大器 音频放大器 |
| 文件： | 总36页 (文件大小：1687K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TAS5441-Q1
ZHCSL26B –APRIL 2020 –REVISED JANUARY 2023
TAS5441-Q1 22 具有负载突降和I2C 诊断功能的W 具有负载突降和I2C 诊断功
能的模拟输入单通道汽车D 类音频放大器
1 特性
2 应用
• 符合汽车应用要求的AEC-Q100 标准
• 汽车类紧急呼叫(eCall) 放大器
• 车载通讯系统
• 仪表板系统
– 温度等级1: –40 ° C 至125 ° C 、T A
• 单声道BTL 数字功率放大器
• 22 负载为4Ω且THD+N 为10% 时的输出功率为
W
• 4.5V 至18V 运行电压范围
• 负载为4Ω时的效率为85%
• 差分模拟输入
• 采用可调功率限制器的Speaker Guard™ 扬声器保
护
• 75dB 电源抑制比(PSRR)
• 负载诊断功能：
• 信息娱乐音频
3 说明
TAS5441-Q1 是一款单声道 D 类音频放大器，适用于
汽车类紧急呼叫 (eCall)、远程信息处理、仪表组和信
息娱乐系统应用。该器件采用 14.4 VDC 汽车电池供
电，可在负载为 4Ω 且 THD+N 不超过 10% 的情况下
提供高达 22W 的功率。该器件具有宽工作电压范围和
优异的效率，是需要启停支持或使用备用电池运行时的
理想选择。集成的负载突降保护能够缩减外部电压钳位
电路的成本与尺寸，板载负载诊断功能能够通过 I2C 报
告扬声器状态。
– 开路和短路输出负载
– 输出到电源和输出到接地短接
• 保护和监控功能：
– 短路保护
器件信息
封装(1)
– 40V 负载突降保护符合ISO-7637-2 标准
– 在音乐播放的同时进行输出直流电平检测
– 过热保护
封装尺寸（标称值）
器件型号
TAS5441-Q1
HTSSOP (16)
5.00mm x 4.40mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 欠压和过压保护
• 采用PowerPAD™ 封装（焊盘朝下）的耐热增强型
16 引脚HTSSOP (PWP) 封装
• 旨在满足汽车电磁兼容性(EMC) 要求
• ISO9000：已通过2002 TS16949 认证
• 待机时40V 负载突降保护
• 待机时无阻塞I2C
简化版方框图
输出功率效率
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLOSE41
TAS5441-Q1
ZHCSL26B –APRIL 2020 –REVISED JANUARY 2023
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes..........................................17
7.5 Register Maps...........................................................18
8 Application and Implementation..................................20
8.1 Application Information............................................. 20
8.2 Typical Application.................................................... 20
8.3 Power Supply Recommendations.............................23
8.4 Layout....................................................................... 24
9 Device and Documentation Support............................28
9.1 Device Support......................................................... 28
9.2 Documentation Support............................................ 28
9.3 接收文档更新通知..................................................... 28
9.4 支持资源....................................................................28
9.5 Trademarks...............................................................28
9.6 静电放电警告............................................................ 28
9.7 术语表....................................................................... 28
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Timing Requirements for I2C Interface Signals...........7
6.7 Typical Characteristics................................................8
7 Detailed Description......................................................10
7.1 Overview...................................................................10
7.2 Functional Block Diagram.........................................10
7.3 Feature Description...................................................11
Information.................................................................... 28
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (June 2020) to Revision B (January 2023)
Page
• Changed Voltage gain minimum/maximum values in Electrical Characteristics table........................................5
• Added minimum value to Overcurrent (OC) Shutdown Protection in Electrical Characteristics table ............... 5
Changes from Revision * (April 2020) to Revision A (June 2020)
Page
• 将数据表状态从预告信息更改为生产数据.........................................................................................................1
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5 Pin Configuration and Functions
16
15
14
13
GND
GND
1
2
STANDBY
PVDD
FAULT
BYP
SDA
3
4
BSTP
OUTP
OUTN
BSTN
GND
Thermal Pad
12
11
10
9
SCL
IN_P
5
6
7
8
IN_N
MUTE
Not to scale
图5-1. PWP Package, 16-Pin, TSSOP With Exposed Thermal Pad (Top View)
表5-1. Pin Functions Table
PIN
TYPE(1)
DESCRIPTION
NAME
BSTN
NO.
10
AI
AI
Bootstrap for negative-output high-side FET
BSTP
BYP
13
Bootstrap for positive-output high-side FET
3
PBY
DO
GND
AI
Voltage-regulator bypass-capacitor pin
FAULT
GND
14
Active-low open-drain output used to report faults
1, 9, 16
Ground
IN_N
7
6
Inverting analog input
IN_P
AI
Non-inverting analog input
MUTE
OUTN
OUTP
PVDD
SCL
8
DI
Mute input, active-high (no internal pullup or pulldown)
11
12
15
5
PO
PO
PWR
DI
Output (–)
Output (+)
Power supply
I2C clock
SDA
4
DI/DO
DI
I2C data
STANDBY
Thermal pad
2
Active-low STANDBY pin (no internal pullup or pulldown)
Must be soldered to ground
—
—
(1) DI = digital input, DO = digital output, AI = analog input, PWR = power supply, PBY = power bypass, PO = power output, GND =
ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
–0.3
–1
MAX
30
40
15
5
UNIT
V
DC supply voltage range, V(PVDD)
Pulsed supply voltage range, V(PVDD_MAX)
Supply voltage ramp rate, ΔV(PVDD_RAMP)
For SCL, SDA, and STANDBY, FAULT pins
For IN_N, IN_P, , and MUTE pins
BYP
Relative to GND
t ≤400 ms exposure
V/ms
Relative to GND
Relative to GND
Relative to GND
Relative to BYP
Relative to GND
Relative to GND
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
Input voltage
6.5
7
V
BSTN, BSTP
30
36.3
30
±4
±1
7
BSTN, BSTP
OUTN, OUTP
DC current on PVDD, GND and OUTx pins, I(PVDD), IO
A
(2)
Current
Maximum current, on all input pins, I(IN_MAX)
mA
°C
Maximum sink current for open-drain pin, I(IN_ODMAX)
Storage temperature, Tstg
150
–55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) See the section for information on analog input voltage and ac coupling.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level H2
±3500
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C5
±1000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
4.5
5
NOM
14.4
14.4
MAX
UNIT
18
4-Ω±20% load (or higher)
2-Ω±20% load
Supply voltage range relative to GND. Includes
ac transients, requires proper decoupling.(3)
V(PVDD_OP)
V
18
1
V(PVDD_RIPPLE)
V(MUTE)
Maximum ripple on PVDD
V(PVDD) < 8 V
Vpp
V
MUTE pin voltage range relative to GND
Analog audio input-signal level
-0.3
0
3.3
5.5
(1)
0.25–1(2)
V(AIN)
AC-coupled input voltage
Vrms
MUTE and STANDBY pins input voltage for
logic-level high
V(IH_STANDBY)
V(IL_STANDBY)
V(IH_SCL)
2
V
V
V
V
V
MUTE and STANDBY pins input voltage for
logic-level low
0.7
R(PU_I2C) = 4.7-kΩpullup, supply voltage = 3.3
V or 5 V
SCL pin input voltage for logic-level high
SDA pin input voltage for logic-level high
SCL pin input voltage for logic-level low
2.1
2.1
R(PU_I2C) = 4.7-kΩpullup, supply voltage = 3.3
V or 5 V
V(IH_SDA)
R(PU_I2C) = 4.7-kΩpullup, supply voltage = 3.3
V or 5 V
V(IL_SCL)
1.1
R(PU_I2C) = 4.7-kΩpullup, supply voltage = 3.3
V or 5 V
V(IL_SDA)
TA
SDA pin input voltage for logic-level low
Ambient temperature
1.1
V
125
°C
–40
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6.3 Recommended Operating Conditions (continued)
MIN
NOM
MAX
UNIT
When using low-impedance loads, do not
exceed overcurrent limit.
R(L)
Nominal speaker load impedance
2
4
16
Ω
Pullup voltage supply (for open-drain logic
outputs)
V(PU) must be less than (V(PVDD) - 1V) during
normal operation.
V(PU)
3
3.3
5.5
V
External pullup resistor on open-drain logic
outputs
Resistor connected between open-drain logic
output and V(PU) supply.
R(PU_EXT)
R(PU_I2C)
C(PVDD)
10
1
50
10
kΩ
kΩ
μF
I2C pullup resistance on SDA and SCL pins
4.7
10
External capacitor on the PVDD pin, typical
value ± 20%(3)
External capacitor on the BYP pin, typical
value ± 10%
C(BYP)
C(OUT)
C(IN)
1
μF
μF
μF
External capacitance to GND on OUT_X pins
4
External capacitance to analog input pin in
series with input signal
1
External boostrap capacitor, typical value ±
20%
C(BSTN), C(BSTP)
220
nF
(1) Signal input for full unclipped output with gains of 36 dB, 32 dB, 26 dB, and 20 dB
(2) Maximum recommended input voltage is determined by the gain setting.
(3) See the section.
6.4 Thermal Information
TAS5441
THERMAL METRIC(1)
PWP (HTSSOP)
UNIT
16 PINS
39.4
24.9
20
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.6
ψJT
19.8
2
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
TC = 25°C, PVDD = 14.4 V, RL = 4 Ω, P(O) = 1 W/ch, AES17 filter, default I2C settings (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
OPERATING CURRENT
PVDD idle current
PVDD standby current
OUTPUT POWER
In PLAY mode, no audio present
16
5
mA
STANDBY mode, MUTE = 0 V
20
µA
18
22
4 Ω, THD+N ≤1%, 1 kHz, TC = 75°C
4 Ω, THD+N = 10%, 1 kHz, TC = 75°C
4 Ω, P(O) = 22 W (10% THD)
Output power per channel
W
Power efficiency
85%
AUDIO PERFORMANCE
Noise voltage at output
G = 20 dB, zero input, and A-weighting
f = 1 kHz, 100 mVrms referenced to GND, G = 20 dB
PVDD = 14.4 Vdc + 1 Vrms, f = 1 kHz
P(O) = 1 W, f = 1 kHz
65
63
µV
dB
Common-mode rejection ratio
Power-supply rejection ratio
Total harmonic distortion + noise
75
0.05%
400
Switching frequency selectable for AM interference
avoidance
Switching frequency
kHz
500
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6.5 Electrical Characteristics (continued)
TC = 25°C, PVDD = 14.4 V, RL = 4 Ω, P(O) = 1 W/ch, AES17 filter, default I2C settings (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Internal common-mode input bias voltage
Internal bias applied to IN_N, IN_P pins
3
V
19.25
25.25
31.25
35.25
20
26
32
36
20.75
Source impedance = 0 Ω, register 0x03 bits 7–6 = 00
Source impedance = 0 Ω, register 0x03 bits 7–6 = 01
Source impedance = 0 Ω, register 0x03 bits 7–6 = 10
Source impedance = 0 Ω, register 0x03 bits 7–6 = 11
26.75
dB
32.75
Voltage gain (VO / VIN
)
36.75
PWM OUTPUT STAGE
FET drain-to-source resistance
Output offset voltage
TJ = 25°C
180
mΩ
Zero input signal, G = 20 dB
±25
mV
PVDD OVERVOLTAGE (OV) PROTECTION
PVDD overvoltage-shutdown set
PVDD overvoltage-shutdown hysteresis
PVDD UNDERVOLTAGE (UV) PROTECTION
PVDD undervoltage-shutdown set
PVDD undervoltage-shutdown hysteresis
BYP
19.5
3.6
21
22.5
V
V
0.6
4
4.4
V
V
0.25
BYP pin voltage
6.4
6.9
0.3
7.4
4.1
V
POWER-ON RESET (POR)
PVDD voltage for POR
V
V
PVDD recovery hysteresis voltage for POR
OVERTEMPERATURE (OT) PROTECTION
Junction temperature for overtemperature shutdown
155
170
15
°C
°C
Junction temperature overtemperature shutdown
hystersis
OVERCURRENT (OC) SHUTDOWN PROTECTION
Maximum current (peak output current) (1)
STANDBY PIN
2.45
3.5
0.1
2.9
A
STANDBY pin current
0.2
µA
DC DETECT
DC detect threshold
V
DC detect step response time
FAULT REPORT
700
ms
FAULT pin output voltage for logic-level high (open-drain
logic output)
2.4
V
V
External 47-kΩpullup resistor to 3.3 V
External 47-kΩpullup resistor to 3.3 V
FAULT pin output voltage for logic-level low (open-drain
logic output)
0.5
LOAD DIAGNOSTICS
Resistance to detect a short from OUT pins to PVDD or
ground
200
Ω
Open-circuit detection threshold
Short-circuit detection threshold
I2C
Including speaker wires
Including speaker wires
70
95
120
1.5
Ω
Ω
0.9
1.2
SDA pin output voltage for logic-level high
SDA pin output voltage for logic-level low
Capacitance for SCL and SDA pins
Capacitance for SDA pin
2.4
V
V
R(PU_I2C) = 4.7-kΩpullup, supply voltage = 3.3 V or 5 V
3-mA sink current
0.4
10
pF
pF
STANDBY mode
30
(1) This parameter is validated by design and verified during product characterization. It is not tested in production.
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6.6 Timing Requirements for I2C Interface Signals
over recommended operating conditions (unless otherwise noted)
MIN
NOM
MAX
400
300
300
UNIT
kHz
ns
f(SCL)
tr
SCL clock frequency
Rise time for both SDA and SCL signals
Fall time for both SDA and SCL signals
SCL pulse duration, high
tf
ns
tw(H)
tw(L)
tsu(2)
th(2)
tsu(1)
th(1)
tsu(3)
C(B)
0.6
1.3
0.6
0.6
100
0(1)
0.6
µs
SCL pulse duration, low
µs
Setup time for START condition
START condition hold time before generation of first clock pulse
Data setup time
µs
µs
ns
Data hold time
ns
Setup time for STOP condition
Load capacitance for each bus line
µs
400
pF
(1) A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of
SCL.
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6.7 Typical Characteristics
TC = 25°C, PVDD = 14.4 V, RL = 4 Ω, P(O) = 1 W/ch, AES17 filter, 1-kHz input, default I2C settings (unless
otherwise noted)
10
2 W
4 W
1
0.1
0.01
0.01
0.1
1
Output Power (W)
10
30
D002
图6-2. THD+N vs Output Power
Gain = 26 dB
f(SW) = 400 kHz
TA = 25°C
V(PVDD) = 14.4 V
图6-1. Efficiency vs Output Power
1
30
25
20
15
10
5
2 W, 1 W
2 W, 5 W
4 W, 1 W
4 W, 5 W
2 W, 1% THD
2 W, 10% THD
4 W, 1% THD
4 W, 10% THD
0.1
0.01
0.001
0
20
100
1k
Frequency (Hz)
10k 20k
5
6
7
8
9
Supply Voltage (V)
10 11 12 13 14 15 16
D004
D003
图6-4. THD+N vs Frequency
图6-3. Output Power vs PVDD
0
0
-20
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
0
2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k 24k
Frequency (Hz)
0
2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k 24k
Frequency (Hz)
D005
D006
图6-5. Noise FFT With –60-dB Output
图6-6. Noise FFT With 1-W Output
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4
3.5
3
2.5
2
1.5
1
0.5
0
25
35
45
55
65
75
Ambient Temperature (ºC)
85
95 105 115 125
D007
图6-7. Overcurrent Threshold vs Temperature
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7 Detailed Description
7.1 Overview
The TAS5441-Q1 is a mono analog-input class-D audio amplifier for use in an automotive environment. The
design uses an ultra-efficient class-D technology developed by Texas Instruments with additional features
specific to the automotive industry. The class-D technology allows for reduced power consumption, reduced
heat, and reduced peak currents in the electrical system. The device realizes an audio sound system design with
smaller size and lower weight than traditional class-AB devices.
The TAS5441-Q1 device has seven core design blocks:
• PWM
• Gate drive
• Power FETs
• Diagnostics
• Protection
• Power supply
• I2C serial communication bus
7.2 Functional Block Diagram
Overcurrent Detection
PVDD
SDA
SCL
LDO
Regulator
DC Detection
Biases
and
References
GVDD
I2C
Protection
Control
BYP
Thermal Protection
Voltage Protection
GVDD
BSTN
Short-to-Ground
Short-to-Power
Shorted Load
Open Load
PVDD
Control
Diagnostics
Control
FAULT
MUTE
Gate
Drive
OUTN
STANDBY
GND
Pulse
Width
GVDD
IN_N
IN_P
Gain
Control
Speaker
Guard
Preamplifier
BSTP
Modulator
(PWM)
PVDD
GND
Gate
Drive
OUTP
GND
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7.3 Feature Description
7.3.1 Analog Audio Input and Preamplifier
The differential input stage of the amplifier cancels common-mode noise that appears on the inputs. For a
differential audio source, connect the positive lead to IN_P and the negative lead to IN_N. The inputs must be
ac-coupled to minimize the output dc-offset and make sure of correct ramping of the output voltages. For good
transient performance, the impedance seen at each of the two differential inputs is the same.
The gain setting impacts the analog input impedance of the amplifier. See Input Impedance and Gain for typical
values.
表7-1. Input Impedance and Gain
Gain
20 dB
26 dB
32 dB
36 dB
Input Impedance
60 kΩ± 20%
30 kΩ± 20%
15 kΩ± 20%
9 kΩ± 20%
7.3.2 Pulse-Width Modulator (PWM)
The PWM converts the analog signal from the preamplifier into a switched signal of varying duty cycle. This is
the critical stage that defines the class-D architecture. In the TAS5441-Q1, the modulator is an advanced design
with high bandwidth, low noise, low distortion, and excellent stability.
The pulse-width modulation scheme allows increased efficiency at low power. Each output is switching from 0 V
to PVDD. The OUTP and OUTN pins are in phase with each other with no input so that there is little or no
current in the speaker. The duty cycle of OUTP is greater than 50% and the duty cycle OUTN is less than 50%
for positive output voltages. The duty cycle of OUTN is greater than 50% and the duty cycle of OUTP is less than
50% for negative output voltages. The voltage across the load is at 0 V through most of the switching period,
reducing power loss.
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OUTP
OUTN
No Output
OUTP – OUTN
0 V
0 A
Speaker
Current
OUTP
OUTN
Positive Output
PVDD
0 V
OUTP – OUTN
Speaker
Current
0 A
OUTP
OUTN
Negative Output
0 V
OUTP – OUTN
–PVDD
0 A
Speaker
Current
图7-1. BD Mode Modulation
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7.3.3 Gate Drive
The gate driver accepts the low-voltage PWM signal and level-shifts the signal to drive a high-current, full-bridge,
power FET stage. The device uses proprietary techniques to optimize EMI and audio performance.
7.3.4 Power FETs
The BTL output comprises four matched N-channel FETs for high efficiency and maximum power transfer to the
load. By design, the FETs withstand large voltage transients during a load-dump event.
7.3.5 Load Diagnostics
The device incorporates load diagnostic circuitry designed for detecting and determining the status of output
connections. The device supports the following diagnostics:
• Short to GND
• Short to PVDD
• Short across load
• Open load
The device reports the presence of any of the short or open conditions to the system via I2C register read.
7.3.5.1 Load Diagnostics Sequence
The load diagnostic function runs on de-assertion of STANDBY or when the device is in a fault state (dc detect,
overcurrent, overvoltage, undervoltage, and overtemperature). During this test, the outputs are in a Hi-Z state.
The device determines whether the output is a short to GND, short to PVDD, open load, or shorted load. The
load diagnostic biases the output, which therefore requires limiting the capacitance value for proper functioning;
see the Recommended Operating Conditions. The load diagnostic test takes approximately 229 ms to run. Note
that the check phase repeats up to five times if a fault is present or a large capacitor to GND is present on the
output. On detection of an open load, the output still operates. On detection of any other fault condition, the
output goes into a Hi-Z state, and the device checks the load continuously until removal of the fault condition.
After detection of a normal output condition, the audio output starts. The load diagnostics run after every other
overvoltage (OV) event. The load diagnostic for open load only has I2C reporting. All other faults have I2C and
FAULT pin assertion.
The device performs load diagnostic tests as shown in 图7-2.
图7-3 illustrates how the diagnostics determine the load based on output conditions.
Discharge
(75 ms)
Ramp Up
(52 ms)
Check
(50 ms)
Ramp Down
(52 ms)
图7-2. Load Diagnostics Sequence of Events
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Output Conditions
Load Diagnostics
Open Load
Open Load Detected
OL Max
OL Min
SL Max
SL Min
Normal or Open Load
May Be Detected
Open Load (OL)
Detection Threshold
Normal
Load
Play Mode
Shorted Load (SL)
Detection Threshold
Normal or Shorted Load
May Be Detected
Shorted Load
Detected
Shorted
Load
图7-3. Load Diagnostic Reporting Thresholds
7.3.5.2 Faults During Load Diagnostics
If the device detects a fault (such as overtemperature, overvoltage, or undervoltage) during the load diagnostics
test, the device exits the load diagnostics, which can result in a pop or click on the output.
7.3.6 Protection and Monitoring
• Overcurrent Shutdown (OCSD): The overcurrent shutdown forces the output into Hi-Z. The device asserts
the FAULT pin and updates the I2C register.
• DC Detect: This circuit checks for a dc offset continuously during normal operation at the output of the
amplifier. If a dc offset occurs, the device asserts the FAULT pin and updates the I2C register. Note that the
dc detection threshold follows PVDD changes.
• Overtemperature Shutdown (OTSD): The device shuts down when the die junction temperature reaches
the overtemperature threshold. The device asserts the FAULT pin asserts and updates I2C register. Recovery
is automatic when the temperature returns to a safe level.
• Undervoltage (UV): The undervoltage (UV) protection detects low voltages on PVDD. In the event of an
undervoltage condition, the device asserts the FAULT pin and resets the I2C register.
• Power-On Reset (POR): Power-on reset (POR) occurs when PVDD drops below the POR threshold. A POR
event causes the I2C bus to go into a high-impedance state. After recovery from the POR event, the device
restarts automatically with default I2C register settings.
• Overvoltage (OV) and Load Dump: OV protection detects high voltages on PVDD. If PVDD reaches the
overvoltage threshold, the device asserts the FAULT pin and updates the I2C register. The device can
withstand 40-V load-dump voltage spikes. The device supports load-dump in both standby and active modes.
• SpeakerGuard: This protection circuitry limits the output voltage to the value selected in I2C register 0x03.
This value determines both the positive and negative limits. The user can use the SpeakerGuard feature to
improve battery life or protect the speaker from exceeding the excursion limits.
• Adjacent-Pin Shorts: The device design is such that shorts between adjacent pins do not cause damage.
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7.3.7 I2C Serial Communication Bus
The device communicates with the system processor via the I2C serial communication bus as an I2C slave-only
device. The processor can poll the device via I2C to determine the operating status. All reports of fault conditions
and detections are via I2C. The system can also set numerous features and operating conditions via I2C. The I2C
interface is active approximately 1 ms after the STANDBY pin is high.
The I2C interface controls the following device features:
• Changing gain setting to 20 dB, 26 dB, 32 dB, or 36 dB.
• Controlling peak voltage value of SpeakerGuard protection circuitry
• Reporting load diagnostic results
• Changing of switching frequency for AM radio avoidance
7.3.7.1 I2C Bus Protocol
The device has a bidirectional serial control interface that is compatible with the Inter IC (I2C) bus protocol and
supports 400-kbps data transfer rates for random and sequential write and read operations. This is a slave-only
device that does not support a multimaster bus environment or wait-state insertion. The master device uses the
I2C control interface to program the registers of the device and to read device status.
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data transfer on the bus is serial, one bit at a time. The transfer of address and data is in byte (8-bit)
format with the most-significant bit (MSB) transferred first. In addition, the receiving device acknowledges each
byte transferred on the bus with an acknowledge bit. Each transfer operation begins with the master device
driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus
uses transitions on the data pin (SDA) while the clock is HIGH to indicate start and stop conditions. A HIGH-to-
LOW transition on SDA indicates a start, and a LOW-to-HIGH transition indicates a stop. Normal data bit
transitions must occur within the low time of the clock period. 图 7-4 shows these conditions. The master
generates the 7-bit slave address and the read/write (R/ W) bit to open communication with another device and
then waits for an acknowledge condition. The device holds SDA LOW during the acknowledge clock period to
indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence. The
address for each device is a unique 7-bit slave address plus a R/ W bit (1 byte). All compatible devices share the
same signals via a bidirectional bus using a wired-AND connection. The SDA and SCL signals require the use of
an external pullup resistor to set the HIGH level for the bus. There is no limit on the number of bytes that the
communicating devices can transmit between start and stop conditions. After transfer of the last word, the
master generates a stop condition to release the bus.
8-Bit Register Data For
Address (N)
8-Bit Register Data For
Address (N)
R/
W
8-Bit Register Address (N)
7-Bit Slave Address
A
A
A
A
SDA
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SCL
Start
Stop
T0035-02
图7-4. Typical I2C Sequence
To communicate with the device, the I2C master uses addresses shown in 图7-4. Transmission of read and write
data can be by single-byte or multiple-byte data transfers.
7.3.7.2 Random Write
As shown in 图 7-5, a single-byte data-write transfer begins with the master device transmitting a start condition
followed by the I2C device address and the read/write bit. The read/write bit determines the direction of the data
transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct I2C device address and the
read/write bit, the device responds with an acknowledge bit. Next, the master transmits the address byte
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corresponding to the internal memory address being accessed. After receiving the address byte, the device
again responds with an acknowledge bit. Next, the master device transmits the data byte for writing to the
memory address being accessed. After receiving the data byte, the device again responds with an acknowledge
bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
R/W
A6 A5 A4 A3 A2 A1 A0
ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
I2C Device Address and
Read/Write Bit
Subaddress
Data Byte
Stop
Condition
T0036-05
图7-5. Random Write Transfer
7.3.7.3 Random Read
As shown in 图 7-6, a single-byte data-read transfer begins with the master device transmitting a start condition
followed by the I2C device address and the read/write bit. For the data-read transfer, the master device performs
both a write and a following read. Initially, the master device performs a write to transfer the address byte of the
internal memory address to be read. As a result, the read/write bit is a 0. After receiving the address and the
read/write bit, the device responds with an acknowledge bit. In addition, after sending the internal memory
address byte, the master device transmits another start condition followed by the device address and the read/
write bit again. This time, the read/write bit is a 1, indicating a read transfer. After receiving the address and the
read/write bit, the device again responds with an acknowledge bit. Next, the device transmits the data byte from
the memory address being read. After receiving the data byte, the master device transmits a not-acknowledge
followed by a stop condition to complete the single-byte data-read transfer.
Repeat Start
Condition
Not
Acknowledge
Start
Condition
Acknowledge
Acknowledge
A0 ACK
Acknowledge
A6 A5
A1 A0 R/W ACK A7 A6 A5 A4
A6 A5
A1 A0 R/W ACK D7 D6
D1 D0 ACK
I2C Device Address and
Read/Write Bit
Subaddress
I2C Device Address and
Read/Write Bit
Data Byte
Stop
Condition
T0036-03
图7-6. Random Read Transfer
7.3.7.4 Sequential Read
A sequential data-read transfer is identical to a single-byte data-read transfer except that the TAS5441-Q1
transmits multiple data bytes to the master device as shown in 图 7-7. Except for the last data byte, the master
device responds with an acknowledge bit after receiving each data byte and automatically increments the I2C
subaddress by one. After receiving the last data byte, the master device transmits a not-acknowledge followed
by a stop condition to complete the transfer.
Repeat Start
Condition
Not
Acknowledge
Start
Condition
Acknowledge
Acknowledge
A0 ACK
Acknowledge
Acknowledge
Acknowledge
D0 ACK D7
A6
A0 R/W ACK A7 A6 A5
A6
A0 R/W ACK D7
D0 ACK D7
D0 ACK
I2C Device Address and
Read/Write Bit
Subaddress
I2C Device Address and First Data Byte
Read/Write Bit
Other Data Bytes
Last Data Byte
Stop
Condition
T0036-07
图7-7. Sequential Read Transfer
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7.4 Device Functional Modes
7.4.1 Hardware Control Pins
Three discrete hardware pins are available for real-time control and indication of device status.
1. FAULT pin: This active-low open-drain output pin indicates the presence of a fault condition which requires
the device to go into the Hi-Z mode. On assertion of this pin, the device has protected itself and the system
from potential damage. The system can read the exact nature of the fault via I2C with the exception of PVDD
undervoltage faults below POR, in which case the I2C bus is no longer operational.
2. STANDBY pin: Assertion of this active-low pin sends the device into a complete shutdown, limiting the
current draw. Load-dump protection is supported. I2C is inactive and non-blocking (does not pull I2C bus low)
and the device registers are reset.
3. MUTE pin: On assertion of this active-high pin, the device is in mute mode. The output pins stop switching
and audio does not pass from the input to the output. To place the device back into play mode, deassert this
pin. The MUTE pin should be asserted low when the device is in STANDBY.
7.4.2 EMI Considerations
Automotive-level EMI performance depends on both careful integrated-circuit design and good system-level
design. Controlling sources of electromagnetic interference (EMI) was a major consideration in all aspects of the
design.
The design has minimal parasitic inductances due to the short leads on the package, which dramatically reduces
the EMI that results from current passing from the die to the system PCB. The design incorporates circuitry that
optimizes output transitions that cause EMI.
7.4.3 Operating Modes and Faults
The following tables list operating modes and faults.
表7-2. Operating Modes
STATE NAME
OUTPUT
OSCILLATOR
I2C (1)
STANDBY
Hi-Z, floating
Stopped
Inactive, Registers
Reset, Non-blocking
Load diagnostic
Mute (Hi-Z) / Fault
Play
DC biased
Hi-Z, floating
Active
Active
Active
Active
Active
Active
Switching with audio
(1) See SLOA264 for I2C applications.
表7-3. Faults and Actions
FAULT
EVENT
FAULT EVENT
CATEGORY
MONITORING
MODES
REPORTING
METHOD
ACTION
TYPE
ACTION
RESULT
CLEARING
STANDBY
POR
UV
Not applicable
Standby
Disabled
Voltage fault
Thermal fault
Mute (Hi-Z), Play
I2C + FAULT pin
OV and Load
dump(1)
Protected, No
Reporting
Hard mute (no ramp)
Hi-Z
OTSD
OC fault
DC detect
Mute (Hi-Z), Play
Play
Self-clearing
Output channel
fault
I2C + FAULT pin
Disabled
Load diagnostic -
short
Hi-Z, re-run
diagnostics
Diagnostic
Hi-Z
None
Load diagnostic -
open
Clears on next
diagnostic cycle
I2C
None
(1) Tested in accordance with ISO7637-1
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I2C ADDRESS
7.5 Register Maps
表7-4. I2C Address
FIXED ADDRESS
READ/WRITE BIT
DESCRIPTION
MSB
6
1
1
5
0
0
4
3
1
1
2
0
0
1
0
0
LSB
I2C write
I2C read
1
1
1
1
0
1
0xD8
0xD9
7.5.1 I2C Address Register Definitions
表7-5. I2C Address Register Definitions
ADDRESS
R/ W
REGISTER DESCRIPTION
0x01
R
Latched fault register
0x02
R
Status and load diagnostics register
Control register
0x03
R/ W
表7-6. Fault Register (0x01)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
0
0
0
0
0
0
0
No protection-created faults, default value
Reserved
1
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
1
–
–
–
–
1
–
–
–
1
–
–
1
–
1
Reserved
–
–
–
–
–
–
–
A load-diagnostics fault has occurred.
Overcurrent shutdown has occurred.
PVDD undervoltage has occurred.
PVDD overvoltage has occurred.
DC offset protection has occurred.
Overtemperature shutdown has occurred.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
表7-7. Status and Load Diagnostic Register (0x02)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
No speaker-diagnostic-created faults, default value
Output short to PVDD is present.
Output short to ground is present.
Open load is present.
0
0
0
0
0
0
0
0
1
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
1
–
–
–
–
1
–
–
–
1
–
–
1
–
1
–
–
–
–
–
–
–
–
–
–
–
–
–
Shorted load is present.
–
–
–
–
–
In a fault condition
–
–
–
–
Performing load diagnostics
In mute mode
–
–
–
–
–
In play mode
–
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表7-8. Control Register (0x03)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
1
1
1
1
0
0
0
26-dB gain, switching frequency set to 400 kHz , SpeakerGuard protection
circuitry disabled
1
Switching frequency set to 500 khz
–
–
–
–
–
–
–
–
–
0
–
–
–
–
–
–
–
–
–
0
–
–
1
–
–
1
–
–
0
–
–
1
1
-
Reserved
SpeakerGuard protection circuitry set to 14-V peak output
SpeakerGuard protection circuitry set to 11.8-V peak output
SpeakerGuard protection circuitry set to 9.8-V peak output
SpeakerGuard protection circuitry set to 8.4-V peak output
SpeakerGuard protection circuitry set to 7-V peak output
SpeakerGuard protection circuitry set to 5.9-V peak output
SpeakerGuard protection circuitry set to 5-V peak output
Gain set to 20 dB
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
0
0
0
–
–
–
–
–
–
–
–
–
1
0
Gain set to 32 dB
1
1
Gain set to 36 dB
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The device is a mono high-efficiency class-D audio amplifier. Typical use of the device is to amplify an audio
input to drive a speaker. The intent of use is for a bridge-tied load (BTL) application, not for support of single-
ended configuration. This section presents how to use the device in the application, including what external
components are necessary and how to connect unused pins.
8.2 Typical Application
PVDD
10µH 330µF
+
10µF 0.1µF
2.2nF 82nF 4.7µF 4.7µF
FAULT
SDA
FAULT
SDA
22µH
0.22µF
OUTP
BSPP
OUTP
0.01µF
3.3µF
SCL
SCL
IN_P
1µF
49.9kꢀ
5.6ꢀ
5.6ꢀ
IN_P
470pF
470pF
49.9kꢀ
IN_N
IN_N
1µF
OUTN
BSPN
MUTE
0.22µF
22µH
OUTN
0.01µF
MUTE
3.3µF
STANDBY
STANDBY
1µF
图8-1. TAS5441-Q1 Typical Application Schematic
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8.2.1 Design Requirements
Use the following for the design requirements:
• Power supplies
The device requires only a single power supply compliant with the recommended operation range. The
device is designed to work with either a vehicle battery or regulated power supply such as from a backup
battery.
• Communication
The device communicates with the system controller with both discrete hardware control pins and with I2C.
The device is an I2C slave and thus requires a master. If a master I2C-compliant device is not present in the
system, the device can still be used, but only with the default settings. Diagnostic information is limited to the
discrete reporting FAULT pin.
• External components
表8-1 lists the components required for the device.
表8-1. Supporting Components
EVM
QUANITY
VALUE
SIZE
DESCRIPTION
USE IN APPLICATION
DESIGNATOR
C7
1
1
3
2
2
2
1
1
1
2
2
1
10 μF ± 10%
330 μF ± 20%
1 μF ± 10%
1206
X7R ceramic capacitor, 25-V
Low-ESR aluminum capacitor, 25-V
X7R ceramic capacitor, 25-V
X7R ceramic capacitor, 25-V
X7R ceramic capacitor, 25-V
X7R ceramic capacitor, 250-V
X7R ceramic capacitor, 25-V
X7R ceramic capacitor, 50-V
X7R ceramic capacitor, 25-V
X7R ceramic capacitor, 25-V
X7R ceramic capacitor, 25-V
Power supply
C8
10 mm
0805
0603
0805
0603
0603
0603
0603
1206
0603
Power supply
C9, C16, C20
C10, C14
C11, C17
C13, C15
C6
Analog audio input filter, bypass
Bootstrap capacitors
Amplifier output filtering
Amplifier output snubbers
Power supply
0.22 μF ± 10%
3.3 μF ± 10%
470 pF ± 10%
0.1 μF ± 10%
2200 pF ± 10%
0.082 μF ± 10%
4.7 μF ± 10%
0.01 μF ± 10%
10 μH ± 20%
C2
Power supply
C3
Power supply
C4, C5
C12, C18
L1
Power supply
Output EMI filtering
Power supply
13.5 mm ×13.5 Shielded ferrite inductor
mm
L2
1
2
2
22 μH ± 20%
49.9 kΩ± 1%
5.6 Ω± 5%
8 mm × 8 mm Coupled inductor
Amplifier output filtering
Analog audio input filter
Output snubbers
R5, R6
R4, R7
0805
0805
Resistors, 0.125-W
Resistors, 0.125-W
8.2.1.1 Amplifier Output Filtering
Output FETs drive the amplifier outputs in an H-bridge configuration. These transistors are either fully off or on.
The result is a square-wave output signal with a duty cycle that is proportional to the amplitude of the audio
signal. The amplifier outputs require a low-pass filter to filter out the PWM modulation carrier frequency. People
frequently call this filter the L-C filter, due to the presence of an inductive element L and a capacitive element C
to make up the 2-pole low-pass filter. The L-C filter attenuates the carrier frequency, reducing electromagnetic
emissions and smoothing the current waveform which the load draws from the power supply. See Class-D LC
Filter Design for a detailed description on proper component selection and design of an L-C filter based upon the
desired load and response.
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8.2.1.2 Amplifier Output Snubbers
A snubber is an RC network placed at the output of the amplifier to dampen ringing or overshoot on the PWM
output waveform. Overshoot and ringing has several negative impacts including: potential EMI sources,
degraded audio performance, and overvoltage stress of the output FETs or board components. For more
information on the use and design of output snubbers, see Class-D Output Snubber Design Guide.
8.2.1.3 Bootstrap Capacitors
The output stage uses dual NMOS transistors; therefore, the circuit requires bootstrap capacitors for the high
side of each output to turn on correctly. The required capacitor connection is from BSTN to OUTN and from
BSTP to OUTP as shown in 图8-1.
8.2.1.4 Analog Audio Input Filter
The circuit requires an input capacitor to allow biasing of the amplifier put to the proper dc level. The input
capacitor and the input impedance of the amplifier form a high-pass filter with a –3-dB corner frequency
determined by the equation: f = 1 / (2πR(i)C(i)), where R(i) is the input impedance of the device based on the
gain setting and C(i) is the input capacitor value. 表 8-2 lists largest recommended input capacitor values. Use a
capacitor which matches the application requirement for the lowest frequency but does not exceed the values
listed.
表8-2. Recommended Input AC-Coupling Capacitors
GAIN (dB)
TYPICAL INPUT IMPEDANCE
INPUT CAPACITANCE (µF)
HIGH-PASS FILTER (Hz)
(kΩ)
1
2.7
1.8
5.3
1.6
2.3
1.8
20
26
60
30
1.5
1
3.3
5.6
10
32
36
15
9
8.2.2 Detailed Design Procedure
Use the following steps for the design procedure:
• Step 1: Hardware Schematic Design: Using the 图8-1 as a guide, integrate the hardware into the system
schematic.
• Step 2: Following the layout guidelines recommended in 节8.4.1, integrate the device and the supporting
components into the system PCB file.
• Step 3: Thermal Design: The device has an exposed thermal pad which requires proper soldering. For more
information, see Semiconductor and IC Package Thermal Metrics and PowerPAD Thermally Enhanced
Package.
• Step 4: Develop software: The EVM User's Guide has detailed instructions for how to set up the device,
interpret diagnostic information, and so forth. For information about control registers, see 节7.5.
For questions and support, go to the E2E forums.
8.2.2.1 Unused Pin Connections
Even if unused, always connect pins to a fixed rail; do not leave them floating. Floating input pins represent an
ESD risk, therefore the user must adhere to the following guidance for each pin.
8.2.2.1.1 MUTE Pin
If the MUTE pin is unused in the application, then connect the pin to GND through a high-impedance resistor.
8.2.2.1.2 STANDBY Pin
If the STANDBY pin is unused in the application, connect it to a low-voltage rail such as 3.3 V or 5 V through a
high-impedance resistor.
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8.2.2.1.3 I2C Pins (SDA and SCL)
If there is no microcontroller in the system, use of the device without I2C communication is possible. In this
situation, connect the SDA and SCL pins to 3.3 V.
8.2.2.1.4 Terminating Unused Outputs
If the FAULT pin does not report to a system microcontroller in the application, then connect the pin to GND.
8.2.2.1.5 Using a Single-Ended Audio Input
When using a single-ended audio source, ac-ground the negative input through a capacitor equal in value to the
input capacitor on the positive input, and apply the audio source to the positive input. For best performance, the
ac ground must be at the audio source instead of at the device input if possible.
8.2.3 Application Curves
See 节6.7 for application performance plots.
表8-3. Table of Graphs
GRAPH
FIGURE NO.
图6-1
Efficiency vs Output Power
THD+N vs Output Power
图6-2
Output Power vs PVDD
图6-3
THD+N vs Frequency
图6-4
Noise FFT With –60-dB Output
Noise FFT With 1-W Output
Overcurrent Threshold vs Temperature
图6-5
图6-6
图6-7
8.3 Power Supply Recommendations
A car battery that can have a large voltage range most commonly provides power for the device. PVDD, a
filtered battery voltage, is the supply for the output FETs and the low-side FET gate driver. Good power-supply
decoupling is necessary, especially at low voltage and temperature levels. To meet the PVDD specifications in
the Electrical Characteristics section, TI uses 10-µF and 0.1-µF ceramic capacitors near the PVDD pin along
with a larger bulk 330-µF electrolytic decoupling capacitor.
An internal linear regulator, which powers the analog circuitry, provides the voltage on the BYP pin. This supply
requires an external bypass ceramic capacitor at the BYP pin.
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8.4 Layout
8.4.1 Layout Guidelines
The EVM layout optimizes for thermal dissipation and EMC performance. The TAS5441-Q1 device has a thermal
pad down, and good thermal conduction and dissipation require adequate copper area. Layout also affects EMC
performance. TAS5411Q1EVM illustrations form the basis for the layout discussions.
8.4.2 Layout Examples
8.4.2.1 Top Layer
The red boxes around number 1 are the copper ground on the top layer. Soldered directly to the thermal pad, the
ground is the first significant thermal dissipation required. There are vias that go to the other layers for further
thermal relief, but vias have high thermal resistance. TI recommends that use of the top layer be mostly for
thermal dissipation. A further recommendation is short routes from output pins to the second-order LC filter for
EMC suppression. The number 2 arrow indicates these short routes for better ECM results. A short route from
the PVDD pin to the LC filter from the battery or power source, as indicated by the number 3 arrow, also
improves EMC suppression. Route on an outside layer for added current capability. The red box around number
4 indicates the ground plane that is common to both OUTP and OUTN. Place the capacitors of the LC filter in the
common ground plane to help with common-mode noise and short ground loops
图8-2. Top layer
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8.4.2.2 Second Layer –Signal Layer
Pour a full ground plane on an inner layer to keep current loops small to reduce EMI.
图8-3. Signal Layer
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8.4.2.3 Third Layer –Power Layer
There is no requirement for a power plane, but TI recommends a wide single wide trace to keep the switching
noise to a minimum and provide enough current to the device. The wide trace provides a low-impedance path
from the power source. Suppression of switching noise (ripple voltage) on both the positive and return (ground)
paths requires a low impedance.
图8-4. Power Layer
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8.4.2.4 Bottom Layer –Ground Layer
The device has an exposed thermal pad on the bottom side for improved thermal performance. Conducting heat
from the thermal pad to other layers requires thermal vias. Because the bottom layer is the secondary heat
exchange surface to ambient, the thermal vias area must have low thermal resistance.
图8-5. Bottom Layer
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9 Device and Documentation Support
9.1 Device Support
9.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
9.2 Documentation Support
9.2.1 Related Documentation
For related documentation see the following:
• AN-1737 Managing EMI in Class D Audio Applications (SNAA050)
• AN-1849 An Audio Amplifier Power Supply Design (SNAA057)
• Class-D LC Filter Design (SLOA119)
• Class-D Output Snubber Design Guide (SLOA201)
• Filter-Free™ Class-D Audio Amplifiers (SLOA145)
• Guidelines for Measuring Audio Power Amplifier Performance (SLOA068)
• Power Rating in Audio Amplifiers (SLEA047)
• PowerPAD Thermally Enhanced Package (SLMA002)
9.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.5 Trademarks
PowerPAD™ and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
9.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
9.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most-
current data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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18-Feb-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TAS5441QPWPRQ1
ACTIVE
HTSSOP
PWP
16
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TAS5441
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TAS5441QPWPRQ1
HTSSOP PWP
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP PWP 16
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
TAS5441QPWPRQ1
2000
Pack Materials-Page 2
PACKAGE OUTLINE
PWP0016B
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.6
6.2
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
0.19
B
0.1
C A
B
(0.15) TYP
SEE DETAIL A
4X 0.15 MAX
NOTE 5
2X 0.95 MAX
NOTE 5
THERMAL
PAD
0.25
GAGE PLANE
3.0
2.4
1.2 MAX
0.15
0.05
0 - 8
0.75
0.50
DETAIL A
TYPICAL
(1)
3.0
2.4
4218971/A 01/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0016B
PowerPADTM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.4)
NOTE 9
SOLDER MASK
DEFINED PAD
(3)
16X (1.5)
SYMM
SEE DETAILS
1
16
16X (0.45)
(1.1)
TYP
SYMM
(3)
(5)
NOTE 9
14X (0.65)
8
9
(
0.2) TYP
VIA
(1.1) TYP
METAL COVERED
BY SOLDER MASK
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-16
4218971/A 01/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0016B
PowerPADTM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3)
BASED ON
0.125 THICK
STENCIL
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
(3)
SYMM
BASED ON
0.125 THICK
STENCIL
14X (0.65)
9
8
SYMM
(5.8)
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.35 X 3.35
3 X 3 (SHOWN)
2.74 X 2.74
0.125
0.15
0.175
2.54 X 2.54
4218971/A 01/2016
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
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