TAS5613 [TI]
150W STEREO / 300W MONO PurePath™ HD ANALOG-INPUT POWER STAGE; 150W立体声/单声道300W的PurePath ™HD模拟输入功率级
| 型号： | TAS5613 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 150W STEREO / 300W MONO PurePath™ HD ANALOG-INPUT POWER STAGE |
| 文件： | 总27页 (文件大小：1420K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TAS5613
PurePath Digital
www.ti.com
SLAS676 –NOVEMBER 2009
150W STEREO / 300W MONO PurePath™ HD ANALOG-INPUT POWER STAGE
Check for Samples: TAS5613
1
FEATURES
•
Two Thermally Enhanced Package Options:
23
•
Active Enabled Integrated Feedback Provides:
(PurePath™ HD)
–
–
PHD (64-pin QFP)
DKD (44-pin PSOP3)
–
Signal Bandwidth up to 80kHz for High
Frequency Content From HD Sources
APPLICATIONS
•
•
•
•
•
Home Theater Systems
AV Receivers
DVD/ Blu-ray Disk™ Receivers
Mini Combo Systems
Active Speakers and Subwoofers
–
–
Ultra Low 0.03% THD at 1W into 4Ω
Flat THD at all Frequencies for Natural
Sound
–
–
–
80dB PSRR (BTL, No Input Signal)
>100dB (A Weighted) SNR
Click and Pop Free Startup and Stop
DESCRIPTION
•
•
Pin compatible with TAS5630, TAS5615 and
TAS5611
The TAS5613 is a high-performance analog input
Class
feedback technology (known as PurePath™ HD). It
has the ability to drive up to 150 W.(1) Stereo into 4Ω
speakers from a single 36V supply.
D amplifier with integrated closed loop
Multiple Configurations Possible on the Same
PCB:
–
–
–
Mono Parallel Bridge Tied Load (PBTL)
Stereo Bridge Tied Load (BTL)
PurePath™ HD technology enables traditional
AB-Amplifier performance (<0.03% THD) levels while
providing the power efficiency of traditional class D
amplifiers.
2.1 Single Ended (SE) Stereo Pair and
Bridge Tied Load Subwoofer
•
•
Total Output Power at 10%THD+N
Unlike traditional Class-D amplifiers, the distortion
curve only increases once the output levels move into
clipping.
–
–
300W in Mono PBTL Configuration
150W per Channel in Stereo BTL
Configuration
PurePath™ HD technology enables lower idle losses
making the device even more efficient.
Total Output Power in BTL Configuration at
1%THD+N
TOTAL HARMONIC DISTORTION+NOISE
VS
OUTPUT POWER
–
–
–
–
160W Stereo into 3Ω
125W Stereo into 4Ω
85W Stereo into 6Ω
65W Stereo into 8Ω
10
4Ohm (6kHz)
TC = 75 C
CONFIG = BTL
4Ohm (1kHz)
1
•
•
>90% Efficient Power Stage With 60-mΩ
Output MOSFETs
0,1
Self-Protection Design (Including
Undervoltage, Overtemperature, Clipping, and
Short Circuit Protection) With Error Reporting
0,01
•
EMI Compliant When Used With
Recommended System Design
0,001
0,01
1
100
PO - Output Power - W
(1) Achievable output power levels are dependent on the thermal
configuration of the target application. A high performance
thermal interface material between the package exposed
heatslug and the heat sink should be used to achieve high
output power levels
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
Blu-ray Disk is a trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TAS5613
SLAS676 –NOVEMBER 2009
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DEVICE INFORMATION
Terminal Assignment
The TAS5613 is available in two thermally enhanced packages:
•
•
64-Pin QFP (PHD) Power Package
44-Pin PSOP3 package (DKD)
The package type contains a heat slugs that is located on the top side of the device for convenient thermal
coupling to the heat sink.
PHD PACKAGE
(TOP VIEW)
DKD PACKAGE
(TOP VIEW)
PSU_REF
VDD
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
GVDD_AB
BST_A
2
OC_ADJ
RESET
3
PVDD_A
PVDD_A
OUT_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
4
OC_ADJ
RESET
C_STARTUP
INPUT_A
INPUT_B
VI_CM
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
GND_A
GND_B
GND_B
OUT_B
OUT_B
PVDD_B
PVDD_B
BST_B
BST_C
PVDD_C
PVDD_C
OUT_C
OUT_C
GND_C
GND_C
GND_D
C_STARTUP
INPUT_A
INPUT_B
VI_CM
5
6
7
8
GND
9
GND
AGND
VREG
10
11
12
13
14
15
16
17
18
19
20
21
22
AGND
VREG
9
INPUT_C
INPUT_D
FREQ_ADJ
OSC_IO+
OSC_IO-
SD
10
11
12
13
14
15
16
INPUT_C
INPUT_D
FREQ_ADJ
OSC_IO+
OSC_IO-
SD
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
OUT_D
PVDD_D
PVDD_D
BST_D
64-pins QFP package
OTW1
OTW
READY
M1
M2
M3
GVDD_CD
PIN ONE LOCATION PHD PACKAGE
Electrical Pin 1
Pin 1 Marker
White Dot
2
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TAS5613
TAS5613
www.ti.com
SLAS676 –NOVEMBER 2009
MODE SELECTION PINS
MODE PINS
ANALOG
OUTPUT
CONFIGURATION
DESCRIPTION
INPUT
M3
0
M2
0
M1
0
Differential
—
2 × BTL
—
AD mode
Reserved
BD mode
0
0
1
0
1
0
Differential
2 × BTL
Differential
(BTL)
Single Ended
(SE)
0
1
1
1
0
0
1
0
1
1 × BTL + 2 × SE
4 × SE
BTL = BD mode, SE = AD mode
AD mode
Single Ended
INPUT_C(1)
INPUT_D(1)
Differential
1 × PBTL
0
1
0
0
AD mode
BD mode
1
1
1
1
0
1
Reserved
(1) INPUT_C and D are used to select between a subset of AD and BD mode operations in PBTL mode (1=VREG and 0=GND).
PACKAGE HEAT DISSIPATION RATINGS(1)
PARAMETER
TAS5613PHD
TAS5613DKD
R
θJC (°C/W) – 2 BTL or 4 SE channels
3.2
5.4
2.1
3.5
RθJC (°C/W) – 1 BTL or 2 SE channel(s)
RθJC (°C/W) – 1 SE channel
7.9
5.1
(2)
Pad Area
64 mm2
80 mm2
(1) JC is junction-to-case, CH is case-to-heat sink
(2) θH is an important consideration. Assume a 2-mil thickness of typical thermal grease between the pad area and the heat sink and both
R
channels active. The RθCH with this condition is 1.22°C/W for the PHD package and 1.02°C/W for the DKD package.
Table 1. ORDERING INFORMATION(1)
TA
PACKAGE
TAS5613PHD
TAS5613DKD
DESCRIPTION
64 pin HTQFP
44 pin PSOP3
0°C–70°C
0°C–70°C
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Link(s): TAS5613
TAS5613
SLAS676 –NOVEMBER 2009
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
TAS5613
UNIT
V
VDD to GND
–0.3 to 13.2
–0.3 to 13.2
–0.3 to 53
–0.3 to 53
–0.3 to 66.2
–0.3 to 53
–0.3 to 4.2
–0.3 to 0.3
–0.3 to 0.3
–0.3 to 4.2
GVDD to GND
V
PVDD_X to GND_X(2)
OUT_X to GND_X(2)
BST_X to GND_X(2)
BST_X to GVDD_X(2)
VREG to GND
V
V
V
V
V
GND_X to GND
V
GND to AGND
V
OC_ADJ, M1, M2, M3, OSC_IO+, OSC_IO–, FREQ_ADJ, VI_CM, C_STARTUP,
PSU_REF to GND
V
INPUT_X
–0.3 to 7
–0.3 to 7
9
V
V
RESET, SD, OTW1, OTW2, CLIP, READY to GND
Continuous sink current (SD, OTW1, OTW2, CLIP, READY)
Operating junction temperature range, TJ
Storage temperature, Tstg
mA
°C
°C
kV
V
0 to 150
–40 to 150
±2
Human-Body Model(3) (all pins)
Charged-Device Model(3) (all pins)
Electrostatic discharge
±500
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions.
(3) Failure to follow good anti-static ESD handling during manufacture and rework will contribute to device malfunction. Make sure the
operators handling the device are adequately grounded through the use of ground straps or alternative ESD protection.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
PVDD_x
GVDD_x
Half-bridge supply
DC supply voltage
DC supply voltage
DC supply voltage
18
36
38
V
Supply for logic regulators and
gate-drive circuitry
10.8
12
13.2
13.2
V
V
VDD
Digital regulator supply voltage
10.8
3.5
2.8
1.6
12
4
RL(BTL)
RL(SE)
RL(PBTL)
Output filter according to Figure 12 and
Figure 13
Load impedance
3
Ω
Ω
2
Output filter according to Figure 12 +
Schottky, ROC = 22kΩ
RL (BTL)
Load impedance
2.8
3
LOUT(BTL)
LOUT(SE)
7
7
10
15
Output filter inductance
Minimum output inductance at IOC
μH
LOUT(PBTL)
7
10
Nominal
350
300
260
9.5
19.8
29.7
400
340
300
10
450
380
PWM frame rate selectable for AM
interference avoidance; 1%
Resistor tolerance
FPWM
AM1
kHz
AM2
335
Nominal; Master mode
AM1; Master mode
AM2; Master mode
10.5
20.2
30.3
PWM frame rate programming
resistor
RFREQ_ADJ
20
kΩ
30
CPVDD
ROC
PVDD close decoupling capacitors
2.0
30
μF
kΩ
Over-current programming resistor Resistor tolerance = 5%
22
4
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TAS5613
TAS5613
www.ti.com
SLAS676 –NOVEMBER 2009
RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
ROC_LATCHED
VFREQ_ADJ
TJ
Over-current programming resistor Resistor tolerance = 5%
47
64
kΩ
Voltage on FREQ_ADJ pin for
Slave mode
3.3
V
slave mode operation
Junction temperature
0
150
°C
PIN FUNCTIONS
PIN
FUNCTION(1)
DESCRIPTION
NAME
AGND
PHD NO.
DKD NO.
8
10
43
34
33
24
–
P
P
P
P
P
O
O
I
Analog ground
BST_A
54
41
40
27
18
3
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_A required.
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_B required.
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_C required.
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_D required.
Clipping warning; open drain; active low
BST_B
BST_C
BST_D
CLIP
C_STARTUP
FREQ_ADJ
5
Startup ramp requires a charging capacitor of 4.7nF to GND
12
14
PWM frame rate programming pin requires resistor to GND
7, 23, 24,
57, 58
GND
9
P
Ground
GND_A
GND_B
GND_C
GND_D
GVDD_A
GVDD_B
GVDD_C
GVDD_D
GVDD_AB
GVDD_CD
INPUT_A
INPUT_B
INPUT_C
INPUT_D
M1
48, 49
46, 47
34, 35
32, 33
55
38
37
30
29
–
P
P
P
P
P
P
P
P
P
P
I
Power ground for half-bridge A
Power ground for half-bridge B
Power ground for half-bridge C
Power ground for half-bridge D
Gate drive voltage supply requires 0.1 μF capacitor to GND_A
Gate drive voltage supply requires 0.1 μF capacitor to GND_B
Gate drive voltage supply requires 0.1 μF capacitor to GND_C
Gate drive voltage supply requires 0.1 uF capacitor to GND_D
Gate drive voltage supply requires 0.22 μF capacitor to GND_A/GND_B
Gate drive voltage supply requires 0.22 μF capacitor to GND_C/GND_D
Input signal for half bridge A
56
–
25
–
26
-
–
44
23
6
–
4
5
7
I
Input signal for half bridge B
10
12
13
20
21
22
–
I
Input signal for half bridge C
11
I
Input signal for half bridge D
20
I
Mode selection
M2
21
I
Mode selection
M3
22
I
Mode selection
NC
59-62
1
–
No connect, pins may be grounded.
OC_ADJ
OSC_IO+
OSC_IO–
/OTW
3
O
I/O
I/O
O
O
O
O
O
O
O
P
Analog over current programming pin requires 30kΩ resistor to ground:
Oscillator master/slave output/input.
13
15
16
18
–
14
Oscillator master/slave output/input.
-
Overtemperature warning signal, open drain, active low.
Overtemperature warning signal, open drain, active low.
Overtemperature warning signal, open drain, active low.
Output, half bridge A
OTW1
16
OTW2
17
–
OUT_A
OUT_B
OUT_C
OUT_D
PSU_REF
52, 53
44, 45
36, 37
28, 29
63
39, 40
36
31
27, 28
1
Output, half bridge B
Output, half bridge C
Output, half bridge D
PSU Reference requires close decoupling of 330pF to GND
Power supply input for half bridges A requires close decoupling of 2μF capacitor to
GND_A.
PVDD_A
50, 51
41, 42
P
(1) I = Input, O = Output, P = Power
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Link(s): TAS5613
TAS5613
SLAS676 –NOVEMBER 2009
www.ti.com
PIN FUNCTIONS (continued)
PIN
FUNCTION(1)
DESCRIPTION
NAME
PVDD_B
PHD NO.
DKD NO.
Power supply input for half bridges B requires close decoupling of 2μF capacitor to
GND_B.
42, 43
35
P
P
P
Power supply input for half bridges C requires close decoupling of 2μF capacitor to
GND_C.
PVDD_C
PVDD_D
38, 39
30, 31
32
Power supply input for half bridges D requires close decoupling of 2μF capacitor to
GND_D.
25, 26
READY
RESET
SD
19
2
19
4
O
I
Normal operation; open drain; active high
Device reset Input; active low, requires 47kΩ pull up resistor to VREG
Shutdown signal, open drain, active low
15
17
O
Power supply for internal voltage regulator requires a 10-μF capacitor with a 0.1-μF
capacitor to GND for decoupling.
VDD
64
2
P
VI_CM
VREG
6
9
8
O
P
Analog comparator reference node requires close decoupling of 1nF to GND
11
Internal regulator supply filter pin requires 0.1-μF capacitor to GND
6
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TAS5613
TAS5613
www.ti.com
SLAS676 –NOVEMBER 2009
TYPICAL SYSTEM BLOCK DIAGRAM
Caps for
External
Filtering
&
System
microcontroller
or
Analog circuitry
Startup/Stop
(2)
BST_A
BST_B
OSC_IO+
OSC_IO-
Oscillator
Synchronization
Bootstrap
Caps
2nd Order
L-C Output
Filter for
each
INPUT_A
INPUT_B
OUT_A
ANALOG_IN_A
ANALOG_IN_B
Input DC
Blocking
Caps
Input
H-Bridge 1
Output
H-Bridge 1
2
OUT_B
2
H-Bridge
Hardwire
2-CHANNEL
H-BRIDGE
BTL MODE
PWM Frame
Rate Adjust
&
FREQ_ADJ
Master/Slave
Mode
2nd Order
L-C Output
Filter for
each
INPUT_C
OUT_C
ANALOG_IN_C
ANALOG_IN_D
Input DC
Blocking
Caps
Input
H-Bridge 2
Output
H-Bridge 2
2
INPUT_D
OUT_D
2
H-Bridge
M1
BST_C
BST_D
Hardwire
Mode
Control
M2
M3
Bootstrap
Caps
8
8
4
Hardwire
PVDD
GND
PVDD
Power Supply
Decoupling
GVDD, VDD,
36V
Over-
Current
Limit
& VREG
Power Supply
Decoupling
SYSTEM
Power
Supplies
GND
12V
GVDD (12V)/VDD (12V)
VAC
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Link(s): TAS5613
TAS5613
SLAS676 –NOVEMBER 2009
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
CLIP
READY
OTW1
OTW2
SD
M1
M2
M3
VDD
POWER-UP
RESET
UVP
VREG
VREG
AGND
GND
RESET
TEMP
SENSE
GVDD_A
GVDD_B
GVDD_C
GVDD_D
STARTUP
CONTROL
C_STARTUP
OVER-LOAD
PROTECTION
CURRENT
SENSE
CB3C
OC_ADJ
OSC_SYNC_IO+
4
4
OSC_SYNC_IO-
FREQ_ADJ
OSCILLATOR
PVDD_X
OUT_X
GND_X
PPSC
4
GVDD_A
BST_A
PWM
ACTIVITY
DETECTOR
PVDD_X
GND
PSU_REF
VI_CM
PSU_FF
PVDD_A
OUT_A
GND_A
GVDD_B
BST_B
PWM
RECEIVER
TIMING
CONTROL
CONTROL
GATE-DRIVE
-
ANALOG
LOOP FILTER
INPUT_A
INPUT_B
+
PVDD_B
OUT_B
GND_B
GVDD_C
BST_C
PWM
RECEIVER
TIMING
CONTROL
CONTROL
CONTROL
CONTROL
GATE-DRIVE
GATE-DRIVE
GATE-DRIVE
+
-
ANALOG
LOOP FILTER
INPUT_C
INPUT_D
PVDD_C
OUT_C
GND_C
GVDD_D
BST_D
-
ANALOG
LOOP FILTER
+
PWM
RECEIVER
TIMING
CONTROL
+
-
ANALOG
LOOP FILTER
PVDD_D
OUT_D
GND_D
PWM
RECEIVER
TIMING
CONTROL
8
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TAS5613
TAS5613
www.ti.com
SLAS676 –NOVEMBER 2009
AUDIO CHARACTERISTICS (BTL)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1kHz, PVDD_X = 36V,
GVDD_X = 12V, RL = 4Ω, fS = 400kHz, ROC = 30kΩ, TC = 75°C, Output Filter: LDEM = 7μH, CDEM = 680nF, mode = 010,
unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
RL = 3Ω, 10% THD+N (ROC = 22kΩ, add
Schottky diodes from OUT_X to GND_X)
200
RL = 4Ω, 10% THD+N
150
PO
Power output per channel
W
RL = 3Ω, 1% THD+N (ROC = 22kΩ, add
Schottky diodes from OUT_X to GND_X)
160
RL = 4Ω, 1% THD+N
125
THD+N Total harmonic distortion + noise
1 W
0.03%
185
A-weighted, AES17 filter, Input Capacitor
Grounded
Vn
Output integrated noise
μV
|VOS
|
Output offset voltage
Signal-to-noise ratio(1)
Inputs AC coupled to GND
20
100
100
1.8
50
mV
dB
dB
W
SNR
DNR
Pidle
Dynamic range
Power dissipation due to Idle losses (IPVDD_X
)
PO = 0, 4 channels switching(2)
(1) SNR is calculated relative to 1% THD+N output level.
(2) Actual system idle losses also are affected by core losses of output inductors.
AUDIO CHARACTERISTICS (PBTL)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1kHz, PVDD_X = 36V,
GVDD_X = 12V, RL = 2Ω, fS = 400 kHz, ROC = 30kΩ, TC = 75°C, Output Filter: LDEM = 7μH, CDEM = 680nF, MODE = 101-BD,
unless otherwise noted.
PARAMETER
TEST CONDITIONS
RL = 2Ω, 10% THD+N
MIN
TYP MAX UNIT
300
200
RL = 3Ω, 10% THD+N
RL = 4Ω, 10% THD+N
RL = 2Ω, 1% THD+N
RL = 3Ω, 1% THD+N
RL = 4Ω, 1% THD+N
1 W
160
PO
Power output per channel
W
250
160
130
THD+N Total harmonic distortion + noise
0.05%
182
Vn
Output integrated noise
Signal to noise ratio(1)
Dynamic range
A-weighted
μV
dB
dB
W
SNR
DNR
Pidle
A-weighted
100
100
1.8
A-weighted
Power dissipation due to idle losses (IPVDD_X) PO = 0, 4 channels switching(2)
(1) SNR is calculated relative to 1% THD+N output level.
(2) Actual system idle losses are affected by core losses of output inductors.
ELECTRICAL CHARACTERISTICS
PVDD_X = 36V, GVDD_X = 12V, VDD = 12V, TC (Case temperature) = 75°C, fS = 400kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
Voltage regulator, only used as reference
VREG
VDD = 12V
3
3.3
3.6
1.9
V
V
node
Analog comparator reference node,
VI_CM
1.5
1.75
Operating, 50% duty cycle
Idle, reset mode
50% duty cycle
20
20
IVDD
VDD supply current
mA
mA
10
IGVDD_x
Gate-supply current per half-bridge
Reset mode
1.5
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Link(s): TAS5613
TAS5613
SLAS676 –NOVEMBER 2009
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
PVDD_X = 36V, GVDD_X = 12V, VDD = 12V, TC (Case temperature) = 75°C, fS = 400kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
50% duty cycle with recommended output
filter
12.5
620
mA
IPVDD_x
Half-bridge idle current
Reset mode, No switching
μA
ANALOG INPUTS
RIN
Input resistance
READY = HIGH
33
7
kΩ
V
VIN
Maximum input voltage swing
Maximum input current
IIN
1
mA
dB
G
Inverting voltage Gain, (VOUT/VIN
)
21
OSCILLATOR
Nominal, Master Mode
AM1, Master Mode
3.5
3.0
4
3.4
3
4.5
3.8
fOSC_IO+
FPWM × 10
MHz
AM2, Master Mode
2.6
3.35
VIH
VIL
High level input voltage
Low level input voltage
1.86
V
V
1.45
OUTPUT-STAGE MOSFETs
Drain-to-source resistance, low side (LS)
Drain-to-source resistance, high side (HS)
60 100
60 100
mΩ
mΩ
TJ = 25°C, Includes metallization resistance,
GVDD = 12V
RDS(on)
I/O PROTECTION
Undervoltage protection limit, GVDD_x
and VDD
Vuvp,G
9.5
V
(1)
Vuvp,hyst
0.6
V
(1)
Overtemperature warning 1, OTW1
95
100 105
125 135
°C
°C
OTW
(1)
Overtemperature warning 2, OTW2
115
Temperature drop needed below OTW
temperature for OTW to be inactive after
OTW event.
(1)
OTWHYST
25
°C
OTE(1)
OTE-
Overtemperature error
145
155 165
30
°C
°C
OTE-OTW differential
(1)
OTWdifferential
A reset needs to occur for SD to be
released following an OTE event
(1)
OTEHYST
25
2.6
14
°C
OLPC
Overload protection counter
fPWM = 400kHz
ms
Resistor – programmable, nominal peak
current in 1Ω load, ROCP = 30kΩ
IOC
Overcurrent limit protection
A
A
Resistor – programmable, nominal peak
current in 1Ω load, ROCP = 22kΩ (with
Schottky diodes on output nodes)
18
14
18
Resistor – programmable, peak current in
1Ω load, ROCP = 64kΩ
IOC_LATCHED
Overcurrent limit protection
Resistor – programmable, nominal peak
current in 1Ω load, ROCP = 47kΩ (with
Schottky diodes on output nodes)
Time from switching transition to flip-state
induced by overcurrent.
IOCT
IPD
Overcurrent response time
150
3
ns
Connected when RESET is active to provide
bootstrap charge. Not used in SE mode.
Output pulldown current of each half
mA
STATIC DIGITAL SPECIFICATIONS
VIH
High level input voltage
Low level input voltage
Input leakage current
1.9
V
V
INPUT_X, M1, M2, M3, RESET
VIL
0.8
Leakage
100
μA
(1) Specified by design.
10 Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TAS5613
TAS5613
www.ti.com
SLAS676 –NOVEMBER 2009
ELECTRICAL CHARACTERISTICS (continued)
PVDD_X = 36V, GVDD_X = 12V, VDD = 12V, TC (Case temperature) = 75°C, fS = 400kHz, unless otherwise specified.
PARAMETER
OTW/SHUTDOWN (SD)
TEST CONDITIONS
MIN
TYP MAX UNIT
Internal pullup resistance, OTW1 to
VREG, OTW2 to VREG, SD to VREG
RINT_PU
VOH
20
26
32
kΩ
Internal pullup resistor
3
3.3
3.6
5
High level output voltage
Low level output voltage
V
External pullup of 4.7kΩ to 5V
4.5
VOL
IO = 4 mA
200 500
mV
Device fanout OTW1, OTW2, SD, CLIP,
READY
FANOUT
No external pullup
30
devices
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Link(s): TAS5613
TAS5613
SLAS676 –NOVEMBER 2009
www.ti.com
TYPICAL CHARACTERISTICS, BTL CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
OUTPUT POWER
vs
SUPPLY VOLTAGE
250
200
150
100
10
T
= 75°C
C
T
= 75°C,
C
THD+N = 10%
3 W
1
4 W
6 W
3 W
8 W
4 W
0.1
6 W
8 W
0.01
0.001
50
0
18
20
22
24
26
28
30
32
34
36
0.01
0.1
1 10
- Output Power - W
100
1000
PVDD - Supply Voltage - V
P
O
Figure 1.
Figure 2.
UNCLIPPED OUTPUT POWER
SYSTEM EFFICIENCY
vs
vs
SUPPLY VOLTAGE
OUTPUT POWER
100
90
200
150
100
T
= 75°C
C
4 W
6 W
8 W
80
3 W
70
60
4 W
6 W
50
40
8 W
30
20
50
0
T
= 25°C
C
THD+N = 10%
10
0
200 300
2 Channel Output Power - W
0
50
100 150
250
350 400
18 20
22
24
26
28
30
32
34
36
PVDD - Supply Voltage - V
Figure 3.
Figure 4.
12
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TAS5613
TAS5613
www.ti.com
SLAS676 –NOVEMBER 2009
TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
SYSTEM POWER LOSS
vs
OUTPUT POWER
vs
OUTPUT POWER
CASE TEMPERATURE
30
20
250
200
150
100
THD+N = 10%
T
= 25°C
C
3 W
4 W
THD+N = 10%
4 W
6 W
6 W
8 W
10
50
0
8 W
0
0
200 300
2 Channel Output Power - W
50
100 150
250
350 400
20
30
40
T
50
60
70
80
90
100
- Case Temperature - °C
C
Figure 5.
Figure 6.
NOISE AMPLITUDE
vs
TOTAL HARMONIC DISTORTION+NOISE
vs
FREQUENCY
FREQUENCY
0
-20
10
R
T
= 4 W,
T
= 75°C,
L
C
VREF = 25.46 V,
= 75°C,
C
Sample Rate = 48 kHz,
FFT size = 16384
Toroidal Output Inductors
-40
1
-60
-80
0.1
1W
-100
-120
4 W
0.01
-140
-160
21 W (1/8 Power)
0.001
0
5
10 15
f - Frequency - kHz
20
10
100
1k
10k
100k
f - Frequency - Hz
Figure 7.
Figure 8.
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Link(s): TAS5613
TAS5613
SLAS676 –NOVEMBER 2009
www.ti.com
TYPICAL CHARACTERISTICS, PBTL CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE
OUTPUT POWER
vs
vs
OUTPUT POWER
SUPPLY VOLTAGE
10
350
300
250
200
150
100
50
T
= 75°C,
T
= 75°C
2 W
3 W
4 W
6 W
8 W
C
THD+N = 10%
C
2 W
1
3 W
4 W
6 W
0.1
8 W
0.01
0.001
0
18 20
22
24
26
28
30
32
34
36
0.01
0.1
1 10
- Output Power - W
100
1000
P
PVDD - Supply Voltage - V
O
Figure 9.
Figure 10.
OUTPUT POWER
vs
CASE TEMPERATURE
400
350
300
250
200
150
100
50
THD+N = 10%
2 W
3 W
4 W
6 W
8 W
0
20
30
40
T
50
60
70
80
90
100
- Case Temperature - °C
C
Figure 11.
14
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TAS5613
TAS5613
www.ti.com
SLAS676 –NOVEMBER 2009
APPLICATION INFORMATION
PCB MATERIAL RECOMMENDATION
FR-4 Glass Epoxy material with 2 oz. (70μm) is recommended for use with the TAS5613. The use of this
material can provide for higher power output, improved thermal performance, and better EMI margin (due to
lower PCB trace inductance.
PVDD CAPACITOR RECOMMENDATION
The large capacitors used in conjunction with each full-bridge, are referred to as the PVDD Capacitors. These
capacitors should be selected for proper voltage margin and adequate capacitance to support the power
requirements. In practice, with a well designed system power supply, 1000 μF, 50V will support more
applications. The PVDD capacitors should be low ESR type because they are used in a circuit associated with
high-speed switching.
DECOUPLING CAPACITOR RECOMMENDATIONS
In order to design an amplifier that has robust performance, passes regulatory requirements, and exhibits good
audio performance, good quality decoupling capacitors should be used. In practice, X7R should be used in this
application.
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the
selection of the 2μF that is placed on the power supply to each half-bridge. It must withstand the voltage
overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the ripple
current created by high power output. A minimum voltage rating of 50V is required for use with a 36V power
supply.
SYSTEM DESIGN RECOMMENDATIONS
The following schematics and PCB layouts illustrate best practices in the use of the TAS5613.
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Link(s): TAS5613
TAS5613
SLAS676 –NOVEMBER 2009
www.ti.com
G N D _ A
P V D D _ A
P V D D _ A
O U T _ A
G N D _ D
3 2
4 9
5 0
5 1
5 2
5 3
5 4
5 5
5 6
5 7
5 8
5 9
6 0
6 1
6 2
6 3
6 4
P V D D _ D
3 1
P V D D _ D
3 0
O U T _ D
2 9
O U T _ A
O U T _ D
2 8
B S T _ A
B S T _ D
2 7
G V D D _ A
G V D D _ B
G V D D _ D
2 6
G V D D _ C
2 5
G N D
G N D
N C
G N D
2 4
G N D
2 3
M 3
2 2
N C
N C
N C
M 2
2 1
M 1
2 0
R E A D Y
1 9
P S U _ R E F
/ C L I P
1 8
V D D
/ O T W 2
1 7
Figure 12. Typical Differential Input BTL Application With BD Modulation Filters
16
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TAS5613
TAS5613
www.ti.com
SLAS676 –NOVEMBER 2009
G N D _ A
P V D D _ A
P V D D _ A
O U T _ A
G N D _ D
3 2
4 9
5 0
5 1
5 2
5 3
5 4
5 5
5 6
5 7
5 8
5 9
6 0
6 1
6 2
6 3
6 4
P V D D _ D
3 1
P V D D _ D
3 0
O U T _ D
2 9
O U T _ A
O U T _ D
2 8
B S T _ A
B S T _ D
2 7
G V D D _ A
G V D D _ B
G V D D _ D
2 6
G V D D _ C
2 5
G N D
G N D
N C
G N D
2 4
G N D
2 3
M 3
2 2
N C
N C
N C
M 2
2 1
M 1
2 0
R E A D Y
1 9
P S U _ R E F
/ C L I P
1 8
V D D
/ O T W 2
1 7
Figure 13. Typical Differential (2N) PBTL Application With BD Modulation Filters
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Link(s): TAS5613
TAS5613
SLAS676 –NOVEMBER 2009
www.ti.com
THEORY OF OPERATION
POWER SUPPLIES
To facilitate system design, the TAS5613 needs only a 12V supply in addition to the (typical) 36V power-stage
supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog
circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is
accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.
In order to provide outstanding electrical and acoustical characteristics, the PWM signal path including gate drive
and output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has
separate gate drive supply (GVDD_X), bootstrap pins (BST_X), and power-stage supply pins (PVDD_X).
Furthermore, an additional pin (VDD) is provided as supply for all common circuits. Although supplied from the
same 12V source, separating to GVDD_A, GVDD_B, GVDD_C, GVDD_D, and VDD on the printed-circuit board
(PCB) by RC filters (see application diagram for details) is recommended. These RC filters provide the
recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as
close to their associated pins as possible. In general, inductance between the power supply pins and decoupling
capacitors must be avoided. (See reference board documentation for additional information.)
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the
bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM
switching frequencies in the range from 300kHz to 400kHz, it is recommended to use 33nF ceramic capacitors,
size 0603 or 0805, for the bootstrap supply. These 33nF capacitors ensure sufficient energy storage, even during
minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining
part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is
decoupled with a 2-μF ceramic capacitor placed as close as possible to each supply pin. It is recommended to
follow the PCB layout of the TAS5613 reference design. For additional information on recommended power
supply and required components, see the application diagrams in this data sheet.
The 12V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 36V
power-stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not
critical as facilitated by the internal power-on-reset circuit. Moreover, the TAS5613 is fully protected against
erroneous power-stage turn on due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are
non-critical within the specified range (see the Recommended Operating Conditions table of this data sheet).
SYSTEM POWER-UP/POWER-DOWN SEQUENCE
Powering Up
The TAS5613 does not require a power-up sequence. The outputs of the H-bridges remain in a high-impedance
state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage protection
(UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). Although not specifically
required, it is recommended to hold RESET in a low state while powering up the device. This allows an internal
circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output.
Powering Down
The TAS5613 does not require a power-down sequence. The device remains fully operational as long as the
gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage
threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is a
good practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks.
18
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TAS5613
TAS5613
www.ti.com
SLAS676 –NOVEMBER 2009
ERROR REPORTING
The SD, OTW, OTW1 and OTW2 pins are active-low, open-drain outputs. The function is for protection-mode
signaling to a PWM controller or other system-control device.
Any fault resulting in device shutdown is signaled by the SD pin going low. Also, OTW and OTW2 go low when
the device junction temperature exceeds 125°C, and OTW1 goes low when the junction temperature exceeds
100°C (seeTable 2).
Table 2. Error Reporting
SD
OTW1 OTW2, OTW DESCRIPTION
0
0
0
Overtemperature (OTE) or overload (OLP) or undervoltage (UVP) Junction temperature higher than 125°C
(overtemperature warning)
0
0
1
Overload (OLP) or undervoltage (UVP). Junction temperature higher than 100°C (overtemperature
warning)
0
1
1
1
1
0
0
1
1
0
1
1
Overload (OLP) or undervoltage (UVP). Junction temperature lower than 100°C
Junction temperature higher than 125°C (overtemperature warning)
Junction temperature higher than 100°C (overtemperature warning)
Junction temperature lower than 100°C and no OLP or UVP faults (normal operation)
Note that asserting either RESET low forces the SD signal high, independent of faults being present. TI
recommends monitoring the OTW signal using the system microcontroller and responding to an overtemperature
warning signal by, e.g., turning down the volume to prevent further heating of the device resulting in device
shutdown (OTE).
To reduce external component count, an internal pullup resistor to 3.3V is provided on both SD and OTW
outputs. Level compliance for 5V logic can be obtained by adding external pullup resistors to 5 V (see the
Electrical Characteristics section of this data sheet for further specifications).
DEVICE PROTECTION SYSTEM
The TAS5613 contains advanced protection circuitry carefully designed to facilitate system integration and ease
of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as
short circuits, overload, overtemperature, and undervoltage. The TAS5613 responds to a fault by immediately
setting the power stage in a high-impedance (Hi-Z) state and asserting the SD pin low. In situations other than
overload and overtemperature error (OTE), the device automatically recovers when the fault condition has been
removed, i.e., the supply voltage has increased.
The device will function on errors, as shown in Table 3.
Table 3. Device Protection
BTL
MODE
PBTL
MODE
SE
MODE
LOCAL
ERROR IN
LOCAL
ERROR IN
LOCAL
ERROR IN
TURNS OFF
TURNS OFF
TURNS OFF
A
B
C
D
A
B
C
D
A
B
C
D
A+B
C+D
A+B
C+D
A+B+C+D
Bootstrap UVP does not shutdown according to the table, it shuts down the respective halfbridge.
PIN-TO-PIN SHORT CIRCUIT PROTECTION (PPSC)
The PPSC detection system protects the device from permanent damage in the case that a power output pin
(OUT_X) is shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an overcurrent
after the demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection is
performed at startup i.e. when VDD is supplied, consequently a short to either GND_X or PVDD_X after system
startup will not activate the PPSC detection system. When PPSC detection is activated by a short on the output,
all half bridges are kept in a Hi-Z state until the short is removed, the device then continues the startup sequence
and starts switching. The detection is controlled globally by a two step sequence. The first step ensures that
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Link(s): TAS5613
TAS5613
SLAS676 –NOVEMBER 2009
www.ti.com
there are no shorts from OUT_X to GND_X, the second step tests that there are no shorts from OUT_X to
PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC filter. The
typical duration is < 15ms/μF. While the PPSC detection is in progress, SD is kept low, and the device will not
react to changes applied to the RESET pins. If no shorts are present the PPSC detection passes, and SD is
released. A device reset will not start a new PPSC detection. PPSC detection is enabled in BTL and PBTL output
configurations, the detection is not performed in SE mode. To make sure not to trip the PPSC detection system it
is recommended not to insert resistive load to GND_X or PVDD_X.
OVERTEMPERATURE PROTECTION
The two different package options has individual over temperature protection schemes.
PHD Package
The TAS5613 PHD package option has a three-level temperature-protection system that asserts an active-low
warning signal (OTW1) when the device junction temperature exceeds 100°C (typical), (OTW2) when the device
junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds 155°C (typical), the
device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z)
state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted.
Thereafter, the device resumes normal operation.
DKD Package
The TAS5613 DKD package option has a two-level temperature-protection system that asserts an active-low
warning signal (OTW) when the device junction temperature exceeds 125°C (typical) and, if the device junction
temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs
being set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case. To clear the
OTE latch, RESET must be asserted. Thereafter, the device resumes normal operation.
UNDERVOLTAGE PROTECTION (UVP) AND POWER-ON RESET (POR)
The UVP and POR circuits of the TAS5613 fully protect the device in any power-up/down and brownout situation.
While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully
operational when the GVDD_X and VDD supply voltages reach stated in the Electrical Characteristics table.
Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on
any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z)
state and SD being asserted low. The device automatically resumes operation when all supply voltages have
increased above the UVP threshold.
DEVICE RESET
When RESET is asserted low, all power-stage FETs in the four half-bridges are forced into a high-impedance
(Hi-Z) state.
In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables
weak pulldown of the half-bridge outputs. In the SE mode, the output is forced into a high impedance state when
asserting the reset input low.
Asserting reset input low removes any fault information to be signalled on the SD output, i.e., SD is forced high.
A rising-edge transition on reset input allows the device to resume operation after an overload fault. To ensure
thermal reliability, the rising edge of reset must occur no sooner than 4 ms after the falling edge of SD.
SYSTEM DESIGN CONSIDERATION
A rising-edge transition on reset input allows the device to execute the startup sequence and starts switching.
Apply only audio when the state of READY is high that will start and stop the amplifier without having audible
artifacts that is heard in the output transducers.
The CLIP signal is indicating that the output is approaching clipping. The signal can be used to either an audio
volume decrease or intelligent power supply controlling a low and a high rail.
The device is inverting the audio signal from input to output.
20
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TAS5613
TAS5613
www.ti.com
SLAS676 –NOVEMBER 2009
The VREG pin is not recommended to be used as a voltage source for external circuitry.
OSCILLATOR
The oscillator frequency can be trimmed by external control of the FREQ_ADJ pin.
To reduce interference problems while using radio receiver tuned within the AM band, the switching frequency
can be changed from nominal to lower values. These values should be chosen such that the nominal and the
lower value switching frequencies together results in the fewest cases of interference throughout the AM band.
can be selected by the value of the FREQ_ADJ resistor connected to AGND in master mode.
For slave mode operation, turn of the oscillator by pulling the FREQ_ADJ pin to VREG. This configures the
OSC_I/O pins as inputs and needs to be slaved from an external differential clock.
PRINTED CIRCUIT BOARD RECOMMENDATION
Use an unbroken ground plane to have good low impedance and inductance return path to the power supply for
power and audio signals. PCB layout, audio performance and EMI are linked closely together. The circuit
contains high fast switching currents; therefore, care must be taken to prevent damaging voltage spikes. Routing
the audio input should be kept short and together with the accompanied audio source ground. A local ground
area underneath the device is important to keep solid to minimize ground bounce.
Netlist for this printed circuit board is generated from the schematic in Figure 12.
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Link(s): TAS5613
TAS5613
SLAS676 –NOVEMBER 2009
www.ti.com
Note T1: PVDD decoupling bulk capacitors C60-C64 should be as close as possible to the PVDD and GND_X pins,
the heat sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and
without going through vias. No vias or traces should be blocking the current path.
Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and
close to the pins.
Note T3: Heat sink needs to have a good connection to PCB ground.
Note T4: Output filter capacitors must be linear in the applied voltage range preferable metal film types.
Figure 14. Printed Circuit Board - Top Layer
22
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TAS5613
TAS5613
www.ti.com
SLAS676 –NOVEMBER 2009
Note B1: It is important to have a direct low impedance return path for high current back to the power supply. Keep
impedance low from top to bottom side of PCB through a lot of ground vias.
Note B2: Bootstrap low impedance X7R ceramic capacitors placed on bottom side providing a short low inductance
current loop.
Note B3: Return currents from bulk capacitors and output filter capacitors.
Figure 15. Printed Circuit Board - Bottom Layer
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Link(s): TAS5613
PACKAGE OPTION ADDENDUM
www.ti.com
15-Dec-2009
PACKAGING INFORMATION
Orderable Device
TAS5613PHD
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
HTQFP
PHD
64
90 Green (RoHS & CU NIPDAU Level-5A-260C-24 HR
no Sb/Br)
TAS5613PHDR
HTQFP
PHD
64
1000 Green (RoHS & CU NIPDAU Level-5A-260C-24 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Applications
Audio
Automotive
Broadband
Digital Control
Medical
Military
Optical Networking
Security
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
www.ti.com/audio
Data Converters
DLP® Products
DSP
Clocks and Timers
Interface
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
Logic
Power Mgmt
Microcontrollers
RFID
Telephony
Video & Imaging
Wireless
RF/IF and ZigBee® Solutions www.ti.com/lprf
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2009, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明