TAS5616 [TI]
160-W STEREO / 300-W MONO PurePath⢠HD DIGITAL-INPUT POWER STAGE; 160 -W立体声/ 300 -W单声道PurePathâ ?? ¢ HD数字输入功率级
| 型号： | TAS5616 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 160-W STEREO / 300-W MONO PurePath⢠HD DIGITAL-INPUT POWER STAGE |
| 文件： | 总33页 (文件大小：1816K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TAS5616
www.ti.com
SLAS596B –JUNE 2009–REVISED JANUARY 2010
160-W STEREO / 300-W MONO PurePath™ HD DIGITAL-INPUT POWER STAGE
Check for Samples: TAS5616
1
FEATURES
APPLICATIONS
•
•
•
•
Mini Combo System
AV Receivers
DVD Receivers
Active Speakers
23
•
PurePath™ HD Enabled Integrated Feedback
Provides:
–
Signal Bandwidth up to 80 kHz for
High-Frequency Content From HD Sources
–
–
Ultralow 0.03% THD at 1 W into 8 Ω
DESCRIPTION
Flat THD at All Frequencies for Natural
Sound
The TAS5616 is a high-performance PWM-input
class-D amplifier with integrated closed-loop
feedback technology (known as PurePath™ HD
technology). It has the ability to drive up to 160-W
–
–
–
–
80-dB PSRR (BTL, No Input Signal)
>100-dB (A-weighted) SNR
(1)
Click- and Pop-Free Startup
stereo into 8-Ω speakers from a single 50-V
supply.
Minimal External Components Compared to
Discrete Solutions
PurePath™ HD technology enables traditional
AB-amplifier performance (<0.03% THD) levels while
providing the power efficiency of traditional class-D
amplifiers.
•
•
Multiple Configurations Possible on the Same
PCB With Stuffing Options:
–
–
–
Mono Parallel Bridge-Tied Load (PBTL)
Stereo Bridge-Tied Load (BTL)
Ultralow 0.03% THD+N is flat across all frequencies,
ensuring that the amplifier does not add uneven
distortion characteristics, and helps maintain a natural
sound.
2.1 Single-Ended Stereo Pair and
Bridge-Tied Load Subwoofer
–
Quad Single-Ended Outputs
The efficiency of this class-D amplifier is greater than
90%. Undervoltage protection, overtemperature,
clipping, short-circuit and overcurrent protection are
all integrated, safeguarding the device and speakers
against fault conditions that could damage the
system. PurePath HD™
Total Output Power at 10% THD+N
–
–
330 W in Mono PBTL Configuration
160 W per Channel in Stereo BTL
Configuration
–
80 W per Channel in Quad Single-Ended
Configuration
♫♪
ANALOG
AUDIO
INPUT
•
•
High-Efficiency Power Stage (>90%) With
120-mΩ Output MOSFETs
PurePathTM HD
TAS5616
TAS3308
Digital Audio
Processor
♫♪
♫♪
(2.1 Configuration)
DIGITAL
AUDIO
INPUT
With Analog Interface
Two Thermally Enhanced Package Options:
–
–
PHD (64-Pin QFP)
12 V
25 V–50 V
DKD (44-Pin PSOP3)
•
•
Self-Protection Design (Including
Undervoltage, Overtemperature, Clipping, and
Short-Circuit Protection) With Error Reporting
PurePathTM HD
Power Supply
Ref. Design
+3.3V
REG.
EMI Compliant When Used With
Recommended System Design
110 VAC®240 VAC
(1) Achievable output power levels are dependent on the thermal
configuration of the target application. A high performance
thermal interface material between the package exposed
thermal pad and the heat sink should be used to achieve high
output power levels.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
PurePath HD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2010, Texas Instruments Incorporated
TAS5616
SLAS596B –JUNE 2009–REVISED JANUARY 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DEVICE INFORMATION
Terminal Assignment
The TAS5616 is available in two thermally enhanced packages:
•
•
44-Pin PSOP3 package (DKD)
64-Pin QFP (PHD) Power Package
Both package types contain a heat slug that is located on the top side of the device for convenient thermal
coupling to the heat sink.
PHD PACKAGE
(TOP VIEW)
DKD PACKAGE
(TOP VIEW)
PSU_REF
VDD
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
GVDD_AB
BST_A
2
OC_ADJ
RESET
3
PVDD_A
PVDD_A
OUT_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
4
OC_ADJ
RESET
C_STARTUP
INPUT_A
INPUT_B
VI_CM
GND
AGND
VREG
INPUT_C
INPUT_D
TEST
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
GND_A
GND_B
GND_B
OUT_B
OUT_B
PVDD_B
PVDD_B
BST_B
BST_C
PVDD_C
PVDD_C
OUT_C
OUT_C
GND_C
GND_C
GND_D
C_STARTUP
INPUT_A
INPUT_B
VI_CM
5
6
7
8
GND
9
10
11
12
13
14
15
16
17
18
19
20
21
22
AGND
VREG
9
10
11
12
13
14
15
16
INPUT_C
INPUT_D
TEST
NC
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
OUT_D
PVDD_D
PVDD_D
BST_D
NC
NC
SD
OTW1
64-pins QFP package
NC
SD
OTW
READY
M1
M2
M3
GVDD_CD
PIN ONE LOCATION PHD PACKAGE
Electrical Pin 1
Pin 1 Marker
White Dot
2
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SLAS596B –JUNE 2009–REVISED JANUARY 2010
MODE SELECTION PINS
MODE PINS
ANALOG
INPUT(1)
OUTPUT
CONFIGURATION
DESCRIPTION
M3
0
M2
0
M1
0
2N
—
2 × BTL
—
AD mode
Reserved
BD mode
AD mode
AD mode
0
0
1
0
1
0
2N
1N
1N
2 × BTL
0
1
1
1 × BTL +2 × SE
4 × SE
1
0
0
INPUT_C(2)
INPUT_D(2)
1
0
1
2N
1 × PBTL
0
1
0
AD mode
BD mode
0
1
1
1
1
0
1
Reserved
(1) The 1N and 2N naming convention is used to indicate the number of PWM lines to the power stage per channel in a specific mode.
(2) INPUT_C and D are used to select between a subset of AD and BD mode operations in PBTL mode (1=VREG and 0=AGND)..
PACKAGE HEAT DISSIPATION RATINGS(1)
PARAMETER
TAS5616PHD
3.63
TAS5616DKD
2.52
R
qJC (°C/W) – 2 BTL or 4 SE channels
RqJC (°C/W) – 1 BTL or 2 SE channel(s)
5.95
3.22
RqJC (°C/W) – 1 SE channel
9.9
6.9
(2)
Pad Area
49 mm2
80 mm2
(1) JC is junction-to-case, CH is case-to-heat sink
(2) qCH is an important consideration. Assume a 2-mil thickness of typical thermal grease between the pad area and the heat sink and
R
both channels active. The RqCH with this condition is 1.22°C/W for the PHD package and 1.02°C/W for the DKD package
Table 1. ORDERING INFORMATION(1)
TA
PACKAGE
TAS5616PHD
TAS5616DKD
DESCRIPTION
64 pin HTQFP
44 pin PSOP3
0°C–70°C
0°C–70°C
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Copyright © 2009–2010, Texas Instruments Incorporated
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SLAS596B –JUNE 2009–REVISED JANUARY 2010
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
TAS5616
UNIT
V
VDD to AGND
–0.3 to 13.2
–0.3 to 13.2
–0.3 to 69.0
–0.3 to 69.0
–0.3 to 82.2
–0.3 to 69.0
–0.3 to 4.2
–0.3 to 0.3
–0.3 to 0.3
–0.3 to 0.3
–0.3 to 4.2
–0.3 to 5.0
–0.3 to 7.0
9
GVDD to AGND
PVDD_X to GND_X(2)
OUT_X to GND_X(2)
BST_X to GND_X(2)
V
V
V
V
BST_X to GVDD_X(2)
V
VREG to AGND
V
GND_X to GND
V
GND_X to AGND
V
GND to AGND
V
OC_ADJ, M1, M2, M3, VI_CM, C_STARTUP, PSU_REF to AGND
INPUT_X
V
V
RESET, SD, OTW1, OTW2, CLIP, READY to AGND
Maximum continuous sink current (SD, OTW1, OTW2, CLIP, READY)
Maximum operating junction temperature range, TJ
Storage temperature, Tstg
V
mA
°C
°C
kV
V
0 to 150
–40 to 150
±2
Human-Body Model (3) (all pins)
Charged-Device Model (3) (all pins)
Electrostatic discharge
±500
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions.
(3) Failure to follow good anti-static ESD handling during manufacture and rework will contribute to device malfunction. Please ensure
operators handling the device are adequately grounded through the use of ground straps or alternative ESD protection.
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX UNIT
Half-bridge supply
25
25
50
38
52.5
V
PVDD_x
GVDD_x
DC supply voltage
Half-bridge supply, BTL 4Ω load
40
Supply for logic regulators and gate-drive
circuitry
DC supply voltage
DC supply voltage
10.8
12
13.2
13.2
V
V
VDD
Digital regulator supply voltage
10.8
7
12
8
RL(BTL)
RL(SE)
Output filter according to
schematics in the application
information section.
Load impedance
3.5
3.5
14
4
Ω
RL(PBTL)
LOUTPUT(BTL)
LOUTPUT(SE)
LOUTPUT(PBTL)
FPWM
4
15
15
15
Minimum output inductance under
short-circuit condition
Output filter inductance
14
mH
14
PWM frame rate
352 384
0
500
150
kHz
°C
TJ
Junction temperature
4
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SLAS596B –JUNE 2009–REVISED JANUARY 2010
TERMINAL FUNCTIONS
TERMINAL
FUNCTION(1)
DESCRIPTION
PHD
NO.
DKD
NO.
NAME
AGND
8
10
43
34
33
24
5
P
P
P
P
P
O
O
Analog ground
BST_A
BST_B
BST_C
BST_D
C_STARTUP
CLIP
54
41
40
27
3
HS bootstrap supply (BST), external 0.033 mF capacitor to OUT_A required.
HS bootstrap supply (BST), external 0.033 mF capacitor to OUT_B required.
HS bootstrap supply (BST), external 0.033 mF capacitor to OUT_C required.
HS bootstrap supply (BST), external 0.033 mF capacitor to OUT_D required.
Startup ramp requires a charging capacitor of 4.7 nF to AGND
Clipping warning; open drain; active low
18
—
7, 23,
24, 57,
58
GND
9
P
Ground
GND_A
GND_B
GND_C
GND_D
GVDD_A
GVDD_AB
GVDD_B
GVDD_C
GVDD_CD
GVDD_D
INPUT_A
INPUT_B
INPUT_C
INPUT_D
M1
48, 49
46, 47
34, 35
32, 33
55
38
37
30
29
—
44
—
—
23
—
6
P
P
P
P
P
P
P
P
P
P
I
Power ground for half-bridge A
Power ground for half-bridge B
Power ground for half-bridge C
Power ground for half-bridge D
Gate drive voltage supply requires 0.1 mF capacitor to AGND
Gate drive voltage supply requires 0.22 mF capacitor to AGND
Gate drive voltage supply requires 0.1 mF capacitor to AGND
Gate drive voltage supply requires 0.1 mF capacitor to AGND
Gate drive voltage supply requires 0.22 mF capacitor to AGND
Gate drive voltage supply requires 0.1 mF capacitor to AGND
Input signal for half bridge A
—
56
25
—
26
4
5
7
I
Input signal for half bridge B
10
12
13
20
21
22
—
15
16
3
I
Input signal for half bridge C
11
I
Input signal for half bridge D
20
I
Mode selection
M2
21
I
Mode selection
M3
22
I
Mode selection
NC
59-62
13
—
—
—
O
No connect, pins may be grounded.
No connect, pins may be grounded.
No connect, pins may be grounded.
NC
NC
14
OC_ADJ
1
Analog over current programming pin requires resistor to ground.
64 pin QFP package (PHD) = 22 kΩ
44 pin PSOP3 Package (DKD) = 24 kΩ
OTW
—
16
18
—
O
O
O
O
O
O
O
P
P
P
P
P
O
I
Overtemperature warning signal, open drain, active low.
Overtemperature warning signal, open drain, active low.
Overtemperature warning signal, open drain, active low.
Output, half bridge A
OTW1
OTW2
17
—
OUT_A
OUT_B
OUT_C
OUT_D
PSU_REF
PVDD_A
PVDD_B
PVDD_C
PVDD_D
READY
RESET
SD
52, 53
44, 45
36, 37
28, 29
63
39, 40
36
Output, half bridge B
31
Output, half bridge C
27, 28
1
Output, half bridge D
PSU Reference requires close decoupling of 4.7 mF to AGND
Power supply input for half bridges A requires close decoupling of 2.2-mF capacitor to GND_A
Power supply input for half bridges B requires close decoupling of 2.2-mF capacitor to GND_B
Power supply input for half bridges C requires close decoupling of 2.2-mF capacitor to GND_C
Power supply input for half bridges D requires close decoupling of 2.2-mF capacitor to GND_D
Normal operation; open drain; active high
50, 51
42, 43
38, 39
30, 31
19
41, 42
35
32
25, 26
19
2
4
Device reset Input; active low
15
17
O
I
Shutdown signal, open drain, active low
TEST
12
14
Connect to VREG node
(1) I = Input, O = Output, P = Power
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TERMINAL FUNCTIONS (continued)
TERMINAL
FUNCTION(1)
DESCRIPTION
PHD
NO.
DKD
NO.
NAME
Power supply for digital voltage regulator requires a 10-mF capacitor in parallel with a 0.1-mF
capacitor to GND for decoupling.
VDD
64
2
P
VI_CM
VREG
6
9
8
O
P
Analog comparator reference input requires close decoupling of 4.7 mF to AGND
Digital regulator supply filter pin requires 0.1-mF capacitor to AGND
11
TYPICAL SYSTEM BLOCK DIAGRAM
Caps for
External
Filtering
&
System
microcontroller
/AMP RESET
I2C
(2)
Startup/Stop
TAS5518/
TAS5508/
TAS5086
*NOTE1
/RESET
BST_A
VALID
Bootstrap
Caps
BST_B
2nd Order
PWM_A
PWM_B
INPUT_A
INPUT_B
OUT_A
Left-
Channel
Output
L-C Output
Filter for
each
Input
H-Bridge 1
Output
H-Bridge 1
2
OUT_B
2
H-Bridge
2-CHANNEL
H-BRIDGE
BTL MODE
2nd Order
L-C Output
Filter for
each
PWM_C
PWM_D
INPUT_C
INPUT_D
OUT_C
Right-
Channel
Output
Input
H-Bridge 2
Output
H-Bridge 2
2
OUT_D
2
H-Bridge
M1
BST_C
BST_D
Hardwire
Mode
Control
M2
M3
Bootstrap
Caps
8
8
4
Hardwire
PVDD
GND
PVDD
Power Supply
Decoupling
GVDD, VDD,
50V
Over-
Current
Limit
& VREG
Power Supply
Decoupling
SYSTEM
Power
Supplies
GND
12V
GVDD (12V)/VDD (12V)
VAC
*NOTE1: Logic AND in or outside microcontroller
6
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SLAS596B –JUNE 2009–REVISED JANUARY 2010
FUNCTIONAL BLOCK DIAGRAM
/CLIP
READY
/OTW1
/OTW2
/SD
M1
M2
M3
VDD
POWER-UP
RESET
UVP
VREG
VREG
AGND
GND
/RESET
TEMP
SENSE
GVDD_A
GVDD_C
STARTUP
CONTROL
GVDD_B
GVDD_D
C_STARTUP
OVER-LOAD
PROTECTION
CURRENT
SENSE
CB3C
OC_ADJ
4
4
4
PVDD_X
OUT_X
GND_X
PPSC
GVDD_A
BST_A
PWM
ACTIVITY
DETECTOR
PVDD_A
OUT_A
GND_A
GVDD_B
BST_B
PWM
RECEIVER
TIMING
CONTROL
CONTROL
GATE-DRIVE
GATE-DRIVE
GATE-DRIVE
GATE-DRIVE
PSU_REF
VI_CM
-
ANALOG
LOOP FILTER
INPUT_A
INPUT_B
+
PVDD_B
OUT_B
GND_B
GVDD_C
BST_C
PWM
RECEIVER
TIMING
CONTROL
CONTROL
CONTROL
CONTROL
+
-
ANALOG
LOOP FILTER
4
PVDD_X
GND
AGC
INPUT_C
INPUT_D
PVDD_C
OUT_C
GND_C
GVDD_D
BST_D
-
ANALOG
LOOP FILTER
+
PWM
RECEIVER
TIMING
CONTROL
+
-
ANALOG
LOOP FILTER
PVDD_D
OUT_D
GND_D
PWM
RECEIVER
TIMING
CONTROL
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AUDIO CHARACTERISTICS (BTL)
Audio performance is recorded as a chipset consisting of a TAS5518 PWM Processor (modulation index limited to 97.7%)
and a TAS5616 power stage. PCB and system configuration are in accordance with recommended guidelines. Audio
frequency = 1kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL = 4Ω, fS = 384 kHz, ROC = 24 kΩ, TC = 75°C, Output Filter: LDEM
15 mH, CDEM = 680 nF, MODE = 000, unless otherwise noted.
=
PARAMETER
TEST CONDITIONS
RL = 8 Ω, 10% THD+N
MIN
TYP
160
125
MAX UNIT
PO
Power output per channel
W
RL = 8 Ω, 1% THD+N
Total harmonic distortion +
noise
THD+N
Vn
1 W
0.03%
Output integrated noise
Output offset supply
Signal to noise ratio(1)
Dynamic range
A-weighted, TAS5518 Modulator
No signal
185
40
mV
mV
dB
dB
|VOS
|
150
SNR
DNR
A-weighted, TAS5518 Modulator
A-weighted, input level –60 dBFS using TAS5518 modulator
103
103
Power dissipation due to idle
losses (IPVDD_X)
Pidle
PO = 0, 4 channels switching(2)
1.8
W
(1) SNR is calculated relative to 1% THD+N output level.
(2) Actual system idle losses also are affected by core losses of output inductors.
AUDIO SPECIFICATION (Single-Ended Output)
Audio performance is recorded as a chipset consisting of a TAS5086 PWM Processor (modulation index limited to 97.7%)
and a TAS5616 power stage. PCB and system configuration are in accordance with recommended guidelines. Audio
frequency = 1kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL = 4Ω, fS = 384 kHz, ROC_PHD = 22 kΩ, or ROC_DLD = 24 kΩ, TC =
75°C, Output Filter: LDEM = 15 mH, CDEM = 330 nF, MODE = 100, unless otherwise noted.
PARAMETER
TEST CONDITIONS
RL = 4 Ω, 10%, THD+N
MIN
TYP MAX UNIT
75
PO
Power output per channel
W
RL = 4 Ω, 0 dBFS
60
THD+N Total harmonic distortion + noise
1 W
0.05%
170
Vn
Output integrated noise
Signal to noise ratio(1)
A-weighted, TAS5086 modulator
A-weighted, TAS5086 modulator
mV
SNR
98
dB
A-weighted, input level –60 dBFS using TAS5086
modulator
DNR
Pidle
Dynamic range
98
dB
W
Power dissipation due to idle losses
(IPVDD_X)
PO = 0, 4 channels switching(2)
2
(1) SNR is calculated relative to 1% THD+N output level
(2) Actual system idle losses are affected by core losses of output inductors.
AUDIO SPECIFICATION (PBTL)
Audio performance is recorded as a chipset consisting of a TAS5518 PWM Processor (modulation index limited to 97.7%)
and a TAS5616 power stage. PCB and system configuration are in accordance with recommended guidelines. Audio
frequency = 1kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL = 4Ω, fS = 384 kHz, ROC_PHD = 22 kΩ, ROC_DKD = 24 kΩ, TC = 75°C,
Output Filter: LDEM = 15 mH, CDEM = 680 nF, MODE = 101-00, unless otherwise noted.
PARAMETER
TEST CONDITIONS
RL = 4 Ω, 10%, THD+N
MIN
TYP MAX UNIT
300
PO
Power output per channel
W
RL = 4 Ω, 1%, THD+N
1 W
210
THD+N Total harmonic distortion + noise
0.03%
180
Vn
Output integrated noise
Signal to noise ratio(1)
A-weighted, TAS5518 modulator
A-weighted, TAS5518 modulator
mV
SNR
103
103
1.8
dB
A-weighted, input level –60 dBFS using
TAS5518 modulator
DNR
Pidle
Dynamic range
dB
W
Power dissipation due to idle losses (IPVDD_X) PO = 0, 4 channels switching(2)
(1) SNR is calculated relative to 1% THD+N output level
(2) Actual system idle losses are affected by core losses of output inductors.
8
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ELECTRICAL CHARACTERISTICS
PVDD_X = 50 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 384 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
Voltage regulator, only used as reference
VREG
VI_CM
VDD = 12 V
3
3.3
3.6
1.9
V
V
node
Analog comparator reference node
1.5
1.75
22.5
22.5
8
Operating, 50% duty cycle
Idle, reset mode
50% duty cycle
IVDD
VDD supply current
mA
mA
IGVDD_x
Gate-supply current per half-bridge
Reset mode
1.5
50% duty cycle without output filter or
load
9
mA
IPVDD_x
Half-bridge idle current
Reset mode, No switching
610
mA
OUTPUT-STAGE MOSFETs
RDS(on),LS
Drain-to-source resistance, (LS)
120 200
120 200
mΩ
mΩ
TJ = 25°C, exclude metallization
resistance, GVDD = 12 V
RDS(on),HS
Drain-to-source resistance, (HS)
I/O PROTECTION
Vuvp,G
Undervoltage protection limit, GVDD_x
9.5
V
V
(1)
Vuvp,hyst
0.6
OTW1(1)
OTW2(1)
Overtemperature warning 1
Overtemperature warning 2
95
100 105
125 135
°C
°C
115
Temperature drop needed below OTW
temperature for OTW to be inactive after
OTW event.
(1)
OTWHYST
25
°C
OTE(1)
OTE-
Overtemperature error
145
155 165
30
°C
°C
OTE-OTW differential
(1)
OTWdifferential
A reset needs to occur for SD to be released
following an OTE event
(1)
OTEHYST
25
°C
OLPC
Overload protection counter
fPWM = 384 kHz
2.6
ms
Resistor – programmable, nominal peak
current in 1Ω load, 64 pin QFP package
(PHD)
10
10
A
A
ROCP = 22 kΩ
IOC
Overcurrent limit protection
Resistor – programmable, nominal peak
current in 1Ω load, 44 pin PSOP3
package (DKD)
ROCP = 24 kΩ
Resistor – programmable, nominal peak
current in 1Ω load,
ROCP = 47 kΩ
IOC_LATCHED
Overcurrent limit protection
10
150
3
A
Time from application of short condition to
Hi-Z of affected half bridge
IOCT
Overcurrent response time
ns
Connected when RESET is active to
provide bootstrap charge. Not used in SE
mode.
IPD
Output pulldown current of each half bridge
mA
STATIC DIGITAL SPECIFICATIONS
VIH
High level input voltage
Low level input voltage
Input leakage current
2
V
V
INPUT_X, M1, M2, M3, RESET
VIL
0.8
Leakage
100
mA
(1) Specified by design.
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ELECTRICAL CHARACTERISTICS (continued)
PVDD_X = 50 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 384 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
OTW/SHUTDOWN (SD)
Internal pull-up resistance, OTW1 to VREG,
OTW2 to VREG, SD to VREG
RINT_PU
VOH
20
26
32
kΩ
Internal pull-up resistor
3
3.3
3.6
5
High level output voltage
Low level output voltage
V
External pull-up of 4.7 kΩ to 5 V
4.5
VOL
IO = 4 mA
200 500
mV
Device fanout OTW1, OTW2, SD, CLIP,
READY
FANOUT
No external pull-up
30
devices
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION
TOTAL HARMONIC+NOISE
OUTPUT POWER
vs
vs
OUTPUT POWER
SUPPLY VOLTAGE
10
5
180
170
160
150
140
130
120
110
100
90
T
= 75°C
T
= 75°C
C
THD+N at 10%
C
2
1
0.5
8 W
0.2
0.1
80
70
60
0.05
8 W
50
40
0.02
0.01
30
20
10
0.005
0
20m 100m 200m
1
2
10 20
100 200
25 27 29 31 33 35 37 39 41 43 45 47 49
V
P
O
- Output Power - W
- Supply Voltage - Vrms
CC
Figure 1.
Figure 2.
UNCLIPPED OUTPUT POWER
SYSTEM EFFICIENCY
vs
vs
SUPPLY VOLTAGE
OUTPUT POWER
100
90
80
70
60
50
40
30
20
10
0
150
140
130
120
110
100
90
T
= 75°C
C
THD+N at 1%
8 W
8 W
80
70
60
50
40
T
= 25°C
C
THD+N at 10%
30
20
10
0
0
40
80 120 160 200 240 280 320 360
2 Channel Output Power - W
25 27 29 31 33 35 37 39 41 43 45 47 49
V
- Supply Voltage - Vrms
CC
Figure 3.
Figure 4.
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
SYSTEM POWER LOSS
vs
OUTPUT POWER
vs
OUTPUT POWER
CASE TEMPERATURE
40
36
32
28
24
20
16
12
8
200
180
160
140
120
100
80
T
= 25°C
C
THD+N at 10%
8 W
8 W
60
40
THD+N at 10%
20
4
0
0
10 20 30 40 50 60 70 80 90 100 110 120
0
40
80
120 160 200 240 280 320 360
T
- Case Temperature - C
C
2 Channel Output Power - W
Figure 5.
Figure 6.
NOISE AMPLITUDE
vs
FREQUENCY - VREF = 32.7 V
0
T
C
= 75°C
V
= 32.69V
-20
-40
REF
Sample Rate = 48 kHz
FFT Size = 16384
-60
-80
-100
-120
-140
-160
8 W
0
2
4
6
8 10 12 14 16 18 20 22
f - Frequency - kHz
Figure 7.
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TYPICAL CHARACTERISTICS, SE CONFIGURATION
TOTAL HARMONIC DISTORTION
OUTPUT POWER
vs
vs
OUTPUT POWER
SUPPLY VOLTAGE
10
5
90
80
70
60
50
40
30
20
10
0
T
= 75°C
C
T
= 75°C
4 W
C
THD+N at 10%
2
1
6 W
0.5
4 W
8 W
6 W
0.2
0.1
8 W
0.05
0.02
0.01
0.005
20m
100m 200m
1
2
10 20
100
25 27 29 31 33 35 37 39 41 43 45 47 49
P
O
- Output Power - W
V
- Supply Voltage - Vrms
CC
Figure 8.
Figure 9.
OUTPUT POWER
vs
CASE TEMPERATURE
90
80
70
60
50
40
30
20
10
0
4 W
6 W
8 W
THD+N at 10%
10 20 30 40 50 60 70 80 90 100 110 120
- Case Temperature - °C
T
C
Figure 10.
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TYPICAL CHARACTERISTICS, PBTL CONFIGURATION
TOTAL HARMONIC DISTORTION
OUTPUT POWER
vs
vs
OUTPUT POWER
SUPPLY VOLTAGE
10
340
320
300
280
260
240
220
200
180
160
140
120
100
80
T
= 75°C
T
= 75°C
C
C
THD+N at 10%
4 W
2
1
6 W
4 W
6 W
0.2
0.1
8 W
8 W
0.02
0.01
60
40
20
0
0.005
25 27 29 31 33 35 37 39 41 43 45 47 49
- Supply Voltage - Vrms
20m 100m 200m
1
2
10 20
100 200 500
V
CC
P
- Output Power - W
O
Figure 11.
Figure 12.
OUTPUT POWER
vs
CASE TEMPERATURE
360
340
320
300
280
260
240
220
200
180
160
140
120
100
80
4 W
6 W
8 W
60
40
THD+N at 10%
20
0
10 20 30 40 50 60 70 80 90 100 110 120
T
- Case Temperature - °C
C
Figure 13.
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APPLICATION INFORMATION
PCB Material Recommendation
FR-4 Glass Epoxy material with 2 oz. (70 mm) is recommended for use with the TAS5616. The use of this
material can provide for higher power output, improved thermal performance, and better EMI margin (due to
lower PCB trace inductance.
PVDD Capacitor Recommendation
The large capacitors used in conjunction with each full-bridge, are referred to as the PVDD Capacitors. These
capacitors should be selected for proper voltage margin and adequate capacitance to support the power
requirements. In practice, with a well designed system power supply, 1000mF, 63V will support more
applications. The PVDD capacitors should be low ESR type because they are used in a circuit associated with
high-speed switching.
Decoupling Capacitor Recommendations
In order to design an amplifier that has robust performance, passes regulatory requirements, and exhibits good
audio performance, good quality decoupling capacitors should be used. In practice, X7R should be used in this
application.
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the
selection of the 0.1mF that is placed on the power supply to each half-bridge. It must withstand the voltage
overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the ripple
current created by high power output. A minimum voltage rating of 63V is required for use with a 50V power
supply.
System Design Recommendations
The following schematics and PCB layouts illustrate best practices in the use of the TAS5616.
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G N D _ A
P V D D _ A
P V D D _ A
O U T _ A
G N D _ D
P V D D _ D
P V D D _ D
O U T _ D
O U T _ D
B S T _ D
G V D D _ D
G V D D _ C
G N D
O U T _ A
B S T _ A
G V D D _ A
G V D D _ B
G N D
G N D
N C
G N D
M 3
N C
N C
N C
M 2
M 1
R E A D Y
/ C L I P
P S U _ R E F
V D D
T W / 2 O
Figure 14. Typical Differential (2N) BTL Application With BD Filters
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G N D _ A
P V D D _ A
P V D D _ A
O U T _ A
G N D _ D
3 2
4 9
5 0
5 1
5 2
5 3
5 4
5 5
5 6
5 7
5 8
5 9
6 0
6 1
6 2
6 3
6 4
P V D D _ D
3 1
P V D D _ D
3 0
O U T _ D
2 9
O U T _ A
O U T _ D
2 8
B S T _ A
B S T _ D
2 7
G V D D _ A
G V D D _ B
G V D D _ D
2 6
G V D D _ C
2 5
G N D
G N D
N C
G N D
2 4
G N D
2 3
M 3
2 2
N C
N C
N C
M 2
2 1
M 1
2 0
R E A D Y
1 9
P S U _ R E F
/ C L I P
1 8
V D D
T W / 2 O
1 7
Figure 15. Typical (2N) PBTL Application With AD Modulation Filters
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G N D _ A
4 9
G N D _ D
3 2
P V D D _ A
5 0
P V D D _ D
3 1
P V D D _ A
5 1
P V D D _ D
3 0
O U T _ A
5 2
O U T _ D
2 9
O U T _ A
5 3
O U T _ D
2 8
B S T _ A
5 4
B S T _ D
2 7
G V D D _ A
5 5
G V D D _ D
2 6
G V D D _ B
5 6
G V D D _ C
2 5
G N D
5 7
G N D
2 4
G N D
5 8
G N D
2 3
N C
5 9
M 3
2 2
N C
6 0
M 2
2 1
N C
6 1
M 1
2 0
N C
6 2
R E A D Y
1 9
P S U _ R E F
6 3
/ C L I P
1 8
V D D
6 4
T W / 2 O
1 7
Figure 16. Typical SE Application
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G N D _ A
P V D D _ A
P V D D _ A
O U T _ A
G N D _ D
3 2
4 9
5 0
5 1
5 2
5 3
5 4
5 5
5 6
5 7
5 8
5 9
6 0
6 1
6 2
6 3
6 4
P V D D _ D
3 1
P V D D _ D
3 0
O U T _ D
2 9
O U T _ A
O U T _ D
2 8
B S T _ A
B S T _ D
2 7
G V D D _ A
G V D D _ B
G V D D _ D
2 6
G V D D _ C
2 5
G N D
G N D
N C
G N D
2 4
G N D
2 3
M 3
2 2
N C
N C
N C
M 2
2 1
M 1
2 0
R E A D Y
1 9
P S U _ R E F
/ C L I P
1 8
V D D
T W / 2 O
1 7
Figure 17. Typical 2.1 System (2N) Input BTL and (1N) Input SE Application
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Figure 18. Typical Input BTL Application and BD Modulation Filters DKD Package
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THEORY OF OPERATION
POWER SUPPLIES
To facilitate system design, the TAS5616 needs only a 12V supply in addition to the (typical) 50V power-stage
supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog
circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is
accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.
In order to provide outstanding electrical and acoustical characteristics, the PWM signal path including gate drive
and output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has
separate gate drive supply (GVDD_X), bootstrap pins (BST_X), and power-stage supply pins (PVDD_X).
Furthermore, an additional pin (VDD) is provided as supply for all common circuits. Although supplied from the
same 12V source, it is highly recommended to separate GVDD_A, GVDD_B, GVDD_C, GVDD_D, and VDD on
the printed-circuit board (PCB) by RC filters (see application diagram for details). These RC filters provide the
recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as
close to their associated pins as possible. In general, inductance between the power supply pins and decoupling
capacitors must be avoided. (See reference board documentation for additional information.)
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the
bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM
switching frequencies in the range from 300kHz to 400kHz, it is recommended to use 33nF ceramic capacitors,
size 0603 or 0805, for the bootstrap supply. These 33nF capacitors ensure sufficient energy storage, even during
minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining
part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is
decoupled with a 2.2mF ceramic capacitor placed as close as possible to each supply pin. It is recommended to
follow the PCB layout of the TAS5616 reference design. For additional information on recommended power
supply and required components, see the application diagrams given previously in this data sheet.
The 12V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 50V
power-stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not
critical as facilitated by the internal power-on-reset circuit. Moreover, the TAS5616 is fully protected against
erroneous power-stage turn on due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are
non-critical within the specified range (see the Recommended Operating Conditions table of this data sheet).
SYSTEM POWER-UP/POWER-DOWN SEQUENCE
Powering Up
The TAS5616 does not require a power-up sequence. The outputs of the H-bridges remain in a high-impedance
state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage protection
(UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). Although not specifically
required, it is recommended to hold RESET in a low state while powering up the device. This allows an internal
circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output.
Powering Down
The TAS5616 does not require a power-down sequence. The device remains fully operational as long as the
gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage
threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is a
good practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks.
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ERROR REPORTING
The SD, OTW, OTW1 and OTW2 pins are active-low, open-drain outputs. Their function is for protection-mode
signaling to a PWM controller or other system-control device.
Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW and OTW2 goes low
when the device junction temperature exceeds 125°C and OTW1 goes low when the junction temperature
exceeds 100°C (see the following table).
SD
OTW1
OTW2,
OTW
DESCRIPTION
0
0
0
0
0
1
Overtemperature (OTE) or overload (OLP) or undervoltage (UVP)
Overload (OLP) or undervoltage (UVP). Junction temperature
higher than 100°C (overtemperature warning)
0
1
1
1
1
0
0
1
1
0
1
1
Overload (OLP) or undervoltage (UVP)
Junction temperature higher than 125°C (overtemperature warning)
Junction temperature higher than 100°C (overtemperature warning)
Junction temperature lower than 100°C and no OLP or UVP faults
(normal operation)
Note that asserting either RESET low forces the SD signal high, independent of faults being present. TI
recommends monitoring the OTW signal using the system microcontroller and responding to an overtemperature
warning signal by, e.g., turning down the volume to prevent further heating of the device resulting in device
shutdown (OTE).
To reduce external component count, an internal pullup resistor to 3.3 V is provided on both SD and OTW
outputs. Level compliance for 5-V logic can be obtained by adding external pullup resistors to 5 V (see the
Electrical Characteristics table of this data sheet for further specifications).
DEVICE PROTECTION SYSTEM
The TAS5616 contains advanced protection circuitry carefully designed to facilitate system integration and ease
of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as
short circuits, overload, overtemperature, and undervoltage. The TAS5616 responds to a fault by immediately
setting the power stage in a high-impedance (Hi-Z) state and asserting the SD pin low. In situations other than
overload and over-temperature error (OTE), the device automatically recovers when the fault condition has been
removed, i.e., the supply voltage has increased.
The device will function on errors, as shown in the following table.
BTL MODE
LOCAL ERROR IN
PBTL MODE
LOCAL ERROR IN
SE MODE
LOCAL ERROR IN
TURNS OFF
TURNS OFF
TURNS OFF
A
B
C
D
A
B
C
D
A
B
C
D
A+B
A+B
A+B+B+D
B+D
B+D
Bootstrap UVP does not shutdown according to the table, it shuts down the respective halfbridge.
PIN-TO-PIN SHORT CIRCUIT PROTECTION (PPSC)
The PPSC detection system protects the device from permanent damage in the case that a power output pin
(OUT_X) is shorted to GND_X or PVDD_X. For comparison the OC protection system detects an over current
after the demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection is
performed at startup i.e. when VDD is supplied, consequently a short to either GND_X or PVDD_X after system
startup will not activate the PPSC detection system. When PPSC detection is activated by a short on the output,
all half bridges are kept in a Hi-Z state until the short is removed, the device then continues the startup sequence
and starts switching. The detection is controlled globally by a two step sequence. The first step ensures that
there are no shorts from OUT_X to GND_X, the second step tests that there are no shorts from OUT_X to
PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC filter. The
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typical duration is < 15 ms/mF. While the PPSC detection is in progress, SD is kept low, and the device will not
react to changes applied to the RESET pins. If no shorts are present the PPSC detection passes, and SD is
released. A device reset will not start a new PPSC detection. PPSC detection is enabled in BTL and PBTL output
configurations, the detection is not performed in SE mode. To make sure not to trip the PPSC detection system it
is recommended not to insert resistive load to GND_X or PVDD_X.
OVERTEMPERATURE PROTECTION
The two different package options have individual over-temperature protection schemes.
PHD Package
The TAS5616 PHD package option has a three-level temperature-protection system that asserts an active-low
warning signal (OTW1) when the device junction temperature exceeds 100°C (typical), (OTW2) when the device
junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds 155°C (typical), the
device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z)
state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted.
Thereafter, the device resumes normal operation.
DKD Package
The TAS5616 DKD package option has a two-level temperature-protection system that asserts an active-low
warning signal (OTW) when the device junction temperature exceeds 125°C (typical) and, if the device junction
temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs
being set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case. To clear the
OTE latch, RESET must be asserted. Thereafter, the device resumes normal operation.
UNDERVOLTAGE PROTECTION (UVP) AND POWER-ON RESET (POR)
The UVP and POR circuits of the TAS5616 fully protect the device in any power-up/down and brownout situation.
While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully
operational when the GVDD_X and VDD supply voltages reach stated in the Electrical Characteristics Table.
Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on
any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z)
state and SD being asserted low. The device automatically resumes operation when all supply voltages have
increased above the UVP threshold.
DEVICE RESET
When RESET is asserted low, all power-stage FETs in the four half-bridges are forced into a high-impedance
(Hi-Z) state.
In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables
weak pulldown of the half-bridge outputs. In the SE mode, the output is forced into a high impedance state when
asserting the reset input low. Asserting reset input low removes any fault information to be signaled on the SD
output, i.e., SD is forced high. A rising-edge transition on reset input allows the device to resume operation after
an overload fault. To ensure thermal reliability, the rising edge of reset must occur no sooner than 4 ms after the
falling edge of SD.
SYSTEM DESIGN CONSIDERATION
A rising-edge transition on reset input allows the device to execute the startup sequence and starts switching.
Apply only audio when the state of READY is high that will start and stop the amplifier without having audible
artifacts that is heard in the output transducers. If an overcurrent protection event is introduced the READY signal
goes low hence filtering is needed if the signal is intended for audio muting.
The CLIP signal is indicating that the output is approaching clipping. The signal can be used to either an audio
volume decrease or intelligent power supply controlling a low and a high rail.
The VREG pin is not recommended to be used as a voltage source for external circuitry.
Copyright © 2009–2010, Texas Instruments Incorporated
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Product Folder Link(s) :TAS5616
TAS5616
SLAS596B –JUNE 2009–REVISED JANUARY 2010
www.ti.com
PRINTED CIRCUIT BOARD RECOMMENDATION
Use an unbroken ground plane to have good low impedance and inductance return path to the power supply for
power and audio signals. PCB layout, audio performance and EMI are linked closely together. The circuit
contains high fast switching currents; therefore, care must be taken to prevent damaging voltage spikes. Routing
the audio input should be kept short and together with the accompanied audio source ground. A local ground
area underneath the device is important to keep solid to minimize ground bounce.
Netlist for this printed circuit board is generated from the schematic in Figure 14.
Note T1: PVDD decoupling bulk capacitors C60-C64 should be as close as possible to the PVDD and GND_X pins,
the heat sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and
without going through vias. No vias or traces should be blocking the current path.
Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and
close to the pins.
Note T3: Heat sink needs to have a good connection to PCB ground.
Note T4: Output filter capacitors must be linear in the applied voltage range preferable metal film types.
Figure 19. Printed Circuit Board - Top Layer
24
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Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s) :TAS5616
TAS5616
www.ti.com
SLAS596B –JUNE 2009–REVISED JANUARY 2010
Note B1: It is important to have a direct low impedance return path for high current back to the power supply. Keep
impedance low from top to bottom side of PCB through a lot of ground vias.
Note B2: Bootstrap low impedance X7R ceramic capacitors placed on bottom side providing a short low inductance
current loop.
Note B3: Return currents from bulk capacitors and output filter capacitors.
Figure 20. Printed Circuit Board - Bottom Layer
REVISION HISTORY
Changes from Original (June 2009) to Revision A
Page
•
Deleted Product Preview from the PHD package ................................................................................................................. 3
Changes from Revision A (September 2009) to Revision B
Page
•
•
•
NC pin function changed from "I/O" to "—" .......................................................................................................................... 5
OLPC typical value changed from 1.3 ms to 2.6 ms ............................................................................................................ 9
Changed error-reporting bits from 010 to 011 .................................................................................................................... 22
Copyright © 2009–2010, Texas Instruments Incorporated
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25
Product Folder Link(s) :TAS5616
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jan-2010
PACKAGING INFORMATION
Orderable Device
TAS5616DKD
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
HSSOP
DKD
44
44
64
64
29 Green (RoHS & CU NIPDAU Level-4-260C-72 HR
no Sb/Br)
TAS5616DKDR
TAS5616PHD
HSSOP
HTQFP
HTQFP
DKD
PHD
PHD
500 Green (RoHS & CU NIPDAU Level-4-260C-72 HR
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-5A-260C-24 HR
no Sb/Br)
TAS5616PHDR
1000 Green (RoHS & CU NIPDAU Level-5A-260C-24 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jan-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TAS5616DKDR
TAS5616PHDR
HSSOP
HTQFP
DKD
PHD
44
64
500
330.0
330.0
24.4
24.4
14.7
17.0
16.4
17.0
4.0
1.5
20.0
20.0
24.0
24.0
Q1
Q2
1000
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jan-2010
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TAS5616DKDR
TAS5616PHDR
HSSOP
HTQFP
DKD
PHD
44
64
500
346.0
346.0
346.0
346.0
41.0
41.0
1000
Pack Materials-Page 2
IMPORTANT NOTICE
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and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
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Applications
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Amplifiers
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
www.ti.com/audio
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www.ti.com/communications
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dsp.ti.com
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www.ti.com/clocks
interface.ti.com
logic.ti.com
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power.ti.com
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www.ti-rfid.com
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www.ti.com/security
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www.ti.com/space-avionics-defense
RF/IF and ZigBee® Solutions www.ti.com/lprf
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www.ti.com/video
www.ti.com/wireless-apps
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Copyright © 2010, Texas Instruments Incorporated
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