TAS5722LRSMT [TI]

15W 单声道、4.5V 至 17V 电源电压、数字输入 D 类音频放大器 | RSM | 32 | -25 to 85;


型号：	TAS5722LRSMT
厂家：	TEXAS INSTRUMENTS
描述：	15W 单声道、4.5V 至 17V 电源电压、数字输入 D 类音频放大器 \| RSM \| 32 \| -25 to 85 放大器商用集成电路音频放大器
文件：	总53页 (文件大小：1869K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TAS5722L

ZHCSFV9A –MAY 2016–REVISED DECEMBER 2016

TAS5722L 15W 数字输入单声道 D 类音频放大器

1 特性

2 应用

•

单声道 D 类放大器

•

低音炮、音箱、条形音响、楼宇自动化

有源扬声器，个人计算机

–

0.02% THD 时为 4Ω/

17V 持续提供 15W 功率

环绕立体声系统，单声道音频系统

•

> 90% 的高效 D 类运行，省去了散热器

音频性能（PVDD = 16.5V，RSPK = 4Ω）

3 说明

TAS5722L器件是一款高效单声道 D 类音频功率放大

器，其中包含集成的数字输出削波器、多个增益选项和

广泛的电源电压范围。该器件的标称电源电压范围为

4.5V 至 17 VDC。

–

空闲声道噪声 = 45μVRMS (A-Wtd)

总谐波失真 + 噪声 (THD+N) = 0.04%

(1W/1kHz)

–

信噪比 (SNR) = 106dB A-Wtd（参考 THD+N =

1%）

TAS5722L 已针对高瞬态功率能力进行优化，能够利

用小型扬声器的动态功率余量。可持续为 4Ω 的扬声器

提供超过 15W 的功率。

•

I²S 输入：32kHz 至 96kHz

时分复用 (TDM) 音频输入

–

多达 8 条声道（32 位，96kHz）

数字时分复用 (TDM) 接口支持多达 8 个器件共用同一

条总线。

•

I²C 控制，通过 8 个可选 I²C 地址实现

电源

–

功率放大器：4.5V 至 17V

数字 I/O 电压：1.8V

TAS5722L器件采用 4mm x 4mm 32 引脚四方扁平无

引线 (QFN) 封装。

•

稳定性特性

器件信息⁽¹⁾

–

时钟误差检测器、直流偏移和短路保护

过压、欠压和过热保护

器件名称

封装

封装尺寸

TAS5722L

QFN (32)

4mm x 4mm

(1) 要了解所有可用封装，请见文档末尾的可订购产品附录。

简化电路原理图

Control and Status

Digital Audio

System

µP

TAS5722L

I2C

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLOS946

TAS5722L

ZHCSFV9A –MAY 2016–REVISED DECEMBER 2016

www.ti.com.cn

7.3 Feature Description................................................. 17

7.4 Device Functional Modes ....................................... 29

7.5 Register Maps......................................................... 31

Applications and Implementation ...................... 39

8.1 Application Information............................................ 39

8.2 Typical Application .................................................. 39

Power Supply Recommendations...................... 41

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 7

6.6 Timing Requirements................................................ 9

6.7 Typical Characteristics............................................ 12

Detailed Description ............................................ 17

7.1 Overview ................................................................. 17

7.2 Functional Block Diagram ....................................... 17

10 Layout................................................................... 41

10.1 Layout Guidelines ................................................. 41

10.2 Layout Example .................................................... 42

11 器件和文档支持 ..................................................... 43

11.1 商标....................................................................... 43

11.2 静电放电警告......................................................... 43

11.3 Glossary................................................................ 43

12 机械封装和可订购信息 .......................................... 44

12.1 Package Option Addendum .................................. 45

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (May 2016) to Revision A

Page

•

已将产品更改为量产数据。..................................................................................................................................................... 1

TAS5722L

www.ti.com.cn

ZHCSFV9A –MAY 2016–REVISED DECEMBER 2016

5 Pin Configuration and Functions

RSM PACKAGE

32 PINS

(TOP VIEW)

24 OUT_P

23 BST_P

VREF_N

FAULTZ

SDZ

PGND

21 PGND

LRCLK

MCLK

BCLK

SDI

PGND

BST_N

OUT_N

SCL

Pin Functions⁽¹⁾

I/O/P⁽²⁾DESCRIPTION

NAME

ADR1

NO.

I²C address inputs. Each pin can detect a short to DVDD, a short to GND, a 22-kΩ connection to GND

and a 22-kΩ connection to DVDD.

ADR0

AVDD

BCLK

Analog power supply input. Connect directly to PVDD.

TDM Interface serial bit clock.

BST_N

BST_P

DVDD

FAULTZ

Class-D Amplifier negative bootstrap. Connect a capacitor between BST_N and OUT_N.

Class-D Amplifier positive bootstrap. Connect a capacitor between BST_P and OUT_P.

Digital power supply. Connect to 1.8-V supply with external decoupling capacitor.

Open drain active low fault flag. Pull up on PCB with resistor to DVDD.

GND

Ground. Connect to PCB ground plane.

GVDD

LRCLK

MCLK

Class-D amplifier gate drive regulator output. Connect decoupling cap to PCB ground plane.

TDM interface left/right clock.

Device master clock.

(1) Connect exposed thermal pad to PCB ground plane

(2) I = input, O = output, P = power, I/O = bi-directional

TAS5722L

ZHCSFV9A –MAY 2016–REVISED DECEMBER 2016

www.ti.com.cn

Pin Functions⁽¹⁾(continued)

I/O/P⁽²⁾DESCRIPTION

NAME

NO.

PGND

Power ground. Connect to PCB ground plane.

PVDD

Class-D amplifier power supply input. Connect to PVDD supply and decouple externally.

OUT_N

OUT_P

Class-D amplifier negative output.

Class-D amplifier positive output.

SCL

I/O

I²C clock Input. Pull up on PCB with a 2.4-kΩ resistor.

I²C bi-directional data. Pull up on PCB with a 2.4-kΩ resistor.

SDA

SDI

TDM interface data input.

SDZ

Active low shutdown signal. Assert low to hold device inactive.

Common mode reference output. Connect decoupling capacitor to the VREF_N pin.

Negative reference for analog. Connect to VCOM and VREG capacitor negative pins.

Analog regulator output. Connect decoupling capacitor to the VREF_N pin.

VCOM

VREF_N

VREG

TAS5722L

www.ti.com.cn

ZHCSFV9A –MAY 2016–REVISED DECEMBER 2016

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

UNIT

PVDD, AVDD

DVDD

V_CC

Supply voltage⁽²⁾

2.25

Digital inputs referenced to

DVDD supply

V_DVDD

0.5

Digital input voltage

–0.5

T_A

Ambient operating temperature

Storage temperature range

–25

–40

°C

T_stg

125

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.

(2) All voltages are with respect to network ground pin.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC specification JESD22-C101,

all pins⁽²⁾

±750

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

TYP

MAX

UNIT

PVDD

AVDD

Power supply voltage

DVDD Power supply voltage

1.65

1.8

V_DVDD

V_IH(DR)High-level digital input voltage

V_IL(DR)Low-level digital input voltage

R_SPK

T_A

Minimum speaker load

3.2

–25

Operating free-air temperature

Operating junction temperature

°C

T_J

150

TAS5722L

ZHCSFV9A –MAY 2016–REVISED DECEMBER 2016

www.ti.com.cn

6.4 Thermal Information

TAS5722L

RSM (QFN)

32 PINS

37.3

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance⁽³⁾

Junction-to-board thermal resistance⁽⁴⁾

Junction-to-top characterization parameter⁽⁵⁾

Junction-to-board characterization parameter⁽⁶⁾

Junction-to-case (bottom) thermal resistance⁽⁷⁾

R_θJCtop

R_θJB

30.4

7.9

°C/W

ψ_JT

0.4

ψ_JB

7.7

R_θJCbot

2.5

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report (SPRA953).

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Spacer

TAS5722L

www.ti.com.cn

ZHCSFV9A –MAY 2016–REVISED DECEMBER 2016

6.5 Electrical Characteristics

V_PVDD= 16.5 V, V_DVDD= 1.8 V, R_L= 4 Ω + 33 µH, f_PWM= 576 kHz, 22-Hz to 20- kHz Bandwidth, AP AUX-0025 + AES17 Filter

(unless otherwise noted)

PARAMETER

CONDITIONS

MIN

TYP

MAX UNIT

DIGITAL INPUT AND OUTPUT

High-level digital input logic

voltage threshold

V_IH

All digital pins

70%

Low-level digital input logic voltage

threshold

V_IL

30%

Input logic "high" leakage for

digital inputs

I_IH

All digital pins, excluding SDZ

–15

µA

Input logic "low" leakage for digital

inputs

I_IL

All digital pins, excluding SDZ

Input logic "high" leakage for SDZ

inputs

I_IH(SDZ)

I_IL(SDZ)

SDZ

Input logic "low" leakage for SDZ

inputs

SDZ

–1

Output logic "low" for FAULTZ

open drain Output

10%

V_DVDD

V_OL

C_IN

I_OL= –2 mA

Input capacitance for digital inputs All digital pins

MASTER CLOCK

D_MCLKAllowable MCLK duty cycle

45%

50%

55%

MCLK input frequency

MHz

Supported single-speed MCLK

frequencies

values: 64, 128, 256 and 512

values: 64, 128 and 256

2.8

5.6

24.6

f_MCLK

Supported double-speed MCLK

frequencies

MHz

SERIAL AUDIO PORT

D_BCLKAllowable BCLK duty cycle

45%

50%

55%

BCLK input frequency

MHz

Supported single-speed BCLK

frequencies

values: 64, 96, 128, 192 and 256

values: 44.1 and 48

2.8

5.6

12.3

24.6

f_BCLK

Supported double-speed BCLK

frequencies

MHz

kHz

Supported single-speed input

sample rates

44.1

88.2

f_S

Supported double-speed input

sample rates

values: 88.2 and 96

I²C CONTROL PORT

Allowable load capacitance for

C_L(I2C)

400

each I²C Line

SCL frequency

f_SCL

No wait states

kHz

PROTECTION

Over-temperature error (OTE)

threshold

OTE_THRESH

OTE_HYST

150

°C

Over-temperature error (OTE)

hysteresis

OCE_THRESH

DCE_THRESH

overcurrent error (OCE) threshold V_PVDD= 16.5 V, T_A= 25°C

DC error (DCE) threshold V_PVDD= 16.5V, TA = 25°C

2.6

TAS5722L

ZHCSFV9A –MAY 2016–REVISED DECEMBER 2016

www.ti.com.cn

Electrical Characteristics (接下页)

V_PVDD= 16.5 V, V_DVDD= 1.8 V, R_L= 4 Ω + 33 µH, f_PWM= 576 kHz, 22-Hz to 20- kHz Bandwidth, AP AUX-0025 + AES17 Filter

(unless otherwise noted)

PARAMETER

CONDITIONS

MIN

TYP

MAX UNIT

AMPLIFIER PERFORMANCE

R_L= 8 Ω+33 µH, 1% THD+N, V_PVDD= 12 V,

f_IN= 1 kHz

8.2

15.25

14.25

R_L= 8 Ω+33 µH, 1% THD+N, V_PVDD= 16.5 V,

f_IN= 1 kHz

P_OUT

Continuous average power

R_L= 4 Ω+33 µH, 1% THD+N, V_PVDD= 12 V,

f_IN= 1 kHz

R_L= 4 Ω+33 µH, 1% THD+N, V_PVDD= 16.5 V,

f_IN= 1 kHz

R_L= 8 Ω+33 µH, V_PVDD= 12 V, P_OUT= 4.25

W, 20 Hz ≤ f_IN≤ 20 kHz

0.05%

0.06%

90%

R_L= 8 Ω+33 µH, V_PVDD= 16.5 V, P_OUT= 4.25

W, 20 Hz ≤ f_IN≤ 20 kHz

Total harmonic distortion plus

noise

THD+N

R_L= 4 Ω+33 µH, V_PVDD= 12 V, P_OUT= 8.25

W, 20 Hz ≤ f_IN≤ 20 kHz

R_L= 4 Ω+33 µH, V_PVDD= 16.5 V, P_OUT= 8.25

W, 20 Hz ≤ f_IN≤ 20 kHz

R_L= 8 Ω+33 µH, V_PVDD= 16.5 V, P_OUT= 10

P_EFF

Power efficiency

R_L= 4 Ω+33 µH, V_PVDD= 16.5 V, P_OUT= 14

87%

A-Weighted, Gain = 20.7dBV, R_L= 8 Ω+33

µH

V_N

Integrated noise floor voltage

µVrms

Into and out of HW reset, into and out of SW

shutdown, when SAIF clocks are applied or

removed and during power rail cycling.

Measured using Maxim click-pop

KCP

Click-pop performance

-60

0.2

measurement method.

Output phase shift between multiple devices

from 20 Hz to 20 kHz. Across all sample

frequencies and SAIF operating modes.

φ _CC

Channel-to-channel phase shift

deg

AC, 5.5 V ≤ V_PVDD≤ 16.5 V, DVDD = 1.8

V+200 mV_P-P, f_RIPPLEfrom 20 Hz to 20 kHz

AC, V_PVDD= 16.5 V+200 mV_P-P, f_RIPPLEfrom

20 Hz to 5 kHz

PSRR

Power supply rejection ratio

Amplifier analog gain⁽¹⁾

AC, V_PVDD= 16.5 V+100 mV_P-P, f_RIPPLEfrom

5 kHz to 20 kHz

AV₀₀

ANALOG_GAIN[1:0] register bits set to "00"

ANALOG_GAIN[1:0] register bits set to "01"

ANALOG_GAIN[1:0] register bits set to "10"

ANALOG_GAIN[1:0] register bits set to "11"

19.2

20.7

23.5

26.3

dBV

AV₀₁

AV₁₀

AV₁₁

AV_ERROR

V_OS

Amplifier analog gain error

DC output offset voltage

Frequency response

±0.15

Measured between OUTP and OUTN

1.5

A_RIPPLE

Maximum deviation above or below passband

gain.

±0.15

f_LP

-3 dB Output Cutoff Frequency

Power stage FET on-resistance

0.47×f_S

120

R_DS(on)FET

T_A= 25°C

mΩ

(1) When PVDD is less than 5.5 V, the voltage regulator that operates the analog circuitry does not have enough headroom to maintain the

nominal 5.4-V internal voltage. The lack of headroom causes a direct reduction in gain (approximately –0.8 dB at 5 V and –1.74 dB at

4.5 V), but the device functions properly down to V_PVDD= 4.5 V. For operation below 5.5V, the VREG_LVL bit (register 0x14, bit 2) can

be set high, which reduces the internal voltage regulator output voltage to prevent variation in gain. When the bit is set high, all gain

settings are reduced by 3dB.

TAS5722L

www.ti.com.cn

ZHCSFV9A –MAY 2016–REVISED DECEMBER 2016

Electrical Characteristics (接下页)

V_PVDD= 16.5 V, V_DVDD= 1.8 V, R_L= 4 Ω + 33 µH, f_PWM= 576 kHz, 22-Hz to 20- kHz Bandwidth, AP AUX-0025 + AES17 Filter

(unless otherwise noted)

PARAMETER

CONDITIONS

MIN

TYP

150

MAX UNIT

Power stage total on-resistance

(FET+bond+package)

R_DS(on)TOT

T_A= 25°C

mΩ

I_P-P

Peak output current

f_PWM

PWM switching frequency

values: 6, 8, 10, 12, 14, 16, 20 and 24

MHz

6.6 Timing Requirements

MIN

NOM

MAX UNIT

From deassertion of SDZ (both pin and I²C

begins switching.

t_ACTIVE

Shutdown to Active Time

From the deassertion of SLEEP until the

Class-D amplifier starts switching.

t_WAKE

t_SLEEP

t_MUTE

t_PLAY

Wake Time

t_vrmp+1

t_vrmp

From the assertion of SLEEP until the

Class-D amplifier stops switching.

Sleep Time

From the assertion of MUTE until the

volume has ramped to the minimum.

Play to Mute Time

Un-Mute to Play Time

From the deassertion of MUTE until the

volume has returned to its current setting.

t_vrmp

From the assertion of SDZ (pin or I²C

switching.

t_SD

Active to Shutdown Time

t_vrmp+1

TAS5722L

ZHCSFV9A –MAY 2016–REVISED DECEMBER 2016

www.ti.com.cn

Timing Requirements (接下页)

MIN

NOM

MAX UNIT

SERIAL AUDIO PORT

Time High/Low, BCLK, LRCLK,

SDI inputs

t_{H_L}

Input t_RISE≤ 1 ns, input t_FALL≤ 1 ns

Input t_RISE≤ 4 ns, input t_FALL≤ 4ns

Input t_RISE≤ 8 ns, input t_FALL≤ 8ns

Setup and hold time. LRCLK, SDI

t_SU/ t_HLD

input to BCLK edge.

Rise-time BCLK, LRCLK, SDI

inputs

t_RISE

Fall-time BCLK, LRCLK, SDI

inputs

t_FALL

I²C CONTROL PORT

Bus free time between start and

stop conditions

t_BUF

1.3

µs

t_H1(I2C)

t_H2(I2C)

Hold Time, SCL to SDA

µs

Hold Time, start condition to SCL

0.6

I2C Startup Time after DVDD

Power On Reset

t_START(I2C)

t_R(I2C)

Rise Time, SCL and SDA

Fall Time, SCL and SDA

Setup, SDA to SCL

300

µs

t_F(I2C)

t_SU1(I2C)

t_SU2(I2C)

t_SU3(I2C)

100

0.6

Setup, SCL to start condition

Setup, SCL to stop condition

Required pulse duration, SCL

"HIGH"

t_W(H)

0.6

1.3

µs

Required pulse duration, SCL

"LOW"

t_W(L)

PROTECTION

DC detect error

650

1.3

t_FAULTZ

Amplifier fault time-out period

OTE or OCE fault

BCLK

LRCLK

SDIN

图 1. SAIF Timing

TAS5722L

www.ti.com.cn

ZHCSFV9A –MAY 2016–REVISED DECEMBER 2016

t_w(H)

t_w(L)

t_r

t_f

SCL

t_su1

t_h1

SDA

T0027-01

图 2. SCL and SDA Timing

SCL

t_(buf)

t_h2

t_su2

t_su3

SDA

Start

Condition

Stop

Condition

T0028-01

图 3. Start and Stop Conditions Timing

t_MUTE

t_PLAY

t_SD

SLEEP

ACTIVE

VRMP

WAKE

SDZ

SLEEP

MUTE

VOLUME

OUTx

图 4. Mode Timing

TAS5722L

ZHCSFV9A –MAY 2016–REVISED DECEMBER 2016

www.ti.com.cn

6.7 Typical Characteristics

T_A= 25ºC, V_DVDD= 1.8 V, f_IN= 1 kHz, f_PWM768 kHz, f_s= 48 kHz, Gain = 20.7 dBV, SDZ = 1, Measured using TAS5722LEVM

with an Audio Precision SYS-2722 and AUX-0025 filter with 22-Hz-to-20- kHz un-weighted bandwidth using the 20- kHz pre-

analyzer filter + 20- kHz brick-wall filter (unless otherwise specified). 33 µH inductors were added in series with 4 Ω loads and

68 µH inductors were placed in series with 8 Ω loads due to the ferrite bead filters.

4 W Load

8 W Load

4 W Load

8 W Load

0.1

0.01

0.001

100

10k 20k

Supply Voltage (V)

Frequency (Hz)

D001

D002

PV_DD= 5 V

Gain = 19.2 dBV

f_PWM= 384 kHz

图 5. Output Power vs Supply Voltage

图 6. THD+N vs Frequency

4 W Load

8 W Load

4 W Load

8 W Load

0.1

0.01

0.001

100

10k 20k

100

10k 20k

Frequency (Hz)

D003

D004

PV_DD= 5 V

Gain = 19.2 dBV

f_PWM= 768 kHz

PV_DD= 12 V

Gain = 19.2 dBV

f_PWM= 384 kHz

图 7. THD+N vs Frequency

图 8. THD+N vs Frequency

4 W Load

8 W Load

P_OUT= 1 W

P_OUT= 8.25 W

P_OUT= 15 W

0.1

0.01

0.001

100

10k 20k

100

10k 20k

Frequency (Hz)

D005

D006

PV_DD= 12 V

Gain = 19.2 dBV

f_PWM= 768 kHz

PV_DD= 16.5 V

Gain = 23.5 dBV

f_PWM= 384 kHz

RLoad = 4 Ω

图 9. THD+N vs Frequency

图 10. THD+N vs Frequency

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ZHCSFV9A –MAY 2016–REVISED DECEMBER 2016

Typical Characteristics (接下页)

T_A= 25ºC, V_DVDD= 1.8 V, f_IN= 1 kHz, f_PWM768 kHz, f_s= 48 kHz, Gain = 20.7 dBV, SDZ = 1, Measured using TAS5722LEVM

with an Audio Precision SYS-2722 and AUX-0025 filter with 22-Hz-to-20- kHz un-weighted bandwidth using the 20- kHz pre-

analyzer filter + 20- kHz brick-wall filter (unless otherwise specified). 33 µH inductors were added in series with 4 Ω loads and

68 µH inductors were placed in series with 8 Ω loads due to the ferrite bead filters.

P_OUT= 1 W

P_OUT= 8.25 W

P_OUT= 15 W

P_OUT= 1 W

P_OUT= 4 W

P_OUT= 8.25 W

0.1

0.01

0.001

100

10k 20k

100

10k 20k

Frequency (Hz)

D007

D008

PV_DD= 16.5 V

Gain = 23.5 dBV

RLoad = 4 Ω

PV_DD= 16.5 V

Gain = 23.5 dBV

f_PWM= 384 kHz

RLoad = 8 Ω

图 11. THD+N vs Frequency

图 12. THD+N vs Frequency

P_OUT= 1 W

f_PWM= 384 kHz

P_OUT= 4 W

P_OUT= 8.25 W

f_PWM= 480 kHz

f_PWM= 576 kHz

f_PWM= 672 kHz

f_PWM= 768 kHz

0.1

0.01

0.001

100

10k 20k

100

10k 20k

Frequency (Hz)

D009

D010

PV_DD= 16.5 V

Gain = 23.5 dBV

RLoad = 8 Ω

PV_DD= 16.5 V

RLoad = 4 Ω

P_OUT= 8.25 W

图 13. THD+N vs Frequency

图 14. THD+N vs Frequency

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Typical Characteristics (接下页)

T_A= 25ºC, V_DVDD= 1.8 V, f_IN= 1 kHz, f_PWM768 kHz, f_s= 48 kHz, Gain = 20.7 dBV, SDZ = 1, Measured using TAS5722LEVM

with an Audio Precision SYS-2722 and AUX-0025 filter with 22-Hz-to-20- kHz un-weighted bandwidth using the 20- kHz pre-

analyzer filter + 20- kHz brick-wall filter (unless otherwise specified). 33 µH inductors were added in series with 4 Ω loads and

68 µH inductors were placed in series with 8 Ω loads due to the ferrite bead filters.

f_PWM= 384 kHz

f_PWM= 480 kHz

f_PWM= 576 kHz

f_PWM= 672 kHz

f_PWM= 768 kHz

PV_DD= 5 V

PV_DD= 12 V

PV_DD= 16.5 V

0.1

0.01

0.001

100

10k 20k

10m

100m

Frequency (Hz)

Output Power (W)

D011

D012

PV_DD= 16.5 V

Gain = 20.7 dBV

P_OUT= 4.25 W

RLoad = 4 Ω

Gain = 23.5 dBV

f_PWM= 768 kHz

RLoad = 8 Ω

图 16. THD+N vs Output Power

图 15. THD+N vs Frequency

100

PV_DD= 5 V

PV_DD= 12 V

PV_DD= 16.5 V

0.1

0.01

Gain = 19.2 dB

Gain = 20.7 dB

Gain = 23.5 dB

Gain = 26.3 dB

0.001

10m

100m

Output Power (W)

Supply Voltage (V)

D013

D014

RLoad = 8 Ω

Gain = 23.5 dBV

f_PWM= 768 kHz

RLoad = 4 Ω

A-weighting Filter

f_PWM= 384 kHz

图 17. Idle Channel Noise vs Supply Voltage

图 18. Idle Channel Noise vs Supply Voltage

100

Gain = 19.2 dB

Gain = 20.7 dB

Gain = 23.5 dB

Gain = 26.3 dB

PV_DD= 5 V

PV_DD= 12 V

PV_DD= 16.5 V

Supply Voltage (V)

Output Power (W)

D015

D016

RLoad = 4 Ω

A-weighting Filter

f_PWM= 768 kHz

RLoad = 4 Ω

Gain = 23.5 dBV

f_PWM= 384 kHz

图 19. Efficiency vs Output Power

图 20. Efficiency vs Output Power

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Typical Characteristics (接下页)

T_A= 25ºC, V_DVDD= 1.8 V, f_IN= 1 kHz, f_PWM768 kHz, f_s= 48 kHz, Gain = 20.7 dBV, SDZ = 1, Measured using TAS5722LEVM

with an Audio Precision SYS-2722 and AUX-0025 filter with 22-Hz-to-20- kHz un-weighted bandwidth using the 20- kHz pre-

analyzer filter + 20- kHz brick-wall filter (unless otherwise specified). 33 µH inductors were added in series with 4 Ω loads and

68 µH inductors were placed in series with 8 Ω loads due to the ferrite bead filters.

100

PV_DD= 5 V

PV_DD= 12 V

PV_DD= 16.5 V

PV_DD= 5 V

PV_DD= 12 V

PV_DD= 16.5 V

Output Power (W)

D017

D018

RLoad = 4 Ω

Gain = 23.5 dBV

f_PWM= 768 kHz

RLoad = 8 Ω

Gain = 23.5 dBV

f_PWM= 384 kHz

图 21. Efficiency vs Output Power

图 22. Efficiency vs Output Power

100

-20

PV_DD= 5 V

PV_DD= 12 V

PV_DD= 16.5 V

-40

-60

-80

PV_DD= 5 V

PV_DD= 12 V

PV_DD= 16.5 V

-100

100

10k 20k

Output Power (W)

Frequency

D019

D020

RLoad = 8 Ω

Gain = 23.5 dBV

f_PWM= 768 kHz

RLoad = 4 Ω

Gain = 20.7 dBV

f_PWM= 768 kHz

图 23. PV<Subscript>DD</Subscript> PSRR vs Frequency

图 24. DVDD PSRR vs Frequency

PV_DD= 5 V

PV_DD= 12 V

PV_DD= 16.5 V

-20

-40

-60

-80

F_PWM= 384 kHz

F_PWM= 768 kHz

-100

100

10k 20k

Frequency

Supply Voltage (V)

D021

D022

RLoad = 4 Ω

Gain = 20.7 dBV

f_PWM= 768 kHz

RLoad = 4 Ω

Gain = 20.7 dBV

图 25. Idle Current vs Supply Voltage

图 26. Shutdown Current vs Supply Voltage

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Typical Characteristics (接下页)

T_A= 25ºC, V_DVDD= 1.8 V, f_IN= 1 kHz, f_PWM768 kHz, f_s= 48 kHz, Gain = 20.7 dBV, SDZ = 1, Measured using TAS5722LEVM

with an Audio Precision SYS-2722 and AUX-0025 filter with 22-Hz-to-20- kHz un-weighted bandwidth using the 20- kHz pre-

analyzer filter + 20- kHz brick-wall filter (unless otherwise specified). 33 µH inductors were added in series with 4 Ω loads and

68 µH inductors were placed in series with 8 Ω loads due to the ferrite bead filters.

Supply Voltage (V)

D023

图 27. PVDD Shutdown Current vs Supply Voltage

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7 Detailed Description

7.1 Overview

The TAS5722L device is a high-efficiency mono Class-D audio power amplifier optimized for high-transient

power capability to utilize the dynamic power headroom of small loudspeakers. The TAS5722L device is capable

of delivering more than 14 W continuously into a 4-Ω speaker.

7.2 Functional Block Diagram

1.8V

4.5-17V

BST_P

OUT_P

Pop/Click

Over Current

Over Temp

Protection

SDZ

ADR0

ADR1

SCL

Closed

Loop

Class-D

Amplifier

SDA

OUT_N

BST_N

System

Interface

FAULTZ

SDI

DAC

LRCLK

BCLK

MCLK

VREGs

7.3 Feature Description

7.3.1 Adjustable I²C Address

The TAS5722L device has two address pins, which allow up to 8 I²C addressable devices to share a common

TDM bus. 表 1 lists each I²C Device ID setting.

注

The I²C Device ID is the 7 most significant bits of the 8-bit address transaction on the bus

(with the read/write bit being the least significant bit). For example, a Device ID of 0x6C

would be read as 0xD8 when the read/write bit is 0.

表 1. I²C Device Identifier (ID) Generation

DEFAULT TDM

ADR1

ADR0

I2C_DEV_ID

SLOT

Short to GND

22-kΩ to GND

22-kΩ to DVDD

Short to DVDD

0x6C

0x6D

0x6E

0x6F

Short to GND

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表 1. I²C Device Identifier (ID) Generation (接下页)

DEFAULT TDM

SLOT

ADR1

ADR0

I2C_DEV_ID

Short to GND

22-kΩ to GND

22-kΩ to DVDD

Short to DVDD

0x70

0x71

0x72

0x73

22-kΩ to GND

Use a 22-kΩ resistor with a 5% (or better) tolerance as a pull-up or pull-down resistor. By default, the device

uses the TDM time slot equal to its offset from the base I²C Device ID (see 表 1). The TDM slot can also be

manually configured by setting the TDM_CFG_SRC bit high (bit 6, reg 0x02) and programming the

TDM_SLOT_SELECT[3:0] bits to the desired slot (bits 0-3, reg 0x03).

For 2-channel, I²S operation, TDM slot 0 and 1 correspond to the right and left channels respectively. For left and

right justified formats, TDM slot 0 and 1 correspond to left and right channels respectively.

7.3.2 I²C Interface

The TAS5722L device has a bidirectional I²C interface that is compatible with the Inter-Integrated Circuit (I²C)

bus protocol and supports both 100 kHz and 400 kHz data transfer rates. The slave-only device does not support

a multi-master bus environment or wait-state insertion. The control interface is used to program the registers of

the device and to read device status.

The I²C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a

system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte

(8-bit) format, with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is

acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master

device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.

The bus uses transitions on the data pin (SDA) while the clock (SCL) is "HIGH" to indicate start and stop

conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal

data-bit transitions must occur within the low time of the clock period. These conditions are shown in 图 28. The

master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another

device and then waits for an acknowledge condition. The TAS5722L device holds SDA "LOW" during the

acknowledge clock period to indicate an acknowledgment. When the hold occurs, the master transmits the next

byte of the sequence. All compatible devices share the same signals via a bidirectional bus using a wired-AND

connection. An external pull-up resistor must be used for the SDA and SCL signals to set the "HIGH" level for the

bus.

8-Bit Register Data For

Address (N)

8-Bit Register Data For

Address (N)

8-Bit Register Address (N)

7-Bit Slave Address

SDA

SCL

Start

Stop

T0035-01

图 28. Typical I²C Timing Sequence

The number of bytes that can be transmitted between start and stop conditions is unlimited. When the last word

transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is shown in

图 28.

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7.3.2.1 Writing to the I²C Interface

As shown 图 29, a single-byte data-write transfer begins with the master device transmitting a start condition

followed by the I²C bit and the read/write bit. The read/write bit determines the direction of the data transfer. For

a data-write transfer, the read/write bit is a 0. After receiving the correct I²C bit and the read/write bit, the

TAS5722L device responds with an acknowledge bit. Next, the master transmits the address byte corresponding

to the TAS5722L device register being accessed. After receiving the address byte, the TAS5722L device again

responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory

address being accessed. After receiving the data byte, the TAS5722L device again responds with an

acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data-write

transfer.

Start

Condition

Acknowledge

R/W

A6 A5 A4 A3 A2 A1 A0

ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

I²C Device Address and

Read/Write Bit

Subaddress

Data Byte

Stop

Condition

T0036-01

图 29. Single Byte Write Transfer Timing

A multi-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are

transmitted as shown in 图 30. After receiving each data byte, the TAS5722L device responds with an

acknowledge bit. Sequential data bytes are written to sequential addresses.

Start

Condition

Acknowledge

D0 ACK D7

Acknowledge

D0 ACK D7

Acknowledge

D0 ACK

A6 A5

A1 A0 R/W ACK A7 A6 A5 A4 A3

A1 A0 ACK D7

I²C Device Address and

Read/Write Bit

Subaddress

First Data Byte

Last Data Byte

Stop

Condition

Other Data Bytes

T0036-02

图 30. Multi-Byte Write Transfer Timing

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7.3.2.2 Reading from the I²C Interface

As shown in 图 30, a data-read transfer begins with the master device transmitting a start condition, followed by

the I²device address and the read/write bit. For the data read transfer, both a write followed by a read are

actually done. Initially, a write is done to transfer the address byte of the internal register to be read. As a result,

the read/write bit becomes a 0. After receiving the TAS5722L device address and the read/write bit, TAS5722L

device responds with an acknowledge bit. In addition, after sending the internal memory address byte or bytes,

the master device transmits another start condition followed by the TAS5722L device address and the read/write

bit again. Then the read/write bit becomes a 1, indicating a read transfer. After receiving the address and the

read/write bit, the TAS5722L device again responds with an acknowledge bit. Next, the TAS5722L device

transmits the data byte from the register being read. After receiving the data byte, the master device transmits a

not-acknowledge followed by a stop condition to complete the data-read transfer.

Repeat Start

Condition

Not

Acknowledge

Start

Condition

Acknowledge

A0 ACK

Acknowledge

A6 A5

A1 A0 R/W ACK A7 A6 A5 A4

A6 A5

A1 A0 R/W ACK D7 D6

D1 D0 ACK

I²C Device Address and

Read/Write Bit

Subaddress

I²C Device Address and

Read/Write Bit

Data Byte

Stop

Condition

T0036-03

图 31. Single Byte Read Transfer Timing

A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes

are transmitted by the TAS5722L to the master device as shown 图 32. Except for the last data byte, the master

device responds with an acknowledge bit after receiving each data byte.

Repeat Start

Condition

Not

Acknowledge

Start

Condition

Acknowledge

D0 ACK D7

A0 R/W ACK A7 A6 A5

A0 ACK

A0 R/W ACK D7

D0 ACK D7

D0 ACK

I²C Device Address and

Read/Write Bit

Subaddress

I²C Device Address and First Data Byte

Read/Write Bit

Other Data Bytes

Last Data Byte

Stop

Condition

T0036-04

图 32. Multi-Byte Read Transfer Timing

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7.3.3 Serial Audio Interface (SAIF)

The TAS5722L device SAIF supports a variety of standard stereo serial audio formats including I²S, Left Justified

and Right Justified. It also supports a time division multiplexed (TDM) format that is capable of transporting up to

8 channels of audio data on a single bus. LRCLK and SDIN are sampled on the rising edge of BCLK.

For the stereo formats (I²S, Left Justified and Right Justified), the TAS5722L device supports BCLK to LRCLK

ratios of 32, 48 and 64. If the BCLK to LRCLK ratio is 64, MCLK can be derived from BCLK internally. The

MCLK_PIN_CFG bit (register 0x13, bit 1) controls the source of MCLK and by default derives MCLK from an

internal version of BCLK. In this case connect the MCLK pin to a valid logic low value.

If the BCLK to LRCLK ratio is 32 or 48, MCLK must be externally driven. The valid MCLK to LRCLK ratios are

64, 128, 256 and 512 as long as the frequency of MCLK is 37 MHz or less. If the BCLK to LRCLK ratio is 64, it is

also acceptable to connect BCLK to MCLK and set the MCLK_PIN_CFG bit high.

For TDM operation, the TAS5722L device supports 4 and 8 times slots at both single speed (44.1 kHz or 48 kHz)

and double speed (88.2/96 kHz) sample rates. 表 2 lists the supported TDM frame configurations. For 16 and 32-

bits per TDM slot, MCLK can be connected to BCLK internally by leaving the MCLK_PIN_CFG bit (register 0x13,

bit 1) to its default value of 0. For 24-bit time slot operation, MCLK must be externally driven with a valid ratio of

64, 128, 256 or 512 as long as MCLK is less than 37 MHz.

表 2. TDM Frame Configurations

BITS

PER

TDM

SAMPLE

RATE

(kHz)

TDM

SLOTS

SUPPORTED

MCLK = BCLK

TDM_SLOT_16B

SLOT

Yes

44.1/48

88.2/96

Yes

If 16-bit time slots are utilized, set the TDM_SLOT_16B register bit (register 0x13, bit 2) to a 1. The SAIF auto

detects 24-bit vs. 32-bit time slot widths if TDM_SLOT_16B is set to a 0.

The TAS5722L device selects the channel for playback based on either its I²C base address offset or based on a

dedicated time slot selection register. See the Adjustable I²C Address section for more information.

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7.3.3.1 Stereo I²S Format Timing

illustrates the timing of the stereo I²S format with 64 BCLK per LRCLK. Two’s complement data is transmitted

MSB to LSB with the left channel word beginning one BCLK after the falling edge of LRCLK and the right

channel beginning one BCLK after the rising edge of LRCLK. Since data is MSB aligned to the beginning of word

transmission, data precision does not need to be configured. Set the SAIF_FORMAT[2:0] register bits to I²S

(register 0x02, bits 2:0 = 3’b100).

BCLK

SDI

A. Data presented in two's-complement form with most significant bit (MSB) first.

图 33. I²S 64-f_SFormat

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7.3.3.2 Stereo Left-Justified Format Timing

The stereo left justified format is very similar to the I²S format timing, except the data word begins transmission

at the same cycle that LRCLK toggles (when it is shifted by one bit from I²S). The phase of LRCLK is also

opposite of I²S. The left channel begins transmission when LRCLK transitions from low to high and the right

channel begins transmission when LRCLK transitions from high-to-low. Set the SAIF_FORMAT[2:0] register bits

to left-justified (register 0x02, bits 2:0 = 3’b101).The timing is illustrated in .

LRCLK

BCLK

SDI

A. Data presented in two's-complement form with most significant bit (MSB) first.

图 34. Left-Justified 64-f_SFormat

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7.3.3.3 Stereo Right-Justified Format Timing

The stereo right justified format aligns the LSB of left channel data to the high to low transition of LRCLK and the

LSB of the right channel data to the low to high transition of LRCLK. To insure data is received correctly, the

SAIF must be configured for the proper data precision. The TAS5722L supports 16, 18, 20 and 24-bit data

precision in right justified format. Set the SAIF_FORMAT[2:0] register bits (register 0x02, bits 2:0) to the

appropriate right-justified setting based on bit precision (value = 3’b000 for 24-bit, 3’b001 for 20-bit, 3’b010 for

18-bit and 3’b011 for 16-bit). The timing is illustrated in .

LRCLK

BCLK

SDI

图 35. Right-Justified 64-f_SFormat

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7.3.3.4 TDM Format Timing

A TDM frame begins with the low to high transition of LRCLK. As long as LRCLK is high for at least one BCLK

period and low for one BCLK period, duty cycle is irrelevant. The SAIF automatically detects the number of time

slots as long as valid BCLK to LRCLK ratios are utilized (see SAIF introduction above).

For I²S aligned TDM operation (when time slot 0 begins, one clock cycle after the low to high transition of

LRCLK), set SAIF_FORMAT[2:0] register bits to I²S (register 0x02, bits 2:0 = 3’b100). Data is MSB aligned within

the 32-bit time slots, so data precision does not need to be configured. The TDM format timing is illustrated in .

BCLK

LRCLK

Slot N

LSB

Slot 0

MSB

Slot 0

MSB-1

Slot 0

LSB

Slot 1

MSB

Slot 1

MSB-1

Slot 1

MSB-2

Slot N-1

LSB

Slot N

MSB

Slot N

MSB-1

Slot N

MSB-2

Slot N

LSB+1

SDI

图 36. TDM I²S Format

For left-justified TDM operation (when time slot 0 begins the cycle LRCLK transitions from low to high), set

SAIF_FORMAT[2:0] register bits to left-justified(register 0x02, bits 2:0 = 3’b101). As with I²S, data is MSB

aligned. The timing is illustrated in .

BCLK

LRCLK

Slot 0

MSB

Slot 0

MSB-1

Slot 0

MSB-2

Slot 0

LSB

Slot 1

MSB

Slot 1

MSB-1

Slot 1

MSB-2

Slot N-1

LSB

Slot N

MSB

Slot N

MSB-1

Slot N

MSB-2

Slot N

LSB

SDI

图 37. TDM Left- and Right-Justified Format

For right-justified TDM operation (when time slot 0 begins the cycle LRCLK transitions from low to high), data is

LSB aligned to the 32-bit time slot. As with stereo right-justified formats, the TAS5722L must have the data

precision configured. Set the SAIF_FORMAT[2:0] register bits (register 0x02, bits 2:0) to the appropriate right-

justified setting based on bit precision (value = 3’b000 for 24-bit, 3’b001 for 20-bit, 3’b010 for 18-bit and 3’b011

for 16-bit). The timing shown in is the same as left-justified TDM, with the data LSB aligned.

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7.3.4 Audio Signal Path

illustrates the audio signal flow from the TDM SAIF to the speaker.

LRCLK

BCLK

(1) See 表 3 for frequency options.

图 38. Audio Signal Path

7.3.4.1 High-Pass Filter (HPF)

Excessive DC in audio content can damage loudspeakers, so the amplifier employs a DC detect circuit that shuts

down the power stage and issues a latching fault if this condition occurs. A high-pass filter is provided in the

TAS5722L device to remove DC from incoming audio data to prevent this from occurring. 表 3 shows the high-

pass, –3 dB corner frequencies for each sample rate. The filter can be bypassed by writing a 1 into bit 7 of

Control 3 register (B[5:7], register 0x13).

表 3. High-Pass Filter –3 dB Corner Frequencies by Sample Rate

-3dB CORNER FREQUENCY (Hz) vs. HPF_CORNER [2:0]

SAMPLE RATE

(kHz)

000

3.675

001

7.35

010

14.7

011

29.4

100

58.8

101

117.6

128

110

235.2

256

111

470.4

512

44.1

88.2

7.35

14.7

29.4

58.8

117.6

128

235.2

256

470.4

512

940.8

1024

7.3.4.2 Amplifier Analog Gain and Digital Volume Control

The gain from TDM SAIF to speaker is controlled by setting the amplifier’s analog gain and digital volume

control. Amplifier analog gain settings are presented as the output level in dBV (dB relative to 1 Vrms) with a full

scale serial audio input (0 dBFS) and the digital volume control set to 0 dB. It should be noted that these levels

may not be achievable because of analog clipping in the amplifier, so they should be used to convey gain only.

表 4 outlines each gain setting expressed in dBV and V_PK

表 4. Amplifier Gain Settings

FULL SCALE OUTPUT

ANALOG_GAIN [1:0]

SETTING

dBV

V_PEAK(V)

12.9

19.2

20.7

23.5

26.3

15.3

21.2

29.2

公式 1 calculates the amplifiers output voltage.

= Input + A

+ A

dBV

AMP

dvc

where

•

V_AMPis the amplifier output voltage in dBV

Input is the digital input amplitude in dB with respect to 0 dBFS

A_dvcis the digital volume control setting, –100 dB to 24dB in 0.25-dB steps

A_AMPis the amplifier analog gain setting (19.2, 20.7, 23.5, or 26.3) in dBV

(1)

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Clipping in the digital domain occurs if the input level (in dB relative to 0 dBFS) plus the digital volume control

setting (in dB) are greater than 0 dB. The signal path has approximately 0.5 dB of headroom, but TI does not

recommend utilizing it.

The digital volume control (DVC) can be adjusted from –100 dB to 24 dB in 0.25-dB steps. 公式 2 illustrates how

to set the 9-bit volume control bits. The top 8 MSBs of the DVCvalue are stored in Volume Control register

(register 0x04) and the LSB is stored in the Digital Control 3 register (register 0x13, bit 0).

dvc

DVC

= 0x19E +

value

0.25

(2)

For example, digital volume settings of 0 dB, 24 dB and –100 dB map to 0x19E, 0x1FE and 0x0E respectively.

Values below 0x0E are equivalent to mute (the amplifier continues to switch with no audio). When a change in

digital volume control occurs, the device ramps the volume to the new setting in 0.25 dB steps either every

LRCLK or every 8 LRCLK depending on the value of the VOL_RAMP_RATE bit (bit 6, reg 0x03).

The Class-D amplifier uses a closed-loop architecture, so the gain does not depend on the supply input (V_PVDD).

The approximate threshold for the onset of analog clipping is calculated in 公式 3.

= V

PVDD

PK max,preclip

(

)

ç 2´R

+ R

+ R ÷

interconnect

DS on

( )

where

•

V_{PK(max,preclip)}is the maximum peak unclipped output voltage in V

V_PVDDis the power supply voltage

R_Lis the speaker load in Ω

R_interconnectis the additional resistance in the PCB (such as cabling and filters) in Ω

R_DS(on)is the power stage total on resistance (FET+bonding+packaging) in Ω

(3)

The effective on-resistance for the device (including FETs, bonding and packaging leads) is approximately 150

mΩ at room temperature and increases by approximately 1.6 times over +100°C rise in temperature.表 5 shows

approximate maximum unclipped peak output voltages at room temperature (excluding interconnect resistances).

表 5. Approximate Maximum Unclipped Peak Output

Voltage at Room Temperature

MAXIMUM UNCLIPPED

PEAK VOLTAGE

V_PK(V)

SUPPLY VOLTAGE

V_PVDD(V)

R_L= 4 Ω

R_L= 8 Ω

11.57

11.16

15.81

16.39

7.3.4.3 Digital Clipper

The digital clipper hard limits the maximum DAC sample value, which provides a simple hardware mechanism to

control the largest signal applied to the speaker. Because the block resides in the digital domain, the actual

maximum output voltage also depends on the amplifier gain setting and the supply voltage (V_PVDD) limited

amplifier voltage swing (For example, analog clipping may occur before digital clipping).

The maximum amplifier output voltage (excluding limitation due to swing) is calculated in 公式 4.

DC_level

V_{AMP max,dc}= 20´log_{10 ç}

+ 0.5 + A_AMP

(

)

0xFFFFF

where

•

V_AMP(max,dc)is the amplifier maximum output voltage in dBV

DC_levelis the digital clipper level

A_AMPis the amplifier analog gain setting (19.2, 20.7, 23.5, or 26.3) in dBV

(4)

Configure the digital clipper by writing the 20-bit DC_levelto registers 0x01, 0x10 and 0x11. Set the DC_levelto

0xFFFFF effectively bypasses the digital clipper.

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7.3.4.4 Class-D Amplifier Settings

The PWM switching rate of the Class-D amplifier is a phase locked multiple of the input audio sample rate. 表 6

lists the PWM switching rate settings as programmed in bit 4 through bit 6 in register 0x06. The double-speed

sample rates (for example 88.2 kHz, 96 kHz) have the same PWM switching frequencies as their equivalent

single-speed sample rates.

表 6. PWM Switching Rates

SINGLE-SPEED

PWM RATE (× f_LRCLK

DOUBLE-SPEED

PWM RATE × f_LRCLK)

44.1 kHz, 88.2 kHz

f_PWM(kHz)

48 kHz, 96 kHz

f_PWM(kHz)

PWM_RATE [2:0]

)

000

001

010

011

100

101

110

111

264.6

352.8

441

288

384

480

576

672

768

960

1152

529.2

617.4

705.6

882

1058.4

The Class-D power stage overcurrent detector issues a latching fault if the load current exceeds the safe limit for

the device. This threshold can be proportionately adjusted if desired by programming bits 4-5 of register 0x08. 表

7 shows the relative setting for each overcurrent setting.

表 7. Overcurrent Threshold Settings

OC_THRESH

[1:0]

OVERCURRENT

THRESHOLD (%)

100

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7.4 Device Functional Modes

This section describes the modes of operation for the TAS5722L device.

表 8. Typical Current Consumption⁽¹⁾

INPUT

VOLTAGE

V_PVDD(V)

PWM

FREQUENCY

f_PWM(kHz)

INPUT

CURRENT

I_DVDD(mA)

I_PVDD+I_AVDD

MODE

(mA)

384

480

576

672

768

—

11.45

12.21

12.94

13.70

14.41

8.48

Idle and Mute

1.30

Sleep

0.32

Shutdown

—

0.021

13.06

14.46

15.79

17.18

18.49

7.49

0.046

384

480

576

672

768

—

Idle and Mute

1.30

12.5

Sleep

0.32

Shutdown

—

0.042

14.00

15.60

17.10

18.66

20.15

7.61

0.046

384

480

576

672

768

—

Idle and Mute

1.30

16.5

Sleep

0.32

Shutdown

—

0.045

0.046

(1) T_A= 25ºC, PVDD pin tied to AVDD pin, V_DVDD= 1.8 V, R_LOAD= 4Ω + 33 µH, f_IN= Idle, f_S= 48 kHz,

Gain = 20.7 dBV, PWR_TUNE bit = 1

7.4.1 Shutdown Mode (SDZ)

The device enters shutdown mode if either the SDZ pin is asserted low or the I²C SDZ register bit is set low (bit

0, reg 0x01). In shutdown mode, the device consumes the minimum quiescent current with most analog and

digital blocks powered down. The Class-D amplifier power stage powers down and the output pins are in a Hi-Z

state. I²C communication remains possible in shutdown mode and register bits states are retained.

If a latching fault condition has occurred (Over Temperature, Over Current or DC detect), the SDZ pin or I²C bit

must toggle low before the fault register can be cleared. For more information on faults and recovery, see the

Faults and Status section.

When the device exits shutdown mode (either by releasing the SDZ pin high or setting the I²C SDZ register bit

high), the device powers up the internal analog and digital blocks required for operation. If the I²C SLEEP bit is

set low (bit 1, reg 0x01), the device powers up the Class-D amplifier and begins the switching of the power

stage. If the I²C MUTE bit is set low (bit 4, reg 0x03), the device ramps up the volume to the current setting and

begins playing audio.

If shutdown mode is asserted while audio is playing, the device ramps down the volume on the audio, stops the

Class-D switching, puts the Class-D power stage output pins in a Hi-Z state and powers down the analog and

digital blocks.

7.4.2 Sleep Mode

Sleep mode is similar to shutdown mode, except analog and digital blocks required to begin playing audio quickly

remain powered up. Sleep mode operates as a hard mute where the Class-D amplifier stops switching, but the

device does not power down completely. Entering sleep mode does not clear latching faults.

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7.4.3 Mode Timing

When SDZ is deasserted (and the device is not in sleep mode), the amplifier begins to switch after a period of

t_ACTIVE. At this point, the volume ramps from –100 dB to the programmed digital volume control (DVC) setting in a

length of time t_VRMP. t_VRMPis determined by the DVC setting, sample rate and volume ramp rate bit,

VOL_RAMP_RATE (bit 6 of register 0x03). Ramping the volume prevents audible artifacts that can occur if

discontinuous volume changes are applied while audio is being played back. This period, t_VRMP, depends on the

DVC setting and sample rate. Typical values for t_VRMPfor a DVC of 0 dB are shown in Timing Requirements. 图 4

illustrates mode timing.

The time to enter or exit sleep or mute and the time to enter shudown are dominated by t_VRMP. 表 9 lists the

timing parameters based on t_VRMP

表 9. Typical DVC Ramp Times

RAMP TIMES (t_VRAMP) FROM –100 dB to 0

dB (ms)

SAMPLE

RATE (kHz)

VOL_RAMP_RATE = VOL_RAMP_RATE =

44.1

72.6

66.7

36.3

33.3

9.1

8.3

4.5

4.2

88.2

7.4.4 Auto Sleep Mode

Auto sleep mode is an optional feature that automatically moves the amplifier from active mode to sleep mode

when the device presents an idle audio input (i.e. zero value) to the SAIF for a prescribed number of samples.

The device automatically returns to active mode when the device presents a non-idle audio input sample to the

SAIF. Auto sleep mode takes advantage of the TAS5722L device's ability to rapidly enter and exit sleep mode

from active mode. Because the device applies idle audio samples to the SAIF before entering sleep mode, a

volume ramp can be avoided. When exiting sleep mode, the amplifier can resume switching before input sample

has propagated through the signal path, which avoids any audible artifacts when resuming playback.

AUTO_SLEEP[1:0] (bits 4:3 in register 0x13) configures the number of idle samples required to enter auto sleep.

7.4.5 Active Mode

If shutdown mode and sleep mode are not asserted, the device is in active mode. During active mode, audio

playback is enabled.

7.4.6 Mute Mode

When the I²C_MUTE bit is set high (bit 4, reg 0x03) and the device is in active mode, the volume is ramped

down and the Class-D amplifier continues to operate with an idle audio input.

7.4.7 Faults and Status

During the power-up sequence, the power-on-reset circuit (POR) monitoring the DVDD pin domain releases all

registers from reset (including the I²C registers) once DVDD is valid. The device does not exit shutdown mode

until the PVDD pin has a valid voltage between the undervoltage lockout (UVLO) and overvoltage lockout

(OVLO) thresholds. If DVDD drops below the POR threshold the device transitions into shutdown mode with all

registers held in reset. If UVLO or OVLO thresholds are violated by PVDD, the device transitions into sleep

mode, but registers are not forced into reset. Both of these conditions are non-latching and the device operates

normally once supply voltages are valid again. The device can be reset only by reducing DVDD below the POR

threshold.

The device transitions into sleep mode if it detects any faults with the SAIF clocks such as

•

Invalid MCLK to LRCLK and BCLK to LRCLK ratios

Invalid MCLK and LRCLK frequencies

Halting of MCLK, BCLK or LRCLK clocks

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Upon detection of a SAIF clock error, the device transitions into sleep mode as quickly as possible to limit the

possibility of audio artifacts. Once all SAIF clock errors are resolved, the device volume ramps back to its

previous playback state. During an SAIF clock error, the FAULTZ pin asserts low and the CLKE bit asserts high

(register 0x08, bit 3).

While operating in shutdown mode, the SAIF clock error detect circuitry powers down and the CLKE bit reads

high. This reading is not an indication of a SAIF clock error. If the device has not entered active mode after a

power-up sequence or after transitioning out of shutdown mode, the FAULTZ pin pulses low for only

approximately 10 µs every 350 µs. This action prevents a possible locking condition if the FAULTZ is connected

to the SDZ pin to accomplish automatic recovery. Once the device has entered active mode one time (after

power up or deassertion of shutdown mode), the SAIF clock errors pull the FAULTZ pin low continuously until the

fault has cleared.

The device also monitors die temperature, power stage load current and amplifier output DC content and issues

latching faults if any of these conditions occur. A die temperature of approximately 150°C causes the device to

enter sleep mode and issue an over-temperature error (OTE) readable via I²C (bit 0, reg 0x08).

Sustained excessive DC content at the output of the Class-D amplifier can damage loudspeakers via voice coil

heating. The amplifier has an internal circuit to detect significant DC content that forces the device into sleep

mode. The device issues a DC detect error (DCE) readable via I²C (bit 1, reg 0x08).

If the Class-D amplifier load current exceeds the threshold set by the OC_THRESH register bits (bits 5-4, reg

0x08), the device enters sleep mode and issues an overcurrent error (OCE) that is readable via I²C (bit 2, reg

0x08).

During OTE, DCE and OCE, the FAULTZ pin asserts low until the latched fault is cleared. FAULTZ is an open

drain pin and requires a pull-up resistor to the DVDD pin to achieve a logic high level when no faults exist. This

can be accomplished either with an internal pull up asserting FAULTZ_PU high (register 0x14, bit 3) or with an

external pull up resistor to DVDD.

Latched faults can be cleared only by toggling the SDZ pin or SDZ I²C bit (bit 0, reg 0x01). This toggle does not

clear I²C registers (except the fault status of OTE, OCE and DCE). If it is desirable for the device to attempt

automatic recovery after latching faults, implement a circuit like the one shown in . The device waits

approximately 650 ms after a DCE fault has cleared and 1.3 s after an OTE or OCE fault has cleared before

releasing FAULTZ high and allowing the device to enter active mode.

DVDD

TAS5722L

10kW

SDZ

SD from

Host

FAULTZ

Open-Drain

Driver or NFET

图 39. Auto Recovery Circuit

7.5 Register Maps

When writing to registers with reserved bits, maintain the values shown in 表 10 to ensure proper device

operation. Default register values are loaded during the power-up sequence or any time the DVDD voltage falls

below the power-on-reset (POR) threshold and then returns to valid operation.

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7.5.1 I²C Register Map Summary

表 10. I²C Register Map Summary

ADDR ADDR

NAME

DEFAULT

(Hex)

(Dec)

(Hex)

DEVICE_ID

0x00

Device ID

0x12

0xFD

0x04

0x80

0xCF

0x51

SDZ

DIGITAL_CLIP_LEVEL [19:14]

SLEEP

0x01

0x02

0x03

Power Control

SSZ/DS

HPF_BYPASS

TDM_CFG_SRC

RSV

SAIF_FORMAT

Digital Control

RSV

MUTE

VOL_RAMP_RATE

RSV

TDM_SLOT_SELECT[2:0]

Digital Control

VOLUME_CONTROL [8:1]

0x04 Volume Control

RSV

ANALOG_GAIN

PWM_RATE

RSV

0x06

0x08

Analog Control

Fault Config

and Error

Status

RSV

OC_THRESH

CLKE

OCE

DCE

OTE

0x00

DIGITAL_CLIP_LEVEL[13:6]

Digital Clipper

0x10

0x11

0x13

0xFF

0xFC

0x00

DIGITAL_CLIP_LEVEL[5:0]

RSV

Digital Clipper

HPF_CORNER

AUTO_SLEEP

TDM_SLOT_16B MCLK_PIN_CFG VOL_CONTROL[0]

Digital Control

RSV

FAULTZ_P

RSV

VREG_LVL

PWR_TUNE

Analog Control

0x14

0x02

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7.5.2 Register Maps

7.5.2.1 Device Identification Register (0x00)

图 40. Device Identification Register

DEVICE_ID[7:0]

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 11. Device Identification Register Field Descriptions

Bit

Field

Type

Reset

Description

This register returns a value of 0x12 when read.

7-0

DEVICE_ID[7:0]

7.5.2.2 Power Control Register (0x01)

图 41. Power Control Register

DIGITAL_CLIP_LEVEL[19:14]

R/W

SLEEP

R/W

SDZ

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 12. Power Control Register Field Descriptions

Bit

Field

Type

Reset

Description

7-2

DIGITAL_CLIP_LEVEL[19:14]

R/W

This register holds the top 6-bits of the 20-bit Digital Clipper

level. The Digital Clipper limits the magnitude of the sample

applied to the DAC. See the Digital Clipper section for more

information.

SLEEP

R/W

When the device enters SLEEP mode, volume ramps down and

the Class-D output stage powers down to a Hi-Z state. The rest

of the blocks maintain a state such that audio playback can be

restarted as quickly as possible. This mode has lower

dissipation than MUTE, but higher than SHUTDOWN. For more

information see the Device Functional Modes section.

0: Exit Sleep (default).

1: Enter Sleep.

SDZ

R/W

The device enters SHUTDOWN mode if either this bit is set to a

0 or the SDZ pin is pulled low externally. In SHUTDOWN, the

device holds the lowest dissipation state. I²C communication

remains functional and all registers are retained. For more

information see the Device Functional Modes section.

0: Enter SHUTDOWN.

1: Exit SHUTDOWN (default).

7.5.2.3 Digital Control Register 1 (0x02)

图 42. Digital Control Register 1

HPF_BYPASS TDM_CFG_SR

Reserved

R/W

SSZ/DS

SAIF_FORMAT[2:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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表 13. Digital Control Register 1 Field Descriptions

Bit

Field

Type

Reset

Description

HPF_BYPASS

R/W

The high-pass filter removes any DC component in the audio

content that could trip the DC detect protection feature in the

amplifer, which is a latching fault. Setting this bit bypasses the

high-pass filter. See the "High-Pass Filter" section under "Audio

Signal Path" for more information.

0: Enable high-pass filter (default).

1: Bypass high-pass filter.

TDM_CFG_SRC

R/W

This bit determines how the device selects which audio channel

direct to the playback stream. See the Serial Audio Interface

(SAIF) section for more information.

0: Set TDM Channel to I²C Device ID (default).

1: Set TDM Channel to TDM_SLOT_SELECT in register 0x03.

5-4

Reserved

SSZ/DS

R/W

These bits are reserved and should be set to 00 when writing to

this register.

This bit sets the sample rate to single speed or double speed

operation. See the Serial Audio Interface (SAIF) section for more

information.

0: Single speed operation (44.1 kHz/48 kHz) - default.

1: Double speed operation (88.2 kHz/96 kHz)

2-0

SAIF_FORMAT[2:0]

R/W

100

These bits set the Serial Audio Interface format. See the Serial

Audio Interface (SAIF) section for more information.

000: Right justified, 24-bit

001:Right justified, 20-bit

010: Right justified, 18-bit

011: Right justified, 16-bit

100: I²S (default)

101: Left Justified, 16-24 bits

110: Reserved. Do not select this value.

111: Reserved. Do not select this value.

7.5.2.4 Register Name (offset = ) [reset = ] or (address = ) [reset = ]

图 43. 8-bit, 1 Row

Reserved

VOL_RAMP_R

ATE

Reserved

MUTE

Reserved

TDM_SLOT_SELECT[2:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 14. (For example, CONTROL_REVISION Register) Field Descriptions

Bit

Field

Type

Reset

Description

Reserved

R/W

This bit is reserved and should be set to 1 when writing to this

address

VOL_RAMP_RATE

Reserved

R/W

This bit determines the volume ramp rate when entering or

exiting Mute, Shutdown or Sleep

0: Ramp 0.25 dB every 8 LRCLK periods (default)

1: Ramp 0.25 dB every LRCLK period

This bit is reserved and should be set to 1 when writing to this

address

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表 14. (For example, CONTROL_REVISION Register) Field Descriptions (接下页)

Bit

Field

Type

Reset

Description

MUTE

R/W

When set the device ramps down volume and play idle audio.

See the Amplifier Analog Gain and Digital Volume Control

section for more information.

0: Exit mute mode (default).

1: Enter mute mode.

Reserved

R/W

This bit is reserved and should be set to 0 when writing to this

address

2-0

TDM_SLOT_SELECT[2:0]

When the TDM_CFG_SRC bit is set to 1 in register 0x02, these

bits select which TDM channel is directed to audio playback.

See the Serial Audio Interface (SAIF) section for more

information.

7.5.2.5 Volume Control Register (0x04)

图 44. Volume Control Register

VOLUME_CONTROL[8:1]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 15. Volume Control Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

VOLUME_CONTROL[8:1]

R/W

11001111 This register sets the top 8 bits of the 9-bit Digital Volume

Control (DVC), The DVC ranges from –100 dB to +24 dB in 0.25

dB steps and has a default setting of 0 dB. Register settings of

less than 0x008 are equivalent to MUTE. Register 0x13 bit 0

sets the LSB value. See the Amplifier Analog Gain and Digital

Volume Control for more information.

7.5.2.6 Analog Control Register (0x06)

图 45. Analog Control Register

Reserved

R/W

PWM_RATE[2:0]

R/W

ANALOG_GAIN[1:0]

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 16. Analog Control Register Field Descriptions

Bit

Field

Type

Reset

Description

Reserved

R/W

This bit is reserved and should be set to 0 when writing to this

address

6-4

PWM_RATE[2:0]

R/W

101

These bits set the PWM switching rate, which is a locked ratio of

LRCLK. For more information see the Class-D Amplifier Settings

section.

000: 6 × LRCLK (single speed), 3 × LRCLK (double speed)

001: 8 × LRCLK (single speed), 4 × LRCLK (double speed)

010: 10 × LRCLK (single speed), 5 × LRCLK (double speed)

011: 12 × LRCLK (single speed), 6 × LRCLK (double speed)

100: 14 × LRCLK (single speed), 7 × LRCLK (double speed)

101: 16 × LRCLK (single speed), 8 × LRCLK (double speed) -

default

110: 20 × LRCLK (single speed), 10 × LRCLK (double speed)

111: 24 × LRCLK (single speed), 12 × LRCLK (double speed)

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表 16. Analog Control Register Field Descriptions (接下页)

Bit

Field

Type

Reset

Description

3-2

ANALOG_GAIN[1:0]

R/W

These bits set the analog gain of the Class-D amplifer. The

values shown indicate the output level with digital volume control

set to 0 dB and a full scale digital input (0 dBFS). This level may

not be acheivable because of analog clipping. See the Amplifier

Analog Gain and Digital Volume Control section for more

information.

00: 19.2 dBV (default)

01: 20.7 dBV

10: 23.5 dBV

11: 26.3 dBV

1-0

Reserved

R/W

These bits are reserved and should be set to 01 when writing to

this address

7.5.2.7 Fault Configuration and Error Status Register (0x08)

图 46. Fault Configuration and Error Status Register

CLKE

OCE

DCE

OTE

Reserved

R/W

OC_THRESH[1:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 17. Fault Configuration and Error Status Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

Reserved

R/W

These bits are reserved and should be set to 00 when writing to

this address.

5-4

OC_THRESH[1:0]

R/W

This register sets the Over Current detector threshold. For more

information see the Class-D Amplifier Settings section.

00: 100% of overcurrent limit (default)

01: 75% of overcurrent limit

10: 50% of overcurrent limit

11: 25% of overcurrent limit

CLKE

OCE

This bit indicates the status of the SAIF clock error detector.

This is a self clearning value.

0: No SAIF clock errors.

1: SAIF clock errors are present.

This bit indicates the status of the overcurrent error detector.

This is a latching value.

0: The Class-D output stage has not experienced an over

current event.

1: The Class-D output stage has experienced an over current

event.

DCE

OTE

This bit indicates the status of the DC detector. This is a latching

value.

0: The Class-D output stage has not experienced a DC detect

error.

1: The Class-D output stage has experienced a DC detect error.

This bit indicates the status of the over temperature detector.

This is a latching value.

0: The Class-D output stage has not experienced an over

temperature error.

1: The Class-D output stage has experienced an over

temperature error.

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7.5.2.8 Digital Clipper 2 Register (0x10)

图 47. Digital Clipper 2 Register

DIGITAL_CLIP_LEVEL[13:6]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 18. Digital Clipper 2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DIGITAL_CLIP_LEVEL[13:6]

R/W

This register holds the bits 13 through 6 of the 20-bit Digital

Clipper level. The Digital Clipper limits the magnitude of the

sample applied to the DAC. See the Digital Clipper section for

more information.

7.5.2.9 Digital Clipper 1 Register (0x11)

图 48. Digital Clipper 1 Register

DIGITAL_CLIP_LEVEL[5:0]

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 19. Digital Clipper 1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-2

DIGITAL_CLIP_LEVEL[5:0]

R/W

This register holds the bits 5 through 0 of the 20-bit Digital

Clipper level. The Digital Clipper limits the magnitude of the

sample applied to the DAC. See the Digital Clipper section for

more information.

1-0

Reserved

R/W

These bits are reserved and should be set to 00 when writing to

this register.

7.5.2.10 Digital Control Register 3 (0x13)

图 49. Digital Control Register 3

HPF_CORNER

AUTO_SLEEP

R/W

TDM_SLOT_16 MCLK_PIN_CF VOL_CONTRO

L[0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 20. Digital Control Register 3 Field Descriptions

Bit

Field

Type

Reset

Description

7-5

HPF_CORNER

R/W

These bits set the High Pass Filter corner frequency. Values for

44.1- kHz sample rate are shown in this table. See 表 3 in the

Audio Signal Path section for more information.

000: 3.7-Hz High Pass Corner at 44.1-kHz Sample Rate

(Default)

001: 7.4-Hz High Pass Corner at 44.1-kHz Sample Rate

010: 14.9-Hz High Pass Corner at 44.1-kHz Sample Rate

011: 29.7-Hz High Pass Corner at 44.1-kHz Sample Rate

100: 59.4-Hz High Pass Corner at 44.1-kHz Sample Rate

101: 118.4-Hz High Pass Corner at 44.1-kHz Sample Rate

110: 235.0-Hz High Pass Corner at 44.1-kHz Sample Rate

111: 463.2-Hz High Pass Corner at 44.1-kHz Sample Rate

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表 20. Digital Control Register 3 Field Descriptions (接下页)

Bit

Field

Type

Reset

Description

4-3

AUTO_SLEEP

R/W

These bits control the auto sleep function that disables the

power stage if no audio input has been zero for a prescribed

number of samples.

00: Auto Sleep Disabled (Default)

01: Auto Sleep after 1024 LRCLK's with idle input

10: Auto Sleep after 64 × 1024 LRCLK with idle input

11: Auto Sleep after 256 × 1024 LRCLK with idle input

This bit indicates the time slot bit width.

TDM_SLOT_16B

MCLK_PIN_CFG

R/W

0: Each time slot is 24 or 32 bits in width (Default).

1: Each time slot is 16 bits in width.

This bit indicates the source of MCLK.

0: MCLK signal is derived from BCLK internally. Connect MCLK

pin to GND on PCB (Default).

1: MCLK signal is derived from MCLK pin.

This is the LSB of the Digital Volume Control.

VOL_CONTROL[0]

R/W

7.5.2.11 Analog Control Register 2 (0x14)

图 50. Analog Control Register 2

Reserved

R/W

FAULTZ_PU

R/W

VREG_LVL

R/W

Reserved

R/W

PWR_TUNE

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 21. Analog Control Register 2 Field Descriptions

Bit

Field

Type

Reset

Description

7-4

Reserved

R/W

These bits are reserved and should be set to 0000 when writing

to this register.

FAULTZ_PU

VREG_LVL

R/W

This bit controls an internal 20-kΩ pull-up resistor on the

FAULTZ pin.

0: Disable pull-up resistor (Default).

1: Enable pull-up resistor.

This bit reduces the analog voltage regulator during low PVDD <

5.5-V operation.

0: Default regulator level of 5.4 V (Default).

1: Reduced regulator level of 3.9 V.

Reserved

R/W

This bit is reserved and should be set to 1 when writing to this

PWR_TUNE

This bit reduces static analog current in the analog domain by

approximately 0.9 mA.

0: Do not reduce analog supply current (Default).

1: Reduce analog supply current.

TAS5722L

www.ti.com.cn

ZHCSFV9A –MAY 2016–REVISED DECEMBER 2016

8 Applications and Implementation

8.1 Application Information

This section describes a filter-free,TDM application.

8.2 Typical Application

PVDD

1uF

0.1uF

100uF

1uF

1.8V

VREF_N

FAULTZ

SDZ

OUT_P

BST_P

PGND

BST_N

OUT_N

220nF

Control &

Status

LRCLK

MCLK

BCLK

SDI

TAS5722L

TDM

Master

1.8V

SCL

220nF

I2C Master

1.8V

PVDD

1uF

0.1uF

100uF

图 51. Filter Free 3-Wire TDM Application Circuit (I2C_DEV_ID = 0x6C)

8.2.1 Design Requirements

•

Input voltage range PVDD and AVDD: 4.5 V to 17 V

Input voltage range DVDD: 1.65 V to 2 V

Input sample rate: 44.1 kHz to 48 kHz or 88.2 kHz to 96 kHz

I²C clock frequency: up tp 400 kHz

Maximum output power: 15 W

8.2.2 Design Procedure

8.2.2.1 Overview

The TAS5722L is a very flexible and easy to use Class D amplifier; therefore the design process is

straightforward. Before beginning the design, gather the following information regarding the audio system.

•

PVDD rail planned for the design

Speaker or load impedance

Audio sample rate

Maximum output power requirement

Desired PWM frequency

TAS5722L

ZHCSFV9A –MAY 2016–REVISED DECEMBER 2016

www.ti.com.cn

Typical Application (接下页)

8.2.2.2 Select the PWM Frequency

Set the PWM frequency by writing to the PWM_RATE bits (bits 6-4, reg 0x06). The default setting for this register

is 101, which is 16 × LRCLK for single speed applications and 8 × LRCLK for double speed application. This

value equates to a default PWM frequency of 768 kHz for a 48 kHz sample rate.

8.2.2.3 Select the Amplifier Gain and Digital Volume Control

In order to select the amplifier gain setting, the designer must determine the maximum power target and the

speaker impedance. Once these parameters have been determined, calculate the required output voltage swing

which delivers the maximum output power.

Choose the lowest analog gain setting that produces an output voltage swing greater than the required output

swing for maximum power. The analog gain can be set by writing to the ANALOG_GAIN bits (bits 3-2, reg 0x06).

The default gain setting is 20.7 dBV referenced to 0dBFS input.

8.2.2.4 Select Input Capacitance

Select the bulk capacitors at the PVDD inputs for proper voltage margin and adequate capacitance to support the

power requirements. The TAS5722L has very good PVDD PSRR, so the capacitor is more about limiting the

ripple and droop for the rest of system than preserving good audio performance. The amount of bulk decoupling

can be reduced as long as the droop and ripple is acceptable. One capacitor should be placed near the PVDD

inputs at each side of the device. PVDD capacitors should be a low ESR type because they are being used in a

high-speed switching application.

8.2.2.5 Select Decoupling Capacitors

Good quality decoupling capacitors must be added at each of the PVDD inputs to provide good reliability, good

audio performance, and to meet regulatory requirements. X5R or better ratings should be used in this

application. Consider temperature, ripple current, and voltage overshoots when selecting decoupling capacitors.

Also, these decoupling capacitors should be located near the PVDD and GND connections to the device in order

to minimize series inductances.

8.2.2.6 Select Bootstrap Capacitors

Each of the outputs require bootstrap capacitors to provide gate drive for the high-side output FETs. For this

design, use 0.22-µF, 25-V capacitors of X5R quality or better.

8.2.3 Application Performance Plots

100

1000

900

800

700

600

500

400

300

200

100

0.001

0.01

0.1

0.001

0.01

0.1

Output Power (W)

R_L= 4Ω + 33 µH

Output Power (W)

R_L= 4Ω + 33 µH

C033

f_PWM= 576 kHz

图 52. Efficiency vs. Output Power

图 53. Supply Current vs. Output Power

TAS5722L

www.ti.com.cn

ZHCSFV9A –MAY 2016–REVISED DECEMBER 2016

9 Power Supply Recommendations

The power supply requirements for the TAS5722L device consist of one 1.8-V supply to power the low-voltage

analog and digital circuitry and one higher-voltage supply to power the output stage of the speaker amplifier.

Several on-chip regulators are included on the TAS5722L device to generate the voltages necessary for the

internal circuitry of the audio path. It is important to note that the voltage regulators which have been integrated

are sized only to provide the current necessary to power the internal circuitry. The external pins are provided only

as a connection point for off-chip bypass capacitors to filter the supply. Connecting external circuitry to these

regulator outputs may result in reduced performance and damage to the device.

The TAS5722L requires two power supplies. A 1.8-V supply, called DVDD, is required to power the digital

section of the device. A higher-voltage supply, between 4.5 V and 17 V, supplies the analog circuitry (AVDD) and

the power stage (PVDD). The AVDD supply feeds several LDOs including GVDD, VREG, and VCOM. These

LDO outputs are connected to external pins for filtering purposes, but should not be connected to external

circuits. These LDO outputs have been sized to provide current necessary for internal functions but not for

external loading.

10 Layout

10.1 Layout Guidelines

•

Pay special attention to the power stage power supply layout. Each half bridge has two PVDD input pins so

that decoupling capacitors can be placed nearby. Use at least a 0.1-µF capacitor of X5R quality or better for

each set of inputs.

•

Keep the current circulating loops containing the supply decoupling capacitors, the H-bridges in the device

and the connections to the speakers as tight as possible to reduce emissions.

Use ground planes to provide the lowest impedance for power and signal current between the device and the

decoupling capacitors. The area directly under the device should be treated as a central ground area for the

device, and all device grounds must be connected directly to that area.

•

Use a via pattern to connect the area directly under the device to the ground planes in copper layers below

the surface. This connection helps to dissipate heat from the device.

Avoid interrupting the ground plane with circular traces around the device. Interruption disconnects the copper

and interrupt flow of heat and current. Radial copper traces are better to use if necessary.

TAS5722L

ZHCSFV9A –MAY 2016–REVISED DECEMBER 2016

www.ti.com.cn

10.2 Layout Example

Connect top ground

to lower ground plane

with vias

Connect top power

connection to lower

supply layer with vias

Speaker Connector

OUT_P

BST_P

LRCLK

Serial

Audio

MCLK

BCLK

SDIN

Source

BST_N

OUT_N

Exposed Thermal

Pad Area

I2C

SCL

Control

SDA

图 54. Layout Example

TAS5722L

www.ti.com.cn

ZHCSFV9A –MAY 2016–REVISED DECEMBER 2016

11 器件和文档支持

11.1 商标

All trademarks are the property of their respective owners.

11.2 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.3 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

TAS5722L

ZHCSFV9A –MAY 2016–REVISED DECEMBER 2016

www.ti.com.cn

12 机械封装和可订购信息

以下页中包括机械封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对本

文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

TAS5722L

www.ti.com.cn

ZHCSFV9A –MAY 2016–REVISED DECEMBER 2016

12.1 Package Option Addendum

12.1.1 Packaging Information

Package

Drawing

Package

Qty

Device

(1)

(2)

(3)

Orderable Device

TAS5722LRSMR

TAS5722LRSMT

Status

Package Type

VQFN

Pins

Eco Plan

Lead/Ball Finish

CU NIPDAU

MSL Peak Temp

Op Temp (°C)

–25 to 85

Marking⁽⁴⁾⁽⁵⁾

TAS

5722L

ACTIVE

RSM

3000

250

Green (RoHS & no Sb/Br)

Level-3-260C-168 HR

TAS

5722L

VQFN

CU NIPDAU

–25 to 85

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

space

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest

availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the

requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified

lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used

between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by

weight in homogeneous material)

space

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

space

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device

space

(5) Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief

on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third

parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for

release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAS5722L

ZHCSFV9A –MAY 2016–REVISED DECEMBER 2016

www.ti.com.cn

12.1.2 Tape and Reel Information

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

Reel

Diameter

(mm)

Reel

Width W1

(mm)

Package

Type

Package

Drawing

(mm)

Pin1

Quadrant

Device

Pins

SPQ

TAS5722LRSMR

TAS5722LRSMT

VQFN

RSM

3000

250

330.0

180.0

12.4

4.25

1.15

8.0

12.0

TAS5722L

www.ti.com.cn

ZHCSFV9A –MAY 2016–REVISED DECEMBER 2016

TAPE AND REEL BOX DIMENSIONS

Width (mm)

Device

Package Type

Package Drawing Pins

SPQ

3000

250

Length (mm) Width (mm)

Height (mm)

35.0

TAS5722LRSMR

TAS5722LRSMT

VQFN

RSM

367.0

210.0

367.0

185.0

35.0

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TAS5722LRSMR

TAS5722LRSMT

ACTIVE

VQFN

RSM

3000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-3-260C-168 HR

-25 to 85

TAS

5722L

ACTIVE

RSM

NIPDAU

TAS

5722L

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Apr-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TAS5722LRSMR

TAS5722LRSMT

VQFN

RSM

3000

250

330.0

180.0

12.4

4.25

1.15

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Apr-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TAS5722LRSMR

TAS5722LRSMT

VQFN

RSM

3000

250

346.0

210.0

346.0

185.0

33.0

35.0

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RSM 32

4 x 4, 0.4 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224982/A

www.ti.com

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TAS5722LRSMT [TI]

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