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TAS5754M

SLAS987 –JUNE 2014

Digital Input, Closed-Loop Class-D Amplifier with HybridFlow Processing

1 Features

3 Description

The TAS5754M device is a high-performance, stereo

closed-loop amplifier with integrated audio processor

with PurePath™ HybridFlow architecture. To convert

from digital to analog, it uses a high performance

DAC with Burr-Brown^®mixed signal heritage. It

requires only two power supplies: one DVDD for low-

voltage circuitry and one PVDD for high-voltage

circuitry. It is controlled via a software control port

using standard I²C communication. In the family, the

TAS5756M uses traditional BD modulation, ensuring

low distortion characteristics. The TAS5754M uses

1SPW modulation, reducing the idle current draw at

the expense of slightly higher distortion.

1

•

Flexible Audio I/O Configuration

–

Supports I²S, TDM, LJ, RJ Digital Input

8 kHz to 192 kHz Sample Rate Support

Stereo Bridge Tied Load (BTL) or Mono

Parallel Bridge Tied Load (PBTL) Operation

–

BD Modulation with TAS5756M, 1SPW

Modulation with TAS5754M

Supports 3-Wire Digital Audio Interface (No

MCLK required)

•

High Performance Closed-Loop Architecture

(PVDD = 12V, R_SPK= 8 Ω, SPK_GAIN = 20dBV)

The unique HybridFlow architecture allows the

system designer to choose from several configurable

DSP programs, specifically designed for use in

popular audio end equipment such as bluetooth (BT)

speakers, sound bars, docking stations, and

subwoofers. This combines the flexibility of a fully

programmable device with the fast download time

and ease of use of a fixed function ROM device.

–

Idle Channel Noise = 62 µVrms (A-Wtd)

THD+N = 0.007 % (at 1 W, 1 kHz)

SNR = 103 A-Wtd (Ref. to THD+N = 1%)

PurePath™ HybridFlow Processing Architecture

–

Several Configurable MiniDSP Programs

(called HybridFlows)

–

Download Time <100 ms (typ)

An optimal mix of thermal performance and device

cost is provided in the 90 mΩ r_DS(on)of the output

MOSFETs. Additionally, a thermally enhanced 48-

Terminal TSSOP provides excellent operation in the

elevated ambient temperatures found in modern

consumer electronic devices.

Advanced Audio Processing Algorithms

•

Communication Features

–

Software Mode Control via I²C Port

Two Address Select Pins – Up to 4 Devices

Robustness and Reliability Features

Device Information⁽¹⁾

–

Clock Error, DC, and Short-Circuit Protection

Over Temperature and Overcurrent Protection

PART NUMBER

PACKAGE

BODY SIZE (NOM)

TAS5754M

TSSOP (48)

12.05 mm × 6.10 mm

2 Applications

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

•

LCD/LED TV and Multi-Purpose Monitors

Sound Bars, Docking Stations, PC Audio

Wireless Subwoofers, Bluetooth and Active

Speakers

Figure 1. Simplified Block Diagram

Figure 2. Power at 10% THD+N vs PVDD

DVDD

PVDD

50

Inst Power, Rspk = 8

Cont Power, Rspk = 8

Inst Power, Rspk = 6

Cont Power, Rspk = 6

Inst Power, Rspk = 4

Cont Power, Rspk = 4

45

40

35

30

25

20

15

10

5

High Voltage

Supply Domain

Low-Voltage Supply Domain

HybridFlow

Processing

High Performance

Stereo DAC

001100

1101

Closed Loop Stereo

Class D Amplifier

Serial

Audio In

Analog

Audio Out

PWM

Modulator

Power

Stage

Serial

Audio Out

miniDSP Core

Hardware

Control Port

Software Control Port

I²C Communication

0

4

6

8

10

12

14

16

18

20

22

24

GPIO/Status

PVDD (V)

C036

Note: Tested on TAS5754M-56MEVM.

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TAS5754M

SLAS987 –JUNE 2014

www.ti.com

Table of Contents

7.13 Typical Performance Plots for the TAS5754M...... 26

Detailed Description ............................................ 34

8.1 Overview ................................................................. 34

8.2 Functional Block Diagram ....................................... 35

8.3 Feature Description................................................. 35

8.4 Register Maps......................................................... 61

Applications and Implementation ...................... 85

9.1 Application Information............................................ 85

9.2 Typical Applications ............................................... 86

1

2

3

4

5

6

Features.................................................................. 1

8

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 3

6.1 Internal Pin Configurations........................................ 5

Specifications......................................................... 8

7.1 Absolute Maximum Ratings ...................................... 8

7.2 Handling Ratings....................................................... 9

7.3 Recommended Operating Conditions....................... 9

7.4 Thermal Information.................................................. 9

7.5 Electrical Characteristics......................................... 10

7.6 MCLK Timing ......................................................... 15

7.7 Serial Audio Port Timing – Slave Mode.................. 16

7.8 Serial Audio Port Timing – Master Mode................ 17

7.9 I²C Bus Timing – Standard ..................................... 18

7.10 I²C Bus Timing – Fast........................................... 18

7.11 SPK_MUTE Timing .............................................. 20

7.12 Power Dissipation ................................................. 20

9

7

10 Power Supply Recommendations ................... 105

10.1 Power Supplies ................................................... 105

11 Layout................................................................. 107

11.1 Layout Guidelines ............................................... 107

11.2 Layout Examples................................................. 109

12 Device and Documentation Support ............... 119

12.1 Device Support.................................................... 119

12.2 Trademarks......................................................... 119

12.3 Electrostatic Discharge Caution.......................... 119

12.4 Glossary.............................................................. 119

13 Mechanical, Packaging, and Orderable

Information ......................................................... 120

4 Revision History

DATE

REVISION

NOTES

June 2014

*

Initial release.

2

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5 Device Comparison Table

DEVICE NAME

MODULATION STYLE

1SPW (Ternary)

TAS5754MDCA

TAS5756MDCA

BD Modulation

6 Pin Configuration and Functions

48-Terminal TSSOP

DCA Package

(Thermal Pad Down)

BSTRPA±

SPK_OUTA±

PGND

SPK_OUTA+

BSTRPA+

PVDD

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

BSTRPB±

SPK_OUTB±

PGND

SPK_OUTB+

BSTRPB+

PVDD

SPK_FAULT

PGND

SPK_INB±

SPK_INB+

DAC_OUTB

CPVSS

CN

GND

CP

CPVDD

DVDD

PVDD

GVDD_REG

SPK_GAIN/FREQ

AGND

9

10

11

12

13

14

15

16

17

18

19

SPK_INA±

SPK_INA+

DAC_OUTA

AVDD

AGND

SDA

SCL

GPIO0

Thermal Pad

GPIO1

ADR1

GPIO2

MCLK

SCLK

DGND

20

21

22

23

24

29

28

27

26

25

DVDD_REG

SPK_MUTE

ADR0

SDIN

LRCK/FS

Pin Functions

NAME

INTERNAL

TERMINATION

TYPE⁽¹⁾

DESCRIPTION

NO.

26

20

10

15

14

Sets the LSB of the I²C Address to 0 if pulled to GND, to 1 if pulled to DVDD

Sets the 2nd LSB of the I²C Address to 0 if pulled to GND, to 1 if pulled to DVDD

ADR0

ADR1

DI

Figure 13

Ground reference for analog circuitry (NOTE: This pin should be connected to the system

ground)

AGND

AVDD

G

—

P

Figure 4

Power supply for internal analog circuitry

Connection point for the SPK_OUTA– bootstrap capacitor which is used to create a power

supply for the high-side gate drive for SPK_OUTA–

BSTRPA–

BSTRPA+

BSTRPB–

BSTRPB+

1

5

Connection point for the SPK_OUTA+ bootstrap capacitor which is used to create a power

supply for the high-side gate drive for SPK_OUTA

P

Figure 5

Connection point for the SPK_OUTB– bootstrap capacitor which is used to create a power

supply for the high-side gate drive for SPK_OUTB–

48

44

Connection point for the SPK_OUTB+ bootstrap capacitor which is used to create a power

supply for the high-side gate drive for SPK_OUTB+

(1) AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, DI/O = Digital Bi-directional (input and output), P =

Power, G = Ground (0 V)

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Pin Functions (continued)

INTERNAL

TERMINATION

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

Negative pin for capacitor connection used in the headphone amplifier and line driver charge

pump

CN

CP

34

P

Figure 17

Positive pin for capacitor connection used in the headphone amplifier and line driver charge

pump

32

Figure 16

CPVDD

31

35

13

36

29

30

P

Figure 4

Power supply for charge pump circuitry

CPVSS

Figure 17

–3.3-V supply generated by charge pump for the DAC

Single-ended output for Channel A of the DAC

Single-ended output for Channel B of the DAC

Ground reference for digital circuitry. Connect this pin to the system ground.

Power supply for the internal digital circuitry

DAC_OUTA

DAC_OUTB

DGND

AO

G

Figure 10

—

DVDD

P

Figure 4

Voltage regulator derived from DVDD supply for use for internal digital circuitry. This pin is

provided as a connection point for filtering capacitors for this supply and must not be used to

power any external circuitry.

DVDD_REG

28

P

Figure 18

GND

33

18

19

21

G

Ground pin for device. This pin should be connected to the system ground.

GPIO0

GPIO1

GPIO2

General purpose input/output pins (GPIOx) which can be incorporated in a HybridFlow for a

given purpose. Refer to documentation of target HybridFlow to determine if any of these pins

are required by the HybridFlow and, if so, how they are to be used. In most HybridFlows,

presentation of a serial audio signal, called SDOUT, is done through GPIO2.

DI/O

P

Figure 13

Figure 7

Voltage regulator derived from PVDD supply to generate the voltage required for the gate drive

of output MOSFETs. This pin is provided as a connection point for filtering capacitors for this

supply and must not be used to power any external circuitry.

GVDD_REG

8

Word select clock for the digital signal that is active on the serial port's input data line. In I²S,

LJ, and RJ, this corresponds to the left channel and right channel boundary. In TDM mode, this

corresponds to the frame sync boundary.

LRCK/FS

MCLK

25

DI/O

DI

Figure 14

22

3

Master clock used for internal clock tree and sub-circuit and state machine clocking

PGND

39

46

6

G

—

Ground reference for power device circuitry. Connect this pin to the system ground.

7

PVDD

41

42

43

17

23

16

24

11

12

38

37

P

Figure 3

Power supply for internal power circuitry

I²C serial control port clock

SCL

DI

DI/O

D1

AI

Figure 12

Figure 14

Figure 11

Figure 14

SCLK

Bit clock for the digital signal that is active on the input data line of the serial data port

I²C serial control port data

SDA

SDIN

Data line to the serial data port

SPK_INA–

SPK_INA+

SPK_INB–

SPK_INB+

Negative pin for differential speaker amplifier input A

Positive pin for differential speaker amplifier input A

Negative pin for differential speaker amplifier input B

Positive pin for differential speaker amplifier input B

AI

Figure 9

AI

Fault pin which is pulled low when an overcurrent, overtemperature, overvoltage, undervoltage,

or DC detect event occurs

SPK_FAULT

40

DO

Figure 19

Figure 8

SPK_GAIN/FREQ

SPK_OUTA–

SPK_OUTA+

SPK_OUTB–

SPK_OUTB+

9

2

AI

Sets the gain and switching frequency of the speaker amplifier.

Negative pin for differential speaker amplifier output A

Positive pin for differential speaker amplifier output A

Negative pin for differential speaker amplifier output B

Positive pin for differential speaker amplifier output B

AO

4

Figure 6

47

45

Speaker amplifier mute which must be pulled low (connected to DGND) to mute the device and

pulled high (connected to DVDD) to unmute the device.

SPK_MUTE

Themal pad

27

I

Figure 15

—

Provides both electrical and thermal connection from the device to the board. A matching

ground pad must be provided on the PCB and the device connected to it through solder. For

proper electrical operation, this ground pad must be connected to the system ground.

G

4

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6.1 Internal Pin Configurations

PVDD

DVDD

30 V ESD

3.3 V ESD

Figure 3. PVDD Pins

Figure 4. AVDD, DVDD and CPVDD Pins

GVDD

PVDD

BSTRPxx

PVDD

7 V ESD

SPK_OUTxx

Figure 5. BSTRPxx Pins

Figure 6. SPK_OUTxx Pins

GVDD

PVDD

10 ꢀ

GVDD

10 Nꢀ

SPK_GAIN/FREQ

7 V ESD

Figure 8. SPK_GAIN/FREQ Pin

Figure 7. GVDD_REG Pin

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Internal Pin Configurations (continued)

AVDD

SPK_INxx

7 V ESD

Gain Switch

CPVSS

DAC_OUTA

Figure 9. SPK_INxx Pins

Figure 10. DAC_OUTx Pins

DVDD

SDA

DVDD

SCL

3.3 V

ESD

3.3 V

ESD

Figure 11. SDA Pin

Figure 12. SCL Pin

DVDD

GPIO1

GPIO2

GPIO3

ADR0

ADR1

MCLK

SCLK

SDIN

3.3 V

ESD

3.3 V

ESD

LRCK/FS

Figure 14. SCLK, BCLK, SDIN, and LRCK/FS Pins

Figure 13. GPIO and ADR Pins

6

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Internal Pin Configurations (continued)

DVDD

CVPDD

CP

SPK_MUTE

3.3 V

ESD

3.3 V

ESD

Figure 15. SPK_MUTE Pin

Figure 16. CP Pin

DVDD

GND

CN

DVDD_REG

3.3 V

ESD

1.8 V

ESD

CPVSS

3.3 V

ESD

Figure 18. DVDD_REG Pin

Figure 17. CN and CPVSS Pins

100 ꢀ

SPK_FAULT

28 V

ESD

Figure 19. SPK_FAULT Pin

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7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

Low-voltage digital, analog, charge pump

supply

DVDD, AVDD, CPVDD

–0.3

3.9

V

PVDD supply

PVDD

–0.3

30

V

Input voltage for SPK_GAIN/FREQ and

SPK_FAULT pins

V_I(AmpCtrl)

–0.3 V_GVDD+0.3

DVDD referenced digital inputs⁽²⁾

Analog input into speaker amplifier

Voltage at speaker output pins

Ambient operating temperature, T_A

V_I(DigIn)

–0.5 V_DVDD+0.5

V

V_{I(SPK_INxx)}

V_{I(SPK_OUTxx)}

–0.3

–25

6.3

32

85

V

°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) DVDD referenced digital pins include: ADR0, ADR1, GPIO0, GPIO1, GPIO2, LRCK/FS, MCLK, SCL, SCLK, SDA, SDIN, and

SPK_MUTE.

8

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7.2 Handling Ratings

MIN

MAX

UNIT

T_stg

Storage temperature range

–40

125

°C

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all

pins⁽¹⁾

–2

2

kV

V

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC specification

JESD22-C101, all pins⁽²⁾

–500

500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

2.9

4.5

3

NOM

MAX

UNIT

DVDD, AVDD, CPVDD

PVDD

3.63

26.4

V_(POWER)

Power supply inputs

V

Minimum speaker load in BTL mode

Minimum speaker load in PBTL mode

Ω

R_SPK

2

Input logic high for DVDD referenced

digital inputs⁽¹⁾⁽²⁾

V_IH(DigIn)

V_IL(DigIn)

L_OUT

0.9×V_DVDD

V_DVDD

1

V_DVDD

V

Input logic low for DVDD referenced

digital inputs⁽¹⁾⁽³⁾

0

0.1×V_DVDD

Minimum inductor value in LC filter

under short-circuit condition

4.7

µH

(1) DVDD referenced digital pins include: ADR0, ADR1, GPIO0, GPIO1, GPIO2, LRCK/FS, MCLK, SCL, SCLK, SDA, SDIN, and

SPK_MUTE.

(2) The best practice for driving the input pins of the TAS5754M device is to power the drive circuit or pull-up resistor from the same supply

which provides the DVDD power supply.

(3) The best practice for driving the input pins of the TAS5754M device low is to pull them down, either actively or through pull-down

resistors to the system ground.

7.4 Thermal Information

TSSOP

(48 PINS)

THERMAL METRIC⁽¹⁾

UNIT

JEDEC

TAS5754M-

56MEVM

STANDARD 2

LAYER PCB

STANDARD 4

LAYER PCB

(AIP012A)

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

41.8

14.4

9.4

27.6

14.4

9.4

19.4

14.4

9.4

R_θJC(top)

R_θJB

ψ_JT

Junction-to-top characterization

parameter

0.6

8.1

1.0

0.6

9.3

1.0

2.0

4.8

N/A

°C/W

ψ_JB

Junction-to-board characterization

parameter

R_θJC(bot)

Junction-to-case (bottom) thermal

resistance

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

10

UNIT

DIGITAL I/O

Input logic high current

level for DVDD

referenced digital input

pins⁽¹⁾

|IIH|1

V_IN(DigIn)= V_DVDD

µA

Input logic low current

level for DVDD

|IIL|1

V_IN(DigIn)= 0 V

–10

referenced digital input

pins.⁽¹⁾

Input logic high

threshold for DVDD

referenced digital

inputs⁽¹⁾

V_IH1

70%

80%

V_DVDD

Input logic low threshold

for DVDD referenced

digital inputs⁽¹⁾

V_IL1

30%

V_DVDD

Output logic high

voltage level⁽¹⁾

V_OH(DigOut)

I_OH= 4 mA

V_DVDD

V

Output logic low voltage

level⁽¹⁾

V_OL(DigOut)

I_OH= –4mA

22%

0.8

Output logic low voltage

level for SPK_FAULT

V_{OL(SPK_FAULT)}

With 100-kΩ pull-up resistor

I²C CONTROL PORT

Allowable load

C_L(I2C)

capacitance for each

I²C Line

400

pF

f_SCL(fast)

f_SCL(slow)

Support SCL frequency No wait states, fast mode

Support SCL frequency No wait states, slow mode

400

100

kHz

Noise margin at High

level for each connected

device (including

hysteresis)

V_NH

0.2 × V_DD

V

MCLK AND PLL SPECIFICATIONS

Allowable MCLK duty

cycle

D_MCLK

40%

128

6.7

1

60%

512

20

Supported MCLK

frequencies

(2)

f_MCLK

Up to 50 MHz

f_S

Clock divider uses fractional divide D

> 0, P = 1

MHz

f_PLL

PLL input frequency

Clock divider uses integer divide D =

0, P = 1

20

(1) DVDD referenced digital pins include: ADR0, ADR1, GPIO0, GPIO1, GPIO2, LRCK/FS, MCLK, SCL, SCLK, SDA, SDIN, and

SPK_MUTE.

(2) A unit of f_Sindicates that the specification is the value listed in the table multiplied by the sample rate of the audio used in the

TAS5754M device .

10

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

SERIAL AUDIO PORT

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Required LRCK/FS to

SCLK rising edge delay

t_DLY

D_SCLK

f_S

5

40%

8

ns

Allowable SCLK duty

cycle

60%

192

Supported input sample

rates

kHz

Supported SCLK

frequencies

(3)

f_SCLK

32

64

f_S

SCLK frequency

Either master mode or slave mode

24.576

MHz

SPEAKER AMPLIFIER (ALL OUTPUT CONFIGURATIONS)

SPK_GAIN/FREQ voltage < 3.0 V,

see Adjustable Amplifier Gain and

Switching Frequency Selection

20.3

dBV

A_{V(SPK_AMP)}

Speaker amplifier gain

SPK_GAIN/FREQ voltage > 3.3 V,

see Adjustable Amplifier Gain and

Switching Frequency Selection

26.427

±1

dBV

Typical variation of

speaker amplifier gain

ΔA_{V(SPK_AMP)}

Switching frequency depends on

voltage presented at

SPK_GAIN/FREQ pin and the

clocking arrangement, including the

incoming sample rate, see Adjustable

Amplifier Gain and Switching

Frequency Selection

Switching frequency of

the speaker amplifier

f_{SPK_AMP}

176.4

768

kHz

Injected Noise = 50 Hz to 60 Hz, 200

mV_P-P, Gain = 26dBV, input audio

signal = digital zero

Power supply rejection

ratio

K_SVR

60

90

dB

V_PVDD= 24 V, I_{(SPK_OUT)}= 500 mA, T_J

= 25°C, includes PVDD/PGND pins,

leadframe, bondwires and

Drain-to-source on

resistance of the

individual output

MOSFETs

mΩ

r_DS(on)

metallization layers.

V_PVDD= 24 V, I_{(SPK_OUT)}= 500 mA, T_J

= 25°C

90

7.5

150

27

mΩ

A

SPK_OUTxx Over-

Current Error Threshold

OCE_THRES

Over-Temperature Error

Threshold

OTE_THRES

°C

V

PVDD Over-Voltage

Error Threshold

OVE_THRES(PVDD)

UVE_THRES(PVDD)

PVDD Under-Voltage

Error Threshold

4.5

V

SPEAKER AMPLIFIER (STEREO BTL)

Measured differentially with zero input

data, SPK_GAIN/FREQ pin

2

5

10

15

configured for 20dBV gain, V_PVDD

12 V

=

|V_OS

|

Amplifier offset voltage

mV

Measured differentially with zero input

data, SPK_GAIN/FREQ pin

configured for 26dBV gain, V_PVDD

24 V

=

(3) A unit of f_Sindicates that the specification is the value listed in the table multiplied by the sample rate of the audio used in the

TAS5754M device .

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_PVDD= 12 V, SPK_GAIN = 20dBV,

R_SPK= 8 Ω, A-Weighted

62

V_PVDD= 15 V, SPK_GAIN = 20dBV,

R_SPK= 8 Ω, A-Weighted

65

78

81

I_CN(SPK)

Idle channel noise

µV_RMS

V_PVDD= 19 V, SPK_GAIN = 26dBV,

R_SPK= 8 Ω, A-Weighted

V_PVDD= 24 V, SPK_GAIN = 26dBV,

R_SPK= 8 Ω, A-Weighted

V_PVDD= 12 V, SPK_GAIN = 20dBV,

R_SPK= 4 Ω, THD+N = 0.1%, Unless

otherwise noted

14

40

V_PVDD= 24 V, SPK_GAIN = 26dBV,

R_SPK= 4 Ω, THD+N = 0.1%, Unless

otherwise noted

V_PVDD= 24 V, SPK_GAIN = 26dBV,

R_SPK= 8 Ω, THD+N = 0.1%

33

30

V_PVDD= 12 V, SPK_GAIN = 20dBV,

R_SPK= 8 Ω, THD+N = 0.1%

Maximum continuous

output power per

channel

P_O(SPK)

W

V_PVDD= 19 V, SPK_GAIN = 26dBV,

R_SPK= 4 Ω, THD+N = 0.1%, Unless

otherwise noted

21

18

V_PVDD= 19 V, SPK_GAIN = 26dBV,

R_SPK= 8 Ω, THD+N = 0.1%

V_PVDD= 15 V, SPK_GAIN = 26dBV,

R_SPK= 4 Ω, THD+N = 0.1%, Unless

otherwise noted

23

V_PVDD= 15 V, SPK_GAIN = 26dBV,

R_SPK= 8 Ω, THD+N = 0.1%

13

V_PVDD= 15 V, SPK_GAIN = 26dBV,

R_SPK= 8 Ω, A-Weighted, -120dBFS

Input

102

V_PVDD= 12 V, SPK_GAIN = 20dBV,

R_SPK= 8 Ω, A-Weighted, -120dBFS

Input

103

105

103

Signal-to-noise ratio

(referenced to 0dBFS

input signal)

SNR

dB

V_PVDD= 24 V, SPK_GAIN[1:0] Pins =

10, R_SPK= 8 Ω, A-Weighted, -

120dBFS Input

V_PVDD= 19 V, SPK_GAIN = 20dB,

R_SPK= 8 Ω, A-Weighted, -120dBFS

Input

V_PVDD= 12 V, SPK_GAIN = 20dBV,

R_SPK= 4 Ω, P_O= 1 W

0.009%

0.006%

0.028%

0.018%

0.017%

0.02%

V_PVDD= 12 V, SPK_GAIN = 20dBV,

R_SPK= 8 Ω, P_O= 1 W

V_PVDD= 24 V, SPK_GAIN = 20dB,

R_SPK= 4 Ω, P_O= 1 W

V_PVDD= 15 V, SPK_GAIN = 20dB,

R_SPK= 4 Ω, P_O= 1 W

Total harmonic

distortion and noise

THD+N_SPK

V_PVDD= 15 V, SPK_GAIN = 20dB,

R_SPK= 8 Ω, P_O= 1 W

V_PVDD= 19 V, SPK_GAIN = 20dB,

R_SPK= 4 Ω, P_O= 1 W

V_PVDD= 19 V, SPK_GAIN = 20dB,

R_SPK= 8 Ω, P_O= 1 W

0.017%

0.022%

V_PVDD= 24 V, SPK_GAIN = 20dB,

R_SPK= 8 Ω, P_O= 1 W

12

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_PVDD= 15 V, SPK_GAIN = 20dB,

R_SPK= 8 Ω, Input Signal 250 mVrms,

1-kHz Sine, across f(S)

–102

V_PVDD= 12 V, SPK_GAIN = 20dBV,

R_SPK= 8 Ω, Input Signal 250 mVrms,

1-kHz Sine, across f(S)

–90

–93

Cross-talk (worst case

between left-to-right and

right-to-left coupling)

X-talk_SPK

dB

V_PVDD= 24 V, SPK_GAIN = 20dB,

R_SPK= 8 Ω, Input Signal 250 mVrms,

1-kHz Sine, across f(S)

V_PVDD= 19 V, SPK_GAIN = 20dB,

R_SPK= 8 Ω, Input Signal 250 mVrms,

1-kHz Sine, across f(S)

SPEAKER AMPLIFIER (MONO PBTL)

Measured differentially with zero input

data, SPK_GAIN/FREQ pin

0.7

4

8

configured for 20dBV gain, V_PVDD

12 V

=

|V_OS

|

Amplifier offset voltage

mV

Measured differentially with zero input

data, SPK_GAIN/FREQ pin

configured for 20dB gain, V_PVDD= 24

V

14

V_PVDD= 15 V, SPK_GAIN = 20 dBV,

RSPK = 8 Ω, A-Weighted

64

62

83

82

V_PVDD= 12 V, SPK_GAIN = 20 dBV,

R_SPK= 8 Ω, A-Weighted

I_CN

Idle channel noise

µV_RMS

V_PVDD= 19 V, SPK_GAIN = 26 dBV,

RSPK = 8 Ω, A-Weighted

V_PVDD= 24 V, SPK_GAIN = 26 dBV,

R_SPK= 8 Ω, A-Weighted

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_PVDD= 24 V, SPK_GAIN = 26 dBV,

R_SPK= 2 Ω, THD+N = 0.1%, Unless

otherwise noted

40

V_PVDD= 24 V, SPK_GAIN = 26 dBV,

R_SPK= 4 Ω, THD+N = 0.1%, Unless

otherwise noted

61

34

50

9

V_PVDD= 24 V, SPK_GAIN = 26 dBV,

R_SPK= 8 Ω, THD+N = 0.1%

V_PVDD= 19 V, SPK_GAIN = 26 dBV,

R_SPK= 2 Ω, THD+N = 0.1%, Unless

otherwise noted

V_PVDD= 12 V, SPK_GAIN = 20 dBV,

R_SPK= 8 Ω, THD+N = 0.1%

V_PVDD= 19 V, SPK_GAIN = 26 dBV,

R_SPK= 4 Ω, THD+N = 0.1%, Unless

otherwise noted

36

20

44

Maximum continuous

output power per

channel

P_O

W

V_PVDD= 19 V, SPK_GAIN = 26 dBV,

R_SPK= 8 Ω, THD+N = 0.1%

V_PVDD= 15 V, SPK_GAIN = 26 dBV,

R_SPK= 2 Ω, THD+N = 0.1%, Unless

otherwise noted

V_PVDD= 15 V, SPK_GAIN = 26 dBV,

R_SPK= 4 Ω, THD+N = 0.1%, Unless

otherwise noted

22

13

30

V_PVDD= 15 V, SPK_GAIN = 26 dBV,

R_SPK= 8 Ω, THD+N = 0.1%

V_PVDD= 12 V, SPK_GAIN = 20 dBV,

R_SPK= 2 Ω, THD+N = 0.1%, Unless

otherwise noted

V_PVDD= 12 V, SPK_GAIN = 20 dBV,

R_SPK= 4 Ω, THD+N = 0.1%, Unless

otherwise noted

16

104

105

107

105

V_PVDD= 15 V, SPK_GAIN = 26 dBV,

R_SPK= 8 Ω, A-Weighted, -120dBFS

Input

V_PVDD= 12 V, SPK_GAIN = 20 dBV,

R_SPK= 8 Ω, A-Weighted, -120dBFS

Input

Signal-to-noise ratio

(referenced to 0dBFS

input signal)

SNR

dB

V_PVDD= 24 V, SPK_GAIN = 26 dBV,

R_SPK= 8 Ω, A-Weighted, -120dBFS

Input

V_PVDD= 19 V, SPK_GAIN = 26 dBV,

R_SPK= 8 Ω, A-Weighted, -120dBFS

Input

14

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_PVDD= 12 V, SPK_GAIN = 20 dBV,

R_SPK= 4 Ω, P_O= 1 W

0.019%

V_PVDD= 12 V, SPK_GAIN = 20 dBV,

R_SPK= 8 Ω, P_O= 1 W

0.014%

0.035%

0.04%

V_PVDD= 24 V, SPK_GAIN = 26 dBV,

R_SPK= 4 Ω, P_O= 1 W

V_PVDD= 24 V, SPK_GAIN = 26 dBV,

R_SPK= 2 Ω, P_O= 1 W

V_PVDD= 24 V, SPK_GAIN = 26 dBV,

R_SPK= 8 Ω, P_O= 1 W

0.027%

0.029%

0.047%

0.025%

0.047%

0.015%

0.037%

0.020%

V_PVDD= 19 V, SPK_GAIN = 26 dBV,

R_SPK= 4 Ω, P_O= 1 W

Total harmonic

distortion and noise

THD+N

V_PVDD= 19 V, SPK_GAIN = 26 dBV,

R_SPK= 2 Ω, P_O= 1 W

V_PVDD= 15 V, SPK_GAIN = 26 dBV,

R_SPK= 4 Ω, P_O= 1 W

V_PVDD= 15 V, SPK_GAIN = 26 dBV,

R_SPK= 2 Ω, P_O= 1 W

V_PVDD= 15 V, SPK_GAIN = 26 dBV,

R_SPK= 8 Ω, P_O= 1 W

V_PVDD= 12 V, SPK_GAIN = 20 dBV,

R_SPK= 2 Ω, P_O= 1 W

V_PVDD= 19 V, SPK_GAIN = 26 dBV,

R_SPK= 8 Ω, P_O= 1 W

7.6 MCLK Timing

MIN

20

9

NOM

MAX

UNIT

ns

t_MCLK

MCLK period

1000

t_MCLKH

t_MCLKL

MCLK pulse width, high

MCLK pulse width, low

ns

9

ns

t

MCLKH

"H"

0.7 × V

DVDD

0.3 × V

DVDD

"L"

t

MCLKL

MCLK

Figure 20. Timing Requirements for MCLK Input

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7.7 Serial Audio Port Timing – Slave Mode

MIN

40

16

8

NOM

MAX

UNIT

ns

t_SCLK

t_SCLKL

t_SCLKH

t_SL

SCLK period

SCLK pulse width, low

ns

SCLK pulse width, high

ns

SCLK rising to LRCK/FS edge

LRCK/FS Edge to SCLK rising edge

Data set-up time, before SCLK rising edge

Data hold time, after SCLK rising edge

Data delay time from SCLK falling edge

ns

t_LS

8

ns

t_SU

8

ns

t_DH

8

ns

t_DFS

15

ns

LRCK/FS

(Input)

0.5 × DVDD

t

SCLKL

SCLKH

t

LS

SCLK

(Input)

t

SL

SCLK

DATA

(Input)

0.5 × DVDD

t

DH

SU

t

DFS

DATA

(Output)

Figure 21. MCLK Timing Diagram in Slave Mode

16

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7.8 Serial Audio Port Timing – Master Mode

MIN

40

16

–10

8

NOM

MAX

UNIT

ns

t_SCLK

t_SCLKL

t_SCLKH

t_LRD

SCLK period

SCLK pulse width, low

ns

SCLK pulse width, high

ns

LRCK/FS delay time from to SCLK falling edge

Data set-up time, before SCLK rising edge

Data hold time, after SCLK rising edge

Data delay time from SCLK falling edge

20

15

ns

t_SU

ns

t_DH

8

ns

t_DFS

ns

t_BCL

t

BCL

t

SCLK.

SCLK

(Input)

0.5 × DVDD

t

LRD

SCLK

LRCK/FS

(Input)

t

DFS

DATA

(Input)

0.5 × DVDD

t

DH

SU

DATA

(Output)

0.5 × DVDD

Figure 22. MCLK Timing Diagram in Master Mode

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7.9 I²C Bus Timing – Standard

MIN

MAX

UNIT

kHz

µs

f_SCL

SCL clock frequency

100

t_BUF

Bus free time between a STOP and START condition

Low period of the SCL clock

High period of the SCL clock

Setup time for (repeated)START condition

Hold time for (repeated)START condition

Data setup time

4.7

t_LOW

t_HI

4.7

µs

4.0

µs

t_RS-SU

t_S-HD

t_D-SU

t_D-HD

t_SCL-R

4.7

µs

4.0

250

µs

ns

Data hold time

0

900

ns

Rise time of SCL signal

20 + 0.1C_B

1000

ns

Rise time of SCL signal after a repeated START condition and after an

acknowledge bit

t_SCL-R1

20 + 0.1C_B

1000

ns

t_SCL-F

t_SDA-R

t_SDA-F

t_P-SU

Fall time of SCL signal

20 + 0.1C_B

4.0

1000

ns

µs

Rise time of SDA signal

Fall time of SDA signal

Setup time for STOP condition

7.10 I²C Bus Timing – Fast

MIN

MAX

UNIT

kHz

µs

f_SCL

SCL clock frequency

400

t_BUF

Bus free time between a STOP and START condition

Low period of the SCL clock

High period of the SCL clock

Setup time for (repeated)START condition

Hold time for (repeated)START condition

Data setup time

1.3

t_LOW

t_HI

1.3

µs

600

ns

t_RS-SU

t_RS-HD

t_D-SU

t_D-HD

t_SCL-R

600

ns

600

100

ns

Data hold time

0

900

300

ns

Rise time of SCL signal

20 + 0.1C_B

ns

Rise time of SCL signal after a repeated START condition and after an

acknowledge bit

t_SCL-R1

20 + 0.1C_B

300

ns

t_SCL-F

t_SDA-R

t_SDA-F

t_P-SU

t_SP

Fall time of SCL signal

20 + 0.1C_B

600

300

ns

Rise time of SDA signal

Fall time of SDA signal

Setup time for STOP condition

Pulse width of spike suppressed

50

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Repeated

START

STOP

t

P-SU

t

D-SU

D-HD

SDA-F

SDA-R

t

BUF.

SDA

t

SP

SCL-R.

RS-HD

t

LOW.

SCL

t

HI.

t

RS-SU

t

SCL-F.

S-HD.

Figure 23. I²C Communication Port Timing Diagram

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7.11 SPK_MUTE Timing

MIN

MAX

20

UNIT

ns

t_r

t_f

Rise time

Fall time

20

ns

0.9 × DV

DD

0.1 × DV

SPK_MUTE

t

r

t

f

< 20 ns

<20ns

Figure 24. SPK_MUTE Timing Diagram for Soft Mute Operation via Hardware Pin

7.12 Power Dissipation

SPK_GAIN^(1)(2)(3)

(dBV)

f_{SPK_AMP}

(kHz)

STATE OF

OPERATION

R_SPK

(Ω)

I_PVDD

I_DVDD

P_DISS

(W)

(4)

(5)

V_PVDD

(V)

(mA)

35

17

1

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

21.3

0.273

0.274

0.071

0.072

0.018

0.019

0.319

0.297

0.319

0.071

0.072

0.019

Idle

Mute

21.33

21.3

21.33

21.34

21.36

2.08

384

Standby

Powerdown

Idle

2.11

2.17

2.03

2.04

1

2.06

1

7.4

20

27.48

27.49

24.46

27.5

35

17

1

Mute

27.51

27.52

2.04

768

Standby

Powerdown

2.08

2.11

2.06

2.07

1

2.08

1

(1) Mute: P0-R3-B0,B5 = 1

(2) Standby: P0-R2-B5 = 1

(3) P0-R2-B0 = 1

(4) I_PVDDrefers to all current that flows through the PVDD supply for the DUT. Any other current sinks not directly related to the DUT current

draw were removed.

(5) I_DVDDrefers to all current that flows through the DVDD (3.3-V) supply for the DUT. Any other current sinks not directly related to the

DUT current draw were removed.

20

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Power Dissipation (continued)

(4)

(5)

V_PVDD

(V)

SPK_GAIN^(1)(2)(3)

(dBV)

f_{SPK_AMP}

(kHz)

STATE OF

OPERATION

R_SPK

(Ω)

I_PVDD

I_DVDD

P_DISS

(W)

(mA)

24.33

24.32

24.36

24.32

24.37

3.58

(mA)

35

17

1

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

0.386

0.385

0.386

0.385

0.386

0.096

0.042

0.043

0.456

0.150

0.456

0.095

0.096

0.042

0.043

Idle

Mute

384

Standby

Powerdown

Idle

3.57

3.58

3.52

1

3.54

1

11.1

20

30.7

35

17

1

30.65

30.67

3.072

30.69

3.54

Mute

768

Standby

Powerdown

3.54

3.58

3.53

1

3.55

1

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Power Dissipation (continued)

(4)

(5)

V_PVDD

(V)

SPK_GAIN^(1)(2)(3)

(dBV)

f_{SPK_AMP}

(kHz)

STATE OF

OPERATION

R_SPK

(Ω)

I_PVDD

I_DVDD

P_DISS

(W)

(mA)

25.07

25.08

25.1

(mA)

35

17

1

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

0.416

0.417

0.416

0.417

0.103

0.050

0.491

0.103

0.050

Idle

Mute

25.12

25.08

25.11

3.92

384

Standby

Powerdown

Idle

3.93

3.94

3.87

3.85

1

3.87

1

12

20

31.31

31.29

31.31

31.33

31.32

3.88

35

17

1

Mute

768

Standby

Powerdown

3.9

3.91

3.89

3.91

1

3.88

1

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Power Dissipation (continued)

(4)

(5)

V_PVDD

(V)

SPK_GAIN^(1)(2)(3)

(dBV)

f_{SPK_AMP}

(kHz)

STATE OF

OPERATION

R_SPK

(Ω)

I_PVDD

I_DVDD

P_DISS

(W)

(mA)

27.94

27.91

27.75

27.98

27.94

27.88

5.09

(mA)

35

17

1

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

0.535

0.534

0.532

0.535

0.534

0.132

0.133

0.134

0.079

0.080

0.611

0.612

0.611

0.132

0.133

0.079

0.080

Idle

Mute

384

Standby

Powerdown

Idle

5.12

5.19

5.02

5.06

1

5.14

1

15

26

33.05

33.03

33.08

33.03

33.04

33.05

5.07

35

17

1

Mute

768

Standby

Powerdown

5.09

5.14

5.02

5.04

1

5.09

1

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Power Dissipation (continued)

(4)

(5)

V_PVDD

(V)

SPK_GAIN^(1)(2)(3)

(dBV)

f_{SPK_AMP}

(kHz)

STATE OF

OPERATION

R_SPK

(Ω)

I_PVDD

I_DVDD

P_DISS

(W)

(mA)

32.27

32.19

32.08

32.27

32.24

32.22

6.95

6.93

7

(mA)

35

17

1

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

0.748

0.746

0.744

0.748

0.747

0.192

0.193

0.138

0.139

0.140

0.801

0.192

0.193

0.137

0.138

0.139

Idle

Mute

384

Standby

Powerdown

Idle

6.89

6.9

1

6.96

34.99

34.95

34.97

34.96

34.98

34.96

6.93

6.98

6.84

6.89

6.9

1

19.6

26

35

17

1

Mute

768

Standby

Powerdown

1

24

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Power Dissipation (continued)

(4)

(5)

V_PVDD

(V)

SPK_GAIN^(1)(2)(3)

(dBV)

f_{SPK_AMP}

(kHz)

STATE OF

OPERATION

R_SPK

(Ω)

I_PVDD

I_DVDD

P_DISS

(W)

(mA)

36.93

36.87

36.77

36.94

36.89

36.85

8.73

(mA)

35

17

1

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

4

6

8

1.002

1.000

0.998

1.002

1.001

1.000

0.266

0.265

0.211

0.212

1.000

0.999

1.000

0.999

0.264

0.265

0.210

0.211

Idle

Mute

384

Standby

Powerdown

Idle

8.72

8.71

8.64

8.66

1

8.69

1

24

26

36.84

36.86

36.83

36.85

36.84

36.82

8.66

35

17

1

Mute

768

Standby

Powerdown

8.68

8.71

8.63

8.64

1

8.65

1

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7.13 Typical Performance Plots for the TAS5754M

All performance plots were taken using the TAS5754M-56MEVM at room temperature, unless otherwise noted.

The term "Traditional LC filter" refers to the output filter that is present by default on the EVM. For "Filterless"

measurements, the on-board LC filter was removed and an Audio Precision AUX-025 measurement filter was

used to take the measurements.

Table 1. Quick Reference Table

OUTPUT

CONFIG

PLOT TITLE

PLOT NUMBER

Figure 25. Output Power vs PVDD

C036

C034

C002

C037

C003

C035

C004

C038

C005

C006

C007

C013

C015

C008

C009

C010

C011

C012

C014

C039

C017

C018

C019

C020

C021

C022

C023

C024

C025

C026

C031

C033

C027

C028

C029

C030

C032

Figure 26. THD+N vs Frequency, V_PVDD= 12 V

Figure 27. THD+N vs Frequency, V_PVDD= 15 V

Figure 28. THD+N vs Frequency, V_PVDD= 18 V

Figure 29. THD+N vs Frequency, V_PVDD= 24 V

Figure 30. THD+N vs Power, V_PVDD= 12 V

Figure 31. THD+N vs Power, V_PVDD= 15 V

Figure 32. THD+N vs Power, V_PVDD= 18 V

Figure 33. THD+N vs Power, V_PVDD= 24 V

Figure 34. Idle Channel Noise vs PVDD

Figure 35. Efficiency vs Output Power

BTL

Figure 36. Idle Current Draw (Filterless) vs PVDD

Figure 37. Idle Current Draw (Traditional LC Filter) vs PVDD

Figure 38. Crosstalk vs. Frequency

Figure 39. PVDD PSRR vs Frequency

Figure 40. DVDD PSRR vs Frequency

Figure 41. AVDD PSRR vs Frequency

Figure 42. CPVDD PSRR vs Frequency

Figure 43. Powerdown Current Draw vs PVDD

Figure 44. Output Power vs PVDD

Figure 45. THD+N vs Frequency, V_PVDD= 12 V

Figure 46. THD+N vs Frequency, V_PVDD= 15 V

Figure 47. THD+N vs Frequency, V_PVDD= 18 V

Figure 48. THD+N vs Frequency, V_PVDD= 24 V

Figure 49. THD+N vs Power, V_PVDD= 12 V

Figure 50. THD+N vs Power, V_PVDD= 15 V

Figure 51. THD+N vs Power, V_PVDD= 18 V

Figure 52. THD+N vs Power, V_PVDD= 24 V

Figure 53. Idle Channel Noise vs PVDD

Figure 54. Efficiency vs Output Power

PBTL

Figure 55. Idle Current Draw (filterless) vs PVDD

Figure 56. Idle Current Draw (traditional LC filter) vs PVDD

Figure 57. PVDD PSRR vs Frequency

Figure 58. DVDD PSRR vs Frequency

Figure 59. AVDD PSRR vs Frequency

Figure 60. CPVDD PSRR vs Frequency

Figure 61. Powerdown Current Draw vs PVDD

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7.13.1 Bridge Tied Load (BTL) Configuration Curves

Return to Quick Reference Table.

50

1

0.1

Inst Power, Rspk = 8

Rspk = 4

Rspk = 6

Rspk = 8

Cont Power, Rspk = 8

Inst Power, Rspk = 6

Cont Power, Rspk = 6

Inst Power, Rspk = 4

Cont Power, Rspk = 4

45

40

35

30

25

20

15

10

5

0.01

0.001

0

4

6

8

10

12

14

16

18

20

22

24

20

200

2k

20k

PVDD (V)

Frequency (Hz)

C036

C034

A_{V(SPK_AMP)}= 26dBV

Figure 25. Output Power vs PVDD – BTL

A_{V(SPK_AMP)}= 20dBV

P_O= 1W

V_PVDD= 12V

Figure 26. THD+N vs Frequency – BTL

1

0.1

Rspk = 4

Rspk = 6

Rspk = 8

Rspk = 6

Rspk = 8

0.1

0.01

0.001

0.01

0.001

20

200

2k

20k

20

200

2k

20k

Frequency (Hz)

C002

C037

A_{V(SPK_AMP)}= 20dBV

P_O= 1W

V_PVDD= 15V

A_{V(SPK_AMP)}= 20dBV

P_O= 1W

V_PVDD= 18V

Figure 27. THD+N vs Frequency – BTL

Figure 28. THD+N vs Frequency – BTL

1

0.1

10

1

Rspk = 4

Rspk = 6

Rspk = 8

Rspk = 6

Rspk = 8

0.1

0.01

0.001

0.01

0.001

20

200

2k

20k

0.01

0.1

1

10

Frequency (Hz)

Power (W)

C003

C035

A_{V(SPK_AMP)}= 26dBV

P_O= 1W

V_PVDD= 24V

A_{V(SPK_AMP)}= 20dBV

Input Signal =

1kHz Sine

V_PVDD= 12V

Figure 29. THD+N vs Frequency – BTL

Figure 30. THD + N vs Power – BTL

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10

1

10

1

Rspk = 4

Rspk = 6

Rspk = 8

Rspk = 4

Rspk = 6

Rspk = 8

0.1

0.01

0.1

0.01

0.001

0.01

0.1

1

10

0.01

0.1

1

10

Power (W)

C004

C038

A_{V(SPK_AMP)}= 20dBV

Input Signal =

1kHz Sine

V_PVDD= 15V

A_{V(SPK_AMP)}= 26dBV

Input Signal =

1kHz Sine

V_PVDD= 18V

Figure 31. THD + N vs Power – BTL

Figure 32. THD + N vs Power – BTL

10

1

150

125

100

75

Gain = 20dBV, fspk_amp = 384kHz

Gain = 26dBV, fspk_amp = 384kHz

Gain = 20dBV, fspk_amp = 768kHz

Gain = 26dBV, fspk_amp = 768kHz

Rspk = 4

Rspk = 6

Rspk = 8

0.1

50

0.01

0.001

25

0

0.01

0.1

1

10

4

6

8

10

12

14

16

18

20

22

24

Power (W)

P_O= 1W

PVDD (V)

C005

C006

A_{V(SPK_AMP)}= 26dBV

V_PVDD= 24V

A_{V(SPK_AMP)}= 20dBV

f_{SPK_AMP}

384kHz

=

R_SPK= 8Ω

Figure 34. Idle Channel Noise vs PVDD – BTL

Figure 33. THD + N vs Power – BTL

100

90

80

70

60

50

60

50

40

30

20

10

0

Filterless

PVDD = 12V

PVDD = 15V

PVDD = 18V

PVDD = 24V

0

20

40

60

80

100

4

6

8

10

12

14

16

18

20

22

24

Total Output Power (W)

PVDD (V)

C007

C013

R_SPK= 8 Ω

f_{SPK_AMP}= 768kHz

R_SPK= 8Ω

Figure 35. Efficiency vs Output Power – BTL

Figure 36. Idle Current Draw (Filterless) vs V_PVDD– BTL

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0

±10

Ch. B vs Ch. A

Ch. A vs Ch. B

Traditional LC

80

70

60

50

40

30

20

10

0

±20

±30

±40

±50

±60

±70

±80

±90

±100

±110

±120

4

6

8

10

12

14

16

18

20

22

24

20

200

2k

20k

PVDD (V)

Frequency (Hz)

C015

C008

f_{SPK_AMP}= 768kHz

R_SPK= 8Ω

A_{V(SPK_AMP)}= 26dBV

Sine Input

V_PVDD= 24V

Figure 37. Idle Current Draw (Traditional LC Filter) vs

PVDD – BTL

Figure 38. Crosstalk vs Frequency – BTL

0

±10

±20

±30

±40

±50

±60

±70

±80

±90

Ch. B kSVR

Ch. A kSVR

Ch. B vs Ch. A

±10

Ch. A vs Ch. B

±20

±30

±40

±50

±60

±70

±80

±90

20

200

2k

20k

20

200

2k

20k

Frequency (Hz)

C009

Supply Noise =

250mV

C010

A_{V(SPK_AMP)}= 26dBV

V_PVDD= 24V

Sine Input

A_{V(SPK_AMP)}= 26dBV

V_PVDD= 24V

R_SPK= 8Ω

Supply Noise =

250mV

Figure 39. PVDD PSRR vs Frequency – BTL

Figure 40. DVDD PSRR vs Frequency – BTL

0

±10

±20

±30

±40

±50

±60

±70

±80

±90

0

±10

±20

±30

±40

±50

±60

±70

±80

±90

Ch. B kSVR

Ch. A kSVR

Left kSVR

Right kSVR

20

200

2k

20k

20

200

2k

20k

Frequency (Hz)

C011

Supply Noise =

250mV

C012

Supply Noise =

250mV

A_{V(SPK_AMP)}= 26dBV

V_PVDD= 24V

R_SPK= 8Ω

A_{V(SPK_AMP)}= 26dBV

V_PVDD= 24V

Sine Input

Figure 41. AVDD PSRR vs Frequency – BTL

Figure 42. CPVDD PSRR vs Frequency – BTL

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10

9

8

7

6

5

4

3

2

1

0

Shutdown

4

6

8

10

12

14

16

18

20

22

24

PVDD (V)

C014

A_{V(SPK_AMP)}= 26dBV

f_{SPK_AMP}

786kHz

=

Figure 43. Powerdown Current Draw vs PVDD – BTL

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7.13.2 Parallel Bridge Tied Load (PBTL) Configuration

Return to Quick Reference Table.

120

1

0.1

Inst Power, Rspk = 4

Cont Power, Rspk = 4

Ins Power, Rspk = 3

Cont Power, Rspk = 3

Inst Power, Rspk = 2

Cont Power, Rspk = 2

Rspk = 2

Rspk = 3

Rspk = 4

100

80

60

40

20

0

0.01

0.001

4

6

8

10

12

14

16

18

20

22

24

20

200

2k

20k

PVDD (V)

C017

Frequency (Hz)

C039

A_{V(SPK_AMP)}= 26dBV

Measured on

TAS5754/6

EVM

A_{V(SPK_AMP)}= 20dBV

P_O= 1W

V_PVDD= 12V

Figure 45. THD+N vs Frequency – PBTL

Figure 44. Output Power vs PVDD – PBTL

1

0.1

1

0.1

Rspk = 2

Rspk = 3

Rspk = 4

Rspk = 2

Rspk = 3

Rspk = 4

0.01

0.001

0.01

0.001

20

200

2k

20k

20

200

2k

20k

C018

C019

Frequency (Hz)

A_{V(SPK_AMP)}= 20dBV

P_O= 1W

V_PVDD= 15V

A_{V(SPK_AMP)}= 26dBV

P_O= 1W

V_PVDD= 18V

Figure 46. THD+N vs Frequency – PBTL

Figure 47. THD+N vs Frequency – PBTL

10

1

0.1

Rspk = 2

Rspk = 3

Rspk = 4

Rspk = 2

Rspk = 3

Rspk = 4

0.1

0.01

0.001

0.01

0.001

0.01

0.1

1

10

20

200

2k

20k

Power (W)

P_O= 1W

C020

Frequency (Hz)

C021

A_{V(SPK_AMP)}= 26dBV

P_O= 1W

V_PVDD= 24V

A_{V(SPK_AMP)}= 20dBV

V_PVDD= 12V

Figure 48. THD+N vs Frequency – PBTL

Figure 49. THD+N vs Power – PBTL

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10

1

10

1

Rspk = 2

Rspk = 3

Rspk = 4

Rspk = 2

Rspk = 3

Rspk = 4

0.1

0.01

0.1

0.01

0.001

0.01

0.1

1

10

0.01

0.1

1

10

100

Power (W)

P_O= 1W

Power (W)

C022

C023

A_{V(SPK_AMP)}= 20dBV

V_PVDD= 15V

A_{V(SPK_AMP)}= 20dBV

V_PVDD= 18V

Input Signal =

1kHz Sine

P_O= 1W

Figure 50. THD+N vs Power – PBTL

Figure 51. THD+N vs Power – PBTL

10

1

150

125

100

75

Gain = 20dBV, fS = 384kHz

Gain = 26dBV, fS = 384kHz

Gain = 20dBV, fS = 768kHz

Gain = 26dBV, fS = 768kHz

Rspk = 2

Rspk = 3

Rspk = 4

0.1

50

0.01

0.001

25

0

0.01

0.1

1

10

100

4

6

8

10

12

14

16

18

20

22

24

Power (W)

PVDD (V)

C024

C025

A_{V(SPK_AMP)}= 20dBV

V_PVDD= 24V

Input Signal =

1kHz Sine

P_O= 1W

A_{V(SPK_AMP)}= 26dBV

I_LOAD= xA

V_PVDD= 18V

Figure 53. Idle Channel Noise vs PVDD – PBTL

Figure 52. THD+N vs Power – PBTL

100

90

80

70

60

50

60

50

40

30

20

10

0

PVDD = 12V

PVDD = 15V

PVDD = 18V

PVDD = 24V

Filterless

0

20

40

60

80

100

4

6

8

10

12

14

16

18

20

22

24

Total Output Power (W)

PVDD (V)

C026

C031

A_{V(SPK_AMP)}= 26dBV

I_LOAD= xA

V_PVDD= 24V

Figure 54. Efficiency vs Output Power – PBTL

Figure 55. Idle Current Draw (Filterless) vs PVDD – PBTL

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0

±10

±20

±30

±40

±50

±60

±70

±80

±90

Rspk = 4

80

70

60

50

40

30

20

10

0

Traditional LC

20 22

4

6

8

10

12

14

16

18

24

20

200

2k

20k

PVDD (V)

Frequency (Hz)

C033

C027

A_{V(SPK_AMP)}= 26dBV

Sine Input

V_PVDD= 24V

Figure 56. Idle Current Draw (Traditional LC filter) vs

PVDD – PBTL

Figure 57. PVDD PSRR vs Frequency – PBTL

0

±10

±20

±30

±40

±50

±60

±70

±80

±90

Rspk = 4

±10

±20

±30

±40

±50

±60

±70

±80

±90

20

200

2k

20k

20

200

2k

20k

Frequency (Hz)

C028

Supply Noise =

250mV

C029

Supply Noise =

250mV

A_{V(SPK_AMP)}= 26dBV

V_PVDD= 24V

R_SPK= 8Ω

A_{V(SPK_AMP)}= 26dBV

V_PVDD= 24V

R_SPK= 8Ω

Figure 58. DVDD PSRR vs Frequency – PBTL

Figure 59. AVDD PSRR vs Frequency – PBTL

0

±10

±20

±30

±40

±50

±60

±70

±80

±90

10

9

8

7

6

5

4

3

2

1

0

Rspk = 4

Shutdown

20

200

2k

20k

4

6

8

10

12

14

16

18

20

22

24

Frequency (Hz)

PVDD (V)

C030

Supply Noise =

250mV

C032

A_{V(SPK_AMP)}= 26dBV

V_PVDD= 24V

Sine Input

A_{V(SPK_AMP)}= 26dBV

f_{SPK_AMP}

786kHz

=

Figure 61. Powerdown Current Draw vs PVDD – PBTL

Figure 60. CPVDD PSRR vs Frequency – PBTL

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8 Detailed Description

8.1 Overview

The TAS5754M device integrates 4 main building blocks together into a single cohesive device that maximizes

sound quality, flexibility, and ease of use. These are shown in the list below:

1. A stereo Audio DAC, boasting a strong Burr-Brown heritage with a highly flexible serial audio port.

2. A miniDSP audio processing core with HybridFlow architecture, which provides an increase in flexibility over

a fixed-function ROM device with faster download time than a fully programmable device

3. A flexible closed-loop amplifier capable of operating in stereo or mono, at several different switching

frequencies, and with a variety of output voltages and loads.

4. An I²C control port for communication with the device

The device requires only two power supplies for proper operation. A DVDD supply is needed to power the low-

voltage digital and analog circuitry. Another supply, called PVDD, is needed to provide power to the output stage

of the audio amplifier. The operating range for these supplies is shown in the Recommended Operating

Conditions table.

Communication with the device is accomplished via the I²C control port. A speaker amplifier fault line is also

provided to notify a system controller of the occurrence of an over-temperature, over-current, over-voltage,

under-voltage, or DC error in the speaker amplifier. There are three digital GPIO pins that are available for use

by the HybridFlows. One popular use of the GPIO lines is to provide a Serial Audio Output from the device

(SDOUT). HybridFlows which provide an SDOUT customarily present that signal on GPIO2, although this

configuration can be changed via the I²C control port. The register space in the control port spans several pages

to accommodate some static controls which maintain their functionality across HybridFlows, as well as controls

that are determined by the HybridFlow used.

The MiniDSP audio processing core, featuring a HybridFlow architecture, allows the selection of a configurable

DSP program called a HybridFlow from a list of available HybridFlows. A hybrid flow combines audio processing

blocks, many of which that are built in the ROM portion of the device, together in a single payload. The PurePath

Console GUI provides a means by which to select the HybridFlow and manipulate the controls associated with

that HybridFlow.

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8.2 Functional Block Diagram

Internal

Voltage

Supplies

Charge

Pump

Internal Gate

Drive Regulator

1.8-V

Internal Voltage

Regulator

Supplies

Closed Loop Class D Amplifier

Gate

SPK_OUTA+

SPK_OUTA-

Full Bridge

Power

Stage A

Mini-DSP

Output

Current

Monitoring

and

Protection

Analog

to

Drives

Hybrid RAM/

ROM

Architecture

with

Several

Selectable

HybridFlows

MCLK

SCLK

SPK_OUTB+

SPK_OUTB-

PWM

Modulator

Full Bridge

Power

Stage B

Gate

Drives

DAC

Serial

Audio

Port

LRCK/FS

SDIN

Clock Monitoring

and Error Protection

Die Temperature

Monitoring and Protection

Error Reporting

SDOUT

Internal Control Registers and State Machines

GPIO0

GPIO1 GPIO2

SPK_GAIN/FREQ

SCL

SDA

ADR0

ADR1

SPK_MUTE

SPK_SD SPK_FAULT

8.3 Feature Description

8.3.1 Power-on-Reset (POR) Function

The TAS5754M device has a power-on reset function. This feature resets all of the registers to their default

configuration as the device is powering up. When the low-voltage power supply used to power DVDD, AVDD,

and CPVDD exceeds the POR threshold, the device holds sets all of the internal registers to their default values

and holds them there until it receives valid MCLK, SCLK, and LRCK/FS toggling for a period of approximately 4

ms. After the toggling period has passed, the internal reset of the registers is removed and the registers can be

programmed via the I²C Control Port.

8.3.2 Device Clocking

The TAS5754M devices have flexible systems for clocking. Internally, the device requires a number of clocks,

mostly at related clock rates to function correctly. All of these clocks can be derived from the Serial Audio

Interface in one form or another.

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Feature Description (continued)

f_S

(24-bit)

16 f_S

(24-bit)

128 f_S

(~8-bit)

Serial Audio

Interface

(Input)

miniDSP

(including

interpolator)

Delta

Sigma

Modulator

I to V

Line

Driver

Current

Segments

+

Audio

In

Audio

Out

Charge Pump

CPCK

DSPCK

OSRCK

DACCK

LRCK/FS

Figure 62. Audio Flow with Respective Clocks

As shown in Figure 62 the basic data flow at basic sample rate (f_S). Once the data is brought into the serial audio

interface, it is processed, interpolated and modulated to 128 × f_Sbefore arriving at the current segments for the

final digital to analog conversion.

The clock tree is shown in Figure 63.

PLLEN

(P0-R4)

MCLK

SREF

(P0-R13)

Divider

DDSP (P0-R27)

SCLK

GPIO

MCLK

SDAC

(P0-R14)

PLL

K × R/P

PLLCKIN

PLLCK

K = J.D

J = 1,2,3,«..,62,63

D= 0000,0001,«.,9998,9999

R= 1,2,3,4,«.,15,16

DACCK (DAC Clock )

MCLK

GPIO

Divider

CPCK (Charge Pump Clock )

P= 1,2,«.,127,128

DDAC

(P0-R28)

Divider

DNCP (P0-R29)

OSRCK

(Oversampling

Ratio Clock )

Divider

MUX

DOSR

(P0-R30)

Divide

by 2

I16E (P0-R34)

Figure 63. TAS5754M Clock Distribution Tree

The Serial Audio Interface typically has 4 connection pins

1. MLCK (System Master Clock),

2. SLCK (Bit Clock)

3. LRCK/FS (Left Right Word Clock and Frame Sync)

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Feature Description (continued)

4. SDIN (note that this is the input data. The output date, SDOUT, is presented on one of the GPIO pins. See

Serial Data Output)

The device has an internal PLL that is used to take either MLCK or SLCK and create the higher rate clocks

required by the and the DAC clock.

In situations where the highest audio performance is required, it’s suggested that the MLCK is brought to the

device, along with SLCK and LRCK/FS. The device should be configured so that the PLL is only providing a

clock source to the DSP. All other clocks are then be a division of the incoming MLCK. This is done by setting

DAC CLK Source Mux (SDAC in the diagram above) to use MLCK as a source, rather than the output of the

MLCK/PLL Mux.

8.3.3 Serial Audio Port

8.3.3.1 Clock Master Mode from Audio Rate Master Clock

In Master Mode, the device generates bit clock and left-right and frame sync clock and outputs them on the

appropriate pins. To configure the device in this mode, first put the device into reset, then use registers SLCKO

and LRKO (P0-R9). Then reset the LRCK/FS and SCLK divider counters using bits RSLCK and RLRK (P0-R12).

Finally, exit reset.

Figure 64 shows a simplified serial port clock tree for the device in master mode.

Audio Related System Clock (MCLK)

MCLK

SCLKO (Bit Clock Output In Master Mode)

Divider

Q1 = 1...128

SCLK

LRCK/FS (LR Clock or Frame Sync Output In

Master Mode

Divider

LRCK/FS

Q1 = 1...128

Figure 64. Simplified Clock Tree for MLCK Sourced Master Mode

In master mode, MLCK is an input and SCLK and LRCK/FS are outputs. SCLK and LRCK/FS are integer

divisions of MLCK. Master mode with a non-audio rate master clock source will require external GPIO’s to use

the PLL in standalone mode. The PLL needs to be configured to ensure that the on-chip processor can be driven

at its maximum clock rate. This mode of operation is described in the Clock Master from a Non-Audio Rate

Master Clock section.

When used with Audio Rate Master Clocks, the register changes that need to be done include switching the

device into master mode, and setting the divider ratio. An example of this mode of operations is using 24.576

MCLK as a master clock source and driving the SCLK and LRCK/FS with integer dividers to create 48 kHz. In

this mode, the DAC section of the device is also running from the PLL output. The TAS5754M device is able to

meet the specified audio performance while using the internal PLL. However, using the MCLK CMOS oscillator

source will have less jitter than the PLL.

To switch the DAC clocks (SDAC in the Figure 63) the following registers should be modified

•

Clock Tree Flex Mode (P253-R63 and P253-R64)

DAC and OSR Source Clock Register (P0-R14). Set to 0x30 (MLCK input, and OSR is set to whatever the

DAC source is)

•

The DAC clock divider should be 16f_S.

–

16 × 48 kHz = 768 kHz

24.576 MHz (MLCK in) / 768 kHz = 32

Therefore, the divide ratio for register DDAC (P0-R28) should be set to 32. The register mapping gives

0x00 = 1, so 32 must be converter to 0x1F (31dec).

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Feature Description (continued)

8.3.3.2 Clock Master from a Non-Audio Rate Master Clock

The classic example here is running 12-MHz Master clock for a 48-kHz sampling system. Given the clock tree for

the device (shown in Figure 63), a non-audio clock rate cannot be brought into the MLCK to the PLL in master

mode. Therefore, the PLL source must be configured to be a GPIO pin, and the output brought back into another

GPIO pin.

Non-Audio MCLK

GPOIx

PLL

GPOIy

New

Audio

MCLK

Master Mode

SLCK Integer

Divider

SCLK

Out

SCLK

Master Mode

LRCK/FS

Integer Divider

LRCK/FS

Out

LRCK/FS

Figure 65. Generating Audio Clocks Using Non-Audio Clock Sources

The clock flow through the system is shown above. The newly generated MLCK must be brought out of the

device on a GPIO pin, then brought into the MLCK pin for integer division to create SCLK and LRCK/FS outputs.

NOTE

Pull-up resistors should be used on SCLK and LRCK/FS in this mode to ensure the device

remains out of sleep mode.

8.3.3.3 Clock Slave Mode with 4-Wire Operation (SCLK, MCLK, LRCK/FS, SDIN)

The TAS5754M device requires a system clock to operate the digital interpolation filters and advanced segment

DAC modulators. The system clock is applied at the MLCK input and supports up to 50 MHz. The TAS5754M

device system-clock detection circuit automatically senses the system-clock frequency. Common audio sampling

frequencies in the bands of 8 kHz, 16 kHz, (32 kHz - 44.1 kHz - 48kHz), (88.2 kHz - 96 kHz), and (176.4 kHz -

192 kHz) are supported.

NOTE

Values in the parentheses are grouped when detected, e.g. 88.2 kHz and 96 kHz are

detected as double rate, 32 kHz, 44.1 kHz and 48 kHz are detected as single rate, etc.

In the presence of a valid bit MCLK, SCLK and LRCK/FS, the device automatically configures the clock tree and

PLL to drive the miniDSP as required.

The sampling frequency detector sets the clock for the digital filter, Delta Sigma Modulator (DSM) and the

Negative Charge Pump (NCP) automatically. Table 2 shows examples of system clock frequencies for common

audio sampling rates.

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Feature Description (continued)

MLCK rates that are not common to standard audio clocks, between 1 MHz and 50 MHz, are supported by

configuring various PLL and clock-divider registers. This programmability allows the device to become a clock

master and drive the host serial port with LRCK/FS and SLCK, from a non-audio related clock (for example,

using a setting of 12 MHz to generate 44.1 kHz (LRCK/FS) and 2.8224 MHz (SLCK) ).

shows the timing requirements for the system clock input. For optimal performance, use a clock source with low

phase jitter and noise. For MCLK timing requirements, refer to the Serial Audio Port Timing – Master Mode

section.

Table 2. System Master Clock Inputs for Audio Related Clocks

SYSTEM CLOCK FREQUENCY (f_MLCK) (MHz)

SAMPLING

FREQUENCY

64 f_S

128 f_S

1.0240⁽²⁾

2.0480⁽²⁾

4.0960⁽²⁾

5.6488⁽²⁾

6.1440⁽²⁾

11.2896⁽²⁾

12.2880⁽²⁾

22.5792

192 f_S

256 f_S

2.0480

384 f_S

3.0720

512 f_S

4.0960

8 kHz

16 kHz

1.5360⁽²⁾

3.0720⁽²⁾

6.1440⁽²⁾

8.4672⁽²⁾

9.2160⁽²⁾

16.9344

18.4320

33.8688

36.8640

4.0960

6.1440

8.1920

32 kHz

8.1920

12.2880

16.9344

18.4320

33.8688

36.8640

16.3840

22.5792

24.5760

45.1584

49.1520

44.1 kHz

48 kHz

11.2896

12.2880

22.5792

24.5760

45.1584

49.1520

See note⁽¹⁾

88.2 kHz

96 kHz

176.4 kHz

192 kHz

See note⁽¹⁾

24.5760

(1) This system clock rate is not supported for the given sampling frequency.

(2) This system clock rate is supported by PLL mode.

8.3.3.4 Clock Slave Mode with SLCK PLL to Generate Internal Clocks (3-Wire PCM)

8.3.3.4.1 Clock Generation using the PLL

The TAS5754M device supports a wide range of options to generate the required clocks as shown in Figure 63.

The clocks for the PLL require a source reference clock. This clock is sourced as the incoming SLCK or MLCK, a

GPIO can also be used.

The source reference clock for the PLL reference clock is selected by programming the SRCREF value on P0-

R13, B[6:4]. The TAS5754M device provides several programmable clock dividers to achieve a variety of

sampling rates. See Figure 63.

If PLL functionality is not required, set the PLLEN value on P0-R4, B[0] to 0. In this situation, an external master

clock is required.

Table 3. PLL Configuration Registers

CLOCK MULTIPLEXER

FUNCTION

PLL Reference

FUNCTION

clock divider

BITS

SREF

DIVIDER

DDSP

P0-R13, B[6:4]

P0-R27, B[6:0]

P0-R32, B[6:0]

P0-R33, B[7:0]

DSLCK

DLRK

External SLCK Div

External LRCK/FS Div

8.3.3.4.2 PLL Calculation

The TAS5754M device has an on-chip PLL with fractional multiplication to generate the clock frequency needed

by the Digital Signal Processing blocks. The programmability of the PLL allows operation from a wide variety of

clocks that may be available in the system. The PLL input (PLLCKIN) supports clock frequencies from 1 MHz to

50 MHz and is register programmable to enable generation of required sampling rates with fine precision.

The PLL is enabled by default. The PLL can be enabled by writing to P0-R4, B[0]. When the PLL is enabled, the

PLL output clock PLLCK is given by Equation 1:

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PLLCKIN x R x J.D

P

PLLCKIN x R x K

P

PLLCK =

or PLLCK =

where

•

R = 1, 2, 3,4, ... , 15, 16

J = 4,5,6, . . . 63, and D = 0000, 0001, 0002, . . . 9999

K = [J value].[D value]

P = 1, 2, 3, ... 15

(1)

R, J, D, and P are programmable. J is the integer portion of K (the numbers to the left of the decimal point), while

D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of precision).

8.3.3.4.2.1 Examples:

•

If K = 8.5, then J = 8, D = 5000

If K = 7.12, then J = 7, D = 1200

If K = 14.03, then J = 14, D = 0300

If K = 6.0004, then J = 6, D = 0004

When the PLL is enabled and D = 0000, the following conditions must be satisfied:

•

1 MHz ≤ ( PLLCKIN / P ) ≤ 20 MHz

64 MHz ≤ (PLLCKIN x K x R / P ) ≤ 100 MHz

1 ≤ J ≤ 63

When the PLL is enabled and D ≠ 0000, the following conditions must be satisfied:

•

6.667 MHz ≤ PLLCLKIN / P ≤ 20 MHz

64 MHz ≤ (PLLCKIN x K x R / P ) ≤ 100 MHz

4 ≤ J ≤ 11

R = 1

When the PLL is enabled,

•

f_S= (PLLCLKIN × K × R) / (2048 × P)

The value of N is selected so that f_S× N = PLLCLKIN x K x R / P is in the allowable range.

Example: MCLK = 12 MHz and f_S= 44.1 kHz, (N=2048)

Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264

Example: MCLK = 12 MHz and f_S= 48.0 kHz, (N=2048)

Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920

Values are written to the registers in Table 4.

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Table 4. PLL Registers

DIVIDER

PLLE

FUNCTION

BITS

PLL enable

PLL P

P0-R4, B[0]

PPDV

PJDV

P0-R20, B[3:0]

P0-R21, B[5:0]

P0-R22, B[5:0]

P0-R23, B[7:0]

P0-R24, B[3:0]

PLL J

PDDV

PRDV

PLL D

PLL R

Table 5. PLL Configuration Recommendations

COLUMN

f_S(kHz)

DESCRIPTION

Sampling frequency

R_MLCK

Ratio between sampling frequency and MLCK frequency (MLCK frequency = RMLCK x sampling frequency)

System master clock frequency at MLCK input (pin 20)

MLCK (MHz)

PLL VCO (MHz) PLL VCO frequency as PLLCK in Figure 63

One of the PLL coefficients in Equation 1

PLL REF (MHz) Internal reference clock frequency which is produced by MLCK / P

P

M = K × R

K = J.D

R

The final PLL multiplication factor computed from K and R as described in Equation 1

One of the PLL coefficients in Equation 1

PLL f_S

DSP f_S

NMAC

Ratio between f_Sand PLL VCO frequency (PLL VCO / f_S)

Ratio between operating clock rate and f_S(PLL f_S/ NMAC)

The clock divider value in Table 3

DSP CLK (MHz) The operating frequency as DSPCK in Figure 63

MOD f_S

Ratio between DAC operating clock frequency and f_S(PLL f_S/ NDAC)

MOD f (kHz)

NDAC

DAC operating frequency as DACCK in

DAC clock divider value in Table 3

OSR clock divider value in Table 3 for generating OSRCK in Figure 63. DOSR must be chosen so that MOD f_S/ DOSR =

16 for correct operation.

DOSR

NCP

CP f

NCP (negative charge pump) clock divider value in Table 3

Negative charge pump clock frequency (f_S* MOD f_S/ NCP)

Percentage of error between PLL VCO / PLL f_Sand f_S(mismatch error).

% Error

•

This value is typically zero but can be non-zero especially when K is not an integer (D is not zero).

This value may be non-zero only when the TAS5754M device acts as a master.

The equations above explain how to calculate all necessary coefficients and controls to configure the PLL.

Table 6 provides for easy reference to the recommended clock divider settings for the PLL as a Master Clock.

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8.3.3.5 Serial Audio Port – Data Formats and Bit Depths

The serial audio interface port is a 3-wire serial port with the signals LRCK/FS (pin 25), SCLK (pin 23), and SDIN

(pin 24). SCLK is the serial audio bit clock, used to clock the serial data present on SDIN into the serial shift

register of the audio interface. Serial data is clocked into the TAS5754M device on the rising edge of SCLK.The

LRCK/FS pin is the serial audio left/right word clock or frame sync when the device is operated in TDM Mode.

Table 7. TAS5754M device Audio Data Formats, Bit Depths and Clock Rates

MAXIMUM LRCK/FS

FREQUENCY (kHz)

FORMAT

DATA BITS

MCLK RATE (f_S)

SCLK RATE (f_S)

I²S/LJ/RJ

32, 24, 20, 16

Up to 192

Up to 48

96

128 to 3072 (≤ 50 MHz)

128 to 3072

64, 48, 32

125, 256

128

TDM/DSP

32, 24, 20, 16

128 to 512

192

128, 192, 256

The TAS5754M device requires the synchronization of LRCK/FS and system clock, but does not need a specific

phase relation between LRCK/FS and system clock.

If the relationship between LRCK/FS and system clock changes more than ±5 MCLK, internal operation is

initialized within one sample period and analog outputs are forced to the bipolar zero level until re-

synchronization between LRCK/FS and system clock is completed.

If the relationship between LRCK/FS and SCLK are invalid more than 4 LRCK/FS periods, internal operation is

initialized within one sample period and analog outputs are forced to the bipolar zero level until re-

synchronization between LRCK/FS and SCLK is completed.

8.3.3.5.1 Data Formats and Master/Slave Modes of Operation

The TAS5754M device supports industry-standard audio data formats, including standard I²S and left-justified.

Data formats are selected via Register (P0-R40). All formats require binary two's complement, MSB-first audio

data; up to 32-bit audio data is accepted. The data formats are detailed in Figure 66 through Figure 71.

The TAS5754M device also supports right-justified and TDM/DSP data. I²S, LJ, RJ, and TDM/DSP are selected

using Register (P0-R40). All formats require binary 2s complement, MSB-first audio data. Up to 32 bits are

accepted. Default setting is I²S and 24 bit word length. The I²S slave timing is shown in .

shows a detailed timing diagram for the serial audio interface.

In addition to acting as a I²S slave, the TAS5754M device can act as an I²S master, by generating SCLK and

LRCK/FS as outputs from the MCLK input. Table 8 lists the registers used to place the device into Master or

Slave mode. Please refer to the Serial Audio Port Timing – Master Mode section for serial audio Interface timing

requirements in Master Mode. For Slave Mode timing, please refer to to the Serial Audio Port Timing – Slave

Mode section.

Table 8. I²S Master Mode Registers

REGISTER

FUNCTION

P0-R9-B0, B4, and B5

P0-R32-B[6:0]

I²S Master mode select

SCLK divider and LRCK/FS divider

P0-R33-B[7:0]

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1 t_{S .}

Right-channel

Left-channel

LRCK/FS

SLCK

«

Audio data word = 16-bit, SLCK = 32, 48, 64f_S

«

1

2

15 16

1

2

15 16

DATA

LSB

MSB

Audio data word = 24-bit, SLCK = 48, 64f_S

«

2

1

2

24

2

23 24

DATA

LSB

MSB

Audio data word = 32-bit, SLCK = 64f_S

«

1

2

31 32

1

2

31 32

DATA

MSB

LSB

MSB

LSB

Figure 66. Left Justified Audio Data Format

1 t_{S .}

LRCK/FS

SLCK

Left-channel

Right-channel

«

Audio data word = 16-bit, SLCK = 32, 48, 64f_S

«

1

2

15 16

1

2

15 16

DATA

LSB

MSB

Audio data word = 24-bit, SLCK = 48, 64f_S

«

2

23 24

1

23 24

DATA

LSB

MSB

LSB

MSB

Audio data word = 32-bit, SLCK = 64f_S

«

1

2

31 32

1

2

31 32

DATA

MSB

LSB

MSB

LSB

I²S Data Format; L-channel = LOW, R-channel = HIGH

Figure 67. I²S Audio Data Format

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1 /f_{S .}

Right-channel

Left-channel

LRCK/FS

«

SLCK

Audio data word = 16-bit, SLCK = 32, 48, 64f_S

DATA

«

1

2

15 16

1

2

15 16

LSB

MSB

Audio data word = 24-bit, SLCK = 48, 64f_S

«

2

1

2

24

1

2

23 24

DATA

MSB

LSB

MSB

LSB

Audio data word = 32-bit, SLCK = 64f_S

«

1

2

31 32

1

2

31 32

DATA

MSB

LSB

MSB

LSB

Right Justified Data Format; L-channel = HIGH, R-channel = LOW

Figure 68. Right Justified Audio Data Format

1 /f_{S .}

LRCK/FS

SLCK

«

Audio data word = 16-bit, Offset = 0

«

1

2

15 16

1

2

15 16

1

DATA

Data Slot 1

Data Slot 2

LSB

MSB

LSB

MSB

Audio data word = 24-bit, Offset = 0

-

,

«

1

2

23 24

1

2

23 24

LSB

DATA

Data Slot 1

LSB

MSB

Audio data word = 32-bit, Offset = 0

«

1

2

31 32

LSB

1

2

31 32

LSB

DATA

MSB

TDM/DSP Data Format with OFFSET = 0

Figure 69. TDM/DSP 1 Audio Data Format

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NOTE

In TDM Modes, Duty Cycle of LRCK/FS should be 1x SCLK at minimum. Rising edge is

considered frame start.

1 /f_{S .}

OFFSET = 1

LRCK/FS

SLCK

«

Audio data word = 16-bit, Offset = 1

«

1

2

15 16

1

2

15 16

1

DATA

Data Slot 1

LSB

Data Slot 2

LSB

MSB

Audio data word = 24-bit, Offset = 1

«

1

2

23 24

1

2

23 24

LSB

DATA

Data Slot 1

Data Slot 2

LSB

MSB

Audio data word = 32-bit, Offset = 1

«

1

2

31 32

LSB

1

2

31 32

DATA

Data Slot 1

Data Slot 2

LSB

MSB

TDM/DSP Data Format with OFFSET = 1

Figure 70. TDM/DSP 2 Audio Data Format

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1 /f_{S .}

OFFSET = n

LRCK/FS

SLCK

«

Audio data word = 16-bit, Offset = n

«

1

2

15 16

1

2

15 16

DATA

Data Slot 1

LSB

Data Slot 2

LSB

MSB

Audio data word = 24-bit, Offset = n

«

1

2

23 24

1

2

23 24

LSB

DATA

Data Slot 1

Data Slot 2

LSB

MSB

Audio data word = 32-bit, Offset = n

«

1

2

31 32

LSB

1

2

31 32

LSB

DATA

Data Slot 1

Data Slot 2

MSB

TDM/DSP Data Format with OFFSET = N

Figure 71. TDM/DSP 3 Audio Data Format

8.3.3.6 Input Signal Sensing (Power-Save Mode)

The TAS5754M device has a zero-detect function. This function can be applied to both channels of data as an

AND function or an OR function, via controls provided in the control port in P0-R65-B[2:1].Continuous Zero data

cycles are counted by LRCK/FS, and the threshold of decision for analog mute can be set by P0-R59, B[6:4] for

the data which is clocked in on the left frame of an I²S signal or Slot 1 of a TDM signal and P0-R59, B[2:0] for

the data which is clocked in on the right frame of an I²S signal or Slot 2 of a TDM signal as shown in Table 10.

Default values are 0 for both channels.

Table 9. Zero Detection Mode

ATMUTECTL

VALUE

FUNCTION

Zero data triggers for the two channels for zero detection are

OR'ed together.

0

Bit : 2

Zero data triggers for the two channels for zero detection are

AND'ed together.

1 (Default)

0

Zero detection and analog mute are disabled for the data

clocked in on the right frame of an I²S signal or Slot 2 of a

TDM signal.

Bit : 1

Bit : 0

Zero detection analog mute are enabled for the data clocked in

on the right frame of an I²S signal or Slot 2 of a TDM signal.

1 (Default)

0

Zero detection analog mute are disabled for the data clocked

in on the left frame of an I²S signal or Slot 1 of a TDM signal.

Zero detection analog mute are enabled for the data clocked in

on the left frame of an I²S signal or Slot 1 of a TDM signal.

1 (Default)

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Table 10. Zero Data Detection Time

ATMUTETIML OR

NUMBER OF

LRCK/FS CYCLES

TIME @ 48kHz

ATMA

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

1024

5120

21 ms

106 ms

10240

25600

51200

102400

256000

512000

213 ms

533 ms

1.066 sec

2.133 sec

5.333 sec

10.66 sec

8.3.3.7 Serial Data Output

If it is supported by the HybridFlow in use, the TAS5754M device can present serial data on one of the three

available hardware pins, GPIO0, GPIO1, or GPIO2. In a HybridFlow which supports serial data out, the serial

data out origin can always be configured to come before the mini-DSP, by clearing the SDSL bit in P0-R7. This

feature is used as a loop-back to check the integrity of the data transmission from the source to the TAS5754M

device . In addition to the default loop-back mode, HybridFlows allows the SDOUT signal to originate from either

a point after the processing or from some intermediary point within the HybridFlow. This option is accomplished

by setting the SDSL bit in P0-R7. Figure 72 shows how to configure the origin of the serial data output signal.

MiniDSP

Audio

Processing

Serial Audio Input

To Speaker Amplifier

Mux

To GPIO Configuration to

be presented on GPIO pins

Mux

SDSL

(P0-R7)

This mux, if present, is

unique to each HybridFlow

and has unique controls

Figure 72. Serial Data Output Signal

Choosing the origin to be after all processing has been applied to the signal (i.e. before it is sent to the amplifier)

is popular for sending a monitor signal back to a voice processing or echo-cancelling device elsewhere in the

system. Other origins may configure the signal to originate after a subwoofer generation block, which sums in the

inputs and applies a low-pass filter to create a mono, low-frequency signal. Please refer to the target

HybridFlows for details regarding the options for the serial data output.

8.3.4 miniDSP Audio Processing Engine

The TAS5754M device integrates a highly efficient processing engine called a miniDSP. The miniDSP in the

TAS5754M device uses a Hybrid architecture in which some processing blocks are built in ROM and other

processing blocks are created in RAM via the PurePath™ Control Console GUI. This approach allows the

flexibility of a fully-programmable device to be combined with the ease of use and rapid download time of a hard-

coded ROM device.

8.3.4.1 HybridFlow Architecture

The Hybrid RAM and ROM Architecture allows the device to be highly flexible, but also easy to use. Unlike a

device where all digital processing blocks are hard-coded in ROM, the hybrid RAM and ROM architecture allows

a variety of processing blocks to be used in various combinations with various connectivity. These combinations

of processing blocks are called HybridFlows.

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HybridFlows are generated by combining a collection of processing blocks together in a targeted manner so that

the device is well suited for a particular application or use case. Some HybridFlows are targeted for stereo

applications, while others are targeted for mono, 1.1 (Bi-Amped), or 2.1 configurations.

It is important to note that the amount of processing which can be combined together into a given process flow is

highly dependent on the sample rate of the audio signal which is being processed. For instance, an audio signal

at 48 kHz can have much more processing applied than the same signal presented to the TAS5754M device at

192 kHz sample rate. For this reason, a HybridFlow which supports only up to 48 kHz sample rate cannot be

used with a 192 kHz input signal.

8.3.4.2 Volume Control

8.3.4.2.1 Digital Volume Control

A basic digital volume control with range between 24 dB and 103 dB and mute is available on each channels by

P0-R61-B[7:0] for SPK_OUTB± and P0-R62-B[7:0] for SPK_OUTA±. These volume controls all have 0.5 dB step

programmability over most gain and attenuation ranges. Table 11 lists the detailed gain versus programmed

setting for this basic volume control. Volume can be changed for both SPK_OUTB± and SPK_OUTA± at the

same time or independently by P0-R61-B[1:0] . When B[1:0] set 00 (default), independent control is selected.

When B[1:0] set 01, SPK_OUTA± accords with SPK_OUTB± volume. When B[1:0] set 10, SPK_OUTA± volume

controls the volume for both channels. To set B[1:0] to 11 is prohibited.

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Table 11. Digital Volume Control Settings

GAIN

SETTING

GAIN

(dB)

BINARY DATA

COMMENTS

0

1

0000-0000

0000-0001

24.0

23.5

Positive maximum

.

46

47

48

49

50

51

0010-1110

0010-1111

0011-0000

0011-0001

0011-0010

0011-0011

1.0

0.5

0.0

No attenuation (default)

–0.5

–1.0

–1.5

.

253

254

255

1111-1101

1111-1110

1111-1111

–102.5

–103

Negative maximum

–

Negative infinite (Mute)

Ramp-up frequency and ramp-down frequency can be controlled by P0-R63, B[7:6] and B[3:2] as shown in

Table 12. Also ramp-up step and ramp-down step can be controlled by P0-R63, B[5:4] and B[1:0] as shown in

Table 13.

Table 12. Ramp Up or Down Frequency

RAMP UP

SPEED

RAMP DOWN

FREQUENCY

EVERY N f_S

COMMENTS

EVERY N f_S

COMMENTS

00

01

10

11

1

Default

00

01

10

11

1

Default

2

4

Direct change

Table 13. Ramp Up or Down Step

RAMP UP

STEP

RAMP DOWN

COMMENTS

STEP dB

COMMENTS

STEP

00

01

10

11

4.0

2.0

1.0

0.5

00

01

–4.0

–2.0

–1.0

–0.5

Default

10

11

Default

8.3.4.2.1.1 Emergency Volume Ramp Down

Emergency ramp down of the volume by is provided for situations such as I²S clock error and power supply

failure. Ramp-down speed is controlled by P0-R64-B[7:6]. Ramp-down step can be controlled by P0-R64-B[5:4].

Default is ramp-down by every f_Scycle with –4dB step.

8.3.5 Adjustable Amplifier Gain and Switching Frequency Selection

The voltage divider between the GVDD_REG pin a the SPK_GAIN/FREQ pin is used to set the gain and

switching frequency of the amplifier. The voltage presented on the SPK_GAIN/FREQ pin is digitized and then

decoded into a 3 bit word which is interpreted inside the TAS5754M device to correspond to a given gain and

switching frequency.

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Because the amplifier adds gain to both the signal and the noise present in the audio signal, the lowest gain

setting that can meet voltage-limited output power targets should be used. This ensures that the power target

can be reached while minimizing the idle channel noise of the system. The switching frequency selection affects

three important operating characteristics of the device. These are the power dissipation in the device, the power

dissipation in the inductor, and the target output filter for the application.

Higher switching frequencies typically result in slightly higher power dissipation in the TAS5754M device and

lower dissipation in the inductor in the system, due to decreased ripple current through the inductor and

increased charging and discharging current in device and parasitic capacitances. Switching at the higher of the

two available switching frequencies will result in lower overall dissipation in the system and lower operating

temperature of the inductors. However, the thermally limited power output of the device may be decreased in this

situation, because some of the TAS5754M device thermal headroom will be absorbed by the higher switching

frequency. Conversely inductor heating can be reduced by using the higher switching frequency in order to

reduce the ripple current.

Another advantage of increasing the switching frequency is that the higher frequency carrier signal can be filtered

by an L-C filter with a higher corner frequency, leading to physically smaller components. Use the highest

switching frequency that continues to meet the thermally limited power targets for the application. If thermal

constraints require heat reduction in the TAS5754M device, use a lower switching rate.

The switching frequency of the speaker amplifier is dependent on an internal synchronizing signal, (f_SYNC), which

is synchronous with the sample rate. The rate of the synchronizing signal is also dependent on the sample rate.

Refer to Table 14 below for details regarding how the sample rates correlate to the synchronizing signal.

Table 14. Sample Rates vs Synchronization Signal

SAMPLE RATE

[kHz]

f_SYNC

[kHz]

8

16

32

96

48

96

192

11.025

22.05

44.1

88.2

Table 15 summarizes the de-code of the voltage presented to the SPK_GAIN/FREQ pin.

Table 15. Amplifier Switching Mode vs.

SPK_GAIN/FREQ Voltage

V_{SPK_GAIN/FREQ}(V)

AMPLIFIER

SWITCHING

FREQUENCY MODE

GAIN MODE

MIN

MAX

6.61

5.44

4.67

3.89

3.11

2.33

1.56

0.78

0

7

Reserved

8 × f_SYNC

6 × f_SYNC

4 × f_SYNC

2 × f_SYNC

8 × f_SYNC

6 × f_SYNC

4 × f_SYNC

2 × f_SYNC

6.6

5.43

4.66

3.88

3.1

26dBV

20dBV

2.32

1.55

0.77

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8.3.6 Error Handling and Protection Suite

8.3.6.1 Device Over-Temperature Protection

The TAS5754M device continuously monitors die temperature to ensure it does to exceed the OTE_THRESlevel

specified in the Recommended Operating Conditions table. If an OTE event occurs, the SPK_FAULT line is

pulled low and out the SPK_OUTxx outputs transition to high impedance, signifying a fault. This latched error

requires the SPK_MUTE line to toggle in order to reset the error. Alternatively, pulling the MCLK, SCLK, or

LRCK/FS pin low causes a clock error, which also resets the device. Normal operation resumes by re-starting the

stopped clock.

8.3.6.2 SPK_OUTxx Over-Current Protection

The TAS5754M device continuously monitors the output current of each amplifier output to ensure it does to

exceed the OCE_THRESlevel specified in the Recommended Operating Conditions table. If an OCE event occurs,

the SPK_FAULT line is pulled low and the SPK_OUTxx outputs transition to high impedance, signifying a fault.

This latched error requires the SPK_MUTE line to toggle in order to reset the error. Alternatively, pulling the

MCLK, SCLK, or LRCK/FS pin low causes a clock error, which also resets the device. Normal operation resumes

by re-starting the stopped clock.

8.3.6.3 DC Offset Protection

If the TAS5754M device measures a DC offset in the output voltage, the SPK_FAULT line is pulled low and the

SPK_OUTxx outputs transition to high impedance, signifying a fault. This latched error require the SPK_MUTE

line to toggle in order to reset the error. Alternatively, pulling the MCLK, SCLK, or LRCK low causes a clock

error, which also resets the device. Normal operation resumes by re-starting the stopped clock.

8.3.6.4 Internal V_AVDDUndervoltage-Error Protection

The TAS5754M device internally monitors the AVDD net to protect against the AVDD supply dropping

unexpectedly. To enable this feature, P1-R5-B0 is used.

8.3.6.5 Internal V_PVDDUndervoltage-Error Protection

If the voltage presented on the PVDD supply drops below the UVE_THRES(PVDD)value listed in the Recommended

Operating Conditions table, the SPK_OUTxx outputs transition to high impedance. This is a self-clearing error,

which means that once the PVDD level drops below the level listed in the Recommended Operating Conditions

table, the device resumes normal operation.

8.3.6.6 Internal V_PVDDOvervoltage-Error Protection

If the voltage presented on the PVDD supply exceeds the OVE_THRES(PVDD)value listed in the Recommended

Operating Conditions table, the SPK_OUTxx outputs will transition to high impedance. This is a self-clearing

error, which means that once the PVDD level drops below the level listed in the Recommended Operating

Conditions table, the device will resume normal operation. It is important to note that this voltage only protects up

to the level described in the Recommended Operating Conditions table for the PVDD voltage. Exceeding this

absolute maximum rating causes damage and possible device failure, because the levels exceed that which can

be protected against by the OVE protection circuit.

8.3.6.7 External Undervoltage-Error Protection

The SPK_MUTE pin can also be used to monitor a system voltage, such as a LCD TV backlight, a battery pack

in portable device, by using a voltage divider created with two resistors. (See Figure 73)

•

If the SPK_MUTE pin makes a transition from “1” to “0” over 6 ms or more, the device switches into external

under-voltage protection mode. This mode uses two trigger levels.

•

When the SPK_MUTE pin level reaches 2 V, soft mute process begins.

When the SPK_MUTE pin level reaches 1.2 V, analog output mute engages, regardless of digital audio level,

and analog output shutdown begins.

A timing diagram to show this is shown in Figure 74.

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NOTE

The SPK_MUTE input pin voltage range is provided in the Recommended Operating

Conditions table. The ratio of external resistors must produce a voltage within this input

range. Any increase in power supply (such as power supply positive noise or ripple) can

pull the SPK_MUTE pin higher than that the level specified in the Recommended

Operating Conditions table, potentially causing damage to or failure of the device.

Therefore, it is imperative that any monitored voltage (including all ripple, power supply

variation, resistor divider variation, transient spikes, etc.) is scaled by the resistor divider

network to never drive the voltage on the SPK_MUTE pin higher than the maximum level

specified in the Recommended Operating Conditions table.

When the divider is set correctly, any DC voltage can be monitored. shows a 12-V example of how the

SPK_MUTE is used for external undervoltage error protection.

V_DD

12 V

7.25 Nꢀ

SPK_MUTE

2.75 Nꢀ

Figure 73. SPK_MUTE Used in External Undervoltage Error Protection

Digital attenuation followed by analog mute

Analog mute

SPK_MUTE

0.9 × DV

DD

2.0 V

1.2 V

0.1 × DV

DD

t

f

Figure 74. SPK_MUTE Timing for External Undervoltage Error Protection

8.3.6.8 Internal Clock Error Notification (CLKE)

8.3.7 GPIO Port and Hardware Control Pins

The TAS5754M device includes a versatile GPIO port, allowing signals to be passed from the system to the

device or sent out of the device to the system. There are three GPIO pins available for use. These pins can be

used for advanced clocking features, to pass internal signals to the system or accept signals from the system for

use inside the device by a HybridFlow, or simply to monitor the status of an external signal via I²C. The GPIO

port requires some configuration in the control port. This configuration is detailed in Figure 75.

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Internal Data

(P0-R82)

GPIOx Output Enable

P0-R8

GPIOx Output Inversion

P0-R87

GPIOx Output Selection

P0-R82

Off (low)

DSP GPIOx output

Register GPIOx output (P0-R86)

Auto mute flag (Both A and B)

Auto mute flag (Channel B)

Auto mute flag (Channel A)

Clock invalid flag

Mux

GPIOx

Mux

Serial Audio Data Output

Analog mute flag for B

Analog mute flag for A

PLL lock flag

Charge Pump Clock

GPIOx Input State

Under voltage flag 1

Under voltage flag 2

Monitoring

(P0-R119)

PLL output/4

To MiniDSP

To Clock Tree

Figure 75. GPIO Port

In addition to the dynamic controls which can be implemented with the GPIO port, each HybridFlow uses the

GPIO port as required. In some HybridFlows, a GPIO is used to present an internal serial audio data signal to a

system controller. In others, the status of a GPIO pin is monitored and the status of that pin is used to adjust the

audio processing applied to the signal. Refer to each HybridFlow for specifics regarding how the GPIO port is

used. GPIOs which have been allocated to a function in a HybridFlow can be reassigned using the same controls

as those listed in Figure 75. However, they no longer serve the purpose intended by the design of the

HybridFlow.

8.3.8 I²C Communication Port

The TAS5754M device supports the I²C serial bus and the data transmission protocol for standard and fast mode

as a slave device.

8.3.8.1 Slave Address

Table 16. I²C Slave Address

MSB

1

LSB

0

1

ADR2

ADR1

R/ W

The TAS5754M device has 7 bits for its own slave address. The first five bits (MSBs) of the slave address are

factory preset to 10011 (0x9x). The next two bits of the address byte are the device select bits which can be

user-defined by the ADR1 and ADR0 terminals. A maximum of four devices can be connected on the same bus

at one time. This gives a range of 0x98, 0x9A, 0x9C and 0x9E, as detailed below. Each TAS5754M device

responds when it receives its own slave address.

Table 17. I²C Address Configuration via ADR0 and ADR1 Pins

ADR1

ADR0

I²C SLAVE ADDRESS [R/W]

0

1

0

1

0

1

0x99/0x98

0x9B/0x9A

0x9D/0x9C

0x9F/0x9E

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8.3.8.2 Register Address Auto-Increment Mode

MSB

LSB

A0

INC

A6

A5

A4

A3

A2

A1

Figure 76. Auto Increment Mode

Auto-increment mode allows multiple sequential register locations to be written to or read back in a single

operation, and is especially useful for block write and read operations.

8.3.8.3 Packet Protocol

A master device must control packet protocol, which consists of start condition, slave address, read/write bit,

data if write or acknowledge if read, and stop condition. The TAS5754M device supports only slave receivers and

slave transmitters.

SDA

SCL

9

1–7

8

9

1–8

9

1–8

9

Sp

St

Slave address

R/W

ACK

DATA

ACK

DATA

ACK

Start

condition

Stop

condition

R/W: Read operation if 1; otherwise, write operation

ACK: Acknowledgement of a byte if 0

DATA: 8 bits (byte)

Figure 77. Packet Protocol

Table 18. Write Operation - Basic I²C Framework

Transmitter

Data Type

M

S

M

S

M

S

M

St

slave address

R/

ACK

DATA

ACK

DATA

ACK

Sp

Table 19. Read Operation - Basic I²C Framework

Transmitter

Data Type

M

S

M

S

M

St

slave address

R/

ACK

DATA

ACK

DATA

ACK

NACK

Sp

M = Master Device; S = Slave Device; St = Start Condition Sp = Stop Condition

8.3.8.4 Write Register

A master can write to any TAS5754M device registers using single or multiple accesses. The master sends a

TAS5754M device slave address with a write bit, a register address with auto-increment bit, and the data. If auto-

increment is enabled, the address is that of the starting register, followed by the data to be transferred. When the

data is received properly, the index register is incremented by 1 automatically. When the index register reaches

0x7F, the next value is 0x0. Table 20 shows the write operation.

Table 20. Write Operation

Transmitter

Data Type

M

S

M

S

M

S

M

S

M

reg

addr

write

data 1

write

data 2

St

slave addr

W

ACK

inc

ACK

Sp

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M = Master Device; S = Slave Device; St = Start Condition Sp = Stop Condition; W = Write; ACK = Acknowledge

8.3.8.5 Read Register

A master can read the TAS5754M device register. The value of the register address is stored in an indirect index

register in advance. The master sends a TAS5754M device slave address with a read bit after storing the

register address. Then the TAS5754M device transfers the data which the index register points to. When auto-

increment is enabled, the index register is incremented by 1 automatically. When the index register reaches

0x7F, the next value is 0x0. Table 21 shows the read operation.

Table 21. Read Operation

Transmitter

Data Type

M

S

M

S

M

S

M

slave

addr

reg

addr

slave

addr

St

W

ACK

inc

ACK

Sr

R

ACK

data

ACK

NACK

Sp

M = Master Device; S = Slave Device; St = Start Condition; Sr = Repeated start condition; Sp = Stop Condition;

W = Write; R = Read; NACK = Not acknowledge

8.3.9 Device Functional Modes

Because the TAS5754M device is a highly configurable device, numerous modes of operation can exist for the

device. For the sake of succinct documentation, these modes are divided into two modes:

•

Fundamental operating modes

Secondary usage modes

Fundamental operating modes are the primary modes of operation that affect the major operational

characteristics of the device. These are the most basic configurations that are chosen to ensure compatibility

with the intended application or the other components that interact with the device in the final system. Some

examples of these are the communication protocol used by the control port, the output configuration of the

amplifier, or the Master/Slave clocking configuration.

The fundamental operating modes are described starting in the Serial Audio Port Operating Modes section.

Secondary usage modes are best described as modes of operation that are used after the fundamental operating

modes are chosen to fine tune how the device operates within a given system. These secondary usage modes

may include selecting between left justified and right justified Serial Audio Port data formats, or enabling some

slight gain/attenuation within the DAC path. Secondary usage modes are accomplished through manipulation of

the registers and controls in the I²C control port. Those modes of operation are described in their respective

register/bit descriptions and, to avoid redundancy, are not included in this section.

8.3.9.1 Serial Audio Port Operating Modes

The serial audio port in the TAS5754M device supports industry-standard audio data formats, including I²S, Time

Division Multiplexing (TDM), Left-Justified (LJ), and Right-Justified (RJ) formats. To select the data format that

will be used with the device, controls are provided on P0-R40. The timing diagrams for the serial audio port are

shown in the Serial Audio Port Timing – Slave Mode section, and the data formats are shown in the Serial Audio

Port – Data Formats and Bit Depths section.

8.3.9.2 Communication Port Operating Modes

The TAS5754M device is configured via an I²C communication port. The device does not support a hardware

only mode of operation, nor Serial Peripheral Interface (SPI) communication. The I²C Communication Protocol is

detailed in the I²C Communication Port section. The I²C timing requirements are described in the I²C Bus

Timing – Standard and I²C Bus Timing – Fast sections.

8.3.9.3 Audio Processing Modes via HybridFlow Audio Processing

The TAS5754M device can be configured to include several different audio processing features through the use

of pre-defined DSP loads called HybridFlows. These HybridFlows have been created and tested to be application

focused. This approach results in a device which offers the flexibility of a programmable device with the ease-of-

use and fast download time of a fixed function device. The HybridFlows are selected and downloaded using the

PurePath™ ControlConsole software. .

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8.3.9.4 Speaker Amplifier Operating Modes

The TAS5754M device can be used in three different amplifier configurations:

•

Stereo Mode

Mono Mode

Bi-Amp Mode

8.3.9.4.1 Stereo Mode

The familiar stereo mode of operation uses the TAS5754M device to amplify two independent signals, which

represent the left and right portions of a stereo signal. These amplified left and right audio signals are presented

on differential output pairs shown as SPK_OUTA± and SPK_OUTB±. The routing of the audio data which is

presented on the SPK_OUTxx outputs can be changed according to the HybridFlow which is used and the

configuration of registers P0-R42-B[5:4] and P0-R42-B[1:0]. This mode of operation is shown in Figure 80.

By default, the TAS5754M device is configured to output the Right frame of a I²S input on the Channel A output

and the left frame on the Channel B output.

8.3.9.4.2 Mono Mode

This mode of operation is used to describe operation in which the two outputs of the device are placed in parallel

with one another to increase the power sourcing capabilities of the device.

On the output side of the TAS5754M device, the summation of the devices can be done before the filter in a

configuration called Pre-Filter Parallel Bridge Tied Load (PBTL). However, it is sometimes preferable to merge

the two outputs together after the inductor portion of the output filter. Doing so does require two additional

inductors, but allows smaller, less expensive inductors to be used because the current is divided between the

two inductors. This is called Post-Filter PBTL. Both variants of mono operation are shown in Figure 78 and

Figure 79.

L_FILT

SPK_OUTA+

C_FILT

SPK_OUTA-

L_FILT

SPK_OUTA-

C_FILT

SPK_OUTB+

C_FILT

L_FILT

SPK_OUTB-

C_FILT

SPK_OUTB+

L_FILT

SPK_OUTB-

C_FILT

Figure 78. Pre-Filter PBTL

Figure 79. Post-Filter PBTL

On the input side of the TAS5754M device, the input signal to the mono amplifier can be selected from the any

slot in a TDM stream or the left or right frame from an I²S, LJ, or RJ signal. It can also be configured to amplify

some mixture of two signals, as in the case of a subwoofer channel which mixes the left and right channel

together and sends it through a low-pass filter in order to create a mono, low-frequency signal.

This mode of operation is shown in the Mono (PBTL) Systems section.

8.3.9.4.3 Bi-Amp Mode

Bi-Amp mode, sometimes also referred to as 1.1 Mode uses a two channel device (such as the TAS5754M

device ) to amplify two different frequency regions of the same signal for a two-way speaker. This is most often

used in a single active speaker, where one channel of the amplifier is use to drive the high frequency transducer

and one channel is used to drive the low-frequency transducer. To operate in Bi-Amped Mode or 1.1 Mode, an

appropriate HybridFlow must be chosen, because the frequency separation and audio processing must occur in

the DSP. This mode of operation is shown in the 1.1 (Dual BTL, Bi-Amped) Systems section.

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8.3.9.4.4 Master and Slave Mode Clocking for Digital Serial Audio Port

The digital audio serial port in the TAS5754M device can be configured to receive its clocks from another device

as a serial audio slave device. This mode of operation is described in the Clock Slave Mode with SLCK PLL to

Generate Internal Clocks (3-Wire PCM) section. If there no system processor available to provide the audio

clocks, the TAS5754M device can be placed into Master Mode. In this mode, the TAS5754M device provides the

clocks to the other audio devices in the system. For more details regarding the Master and Slave mode operation

within the TAS5754M device, please refer to Serial Audio Port Operating Modes.

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8.4 Register Maps

8.4.1 Control Port Registers- Quick Reference

Register Quick Reference ~ Page 0

Default (Binary)

Adr.

(Dec) (Hex)

Adr.

Register

Name

Default

(Hex)

B7

B6

B5

B4

RSTM

0

B3

B2

B1

B0

RSTR

0

Reserved Reserved Reserved

1

2

3

4

1

2

3

4

P0-R1

P0-R2

P0-R3

P0-R4

0

Reserved Reserved Reserved

RQST

0

Reserved Reserved Reserved

RQPD

0

1

0

Reserved Reserved Reserved

RQMB

0

Reserved Reserved Reserved

RQMA

0

Reserved Reserved Reserved

PLCK

0

Reserved Reserved Reserved

PLLE

1

0

5

6

5

6

P0-R5

P0-R6

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

Reserved Reserved Reserved

DEMP

Reserved Reserved Reserved

SDSL

0

7

8

9

7

8

9

P0-R7

P0-R8

P0-R9

0

G2OE

0

G0OE

0

G1OE

0

Reserved Reserved

INTMUTE

Reserved Reserved

0

SCLKO

0

Reserved Reserved

SCLKP

0

Reserved Reserved Reserved LRCKFSO

0

10

11

A

B

P0-R10

P0-R11

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

Reserved Reserved Reserved Reserved Reserved Reserved

RSCLK

0

RLRCKFS

0

12

13

C

D

P0-R12

P0-R13

P0-R14

7C

0

1

0

1

SREF

0

1

0

1

Reserved

Reserved Reserved Reserved Reserved

0

Reserved

0

SDAC

0

Reserved Reserved Reserved Reserved

14

15

E

F

0

P0-R15

...

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

... ...

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

...

17

18

H

P0-R17

Reserved Reserved Reserved Reserved Reserved

GREF

0

12

P0-R18

P0-R19

P0-R20

P0-R21

P0-R22

P0-R23

P0-R24

0

10

0

RQSY

0

Reserved Reserved Reserved Reserved Reserved Reserved Reserved

19

20

21

22

23

24

13

14

15

16

17

18

0

1

0

Reserved Reserved Reserved Reserved

PPDV

0

PJDV

0

Reserved Reserved Reserved

0

Reserved Reserved

PDDV (MSB)

0

PDDV (LSB)

0

–

0

–

0

–

0

–

PRDV

0

Reserved Reserved Reserved Reserved

25

26

19

1A

P0-R25

P0-R26

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

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Register Maps (continued)

Register Quick Reference ~ Page 0 (continued)

Default (Binary)

Adr.

(Dec) (Hex)

Adr.

Register

Name

Default

(Hex)

B7

B6

0

B5

0

B4

0

B3

DDSP

0

B2

0

B1

0

B0

0

Reserved

27

28

29

1B

1C

1D

P0-R27

P0-R28

P0-R29

0

Reserved

DDAC

0

Reserved

DNCP

0

Reserved

0

DOSR

0

30

31

32

1E

1F

20

P0-R30

P0-R31

P0-R32

0

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

DSCLK

0

DLRCKFS

33

34

35

36

37

21

22

23

24

25

P0-R33

P0-R34

P0-R35

P0-R36

P0-R37

0

1

0

Reserved

0

FSSP

I16E

0

Reserved Reserved Reserved Reserved

0

IDAC (MSB)

0

1

IDAC (LSB)

0

IPLK

0

DCAS

0

IDCM

0

IDCH

0

IDSK

0

IDBK

0

IDFS

0

Reserved

–

38

39

26

27

P0-R38

P0-R39

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

Reserved Reserved

AFMT

Reserved Reserved

ALEN

40

41

42

43

44

28

29

2A

2B

2C

P0-R40

P0-R41

P0-R42

P0-R43

P0-R44

2

0

1

0

1

0

1

0

AOFS

AUPB

0

Reserved

0

Reserved Reserved Reserved

AUPA

11

1

0

Reserved Reserved Reserved Reserved

PSEL

0

CMDP

0

Reserved Reserved Reserved Reserved Reserved

0

45

...

2D

...

P0-R45

...

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

... ...

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

58

3A

P0-R58

Reserved

0

AMTB

0

Reserved

0

AMTA

0

59

60

61

62

3B

3C

3D

3E

P0-R59

P0-R60

P0-R61

P0-R62

0

Reserved Reserved Reserved Reserved Reserved Reserved

PCTL

0

1

0

1

0

VOLB

VOLA

30

62

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Register Maps (continued)

Register Quick Reference ~ Page 0 (continued)

Default (Binary)

Adr.

(Dec) (Hex)

Adr.

Register

Name

Default

(Hex)

B7

0

B6

0

B5

1

B4

0

B3

B2

B1

B0

VNDF

VEDF

VNDS

VEDS

VNUF

VNUS

63

64

65

3F

40

41

P0-R63

P0-R64

P0-R65

22

0

1

0

Reserved Reserved Reserved Reserved

2

4

0

ACTL

1

AMLE

0

AMRE

0

Reserved Reserved Reserved Reserved Reserved

0

66

...

42

...

P0-R66

...

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

... ...

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

81

51

P0-R81

Reserved Reserved Reserved

G1SL

0

82

52

P0-R82

0

Reserved Reserved Reserved

G0SL

0

83

84

85

53

54

55

P0-R83

P0-R84

P0-R85

0

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

Reserved Reserved Reserved

G2SL

0

GOUT2

0

GOUT0

0

GOUT1

0

Reserved Reserved

Reserved

Reserved Reserved

86

87

56

57

P0-R86

P0-R87

0

Reserved

0

Reserved Reserved

GINV2

0

GINV0

0

GINV1

0

Reserved Reserved

0

88

89

58

59

P0-R88

P0-R89

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

Reserved Reserved Reserved

B1OV

0

A1OV

0

B2OV

0

A2OV

0

SFOV

0

90

91

92

93

94

95

5A

5B

5C

5D

5E

5F

P0-R90

P0-R91

P0-R92

P0-R93

P0-R94

P0-R95

0

38

0

Reserved

0

DTFS

1

DTSR

0

1

0

Reserved Reserved Reserved Reserved Reserved Reserved

DTBR

0

DTBR

Reserved Reserved Reserved Reserved Reserved Reserved Reserved

40

0

Reserved

0

1

CDST6

0

CDST5

0

CDST4

0

CDST2

0

CDST1

0

CDST0

0

CDST3

0

Reserved

0

Reserved Reserved Reserved

LTSH

0

CKMF

0

CSRF

0

CERF

0

96

...

60

...

P0-R96

...

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

... ...

107

6B

PO-R107 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

Reserved Reserved Reserved Reserved Reserved Reserved

AMBM

1

AMAM

108

109

6C

6D

P0-R108

P0-R109

33

0

1

SDTM

0

1

SHTM

0

Reserved Reserved Reserved

0

110

...

6E

...

PO-R110 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

... ... ...

PO-R113 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

113

71

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Register Maps (continued)

Register Quick Reference ~ Page 0 (continued)

Default (Binary)

Adr.

(Dec) (Hex)

Adr.

Register

Name

Default

(Hex)

B7

B6

B5

B4

B3

B2

B1

1

B0

1

Reserved Reserved Reserved Reserved Reserved Reserved

MTST

FSMM

114

115

72

73

P0-R114

P0-R115

3

0

Reserved Reserved Reserved Reserved Reserved Reserved

0

116

117

74

75

P0-R116 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

P0-R117 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

BOTM

1

Reserved Reserved Reserved

PSTM

118

119

120

121

122

76

77

78

79

7A

P0-R118

P0-R119

P0-R120

P0-R121

P0-R122

85

2D

0

1

0

1

Reserved Reserved

GPIN

0

1

0

AMFB

0

1

AMFA

0

Reserved Reserved Reserved

0

Reserved Reserved Reserved Reserved Reserved Reserved Reserved

DAMD

0

Reserved Reserved Reserved Reserved Reserved Reserved Reserved

EIFM

0

Register Quick Reference ~ Page 1

Default (Binary)

Adr.

(Dec) (Hex)

Adr.

Register

Name

Default

(Hex)

B7

B6

B5

B4

B3

B2

B1

B0

Reserved Reserved Reserved Reserved Reserved Reserved Reserved

OSEL

1

2

1

2

P1-R1

P1-R2

0

BAGN

0

AAGN

0

Reserved Reserved Reserved

0

Reserv

ed

3

4

3

4

P1-R3

P1-R4

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

Reserv

ed

Reserved Reserved Reserved Reserved Reserved Reserved

UEPD

0

UIPD

5

6

7

8

9

5

6

7

8

9

P1-R5

P1-R6

P1-R7

P1-R8

P1-R9

11

0

1

0

1

AMCT

0

Reserved Reserved Reserved Reserved Reserved Reserved Reserved

0

AGBB

0

Reserved Reserved Reserved

AGBA

0

Reserved Reserved Reserved Reserved Reserved Reserved Reserved

RCMF

0

Reserved Reserved Reserved Reserved Reserved Reserved Reserved

VCPD

0

64

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Register Quick Reference ~ Page 44

Default (Binary)

Adr.

(Dec) (Hex)

Adr.

Register

Name

Default

(Hex)

B7

B6

B5

B4

B3

ACRM

0

B2

AMDC

0

B1

ACRS

0

B0

ASCW

0

Reserved Reserved Reserved Reserved

1

P44-R1

0

Register Quick Reference ~ Page 253

Default (Binary)

Adr.

(Dec) (Hex)

Adr.

Register

Name

Default

(Hex)

B7

0

B6

0

B5

0

B4

B3

B2

0

B1

0

B0

0

PLLFLEX1

63

64

3F

40

P253-63

P253-64

0

PLLFLEX2

0

8.4.2 Control Port Registers- Detailed Description

8.4.2.1 P0-R1

Reset Modules [4] (R/W)

00000000

This bit resets the interpolation filter and the DAC modules. Since the DSP is also reset, the coefficient RAM content will also be cleared by

the DSP. This bit is auto cleared and can be set only in standby mode.

Normal

- - - 0 - - - -

- - - 1 - - - -

Reset modules

Reset Register [0] (R/W)

00000000

This bit resets the mode registers back to their initial values. The RAM content is not cleared, but the execution source will be back to ROM.

This bit is auto cleared and must be set only when the DAC is in standby mode (resetting registers when the DAC is running is prohibited

and not supported).

Normal

- - - - - - - 0

- - - - - - - 1

Reset mode registers

8.4.2.2 P0-R2

Standby Request [4] (R/W)

00000000

When this bit is set, the DAC will be forced into a system standby mode, which is also the mode the system enters in the case of clock

errors. In this mode, most subsystems will be powered down but the charge pump and digital power supply.

Normal operation

Standby mode

- - - 0 - - - -

- - - 1 - - - -

00000000

Powerdown Request [0] (R/W)

When this bit is set, the DAC will be forced into powerdown mode, in which the power consumption would be minimum as the charge pump

is also powered down. However, it will take longer to restart from this mode. This mode has higher precedence than the standby mode, i.e.

setting this bit along with bit 4 for standby mode will result in the DAC going into powerdown mode.

Normal operation

Powerdown mode

- - - - - - - 0

- - - - - - - 1

8.4.2.3 P0-R3

Mute Channel B [4] (R/W)

00000000

This bit issues soft mute request for the Channel B. The volume will be smoothly ramped down/up to avoid pop/click noise.

Normal volume

Mute

- - - 0 - - - -

- - - 1 - - - -

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Mute Channel A [0] (R/W)

00000000

This bit issues soft mute request for the Channel A. The volume will be smoothly ramped down/up to avoid pop/click noise.

Normal volume

Mute

- - - - - - - 0

- - - - - - - 1

8.4.2.4 P0-R4

PLL Lock Flag [4] (Read Only)

00000001

This bit indicates whether the PLL is locked or not. When the PLL is disabled this bit always shows that the PLL is not locked.

The PLL is locked

- - - 0 - - - -

- - - 1 - - - -

00000001

The PLL is not locked

PLL Enable [0] (R/W)

This bit enables or disables the internal PLL. When PLL is disabled, the master clock is switched to the MCLK.

Disable PLL

Enable PLL

- - - - - - - 0

- - - - - - - 1

8.4.2.5 P0-R7

De-Emphasis Enable [4] (R/W)

00000000

This bit enables or disables the de-emphasis filter. The default coefficients are for 44.1 kHz sampling rate, but can be changed by

reprogramming the appropriate coeffients via the coefficient spaces provided in each HybridFlow.

De-emphasis filter is disabled

De-emphasis filter is enabled

- - - 0 - - - -

- - - 1 - - - -

SDOUT Select [0] (R/W)

00000000

This bit selects what is being output as SDOUT via GPIO pins.

SDOUT is the DSP output (post-processing)⁽¹⁾

SDOUT is the DSP input (pre-processing)

- - - - - - - 0

- - - - - - - 1

(1) Some HybridFlows offer several paths from which to take the SDOUT signal. In this case, this bit should be cleared, and the appropirate

mixer/mux function in the HybridFlow should be used to determine which processed signal should be presented as the SDOUT signal.

8.4.2.6 P0-R8

GPIO2 Output Enable [5] (R/W)

GPIO0 Output Enable [3] (R/W)

GPIO1 Output Enable [2] (R/W)

00000000

This bit sets the direction of the GPIO2 pin

GPIO2 is input

- - - 0 - - - - -

- - - 1 - - - - -

00000000

GPIO2 is output

This bit sets the direction of the GPIO0 pin

GPIO0 is input

- - - - - 0 - - -

- - - - - 1 - - -

00000000

GPIO0 is output

This bit sets the direction of the GPIO1 pin

GPIO1 is input

- - - - - 0 - -

- - - - - 1 - -

GPIO1 is output

8.4.2.7 P0-R9

SCLK Polarity [5] (R/W)

00000000

This bit sets the inverted SCLK mode. In inverted SCLK mode, the DAC assumes that the LRCK/FS and SDIN edges are aligned to the

rising edge of the SCLK. Normally they are assumed to be aligned to the falling edge of the SCLK.

Normal SCLK mode

Inverted SCLK mode

- - - 0 - - - - -

- - - 1 - - - - -

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SCLK Output Enable [4] (R/W)

00000000

This bit sets the SCLK pin direction to output for I2S master mode operation. In I²S master mode the TAS5754M outputs the reference

SCLK and LRCK/FS, and the external source device provides the SDIN according to these clocks. Use P0-R32 to program the division

factor of the MCLK to yield the desired SCLK rate (normally 64F_S)

SCLK is input (I²S slave mode)

SCLK is output (I²S master mode)

- - - 0 - - - -

- - - 1 - - - -

00000000

LRCK/FS Output Enable [0] (R/W)

This bit sets the LRCK/FS pin direction to output for I2S master mode operation. In I2S master mode the PCM51xx outputs the reference

SCLK and LRCK/FS, and the external source device provides the SDIN according to these clocks. Use P0/R33 to program the division

factor of the SCLK to yield 1F_Sfor LRCK/FS.

LRCK/FS is input (I²S slave mode)

LRCK/FS is output (I²S master mode)

- - - - - - - 0

- - - - - - - 1

8.4.2.8 P0-R12

Master Mode SCLK Divider Reset [1] (R/W)

01111100

This bit, when set to 0, will reset the MCLK divider to generate SCLK clock for I2S master mode. To use I2S master mode, the divider must

be enabled and programmed properly.

Master mode SCLK clock divider is reset

- - - - - - - 0 -

- - - - - - - 1 -

01111100

Master mode SCLK clock divider is functional

Master Mode LRCK/FS Divider Reset [0] (R/W)

This bit, when set to 0, will reset the SCLK divider to generate LRCK/FS clock for I2S master mode. To use I2S master mode, the divider

must be enabled and programmed properly.

Master mode LRCK/FS clock divider is reset

- - - - - - - 0

- - - - - - - 1

Master mode LRCK/FS clock divider is functional

8.4.2.9 P0-R13

PLL Reference [6:4] (R/W)

00000000

This bit select the source clock for internal PLL. This bit is ignored and overriden in clock auto set mode.

The PLL reference clock is MCLK

Reserved

- 0 0 0 - - - -

- 0 0 1- - - -

- 1 0 0 - - - -

- 1 1 1 - - - -

The PLL reference clock is GPIO (selected using P0-R18)

8.4.2.10 P0-R14

DAC Clock Source [6:4] (R/W)

00000000

These bits select the source clock for DAC clock divider.

Master clock (PLL/MCLK and OSC auto-select)

PLL clock

- 0 0 0 - - - -

- 0 0 1- - - -

- 0 1 0 - - - -

- 0 1 1 - - - -

- 1 0 0 - - - -

Reserved

MCLK clock

SCLK clock others:

Others: reserved (muted)

8.4.2.11 P0-R18

GPIO Source for PLL Reference clock [2:0] (R/W)

00000000

These bits select the GPIO pins as clock input source when GPIO is selected as the PLL reference clock source.

Reserved

- - - - - 0 0 0

- - - - - 0 0 1

- - - - - 0 1 0

Reserved

GPIO1 functions as clock input source

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GPIO Source for PLL Reference clock [2:0] (R/W)

00000000

GPIO0 functions as clock input source

Reserved

- - - - - 0 1 1

- - - - - 1 0 0

- - - - - 1 0 1

GPIO2 functions as clock input source

Others: reserved (muted)

8.4.2.12 P0-R19

Synchronization Request [0] (R/W)

00010000

This bit, when set to 1 will issue the clock resynchronization by synchronously resets the DAC, CP and OSR clocks. The actual clock

resynchronization takes place when this bit is set back to 0, where the DAC, CP and OSR clocks are resumed at the beginning of the audio

frame.

Resume DAC, CP and OSR clocks synchronized to the beginning of audio frame

Halt DAC, CP and OSR clocks as the beginning of re-synchronization process

- - - - - - - 0

- - - - - - - 1

8.4.2.13 P0-R20

PLL Divider P-Factor [3:0] (R/W)

These bits set the PLL divider P factor. These bits are ignored in clock auto set mode.

Sets the PLL divider P factor to P=1

00000000

- - - - 0 0 0 0

- - - - 0 0 0 1

- - - - 0 0 1 0

...

Sets the PLL divider P factor to P=2

Sets the PLL divider P factor to P=3

...

Sets the PLL divider P factor to P=13

- - - - 1 1 0 0

- - - - 1 1 0 1

- - - - 1 1 1 0

- - - - 1 1 1 1

Sets the PLL divider P factor to P=14

Sets the PLL divider P factor to P=15

Prohibited (do not set this value)

8.4.2.14 P0-R21

PLL Divider J-Factor [4:0] (R/W)

These bits set the J part of the overall PLL multiplication factor J.D * R. These bits are ignored in clock auto set mode.

Prohibited (do not set this value)

00000000

- - - 0 0 0 0 0

- - - 0 0 0 0 1

- - - 0 0 0 1 0

- - - 0 0 0 1 1

...

Sets the J part if the overall PLL multiplication factor J.D * R to J = 1

Sets the J part if the overall PLL multiplication factor J.D * R to J = 2

Sets the J part if the overall PLL multiplication factor J.D * R to J = 3

...

Sets the J part if the overall PLL multiplication factor J.D * R to J = 61

Sets the J part if the overall PLL multiplication factor J.D * R to J = 62

Sets the J part if the overall PLL multiplication factor J.D * R to J = 63

- - - 1 1 1 0 1

- - - 1 1 1 1 0

- - - 1 1 1 1 1

8.4.2.15 P0-R22

PLL Divider D-Factor (Most Significant Bit) [5:0] (Least Significant Bit) [7:0] (R/W)

These bits set the D part of the overall PLL multiplication factor J.D * R. These bits are ignored in clock auto set mode.

Sets the D part if the overall PLL multiplication factor J.D * R to D = 0000

Sets the D part if the overall PLL multiplication factor J.D * R to D = 0001

Sets the D part if the overall PLL multiplication factor J.D * R to D = 0010

...

Decimal

0

1

2

...

Sets the D part if the overall PLL multiplication factor J.D * R to D = 9997

Sets the D part if the overall PLL multiplication factor J.D * R to D = 9998

Sets the D part if the overall PLL multiplication factor J.D * R to D = 9999

9997

9998

9999

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8.4.2.16 P0-R24

PLL Divider R-Factor [3:0] (R/W)

00000000

These bits set the R part of the overall PLL multiplication factor J.D * R. These bits are ignored in clock auto set mode.

Sets the R part if the overall PLL multiplication factor J.D * R to R = 1

Sets the R part if the overall PLL multiplication factor J.D * R to R = 2

Sets the R part if the overall PLL multiplication factor J.D * R to R = 3

...

- - - - 0 0 0 0

- - - - 0 0 0 1

- - - - 0 0 1 0

...

Sets the R part if the overall PLL multiplication factor J.D * R to R = 14

Sets the R part if the overall PLL multiplication factor J.D * R to R = 15

Sets the R part if the overall PLL multiplication factor J.D * R to R = 16

- - - - 1 1 0 1

- - - - 1 1 1 0

- - - - 1 1 1 1

8.4.2.17 P0-R27

DSP Clock Divider [6:0] (R/W)

These bits set the source clock divider value for the DSP clock. These bits are ignored in clock auto set mode.

These bits set the source clock divider value for the DSP clock. Divide by 1

These bits set the source clock divider value for the DSP clock. Divide by 2

These bits set the source clock divider value for the DSP clock. Divide by 3

...

00000000

- 0 0 0 0 0 0 0

- 0 0 0 0 0 0 1

- 0 0 0 0 0 1 0

...

These bits set the source clock divider value for the DSP clock. Divide by 126

These bits set the source clock divider value for the DSP clock. Divide by 127

These bits set the source clock divider value for the DSP clock. Divide by 128

- 1 1 1 1 1 0 1

- 1 1 1 1 1 1 0

- 1 1 1 1 1 1 1

8.4.2.18 P0-R28

DAC Clock Divider [6:0] (R/W)

These bits set the source clock divider value for the DAC clock. These bits are ignored in clock auto set mode.

These bits set the source clock divider value for the DAC clock. Divide by 1

These bits set the source clock divider value for the DAC clock. Divide by 2

These bits set the source clock divider value for the DAC clock. Divide by 3

...

00000000

- 0 0 0 0 0 0 0

- 0 0 0 0 0 0 1

- 0 0 0 0 0 1 0

...

These bits set the source clock divider value for the DAC clock. Divide by 126

These bits set the source clock divider value for the DAC clock. Divide by 127

These bits set the source clock divider value for the DAC clock. Divide by 128

- 1 1 1 1 1 0 1

- 1 1 1 1 1 1 0

- 1 1 1 1 1 1 1

8.4.2.19 P0-R29

NCP Clock Divider [6:0] (R/W)

These bits set the source clock divider value for the CP clock. These bits are ignored in clock auto set mode.

These bits set the source clock divider value for the NCP clock. Divide by 1

These bits set the source clock divider value for the NCP clock. Divide by 2

These bits set the source clock divider value for the NCP clock. Divide by 3

...

00000000

- 0 0 0 0 0 0 0

- 0 0 0 0 0 0 1

- 0 0 0 0 0 1 0

...

These bits set the source clock divider value for the NCP clock. Divide by 126

These bits set the source clock divider value for the NCP clock. Divide by 127

These bits set the source clock divider value for the NCP clock. Divide by 128

- 1 1 1 1 1 0 1

- 1 1 1 1 1 1 0

- 1 1 1 1 1 1 1

8.4.2.20 P0-R30

OSR Clock Divider [6:0] (R/W)

00000000

These bits set the source clock divider value for the OSR clock. These bits are ignored in clock auto set mode.

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OSR Clock Divider [6:0] (R/W)

00000000

These bits set the source clock divider value for the OSR clock. Divide by 1

These bits set the source clock divider value for the OSR clock. Divide by 2

These bits set the source clock divider value for the OSR clock. Divide by 3

...

- 0 0 0 0 0 0 0

- 0 0 0 0 0 0 1

- 0 0 0 0 0 1 0

...

These bits set the source clock divider value for the OSR clock. Divide by 126

These bits set the source clock divider value for the OSR clock. Divide by 127

These bits set the source clock divider value for the OSR clock. Divide by 128

- 1 1 1 1 1 0 1

- 1 1 1 1 1 1 0

- 1 1 1 1 1 1 1

8.4.2.21 P0-R32

Master Mode SCLK Divider [6:0] (R/W)

These bits set the MCLK divider value to generate I2S master SCLK clock.

These bits set the source clock divider value for the SCLK clock. Divide by 1

These bits set the source clock divider value for the SCLK clock. Divide by 2

These bits set the source clock divider value for the SCLK clock. Divide by 3

...

00000000

- 0 0 0 0 0 0 0

- 0 0 0 0 0 0 1

- 0 0 0 0 0 1 0

...

These bits set the source clock divider value for the SCLK clock. Divide by 126

These bits set the source clock divider value for the SCLK clock. Divide by 127

These bits set the source clock divider value for the SCLK clock Divide by 128

- 1 1 1 1 1 0 1

- 1 1 1 1 1 1 0

- 1 1 1 1 1 1 1

8.4.2.22 P0-R33

Master Mode LRCK/FS Divider [7:0] (R/W)

These bits set the I2S master SCLK clock divider value to generate I2S master LRCK/FS clock.

These bits set the source clock divider value for the LRCK/FS clock. Divide by 1

These bits set the source clock divider value for the LRCK/FS clock. Divide by 2

These bits set the source clock divider value for the LRCK/FS clock. Divide by 3

...

00000000

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 1

0 0 0 0 0 0 1 0

...

These bits set the source clock divider value for the LRCK/FS clock. Divide by 254

These bits set the source clock divider value for the LRCK/FS clock. Divide by 255

These bits set the source clock divider value for the LRCK/FS clock. Divide by 256

1 1 1 1 1 1 0 1

1 1 1 1 1 1 1 0

1 1 1 1 1 1 1 1

8.4.2.23 P0-R34

16x Interpolation [4] (R/W)

This bit enables or disables the 16x interpolation mode

8x interpolation

00000000

- - - 0 - - - -

- - - 1 - - - -

000000000

16x interpolation

Switching Frequency Speed Mode [1:0] (R/W)

These bits select the F_Soperation mode, which must be set according to the current audio sampling rate. These bits are ignored in clock

auto set mode.

Single speed (f_SW≤ 48 kHz)

- - - - - - 0 0

- - - - - - 0 1

- - - - - - 1 0

Double speed (48 kHz ≤ f_SW≤ 96 kHz)

Quad speed (96 kHz ≤ f_SW≤ 192 kHz)

8.4.2.24 P0-R35

Available DSP Clock Cycles (MSB) [7:0] (R/W)

00000001

These bits specify the number of DSP clock cycles available in one audio frame. The value should match the DSP clock F_Sratio. These bits

are ignored in clock auto set mode.

DSP clock:F_Sratio = x

0 0 0 0 0 0 0 0

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Available DSP Clock Cycles (MSB) [7:0] (R/W)

00000001

0 0 0 0 0 0 0 1

0 0 0 0 0 0 1 0

...

DSP clock:F_Sratio = x

...

DSP clock:F_Sratio = x

1 1 1 1 1 1 0 1

1 1 1 1 1 1 1 0

1 1 1 1 1 1 1 1

8.4.2.25 P0-R36

Available DSP Clock Cycles (LSB) [7:0] (R/W)

00000000

These bits specify the number of DSP clock cycles available in one audio frame. The value should match the DSP clock F_Sratio. These bits

are ignored in clock auto set mode.

DSP clock:F_Sratio = x

...

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 1

0 0 0 0 0 0 1 0

...

DSP clock:F_Sratio = x

1 1 1 1 1 1 0 1

1 1 1 1 1 1 1 0

1 1 1 1 1 1 1 1

8.4.2.26 P0-R37

Ignore F_SDetection [6] (R/W)

00000000

This bit controls whether to ignore the F_Sdetection. When ignored, F_Serror will not cause a clock error.

Regard F_Sdetection

- 0 - - - - - -

- 1 - - - - - -

00000000

Ignore F_Sdetection

Ignore SCLK Detection [5] (R/W)

This bit controls whether to ignore the SCLK detection against LRCK/FS. The SCLK must be stable between 32F_Sand 256F_Sinclusive or

an error will be reported. When ignored, a SCLK error will not cause a clock error.

Regard SCLK detection

Ignore SCLK detection

- - 1 - - - - -

- - 0 - - - - -

00000000

Ignore MCLK Detection [4] (R/W)

This bit controls whether to ignore the MCLK detection against LRCK/FS. Only some certain MCLK ratios within some error margin are

allowed. When ignored, an MCLK error will not cause a clock error.

Regard MCLK detection

Ignore MCLK detection

- - - 0 - - - -

- - - 1 - - - -

00000000

Ignore Clock Halt Detection [3] (R/W)

This bit controls whether to ignore the MCLK halt (static or frequency is lower than acceptable) detection. When ignored an MCLK halt will

not cause a clock error.

Regard MCLK halt detection

Ignore MCLK halt detection

- - - - - - 0 -

- - - - - - 1 -

00000000

Ignore LRCK/FS and SCLK Missing Detection [2] (R/W)

This bit controls whether to ignore the LRCK/FS and SCLK missing detection. The LRCK/FS and SCLK need to be in low state (not only

static) to be deemed missing. When ignored an LRCK/FS and SCLK missing will not cause the DAC go into powerdown mode.

Regard LRCK/FS and SCLK missing detection

Ignore LRCK/FS and SCLK missing detection

- - - - - 0 - -

- - - - - 1 - -

00000000

Disable Clock Divider Autoset [1] (R/W)

This bit enables or disables the clock auto set mode. When dealing with uncommon audio clock configuration, the auto set mode must be

disabled and all clock dividers must be set manually. Addtionally, some clock detectors might also need to be disabled. The clock autoset

feature will not work with PLL enabled in VCOM mode. In this case this feature has to be disabled and the clock dividers must be set

manually.

Enable clock auto set

- - - - - - 0 -

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Disable Clock Divider Autoset [1] (R/W)

Ignore PLL Lock Detection [0] (R/W)

00000000

Disable clock auto set

- - - - -- 1 -

00000000

This bit controls whether to ignore the PLL lock detection. When ignored, PLL unlocks will not cause a clock error. The PLL lock flag at P0-

R4, bit 4 is always correct regardless of this bit.

PLL unlocks raise clock error

PLL unlocks are ignored

- - - - - - - 0

- - - - - - - 1

8.4.2.27 P0-R40

I²S Data Format [5:4] (R/W)

00000010

These bits control both input and output audio interface formats for DAC operation.

Input and output audio interface formats for DAC operation is I²S

- - 0 0 - - - -

- - 0 1 - - - -

- - 1 0 - - - -

- - 1 1 - - - -

000000010

Input and output audio interface formats for DAC operation is TDM/DSP

Input and output audio interface formats for DAC operation is RTJ

Input and output audio interface formats for DAC operation is LTJ

I²S Word Length [1:0] (R/W)

These bits control both input and output audio interface sample word lengths for DAC operation.

Input and output audio interface sample word length for DAC operation is 16 bits

Input and output audio interface sample word length for DAC operation is 20 bits

Input and output audio interface sample word length for DAC operation is 24 bits

Input and output audio interface sample word length for DAC operation is 32 bits

- - - - - - 0 0

- - - - - - 0 1

- - - - - - 1 0

- - - - - - 1 1

8.4.2.28 P0-R41

I²S Shift [7:0] (R/W)

00000000

These bits control the offset of audio data in the audio frame for both input and output. The offset is defined as the number of SCLK from

the starting (MSB) of audio frame to the starting of the desired audio sample.

Offset (number of SCLK from the starting (MSB) of audio frame to the starting of the desired audio sample) is 0 SCLK

(no offset)

0 0 0 0 0 0 0 0

Offset is 1 SCLK

Offset is 2 SCLKs

...

0 0 0 0 0 0 0 1

0 0 0 0 0 0 1 0

...

Offset is 254 SCLKs

Offset is 255 SCLKs

Offset is 256 SCLKs

1 1 1 1 1 1 0 1

1 1 1 1 1 1 1 0

1 1 1 1 1 1 1 1

8.4.2.29 P0-R42

Channel B DAC Data Path [5:4] (R/W)

00000001

These bits control the Channel B audio data path connection.

Zero data (mute)

Channel B data

- - 0 0 - - - -

- - 0 1 - - - -

- - 1 0 - - - -

- - 1 1 - - - -

000000001

Channel A data

Reserved (do not set)

Channel A DAC Data Path [1:0] (R/W)

These bits control the Channel A audio data path connection.

Zero data (mute)

Channel A data

- - - - - - 0 0

- - - - - - 0 1

- - - - - - 1 0

- - - - - - 1 1

Channel B data

Reserved (do not set)

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8.4.2.30 P0-R43

DSP Program Selection [4:0] (R/W)

00000001

These bits select the DSP program to use for audio processing.

Reserved (do not set)

- - - 0 0 0 0 0

- - - 0 0 0 0 1

- - - 0 0 0 1 0

- - - 0 0 0 1 1

- - - 0 0 1 0 0

- - - 0 0 1 0 1

- - - 0 0 1 1 0

- - - 0 0 1 1 1

...

8x, 4x, or 2x FIR interpolation filter with de-emphasis

8x, 4x, or 2x Low latency IIR interpolation filter with de-emphasis

16x FIR interpolation filter with de-emphasis

16x Low latency IIR interpolation filter with de-emphasis

Fixed process flow with configurable parameters

Reserved (do not set)

8× Ringing-less low latency FIR interpolation filter without de-emphasis

Others: Reserved (do not set)

User program in RAM

- - - 1 1 1 1 1

8.4.2.31 P0-R44

Clock Missing Detection Period [2:0] (R/W)

00000000

These bits set how long both SCLK and LRCK/FS keep low before the audio clocks deemed missing and the DAC transitions to powerdown

mode.

Period that SCLK and LRCK/FS are keep low before the audio clock is deemed missing and the DAC transitions to

powerdown mode is approximately 1 second

- - - - - 0 0 0

Period that SCLK and LRCK/FS are keep low before the audio clock is deemed missing and the DAC transitions to

powerdown mode is approximately 2 seconds

- - - - - 0 0 1

...

Period that SCLK and LRCK/FS are keep low before the audio clock is deemed missing and the DAC transitions to

powerdown mode is approximately 7 seconds

- - - - - 1 1 0

Period that SCLK and LRCK/FS are keep low before the audio clock is deemed missing and the DAC transitions to

powerdown mode is approximately 8 seconds

- - - - - 1 1 1

8.4.2.32 P0-R59

Auto Mute Time for Channel B [6:4] (R/W)

00000000

These bits specify the length of consecutive zero samples at Channel B before the channel can be auto muted. The times shown are for 48

kHz sampling rate and will scale with other rates.

Length of consecutive zero samples before the channel can be auto muted is 21 ms

Length of consecutive zero samples before the channel can be auto muted is 106 ms

Length of consecutive zero samples before the channel can be auto muted is 213 ms

Length of consecutive zero samples before the channel can be auto muted is 533 ms

Length of consecutive zero samples before the channel can be auto muted is 1.07 seconds

Length of consecutive zero samples before the channel can be auto muted is 2.13 seconds

Length of consecutive zero samples before the channel can be auto muted is 5.33 seconds

Length of consecutive zero samples before the channel can be auto muted is 10.66 seconds

Auto Mute Time for Channel A [2:0] (R/W)

- 0 0 0 - - - -

- 0 0 1- - - -

- 0 1 0 - - - -

- 0 1 1 - - - -

- 1 0 0 - - - -

- 1 0 1 - - - -

- 1 1 0 - - - -

- 1 1 1 - - - -

00000000

These bits specify the length of consecutive zero samples at Channel A before the channel can be auto muted. The times shown are for 48

kHz sampling rate and will scale with other rates.

Length of consecutive zero samples before the channel can be auto muted is 21 ms

Length of consecutive zero samples before the channel can be auto muted is 106 ms

Length of consecutive zero samples before the channel can be auto muted is 213 ms

Length of consecutive zero samples before the channel can be auto muted is 533 ms

Length of consecutive zero samples before the channel can be auto muted is 1.07 seconds

Length of consecutive zero samples before the channel can be auto muted is 2.13 seconds

Length of consecutive zero samples before the channel can be auto muted is 5.33 seconds

- - - - - 0 0 0

- - - - - 0 0 1

- - - - - 0 1 0

- - - - - 0 1 1

- - - - - 1 0 0

- - - - - 1 0 1

- - - - - 1 1 0

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Auto Mute Time for Channel A [2:0] (R/W)

00000000

Length of consecutive zero samples before the channel can be auto muted is 10.66 seconds

- - - - - 1 1 1

8.4.2.33 P0-R60

Digital Volume Control [1:0] (R/W)

These bits control the behavior of the digital volume.

The volume for Channels A and B are independent

Channel A volume follows Channel B setting

000000000

- - - - - - 0 0

- - - - - - 0 1

- - - - - - 1 0

- - - - - - 1 1

Channel B volume follows Channel A setting

Reserved (The volume for Channels A and B are independent)

8.4.2.34 P0-R61

Channel B Digital Volume [7:0] (R/W)

00110000

These bits control the Channel B digital volume. The digital volume is 24 dB to -103 dB in -0.5 dB step.

Channel B digital volume is 24 dB

Channel B digital volume is 23.5 dB

Channel B digital volume is 23 dB.

...

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 1

0 0 0 0 0 0 1 0

...

Channel B digital volume is 0.5 dB

Channel B digital volume is 0 dB

Channel B digital volume is –0.5 dB

...

0 0 1 0 0 0 0 0

0 0 1 1 0 0 0 0

0 0 1 1 0 0 0 1

...

Channel B digital volume is –102.5 dB

Channel B digital volume is –103 dB

Reserved

1 1 1 1 1 1 0 1

1 1 1 1 1 1 1 0

1 1 1 1 1 1 1 1

8.4.2.35 P0-R62

Channel A Digital Volume [7:0] (R/W)

00110000

These bits control the Channel A digital volume. The digital volume is 24 dB to -103 dB in -0.5 dB step.

Channel A digital volume is 24 dB

Channel A digital volume is 23.5 dB

Channel A digital volume is 23 dB.

...

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 1

0 0 0 0 0 0 1 0

...

Channel A digital volume is 0.5 dB

Channel A digital volume is 0 dB

Channel A digital volume is –0.5 dB

...

0 0 1 0 0 0 0 0

0 0 1 1 0 0 0 0

0 0 1 1 0 0 0 1

...

Channel A digital volume is –102.5 dB

Channel A digital volume is –103 dB

Reserved

1 1 1 1 1 1 0 1

1 1 1 1 1 1 1 0

1 1 1 1 1 1 1 1

8.4.2.36 P0-R63

Digital Volume Normal Ramp-Down Frequency [7:6] (R/W)

00100010

These bits control the frequency of the digital volume updates when the volume is ramping down. The setting here is applied to soft mute

request, asserted by SPK_MUTE pin or P0-R3.

The frequency of the digital volume updates is every 1 F_Speriod

The frequency of the digital volume updates is every 2 F_Speriod

The frequency of the digital volume updates is every 4 F_Speriod

0 0 - - - - - -

0 1 - - - - - -

1 0 - - - - - -

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Digital Volume Normal Ramp-Down Frequency [7:6] (R/W)

Directly sets the volume to zero (Instant mute)

Digital Volume Normal Ramp Down Step [5:4] (R/W)

00100010

1 1 - - - - - -

00100010

These bits control the step of the digital volume updates when the volume is ramping down. The setting here is applied to soft mute

request, asserted by SPK_MUTE pin or P0-R3.

Decrement by 4 dB for each update

Decrement by 2 dB for each update

Decrement by 1 dB for each update

Decrement by 0.5 dB for each update

- - 0 0 - - - -

- - 0 1 - - - -

- - 1 0 - - - -

- - 1 1 - - - -

00100010

Digital Volume Normal Ramp-Up Frequency [3:2] (R/W)

These bits control the frequency of the digital volume updates when the volume is ramping up. The setting here is applied to soft unmute

request, asserted by SPK_MUTE pin or P0-R3.

The frequency of the digital volume updates is every 1 F_Speriod

The frequency of the digital volume updates is every 2 F_Speriod

The frequency of the digital volume updates is every 4 F_Speriod

Directly sets the volume to zero (Instant unmute)

- - - - 0 0 - -

- - - - 0 1 - -

- - - - 1 0 - -

- - - - 1 1 - -

001000010

Digital Volume Normal Ramp Up Step [1:0] (R/W)

These bits control the step of the digital volume updates when the volume is ramping up. The setting here is applied to soft unmute request,

asserted by SPK_MUTE pin or P0-R3.

Increment by 4 dB for each update

Increment by 2 dB for each update

Increment by 1 dB for each update

Increment by 0.5 dB for each update

- - - - - - 0 0

- - - - - - 0 1

- - - - - - 1 0

- - - - - - 1 1

8.4.2.37 P0-R64

Digital Volume Emergency Ramp Down Frequency [7:6] (R/W)

00000010

These bits control the frequency of the digital volume updates when the volume is ramping down due to clock error or power outage, which

usually needs faster ramp down compared to normal soft mute.

The frequency of the digital volume updates is every 1 F_Speriod

The frequency of the digital volume updates is every 2 F_Speriod

The frequency of the digital volume updates is every 4 F_Speriod

Directly sets the volume to zero (Instant mute)

0 0 - - - - - -

0 1 - - - - - -

1 0 - - - - - -

1 1 - - - - - -

00000010

Digital Volume Emergency Ramp Down Step [5:4] (R/W)

These bits control the step of the digital volume updates when the volume is ramping down due to clock error or power outage, which

usually needs faster ramp down compared to normal soft mute.

Decrement by 4 dB for each update

Decrement by 2 dB for each update

Decrement by 1 dB for each update

Decrement by 0.5 dB for each update

- - 0 0 - - - -

- - 0 1 - - - -

- - 1 0 - - - -

- - 1 1 - - - -

8.4.2.38 P0-R65

Auto Mute Control [2] (R/W)

00000100

This bit controls the behavior of the auto mute upon zero sample detection. The time length for zero detection is set with P0-R59.

Auto mute Channel B and Channel A independently

- - - - - 0 - -

Auto mute Channels A and Channel B only when both channels are about to be auto muted

Auto Mute Channel B [1] (R/W)

- - - - - 1 - -

00000100

This bit enables or disables auto mute on Channel A. Note that when Channel A auto mute is disabled and the P0-R65, bit 2 is set to 1, the

Channel B will also never be auto muted.

Disable Channel A auto mute

Enable Channel A auto mute

- - - - - - - 0 -

- - - - - - - 1 -

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Auto Mute Channel A [0] (R/W)

00000100

This bit enables or disables auto mute on Channel B. Note that when Channel B auto mute is disabled and the P0-R65, bit 2 is set to 1, the

Channel A will also never be auto muted.

Disable Channel B auto mute

Enable Channel B auto mute

- - - - - - - 0

- - - - - - - 1

8.4.2.39 P0-R82

GPIO1 Output Selection [4:0] (R/W)

00000000

These bits select the signal to output to GPIO1. To actually output the selected signal, the GPIO1 must be set to output mode at P0-R8.

Off (low)

- - - 0 0 0 0 0

- - - 0 0 0 0 1

- - - 0 0 0 1 0

- - - 0 0 0 1 1

- - - 0 0 1 0 0

- - - 0 0 1 0 1

- - - 0 0 1 1 0

- - - 0 0 1 1 1

- - - 0 1 0 0 0

- - - 0 1 0 0 1

- - - 0 1 0 1 0

- - - 0 1 0 1 1

- - - 0 1 1 0 0

- - - 0 1 1 0 1

- - - 0 1 1 1 0

- - - 0 1 1 1 1

- - - 1 0 0 0 0

DSP GPIO1 output

Register GPIO1 output (P0-R86, bit 2)

Auto mute flag (asserted when both Channel A and Channel B are auto muted)

Auto mute flag for Channel B

Auto mute flag for Channel A

Clock invalid flag (clock error or clock changing or clock missing)

Serial audio interface data output (SDOUT)

Analog mute flag for Channel B (low active)

Analog mute flag for Channel A (low active)

PLL lock flag

Charge pump clock

Reserved

Under voltage flag, asserted when SPK_MUTE voltage is higher than 0.7 DVDD

Under voltage flag, asserted when SPK_MUTE voltage is higher than 0.3 DVDD

PLL Output/4 (Requires Clock Flex Register)

Others: reserved

8.4.2.40 P0-R83

GPIO0 Output Selection [4:0] (R/W)

00000000

These bits select the signal to output to GPIO0. To actually output the selected signal, the GPIO0 must be set to output mode at P0-R8.

Off (low)

- - - 0 0 0 0 0

- - - 0 0 0 0 1

- - - 0 0 0 1 0

- - - 0 0 0 1 1

- - - 0 0 1 0 0

- - - 0 0 1 0 1

- - - 0 0 1 1 0

- - - 0 0 1 1 1

- - - 0 1 0 0 0

- - - 0 1 0 0 1

- - - 0 1 0 1 0

- - - 0 1 0 1 1

- - - 0 1 1 0 0

- - - 0 1 1 0 1

- - - 0 1 1 1 0

- - - 0 1 1 1 1

- - - 1 0 0 0 0

DSP GPIO0 output

Register GPIO0 output (P0-R86, bit 2)

Auto mute flag (asserted when both Channel A and Channel B are auto muted)

Auto mute flag for Channel B

Auto mute flag for Channel A

Clock invalid flag (clock error or clock changing or clock missing)

Serial audio interface data output (SDOUT)

Analog mute flag for Channel B (low active)

Analog mute flag for Channel A (low active)

PLL lock flag

Charge pump clock

Reserved

Under voltage flag, asserted when SPK_MUTE voltage is higher than 0.7 DVDD

Under voltage flag, asserted when SPK_MUTE voltage is higher than 0.3 DVDD

PLL Output/4 (Requires Clock Flex Register)

Others: reserved

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8.4.2.41 P0-R85

GPIO2 Output Selection [4:0] (R/W)

00000000

These bits select the signal to output to GPIO2. To actually output the selected signal, the GPIO2 must be set to output mode at P0-R8.

Off (low)

- - - 0 0 0 0 0

- - - 0 0 0 0 1

- - - 0 0 0 1 0

- - - 0 0 0 1 1

- - - 0 0 1 0 0

- - - 0 0 1 0 1

- - - 0 0 1 1 0

- - - 0 0 1 1 1

- - - 0 1 0 0 0

- - - 0 1 0 0 1

- - - 0 1 0 1 0

- - - 0 1 0 1 1

- - - 0 1 1 0 0

- - - 0 1 1 0 1

- - - 0 1 1 1 0

- - - 0 1 1 1 1

- - - 1 0 0 0 0

DSP GPIO2 output

Register GPIO2 output (P0-R86, bit 5)

Auto mute flag (asserted when both Channels A and B are auto muted)

Auto mute flag for Channel B

Auto mute flag for Channel A

Clock invalid flag (clock error or clock changing or clock missing)

Serial audio interface data output (SDOUT)

Analog mute flag for Channel B (low active)

Analog mute flag for Channel A (low active)

PLL lock flag

Charge pump clock

Reserved

Under voltage flag, asserted when SPK_MUTE voltage is higher than 0.7 DVDD

Under voltage flag, asserted when SPK_MUTE voltage is higher than 0.3 DVDD

PLL Output/4 (Requires Clock Flex Register)

Others: reserved

8.4.2.42 P0-R86

GPIO2 Output Control [5] (R/W)

00000000

This bit controls the GPIO2 output when the selection at P0-R85 is set to 0010 (register output).

Output low

- - - 0 - - - - -

- - - 1 - - - - -

00000000

Output high

GPIO0 Output Control [3] (R/W)

This bit controls the GPIO0 output when the selection at P0-R83 is set to 0010 (register output).

Output low

- - - - - 0 - - -

- - - - - 1 - - -

00000000

Output high

GPIO1 Output Control [2] (R/W)

This bit controls the GPIO1 output when the selection at P0-R82 is set to 0010 (register output).

Output low

Output high

- - - - - 0 - -

- - - - - 1 - -

8.4.2.43 P0-R87

GPIO2 Output Inversion [5] (R/W)

00000000

This bit controls the polarity of GPIO2 output. When set to 1, the output is inverted for any signal being selected.

Non-inverted

- - - 0 - - - - -

- - - 1 - - - - -

00000000

Inverted

GPIO0 Output Inversion [3] (R/W)

This bit controls the polarity of GPIO0 output. When set to 1, the output is inverted for any signal being selected.

Non-inverted

Inverted

- - - - - 0 - - -

- - - - - 1 - - -

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GPIO1 Output Inversion [2] (R/W)

00000000

This bit controls the polarity of GPIO1 output. When set to 1, the output is inverted for any signal being selected.

Non-inverted

Inverted

- - - - - 0 - -

- - - - - 1 - -

8.4.2.44 P0-R90

Channel B-1 Overflow [4] (Read Only)

00000000

This bit indicates whether the Channel B of DSP first output port has overflow. This bit is sticky and is cleared when read.

No overflow

- - - 0 - - - -

- - - 1 - - - -

00000000

Overflow occurred

Channel A-1 Overflow [3] (Read Only)

This bit indicates whether the Channel A of DSP first output port has overflow. This bit is sticky and is cleared when read.

No overflow

- - - - - 0 - - -

- - - - - 1 - - -

00000000

Overflow occurred

Channel B-2 Overflow [2] (Read Only)

This bit indicates whether the Channel B of DSP second output port has overflow. This bit is sticky and is cleared when read.

No overflow

- - - - - 0 - -

- - - - - 1 - -

00000000

Overflow occurred

Channel A-2 Overflow [1] (Read Only)

This bit indicates whether the Channel A of DSP second output port has overflow. This bit is sticky and is cleared when read.

No overflow

- - - - - - - 0 -

- - - - - - - 1 -

00000000

Overflow occurred

Shifter Overflow [0] (Read Only)

This bit indicates whether overflow occurred in the DSP shifter (possible sample corruption). This bit is sticky and is cleared when read.

No overflow

- - - - - - - 0

- - - - - - - 1

Overflow occurred

8.4.2.45 P0-R91

Detected F_S[6:4] (Read Only)

00111000

These bits indicate the currently detected audio sampling rate.

Error (out-of-valid range)

8 kHz

- 0 0 0 - - - -

- 0 0 1 - - - -

- 0 1 0 - - - -

- 0 1 1 - - - -

- 1 0 0 - - - -

- 1 0 1 - - - -

- 1 1 1 - - - -

00111000

16 kHz

32 kHz to 48 kHz

88.2 kHz to 96 kHz

176.4 kHz to 192 kHz

Reserved

Detected MCLK Ratio [3:0] (Read Only)

These bits indicate the currently detected MCLK ratio. Note that even if the MCLK ratio is not indicated as error, clock error might still be

flagged due to incompatible combination with the sampling rate. Specifically the MCLK ratio must be high enough to allow enough DSP

cycles for minimal audio processing when PLL is disabled. The absolute MCLK frequency must also be lower than 50 MHz.

Ratio error (The MCLK ratio is not allowed)

MCLK = 32 F_S

- - - - 0 0 0 0

- - - - 0 0 0 1

- - - - 0 0 1 0

- - - - 0 0 1 1

- - - - 0 1 0 0

- - - - 0 1 0 1

- - - - 0 1 1 0

- - - - 0 1 1 1

MCLK = 48 F_S

MCLK = 64 F_S

MCLK = 128 F_S

MCLK = 192 F_S

MCLK = 256 F_S

MCLK = 384 F_S

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Detected MCLK Ratio [3:0] (Read Only)

00111000

MCLK = 512 F_S

MCLK = 768 F_S

MCLK = 1024 F_S

MCLK = 1152 F_S

MCLK = 1536 F_S

MCLK = 2048 F_S

MCLK = 3072 F_S

- - - - 1 0 0 0

- - - - 1 0 0 1

- - - - 1 0 1 0

- - - - 1 0 1 1

- - - - 1 1 0 0

- - - - 1 1 0 1

- - - - 1 1 1 0

8.4.2.46 P0-R92

Detected SCLK Ratio [0] (Read Only)

00000000

This bit is the MSB of the 9 bit word that describes the currently detected SCLK to LRCK/FS Ratio. Binary to decimal conversion gives ratio.

Decode with P0-93 to determine value.

- - - - - - - 0

- - - - - - - 1

8.4.2.47 P0-R93

Detected SCLK Ratio [7:0] (Read Only)

00000000

These bits are bit 1 through bit 8 of the 9 bit word that describes the currently detected SCLK to LRCK/FS Ratio. Binary to decimal

conversion gives ratio.

LSB of 9 bit word

- - - - - - - 0

2nd LSB of 9 bit word

- - - - - - 0 -

...

2nd MSB of 9 bit word (MSB is found in P0-R92-B0)

0 - - - - - - -

00111000

Detected MCLK Ratio [3:0] (Read Only)

These bits indicate the currently detected MCLK ratio. Note that even if the MCLK ratio is not indicated as error, clock error might still be

flagged due to incompatible combination with the sampling rate. Specifically the MCLK ratio must be high enough to allow enough DSP

cycles for minimal audio processing when PLL is disabled. The absolute MCLK frequency must also be lower than 50 MHz.

These bits indicate the currently detected MCLK ratio. Note that even if the MCLK ratio is not indicated as error, clock

error might still be flagged due to incompatible combination with the sampling rate. Specifically the MCLK ratio must be

high enough to allow enough DSP cycles for minimal audio processing when PLL is disabled. The absolute MCLK

- - - - 0 0 0 0

frequency must also be lower than 50 MHz. Ratio error (The MCLK ratio is not allowed)

MCLK = 32 F_S

MCLK = 48 F_S

MCLK = 64 F_S

MCLK = 128 F_S

MCLK = 192 F_S

MCLK = 256 F_S

MCLK = 384 F_S

MCLK = 512 F_S

MCLK = 768 F_S

MCLK = 1024 F_S

MCLK = 1152 F_S

MCLK = 1536 F_S

MCLK = 2048 F_S

MCLK = 3072 F_S

- - - - 0 0 0 1

- - - - 0 0 1 0

- - - - 0 0 1 1

- - - - 0 1 0 0

- - - - 0 1 0 1

- - - - 0 1 1 0

- - - - 0 1 1 1

- - - - 1 0 0 0

- - - - 1 0 0 1

- - - - 1 0 1 0

- - - - 1 0 1 1

- - - - 1 1 0 0

- - - - 1 1 0 1

- - - - 1 1 1 0

8.4.2.48 P0-R94

Clock Detector Status [6] (Ready Only)

00000000

This bit indicates whether the MCLK clock is present or not.

MCLK is present

- 0 - - - - - -

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Clock Detector Status [6] (Ready Only)

Clock Detector Status 5 [5] (Ready Only)

00000000

MCLK is missing (halted)

- 1 - - - - - -

00000000

This bit indicates whether the PLL is locked or not. The PLL will be reported as unlocked when it is disabled.

PLL is locked

- - 1 - - - - -

- - 0 - - - - -

00000000

PLL is unlocked

Clock Detector Status 4 [4] (Ready Only)

This bit indicates whether the both LRCK/FS and SCLK are missing (tied low) or not.

LRCK/FS and/or SCLK is present

- - - 0 - - - -

- - - 1 - - - -

00000000

LRCK/FS and SCLK are missing

Clock Detector Status 3 [3] (Read Only)

This bit indicates whether the combination of current sampling rate and MCLK ratio is valid for clock auto set.

The combination of FS:MCLK ratio is valid

- - - - - 0 - - -

- - - - - 1 - - -

00000000

Error (clock auto set is not possible)

Clock Detector Status 2 [2] (Read Only)

This bit indicates whether the MCLK is valid or not. The MCLK ratio must be detectable to be valid. There is a limitation with this flag, that

is, when the low period of LRCK/FS is less than or equal to 5 SCLKs, this flag will be asserted (MCLK invalid reported).

MCLK is valid

- - - - - 0 - -

- - - - - 1 - -

00000000

MCLK is invalid

Clock Detector Status 1 [1] (Read Only)

This bit indicates whether the SCLK is valid or not. The SCLK ratio must be stable and in the range of 32-256F_Sto be valid.

SCLK is valid

- - - - - - - 0 -

- - - - - - - 1 -

00000000

SCLK is invalid

Clock Detector Status 0 [0] (Read Only)

This bit indicated whether the audio sampling rate is valid or not. The sampling rate must be detectable to be valid. There is a limitation with

this flag, that is when this flag is asserted and P0-R37 is set to ignore all asserted error flags such that the DAC recovers, this flag will be

de-asserted (sampling rate invalid not reported anymore).

Sampling rate is valid

Sampling rate is invalid

- - - - - - - 0

- - - - - - - 1

8.4.2.49 P0-R95

Latched Clock Halt [4] (Ready Only)

00000000

This bit indicates whether MCLK halt has occurred. The bit is cleared when read.

MCLK halt has not occurred

- - - 0 - - - -

- - - 1 - - - -

00000000

MCLK halt has occurred since last read

Clock Missing [2] (Read Only)

This bit indicates whether the LRCK/FS and SCLK are missing (tied low).

One or both of LRCK/FS SCLK is present

Both LRCK/FS and SCLK are missing

Clock Resync Request [1] (Read Only)

This bit indicates whether the clock resynchronization is in progress.

Not resynchronizing

- - - - - 0 - -

- - - - - 1 - -

00000000

- - - - - - - 0 -

- - - - - - - 1 -

00000000

Clock resynchronization is in progress

Clock Error [0] (Read Only)

This bit indicates whether a clock error is being reported.

Clock is valid

- - - - - - - 0

- - - - - - - 1

Clock is invalid (Error)

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8.4.2.50 P0-R108

Channel B Analog Mute Monitor [1] (Read Only)

00110011

This bit is a monitor for Channel B analog mute status.

Mute

- - - - - - - 0 -

- - - - - - - 1 -

00110011

Unmute

Channel A Analog Mute Monitor [0] (Read Only)

This bit is a monitor for Channel A analog mute status.

Mute

- - - - - - - 0

- - - - - - - 1

Unmute

8.4.2.51 P0-R109

Short Detect Monitor [4] (Ready Only)

00000000

This bit indicates whether line output short is occurring on the DAC_OUTx line.

Normal (No short)

- - - 0 - - - -

- - - 1 - - - -

00000000

Line output is being shorted

Short Detected Monitor [0] (Read Only)

This bit indicates whether line output short on DAC_OUTx has occurred since last read. This bit is sticky and is cleared when read.

No short

- - - - - - - 0

Line output short occurred

- - - - - - - 1

8.4.2.52 P0-R114

SPK_MUTE Decoder Status[1:0] (Read Only)

00000000

These bits indicate the output of the SPK_MUTE level decoder for monitoring purpose.

VDD > SPK_MUTE

- - - - - - 0 0

- - - - - - 0 1

- - - - - - 1 0

- - - - - - 1 1

VDD ≤ SPK_MUTE < 0.7 × VDD

Reserved (do not set)

0.7 × VDD ≤ SPK_MUTE

8.4.2.53 P0-R115

F_SSpeed Mode Monitor [1:0] (Read Only)

00000000

These bits indicate the actual F_Soperation mode being used. The actual value is the auto set one when clock auto set is active and register

set one when clock auto set is disabled.

Single speed (f_S≤ 48 kHz)

- - - - - - 0 0

- - - - - - 0 1

- - - - - - 1 0

Double speed (48 kHz ≤ f_S≤ 96 kHz)

Quad speed (96 kHz ≤ f_S≤ 192 kHz)

8.4.2.54 P0-R117

DSP Boot Done Flag [7] (R/W)

00000000

This bit indicates whether the DSP boot is completed.

DSP is booting

0 - - - - - - -

1 - - - - - - -

00000000

DSP boot completed

Power State [3:0] (Read Only)

These bits indicate the current power state of the DAC

Powerdown

- - - - 0 0 0 0

- - - - 0 0 0 1

- - - - 0 0 1 0

- - - - 0 0 1 1

Wait for CP voltage valid

Calibration

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Power State [3:0] (Read Only)

00000000

Volume ramp up

- - - - 0 1 0 0

- - - - 0 1 0 1

- - - - 0 1 1 0

- - - - 0 1 1 1

- - - - 1 0 0 0

Run (Playing)

Line output short or low impedance

Volume ramp down

Standby

8.4.2.55 P0-R119

GPIO2 Input State [5] (Read Only)

00101101

This bit indicates the logic level at GPIO2 pin.

GPIO2 logic level low

- - - 0 - - - - -

- - - 1 - - - - -

00101101

GPIO2 logic level high

GPIO0 Input State [3] (Read Only)

This bit indicates the logic level at GPIO0 pin.

GPIO0 logic level low

- - - - - 0 - - -

- - - - - 1 - - -

00101101

GPIO0 logic level high

GPIO1 Input State [2] (Read Only)

This bit indicates the logic level at GPIO1 pin.

GPIO1 logic level low

- - - - - 0 - -

- - - - - 1 - -

GPIO1 logic level high

8.4.2.56 P0-R120

Auto Mute Flag for Channel B [4] (Read Only)

00000000

This bit indicates the auto mute status for Channel B.

Not auto muted

Auto muted

- - - 0 - - - -

- - - 1 - - - -

00000000

Auto Mute Flag for Channel A [0] (Read Only)

This bit indicates the auto mute status for Channel A.

Not auto muted

Auto muted

- - - - - - - 0

- - - - - - - 1

8.4.2.57 P0-R121

DAC Mode [0] (R/W)

00000000

This bit controls the DAC mode.

Mode1

Mode2

- - - - - - - 0

- - - - - - - 1

8.4.2.58 P1-R2

Analog Gain Control for Channel B [4] (R/W)

00000000

This bit controls the Channel B analog gain.

0 dB

- - - 0 - - - -

- - - 1 - - - -

00000000

–6 dB

Analog Gain Control for Channel A [0] (R/W)

This bit controls the Channel A analog gain.

0 dB

- - - - - - - 0

- - - - - - - 1

–6 dB

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8.4.2.59 P1-R5

External UVP Control [1] (R/W)

00010001

This bit enables or disables detection of power supply drop via SPK_MUTE pin (external UVLO protection).

Enabled

- - - - - - - 0 -

- - - - - - - 1 -

00010001

Disabled

Internal UVP Control [0] (R/W)

This bit enables or disables internal detection of AVDD voltage drop (internal UVLO protection).

Enabled

Disabled

- - - - - - - 0

- - - - - - - 1

8.4.2.60 P1-R6

Analog Mute Control [0] (R/W)

00000000

This bit enables or disables analog mute following digital mute.

Enabled

Disabled

- - - - - - - 0

- - - - - - - 1

8.4.2.61 P1-R7

Analog +10% Gain for Channel B [4] (R/W)

This bit enables or disables amplitude boost mode for Channel B.

Normal amplitude

00000000

- - - 0 - - - -

- - - 1 - - - -

00000000

+10% (+0.8 dB) boosted amplitude

Analog +10% Gain for Channel A [0] (R/W)

This bit enables or disables amplitude boost mode for Channel A.

Normal amplitude

- - - - - - - 0

- - - - - - - 1

+10% (+0.8 dB) boosted amplitude

8.4.2.62 P1-R8

VCOM Reference Ramp-Up [0] (R/W)

This bit controls the VCOM voltage ramp up speed.

00000000

Normal ramp-up time is approximately 600 ms with external capacitance = 1 µF

Fast ramp-up time is approximately 3 ms with external capacitance = 1 µF

- - - - - - - 0

- - - - - - - 1

8.4.2.63 P1-R9

VCOM Power-Down Control [0] (R/W)

This bit controls VCOM powerdown switch.

VCOM is powered on

00000000

- - - - - - - 0

- - - - - - - 1

VCOM is powered down

8.4.2.64 P44-R1

Active CRAM Monitor [3] (Read Only)

00000000

This bit indicates which CRAM is being accessed by the DSP when adaptive mode is disabled. When adaptive mode is enabled, this bit

has no meaning.

CRAM A is being used by the DSP

CRAM B is being used by the DSP

- - - - - 0 - - -

- - - - - 1 - - -

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Adaptive Mode Control [2] (R/W)

00000000

This bit controls the DSP adaptive mode. When in adaptive mode, only CRAM A is accessible via serial interface when the DSP is disabled

(DAC in standby state), while when the DSP is enabled (DAC is run state) the CRAM A can only be accessed by the DSP and the CRAM B

can only be accessed by the serial interface, or vice versa depending on the value of CRAMSTAT. When not in adaptive mode, both CRAM

A and B can be accessed by the serial interface when the DSP is disabled, but when the DSP is enabled, no CRAM can be accessed by

serial interface. The DSP can access either CRAM, which can be monitored at SWPMON.

Adaptive mode disabled

Adaptive mode enabled

- - - - - 0 - -

- - - - - 1 - -

00000000

Active CRAM Selection [1] (Read Only)

This bit indicates which CRAM currently serves as the active one. The other CRAM serves as an update buffer, and can accessed by serial

interface (SPI/I²C)

CRAM A is active and being used by the DSP

CRAM B is active and being used by the DSP

- - - - - - - 0 -

- - - - - - - 1 -

00000000

Switch Active CRAM [0] (R/W)

This bit is used to request switching roles of the two buffers, (switching the active buffer role between CRAM A and CRAM B). This bit is

cleared automatically when the switching process completed.

No switching requested or switching completed

Switching is being requested

- - - - - - - 0

- - - - - - - 1

8.4.2.65 P253-R63

Clock Flex Register No. 1 [7:0] (R/W)

00000000

Using this register allows the PLL I/O to be set to GPIOs.

Set to 0x11

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 1

0 0 0 0 0 0 1 0

...

0 0 1 0 0 0 0 0

0 0 1 1 0 0 0 0

0 0 1 1 0 0 0 1

...

1 1 1 1 1 1 0 1

1 1 1 1 1 1 1 0

1 1 1 1 1 1 1 1

8.4.2.66 P253-R64

Clock Flex Register No. 2 [7:0] (R/W)

00000000

Using this register allows the PLL I/O to be set to GPIOs.

Set to 0x11

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 1

0 0 0 0 0 0 1 0

...

0 0 1 0 0 0 0 0

0 0 1 1 0 0 0 0

0 0 1 1 0 0 0 1

...

1 1 1 1 1 1 0 1

1 1 1 1 1 1 1 0

1 1 1 1 1 1 1 1

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9 Applications and Implementation

9.1 Application Information

One of the most significant benefits of the TAS5754M device is the ability to be used in a variety of applications

and with an assortment of signal processing options. This section details the information needed to configure the

device for several popular configurations and provides guidance on integrating the TAS5754M device into the

larger system.

9.1.1 External Component Selection Criteria

The Supporting Component Requirements table in each application description section lists the details of the

supporting required components in each of the System Application Schematics.

Where possible, the supporting component requirements have been consolidated to minimize the number of

unique components which are used in the design. Component list consolidation is a method to reduce the

number of unique part numbers in a design, to ease inventory management, and reduce the manufacturing steps

during board assembly. For this reason, some capacitors are specified at a higher voltage than what would

normally be required. An example of this is a 50-V capacitor may be used for decoupling of a 3.3-V power supply

net.

In this example, a higher voltage capacitor can be used even on the lower voltage net to consolidate all caps of

that value into a single component type. Similarly, a several unique resistors, having all the same size and value

but with different power ratings can be consolidated by using the highest rated power resistor for each instance

of that resistor value.

While this consolidation may seem excessive, the benefits of having fewer components in the design may far

outweigh the trivial cost of a higher voltage capacitor. If lower voltage capacitors are already available elsewhere

in the design, they can be used instead of the higher voltage capacitors. In all situations, the voltage rating of the

capacitors must be at least 1.45 times the voltage of the voltage which appears across them. The power rating of

the capacitors should be 1.5 times to 1.75 times the power dissipated in it during normal use case.

9.1.2 Component Selection Impact on Board Layout, Component Placement, and Trace Routing

Because the layout is important to the overall performance of the circuit, the package size of the components

shown in the component list were intentionally chosen to allow for proper board layout, component placement,

and trace routing. In some cases, traces are passed in between two surface mount pads or ground plane

extends from the TAS5754M device between two pads of a surface mount component and into to the

surrounding copper for increased heat-sinking of the device. While components may be offered in smaller or

larger package sizes, it is highly recommended that the package size remain identical to that used in the

application circuit as shown. This consistency ensures that the layout and routing can be matched very closely,

optimizing thermal, electromagnetic, and audio performance of the TAS5754M device in circuit in the final

system.

9.1.3 Amplifier Output Filtering

The TAS5754M device is often used with a low-pass filter, which is used to filter out the carrier frequency of the

PWM modulated output. This filter is frequently referred to as the L-C Filter, due to the presence of an inductive

element L and a capacitive element C to make up the 2-pole filter.

The L-C filter removes the carrier frequency, reducing electromagnetic emissions and smoothing the current

waveform which is drawn from the power supply. The presence and size of the L-C filter is determined by several

system level constraints. In some low-power use cases that do not have other circuits which are sensitive to EMI,

a simple ferrite bead or ferrite bead and capacitor can replace the traditional large inductor and capacitor that are

commonly used. In other high-power applications, large toroid inductors are required for maximum power and

film capacitors may be preferred due to audio characteristics. Refer to the application report SLOA119 for a

detailed description on proper component selection and design of an L-C filter based upon the desired load and

response.

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9.2 Typical Applications

9.2.1 2.0 (Stereo BTL) System

For the stereo (BTL) PCB layout, see Figure 87.

A 2.0 system generally refers to a system in which there are two full range speakers without a separate amplifier

path for the speakers which reproduce the low-frequency content. In this system, two channels are presented to

the amplifier via the digital input signal. These two channels are amplified and then sent to two separate

speakers. In some cases, the amplified signal is further separated based upon frequency by a passive crossover

network after the L-C filter. Even so, the application is considered 2.0.

Most commonly, the two channels are a pair of signals called a stereo pair, with one channel containing the

audio for the left channel and the other channel containing the audio for the right channel. While certainly the two

channels can contain any two audio channels, such as two surround channels of a multi-channel speaker

system, the most popular occurrence in two channels systems is a stereo pair.

It is important to note that the HybridFlows which have been developed for specifically for stereo applications will

frequently apply the same equalizer curves to the left channel and the right channel. This maximizes the

processing capabilities of each HybridFlow by minimizing the cycles required by the BiQuad filters.

When two signals that are not two separate signals, but instead are derived from a single signal which is

separated into low frequency and high frequency by the signal processor, the application is commonly referred to

as 1.1 or Bi-Amped systems. The 2.0 (Stereo BTL) System application is shown in Figure 80.

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9.2.1.1 Design Requirements

•

Power Supplies:

–

3.3-V Supply

5-V to 24-V Supply

Communication: Host Processor serving as I²C Compliant Master

•

External Memory (such as EEPROM and Flash) used for coefficients and RAM portions of HybridFlow < 5 kB

The requirements for the supporting components for the TAS5754M device in a Mono (PBTL) System is provided

in Table 22.

Table 22. Supporting Component Requirements for Stereo 2.0 (BTL) Systems

REFERENCE

DESIGNATOR

VALUE

SIZE

DETAILED DESCRIPTION

Digital-input, closed-loop class-D amplifier with HybridFlow

processing

U100

TAS5754M

48 Pin TSSOP

See Adjustable

Amplifier Gain and

Switching Frequency

Selection

R100

R101

0402

1%, 0.063 W

See Adjustable

Amplifier Gain and

Switching Frequency

Selection

L100, L101, L102,

L103

See Amplifier Output Filtering

C196, C197, C198,

C199

0.01 µF

0.1 µF

0.22 µF

0.68 µF

1 µF

0603

0402

0603

0805

0603

0402

Ceramic, 0.01 µF, 50V, ±10%, X7R

Ceramic, 0.1 µF, ±10%, X7R

Voltage rating must be > 1.45 × V_PVDD

C100, C121

C104, C108, C111,

C115

Ceramic, 0.22 µF, ±10%, X7R

Voltage rating must be > 1.45 × V_PVDD

C109, C110, C116,

C117

Ceramic, 0.68 µF, ±10%, X7R

Voltage rating must be > 1.8 × V_PVDD

Ceramic, 1 µF, ±10%, X7R

Voltage rating must be > 1.45 × V_PVDD

C103

C105, C118, C119,

C120

1 µF

Ceramic, 1 µF, 6.3V, ±10%, X5R

C106, C107, C113,

C114

Ceramic, 2.2 µF, ±10%, X5R

Voltage rating must be > 1.45 × V_PVDD

2.2 µF

22 µF

0402

0805

C101, C102, C122,

C123

Ceramic, 22 µF, ±20%, X5R

Voltage rating must be > 1.45 × V_PVDD

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Step One: Hardware Integration

•

Using the Typical Application Schematic as a guide, integrate the hardware into the system schematic.

Following the recommended component placement, board layout and routing give in the example layout

above, integrate the device and its supporting components into the system PCB file.

–

The most critical section of the circuit is the the power supply inputs, the amplifier output signals, and the

high-frequency signals which go to the serial audio port. It is recommended that these be constructed to

ensure they are given precedent as design trade-offs are made.

–

For questions and support go to the E2E forums (e2e.ti.com). If it is necessary to deviate from the

recommended layout, please visit the E2E forum to request a layout review.

9.2.1.2.2 Step Two: HybridFlow Selection and System Level Tuning

•

Use the TAS5754/6M HybridFlow Processsor User Guide and HybridFlow Documentation (SLAU577) to

select the HybridFlow that meets the needs of the target application.

•

Use the TAS5754_56MEVM evaluation module and the PurePath ControlConsole (PPC) software, to load the

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appropriate HybridFlow. Tune the end equipment by following the instructions in the SLAU577 .

9.2.1.2.3 Step Three: Software Integration

•

Use the Register Dump feature of the PPC software to generate a baseline configuration file.

Generate additional configuration files based upon operating modes of the end-equipment and integrate static

configuration information into initialization files.

•

Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the

main system program.

9.2.1.3 Application Specific Performance Plots for Stereo 2.0 (BTL) Systems

Table 23. Relevant Performance Plots

PLOT TITLE

Figure 25. Output Power vs PVDD

PLOT NUMBER

C036

Figure 26. THD+N vs Frequency, V_PVDD= 12 V

Figure 27. THD+N vs Frequency, V_PVDD= 15 V

Figure 28. THD+N vs Frequency, V_PVDD= 18 V

Figure 29. THD+N vs Frequency, V_PVDD= 24 V

Figure 30. THD+N vs Power, V_PVDD= 12 V

Figure 31. THD+N vs Power, V_PVDD= 15 V

Figure 32. THD+N vs Power, V_PVDD= 18 V

Figure 33. THD+N vs Power, V_PVDD= 24 V

Figure 34. Idle Channel Noise vs PVDD

C034

C002

C037

C003

C035

C004

C038

C005

C006

Figure 35. Efficiency vs Output Power

C007

Figure 36. Idle Current Draw (Filterless) vs PVDD

Figure 37. Idle Current Draw (Traditional LC Filter) vs PVDD

Figure 40. DVDD PSRR vs. Frequency

C013

C015

C028

Figure 41. AVDD PSRR vs. Frequency

C029

Figure 42. C_PVDDPSRR vs. Frequency

C030

Figure 43. Powerdown Current Draw vs. PVDD

C032

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9.2.2 Mono (PBTL) Systems

For the mono (PBTL) PCB layout, see Figure 89.

A mono system refers to a system in which the amplifier is used to drive a single loudspeaker. Parallel Bridge

Tied Load (PBTL) indicates that the two full-bridge channels of the device are placed in parallel and drive the

loudspeaker simultaneously using an identical audio signal. The primary benefit of operating the TAS5754M

device in PBTL operation is to reduce the power dissipation and increase the current sourcing capabilities of the

amplifier output. In this mode of operation, the current limit of the audio amplifier is approximately doubled while

the on-resistance is approximately halved.

The loudspeaker can be a full-range transducer or one that only reproduces the low-frequency content of an

audio signal, as in the case of a powered subwoofer. Often in this use case, two stereo signals are mixed

together and sent through a low-pass filter in order to create a single audio signal which contains the low

frequency information of the two channels. Conversely, advanced digital signal processing can create a low-

frequency signal for a multichannel system, with audio processing which is specifically targeted on low-frequency

effects.

Although any of the HybridFlows can be made to work with a mono speaker, it is strongly recommended that

HybridFlows which have been created specifically for mono applications be used. These HybridFlows contain the

mixing and filtering required to generate the mono signal. They also include processing which is targeted at

improving the low-frequency performance of an audio system- a feature that, while targeted at subwoofers, can

also be used to enhance the low-frequency performance of a full-range speaker.

Because low-frequency signals are not perceived as having a direction (at least to the extent of high-frequency

signals) it is common to reproduce the low-frequency content of a stereo signal that is sent to two separate

channels. This configuration pairs one device in Mono PBTL configuration and another device in Stereo BTL

configuration in a single system called a 2.1 system. The Mono PBTL configuration is detailed in the 2.1 (Stereo

BTL + External Mono Amplifier) Systems section.

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9.2.2.1 Design Requirements

•

Power Supplies:

–

3.3-V Supply

5-V to 24-V Supply

Communication: Host Processor serving as I²C Compliant Master

•

External Memory (EEPROM, Flash, Etc.) used for Coefficients and RAM portions of HybridFlow < 5 kB

The requirements for the supporting components for the TAS5754M device in a Mono (PBTL) System is provided

in Table 24.

Table 24. Supporting Component Requirements for Mono (PBTL) Systems

REFERENCE

DESIGNATOR

VALUE

SIZE

DETAILED DESCRIPTION

Digital-input, closed-loop class-D amplifier with HybridFlow

processing

U200

TAS5754M

48 Pin TSSOP

See Adjustable

Amplifier Gain and

Switching Frequency

Selection

R200

R201

R202

0402

1%, 0.063 W

See Adjustable

Amplifier Gain and

Switching Frequency

Selection

See Adjustable

Amplifier Gain and

Switching Frequency

Selection

L200, L201

C298, C299

See Amplifier Output Filtering

0.01 µF

0.1 µF

0603

0402

Ceramic, 0.01 µF, 50 V, ±10%, X7R

Ceramic, 0.1 µF, ±10%, X7R

Voltage rating must be > 1.45 × V_PVDD

C216

C208, C209, C214,

C215

Ceramic, 0.22 µF, ±10%, X7R

Voltage rating must be > 1.45 × V_PVDD

0.22 µF

0.68 µF

1 µF

0603

0805

0603

0402

0805

Ceramic, 0.68 µF, ±10%, X7R

Voltage rating must be > 1.8 × V_PVDD

C220, C221

C200

Ceramic, 1 µF, ±10%, X7R

Voltage rating must be > 1.45 × V_PVDD

C205, C211, C213,

C212

1 µF

Ceramic, 1 µF, 6.3 V, ±10%, X5R

C202, C217, C352,

C367

Ceramic, 1 µF, ±10%, X5R

Voltage rating must be > 1.45 × V_PVDD

1 µF

Ceramic, 2.2 µF, ±10%, X5R

Voltage rating must be > 1.45 × V_PVDD

C206, C207

C203, C218

C204, C219

2.2 µF

22 µF

0402

0805

Ceramic, 22 µF, ±20%, X5R

Voltage rating must be > 1.45 × V_PVDD

390 µF

10 × 10

Aluminum, 390 µF, ±20%, 0.08-Ω

Voltage rating must be > 1.45 × V_PVDD

9.2.2.2 Detailed Design Procedure

9.2.2.2.1 Step One: Hardware Integration

•

Using the Typical Application Schematic as a guide, integrate the hardware into the system schematic.

Following the recommended component placement, board layout and routing give in the example layout

above, integrate the device and its supporting components into the system PCB file.

–

The most critical section of the circuit is the the power supply inputs, the amplifier output signals, and the

high-frequency signals which go to the serial audio port. It is recommended that these be constructed to

ensure they are given precedent as design trade-offs are made.

–

For questions and support go to the E2E forums (e2e.ti.com). If it is necessary to deviate from the

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recommended layout, please visit the E2E forum to request a layout review.

9.2.2.2.2 Step Two: HybridFlow Selection and System Level Tuning

•

Use the TAS5754/6M HybridFlow Processsor User Guide and HybridFlow Documentation (SLAU577) to

select the HybridFlow that meets the needs of the target application.

•

Use the TAS5754_56MEVM evaluation module and the PurePath ControlConsole (PPC) software, to load the

appropriate HybridFlow. Tune the end equipment by following the instructions in the SLAU577 .

9.2.2.2.3 Step Three: Software Integration

•

Use the Register Dump feature of the PPC software to generate a baseline configuration file.

Generate additional configuration files based upon operating modes of the end-equipment and integrate static

configuration information into initialization files.

•

Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the

main system program.

9.2.2.3 Application Specific Performance Plots for Mono (PBTL) Systems

Table 25. Relevant Performance Plots

PLOT TITLE

Figure 44. Output Power vs PVDD

PLOT NUMBER

C039

. THD+N vs Frequency, V_PVDD= 12 V

C017

. THD+N vs Frequency, V_PVDD= 15 V

C018

Figure 47. THD+N vs Frequency, V_PVDD= 18 V

Figure 48. THD+N vs Frequency, V_PVDD= 24 V

Figure 49. THD+N vs Power, V_PVDD= 12 V

Figure 50. THD+N vs Power, V_PVDD= 15 V

Figure 51. THD+N vs Power, V_PVDD= 18 V

Figure 52. THD+N vs Power, V_PVDD= 24 V

Figure 53. Idle Channel Noise vs PVDD

Figure 54. Efficiency vs Output Power

C019

C020

C021

C022

C023

C024

C025

C026

Figure 55. Idle Current Draw (filterless) vs PVDD

Figure 56. Idle Current Draw (traditional LC filter) vs PVDD

Figure 57. PVDD PSRR vs Frequency

C031

C032

C027

Figure 40. DVDD PSRR vs. Frequency

Figure 41. AVDD PSRR vs. Frequency

Figure 42. C_PVDDPSRR vs. Frequency

Figure 43. Powerdown Current Draw vs. PVDD

C028

C029

C030

C032

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9.2.3 2.1 (Stereo BTL + External Mono Amplifier) Systems

Figure 91 shows the PCB Layout for the 2.1 System.

To increase the low-frequency output capabilities of an audio system, a single subwoofer can be added to the

system. Because the spatial clues for audio are predominately higher frequency than that reproduced by the

subwoofer, often a single subwoofer can be used to reproduce the low frequency content of several other

channels in the system. This is frequently referred to as a dot one system. A stereo system with a subwoofer is

referred to as a 2.1 (two-dot-one), a 3 channel system with subwoofer is referred to as a 3.1 (three-dot-one), a

popular surround system with five speakers and one subwoofer is referred to as a 5.1, and so on.

9.2.3.1 Basic 2.1 System (TAS5754M Device + Simple Digital Input Amplifier)

In the most basic 2.1 system, a subwoofer is added to a stereo left and right pair of speakers as discussed

above. The audio amplifiers include one TAS5754M device for the high frequency channels and one simple

digital input device without integrated audio processing for the subwoofer channel. A member of the popular

TAS5760xx family of devices is a popular choice for the subwoofer amplifier. In this system, the subwoofer

content is generated by summing the two channels of audio and sending them through a high-pass filter to filter

out the high frequency content. This is then sent to the SDIN pin of the subwoofer amplifier, which is operating in

PBTL, via the SDOUT line of the TAS5754M device . In the basic 2.1 system, only HybridFlows which included

subwoofer signal generation can be used, because the subwoofer amplifier depends on the TAS5754M device to

create its stereo low-frequency input signal.

9.2.3.2 Advanced 2.1 System ( Two TAS5754M devices)

In higher performance systems, the subwoofer output can be enhanced using digital audio processing as was

done in the high-frequency channels. To accomplish this, two TAS5754M devices are used- one for the high

frequency left and right speakers and one for the mono subwoofer speaker. In this system, the audio signal can

be sent from the TAS5754M device through the SDOUT pin. Alternatively, the subwoofer amplifier can accept

the same digital input as the stereo, which might come from a central systems processor. In advanced 2.1

systems, any HybridFlow can be used for the subwoofer, provided the sample rates for the two are the same.

While any of the HybridFlows can be used, it is highly recommended that only mono HybridFlows are used for

the subwoofer. Doing so streamlines development time and effort by minimizing confusion and complexity.

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PVDD

R300

750k

R301

150k

C303

1µF

C300

0.1µF

C301

22µF

C302

22µF

GND

C304

To System Processor

3.3V

0.22µF

L300

L301

2.1-SDA

2.1-SCL

2.1-SPK_OUT1A+

2.1-GPIO0_HF

2.1-GPIO1_HF

2.1-HF_OUTA+

2.1-HF_OUTA-

C305

1µF

C306

2.2µF

C307

2.2µF

2.1-MCLK

2.1-SCLK

2.1-SDIN

3.3V

2.1-SPK_OUT1A-

C308

C309

0.68µF

C310

0.68µF

0.22µF

GND

U300

TAS5754MDCA

TAS5756MDCA

GND

PAD

GND

C311

2.1-LRCK/FS

0.22µF

L302

GND

2.1-SPK_OUT1B-

2.1-HF_OUTB-

L303

C312

1µF

C313

2.2µF

C314

2.2µF

3.3V

2.1-SPK_OUT1B+

C315

2.1-HF_OUTB+

C316

0.68µF

C317

0.68µF

C318

1µF

C319

1µF

C320

1µF

GND

PVDD

0.22µF

GND

2.1-SPK_MUTE

2.1-SPK_FAULT

GND

C321

0.1µF

C322

22µF

C323

22µF

GND

PVDD

R350

750k

R351

150k

C354

390µF

C350

1µF

C351

0.1µF

C352

1µF

C353

22µF

GND

3.3V

C358

2.1-GPIO0_LF

2.1-GPIO1

2.1-SDOUT_LF

0.22µF

L350

C355

1µF

C356

2.2µF

C357

2.2µF

2.1-SPK_OUT2A

C359

2.1_LF+

C370

0.68µF

0.22µF

GND

U301

TAS5754MDCA

TAS5756MDCA

GND

PAD

GND

C364

0.22µF

2.1-SPK_OUT2B

C365

L351

GND

2.1_LF-

C360

1µF

R352

49.9k

C371

0.68µF

3.3V

0.22µF PVDD

C361

1µF

C362

1µF

C363

1µF

GND

C369

390µF

C366

0.1µF

C367

1µF

C368

22µF

GND

Figure 82. 2.1 (Stereo BTL + External Mono Amplifier) Application Schematic

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9.2.3.3 Design Requirements

•

Power Supplies:

–

3.3-V Supply

5-V to 24-V Supply

Communication: Host Processor serving as I²C Compliant Master

•

External Memory (EEPROM, Flash, Etc.) used for Coefficients and RAM portions of HybridFlow < 5 kB

The requirements for the supporting components for the TAS5754M device in a 2.1 (Stereo BTL + External Mono

Amplifier) System is provided in Table 26.

Table 26. Supporting Component Requirements for 2.1 (Stereo BTL + External Mono Amplifier) Systems

REFERENCE

DESIGNATOR

VALUE

SIZE

DETAILED DESCRIPTION

Digital-input, closed-loop class-D amplifier with HybridFlow

processing

U300

TAS5754M

48 Pin TSSOP

See Adjustable

Amplifier Gain and

Switching Frequency

Selection

R300, R350

R301, R351

R352

0402

1%, 0.063 W

See Adjustable

Amplifier Gain and

Switching Frequency

Selection

See Adjustable

Amplifier Gain and

Switching Frequency

Selection

L300, L301, L302,

L303

See Amplifier Output Filtering

Ceramic, 0.01µF, 50V, +/-10%, X7R

L350, L351

C394, C395, C396,

C397, C398, C399

0.01 µF

0.1 µF

0603

0402

C300, C321, C351,

C366

Ceramic, 0.1µF, ±10%, X7R

Voltage rating must be > 1.45 × V_PVDD

C304, C308, C311,

C315, C358, C359,

C364, C365

Ceramic, 0.22µF, ±10%, X7R

Voltage rating must be > 1.45 × V_PVDD

0.22 µF

0603

C309, C310, C316,

C317, C370, C371

Ceramic, 0.68 µF, ±10%, X7R

Voltage rating must be > 1.8 × V_PVDD

0.68 µF

1 µF

0805

0603

C303, C350, C312,

C360

Ceramic, 1 µF, ±10%, X7R

Voltage rating must be > 1.45 × V_PVDD

C305, C318, C319,

C320, C355, C361,

C363, C312, C362

1 µF

0402

Ceramic, 1 µF, 6.3V, ±10%, X5R

Ceramic, 1 µF, ±10%, X7R

Voltage rating must be > 1.45 × V_PVDD

C352, C367

1 µF

0805

0402

C306, C307, C313,

C314, C356, C357,

2.2 µF

Ceramic, 2.2 µF, ±10%, X5R

Voltage rating must be > 1.45 × V_PVDD

C301, C302, C322,

C323, C353, C368

22 µF

0805

Ceramic, 22 µF, ±20%, X5R

Voltage rating must be > 1.45 × V_PVDD

C354, C369

390 µF

10 × 10

Aluminum, 390 µF, ±20%, 0.08 Ω

Voltage rating must be > 1.45 × V_PVDD

9.2.3.4 Detailed Design Procedure

9.2.3.4.1 Step One: Hardware Integration

•

Using the Typical Application Schematic as a guide, integrate the hardware into the system schematic.

Following the recommended component placement, board layout and routing give in the example layout

above, integrate the device and its supporting components into the system PCB file.

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–

The most critical section of the circuit is the the power supply inputs, the amplifier output signals, and the

high-frequency signals which go to the serial audio port. It is recommended that these be constructed to

ensure they are given precedent as design trade-offs are made.

For questions and support go to the E2E forums (e2e.ti.com). If it is necessary to deviate from the

recommended layout, please visit the E2E forum to request a layout review.

9.2.3.4.2 Step Two: HybridFlow Selection and System Level Tuning

•

Use the TAS5754/6M HybridFlow Processsor User Guide and HybridFlow Documentation (SLAU577) to

select the HybridFlow that meets the needs of the target application.

•

Use the TAS5754_56MEVM evaluation module and the PurePath ControlConsole (PPC) software, to load the

appropriate HybridFlow. Tune the end equipment by following the instructions in the SLAU577 .

9.2.3.4.3 Step Three: Software Integration

•

Use the Register Dump feature of the PPC software to generate a baseline configuration file.

Generate additional configuration files based upon operating modes of the end-equipment and integrate static

configuration information into initialization files.

•

Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the

main system program.

9.2.3.5 Application Specific Performance Plots for 2.1 (Stereo BTL + External Mono Amplifier) Systems

Table 27. Relevant Performance Plots

DEVICE

PLOT TITLE

Figure 25. Output Power vs PVDD

PLOT NUMBER

C036

C034

C002

C037

C003

C035

C004

C038

C005

C006

C007

C013

C015

C039

C017

C018

C019

C020

C021

C022

C023

C024

C025

C026

C031

C032

C027

Figure 26. THD+N vs Frequency, V_PVDD= 12 V

Figure 27. THD+N vs Frequency, V_PVDD= 15 V

Figure 28. THD+N vs Frequency, V_PVDD= 18 V

Figure 29. THD+N vs Frequency, V_PVDD= 24 V

Figure 30. THD+N vs Power, V_PVDD= 12 V

Figure 31. THD+N vs Power, V_PVDD= 15 V

Figure 32. THD+N vs Power, V_PVDD= 18 V

Figure 33. THD+N vs Power, V_PVDD= 24 V

Figure 34. Idle Channel Noise vs PVDD

U300

Figure 35. Efficiency vs Output Power

Figure 36. Idle Current Draw (Filterless) vs PVDD

Figure 37. Idle Current Draw (Traditional LC Filter) vs PVDD

Figure 44. Output Power vs PVDD

. THD+N vs Frequency, V_PVDD= 12 V

. THD+N vs Frequency, V_PVDD= 15 V

Figure 47. THD+N vs Frequency, V_PVDD= 18 V

Figure 48. THD+N vs Frequency, V_PVDD= 24 V

Figure 49. THD+N vs Power, V_PVDD= 12 V

Figure 50. THD+N vs Power, V_PVDD= 15 V

Figure 51. THD+N vs Power, V_PVDD= 18 V

Figure 52. THD+N vs Power, V_PVDD= 24 V

Figure 53. Idle Channel Noise vs PVDD

U301

Figure 54. Efficiency vs Output Power

Figure 55. Idle Current Draw (filterless) vs PVDD

Figure 56. Idle Current Draw (traditional LC filter) vs PVDD

Figure 57. PVDD PSRR vs Frequency

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Table 27. Relevant Performance Plots (continued)

DEVICE

PLOT TITLE

Figure 40. DVDD PSRR vs. Frequency

Figure 41. AVDD PSRR vs. Frequency

Figure 42. C_PVDDPSRR vs. Frequency

Figure 43. Powerdown Current Draw vs. PVDD

PLOT NUMBER

C028

U300

and

U301

C029

C030

C032

9.2.4 2.2 (Dual Stereo BTL) Systems

For the 2.2 (Dual Stereo BTL) PCB layout, see Figure 93.

A 2.2 system consists of a stereo pair of loudspeakers with a pair of low frequency loudspeakers. In some cases,

this is implemented as two stereo full-range speakers and two subwoofers. In others, it is implemented as two

high frequency speakers and two mid-range speakers.

As in the case of the 2.1 system, the 2.2 system can be created by using the audio processing inside of the

TAS5754M device and creating a subwoofer signal which is sent to a simple digital input amplifier like one of the

TAS5760xx devices (or similar). This requires that a HybridFlow that contains a subwoofer generation processing

block be used in the TAS5754M device. This signal is created by summing the left and right channel, filtering

with a high-pass filter and sending it to the subwoofer amplifier. For this type of system, the TAS5754M device

used for the high-frequency drivers must have a subwoofer generation processing block in order to provide the

appropriate signal to the subwoofer amplifiers.

Alternatively, the low-frequency drivers can be implemented by using two TAS5754M devices; each receiving

their input from a central systems processor. This type of implementation allows for any stereo HybridFlow to be

used for both the low-frequency and high-frequency drivers, increasing the processing options available for the

system. This expands the processing capabilities of the system, introducing digital signal processing to the low-

frequency drivers as well as the high-frequency drivers. This type of 2.2 system is described in Figure 83.

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PVDD

R400

750k

R401

150k

C403

1µF

C400

0.1µF

C401

22µF

C402

22µF

GND

To System Processor

C404

3.3V

0.22µF

L400

L401

2.2-SDA

2.2-SCL

2.2-SPK_OUT1A+

2.2-GPIO0_HF

2.2-GPIO1_HF

2.2-HF_OUTA+

C405

1µF

C406

2.2µF

C407

2.2µF

2.2-MCLK

2.2-SCLK

2.2-SDIN

3.3V

2.2-SPK_OUT1A-

C408

2.2-HF_OUTA-

C410

0.68µF

C409

0.68µF

0.22µF

GND

U400

TAS5754MDCA

TAS5756MDCA

GND

PAD

GND

C411

2.2-LRCK/FS

0.22µF

L402

L403

GND

2.2-SPK_OUT1B-

2.2-HF_OUTB-

C412

1µF

C413

2.2µF

C414

2.2µF

3.3V

2.2-SPK_OUT1B+

C415

2.2-HF_OUTB+

C416

0.68µF

C417

0.68µF

C418

1µF

C419

1µF

C420

1µF

GND

PVDD

0.22µF

GND

2.2-SPK_MUTE

2.2-SPK_FAULT

GND

C421

0.1µF

C422

22µF

C423

22µF

GND

PVDD

R450

750k

R451

150k

C453

1µF

C450

0.1µF

C451

22µF

C452

22µF

GND

C454

3.3V

0.22µF

L450

L451

2.2-SPK_OUT2A+

2.2-GPIO0_LF

2.2-GPIO1_LF

2.2-SDOUT_LF

2.2-LF_OUTA+

C455

1µF

C456

2.2µF

C457

2.2µF

3.3V

2.2-SPK_OUT2A-

C458

2.2-LF_OUTA-

C459

0.68µF

C460

0.68µF

0.22µF

GND

U401

TAS5754MDCA

TAS5756MDCA

GND

PAD

GND

C461

0.22µF

L452

L453

GND

2.2-SPK_OUT2B-

2.2-LF_OUTB-

C462

1µF

C463

2.2µF

C464

2.2µF

3.3V

2.2-SPK_OUT2B+

C465

2.2-LF_OUTB+

C466

0.68µF

C467

0.68µF

C468

1µF

C469

1µF

C470

1µF

GND

PVDD

0.22µF

GND

C471

0.1µF

C472

22µF

C473

22µF

GND

Figure 83. 2.2 (Dual Stereo BTL) Application Schematic

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9.2.4.1 Design Requirements

•

Power Supplies:

–

3.3-V Supply

5-V to 24-V Supply

Communication: Host Processor serving as I²C Compliant Master

•

External Memory (EEPROM, Flash, Etc.) used for Coefficients and RAM portions of HybridFlow < 5 kB

The requirements for the supporting components for the TAS5754M device in a 2.1 (Stereo BTL + External Mono

Amplifier) System is provided in Figure 89.

Table 28. Supporting Component Requirements for 2.2 (Dual Stereo BTL) Systems

REFERENCE

DESIGNATOR

VALUE

SIZE

DETAILED DESCRIPTION

U400, U401

Digital Input, Closed-Loop Class-

D Amplifier with HybridFlow

Processing

TAS5754M device

48-pin TSSOP

R400, R450

R401, R451

See Figure 84

0402

1%, 0.063 W

L400, L401, L402, L403, L450,

L451, L452, L453

See Amplifier Output Filtering

0603

C492, C493, C494, C495, C496,

C497, C498, C499

Ceramic, 0.01 µF, 50 V, ±10%,

X7R

0.01 µF

0.1 µF

C400, C421, C450, C471

Ceramic, 0.1 µF, ±10%, X7R,

Voltage rating must be > 1.45 ×

V_PVDD

0402

0603

0805

C404, C408, C411, C415, C454,

C458, C461, C465

Ceramic, 0.22 µF, ±10%, X7R,

Voltage rating must be > 1.45 ×

V_PVDD

0.22 µF

0.68 µF

C409, C410, C416, C417, C459,

C460, C466, C467

Ceramic, 0.68 µF, ±10%, X7R,

Voltage rating must be > 1.8 ×

V_PVDD

C403, C453, C462

Ceramic, 1 µF, ±10%, X7R,

Voltage rating must be > 1.45 ×

V_PVDD

1 µF

0603

0402

C405, C418, C419, C420, C455,

C468, C469, C470, C412, C462

Ceramic, 1 µF, 6.3V, ±10%, X5R

C406, C407, C413, C414, C456,

C457, C463, C464

Ceramic, 2.2 µF, ±10%, X5R,

Voltage rating must be > 1.45 ×

V_PVDD

2.2 µF

C401, C402, C422, C423, C451,

C452, C472, C473

Ceramic, 22 µF, ±20%, X5R,

Voltage rating must be > 1.45 ×

V_PVDD

22 µF

0805

9.2.4.2 Detailed Design Procedure

9.2.4.2.1 Step One: Hardware Integration

•

Using the Typical Application Schematic as a guide, integrate the hardware into the system schematic.

Following the recommended component placement, board layout and routing give in the example layout

above, integrate the device and its supporting components into the system PCB file.

–

The most critical section of the circuit is the the power supply inputs, the amplifier output signals, and the

high-frequency signals which go to the serial audio port. It is recommended that these be constructed to

ensure they are given precedent as design trade-offs are made.

–

For questions and support go to the E2E forums (e2e.ti.com). If it is necessary to deviate from the

recommended layout, please visit the E2E forum to request a layout review.

9.2.4.2.2 Step Two: HybridFlow Selection and System Level Tuning

•

Use the TAS5754/6M HybridFlow Processsor User Guide and HybridFlow Documentation (SLAU577) to

select the HybridFlow that meets the needs of the target application.

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•

Use the TAS5754_56MEVM evaluation module and the PurePath ControlConsole (PPC) software, to load the

appropriate HybridFlow. Tune the end equipment by following the instructions in the SLAU577 .

9.2.4.2.3 Step Three: Software Integration

•

Use the Register Dump feature of the PPC software to generate a baseline configuration file.

Generate additional configuration files based upon operating modes of the end-equipment and integrate static

configuration information into initialization files.

•

Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the

main system program.

9.2.4.3 Application Specific Performance Plots for 2.2 (Dual Stereo BTL) Systems

Table 29. Relevant Performance Plots

PLOT TITLE

Figure 25. Output Power vs PVDD

PLOT NUMBER

C036

C034

C002

C037

C003

C035

C004

C038

C005

C006

C007

C013

C015

C028

C029

C030

C032

Figure 26. THD+N vs Frequency, V_PVDD= 12 V

Figure 27. THD+N vs Frequency, V_PVDD= 15 V

Figure 28. THD+N vs Frequency, V_PVDD= 18 V

Figure 29. THD+N vs Frequency, V_PVDD= 24 V

Figure 30. THD+N vs Power, V_PVDD= 12 V

Figure 31. THD+N vs Power, V_PVDD= 15 V

Figure 32. THD+N vs Power, V_PVDD= 18 V

Figure 33. THD+N vs Power, V_PVDD= 24 V

Figure 34. Idle Channel Noise vs PVDD

Figure 35. Efficiency vs Output Power

Figure 36. Idle Current Draw (Filterless) vs PVDD

Figure 37. Idle Current Draw (Traditional LC Filter) vs PVDD

Figure 40. DVDD PSRR vs. Frequency

Figure 41. AVDD PSRR vs. Frequency

Figure 42. C_PVDDPSRR vs. Frequency

Figure 43. Powerdown Current Draw vs. PVDD

9.2.5 1.1 (Dual BTL, Bi-Amped) Systems

The 1.1 use case is a special application of the 2.0 stereo BTL system. In this system, two channels of an

amplifier are used to reproduce a single channel of an audio signal that has been separated based on frequency.

This configuration removes the need for passive cross-over elements inside of a loudspeaker, because the signal

is separated into a low-frequency and a high-frequency component before it is amplified. Systems which operate

in this configuration, in which separate amplifier channels drive the low and high-frequency loudspeakers directly,

are often called “bi-amped” systems.

Popular applications for this configuration include:

•

Powered near-field monitors

Blue-tooth Speakers

Co-axial Loudspeakers

Surround/Fill Speakers for multi-channel audio

From a hardware perspective, the TAS5754M device is configured in the same way as the Stereo BTL system.

However, special HybridFlows which support 1.1 operation must be used, because HybridFlows that are

designed for stereo applications frequently apply the same equalizer curves to the left and the right hand

channel. Additionally, many 1.1 HybridFlows include a delay element which can improve time alignment between

two loudspeakers that are mounted on the same baffle some distance apart.

For the 1.1 (Dual BTL, Bi-Amped) PCB layout, see Figure 95.

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9.2.5.1 Design Requirements

•

Power Supplies:

–

DVDD Supply, in compliance with the voltage ranges shown in the Recommended Operating Conditions

table.

–

PVDD Supply, in compliance with the voltage ranges shown in the Recommended Operating Conditions

table.

•

Communication: Host Processor serving as I²C Compliant Master

External Memory (EEPROM, Flash, Etc.) used for Coefficients and RAM portions of HybridFlow < 5 kB

The requirements for the supporting components for the TAS5754M device in a Dual BTL, Bi-Amped System is

provided in Figure 95.

Table 30. Supporting Component Requirements for 1.1 (Dual BTL, Bi-Amped) Systems

REFERENCE

DESIGNATOR

VALUE

SIZE

DETAILED DESCRIPTION

Digital-input, closed-loop class-D amplifier with HybridFlow

processing

U500

TAS5754M

48 Pin TSSOP

See Adjustable

Amplifier Gain and

Switching Frequency

Selection

R500

R501

0402

1%, 0.063 W

See Adjustable

Amplifier Gain and

Switching Frequency

Selection

L500, L501, L502,

L503

See Amplifier Output Filtering

C596, C597, C598,

C599

0.01 µF

0.1 µF

0.22 µF

0.68 µF

1 µF

0603

0402

0603

0805

0603

0402

Ceramic, 0.01 µF, 50 V, ±10%, X7R

Ceramic, 0.1 µF, ±10%, X7R

Voltage rating must be > 1.45 × V_PVDD

C500, C521

C504, C508, C511,

C515

Ceramic, 0.22 µF, ±10%, X7R

Voltage rating must be > 1.45 × V_PVDD

C509, C510, C516,

C517

Ceramic, 0.68 µF, ±10%, X7R

Voltage rating must be > 1.8 × V_PVDD

Ceramic, 1 µF, ±10%, X7R

Voltage rating must be > 1.45 × V_PVDD

C503

C505, C518, C519,

C520, C512

1 µF

Ceramic, 1 µF, 6.3V, ±10%, X5R

C506, C507, C513,

C514

Ceramic, 2.2 µF, ±10%, X5R

Voltage rating must be > 1.45 × V_PVDD

2.2 µF

22 µF

0402

805

C501, C502, C522,

C523

Ceramic, 22 µF, ±20%, X5R

Voltage rating must be > 1.45 × V_PVDD

9.2.5.2 Detailed Design Procedure

9.2.5.2.1 Step One: Hardware Integration

•

Using the Typical Application Schematic as a guide, integrate the hardware into the system schematic.

Following the recommended component placement, board layout and routing give in the example layout

above, integrate the device and its supporting components into the system PCB file.

–

The most critical section of the circuit is the the power supply inputs, the amplifier output signals, and the

high-frequency signals which go to the serial audio port. It is recommended that these be constructed to

ensure they are given precedent as design trade-offs are made.

–

For questions and support go to the E2E forums (e2e.ti.com). If it is necessary to deviate from the

recommended layout, please visit the E2E forum to request a layout review.

9.2.5.2.2 Step Two: HybridFlow Selection and System Level Tuning

•

Use the TAS5754/6M HybridFlow Processsor User Guide and HybridFlow Documentation (SLAU577) to

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select the HybridFlow that meets the needs of the target application.

•

Use the TAS5754_56MEVM evaluation module and the PurePath ControlConsole (PPC) software, to load the

appropriate HybridFlow. Tune the end equipment by following the instructions in the SLAU577 .

9.2.5.2.3 Step Three: Software Integration

•

Use the Register Dump feature of the PPC software to generate a baseline configuration file.

Generate additional configuration files based upon operating modes of the end-equipment and integrate static

configuration information into initialization files.

•

Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the

main system program.

9.2.5.3 Application Specific Performance Plots for 1.1 (Dual BTL, Bi-Amped) Systems

Table 31. Relevant Performance Plots

PLOT TITLE

Figure 25. Output Power vs PVDD

PLOT NUMBER

C036

Figure 26. THD+N vs Frequency, V_PVDD= 12 V

Figure 27. THD+N vs Frequency, V_PVDD= 15 V

Figure 28. THD+N vs Frequency, V_PVDD= 18 V

Figure 29. THD+N vs Frequency, V_PVDD= 24 V

Figure 30. THD+N vs Power, V_PVDD= 12 V

Figure 31. THD+N vs Power, V_PVDD= 15 V

Figure 32. THD+N vs Power, V_PVDD= 18 V

Figure 33. THD+N vs Power, V_PVDD= 24 V

Figure 34. Idle Channel Noise vs PVDD

C034

C002

C037

C003

C035

C004

C038

C005

C006

Figure 35. Efficiency vs Output Power

C007

Figure 36. Idle Current Draw (Filterless) vs PVDD

Figure 37. Idle Current Draw (Traditional LC Filter) vs PVDD

Figure 40. DVDD PSRR vs. Frequency

C013

C015

C028

Figure 41. AVDD PSRR vs. Frequency

C029

Figure 42. C_PVDDPSRR vs. Frequency

C030

Figure 43. Powerdown Current Draw vs. PVDD

C032

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10 Power Supply Recommendations

10.1 Power Supplies

The TAS5754M device requires two power supplies for proper operation. A high-voltage supply called PVDD is

required to power the output stage of the speaker amplifier and its associated circuitry. Additionally, one low-

voltage power supply called DVDD is required to power the various low-power portions of the device. The

allowable voltage range for both the PVDD and the DVDD supply are listed in the Recommended Operating

Conditions table.

AVDD

Internal Analog Circuitry

Internal Mixed

Signal Circuitry

Internal Digital

Circuitry

+

DVDD

DVDD_REG

External Filtering/Decoupling

±

LDO

CPVDD

CPVSS

External Filtering/Decoupling

Charge

Pump

DAC Output Stage

(Positive)

DAC Output Stage

(Negative)

Output Stage

Power Supply

Gate Drive

Voltage

PVDD

GVDD_REG

External Filtering/Decoupling

Linear

Regulator

+

PVDD

±

Figure 85. Power Supply Functional Block Diagram

10.1.1 DVDD Supply

The DVDD supply required from the system is used to power several portions of the device. As shown in the

Figure 85, it provides power to the DVDD pin, the CPVDD pin, and the AVDD pin. Proper connection, routing,

and decoupling techniques are highlighted in the TAS5754M device EVM User's Guide SLAU583 (as well as the

Applications and Implementation section and Layout Examples section) and must be followed as closely as

possible for proper operation and performance. Deviation from the guidance offered in the TAS5754M device

EVM User's Guide, which followed the same techniques as those shown in the Applications and Implementation

section, may result in reduced performance, errant functionality, or even damage to the TAS5754M device.

Some portions of the device also require a separate power supply which is a lower voltage than the DVDD

supply. To simplify the power supply requirements for the system, the TAS5754M device includes an integrated

low-dropout (LDO) linear regulator to create this supply. This linear regulator is internally connected to the DVDD

supply and its output is presented on the DVDD_REG pin, providing a connection point for an external bypass

capacitor. It is important to note that the linear regulator integrated in the device has only been designed to

support the current requirements of the internal circuitry, and should not be used to power any additional external

circuitry. Additional loading on this pin could cause the voltage to sag, negatively affecting the performance and

operation of the device.

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Power Supplies (continued)

The outputs of the high-performance DACs used in the TAS5754M device are ground centered, requiring both a

positive low-voltage supply and a negative low-voltage supply. The positive power supply for the DAC output

stage is taken from the AVDD pin, which is connected to the DVDD supply provided by the system. A charge

pump is integrated in the TAS5754M device to generate the negative low-voltage supply. The power supply input

for the charge pump is the CPVDD pin. The CPVSS pin is provided to allow the connection of a filter capacitor

on the negative low-voltage supply. As is the case with the other supplies, the component selection, placement,

and routing of the external components for these low voltage supplies are shown in the evmName and should be

followed as closely as possible to ensure proper operation of the device.

10.1.2 PVDD Supply

The output stage of the speaker amplifier drives the load using the PVDD supply. This is the power supply which

provides the drive current to the load during playback. Proper connection, routing, and decoupling techniques are

highlighted in the evmName and must be followed as closely as possible for proper operation and performance.

Due the high-voltage switching of the output stage, it is particularly important to properly decouple the output

power stages in the manner described in the TAS5754M device EVM User's Guide. Lack of proper decoupling,

like that shown in the EVM User's Guide, results in voltage spikes which can damage the device.

A separate power supply is required to drive the gates of the MOSFETs used in the output stage of the speaker

amplifier. This power supply is derived from the PVDD supply via an integrated linear regulator. A GVDD_REG

pin is provided for the attachment of decoupling capacitor for the gate drive voltage regulator. It is important to

note that the linear regulator integrated in the device has only been designed to support the current requirements

of the internal circuitry, and should not be used to power any additional external circuitry. Additional loading on

this pin could cause the voltage to sag, negatively affecting the performance and operation of the device.

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11 Layout

11.1 Layout Guidelines

11.1.1 General Guidelines for Audio Amplifiers

Audio amplifiers which incorporate switching output stages must have special attention paid to their layout and

the layout of the supporting components used around them. The system level performance metrics, including

thermal performance, electromagnetic compliance (EMC), device reliability, and audio performance are all

affected by the device and supporting component layout.

Ideally, the guidance provided in the applications section with regard to device and component selection can be

followed by precise adherence to the layout guidance shown in . These examples represent exemplary baseline

balance of the engineering trade-offs involved with laying out the device. These designs can be modified slightly

as needed to meet the needs of a given application. In some applications, for instance, solution size can be

compromised in order to improve thermal performance through the use of additional contiguous copper near the

device. Conversely, EMI performance can be prioritized over thermal performance by routing on internal traces

and incorporating a via picket-fence and additional filtering components. In all cases, it is recommended to start

from the guidance shown in the Layout Examples section and the TAS5754M-56MEVM, and work with TI field

application engineers or through the E2E community in order to modify it based upon the application specific

goals.

11.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network

Placing the bypassing and decoupling capacitors close to supply has been long understood in the industry. This

applies to DVDD, AVDD, CPVDD, and PVDD. However, the capacitors on the PVDD net for the TAS5754M

device deserve special attention.

It is imperative that the small bypass capacitors on the PVDD lines of the DUT be placed as close the PVDD pins

as possible. Not only does placing these devices far away from the pins increase the electromagnetic

interference in the system, but doing so can also negatively affect the reliability of the device. Placement of these

components too far from the TAS5754M device may cause ringing on the output pins that can cause the voltage

on the output pin to exceed the maximum allowable ratings shown in the Absolute Maximum Ratings table,

damaging the device. For that reason, the capacitors on the PVDD net must be no further away from their

associated PVDD pins than what is shown in the example layouts in the Layout Examples section

11.1.3 Optimizing Thermal Performance

Follow the layout examples shown in the Layout Examples section of this document to achieve the best balance

of solution size, thermal, audio, and electromagnetic performance. In some cases, deviation from this guidance

may be required due to design constraints which cannot be avoided. In these instances, the system designer

should ensure that the heat can get out of the device and into the ambient air surrounding the device.

Fortunately, the heat created in the device would prefer to travel away from the device and into the lower

temperature structures around the device.

11.1.3.1 Device, Copper, and Component Layout

Primarily, the goal of the PCB design is to minimize the thermal impedance in the path to those cooler structures.

These tips should be followed to achieve that goal:

•

Avoid placing other heat producing components or structures near the amplifier (including above or below in

the end equipment).

•

If possible, use a higher layer count PCB to provide more heat sinking capability for the TAS5754M device

and to prevent traces and copper signal and power planes from breaking up the contiguous copper on the top

and bottom layer.

•

Place the TAS5754M device away from the edge of the PCB when possible to ensure that heat can travel

away from the device on all four sides.

Avoid cutting off the flow of heat from the TAS5754M device to the surrounding areas with traces or via

strings. Instead, route traces perpendicular to the device and line up vias in columns which are perpendicular

to the device.

•

Unless the area between two pads of a passive component is large enough to allow copper to flow in

between the two pads, orient it so that the narrow end of the passive component is facing the TAS5754M

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Layout Guidelines (continued)

device .

•

Because the ground pins are the best conductors of heat in the package, maintain a contiguous ground plane

from the ground pins to the PCB area surrounding the device for as many of the ground pins as possible.

11.1.3.2 Stencil Pattern

The recommended drawings for the TAS5754M device PCB foot print and associated stencil pattern are shown

at the end of this document in the package addendum. Additionally, baseline recommendations for the via

arrangement under and around the device are given as a starting point for the PCB design. This guidance is

provided to suit the majority of manufacturing capabilities in the industry and prioritizes manufacturability over all

other performance criteria. In elevated ambient temperatures or under high-power dissipation use-cases, this

guidance may be too conservative and advanced PCB design techniques may be used to improve thermal

performance of the system. It is important to note that the customer must verify that deviation from the guidance

shown in the package addendum, including the deviation explained in this section, meets the customer’s quality,

reliability, and manufacturability goals.

11.1.3.2.1 PCB footprint and Via Arrangement

The PCB footprint (also known as a symbol or land pattern) communicates to the PCB fabrication vendor the

shape and position of the copper patterns to which the TAS5754M device will be soldered to. This footprint can

be followed directly from the guidance in the package addendum at the end of this data sheet. It is important to

make sure that the thermal pad, which connects electrically and thermally to the PowerPAD of the TAS5754M

device , be made no smaller than what is specified in the package addendum. This ensures that the TAS5754M

device has the largest interface possible to move heat from the device to the board.

The via pattern shown in the package addendum provides an improved interface to carry the heat from the

device through to the layers of the PCB, because small diameter plated vias (with minimally-sized annular rings)

present a low thermal-impedance path from the device into the PCB. Once into the PCB, the heat travels away

from the device and into the surrounding structures and air. By increasing the number of vias, as shown in the

Layout Examples section, this interface can benefit from improved thermal performance.

NOTE

Vias can obstruct heat flow if they are not constructed properly.

•

Remove thermal reliefs on thermal vias, because they impede the flow of heat through the via.

Vias filled with thermally conductive material are best, but a simple plated via can be used to avoid the

additional cost of filled vias.

•

The drill diameter should be no more than 8mils in diameter. Also, the distance between the via barrel and

the surrounding planes should be minimized to help heat flow from the via into the surrounding copper

material. In all cases, minimum spacing should be determined by the voltages present on the planes

surrounding the via and minimized wherever possible.

•

Vias should be arranged in columns, which extend in a line radially from the heat source to the surrounding

area. This arrangement is shown in the Layout Examples section.

•

Ensure that vias do not cut-off power current flow from the power supply through the planes on internal

layers. If needed, remove some vias which are farthest from the TAS5754M device to open up the current

path to and from the device.

11.1.3.2.1.1 Solder Stencil

During the PCB assembly process, a piece of metal called a stencil on top of the PCB and deposits solder paste

on the PCB wherever there is an opening (called an aperture) in the stencil. The stencil determines the quantity

and the location of solder paste that is applied to the PCB in the electronic manufacturing process. In most

cases, the aperture for each of the component pads is almost the same size as the pad itself.

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Layout Guidelines (continued)

However, the thermal pad on the PCB is quite large and depositing a large, single deposition of solder paste

would lead to manufacturing issues. Instead, the solder is applied to the board in multiple apertures, to allow the

solder paste to outgas during the assembly process and reduce the risk of solder bridging under the device. This

structure is called an aperture array, and is shown in the Layout Examples section. It is important that the total

area of the aperture array (the area of all of the small apertures combined) covers between 70% and 80% of the

area of the thermal pad itself.

11.2 Layout Examples

11.2.1 2.0 (Stereo BTL) System

Figure 86. 2.0 (Stereo BTL) 3-D View

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Layout Examples (continued)

Figure 87. 2.0 (Stereo BTL) Top Copper View

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Layout Examples (continued)

11.2.2 Mono (PBTL) System

Figure 88. Mono (PBTL) 3-D View

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Layout Examples (continued)

Figure 89. Mono (PBTL) Top Copper View

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Layout Examples (continued)

11.2.3 2.1 (Stereo BTL + Mono PBTL) Systems

Figure 90. 2.1 (Stereo BTL + Mono PBTL) 3-D View

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Layout Examples (continued)

Figure 91. 2.1 (Stereo BTL + Mono PBTL) Top Copper View

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Layout Examples (continued)

11.2.4 2.2 (Dual Stereo BTL) Systems

Figure 92. 2.2 (Dual Stereo BTL) 3-D View

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Layout Examples (continued)

Figure 93. 2.2.2 (Dual Stereo BTL) Top Copper View

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Layout Examples (continued)

11.2.5 1.1 (Bi-Amped BTL) Systems

Figure 94. 1.1 (Bi-Amped BTL) 3-D View

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Layout Examples (continued)

Figure 95. 2. 1.1 (Bi-Amped BTL) Top Copper View

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Specification Definitions

The glossary listed in the Glossary section is a general glossary with commonly used acronyms and words which

are defined in accordance with a broad TI initiative to comply with industry standards such as JEDEC, IPC, IEEE,

and others. The glossary provided in this section defines words, phrases, and acronyms that are unique to this

product and documentation, collateral, or support tools and software used with this product. For any additional

questions regarding definitions and terminology, please see the e2e Audio Amplfier Forum.

Bridge tied load (BTL) is an output configuration in which one terminal of the speaker is connected to one half-

bridge and the other terminal is connected to another half-bridge.

DUT refers to a device under test to differentiate one device from another.

Closed-loop architecture describes a topology in which the amplifier monitors the output terminals, comparing

the output signal to the input signal and attempts to correct for non-linearities in the output.

Dynamic controls are those which are changed during normal use by either the system or the end-user.

GPIO is a general purpose input/output pin. It is a highly configurable, bi-directional digital pin which can perform

many functions as required by the system.

Host processor refers to device which serves as a central system controller, providing control information to

devices connected to it as well as gathering audio source data from devices upstream from it and distributing it to

other devices. Configuring the controls of a device to optimize the audio output of a loudspeaker based on

frequency response, time alignment, target sound pressure level, safe operating area of the system, and user

preference.

HybridFlow uses components which are built in RAM and components which are built in ROM to make a

configurable device that is easier to use than a fully-programmable device while remaining flexible enough to be

used in several applications

Maximum continuous output power refers to the maximum output power that the amplifier can continuously

deliver without shutting down when operated in a 25°C ambient temperature. Testing is performed for the period

of time required that their temperatures reach thermal equilibrium and are no longer increasing

Parallel bridge tied load (PBTL) is an output configuration in which one terminal of the speaker is connected to

two half-bridges which have been placed in parallel and the other terminal is connected to another pair of half

bridges placed in parallel

r_DS(on)is a measure of the on-resistance of the MOSFETs used in the output stage of the amplifier.

Static configuration information are controls which do not change while the system is in normal use.

Vias are copper-plated through-hole in a PCB.

12.2 Trademarks

PurePath is a trademark of Texas Instruments.

Burr-Brown is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.3 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.4 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

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13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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Product Folder Links: TAS5754M

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TAS5754MDCAR

HTSSOP DCA

48

2000

330.0

24.4

8.6

13.0

1.8

12.0

24.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

*All dimensions are nominal

Device

Package Type Package Drawing Pins

HTSSOP DCA 48

SPQ

Length (mm) Width (mm) Height (mm)

350.0 350.0 43.0

TAS5754MDCAR

2000

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TUBE

*All dimensions are nominal

Device

Package Name Package Type

DCA HTSSOP

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

TAS5754MDCA

48

40

530

11.89

3600

4.9

Pack Materials-Page 3

GENERIC PACKAGE VIEW

DCA 48

12.5 x 6.1, 0.5 mm pitch

HTSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224608/A

www.ti.com

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TAS5754M
厂家：	TEXAS INSTRUMENTS
描述：	40W 立体声、61W 单声道、4.5V 至 26.4V 电源电压、数字输入 D 类音频放大器放大器音频放大器
文件：	总129页 (文件大小：4345K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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