TAS6424MS-Q1 [TI]
汽车类 45W、2MHz、4 通道、4.5V 至 18V 数字输入 D 类音频放大器;
| 型号： | TAS6424MS-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 45W、2MHz、4 通道、4.5V 至 18V 数字输入 D 类音频放大器 放大器 音频放大器 |
| 文件： | 总68页 (文件大小：3795K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TAS6424MS-Q1
ZHCSMI4 – NOVEMBER 2020
TAS6424MS-Q1 具有负载突降保护和 I2C 诊断功能的 45W、2MHz 数字输入 4 通
道汽车用 D 类音频放大器
1 特性
2 应用
•
符合面向汽车应用的 AEC-Q100 标准
– 温度等级 1：–40°C 至 +125°C TA
高级负载诊断
•
•
汽车音响主机
汽车外部放大器
•
3 说明
– 直流诊断功能，无需输入时钟即可执行
– 交流诊断功能，可通过阻抗和相位响应实现高频
扬声器检测
TAS6424MS-Q1 器件是一款采用 2.1MHz PWM 开关
频率的四通道数字输入 D 类音频放大器，以非常小的
PCB 尺寸实现成本优化的解决方案，可针对启停事件
在低至 4.5V 的电压下全面运行，并可在高达 40kHz 的
音频带宽下提供出色的音质。
•
•
可轻松满足 CISPR25-L5 EMC 规范
音频输入
– 4 通道 I2S 或 4/8 通道 TDM 输入
– 输入采样率：44.1kHz、48kHz、96kHz
– 输入格式：16 位至 32 位 I2S 和 TDM
音频输出
输出开关频率既可以设置为高于调幅 (AM) 频带，以消
除 AM 频带干扰并降低输出滤波需求及成本；也可以
设置为低于 AM 频带，以优化器件效率。
•
– 四通道桥接式负载 (BTL)
– 双通道并行 BTL (PBTL)
– 最高可达 2.1MHz 的输出开关频率
– 在 4Ω 负载、14.4V BTL 条件下，输出功率为
27W，THD 为 10%
– 在 2Ω 负载、14.4V BTL 条件下，输出功率为
45W，THD 为 10%
– 在 2Ω 负载、18V PBTL 条件下，输出功率为
80W，THD 为 10%
在 4Ω 负载、14.4V BTL 条件下的音频性能
– 输出功率为 1W 时，THD+N < 0.02%
– 42µVRMS 输出噪声
– –90dB 串扰
负载诊断功能
该器件内置负载诊断功能，用于检测和诊断误接的输
出，以及检测交流耦合型高频扬声器，从而帮助缩短制
造过程中的测试时间。
TAS6424MS-Q1 D 类音频放大器专为汽车音响主机和
外部放大器模块而设计。有关引脚兼容的单通道、双通
道及四通道器件，请参阅器件选项表。
器件信息
器件型号
封装(1)
封装尺寸（标称值）
•
•
TAS6424MS-Q1
HSSOP (56)
18.41mm × 7.49mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 开路和短路输出负载
– 输出至电池短路或接地短路
– 线路输出检测能力高达 6kΩ
– 独立于主机运行
•
•
保护
– 输出电流限制和短路保护
– 40V 负载突降
– 可承受接地开路和电源开路
– 直流失调电压
– 温度过高
– 欠压和过压
常规运行
PCB 区域
– 4.5V 至 18V 的电源电压
– I2C 控制，具有 4 个地址选项
– 锁存或非锁存削波检测
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLOSE66
TAS6424MS-Q1
ZHCSMI4 – NOVEMBER 2020
www.ti.com.cn
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Options................................................................ 3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings ....................................... 6
7.2 ESD 等级.................................................................... 6
7.3 Recommended Operating Conditions ........................6
7.4 Thermal Information ...................................................7
7.5 Electrical Characteristics ............................................7
7.6 Typical Characteristics..............................................12
8 Parameter Measurement Information..........................17
9 Detailed Description......................................................18
9.1 Overview...................................................................18
9.2 Functional Block Diagram.........................................18
9.3 Feature Description...................................................19
9.4 Device Functional Modes..........................................30
9.5 Programming............................................................ 31
9.6 Register Maps...........................................................34
10 Application Information Disclaimer...........................50
10.1 Application Information........................................... 50
10.2 Typical Applications ............................................... 52
11 Power Supply Recommendations..............................57
12 Layout...........................................................................58
12.1 Layout Guidelines................................................... 58
12.2 Layout Example...................................................... 58
12.3 Thermal Considerations..........................................58
13 Device and Documentation Support..........................60
13.1 Documentation Support.......................................... 60
13.2 Related Documentation.......................................... 60
13.3 Receiving Notification of Documentation Updates..60
13.4 支持资源..................................................................60
13.5 商标.........................................................................60
13.6 静电放电警告.......................................................... 60
13.7 术语表..................................................................... 60
14 Mechanical, Packaging, and Orderable
Information.................................................................... 60
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
November 2020
*
Initial release.
spacer
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5 Device Options
Non-
Latching
Output Power per channel / 10% THD
Channel
Current Limit
(Typ)
Channel Power-Supply Voltage
Part Number
4 Ω / BTL
14.4 V
4 Ω / BTL
2 Ω / BTL
14.4 V
2 Ω / PBTL
Max Voltage
Count
Range
Clip Detect
WARN Pin(1)
Max Voltage
TAS6424-Q1
TAS6424M-Q1
TAS6424L-Q1
TAS6422-Q1
4
4
4
2
1
4
4
2
4.5 V to 26.4 V
4.5 V to 18 V
4.5 V to 18 V
4.5 V to 26.4 V
4.5 V to 26.4 V
4.5 V to 18 V
4.5 V to 18 V
4.5 V to 26.4 V
6.5 A
6.5 A
4.8 A
6.5 A
6.5 A
4.8 A
6.5 A
6.5 A
N
N
N
N
Y
Y
Y
Y
27 W
27 W
27 W
27 W
27 W
27 W
27 W
27 W
75 W at 25 V
45 W at 18 V
45 W at 18 V
75 W at 25 V
75 W at 25 V
75 W at 25 V
45 W at 18 V
75 W at 25 V
45 W
45 W
27 W
45 W
45 W
27 W
45 W
45 W
150 W at 25 V
80 W at 18 V
80 W at 18 V
150 W at 25 V
N/A
TAS6421-Q1
TAS6424LS-Q1
TAS6424MS-Q1
TAS6422E-Q1
80 W at 18 V
80 W at 18 V
150 W at 25 V
(1) Register configurable function. N = Latched clip detect only. Y = Supports both latched and non-latched clip detect .
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6 Pin Configuration and Functions
GND
PVDD
VBAT
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PVDD
2
PVDD
3
BST_4P
OUT_4P
GND
AREF
4
VREG
VCOM
AVSS
5
6
OUT_4M
BST_4M
GND
7
AVDD
GVDD
GVDD
GND
8
9
BST_3P
OUT_3P
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MCLK
SCLK
OUT_3M
BST_3M
PVDD
FSYNC
SDIN1
SDIN2
GND
Thermal
Pad
PVDD
BST_2P
OUT_2P
GND
GND
VDD
OUT_2M
BST_2M
GND
SCL
SDA
I2C_ADDR0
I2C_ADDR1
STANDBY
MUTE
FAULT
WARN
GND
BST_1P
OUT_1P
GND
OUT_1M
BST_1M
PVDD
PVDD
Not to scale
图 6-1. DKQ Package, 56-Pin HSSOP With Exposed Thermal Pad, Top View
表 6-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
AREF
AVDD
AVSS
NO.
4
PWR
PWR
PWR
VREG and VCOM bypass capacitor return
8
Voltage regulator bypass. Connect 1 µF capacitor from AVDD to AVSS
AVDD bypass capacitor return
7
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表 6-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
31
35
37
41
44
48
50
54
26
14
BST_1M
BST_1P
BST_2M
BST_2P
BST_3M
BST_3P
BST_4M
BST_4P
FAULT
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
DO
Bootstrap capacitor connection pins for high-side gate driver
Bootstrap capacitor connection pins for high-side gate driver
Bootstrap capacitor connection pins for high-side gate driver
Bootstrap capacitor connection pins for high-side gate driver
Bootstrap capacitor connection pins for high-side gate driver
Bootstrap capacitor connection pins for high-side gate driver
Bootstrap capacitor connection pins for high-side gate driver
Bootstrap capacitor connection pins for high-side gate driver
Reports a fault (active low, open drain), 100-kΩ internal pull-up resistor
Audio frame clock input
FSYNC
DI
1, 11, 17, 18,
28, 33, 36, 39,
46, 49, 52
GND
GND
Ground
9
Gate drive voltage regulator derived from VBAT input pin. Connect 2.2 µF capacitor to GND
Gate drive voltage regulator derived from VBAT input pin. Connect 2.2 µF capacitor to GND
GVDD
PWR
DI
10
22
23
12
I2C_ADDR0
I2C_ADDR1
MCLK
I2C address pins. Refer to 表 9-8
DI
DI
Audio master clock input
Mutes the device outputs (active low) while keeping output FETs switching at 50%, 100-kΩ
internal pull-down resistor
MUTE
25
OUT_1M
OUT_1P
OUT_2M
OUT_2P
OUT_3M
OUT_3P
OUT_4M
OUT_4P
32
34
38
40
45
47
51
53
NO
PO
NO
PO
NO
PO
NO
PO
Negative output for the channel
Positive output for the channel
Negative output for the channel
Positive output for the channel
Negative output for the channel
Positive output for the channel
Negative output for the channel
Positive output for the channel
2, 29, 30, 42,
43, 55, 56
PVDD voltage input (can be connected to battery). Bulk capacitor and bypass capacitor
required
PVDD
PWR
SCL
20
13
21
15
16
24
3
DI
DI
I2C clock input
SCLK
SDA
Audio bit and serial clock input
DI/O
DI
I2C data input and output
SDIN1
SDIN2
STANDBY
VBAT
VCOM
VDD
TDM data input and audio I2S data input for channels 1 and 2
Audio I2S data input for channels 3 and 4
Enables low power standby state (active Low), 100-kΩ internal pull-down resistor
Battery voltage input
DI
DI
PWR
PWR
PWR
PWR
DO
6
Bias voltage
19
5
3.3 V external supply voltage
VREG
WARN
Voltage regulator bypass
27
Clip and overtemperature warning (active low, open drain), 100-kΩ internal pull-up resistor
Provides both electrical and thermal connection for the device. Heatsink must be connected to
GND.
Thermal Pad
—
GND
(1) GND = ground, PWR = power, PO = positive output, NO = negative output, DI = digital input, DO = digital output, DI/O = digital input
and output, NC = no connection
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
PVDD, VBAT
VMAX
DC supply voltage relative to GND
Transient supply
-0.3
30
V
voltage: PVDD,
VBAT
t ≤ 400 ms exposure
-1
40
V
VRAMP
VDD
IMAX
Supply-voltage ramp rate: PVDD, VBAT
DC supply voltage relative to GND
75
3.5
±8
V/ms
V
-0.3
Maximum current per pin (PVDD, VBAT, OUT_xP, OUT_xM, GND)
Pulsed supply
A
IMAX_PULSED
current per PVDD
pin (one shot)
t < 100 ms
±12
A
V
Input voltage for logic pins (SCL, SDA, SDIN1, SDIN2, MCLK,
BCLK, LRCLK, MUTE,/STANDBY, I2C_ADDRx)
VLOGIC
-0.3
VDD + 0.5
VGND
TJ
Maximum voltage between GND pins
Maximum operating junction temperature
Storage temperature
-0.3
-55
-55
0.3
150
150
V
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD 等级
值
单位
人体放电模型 (HBM)，符合 AEC Q100-002(1)
HBM ESD 分类等级 2
±3000
±500
±1000
V
V
V(ESD）
静电放电
所有引脚
充电器件模型 (CDM)，符合 AEC Q100–011
CDM ESD 分类等级 C4B
转角引脚（1、28、29 和
56）
(1) (1) AEC Q100–002 指示应当按照 ANSI/ESDA/JEDEC JS–001 规范执行 HBM 应力测试。
7.3 Recommended Operating Conditions
MIN
4.5
TYP
MAX UNIT
PVDD
VBAT
VDD
TA
Output FET Supply Voltage Range
Battery Supply Voltage Input
DC Logic supply
Relative to GND
Relative to GND
Relative to GND
18
4.5
14.4
3.3
18
3.5
V
3.0
Ambient temperature
–40
125
°C
Ω
An adequate thermal design is
required
TJ
Junction temperature
–40
150
BTL Mode
2
1
1
4
2
RL
Minimum speaker load impedance
PBTL Mode
RPU_I2C
CBypass
CGVDD
I2C pullup resistance on SDA and SCL pins
External capacitance on bypass pins
External capacitance on GVDD pins
4.7
1
10
kΩ
µF
µF
Pin 2, 3, 5, 6, 8, 19
Pin 9, 10
2.2
Limit set by DC-diagnostic
timing
COUT
External capacitance to GND on OUT pins
1
3.3
µF
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7.3 Recommended Operating Conditions (continued)
MIN
TYP
MAX UNIT
Minimum inductance at ISD
current
levels
LO
Output filter inductance
1
µH
7.4 Thermal Information
TAS6424MS-Q1(2)
TAS6424MS-Q1(3)
THERMAL METRIC(1)
DKQ (HSSOP)
DKQ(HSSOP)
56 PINS
37.3
0.4
56 PINS
RθJA
Junction-to-ambient thermal resistance
-
1.1
-
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
15.2
0.2
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
-
ΨJB
14.7
n/a
10
-
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) JEDEC Standard 4 Layer PCB.
(3) Measured using the TAS6424MS-Q1 EVM layout and heat sink. The device is not intended to be used without a heatsink.
7.5 Electrical Characteristics
Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, f =
1kHz, fSW = 2.11 MHz, AES17 Filter, default I2C settings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING CURRENT
IPVDD_IDLE
IVBAT_IDLE
IPVDD_STBY
IVBAT_STBY
IVDD
PVDD idle current
All channels playing, no audio input
All channels playing, no audio input
STANDBY Active, VDD = 0 V
75
90
0.5
4
90
100
1
mA
mA
µA
VBAT idle current
PVDD standby current
VBAT standby current
VDD supply current
STANDBY Active, VDD = 0 V
6
µA
All channels playing, –60-dB signal
15
18
mA
OUTPUT POWER
4 Ω, PVDD = 14.4 V, THD+N = 1%,
TC = 75°C
20
25
38
42
30
40
22
27
40
45
33
45
4 Ω, PVDD = 14.4 V, THD+N = 10%,
TC = 75°C
2 Ω, PVDD = 14.4 V, THD+N = 1%,
TC = 75°C
PO_BTL
Output power per channel, BTL
W
2 Ω, PVDD = 14.4 V, THD+N = 10%,
TC = 75°C
4 Ω, PVDD = 18 V, THD+N = 1%,
TC = 75°C
4 Ω, PVDD = 18 V, THD+N = 10%,
TC = 75°C
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7.5 Electrical Characteristics (continued)
Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, f =
1kHz, fSW = 2.11 MHz, AES17 Filter, default I2C settings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2 Ω, PVDD = 14.4 V, THD+N = 1%,
TC = 75°C
35
40
2 Ω, PVDD = 14.4 V, THD+N = 10%,
TC = 75°C
45
72
80
60
75
50
80
90
65
80
1 Ω, PVDD = 14.4 V, THD+N = 1%,
TC = 75°C
Output power per channel in parallel
mode, PBTL
PO_PBTL
W
1 Ω, PVDD = 14.4 V, THD+N = 10%,
TC = 75°C
2 Ω, PVDD = 18 V, THD+N = 1%,
TC = 75°C
2 Ω, PVDD = 18 V, THD+N = 10%,
TC = 75°C
4 channels operating, 25-W output
power/ch 4 Ω load,PVDD = 14.4 V,
TC = 25°C
EFFP
Power efficiency
86%
AUDIO PERFORMANCE
Zero input, A-weighting, gain level 1,
PVDD = 14.4 V
42
55
67
85
7.5
15
21
29
Zero input, A-weighting, gain level 2,
PVDD = 14.4 V
Vn
Output noise voltage
µV
Zero input, A-weighting, gain level 3,
PVDD = 18 V
Zero input, A-weighting, gain level 4,
PVDD = 18 V
gain level 1, Register 0x01, bit 1-0 =
00
gain level 2, Register 0x01, bit 1-0 =
01
GAIN
Peak Output Voltage/dBFS
V/FS
gain level 3, Register 0x01, bit 1-0 =
10
gain level 4, Register 0x01, bit 1-0 =
11
GAINVAR
Crosstalk
Channel Gain Variation
Channel crosstalk
Gain variation for all gain levels.
-0.5
-0.5
0.5
0.5
dB
dB
PVDD = 14.4 Vdc + 1 VRMS, f = 1
kHz
-90
75
PVDD = 14.4 Vdc + 1 VRMS, f = 1
kHz
PSRR
Power-supply rejection ratio
dB
dB
THD+N
GCH
Total harmonic distortion + noise
Channel-to-channel gain variation
0.02
0
LINE OUTPUT PERFROMANCE
Zero input, A-weighting, channel set
to LINE MODE
Vn_LINEOUT
VO_LINEOUT
THD+N
LINE output noise voltage
LINE output voltage
42
5.5
µV
0dB input, channel set to LINE
MODE
VRMS
Line output total harmonic distortion + VO = 2 VRMS , channel set to LINE
0.01
noise
MODE
DIGITAL INPUT PINS
VIH
VIL
IIH
Input logic level high
70
%VDD
%VDD
µA
Input logic level low
30
15
Input logic current, high
VI = VDD
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7.5 Electrical Characteristics (continued)
Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, f =
1kHz, fSW = 2.11 MHz, AES17 Filter, default I2C settings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IIL
Input logic current, low
VI = 0
-15
µA
PWM OUTPUT STAGE
Not including bond wire and
package resistance
RDS(on)
FET drain-to-source resistance
90
mΩ
OVER VOLTAGE (OV) PROTECTIONI
VPVDD_OV
PVDD overvoltage shutdown
19.3
20
20
0.8
22
23
V
V
V
PVDD overvoltage shutdown
hysteresis
VPVDD_OV_HY S
VVBAT_OV
VBAT overvoltage shutdown
21.5
0.6
VBAT overvoltage shutdown
hysteresis
VVBAT_OV_HY S
UNDER VOLTAGE (UV) PROTECTIONI
VBATUV
VBAT undervoltage shutdown
4
0.2
4
4.5
4.5
V
V
V
V
VBAT undervoltage shutdown
hysteresis
VBATUV_HYS
PVDDUV
PVDD undervoltage shutdown
PVDD undervoltage shutdown
hysteresis
PVDDUV_HY S
0.2
BYPASS VOLTAGES
VGVDD
VAVDD
VVCOM
VVREG
Gate drive bypass pin voltage
7
6
V
V
V
V
Analog bypass pin voltage
Common bypass pin voltage
Regulator bypass pin voltage
2.5
5.5
POWER-ON RESET(POR)
VPOR
VDD voltage for POR
VDD POR recovery hysteresis voltage
2.1
0.5
2.7
V
V
VPOR_HY
OVER TEMPERATURE (OT) PROTECTION
OTW(i)
Channel overtemperature warning
Channel overtemperature shutdown
150
175
°C
°C
OTSD(i)
Global junction overtemperature
warning
OTW
130
°C
Global junction overtemperature
shutdown
OTSD
OTHYS
160
15
°C
°C
Overtemperature hysteresis
LOAD OVER CURRENT PROTECTION
OC Level 1
OC Level 2
4.0
6.0
4.8
7
A
A
ILIM Overcurrent cycle-by-cycle limit
OC Level 1, Any short to supply,
ground, or other channels
7
9
A
A
ISD
Overcurrent shutdown
OC Level 2, Any short to supply,
ground, or other channels
MUTE MODE
GMUTE
Output attenuation
100
7
dB
CLICK AND POP
ITU-R 2k filter, High-Z/MUTE to
Play, Play to Mute/High-Z
VCP
Output click and pop voltage
mV
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7.5 Electrical Characteristics (continued)
Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, f =
1kHz, fSW = 2.11 MHz, AES17 Filter, default I2C settings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mV
V
DC OFFSET
VOFFSET
Output offset voltage
Output DC fault protection
2
5
DC DETECT
DCFAULT
2
2.5
DIGITAL OUTPUT PINS
VOH
VOL
Output voltage for logic level high
I = ±2 mA
90
%VDD
%VDD
Output voltage for logic level low
I = ±2 mA
10
20
Signal delay when output clipping
detected
tDELAY_CLIPDE T
µs
LOAD DIAGNOSTICS
Maximum resistance to detect a short
from OUT pin(s) to PVDD
S2P
S2G
500
Ω
Ω
Maximum resistance to detect a short
from OUT pin(s) to ground
200
SL
Shorted load detection tolerance
Open load
Other channels in Hi-Z
Other channels in Hi-Z
All 4 Channels
±0.5
Ω
Ω
OL
40
70
TDC_DIAG
LO
DC diagnostic time
Line output
230
ms
kΩ
ms
Ω
6
TLINE_DIAG
Line output diagnostic time
40
Offset
±0.5
0.25
ACIMP
AC impedance accuracy
AC diagnostic time
Gain linearity, ƒ = 19 kHz, RL = 2 Ω
to 16 Ω
TAC_DIAG
All 4 Channels
520
300
ms
µs
I2C_ADDR PINS
Time delay needed for I2C address
set-up
tI2C_ADDR
I2C CONTROL PORT
Bus free time between start and stop
conditions
tBUS
1.3
µs
tHOLD1
tHOLD2
Hold time, SCL to SDA
Hold time, start condition to SCL
0
ns
µs
0.6
I2C startup time after VDD power on
reset
tSTART
12
ms
tRISE
tFALL
tSU1
tSU2
tSU3
tW(H)
tW(L)
Rise time, SCL and SDA
300
300
ns
ns
ns
µs
µs
µs
µs
Fall time, SCL and SDA
Setup, SDA to SCL
100
0.6
0.6
0.6
1.3
Setup, SCL to start condition
Setup, SCL to stop condition
Required pulse duration SCL high
Required pulse duration SCL low
SERIAL AUDIO PORT
DMCLK, DSCLK Allowable input clock duty cycle
fMCLK
fMCLK_Max
tSCY
0.45
128
0.5
0.55
512
25
Supported MCLK frequencies
Maximum frequency
128, 256, or 512
xFS
MHz
ns
SCLK pulse cycle time
40
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7.5 Electrical Characteristics (continued)
Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, f =
1kHz, fSW = 2.11 MHz, AES17 Filter, default I2C settings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tSCL
tSCH
tRISE/FALL
tSF
SCLK pulse-with LOW
SCLK pulse-with HIGH
Rise and fall time
16
ns
16
ns
<5
ns
Required FSYNC to SCLK rising edge
FSYNC rising edge to SCLK edge
DATA set-up time
8
8
8
8
ns
tFS
ns
tDS
ns
tDH
DATA hold time
ns
Required SDIN hold time after SCLK
rising edge
th
15
15
ns
ns
pf
Required SDIN setup time before
SCLK rising edge
tsu
Ci
Input capacitance, pins MCLK, SCLK,
FSYNC, SDIN1, SDIN2
10
FSYNC = 44.1 kHz or 48 kHz
FSYNC = 96 kHz
30
12
Latency from input to output measured
in FSYNC sample count
TLA
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7.6 Typical Characteristics
TA = 25 °C, VVDD = 3.3 V, VBAT = PVDD = 14.4 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, fSW = 2.1 MHz, AES17 filter, default I2C
settings, see 图 10-2 and 图 10-3 (unless otherwise noted)
0
0
-20
Ch 1 to Ch 2
Ch 2 to Ch 1
-20
-40
-40
-60
-60
-80
-80
-100
-120
-100
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency
10k
D002
D068
PO = 1 W
图 7-1. Crosstalk vs Frequency
PO = 1 W
图 7-2. PVDD PSRR vs Frequency
0
-20
10
4 : Load
5
2
1
-40
0.5
0.2
0.1
-60
0.05
0.02
0.01
-80
0.005
-100
0.002
0.001
20
100
1k
10k 20k
-120
Frequency (Hz)
20
100
1k
Frequency
10k 20k
D005
D070
PO = 1 W
fSW = 384 kHz
PO = 1 W
图 7-4. THD+N vs Frequency
图 7-3. VBAT PSRR vs Frequency
10
2 W Load
4 W Load
10
5
4 : Load
2
1
1
0.1
0.5
0.2
0.1
0.05
0.02
0.01
0.01
0.005
0.002
0.001
0.001
10m
100m
1
10 20
20
100
1k
Frequency (Hz)
10k 20k
Output Power (W)
D009
D006
PO = 1 W
fSW = 2.1 MHz
fSW = 384 kHz
图 7-5. THD+N vs Frequency
图 7-6. THD+N vs Power
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7.6 Typical Characteristics (continued)
TA = 25 °C, VVDD = 3.3 V, VBAT = PVDD = 14.4 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, fSW = 2.1 MHz, AES17 filter, default I2C
settings, see 图 10-2 and 图 10-3 (unless otherwise noted)
10
2 W Load
4 W Load
100
80
60
40
20
0
2 : Load
4 : Load
1
0.1
0.01
10m
100m
1
Output Power (W)
10
100
D010
5
10
15
18
Supply Voltage (V)
fSW = 2.1 MHz
D013
图 7-7. THD+N vs Power
10% THD
fSW = 384 kHz
图 7-8. Output Power vs Supply Voltage
60
50
40
30
20
10
0
160
150
140
130
120
110
100
90
80
70
60
50
Gain Level 1
2 W Load
4 W Load
Gain Level 2
Gain Level 3
Gain Level 4
40
30
20
10
0
5
7
9
11 13
Supply Voltage (V)
15
17 18
5
7
9
11 13
Supply Voltage (V)
15
17 18
D062
D083
A-weighted Noise
fSW = 2.1 MHz
10% THD
图 7-10. Noise vs Supply voltage
图 7-9. Output Power vs Supply Voltage
100
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
PVDD = 14.4 V
80 100
PVDD = 14.4 V
80 100
0
230
40 60
Output Power (W)
0
230
40 60
Output Power (W)
D065
D066
4 Ω
fSW = 384 kHz
4 Ω
fSW = 2.1 MHz
图 7-11. PVDD Power Efficiency vs Total Output Power
图 7-12. PVDD Power Efficiency vs Total Output Power
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7.6 Typical Characteristics (continued)
TA = 25 °C, VVDD = 3.3 V, VBAT = PVDD = 14.4 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, fSW = 2.1 MHz, AES17 filter, default I2C
settings, see 图 10-2 and 图 10-3 (unless otherwise noted)
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
PVDD = 14.4 V
80 100
PVDD = 14.4 V
80 100
0
320
40 60
Output Power (W)
0
230
40 60
Output Power (W)
D063
D064
2 Ω
fSW = 384 kHz
2 Ω
fSW = 2.1 MHz
图 7-13. PVDD Power Efficiency vs Total Output Power
图 7-14. PVDD Power Efficiency vs Total Output Power
100
50
40
30
20
10
95
90
85
80
75
70
65
60
FPWM = 2.1 MHz
15 18
0
5
10
6
8
10 12
Supply Voltage (V)
14
16
18
Supply Voltage (V)
D071
D026
图 7-16. VBAT Idle Current vs Voltage
图 7-15. PVDD Idle Current vs Voltage
10
1
5
4
3
2
1
0
2 W Load
4 W Load
0.1
0.01
0.001
20
100
1k
Frequency (Hz)
10k 20k
5
10
Supply Voltage (V)
15
18
D028
D073
1 W
fSW = 384 kHz
图 7-17. PVDD Standby Current vs Voltage
图 7-18. PBTL THD+N vs Frequency
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7.6 Typical Characteristics (continued)
TA = 25 °C, VVDD = 3.3 V, VBAT = PVDD = 14.4 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, fSW = 2.1 MHz, AES17 filter, default I2C
settings, see 图 10-2 and 图 10-3 (unless otherwise noted)
10
10
1
2 W Load
4 W Load
2 W Load
4 W Load
1
0.1
0.1
0.01
0.01
0.001
0.001
20
100
1k
Frequency (Hz)
10k 20k
10m
100m
1
Output Power (W)
10 20
100
D029
D032
PO = 1 W
fSW = 2.1 MHz
fSW = 384 kHz
图 7-19. PBTL THD+N vs Frequency
图 7-20. PBTL THD+N vs Power
10
1
90
80
70
60
50
40
30
20
10
0
2 W Load
4 W Load
0.1
0.01
2 W Load
4 W Load
0.001
10m
100m
1
Output Power (W)
10
100
5
10
Supply Voltage (V)
15
18
D008
D078
fSW = 2.1 MHz
10 % THD
fSW = 384 kHz
图 7-21. PBTL THD+N vs Power
图 7-22. PBTL Output Power vs Voltage
90
80
70
60
50
40
30
20
10
0
20
10
0
2 W Load
4 W Load
2 W Load
4 W Load
5
10
Supply Voltage (V)
15
18
0
20
40 60
Total Output Power (W)
80
100
D079
D080
10 % THD
fSW = 2.1 MHz
fSW = 384 kHz
图 7-23. PBTL Output Power vs Voltage
图 7-24. Power Dissipation vs Total Output Power
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7.6 Typical Characteristics (continued)
TA = 25 °C, VVDD = 3.3 V, VBAT = PVDD = 14.4 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, fSW = 2.1 MHz, AES17 filter, default I2C
settings, see 图 10-2 and 图 10-3 (unless otherwise noted)
20
2 W Load
4 W Load
10
0
0
20
40 60
Total Output Power (W)
80
100
D081
fSW = 2.1 MHz
图 7-25. Power Dissipation vs Total Output Power
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8 Parameter Measurement Information
The parameters for the TAS6424MS-Q1 device were measured using the circuit in 图 10-2.
For measurements with 2.1 MHz switching frequency the 3.3 µH inductor from the TAS6424MS-Q1 EVM is
used.
For measurements with 384 kHz switching frequency a 10 µH inductor was used.
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9 Detailed Description
9.1 Overview
The TAS6424MS-Q1 is a four-channel digital-input Class-D audio amplifier specifically tailored for use in the
in the automotive industry. The device is designed for vehicle battery operation. This ultra-efficient Class-D
technology allows for reduced power consumption, reduced PCB area and reduced heat. The device realizes an
audio sound-system design with smaller size and lower weight than traditional Class-AB solutions.
The core design blocks are as follows:
•
•
•
•
•
•
•
•
•
•
Serial audio port
Clock management
High-pass filter and volume control
Pulse width modulator (PWM) with output stage feedback
Gate drive
Power FETs
Diagnostics
Protection
Power supply
I2C serial communication bus
9.2 Functional Block Diagram
VDD
VCOM VREG
VBAT
GVDD
PVDD
MUTE
Gate Drive
Regulator
Reference
Regulators
STANDBY
Digital Core
WARN
Closed Loop Class D Amplifier
OUT_1P
OUT_1M
Channel 1
Powerstage
FAULT
MCLK
Digital to PWM
OUT_2P
OUT_2M
OUT_3P
OUT_3M
Channel 2
Powerstage
SCLK
Serial
Volume Control
-100 to +24 dB
0.5 dB steps
Gate
Drives
Audio
Port
FSYNC
SDIN1
SDIN2
Channel 3
Powerstage
Clip
Detection
OUT_4P
OUT_4M
Channel 4
Powerstage
PLL and Clock
Management
Protection
DC Load Diagnostics
Short to GND
Short to Power
Open Load
Overcurrent Limit
Overcurrent
SCL
SDA
2
I C Control
Overtemperature
I2C_ADDR0
I2C_ADDR1
Overvoltage and Undervoltage
DC Detection
Shorted Load
AC Load Diagnostics
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9.3 Feature Description
9.3.1 Serial Audio Port
The serial audio port (SAP) receives audio in either I2S, left justified, right justified, or TDM formats.
Settings for the serial audio port are programmed in the SAP control register (address 0x03), see the 节 9.6.4
section.
图 9-1 shows the digital audio data connections for I2S and TDM8 mode for an eight channel system.
i2S
TDM8
SOC
MCLK
SOC
MCLK
Device A
MCLK
Device A
MCLK
SCLK
FSYNC
DATA1
DATA2
DATA3
DATA4
SCLK
SCLK
FSYNC
DATA
SCLK
FSYNC
SDIN1
SDIN2
FSYNC
SDIN1
SDIN2
Device B
Device B
MCLK
SCLK
MCLK
SCLK
FSYNC
SDIN1
SDIN2
FSYNC
SDIN1
SDIN2
图 9-1. Digital-Audio Data Connection
9.3.1.1 I2S Mode
I2S timing uses the FSYNC pin to define when the data being transmitted is for the left channel and when the
data is for the right channel. The FSYNC pin is low for the left channel and high for the right channel. The bit
clock, SCLK, runs at 32 × fS or 64 × fS and is used to clock in the data. A delay of one bit clock occurs from
the time the FSYNC signal changes state to the first bit of data on the data lines. The data is presented in
2s-complement form (MSB-first). The data is valid on the rising edge of the bit clock and is used to clock in the
data.
9.3.1.2 Left-Justified Timing
Left-justified (LJ) timing also uses the FSYNC pin to define when the data being transmitted is for the left
channel and when the data is for the right channel. The FSYNC pin is high for the left channel and low for the
right channel. A bit clock running at 32 × fS or 64 × fS is used to clock in the data. The first bit of data appears
on the data lines at the same time FSYNC toggles. The data is written MSB-first and is valid on the rising edge
of the bit clock. Digital words can be 16-bits or 24-bits wide and pad any unused trailing data-bit positions in the
left-right (L/R) frame with zeros.
9.3.1.3 Right-Justified Timing
Right-justified (RJ) timing also uses the FSYNC pin to define when the data being transmitted is for the left
channel and when the data is for the right channel. The FSYNC pin is high for the left channel and low for the
right channel. A bit clock running at 32 × fS or 64 × fS is used to clock in the data. The first bit of data appears on
the data 8-bit clock periods (for 24-bit data) after the FSYNC pin toggles. In RJ mode the LSB of data is always
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clocked by the last bit clock before the FSYNC pin transitions. The data is written MSB-first and is valid on the
rising edge of bit clock. The device pads the unused leading data-bit positions in the L/R frame with zeros.
9.3.1.4 TDM Mode
TDM mode supports 4 or 8 channels of audio data. The TDM mode is automatically selected when the TDM
clocks are present. The device can be configured through I2C to use different stereo pairs in the TDM data
stream. The TDM mode supports 16-bit, 24-bit, and 32-bit input data lengths
In TDM mode, SCLK must be 128 x fs or 256 x fs, depending on the TDM slot size. In TDM mode SCLK and
MCLK can be connected together. If SCLK and MCLK are connected together or the frequency of SCLK and
MCLK is equal, FSYNC should be minimum 2 MCLK pulses long.
In TDM mode, the SDIN1 pin (pin 15) is used for digital audio data. TI recommends to connect the unused
SDIN2 pin (pin 16) to ground. 表 9-1 lists register settings for the TDM channel selection.
表 9-1. TDM Channel Selection
REGISTER SETTING
TDM8 CHANNEL SLOT
0x03
BIT 5
0x03
BIT 3
1
2
3
4
5
6
7
8
0
1
0
1
0
0
1
1
CH1
—
CH2
—
CH3
—
CH4
—
—
CH1
—
—
CH2
—
—
CH3
—
—
CH4
—
CH3
—
CH4
—
CH1
—
CH2
—
CH3
CH4
CH1
CH2
If PBTL mode is programmed for channel 1/2 or channel 3/4 the datasource can be set according to 表 9-2.
表 9-2. TDM Channel Selection in PBTL Mode
REGISTER SETTING
TDM8 CHANNEL SLOT
0x03
BIT 5
0x03
BIT 3
0x21
BIT 6
1
2
3
4
5
6
7
8
PBTL
CH1/2
PBTL
CH3/4
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
—
—
—
—
—
—
—
—
—
—
—
—
PBTL
CH1/2
PBTL
CH3/4
0
1
1
0
0
1
1
—
—
—
—
—
—
PBTL
CH1/2
PBTL
CH3/4
—
—
—
—
—
—
PBTL
CH1/2
PBTL
CH3/4
—
—
—
—
—
—
PBTL
CH3/4
PBTL
CH1/2
—
—
—
—
—
—
PBTL
CH3/4
PBTL
CH1/2
—
—
—
—
—
—
PBTL
CH3/4
PBTL
CH1/2
—
—
—
—
PBTL
CH3/4
PBTL
CH1/2
—
—
9.3.1.5 Supported Clock Rates
The device supports MCLK rates of 128 × fS, 256 × fS, or 512 × fS.
The device supports SCLK rates of 32 × fS or 64 × fS in I2S, LJ or RJ modes or 128 × fS, or 256 × fS in TDM
mode.
The device supports FSYNC rates of 44.1 kHz, 48 kHz, or 96 kHz.
The maximum clock frequency is 25 MHz. Therefore, for a 96 kHz FSYNC rate, the maximum MCLK rate is
256 × fS.
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Duty cycle of 50% is required for 128x FSYNC, for 256x and 512x 50% duty cycle is not required.
9.3.1.6 Audio-Clock Error Handling
When any kind of clock error, MCLK-FSYNC or SCLK-FSYNC ratio, or clock halt is detected, the device puts
all channels into the Hi-Z state. When all audio clocks are within the expected range, the device automatically
returns to the state it was in. See the Electrical Characteristics table for timing requirements.
FSYNC
(Input)
0.5 × DVDD
t
t
t
FS
SCH
SCL
SCLK
(Input)
0.5 × DVDD
t
t
SF
SCY
DATA
(Input)
0.5 × DVDD
t
t
DH
DS
图 9-2. Serial Audio Timing
1/f
S
FSYNC
SCLK
L-channel
R-channel
Audio data word = 16 bit, SCLK = 64 f
S
S
0
1
14 15
0
1
14 15
SDIN
MSB
LSB
MSB
LSB
Audio data word = 24 bit, SCLK = 64 f
0
1
22 23
0
1
22 23
SDIN
MSB
LSB
MSB
LSB
Audio data word = 32 bit, SCLK = 64 f
S
0
1
30 31
0
1
30 31
LSB
SDIN
MSB
LSB
MSB
图 9-3. Left-Justified Audio Data Format
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1/f
S
FSYNC
L-channel
R-channel
SCLK
Audio data word = 16 bit, SCLK = 64 f
S
S
0
1
14 15
0
1
14 15
SDIN
MSB
LSB
MSB
LSB
Audio data word = 24 bit, SCLK = 64 f
0
1
22 23
0
1
22 23
SDIN
MSB
LSB
MSB
LSB
Audio data word = 32 bit, SCLK = 64 f
S
0
1
30 31
LSB
0
1
30 31
LSB
SDIN
MSB
MSB
图 9-4. I2S Audio Data Format
1/Fs (256 sbclks)
FSYNC
SCLK
SDIN (I2S mode)
23
22
1
0
23
22
1
0
23
22
1
0
23
22
32 SCLK
32 SCLK
8 blocks of 32 SCLK
Audio Data Format: TDM8 mode
图 9-5. TDM8 Audio Data Format
9.3.2 High-Pass Filter
Direct-current (DC) content in the audio signal can damage speakers. The data path has a high-pass filter to
remove any DC from the input signal. The corner frequency is selectable from 4 Hz, 8 Hz, or 15 Hz to 30 Hz with
bits 0 through 3 in register 0x26. The default value of –3 dB is approximately 4 Hz for 44.1 kHz or 48 kHz and
approximately 8 Hz for 96 kHz sampling rates.
9.3.3 Volume Control and Gain
Each channel has an independent digital-volume control with a range from –100 dB to +24 dB with 0.5-dB steps.
The volume control is set through I2C. The gain-ramp rate is programmable through I2C to take one step every 1,
2, 4, or 8 FSYNC cycles.
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The peak output-voltage swing is also configurable in the gain control register through I2C. The four gain settings
are 7.5 V, 15 V, 21 V, and 29 V. TI recommends selecting the lowest possible for the expected PVDD operation
to optimize output noise and dynamic range performance.
9.3.4 High-Frequency Pulse-Width Modulator (PWM)
The PWM converts the PCM input data into a switched signal of varying duty cycle. The PWM modulator is
an advanced design with high bandwidth, low noise, low distortion, and excellent stability. The output switching
rate is synchronous to the serial audio-clock input and is programmed through I2C to be between 8× and 48×
the input-sample rate. The option to switch at high frequency allows the use of smaller and lower cost external
filtering components. 表 9-3 lists the switch frequency options for bits 4 through 6 in the Miscellaneous Control 2
Register (address 0x02).
表 9-3. Output Switch Frequency Option
INPUT SAMPLE RATE
BIT 6:4 SETTINGS
000
001
010 to 100
101
110
111
44.1 kHz
48 kHz
96 kHz
352.8 kHz
384 kHz
384 kHz
441 kHz
480 kHz
480 kHz
RESERVED
RESERVED
RESERVED
1.68 MHz
1.82 MHz
1.82 MHz
1.94 MHz
2.11 MHz
2.11 MHz
2.12 MHz
Not supported
Not supported
9.3.5 Channel-to-Channel Phase Control
The TAS6424MS-Q1 has configurable output PWM phase control to manage conducted and radiated emissions.
This feature allows the channel output PWM phase offset, relative to other channels, to be changed..
When the connected output loads have an impedance of 4 Ω or larger, a channel phase offset of 180 degrees,
210 degrees, 225 degrees or 240 degrees can be selected. For loads with an impedance of less than 4 Ω, only
the channel phase offsets of 210 degrees, 225 degrees or 240 degrees should be selected and the default value
of 180 degree needs to be adjusted.
The phase options available can be found in Miscellaneous Control 2 Register (address = 0x02) [default = 0x62].
9.3.6 Gate Drive
The gate driver accepts the low-voltage PWM signal and level shifts it to drive a high-current, full-bridge,
power-FET stage. The device uses proprietary techniques to optimize EMI and audio performance.
The gate-driver power-supply voltage, GVDD, is internally generated and a decoupling capacitor is connected at
pin 9 and pin 10.
The full H-bridge output stages use only NMOS transistors. Therefore, bootstrap capacitors are required for the
proper operation of the high side NMOS transistors. A 1-µF ceramic capacitor of quality X7R or better, rated
for at least 16 V, must be connected from each output to the corresponding bootstrap input (see the application
circuit diagram in 图 10-2).
The bootstrap capacitors connected between the BST pins and corresponding output function as a floating
power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching
cycle, the bootstrap capacitors hold the gate-to-source voltage high keeping the high-side MOSFETs turned on.
9.3.7 Power FETs
The BTL output for each channel comprises four N-channel 90 mΩ FETs for high efficiency and maximum power
transfer to the load. These FETs are designed to handle the fast switching frequency and large voltage transients
during load dump.
9.3.8 Load Diagnostics
The device incorporates both DC-load and AC-load diagnostics, which are used to determine the status of
the load. The DC diagnostics are turned on by default, but if a fast startup without diagnostics is required,
the DC diagnostics can be bypassed through I2C. The DC diagnostics runs when any channel is directed to
leave the Hi-Z state and enter the MUTE or PLAY state. The DC diagnostics can also be enabled manually to
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run on any or all channels, even if the other channels are playing audio. DC Diagnostics can be started from
any operating condition, but if the channel is in PLAY state, then the time to complete the diagnostic is longer
because the device must ramp down the audio signal of that channel before transitioning to the Hi-Z state.
The DC diagnostics are available as soon as the device supplies are within the recommended operating range.
The DC diagnostics do not rely on the audio input clocks to be available to function. DC Diagnostic results are
reported for each channel separately through the I2C registers.
9.3.8.1 DC Load Diagnostics
The DC load diagnostics are used to verify the load connected. The DC diagnostics consists of four tests:
short-to-power (S2P), short-to-ground (S2G), open-load (OL), and shorted-load (SL). The S2P and S2G tests
trigger if the impedance to GND or a power rail is below that specified in the Electrical Characteristics section.
The diagnostic detects a short to vehicle battery, even when the supply is boosted. The SL test has an
I2C-configurable threshold depending on the expected load to be connected. Because the speakers connected
to each channel might be different, each channel can be assigned a unique threshold value. The OL test reports
if the select channel has a load impedance greater than the limits in the Electrical Characteristics section.
Open Load
Open Load Detected
OL Maximum
Open Load (OL)
Detection Threshold
Normal or Open Load
May Be Detected
OL Minimum
SL Maximum
SL Minimum
Normal Load
Play Mode
Shorted Load (SL)
Detection Threshold
Normal or Shorted Load
May Be Detected
Shorted Load
Shorted Load Detected
图 9-6. DC Load Diagnostic Reporting Thresholds
9.3.8.2 Line Output Diagnostics
The device also includes an optional test to detect a line-output load. A line-output load is a high-impedance load
that is above the open-load (OL) threshold such that the DC-load diagnostics report an OL condition. After an OL
condition is detected on a channel, if the line output detection bit is also set, the channel checks if a line-output
load is present as well. This test is not pop free, so if an external amplifier is connected it should be muted.
9.3.8.3 AC Load Diagnostics
The AC load diagnostic is used to determine the proper connection of a capacitively-coupled speaker or tweeter
when used with a passive crossover. The AC load diagnostic is controlled through I2C. The AC diagnostics
requires an external input signal and reports the approximate load impedance and phase. The selected signal
frequency should create current flow through the desired speaker for proper detection. If multiple channels must
be tested, the diagnostics should be run in series. The AC load-diagnostic test procedure is as follows.
9.3.8.3.1 Impedance Magnitude Measurement
For load-impedance detection, use the following test procedure:
1. Set the channels to be tested into the Hi-Z state.
2. Set the AC_DIAGS_LOOPBACK bit (bit 7 in register 0x16) to 0.
3. Apply a full-scale input signal from the DSP for the tested channels with the desired frequency
(recommended 10 kHz to 20 kHz).
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备注
The device ramps the signal up and down automatically to prevent pops and clicks.
4. Set the device into the AC diagnostic mode (set bit 3 through bit 0 as needed in register 0x15 to 1 for CH1 to
CH4. (For PBTL mode, test channel 1 for PBTL12 and channel 3 for PBTL34))
5. Read back the AC impedance (register 0x17 through register 0x1A).
When the test is complete, the channel reporting register indicates the status change from the AC diagnostic
mode to the Hi-Z state. The detected impedance is stored in the appropriate I2C register.
The hexadecimal register value must be converted to decimal and used to calculate the impedance magnitude
using the following equation:
AC Magnitude Calculation
Impedance _ CHxì2.371mV
(Gain)(I mA)
Channelx Impedance =
(Ohms)
(1)
9.3.8.3.2 Impedance Phase Reference Measurement
The first stage to determine the AC phase is to utilize the built-in loopback mode to determine the reference
value for the phase measurement. This reference nullifies any phase offset in the device and measure only the
phase of the load. This is measured for channel 1 and 3 only. Channel 2 uses the results of channel 1 for the
calculations. Channel 4 uses the results of channel 3 for the calculations. Measure channel 1 and channel 3
sequentially, they cannot be measured at the same time.
For loopback delay detection, use the following test procedure for either BTL mode or PBTL mode:
•
BTL mode
1. Set the AC_DIAGS_LOOPBACK bit (bit 7 in register 0x16) to 1 to enable AC loopback mode.
2. Apply a 0-dBFS 19 kHz signal and enable AC load diagnostics. CH1 and CH2 reuse the AC sensing loop
of CH1 (set bit 3 in register 0x15 to 1). CH3, CH4 reuse the AC sensing loop of CH3 (set bit 1 in register
0x15 to 1).
3. Read back the 16bit hexadecimal, AC_LDG_PHASE1 value. Register 0x1B holds the MSB and register
0x1C holds the LSB.
4. For channel 1/2 set bit 3 in register 0x15 to 0. For channel 3/4 set bit 1 in register 0x15 to 0.
PBTL mode
•
1. Set the AC_DIAGS_LOOPBACK bit (bit 7 in register 0x16) to 1 to enable AC loopback mode.
2. Set the PBTL CH12 and PBTL CH34 bits (see register 0x00) to 0 without toggling SDz pin to enter BTL
mode only for load diagnostics.
3. Apply a 0 dBFS 19 kHz signal and enable AC load diagnostics. For PBTL_12, enable the AC sensing
loop of CH1 (set bit 3 in register 0x15 to 1). For PBTL_34, enable the AC sensing loop of CH3 (set bit 1 in
register 0x15 to 1).
4. Read back the AC_LDG_PHASE1 value. Register 0x1B holds the MSB and register 0x1C holds the LSB.
5. Set the PBTL CH12 and PBTL CH34 bits (see register 0x00) to 1 to go back to PBTL mode for load
diagnostics.
6. For PBTL_12 set bit 3 in register 0x15 to 0. For PBTL_34 set bit 1 in register 0x15 to 0.
When the test is complete, the channel reporting register indicates the status change from the AC diagnostic
mode to the Hi-Z state. The detected impedance is stored in the appropriate I2C register.
9.3.8.3.3 Impedance Phase Measurement
After performing the phase reference measurements, measure the phase of the speaker load. This is performed
in the same manner as the reference measurements, except the loopback is disabled in bit 7 register 0x16.
Previously, the phase reference is measured on channel 1 and channel 3. In this test stage all four channels are
measured. Measure the channels sequentially as they cannot be measured at the same time.
For loopback delay detection, use the following test procedure for either BTL mode or PBTL mode:
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•
BTL mode
1. Set the AC_DIAGS_LOOPBACK bit (bit 7 in register 0x16) to 0 to disable AC loopback mode.
2. Apply a 0-dBFS 19 kHz signal and enable AC load diagnostics. CH1 and CH2 reuse the AC sensing loop
of CH1 (set bit 3 in register 0x15 to 1). CH3, CH4 reuse the AC sensing loop of CH3 (set bit 1 in register
0x15 to 1).
3. Read back the 16 bit hexadecimal, AC_LDG_PHASE1 value. Register 0x1B holds the MSB and register
0x1C holds the LSB.
4. Read back the hexadecimal stimulus value, STI. register 0x1D holds the MSB and register 0x1E holds
the LSB.
5. For channel 1/2 set bit 3 in register 0x15 to 0. For channel 3/4 set bit 1 in register 0x15 to 0.
When the test is complete, the channel reporting register indicates the status change from the AC diagnostic
mode to the Hi-Z state. The detected impedance is stored in the appropriate I2C register.
PBTL mode
•
1. Set the AC_DIAGS_LOOPBACK bit (bit 7 in register 0x16) to 0 to disable AC loopback mode.
2. Set the PBTL CH12 and PBTL CH34 bits (see register 0x00) to 0 without toggling SDz pin to enter BTL
mode only for load diagnostics.
3. Apply a 0 dBFS 19 kHz signal and enable AC load diagnostics. For PBTL_12, enable the AC sensing
loop of CH1 (set bit 3 in register 0x15 to 1). For PBTL_34, enable the AC sensing loop of CH3 (set bit 1 in
register 0x15 to 1).
4. Read back the AC_LDG_PHASE1 value. register 0x1B holds the MSB and register 0x1C holds the LSB.
5. Read back the hexadecimal stimulus value, STI. register 0x1D holds the MSB and register 0x1E holds
the LSB
6. Set the PBTL CH12 and PBTL CH34 bits (see register 0x00) to 1 to go back to PBTL mode for load
diagnostics.
7. For PBTL_12 set bit 3 in register 0x15 to 0. For PBTL_34 set bit 1 in register 0x15 to 0.
The AC phase in degrees is calculated with the AC Phase Calculation equation:
:
;
2D=OA_%*T .$- F 2D=OA_%*T(.&/)
2D=OA_%*T = 360(
)
56+_%*T(.&/)
(2)
Where:
•
•
•
Phase_CHx(LBK) is the reference phase measurement. LBK stands for loopback mode
Phase_CHx(LDM) is the phase measure of the load. LDM stands for load mode
STI_CHx(LDM) is the stimulus value
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表 9-4. AC Impedance Code to Magnitude
MAPPING FROM CODE
TO MAGNITUDE (Ω/
Code)
MEASUREMENT RANGE
SETTING
GAIN AT 19 kHz
I(A)
(Ω)
Gain = 4, I = 10 mA
(recommended)
4.28
4.28
1
0.01
0.019
0.01
12
6
0.05832
0.0307
0.2496
0.1314
Gain = 4, I = 19 mA
Gain = 1, I = 10 mA
(recommended)
48
24
Gain = 1, I = 19 mA
1
0.019
9.3.9 Protection and Monitoring
9.3.9.1 Overcurrent Limit (ILIMIT
The overcurrent limit terminates each PWM pulse to limit the output current flow when the current limit (ILIMIT
)
)
is exceeded. Power is limited, but operation continues without disruption and prevents undesired shutdown for
transient music events. ILIMIT is not reported as a fault condition to either registers or the FAULT pin but as
warning condition to the WARN pin and ILIMIT Status Register (address = 0x25). Each channel is independently
monitored and limited. The two programable levels can be set by bit 4 in the Miscellaneous Control 1 register
(address 0x01).
9.3.9.2 Overcurrent Shutdown (ISD
)
If the output load current reaches ISD, such as an output short to GND, then a peak current limit occurs, which
shuts down the channel. The time to shutdown the channel varies depending on the severity of the short
condition. The affected channel is placed into the Hi-Z state, the fault is reported to the register, and the FAULT
pin is asserted. The device remains in this state until the CLEAR FAULT bit is set in Miscellaneous Control 3
Register, 0x21 bit 7. After clearing this bit and if the diagnostics are enabled, the device automatically starts
diagnostics on the channel and, if no load failure is found, the device restarts. If a load fault is found the device
continues to rerun the diagnostics once per second. Because this hiccup mode uses the diagnostics, no high
current is created. If the diagnostics are disabled, the device sets the state for that channel to Hi-Z and requires
the MCU to take the appropriate action, setting the CLEAR FAULT bit after the fault got removed, in order to
return to Play state.
Two programable levels can be set by bit 4 in the Miscellaneous Control 1 register (address 0x01).
9.3.9.3 DC Detect
This circuit detects a DC offset continuously during normal operation at the output of the amplifier. If the DC
offset exceeds the threshold, that channel is placed in the Hi-Z state, the fault is reported to the I2C register, and
the FAULT pin is asserted. A register bit can be used to mask reporting to the FAULT pin if required.
9.3.9.4 Clip Detect
The clip detect is reported on the WARN pin if 100% duty-cycle PWM is reached for a minimum number of PWM
cycles set by the Clip Window Register (address 0x23). The default is 20 PWM cycles. If any channel is clipping,
the clipping is reported to the pin. The clip detect is latched and can be cleared by I2C. Masking the clip reporting
to the pin is possible through I2C. If desired, the Clip Detect can be configured to be non-latching in Clip Control
Register (address = 0x22). In non-latching mode, Clip Detect is reported when the PWM duty cycle reaches
100%, and deasserted once the PWM duty cycle falls below 100%.
9.3.9.5 Global Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD)
Four overtemperature warning levels are available in the device (see the Register Maps section for thresholds).
When the junction temperature exceeds the warning level, the WARN pin is asserted, unless the mask bit has
been set to disable reporting. The device functions until the OTSD value is reached at which point all channels
are placed in the Hi-Z state, and the FAULT pin is asserted. By default, the device remains shut down after the
temperature drops to normal levels. This configuration can be changed in bit 3 of the Miscellaneous Control 3
Register (address = 0x21) to auto-recovery: When the junction temperature returns to normal levels, the device
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automatically recovers and places the channel into the state indicated by the state control register. Note that
even in auto-recovery configuration the FAULT pin remains asserted until the CLEAR FAULT bit (bit 7) is set in
register 0x21.
9.3.9.6 Channel Overtemperature Warning [OTW(i)] and Shutdown [OTSD(i)]
In addition to the global OTW, each channel also has an individual overtemperature warning and shutdown. If
a channel exceeds the OTW(i) threshold, the warning register bit is set as the WARN pin is asserted, unless
the mask bit has been set to disable reporting. If the channel temperature exceeds the OTSD(i) threshold then
the channel goes to the Hi-Z state and either remains there or auto-recovers to the state indicated by the state
control register when the temperature drops below the OTW(i) threshold, depending on the setting of bit 3 of the
Miscellaneous Control 3 Register (address = 0x21).
9.3.9.7 Undervoltage (UV) and Power-On-Reset (POR)
The undervoltage (UV) protection detects low voltages on the PVDD and VBAT pins. In the event of an UV
condition, the FAULT pin is asserted, and the I2C register is updated. A power-on reset (POR) on the VDD
pin causes the I2C to goes to the high-impedance (Hi-Z) state, and all registers are reset to default values. At
power-on or after a POR event, the POR warning bit and WARN pin are asserted.
9.3.9.8 Overvoltage (OV) and Load Dump
The overvoltage (OV) protection detects high voltages on the PVDD pin. If the PVDD pin reaches the OV
threshold, the FAULT pin is asserted and the I2C register is updated. The device can withstand 40 V load-dump
voltage spikes.
9.3.10 Power Supply
The device has three power supply inputs, VDD, PVDD, and VBAT, which are described as follows:
VDD This pin is a 3.3V supply pin that provides power to the low voltage circuitry.
VBAT This pin is a higher voltage supply that can be connected to the vehicle battery or the regulated voltage
rail in a boosted system within the recommended limits. For best performance, this rail should be 10 V or
higher. See the Recommended Operating Conditions table for the maximum supply voltage. This supply
rail is used for higher voltage analog circuits but not the output FETs.
PVDD This pin is a high-voltage supply that can either be connected to the vehicle battery or to another voltage
rail in a boosted system. The PVDD pin supplies the power to the output FETs and can be within the
recommended operating limits, even if that is below the VBAT supply, to allow for dynamic voltage
systems.
Several on-chip regulators are included for generating the voltages necessary for the internal circuitry. The
external pins are provided only for bypass capacitors to filter the supply and should not be used to power other
circuits.
The device can withstand fortuitous open ground and power conditions within the absolute maximum ratings
for the device. Fortuitous open ground usually occurs when a speaker wire is shorted to ground, allowing for a
second ground path through the body diode in the output FETs.
9.3.10.1 Vehicle-Battery Power-Supply Sequence
Power-Up Sequence
In a typical system, the VBAT and PVDD supplies are both connected to the vehicle battery and power up at the
same time. The VDD supply should be applied after the VBAT and PVDD supplies are within the recommended
operating range.
9.3.10.2 Power-Down Sequence
To power-down the device, first set the STANDBY pin low for at least 15ms before removing PVDD, VBAT or
VDD. After 15ms, the power supplies can be removed.
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9.3.10.3 Boosted Power-Supply Sequence
In this case, the VBAT and PVDD inputs are not connected to the same supply.
When powering up, apply the VBAT supply first, the VDD supply second, and the PVDD supply last.
When powering down, first set the STANDBY pin low for at least 15ms before removing PVDD, VBAT or VDD.
After 15 ms, the power supplies can be removed.
9.3.11 Hardware Control Pins
The device has four pins for control and device status: FAULT, MUTE, WARN, and STANDBY.
9.3.11.1 FAULT
The FAULT pin reports faults and is active low under any of the following conditions:
•
•
•
•
Any channel faults (overcurrent or DC detection)
Overtemperature shutdown
Overvoltage or undervoltage conditions on the VBAT or PVDD pins
Clock errors
For all listed faults, the FAULT pin remains asserted after the fault condition is rectified. Deassert the FAULT pin
by writing the CLEAR FAULT bit (bit 7) in register 0x21.
The register reports for all fault reports remain asserted until they are cleared by writing the CLEAR FAULT bit
(bit 7) in register 0x21.
Register bits are available to mask fault categories from reporting to the FAULT pin. These bits only mask the
setting of the pin and do not affect the register reporting or protection of the device. By default all faults are
reported to the pin. See the Register Maps section for a description of the mask settings.
This pin is an open-drain output with an internal 100 kΩ pull-up resistor to VDD.
9.3.11.2 WARN
This active-low output pin reports audio clipping, overtemperature warnings, overcurrent limit warnings and POR
events.
Clipping is reported if any channel is at the maximum modulation for 20 consecutive PWM clocks (default value)
which results in a 10-µs delay to report the onset of clipping. Changing the number of required consecutive PWM
clocks in the Clip Window Register (address = 0x23) impacts the report delay time. The Clip Detect warning bit is
sticky in latching mode and can be cleared by the CLEAR FAULT bit (bit 7) in register 0x21.
An overtemperature warning (OTW) is reported if the general temperature or any of the channel temperature
warnings are set. The warning temperature can be set through bits 5 and 6 in Miscellaneous Control 1 Register
(address = 0x01).
Register bits are available to mask either clipping or OTW reporting to the pin. These bits only mask the setting
of the pin and do not affect the register reporting. By default clipping, ILIMIT and OTW are reported.
The WARN pin is latched and can be cleared by writing the CLEAR FAULT bit (bit 7) in register 0x21.
This pin is an open-drain output with an internal 100 kΩ pull-up resistor to VDD.
9.3.11.3 MUTE
This active-low input pin is used for hardware control of the mute and unmute function for all channels.
This pin has a 100 kΩ internal pull-down resistor.
9.3.11.4 STANDBY
When this active-low input pin is asserted, the device goes into shutdown and current draw is limited. This pin
can be used to shut down the device rapidly. The outputs are ramped down in less than 5 ms if the device is not
already in the Hi-Z state.
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This pin has a 100 kΩ internal pull-down resistor.
9.4 Device Functional Modes
9.4.1 Operating Modes and Faults
The operating modes and faults are listed in the following tables.
表 9-5. Operating Modes
STATE NAME
STANDBY
Hi-Z
OUTPUT FETS
OSCILLATOR
Stopped
Active
I2C
Hi-Z
Active
Active
Active
Active
Hi-Z
MUTE
Switching at 50%
Switching with audio
Active
PLAY
Active
表 9-6. Global Faults and Actions
FAULT/
EVENT
FAULT/EVENT
MONITORING
MODES
REPORTING
METHOD
ACTION
RESULT
CATEGORY
POR
VBAT UV
PVDD UV
VBAT or PVDD OV
OTW
All
I2C + WARN pin
Standby
Voltage fault
Hi-Z, mute, normal
I2C + FAULT pin
Hi-Z
Thermal warning
Hi-Z, mute, normal
Hi-Z, mute, normal
I2C + WARN pin
I2C + FAULT pin
None
Hi-Z
OTSD
Thermal shutdown
表 9-7. Channel Faults and Actions
FAULT/
EVENT
FAULT/EVENT
MONITORING
MODES
REPORTING
METHOD
ACTION
TYPE
CATEGORY
Clipping
Overcurrent limiting
Overcurrent fault
DC detect
Warning
None
I2C + WARN pin
Protection
Current limit
Mute and play
Output channel fault
I2C + FAULT pin
Hi-Z
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9.5 Programming
9.5.1 I2C Serial Communication Bus
The device communicates with the system processor through the I2C serial communication bus as an I2C
slave-only device. The processor can poll the device through I2C to determine the operating status, configure
settings, or run diagnostics. For a complete list and description of all I2C controls, see the Register Maps section.
The device includes two I2C address pins, so up to four devices can be used together in a system with no
additional bus switching hardware. The I2C ADDRx pins set the slave address of the device as listed in 表 9-8.
表 9-8. I2C Addresses
DESCRIPTION
I2C ADDR1
I2C ADDR0
I2C Write
0xD4
I2C Read
0xD5
Device 0
Device 1
Device 2
Device 3
0
0
1
1
0
1
0
1
0xD6
0xD7
0xD8
0xD9
0xDA
0xDB
9.5.2 I2C Bus Protocol
The device has a bidirectional serial-control interface that is compatible with the Inter IC (I2C) bus protocol and
supports 100 kbps and 400 kbps data transfer rates for random and sequential write and read operations. The
TAS6424MS-Q1 device is a slave-only device that does not support a multimaster bus environment or wait-state
insertion. The control interface is used to program the registers of the device and to read device status.
The I2C bus uses two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data is transferred on the bus serially, one bit at a time. The address and data are transferred in
byte (8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the
bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the
master device driving a start condition on the bus and ends with the master device driving a stop condition on
the bus. The bus uses transitions on the data terminal (SDA) while the clock is HIGH to indicate a start and
stop conditions. A HIGH-to-LOW transition on SDA indicates a start, and a LOW-to-HIGH transition indicates
a stop. Normal data bit transitions must occur within the low time of the clock period. The master generates
the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then wait
for an acknowledge condition. The device holds SDA LOW during the acknowledge-clock period to indicate
an acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is
addressed by a unique 7-bit slave address plus a R/W bit (1 byte). All compatible devices share the same
signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for the
SDA and SCL signals to set the HIGH level for the bus. The number of bytes that can be transmitted between
start and stop conditions is unlimited. When the last word transfers, the master generates a stop condition to
release the bus.
R/
W
8-Bit Register Data for
Address (N)
8-Bit Register Data for
Address (N)
7-Bit Slave Address
A
8-Bit Register Address (N)
A
A
A
SDA
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SCL
Start
Stop
图 9-7. Typical I2C Sequence
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t
t
t
r
t
f
w(H)
w(L)
SCL
t
t
h1
su1
SDA
图 9-8. SCL and SDA Timing
Use the I2C ADDRx pins to program the device slave address. Read and write data can be transmitted using
single-byte or multiple-byte data transfers.
9.5.3 Random Write
As shown in 图 9-9, a single-byte data-write transfer begins with the master device transmitting a start condition
followed by the I2C device address and the R/W bit. The R/W bit determines the direction of the data transfer.
For a write data transfer, the R/W bit is a 0. After receiving the correct I2C device address and the R/W bit, the
device responds with an acknowledge bit. Next, the master transmits the address byte or bytes corresponding to
the internal memory address being accessed. After receiving the address byte, the device again responds with
an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being
accessed. After receiving the data byte, the device again responds with an acknowledge bit. Finally, the master
device transmits a stop condition to complete the single-byte data-write transfer.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
ACK
A4
R/W
A7
ACK
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5
ACK
A6 A5
A3 A2 A1 A0
D4 D3 D2 D1 D0
I2C Device Address
and R/W Bit
Stop
Condition
Subaddress
Data Byte
图 9-9. Random Write Transfer
9.5.4 Sequential Write
A sequential data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes are
transmitted by the master to the device as shown in 图 9-10. After receiving each data byte, the device responds
with an acknowledge bit and the I2C subaddress is automatically incremented by one.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
A5
A0
R/W ACK
A4 A3
A0
ACK
ACK
ACK
ACK
D0
A6
A1
A7
A6
A5
A1
D7
D0
D7
D0
D7
I2C Device Address
and R/W Bit
Stop
Condition
Subaddress
First Data Byte
Other Data Byte
Last Data Byte
图 9-10. Sequential Write Transfer
9.5.5 Random Read
As shown in 图 9-11, a single-byte data-read transfer begins with the master device transmitting a start condition
followed by the I2C device address and the R/W bit. For the data-read transfer, both a write followed by a
read occur. Initially, a write occurs to transfer the address byte or bytes of the internal memory address to be
read. As a result, the R/W bit is a 0. After receiving the address and the R/W bit, the device responds with
an acknowledge bit. In addition, after sending the internal memory address byte or bytes, the master device
transmits another start condition followed by the address and the R/W bit again. This time the R/W bit is a
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1, indicating a read transfer. After receiving the address and the R/W bit, the device again responds with an
acknowledge bit. Next, the device transmits the data byte from the memory address being read. After receiving
the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the
single-byte data-read transfer.
Repeat Start
Condition
Acknowledge
Start
Condition
Not
Acknowledge
Acknowledge
Acknowledge
R/W ACK
ACK
R/W ACK
ACK
D0 D6
A6 A5
A1 A0
A7 A6 A5 A4
Subaddress
A0
A6 A5
A1 A0
D7 D6
I2C Device Address
and R/W Bit
I2C Device Address
and R/W Bit
Stop
Condition
Data Byte
图 9-11. Random Read Transfer
9.5.6 Sequential Read
A sequential data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes
are transmitted by the device to the master device as shown in 图 9-12. Except for the last data byte, the
master device responds with an acknowledge bit after receiving each data byte and automatically increments
the I2C subaddress by one. After receiving the last data byte, the master device transmits a not-acknowledge bit
followed by a stop condition to complete the transfer.
Repeat Start
Condition
Acknowledge
Start
Condition
Not
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
R/W ACK
ACK
R/W ACK
ACK
ACK
ACK
D0
A6
A0
A7 A6 A5
A0
A6
A0
D7
D0
D7
D0
D7
I2C Device Address
and R/W Bit
I2C Device Address
and R/W Bit
Stop
Condition
Subaddress
First Data Byte Other Data Byte Last Data Byte
图 9-12. Sequential Read Transfer
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9.6 Register Maps
表 9-9. I2C Address Register Definitions
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Register Description
Section
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Mode Control
Miscellaneous Control 1
Miscellaneous Control 2
SAP Control (Serial Audio-Port Control)
Channel State Control
Channel 1 Volume Control
Channel 2 Volume Control
Channel 3 Volume Control
Channel 4 Volume Control
DC Diagnostic Control 1
DC Diagnostic Control 2
DC Diagnostic Control 3
DC Load Diagnostic Report 1 (Channels 1 and 2)
DC Load Diagnostic Report 2 (Channels 3 and 4)
DC Load Diagnostic Report 3-Line Output
Channel State Reporting
Channel Faults (Overcurrent, DC Detection)
Global Faults 1
R
R
R
R
R
R
Global Faults 2
R
Warnings
R/W
R/W
R/W
R
Pin Control
AC Load Diagnostic Control 1
AC Load Diagnostic Control 2
AC Load Diagnostic Report Channel 1
AC Load Diagnostic Report Channel 2
AC Load Diagnostic Report Channels 3
AC Load Diagnostic Report Channels 4
AC Load Diagnostic Phase Report High
AC Load Diagnostic Phase Report Low
AC Load Diagnostic STI Report High
AC Load Diagnostic STI Report Low
RESERVED
R
R
R
R
R
R
R
R
R
RESERVED
R/W
R/W
R/W
R/W
R/W
R/W
R
Miscellaneous Control 3
Go
Go
Go
Go
Go
Go
Clip Control
Clip Window
Clip Warning
ILIMIT Status
Miscellaneous Control 4
RESERVED
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9.6.1 Mode Control Register (address = 0x00) [default = 0x00]
The Mode Control register is shown in 图 9-13 and described in 表 9-10.
图 9-13. Mode Control Register
7
6
5
4
3
2
1
0
RESET
R/W-0
RESERVED
R/W-0
PBTL CH34
R/W-0
PBTL CH12
R/W-0
CH1 LO MODE CH2 LO MODE CH3 LO MODE CH4 LO MODE
R/W-0 R/W-0 R/W-0 R/W-0
表 9-10. Mode Control Field Descriptions
Bit
Field
Type
Reset
Description
7
RESET
R/W
0
0: Normal operation
1: Resets the device. Self-clearing, reads back 0.
6
5
RESERVED
PBTL CH34
R/W
R/W
0
0
RESERVED
0: Channels 3 and 4 are in BTL mode
1: Channels 3 and 4 are in parallel BTL mode
4
3
2
1
0
PBTL CH12
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0: Channels 1 and 2 are in BTL mode
1: Channels 1 and 2 are in parallel BTL mode
CH1 LO MODE
CH2 LO MODE
CH3 LO MODE
CH4 LO MODE
0: Channel 1 is in normal/speaker mode
1: Channel 1 is in line output mode
0: Channel 2 is in normal/speaker mode
1: Channel 2 is in line output mode
0: Channel 3 is in normal/speaker mode
1: Channel 3 is in line output mode
0: Channel 4 is in normal/speaker mode
1: Channel 4 is in line output mode
9.6.2 Miscellaneous Control 1 Register (address = 0x01) [default = 0x32]
The Miscellaneous Control 1 register is shown in 图 9-14 and described in 表 9-11.
图 9-14. Miscellaneous Control 1 Register
7
6
5
4
3
2
1
0
HPF BYPASS
R/W-0
OTW CONTROL
R/W-01
OC CONTROL
R/W-1
VOLUME RATE
R/W-00
GAIN
R/W-10
表 9-11. Misc Control 1 Field Descriptions
Bit
Field
Type
Reset
Description
7
HPF BYPASS
R/W
0
0: High pass filter eneabled
1: High pass filter disabled
6–5
OTW CONTROL
R/W
01
00: Global overtemperature warning set to 140°C
01: Global overtemperature warning set to 130C
10: Global overtemperature warning set to 120°C
11: Global overtemperature warning set to 110°C
4
OC CONTROL
VOLUME RATE
R/W
R/W
1
0: Overcurrent is level 1
1: Overcurrent is level 2
3–2
00
00: Volume update rate is 1 step / FSYNC
01: Volume update rate is 1 step / 2 FSYNCs
10: Volume update rate is 1 step / 4 FSYNCs
11: Volume update rate is 1 step / 8 FSYNCs
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表 9-11. Misc Control 1 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1–0
GAIN
R/W
10
00: Gain level 1 = 7.5 V peak output voltage
01: Gain Level 2 = 15 V peak output voltage
10: Gain Level 3 = 21 V peak output voltage
11: Gain Level 4 = 29 V peak output voltage
9.6.3 Miscellaneous Control 2 Register (address = 0x02) [default = 0x62]
The Miscellaneous Control 2 register is shown in 图 9-15 and described in 表 9-12.
图 9-15. Miscellaneous Control 2 Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0
PWM FREQUENCY
R/W-110
RESERVED
R/W-0
SDM_OSR
R/W-0
OUTPUT PHASE
R/W-10
表 9-12. Misc Control 2 Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
7
R/W
0
RESERVED
6–4
PWM FREQUENCY
R/W
110
000: 8 × fS (352.8 kHz / 384 kHz)
001: 10 × fS (441 kHz / 480 kHz)
010: RESERVED
011: RESERVED
100: RESERVED
101: 38 × fS (1.68 MHz / 1.82 MHz)
110: 44 × fS (1.94 MHz / 2.11 MHz)
111: 48 × fS (2.12 MHz / not supported)
3
2
RESERVED
SDM_OSR
R/W
R/W
0
0
RESERVED
0: 64x OSR
1: 128x OSR
1–0
OUTPUT PHASE
R/W
10
00: 0 degrees output-phase switching offset
01: 30 degrees output-phase switching offset
10: 45 degrees output-phase switching offset
11: 60 degrees output-phase switching offset
9.6.4 SAP Control (Serial Audio-Port Control) Register (address = 0x03) [default = 0x04]
The SAP Control (serial audio-port control) register is shown in 图 9-16 and described in 表 9-13.
图 9-16. SAP Control Register
7
6
5
4
3
2
1
0
INPUT SAMPLING RATE
8 Ch TDM
SLOT SELECT
TDM SLOT
SIZE
TDM SLOT
SELECT 2
INPUT FORMAT
R/W-00
R/W-0
R/W-0
R/W-0
R/W-100
表 9-13. SAP Control Field Descriptions
Bit
Field
Type
Reset
Description
7–6
INPUT SAMPLING RATE
R/W
00
00: 44.1 kHz
01: 48 kHz
10: 96 kHz
11: RESERVED
5
8 Ch TDM SLOT SELECT
R/W
0
0: First four TDM slots
1: Last four TDM slots
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表 9-13. SAP Control Field Descriptions (continued)
Bit
Field
Type
Reset
Description
4
TDM SLOT SIZE
R/W
0
0: TDM slot size is 24-bit or 32-bit
1: TDM slot size is 16-bit
3
TDM SLOT SELECT 2
INPUT FORMAT
R/W
R/W
0
0: Normal
1: swap channel 1/2 with channel 3/4
2–0
100
000: 24-bit right justified
001: 20-bit right justified
010: 18-bit right justified
011: 16-bit right justified
100: I2S (16-bit or 24-bit)
101: Left justified (16-bit or 24-bit)
110: DSP mode (16-bit or 24-bit)
111: RESERVED
9.6.5 Channel State Control Register (address = 0x04) [default = 0x55]
The Channel State Control register is shown in 图 9-17 and described in 表 9-14.
图 9-17. Channel State Control Register
7
6
5
4
3
2
1
0
CH4 STATE CONTROL
R/W-01
CH1 STATE CONTROL
R/W-01
CH2 STATE CONTROL
R/W-01
CH3 STATE CONTROL
R/W-01
表 9-14. Channel State Control Field Descriptions
Bit
Field
Type
Reset
Description
7–6
5–4
3–2
1–0
CH1 STATE CONTROL
R/W
01
00: PLAY
01: Hi-Z
10: MUTE
11: DC load diagnostics
CH2 STATE CONTROL
CH3 STATE CONTROL
CH4 STATE CONTROL
R/W
R/W
R/W
01
01
01
00: PLAY
01: Hi-Z
10: MUTE
11: DC load diagnostics
00: PLAY
01: Hi-Z
10: MUTE
11: DC load diagnostics
00: PLAY
01: Hi-Z
10: MUTE
11: DC load diagnostics
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9.6.6 Channel 1 Through 4 Volume Control Registers (address = 0x05–0x08) [default = 0xCF]
The Channel 1 Through 4 Volume Control registers are shown in 图 9-18 and described in 表 9-15.
图 9-18. Channel x Volume Control Register
7
6
5
4
3
2
1
0
CH x VOLUME
R/W-CF
表 9-15. Ch x Volume Control Field Descriptions
Bit
Field
CH x VOLUME
Type
Reset
Description
7–0
R/W
0xCF
8-Bit Volume Control for each channel, register address for Ch1
is 0x05, Ch2 is 0x06, Ch3 is 0x07 and Ch4 is 0x08, 0.5 dB/step:
0xFF: 24 dB
0xCF: 0 dB
0x07: –100 dB
< 0x07: MUTE
9.6.7 DC Load Diagnostic Control 1 Register (address = 0x09) [default = 0x00]
The DC Diagnostic Control 1 register is shown in 图 9-19 and described in 表 9-16.
图 9-19. DC Load Diagnostic Control 1 Register
7
6
5
4
3
2
1
0
DC LDG
ABORT
2x_RAMP
2x_SETTLE
RESERVED
LDG LO
ENABLE
LDG BYPASS
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表 9-16. DC Load Diagnostics Control 1 Field Descriptions
Bit
Field
Type
Reset
Description
7
DC LDG ABORT
R/W
0
0: Default state, clear after abort
1: Aborts the load diagnostics in progress
6
5
2x_RAMP
R/W
R/W
0
0
0: Normal ramp time
1: Double ramp time
2x_SETTLE
0: Normal Settle time
1: Double settling time
4–2
1
RESERVED
R/W
R/W
000
0
RESERVED
LDG LO ENABLE
0: Line output diagnostics are disabled
1: Line output diagnostics are enabled
0
LDG BYPASS
R/W
0
0: Automatic diagnostics when leaving Hi-Z and after
channel fault
1: Diagnostics are not run automatically
9.6.8 DC Load Diagnostic Control 2 Register (address = 0x0A) [default = 0x11]
The DC Diagnostic Control 2 register is shown in 图 9-20 and described in 表 9-17.
图 9-20. DC Load Diagnostic Control 2 Register
7
6
5
4
3
2
1
0
CH1 DC LDG SL
R/W-0001
CH2 DC LDG SL
R/W-0001
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表 9-17. DC Load Diagnostics Control 2 Field Descriptions
Bit
Field
CH1 DC LDG SL
Type
Reset
Description
7–4
R/W
0001
DC load diagnostics shorted-load threshold
0000: 0.5 Ω
0001: 1 Ω
0010: 1.5 Ω
...
1001: 5 Ω
3–0
CH2 DC LDG SL
R/W
0001
DC load diagnostics shorted-load threshold
0000: 0.5 Ω
0001: 1 Ω
0010: 1.5 Ω
...
1001: 5 Ω
9.6.9 DC Load Diagnostic Control 3 Register (address = 0x0B) [default = 0x11]
The DC Diagnostic Control 3 register is shown in 图 9-21 and described in 表 9-18.
图 9-21. DC Load Diagnostic Control 3 Register
7
6
5
4
3
2
1
0
CH3 DC LDG SL
R/W-0001
CH4 DC LDG SL
R/W-0001
表 9-18. DC Load Diagnostics Control 3 Field Descriptions
Bit
Field
Type
Reset
Description
7–4
CH3 DC LDG SL
R/W
0001
DC load diagnostics shorted-load threshold
0000: 0.5 Ω
0001: 1 Ω
0010: 1.5 Ω
...
1001: 5 Ω
3–0
CH4 DC LDG SL
R/W
0001
DC load diagnostics shorted-load threshold
0000: 0.5 Ω
0001: 1 Ω
0010: 1.5 Ω
...
1001: 5 Ω
9.6.10 DC Load Diagnostic Report 1 Register (address = 0x0C) [default = 0x00]
DC Load Diagnostic Report 1 register is shown in 图 9-22 and described in 表 9-19.
图 9-22. DC Load Diagnostic Report 1 Register
7
6
5
4
3
2
1
0
CH1 S2G
R-0
CH1 S2P
R-0
CH1 OL
R-0
CH1 SL
R-0
CH2 S2G
R-0
CH2 S2P
R-0
CH2 OL
R-0
CH2 SL
R-0
表 9-19. DC Load Diagnostics Report 1 Field Descriptions
Bit
Field
CH1 S2G
Type
Reset
Description
7
R
0
0: No short-to-GND detected
1: Short-To-GND Detected
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表 9-19. DC Load Diagnostics Report 1 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
6
CH1 S2P
R
0
0: No short-to-power detected
1: Short-to-power detected
5
4
3
2
1
0
CH1 OL
CH1 SL
CH2 S2G
CH2 S2P
CH2 OL
CH2 SL
R
R
R
R
R
R
0
0
0
0
0
0
0: No open load detected
1: Open load detected
0: No shorted load detected
1: Shorted load detected
0: No short-to-GND detected
1: Short-to-GND detected
0: No short-to-power detected
1: Short-to-power detected
0: No open load detected
1: Open load detected
0: No shorted load detected
1: Shorted load detected
9.6.11 DC Load Diagnostic Report 2 Register (address = 0x0D) [default = 0x00]
The DC Load Diagnostic Report 2 register is shown in 图 9-23 and described in 表 9-20.
图 9-23. DC Load Diagnostic Report 2 Register
7
6
5
4
3
2
1
0
CH3 S2G
R-0
CH3 S2P
R-0
CH3 OL
R-0
CH3 SL
R-0
CH4 S2G
R-0
CH4 S2P
R-0
CH4 OL
R-0
CH4 SL
R-0
表 9-20. DC Load Diagnostics Report 2 Field Descriptions
Bit
Field
CH3 S2G
Type
Reset
Description
7
R
0
0: No short-to-GND detected
1: Short-to-GND detected
6
5
4
3
2
1
0
CH3 S2P
CH3 OL
CH3 SL
CH4 S2G
CH4 S2P
CH4 OL
CH4 SL
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0: No short-to-power detected
1: Short-to-power detected
0: No open load detected
1: Open load detected
0: No shorted load detected
1: Shorted load detected
0: No short-to-GND detected
1: Short-to-GND detected
0: No short-to-power detected
1: Short-to-power detected
0: No open load detected
1: Open load detected
0: No shorted load detected
1: Shorted load detected
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9.6.12 DC Load Diagnostics Report 3 Line Output Register (address = 0x0E) [default = 0x00]
The DC Load Diagnostic Report, Line Output, register is shown in 图 9-24 and described in 表 9-21.
图 9-24. DC Load Diagnostics Report 3 Line Output Register
7
6
5
4
3
2
1
0
RESERVED
R-0000
CH1 LO LDG
R-0
CH2 LO LDG
R-0
CH3 LO LDG
R-0
CH4 LO LDG
R-0
表 9-21. DC Load Diagnostics Report 3 Line Output Field Descriptions
Bit
Field
Type
Reset
0000
0
Description
7–4
RESERVED
R
RESERVED
3
2
1
0
CH1 LO LDG
CH2 LO LDG
CH3 LO LDG
CH4 LO LDG
R
0: No line output detected on channel 1
1: Line output detected on channel 1
R
R
R
0
0
0
0: No line output detected on channel 2
1: Line output detected on channel 2
0: No line output detected on channel 3
1: Line output detected on channel 3
0: No line output detected on channel 4
1: Line output detected on channel 4
9.6.13 Channel State Reporting Register (address = 0x0F) [default = 0x55]
The Channel State Reporting register is shown in 图 9-25 and described in 表 9-22.
图 9-25. Channel State-Reporting Register
7
6
5
4
3
2
1
0
CH1 STATE REPORT
R-01
CH2 STATE REPORT
R-01
CH3 STATE REPORT
R-01
CH4 STATE REPORT
R-01
表 9-22. State-Reporting Field Descriptions
Bit
Field
Type
Reset
Description
7–6
5–4
3–2
1–0
CH1 STATE REPORT
R
01
00: PLAY
01: Hi-Z
10: MUTE
11: DC load diagnostics
CH2 STATE REPORT
CH3 STATE REPORT
CH4 STATE REPORT
R
R
R
01
01
01
00: PLAY
01: Hi-Z
10: MUTE
11: DC load diagnostics
00: PLAY
01: Hi-Z
10: MUTE
11: DC load diagnostics
00: PLAY
01: Hi-Z
10: MUTE
11: DC load diagnostics
9.6.14 Channel Faults (Overcurrent, DC Detection) Register (address = 0x10) [default = 0x00]
The Channel Faults (overcurrent, DC detection) register is shown in 图 9-26 and described in 表 9-23.
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图 9-26. Channel Faults Register
7
6
5
4
3
2
1
0
CH1 OC
R-0
CH2 OC
R-0
CH3 OC
R-0
CH4 OC
R-0
CH1 DC
R-0
CH2 DC
R-0
CH3 DC
R-0
CH4 DC
R-0
表 9-23. Channel Faults Field Descriptions
Bit
Field
Type
Reset
Description
7
CH1 OC
R
0
0: No overcurrent fault detected
1: Overcurrent fault detected
6
5
4
3
2
1
0
CH2 OC
CH3 OC
CH4 OC
CH1 DC
CH2 DC
CH3 DC
CH4 DC
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0: No overcurrent fault detected
1: Overcurrent fault detected
0: No overcurrent fault detected
1: Overcurrent fault detected
0: No overcurrent fault detected
1: Overcurrent fault detected
0: No DC fault detected
1: DC fault detected
0: No DC fault detected
1: DC fault detected
0: No DC fault detected
1: DC fault detected
0: No DC fault detected
1: DC fault detected
9.6.15 Global Faults 1 Register (address = 0x11) [default = 0x00]
The Global Faults 1 register is shown in 图 9-27 and described in 表 9-24.
图 9-27. Global Faults 1 Register
7
6
5
4
3
2
1
0
RESERVED
INVALID
CLOCK
PVDD OV
VBAT OV
PVDD UV
VBAT UV
R-0
R-0
R-0
R-0
R-0
R-000
表 9-24. Global Faults 1 Field Descriptions
Bit
Field
Type
Reset
Description
7–5
RESERVED
R
000
RESERVED
4
3
2
1
0
INVALID CLOCK
R
R
R
R
R
0
0
0
0
0
0: No clock fault detected
1: Clock fault detected
PVDD OV
VBAT OV
PVDD UV
VBAT UV
0: No PVDD overvoltage fault detected
1: PVDD overvoltage fault detected
0: No VBAT overvoltage fault detected
1: VBAT overvoltage fault detected
0: No PVDD undervoltage fault detected
1: PVDD undervoltage fault detected
0: No VBAT undervoltage fault detected
1: VBAT undervoltage fault detected
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9.6.16 Global Faults 2 Register (address = 0x12) [default = 0x00]
The Global Faults 2 register is shown in 图 9-28 and described in 表 9-25.
图 9-28. Global Faults 2 Register
7
6
5
4
3
2
1
0
RESERVED
R-000
OTSD
R-0
CH1 OTSD
R-0
CH2 OTSD
R-0
CH3 OTSD
R-0
CH4 OTSD
R-0
表 9-25. Global Faults 2 Field Descriptions
Bit
Field
Type
Reset
000
0
Description
7–5
RESERVED
OTSD
R
RESERVED
4
3
2
1
0
R
0: No global overtemperature shutdown
1: Global overtemperature shutdown
CH1 OTSD
CH2 OTSD
CH3 OTSD
CH4 OTSD
R
R
R
R
0
0
0
0
0: No overtemperature shutdown on Ch1
1: Overtemperature shutdown on Ch1
0: No overtemperature shutdown on Ch2
1: Overtemperature shutdown on Ch2
0: No overtemperature shutdown on Ch3
1: Overtemperature shutdown on Ch3
0: No overtemperature shutdown on Ch4
1: Overtemperature shutdown on Ch4
9.6.17 Warnings Register (address = 0x13) [default = 0x20]
The Warnings register is shown in 图 9-29 and described in 表 9-26.
图 9-29. Warnings Register
7
6
5
4
3
2
1
0
RESERVED
R-00
VDD POR
R-0
OTW
R-0
OTW CH1
R-0
OTW CH2
R-0
OTW CH3
R-0
OTW CH4
R-0
表 9-26. Warnings Field Descriptions
Bit
Field
Type
Reset
Description
7-6
RESERVED
R
00
RESERVED
5
4
3
2
1
0
VDD POR
R
R
R
R
R
R
0
0
0
0
0
0
0: No VDD POR has occurred
1 VDD POR occurred
OTW
0: No global overtemperature warning
1: Global overtemperature warning
OTW CH1
OTW CH2
OTW CH3
OTW CH4
0: No overtemperature warning on channel 1
1: Overtemperature warning on channel 1
0: No overtemperature warning on channel 2
1: Overtemperature warning on channel 2
0: No overtemperature warning on channel 3
1: Overtemperature warning on channel 3
0: No overtemperature warning on channel 4
1: Overtemperature warning on channel 4
9.6.18 Pin Control Register (address = 0x14) [default = 0x00]
The Pin Control register is shown in 图 9-30 and described in 表 9-27.
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图 9-30. Pin Control Register
7
6
5
4
3
2
1
0
MASK OC
R/W-0
MASK OTSD
R/W-0
MASK UV
R/W-0
MASK OV
R/W-0
MASK DC
R/W-0
RESERVED
R/W-0
MASK CLIP
R/W-0
MASK OTW
R/W-0
表 9-27. Pin Control Field Descriptions
Bit
Field
MASK OC
Type
Reset
Description
7
R/W
0
0: Report overcurrent faults on the FAULT pin
1: Do not report overcurrent faults on the FAULT Pin
6
5
4
3
MASK OTSD
MASK UV
MASK OV
MASK DC
R/W
R/W
R/W
R/W
0
0
0
0
0: Report overtemperature faults on the FAULT pin
1: Do not report overtemperature faults on the FAULT pin
0: Report undervoltage faults on the FAULT pin
1: Do not report undervoltage faults on the FAULT pin
0: Report overvoltage faults on the FAULT pin
1: Do not report overvoltage faults on the FAULT pin
0: Report DC faults on the FAULT pin
1: Do not report DC faults on the FAULT pin
2
1
RESERVED
MASK CLIP
R/W
R/W
0
0
RESERVED
0: Report clipping on the configured pin
1: Do not report clipping on the configured pin
0
MASK OTW
R/W
0
0: Report overtemperature warnings on the WARN pin
1: Do not report overtemperature warnings on the WARN pin
9.6.19 AC Load Diagnostic Control 1 Register (address = 0x15) [default = 0x00]
The AC Load Diagnostic Control 1 register is shown in 图 9-31 and described in 表 9-28.
图 9-31. AC Load Diagnostic Control 1 Register
7
6
5
4
3
2
1
0
CH1 GAIN
R/W-0
CH2 GAIN
R/W-0
CH3 GAIN
R/W-0
CH4 GAIN
R/W-0
CH1 ENABLE
R/W-0
CH2 ENABLE
R/W-0
CH3 ENABLE
R/W-0
CH4 ENABLE
R/W-0
表 9-28. AC Load Diagnostic Control 1 Field Descriptions
Bit
Field
Type
Reset
Description
7
CH1, PBTL12: GAIN
R/W
0
0: Gain 1
1: Gain 4
6
5
4
3
2
1
CH2 GAIN
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0: Gain 1
1: Gain 4
CH3, CH4, PBTL34: GAIN
CH4 GAIN
0: Gain 1
1: Gain 4
0: Gain 1
1: Gain 4
CH1 ENABLE
0: AC diagnostics disabled
1: Enable AC diagnostics
CH2 ENABLE
0: AC diagnostics disabled
1: Enable AC diagnostics
CH3 ENABLE
0: AC diagnostics disabled
1: Enable AC diagnostics
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表 9-28. AC Load Diagnostic Control 1 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
CH4 ENABLE
R/W
0
0: AC diagnostics disabled
1: Enable AC diagnostics
9.6.20 AC Load Diagnostic Control 2 Register (address = 0x16) [default = 0x00]
The AC Load Diagnostic Control 2 register is shown in 图 9-32 and described in 表 9-29.
图 9-32. AC Load Diagnostic Control 2 Register
7
6
5
4
3
2
1
0
AC_DIAGS_LO
OPBACK
RESERVED
AC TIMING
AC CURRENT
RESERVED
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0 R/W-0
表 9-29. AC Load Diagnostic Control 2 Field Descriptions
Bit
Field
Type
Reset
Description
7
AC_DIAGS_LOOPBACK
R/W
0
0: Disable AC Diag loopback
1: Enable AC Diag loopback
6-5
4
RESERVED
AC TIMING
R/W
R/W
00
0
RESERVED
0: 32 Cycles
1: 64 Cycles
3-2
AC CURRENT
R/W
00
00: 10mA
01: 19 mA
10: RESERVED
11: RESERVED
1-0
RESERVED
R/W
00
RESERVED
9.6.21 AC Load Diagnostic Impedance Report Ch1 through Ch4 Registers (address = 0x17–0x1A) [default
= 0x00]
The AC Load Diagnostic Report Ch1 through Ch4 registers are shown in 图 9-33 and described in 表 9-30.
图 9-33. AC Load Diagnostic Impedance Report Chx Register
7
6
5
4
3
2
1
0
CHx IMPEDANCE
R-00000000
表 9-30. Chx AC LDG Impedance Report Field Descriptions
Bit
Field
Type
Reset
Description
7–0
CH x IMPEDANCE
R
00000000
8-bit AC-load diagnostic report for each channel with a step size
of 0.2496 Ω/bit (control by register 0x15 and register 0x16)
0x00: 0 Ω
0x01: 0.2496 Ω
...
0xFF: 63.65 Ω
9.6.22 AC Load Diagnostic Phase Report High Register (address = 0x1B) [default = 0x00]
The AC Load Diagnostic Phase High value registers are shown in 图 9-34 and described in 表 9-31.
图 9-34. AC Load Diagnostic (LDG) Phase High Report Register
7
6
5
4
3
2
1
0
AC Phase High
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图 9-34. AC Load Diagnostic (LDG) Phase High Report Register (continued)
R-00000000
表 9-31. AC LDG Phase High Report Field Descriptions
Bit
Field
Type
Reset
Description
7–0
AC Phase High
R
00000000 Bit 15:8
9.6.23 AC Load Diagnostic Phase Report Low Register (address = 0x1C) [default = 0x00]
The AC Load Diagnostic Phase Low value registers are shown in 图 9-35 and described in 表 9-32.
图 9-35. AC Load Diagnostic (LDG) Phase Low Report Register
7
6
5
4
3
2
1
0
AC Phase Low
R-00
表 9-32. AC LDG Phase Low Report Field Descriptions
Bit
Field
AC Phase Low
Type
Reset
Description
7–0
R
00
Bit 7:0
9.6.24 AC Load Diagnostic STI Report High Register (address = 0x1D) [default = 0x00]
The AC Load Diagnostic STI High value registers are shown in 图 9-36 and described in 表 9-33.
图 9-36. AC Load Diagnostic (LDG) STI High Report Register
7
6
5
4
3
2
1
0
AC STI High
R-00
表 9-33. AC LDG STI High Report Field Descriptions
Bit
Field
Type
Reset
Description
7–0
AC STI High
R
00
Bit 15:8
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9.6.25 AC Load Diagnostic STI Report Low Register (address = 0x1E) [default = 0x00]
The AC Load Diagnostic STI Low value registers are shown in 图 9-37 and described in 表 9-34.
图 9-37. AC Load Diagnostic (LDG) STI Low Report Register
7
6
5
4
3
2
1
0
AC STI Low
R-00
表 9-34. Chx AC LDG STI Low Report Field Descriptions
Bit
Field
Type
Reset
Description
7–0
AC STI Low
R
00
Bit 7:0
9.6.26 Miscellaneous Control 3 Register (address = 0x21) [default = 0x00]
The Miscellaneous Control 3 register is shown in 图 9-38 and described in 表 9-35.
图 9-38. Miscellaneous Control 3 Register
7
6
5
4
3
2
1
0
CLEAR FAULT PBTL_CH_SEL
RESERVED
RESERVED
OTSD AUTO
RECOVERY
RESERVED
R/W-0 R/W-0
R/W-0
R/W-0
R/W-0
表 9-35. Misc Control 3 Field Descriptions
Bit
Field
Type
Reset
Description
7
CLEAR FAULT
R/W
0
0: Normal operation
1: Clear fault
6
PBTL_CH_SEL
R/W
0
0: PBTL normal signal source
1: PBTL flip signal source
5
4
3
RESERVED
R/W
R/W
R/W
0
0
0
RESERVED
RESERVED
RESERVED
OTSD AUTO RECOVERY
0: OTSD is latched
1: OTSD is autorecovery
2–0
RESERVED
0
RESERVED
9.6.27 Clip Control Register (address = 0x22) [default = 0x01]
The Clip Detect register is shown in 图 9-39 and described in 表 9-36. To ensure the Clip Detect Warning is
operating according to the expectation, the related bit values in the Clip Window Register (address = 0x23) and
Clip Warning Register (address = 0x24) must be set accordingly.
图 9-39. Clip Control Register
7
6
5
4
3
2
1
0
RESERVED
CLIP_PIN
R/W-0
CLIP_LATCH
R/W-0
CLIPDET_EN
R/W-1
表 9-36. Clip Control Field Descriptions
Bit
Field
Type
Reset
Description
7-3
RESERVED
RESERVED
2
CLIP_PIN
R/W
0
0: CH1-4 Clip Detect report to WARN pin
1: CH1-2 Clip Detect report to WARN pin, CH3-4 Clip Detect
report to FAULT pin
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表 9-36. Clip Control Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1
CLIP_LATCH
R/W
0
0: Pin latching
1: Pin non-latching
0
CLIPDET_EN
R/W
1
0: Clip Detect disable
1: Clip Detect Enable
9.6.28 Clip Window Register (address = 0x23) [default = 0x14]
The Clip Window register is shown in 图 9-40 and described in 表 9-37. The register value represents the
minimum number of 100% duty-cycle PWM cycles before Clip Detect is reported.
图 9-40. Clip Window Register
7
6
5
4
3
2
1
0
CLIP_WINDOW_SEL[7:1]
R/W-00010100
表 9-37. Clip Window Field Descriptions
Bit
Field
CLIP_WINDOW_SEL[7:1]
Type
Reset
Description
7-0
R/W
00010100
Default value is 20. Acceptable range is from 0-20 cycles.
00010100: 20-100% duty-cycle PWM cycles before Clip
Detect is triggered
9.6.29 Clip Warning Register (address = 0x24) [default = 0x00]
The Clip Window register is shown in 图 9-41 and described in 表 9-38.
图 9-41. Clip Warning Register
7
6
5
4
3
2
1
0
RESERVED
CH4_CLIP
R-0
CH3_CLIP
R-0
CH2_CLIP
R-0
CH1_CLIP
R-0
表 9-38. Clip Warning Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
0
RESERVED
3
2
1
0
CH4_CLIP
CH3_CLIP
CH2_CLIP
CH1_CLIP
R
R
R
R
0
0
0
0
0: No Clip Detect
1: Clip Detect
0: No Clip Detect
1: Clip Detect
0: No Clip Detect
1: Clip Detect
0: No Clip Detect
1: Clip Detect
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9.6.30 ILIMIT Status Register (address = 0x25) [default = 0x00]
The ILIMIT Status register is shown in 图 9-42 and described in 表 9-39.
图 9-42. ILIMIT Status Register
7
6
5
4
3
2
1
0
RESERVED
CH4_ILIMIT_W CH3_ILIMIT_W CH2_ILIMIT_W CH1_ILIMIT_W
ARN
ARN
ARN
ARN
R-0
R-0
R-0
R-0
表 9-39. ILIMIT Status Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
0
RESERVED
3
2
1
0
CH4_ILIMIT_WARN
CH3_ILIMIT_WARN
CH2_ILIMIT_WARN
CH1_ILIMIT_WARN
R
R
R
R
0
0
0
0
0: No ILIMIT
1: ILIMIT Warning
0: No ILIMIT
1: ILIMIT Warning
0: No ILIMIT
1: ILIMIT Warning
0: No ILIMIT
1: ILIMIT Warning
9.6.31 Miscellaneous Control 4 Register (address = 0x26) [default = 0x40]
The Miscellaneous Control 4 register is shown in 图 9-43 and described in 表 9-40.
图 9-43. Miscellaneous Control 4 Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0100
BCLK_INV
R/W-0
HPF_CORNER[2:0]
R/W-000
表 9-40. Misc Control 4 Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R/W
0100
RESERVED
3
BCLK_INV
R/W
R/W
0
0: All other MCLK/BCLK frequency / phase use cases
1: Inverted MCLK/BCLK phase relationship when MCLK/BCLK
run at the same frequency
2-0
HPF_CORNER[2:0]
000
000: 3.7 Hz
001: 7.4 Hz
010: 15 Hz
011: 30 Hz
100: 59 Hz
101: 118 Hz
110: 235 Hz
111: 463 Hz
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10 Application Information Disclaimer
备注
以下应用部分中的信息不属于 TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
10.1 Application Information
The TAS6424MS-Q1 is a two-channel class-D digital-input audio-amplifier design for use in automotive head
units and external amplifier modules. The TAS6424MS-Q1 incorporates the necessary functionality to perform in
demanding OEM applications.
10.1.1 AM-Radio Band Avoidance
AM-radio frequency interference can be avoided by setting the switching frequency of the device above the AM
band. The switching frequency options available are 38 fs, 44 fs, and 48 fs. If the switch frequency cannot be set
above the AM band, then use the two options of 8 fs and 10 fs. These options should be changed to avoid AM
active channels.
10.1.2 Parallel BTL Operation (PBTL)
The device can drive more current-paralleling BTL channels on the load side of the LC output filter. For parallel
operation, the parallel BTL mode, PBTL, must be used and the paralleled channels must have the same state in
the state control register. If the two states are not aligned the device reports a fault condition.
To set the requested channels to PBTL mode the device must be in standby mode for the commands to take
effect.
A load diagnostic is supported for PBTL channels. Paralleling on the device side of the LC output filter is not
supported.
10.1.3 Demodulation Filter Design
The amplifier outputs are driven by high-current LDMOS transistors in an H-bridge configuration. These
transistors are either fully off or fully on. The result is a square-wave output signal with a duty cycle that is
proportional to the amplitude of the audio signal. An LC demodulation filter is used to recover the audio signal.
The filter attenuates the high-frequency components of the output signals that are out of the audio band. The
design of the demodulation filter significantly affects the audio performance of the power amplifier. Therefore, to
meet the system THD+N requirements, the selection of the inductors used in the output filter should be carefully
considered.
10.1.4 Line Driver Applications
In many automotive audio applications, the same head unit must drive either a speaker (with several ohms of
impedance) or an external amplifier input (with several kΩ of impedance). The design is capable of supporting
both applications and has special line-drive gain and diagnostics. Coupled with the high switching frequency, the
device is well suited for this type of application. Set the desired channel in line driver mode through I2C register
0x00, the externally connected amplifier must have a differential impedance from 600 Ω to 4.7 kΩ for the DC line
diagnostic to detect the connected external amplifier. 图 10-1 shows the recommended external amplifier input
configuration.
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Output Filter
External Amplifier
3.3 µH
3.3 µH
1 …F
1 …F
1 …F
1 …F
1 nF
600 ꢀ
to
4.7 kꢀ
1 nF
100 kꢀ
100 kꢀ
图 10-1. External Amplifier Input Configuration for Line Driver
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10.2 Typical Applications
10.2.1 BTL Application
图 10-2 shows the schematic of a typical 4-channel solution for a head-unit application.
PVDD
Input
PVDD
1 ꢀF
1 nF
470 ꢀF
56
PVDD
PVDD
PVDD
1
GND
0.1 ꢀF
10 ꢀF
10 ꢀF
10 ꢀF
1 ꢀF
55
2
3
4
5
PVDD
VBAT
AREF
VREG
PVDD
54
53
52
51
BST_4P
OUT_4P
GND
1 ꢀF
3.3 ꢀH
1 ꢀF
1 ꢀF
1 nF
1 nF
1 ꢀF
1 ꢀF
4 ꢁ
3.3 ꢀH
6
VCOM
OUT_4M
50
49
7
8
1 ꢀF
1 ꢀF
BST_4M
GND
AVSS
AVDD
1 ꢀF
48
47
46
45
9
BST_3P
OUT_3P
GND
GVDD
2.2 ꢀF
3.3 ꢀH
10
GVDD
GND
1 ꢀF
1 ꢀF
1 nF
1 nF
2.2 ꢀF
4 ꢁ
11
3.3 ꢀH
OUT_3M
12
13
14
15
16
MCLK
SCLK
44
43
1 ꢀF
BST_3M
PVDD
PVDD
FSYNC
SDIN1
SDIN2
DSP
0.1 ꢀF
42
PVDD
41
40
39
38
BST_2P
OUT_2P
GND
1 ꢀF
17
18
GND
GND
3.3 ꢀH
1 ꢀF
1 ꢀF
1 nF
1 nF
1 uF
4 ꢁ
19
3.3 ꢀH
VDD
SCL
VDD
2 kꢁ
OUT_2M
2 kꢁ
20
21
37
36
1 ꢀF
1 ꢀF
BST_2M
GND
SDA
22
23
I2C_ADDR0
35
34
33
32
BST_1P
OUT_1P
GND
3.3 ꢀH
I2C_ADDR1
STANDBY
Micro
24
25
1 ꢀF
1 ꢀF
1 nF
1 nF
4 ꢁ
3.3 ꢀH
MUTE
FAULT
WARN
GND
OUT_1M
26
27
28
31
30
1 ꢀF
BST_1M
PVDD
PVDD
0.1 ꢀF
29
PVDD
图 10-2. Typical 4-Channel BTL Application Schematic
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10.2.1.1 Design Requirements
Use the following requirements for this design:
•
•
•
This head-unit example is focused on the smallest solution size for 4 × 50 W output power into 2 Ω with a
battery supply of 14.4 V.
The switching frequency is set above the AM-band with 44 times the input sample rate of 48 kHz which
results in a frequency of 2.11 MHz.
The selection of a 2.11 MHz switch frequency enables the use of a small output inductor value of 3.3 µH
which leads to a very small solution size.
10.2.1.1.1 Communication
All communications to the TAS6424MS-Q1 are through the I2C protocol. A system controller can communicate
with the device through the SDA pins and SCL pins. The device is an I2C slave and requires a master. The
device cannot generate an I2C clock or initiate a transaction. The maximum clock speed accepted by the device
is 400 kHz. If multiple TAS6424MS-Q1devices are on the same I2C bus, the I2C address must be different for
each device. Up to four TAS6424MS-Q1 devices can be on the same I2C bus.
The I2C bus is shared internally.
备注
Complete any internal operations, such as load diagnostics, before reading the registers for the
results.
10.2.1.2 Detailed Design Procedure
10.2.1.2.1 Hardware Design
Use the following procedure for the hardware design:
•
Determine the input format. The input format can be either I2S or TDM mode. The mode determines the
correct pin connections and the I2C register settings.
•
Determine the power output that is required into the load. The power requirement determines the required
power-supply voltage and current. The output reconstruction-filter components that are required are also
driven by the output power.
•
With the requirements, adjust the typical application schematic in 图 10-2 for the input connections.
10.2.1.2.2 Digital Input and the Serial Audio Port
The TAS6424MS-Q1 device supports four different digital input formats which are: I2S, Right Justified, Left
Justified, and TDM mode. Depending on the format, the device can support 16, 18, 20, 24, and 32 bit data. The
supported frequencies are 96 kHz, 48 kHz, and 44.1 kHz. Please see SAP Control (Serial Audio-Port Control)
Register (address = 0x03) [default = 0x04] for the complete matrix to set up the serial audio port.
备注
Bits 3, 4, and 5 in this register are ignored in all input formats except for TDM. Setting up all the
control registers to the system requirements should be done before the device is placed in Mute mode
or Play mode. After the registers are setup, use bit 7 in Miscellaneous Control 3 Register (address =
0x21)to clear any faults. Then read the fault registers to make sure no faults are present. When no
faults are present, use SAP Control (Serial Audio-Port Control) Register (address = 0x03) [default =
0x04] to place the device properly into Play mode.
10.2.1.2.3 Bootstrap Capacitors
The bootstrap capacitors provide the gate-drive voltage of the upper N-channel FET. These capacitors must be
sized appropriately for the system specification. A special condition can occur where the bootstrap may sag if
the capacitor is not sized accordingly. The special condition is just below clipping where the PWM is slightly less
than 100% duty cycle with sustained low-frequency signals. Changing the bootstrap capacitor value to 2.2 µF for
driving subwoofers that require frequencies below 30 Hz may be necessary.
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10.2.1.2.4 Output Reconstruction Filter
The output FETs drive the amplifier outputs in an H-Bridge configuration. These transistors are either fully off or
fully on. The result is a square-wave output signal with a duty cycle that is proportional to the amplitude of the
audio signal. The amplifier outputs require a reconstruction filter that comprises a series inductor and a capacitor
to ground on each output, generally called an LC filter. The LC filter attenuates the PWM frequency and reduces
electromagnetic emissions, allowing the reconstructed audio signal to pass to the speakers. refer to the Class-D
LC Filter Design Application Report, (SLAA701A) for a detailed description of proper component description and
design of the LC filter based upon the specified load and frequency response. The recommended low-pass
cutoff frequency of the LC filter is dependent on the selected switching frequency. The low-pass cutoff frequency
can be as high as 100 kHz for a PWM frequency of 2.1 MHz. At a PWM frequency of 384 kHz the low-pass
cutoff frequency should be less than 40 kHz. Certain specifications must be understood for a proper inductor.
The inductance value is given at zero current, but the device has current. Use the inductance versus current
curve for the inductor to make sure the inductance does not drop below 1 µH (for fSW = 2.1 MHz) at the
maximum current provided by the system design. The DCR of the inductor directly affects the output power of
the system design. The lower the DCR, the more power is provided to the speakers. The typical inductor DCR
for a 4 Ω system is 40 to 50 mΩ and for a 2 Ω system is 20 to 25 mΩ. Further guidance is provided in the
Inductor Selection Guide for 2.1 MHz Class-D Amplifiers.
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10.2.2 PBTL Application
图 10-3 shows a schematic of a typical 2-channel solution for a head unit or external amplifier application where
high power into 2 Ω is required.
PVDD
Input
PVDD
1 ꢀF
1 nF
470 ꢀF
56
55
PVDD
PVDD
PVDD
1
GND
0.1 ꢀF
3.3 ꢀH
10 ꢀF
1 ꢀF
2
3
4
5
PVDD
VBAT
AREF
VREG
PVDD
54
53
52
51
BST_4P
OUT_4P
GND
1 ꢀF
1 ꢀF
1 ꢀF
1 ꢀF
3.3 ꢀH 1 ꢀF
6
VCOM
OUT_4M
50
49
7
8
1 ꢀF
1 ꢀF
BST_4M
GND
AVSS
AVDD
1 nF
1 nF
2 ꢁ
1 ꢀF
48
47
46
45
9
BST_3P
OUT_3P
GND
GVDD
2.2 ꢀF
3.3 ꢀH
10
GVDD
GND
1 ꢀF
2.2 ꢀF
11
3.3 ꢀH 1 ꢀF
OUT_3M
12
13
14
15
16
MCLK
SCLK
44
43
1 ꢀF
1 ꢀF
BST_3M
PVDD
PVDD
FSYNC
SDIN1
SDIN2
DSP
0.1 ꢀF
10 ꢀF
42
PVDD
41
40
39
38
BST_2P
OUT_2P
GND
GND
GND
3.3 ꢀH
18
19
1 ꢀF
1 uF
3.3 ꢀH 1 ꢀF
VDD
SCL
OUT_2M
2 kꢁ
2 kꢁ
20
21
37
36
1 ꢀF
1 ꢀF
BST_2M
GND
1 nF
1 nF
2 ꢁ
SDA
22
23
I2C_ADDR0
36
34
33
32
BST_1P
OUT_1P
GND
3.3 ꢀH
I2C_ADDR1
STANDBY
Micro
24
25
1 ꢀF
3.3 ꢀH 1 ꢀF
MUTE
FAULT
WARN
GND
OUT_1M
26
27
28
31
30
BST_1M
PVDD
1 ꢀF
PVDD
0.1 ꢀF
10 ꢀF
29
PVDD
图 10-3. Typical 2-Channel PBTL Application Schematic
To operate in PBTL mode the output stage must be paralleled according to the schematic in 图 10-3. The device
can operate in a mix of PBTL and BTL mode. This application can be set up for 3-channels, with one channel
in PBTL mode and two channels in BTL mode. The device does not support a parallel configuration of all four
channels for a one channel amplifier.
10.2.2.1 Design Requirements
Use the following requirements for this design:
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•
•
•
This head-unit example is focused on the smallest solution size for 2 x 50 W output power into 2 Ω with a
battery supply of 14.4 V.
The switching frequency is set above the AM-band with 44 times the input sample rate of 48 kHz which
results in a frequency of 2.11 MHz.
The selection of a 2.11 MHz switch frequency enables the use of a small output inductor value of 3.3 µH
which leads to a very small solution size.
10.2.2.1.1 Detailed Design Procedure
As a starting point, refer to the section for the BTL application. PBTL mode requires schematic changes in the
output stage as shown in 图 10-3. The other required changes include setting up the I2C registers correctly (see
表 9-13) and selecting which frame or channel to use on each output. Bit 6 in register 0x21 controls the frame
selection.
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11 Power Supply Recommendations
The TAS6424MS-Q1 requires three power supplies. The PVDD supply is the high-current supply in the
recommended supply range. The VBAT supply is lower current supply that must be in the recommended supply
range. The PVDD and VBAT pins can be connected to the same supply if the recommended supply range for
VBAT is maintained. The VDD supply is the 3.3 Vdc logic supply and must be maintained in the tolerance as
shown in the Recommended Operating Conditions table.
For best device performance and to avoid unexpected device behavior follow the recommendations in the
Vehicle-Battery Power-Supply Sequence section.
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12 Layout
12.1 Layout Guidelines
The pinout of the TAS6424MS-Q1 was selected to provide flowthrough layout with all high-power connections on
the right side, and all low-power signals and supply decoupling on the left side.
图 12-1 shows the area for the components in the application example (see the Typical Applications section).
The TAS6424MS-Q1 EVM uses a four-layer PCB. The copper thickness was selected as 70 µm to optimize
power loss.
The small value of the output filter provides a small size and, in this case, the low height of the inductor enables
double-sided mounting.
The EVM PCB shown in 图 12-1 is the basis for the layout guidelines.
12.2 Layout Example
Power Supply
and
Amplifier
Section
B
C
F
A
D
E
图 12-1. EVM Layout
12.3 Thermal Considerations
The thermally enhanced PowerPAD package has an exposed pad up for connection to a heat sink. The output
power of any amplifier is determined by the thermal performance of the amplifier as well as limitations placed on
it by the system, such as the ambient operating temperature. The heat sink absorbs heat from the TAS6424MS-
Q1 and transfers it to the air. With proper thermal management this process can reach equilibrium and heat
can be continually transferred from the device. Heat sinks can be smaller than that of classic linear amplifier
design because of the excellent efficiency of class-D amplifiers. This device is intended for use with a heat sink,
therefore, RθJC is used as the thermal resistance from junction to the exposed metal package. This resistance
dominates the thermal management, so other thermal transfers is not considered. The thermal resistance of
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RθJA (junction to ambient) is required to determine the full thermal solution. The thermal resistance is comprised
of the following components:
•
•
•
RθJC of the TAS6424MS-Q1
Thermal resistance of the thermal interface material
Thermal resistance of the heat sink
The thermal resistance of the thermal interface material can be determined from the manufacturer’s value for the
area thermal resistance (expressed in °Cmm2/W) and the area of the exposed metal package. For example, a
typical, white, thermal grease with a 0.0254 mm (0.001 inch) thick layer is approximately 4.52°C mm2/W. The
TAS6424MS-Q1 in the DKQ package has an exposed area of 47.6 mm2. By dividing the area thermal resistance
by the exposed metal area determines the thermal resistance for the thermal grease. The thermal resistance of
the thermal grease is 0.094°C/W
表 12-1 lists the modeling parameters for one device on a heat sink. The junction temperature is assumed to be
115°C while delivering and average power of 10 watts per channel into a 4 Ω load. The thermal-grease example
previously described is used for the thermal interface material. Use 方程式 3 to design the thermal system.
RθJA = RθJC + thermal interface resistance + heat sink resistance
(3)
表 12-1. Thermal Modeling
Description
Ambient Temperature
Value
25°C
40W (4 x 10W)
Average Power to load
Power dissipation
8W (4 x 2W)
Junction Temperature
115°C
ΔT inside package
5.6°C (0.7°C/W × 8W)
0.75°C (0.094°C/W × 8W)
10.45°C/W ([115°C – 25°C – 5.6°C – 0.75°C] / 8W)
11.24°C/W
ΔT through thermal interface material
Required heat sink thermal resistance
System thermal resistance to ambient RθJA
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13 Device and Documentation Support
13.1 Documentation Support
13.2 Related Documentation
For related documentation see the following:
•
•
PurePath™ Console 3 Graphical Development Suite
TAS6422E-Q1 EVM User's Guide (SLOU541)
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI
的《使用条款》。
13.5 商标
PurePath™ is a trademark of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.6 静电放电警告
静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
13.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TAS6424MSQDKQRQ1
ACTIVE
HSSOP
DKQ
56
1000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TAS
6424MS
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Nov-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TAS6424MSQDKQRQ1 HSSOP
DKQ
56
1000
330.0
32.4
11.35 18.67
3.1
16.0
32.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Nov-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HSSOP DKQ 56
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 55.0
TAS6424MSQDKQRQ1
1000
Pack Materials-Page 2
PACKAGE OUTLINE
DKQ0056A
PowerPADTM HSSOP - 2.475 mm max height
S
C
A
L
E
1
.
0
0
0
PLASTIC SMALL OUTLINE
C
10.67
10.03
TYP
SEATING PLANE
A
PIN 1 ID AREA
0.1 C
54X 0.635
56
1
EXPOSED
THERMAL PAD
18.54
18.29
NOTE 3
8.661
8.611
2X
17.15
5.533
5.483
28
29
0.37
56X
0.17
0.13
(2.29)
7.59
7.39
B
C A B
NOTE 4
0.25
0.13
2.29 0.05
TYP
2.475
2.240
NOTE 6
0.25
GAGE PLANE
SEE DETAIL A
0.08
0.00
1.02
0.51
0 - 8
DETAIL A
TYPICAL
4221870/D 01/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. The exposed thermal pad is designed to be attached to an external heatsink.
6. For clamped heatsink design, refer to overall package height above the seating plane as 2.325 +/- 0.075 and molded body
thickness dimension.
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EXAMPLE BOARD LAYOUT
DKQ0056A
PowerPADTM HSSOP - 2.475 mm max height
PLASTIC SMALL OUTLINE
56X (1.9)
SEE DETAILS
SYMM
1
56
56X (0.4)
54X (0.635)
SYMM
28
29
(R0.05) TYP
(9.5)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:6X
METAL UNDER
SOLDER MASK
SOLDER MASK
METAL
SOLDER MASK
OPENING
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221870/D 01/2019
NOTES: (continued)
7. Publication IPC-7351 may have alternate designs.
8. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
9. Size of metal pad may vary due to creepage requirement.
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EXAMPLE STENCIL DESIGN
DKQ0056A
PowerPADTM HSSOP - 2.475 mm max height
PLASTIC SMALL OUTLINE
56X (1.9)
SYMM
1
56
56X (0.4)
54X (0.635)
SYMM
28
29
(R0.05) TYP
(9.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE:6X
4221870/D 01/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
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