TB5D1MDWRE4 [TI]

QUAD LINE DRIVER, PDSO16, ROHS COMPLIANT, PLASTIC, SOIC-16;
TB5D1MDWRE4
型号: TB5D1MDWRE4
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

QUAD LINE DRIVER, PDSO16, ROHS COMPLIANT, PLASTIC, SOIC-16

驱动 光电二极管 接口集成电路 驱动器
文件: 总21页 (文件大小:711K)
中文:  中文翻译
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TB5D1M, TB5D2H  
www.ti.com  
SLLS579CSEPTEMBER 2003REVISED JANUARY 2008  
QUAD DIFFERENTIAL PECL DRIVERS  
The TB5D1M device is  
a pin and functional  
1
FEATURES  
replacement for the Agere systems BDG1A and  
BPNGA quad differential drivers. The TB5D1M has a  
built-in lightning protection circuit to absorb large  
transitions on the transmission lines without  
destroying the device. When the circuit is powered  
down it loads the transmission line, because of the  
protection circuit.  
Functional Replacements for the Agere  
BDG1A, BPNGA and BDGLA  
Pin-Equivalent to the General-Trade 26LS31  
Device  
2.0 ns Maximum Propagation Delays  
0.15 ns Output Skew Typical Between Pairs  
Capable of Driving 50-Loads  
The TB5D2H device is  
a pin and functional  
replacement for the Agere systems BDG1A and  
BDGLA quad differential drivers. Upon power down  
the TB5D2H output circuit appears as an open circuit  
and does not load the transmission line.  
5.0-V or 3.3-V Supply Operation  
TB5D1M Includes Surge Protection on  
Differential Outputs  
TB5D2H No Line Loading When VCC = 0  
Third State Output Capability  
Both drivers feature a 3-state output with a third-state  
level of less than 0.1 V.  
-40C to 85C Operating Temp Range  
ESD Protection HBM > 3 kV and CDM > 2 kV  
The packaging options available for these quad  
differential line drivers include  
a 16-pin SOIC  
gull-wing (DW) and a 16-pin SOIC (D) package.  
Available in Gull-Wing SOIC (JEDEC MS-013,  
DW) and SOIC (D) Packages  
Both drivers are characterized for operation from  
-40C to 85C  
APPLICATIONS  
The logic inputs of this device include internal pull-up  
resistors of approximately 40 kthat are connected  
to VCC to ensure a logical high level input if the inputs  
are open circuited.  
Digital Data or Clock Transmission Over  
Balanced Transmission Lines  
DESCRIPTION  
These quad differential drivers are TTL input to  
pseudo-ECL differential output used for digital data  
transmission over balanced transmission lines.  
DW AND D PACKAGE  
(TOP VIEW)  
FUNCTIONAL DIAGRAM  
AO  
AI  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
AI  
AO  
AO  
E1  
CC  
DI  
AO  
BO  
DO  
DO  
E2  
CO  
CO  
CI  
BI  
BO  
ENABLE TRUTH TABLE  
BO  
BO  
BI  
CO  
CO  
DO  
DO  
E1  
E2 Condition  
CI  
DI  
0
0
Active  
1
0
1
0
1
1
Active  
Disabled  
Active  
GND  
E1  
E2  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2003–2008, Texas Instruments Incorporated  
TB5D1M, TB5D2H  
www.ti.com  
SLLS579CSEPTEMBER 2003REVISED JANUARY 2008  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
ORDERING INFORMATION  
PART NUMBER  
TB5D1MDW  
TB5D1MD  
PART MARKING  
TB5D1M  
PACKAGE  
Gull-wing SOIC  
SOIC  
LEAD FINISH  
NiPdAu  
STATUS  
Production  
Production  
Production  
Production  
TB5D1M  
NiPdAu  
TB5D2HDW  
TB5D2HD  
TB5D2H  
Gull-wing SOIC  
SOIC  
NiPdAu  
TB5D2H  
NiPdAu  
PACKAGE DISSIPATION RATINGS  
CIRCUIT  
BOARD  
MODEL  
T
A 25°C  
THERMAL RESISTANCE,  
JUNCTION-TO-AMBIENT  
WITH NO AIR FLOW  
DERATING FACTOR(1)  
ABOVE TA = 25C  
TA = 85C POWER  
RATING  
PACKAGE  
POWER  
RATING  
Low-K(2)  
High-K(3)  
Low-K(2)  
High-K(3)  
754 mW  
1166 mW  
816 mW  
1206 mW  
132.6 C/W  
85.8 C/W  
122.5 C/W  
82.9 C/W  
7.54 mW/C  
11.7 mW/C  
8.17 mW/C  
12.1 mW/C  
301 mW  
466 mW  
326 mW  
482 mW  
D
DW  
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted with no air flow.  
(2) In accordance with the low-K thermal metric definitions of EIA/JESD51-3.  
(3) In accordance with the high-K thermal metric definitions of EIA/JESD51-7.  
THERMAL CHARACTERISTICS  
PARAMETER  
PACKAGE  
VALUE  
UNITS  
C/W  
D
51.4  
56.6  
45.7  
49.2  
θJB  
Junction-to-board thermal resistance  
DW  
D
C/W  
C/W  
θJC  
Junction-to-case thermal resistance  
DW  
C/W  
ABSOLUTE MAXIMUM RATINGS  
over operating free-air temperature range unless otherwise noted(1)  
TB5D1M, TB5D2H  
Supply voltage, VCC  
Input voltage  
0 V to 6 V  
- 0.3 V to (VCC + 0.3 V)  
3 kV  
Human Body Model(2)  
All Pins  
All Pins  
ESD  
Charged-Device Model(3)  
2 kV  
Continuous power dissipation  
Storage temperature, Tstg  
Junction temperature, TJ  
See Dissipation Rating Table  
-65C to 130C  
130C  
D Package  
-80 V to 100 V  
-100 V to 100 V  
Lightning surge, TB5D1M only, see Figure 6  
DW Package  
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating  
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) Tested in accordance with JEDEC Standard 22, Test Method A114-A.  
(3) Tested in accordance with JEDEC Standard 22, Test Method C101.  
2
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Copyright © 2003–2008, Texas Instruments Incorporated  
Product Folder Link(s): TB5D1M TB5D2H  
TB5D1M, TB5D2H  
www.ti.com  
SLLS579CSEPTEMBER 2003REVISED JANUARY 2008  
RECOMMENDED OPERATING CONDITIONS(1)  
MIN  
4.5  
3.0  
-40  
NOM  
5
MAX  
5.5  
3.6  
85  
UNIT  
Supply voltage, VCC  
5.0-V nominal supply  
3.3-V nominal supply  
V
V
C
3.3  
Operating free-air temperature, TA  
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet, unless  
otherwise stated.  
ELECTRICAL CHARACTERISTICS  
over recommended operating conditions unless otherwise noted  
parameter  
test conditions  
min  
typ(1)  
max  
unit  
VCC = 4.5 V to 5.5 V,  
no loads  
40  
ICC  
Supply current  
mA  
VCC = 3.0 V to 3.6 V,  
no loads  
40  
VCC = 4.5 V to 5.5 V,  
Figure 3 loads all outputs  
290  
280  
360  
360  
PD  
Power dissipation  
mW  
VCC = 3.0 V to 3.6 V,  
Figure 4 loads all outputs  
VOH  
VOL  
VOD  
VOH  
VOL  
VOD  
Output high voltage  
VCC - 1.8  
VOH - 1.4  
0.7  
VCC - 1.3  
VOH - 1.2  
1.2  
VCC - 0.8  
VOH - 0.7  
1.4  
V
V
V
V
V
V
VCC = 4.5 V to 5.5 V,  
Figure 3  
Output low voltage  
Differential output voltage |VOH - VOL  
|
Output high voltage  
VCC - 1.8  
VOH - 1.4  
0.5  
VCC - 1.3  
VOH - 1.1  
1.1  
VCC - 0.8  
VOH - 0.5  
1.4  
VCC = 3.0 V to 3.6 V,  
Figure 4  
Output low voltage  
Differential output voltage |VOH - VOL  
|
Peak-to-peak common-mode output  
voltage  
VOC(PP)  
CL= 5 pF, Figure 5  
230  
600  
mV  
VOZ  
VIL  
Third-state output voltage  
Low level input voltage(2)  
High level input voltage  
Enable input clamp voltage  
Figure 3 or Figure 4 load  
0.1  
0.8  
V
V
V
V
VIH  
VIK  
2
VCC = 4.5 V, II = -5 mA  
VCC = 5.5 V, VO = 0 V  
VCC = 5.5 V, VOD = 0 V  
VCC = 5.5 V, VI = 0.4 V  
VCC = 5.5 V, VI =2.7 V  
VCC = 5.5 V, VI =5.5 V  
-1(3)  
-250(3)  
10(3)  
-400(3)  
20  
IOS  
IIL  
Output short-circuit current(4)  
mA  
Input low current, enable or data  
Input high current, enable or data  
Input reverse current, enable or data  
Input capacitance  
A
A
IIH  
100  
A
CIN  
5
pF  
(1) All typical values are at 25C and with a 3.3-V or 5-V supply.  
(2) The input level provides no noise immunity and should be tested only in a static, noise-free environment.  
(3) This parameter is listed using a magnitude and polarity/direction convention, rather than an algebraic convention, to match the original  
Agere data sheet.  
(4) Test must be performed one output at a time to prevent damage to the device. No test circuit attached.  
Copyright © 2003–2008, Texas Instruments Incorporated  
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TB5D1M, TB5D2H  
www.ti.com  
SLLS579CSEPTEMBER 2003REVISED JANUARY 2008  
THIRD STATE—A TB5D1M (or TB5D2H) driver produces pseudo-ECL levels, and has a third-state mode, which  
is different than a conventional TTL device. When a TB5D1M (or TB5D2H) driver is placed in the third state, the  
base of the output transistors is pulled low, bringing the outputs below the active-low level of standard PECL  
devices. [For example: The TB5D1M low output level is typically 2.7 V, while the third state output level is less  
than 0.1 V.] In a bidirectional, multipoint, bus application, the driver of one device, which is in its third state, may  
be back driven by another driver on the bus whose voltage in the low state is lower than the third-stated device.  
This could come about due to differences in the driver's independent power supplies. In this case, the device in  
the third state controls the line, thus clamping the line and reducing the signal swing. If the difference voltage  
between the independent driver power supplies is small, this consideration can be ignored. Again using the  
TB5D1M driver as an example, a typical supply voltage difference between separate drivers of > 2 V can exist  
without significantly affecting the amplitude of the signal.  
SWITCHING CHARACTERISTICS, 5-V NOMINAL SUPPLY  
over recommended operating conditions unless otherwise noted  
parameter  
test conditions  
min  
typ(1)  
max  
unit  
ns  
tP1  
tP2  
ΔtP  
Propagation delay time, input high to output(2)  
Propagation delay time, input low to output(2)  
Capacitive delay  
1.2  
1.2  
2
2
CL = 5 pF, See Figure 1 and  
Figure 3  
0.01  
0.03  
ns/pF  
Propagation delay time,  
high-level-to-high-impedance output  
tPHZ  
tPLZ  
tPZH  
tPZL  
7
12  
12  
12  
12  
Propagation delay time,  
low-level-to-high-impedance output  
7
5
4
CL = 5 pF, See Figure 2 and  
Figure 3  
ns  
Propagation delay time,  
high-impedance-to-high-level output  
Propagation delay time,  
high-impedance-to-low-level output  
tskew1  
tshew2  
tskew(pp)  
Δtskew  
tTLH  
Output skew, |tP1 - tP2  
|
0.15  
0.15  
0.1  
0.3  
1.1  
1
Output skew, |tPHH - tPHL|, |tPLH - tPLL  
Part-to-part skew(3)  
Output skew, difference between drivers(4)  
Rise time (20% - 80%)  
|
CL = 5 pF, See Figure 1 and  
Figure 3  
ns  
ns  
0.3  
2
0.7  
0.7  
CL = 5 pF, See Figure 1 and  
Figure 3  
tTHL  
Fall time (80% - 20%)  
2
(1) All typical values are at 25C and with a 5-V supply.  
(2) Parameters tP1 and tP2 are measured from the 1.5 V point of the input to the crossover point of the outputs (see Figure 1).  
(3) tskew(pp) is the magnitude of the difference in differential propagation delay times, tP1 or tP2, between any specified outputs of two devices  
when both devices operate with the same supply voltage, at the same temperature, and have identical packages and test circuits.  
(4) Δtskew is the magnitude of the difference in differential skew tskew1 between any specified outputs of a single device.  
4
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Copyright © 2003–2008, Texas Instruments Incorporated  
Product Folder Link(s): TB5D1M TB5D2H  
TB5D1M, TB5D2H  
www.ti.com  
SLLS579CSEPTEMBER 2003REVISED JANUARY 2008  
SWITCHING CHARACTERISTICS, 3.3-V NOMINAL SUPPLY  
over recommended operating conditions unless otherwise noted  
typ(1  
parameter  
test conditions  
min  
max  
unit  
)
tP1  
Propagation delay time, input high to output(2)  
Propagation delay time, input low to output(2)  
1.2  
1.2  
0.01  
8
3.5  
3.5  
CL = 5 pF, See Figure 1 and  
Figure 4  
ns  
tP2  
ΔtP  
Capacitive delay  
0.03 ns/pF  
12  
tPHZ  
tPLZ  
tPZH  
tPZL  
Propagation delay time, high-level-to-high-impedance output  
Propagation delay time, low-level-to-high-impedance output  
Propagation delay time, high-impedance-to-high-level output  
Propagation delay time, high-impedance-to-low-level output  
5
12  
ns  
12  
CL = 5 pF, See Figure 2 and  
Figure 4  
5
8
12  
tskew1  
tshew2  
tskew(pp)  
Δtskew  
tTLH  
Output skew, |tP1 - tP2  
|
0.15  
0.15  
0.1  
0.3  
Output skew, |tPHH - tPHL|, |tPLH - tPLL  
Part-to-part skew(3)  
Output skew, difference between drivers(4)  
Rise time (20% - 80%)  
|
1.2  
ns  
1
CL = 5 pF, See Figure 1 and  
Figure 4  
0.3  
0.7  
0.7  
2
CL = 5 pF, See Figure 1 and  
Figure 4  
ns  
2
tTHL  
Fall time (80% - 20%)  
(1) All typical values are at 25C and with a 3.3-V supply.  
(2) Parameters tP1 and tP2 are measured from the 1.5 V point of the input to the crossover point of the outputs (see Figure 1).  
(3) tskew(pp) is the magnitude of the difference in differential propagation delay times, tP1 or tP2, between any specified outputs of two devices  
when both devices operate with the same supply voltage, at the same temperature, and have identical packages and test circuits.  
(4) Δtskew is the magnitude of the difference in differential skew tskew1 between any specified outputs of a single device.  
Copyright © 2003–2008, Texas Instruments Incorporated  
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Product Folder Link(s): TB5D1M TB5D2H  
TB5D1M, TB5D2H  
www.ti.com  
SLLS579CSEPTEMBER 2003REVISED JANUARY 2008  
2.4 V  
1.5 V  
0.4 V  
INPUT  
OUTPUTS  
OUTPUT  
OUTPUT  
t
t
t
t
P1  
P2  
V
OH  
V
OL  
V
OH  
PHH  
PLL  
(V + V )/2  
OH  
OL  
V
OL  
t
t
PHL  
PLH  
V
OH  
(V + V )/2  
OH  
OL  
V
V
V
OL  
OH  
OL  
80%  
20%  
80%  
OUTPUT  
20%  
t
t
tHL  
tLH  
Figure 1. Propagation Delay Time Waveforms  
2.4 V  
(1)  
E1  
1.5 V  
0.4 V  
2.4 V  
1.5 V  
0.4 V  
(2)  
E2  
t
t
PZH  
PHZ  
V
V
V
OH  
+ 0.2 V  
− 0.1 V  
OL  
OL  
OUTPUT  
V
OL  
t
t
PZL  
PLZ  
V
V
OL  
OUTPUT  
− 0.1 V  
OL  
(1)  
E2 = 1 while E1 changes state  
E1 = 0 while E2 changes state  
(2)  
NOTE: In the third state, both outputs (OUTPUT and OUTPUT) are 0.1 V (max).  
Figure 2. Enable and Disable Delay Time Waveforms  
6
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Product Folder Link(s): TB5D1M TB5D2H  
TB5D1M, TB5D2H  
www.ti.com  
SLLS579CSEPTEMBER 2003REVISED JANUARY 2008  
TEST CONDITIONS  
Parametric values specified under the Electrical Characteristics and Switching Characteristics sections are  
measured with the following output load circuit.  
OUTPUT  
100  
200 Ω  
OUTPUT  
200 Ω  
C
L
C
L
Figure 3. Driver Test Circuits, 5-V Nominal Supplies  
OUTPUT  
100  
75 Ω  
OUTPUT  
75 Ω  
C
L
C
L
Figure 4. Driver Test Circuits, 3.3-V Nominal Supplies  
V
OC  
V
OC  
OUTPUT  
OUTPUT  
OUTPUT  
OUTPUT  
50  
50 Ω  
50 Ω  
50 Ω  
200 Ω  
200 Ω  
75 Ω  
75 Ω  
C
L
C
P
= 2 pF  
C
L
C
L
C
P
= 2 pF  
C
L
Note: V  
load circuit for 5-V nominal supplies.  
Note: V  
load circuit for 3.3-V nominal supplies.  
OC(PP)  
OC(PP)  
V
V
OH  
OUTPUT  
OL  
V
OC  
V
OC(PP)  
Note: All input pulses are supplied by a generator having the following characteristics: t or t = 1 ns, pulse repetition rate  
r
f
(PRR) = 0.25 Mbps, pulse width = 500 ± 10 ns. C includes the instrumentation and fixture capacitance within 0,06 m of the D.U.T.  
P
The measurement of V  
is made on test equipment with a –3 dB bandwidth of at least 1 GHz.  
OC(PP)  
Figure 5. Test Circuits and Definitions for the Driver Common-Mode Output Voltage  
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TB5D1M, TB5D2H  
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SLLS579CSEPTEMBER 2003REVISED JANUARY 2008  
V
CC  
110  
DUT  
110 Ω  
+
_
Lightning Surge  
Test Generators  
+
_
Note: Surges may be applied simultaneously, but never in opposite polarities.  
Surge test pulses have t = t = 2 µs, pulse width = 7 µs (50% points), and  
r
f
period = 250 ms.  
Figure 6. Lightning-Surge Testing Configuration for TB5D1M  
TYPICAL CHARACTERISTICS  
OUTPUT VOLTAGE RELATIVE TO VCC  
vs  
OUTPUT CURRENT  
OUTPUT VOLTAGE RELATIVE TO VCC  
vs  
FREE-AIR TEMPERATURE  
0
0
V
= 4.5 V to 5.5 V,  
CC  
T = 255C  
A
Figure 3 Load  
-0.5  
-0.5  
V
OH  
-1  
V
Max  
OH  
-1  
-1.5  
-2  
-1.5  
-2  
V
Min  
OH  
V
OL  
Max  
Min  
-2.5  
-3  
V
OL  
V
OL  
-2.5  
-3  
-3.5  
-50  
0
50  
100  
150  
-50  
-40  
-30  
-20  
-10  
0
T
A
- Free-Air Temperature - °C  
I
O
- Output Current - mA  
Figure 7.  
Figure 8.  
8
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Product Folder Link(s): TB5D1M TB5D2H  
TB5D1M, TB5D2H  
www.ti.com  
SLLS579CSEPTEMBER 2003REVISED JANUARY 2008  
TYPICAL CHARACTERISTICS (continued)  
OUTPUT VOLTAGE RELATIVE TO VCC  
DIFFERENTIAL OUTPUT VOLTAGE  
vs  
vs  
FREE-AIR TEMPERATURE  
FREE-AIR TEMPERATURE  
0
1.6  
1.4  
1.2  
V
CC  
= 4.5 V to 5.5 V,  
V
= 3 V to 3.6 V,  
CC  
Figure 3 Load  
Figure 4 Load  
V
OD  
Max  
-0.5  
-1  
V
Max  
Min  
OH  
V
Nom  
Min  
OD  
V
-1.5  
-2  
OH  
V
OD  
V
OL  
Max  
Min  
1
V
OL  
-2.5  
-3  
0.8  
-50  
-50  
0
50  
100  
150  
0
50  
100  
150  
T
A
- Free-Air Temperature - °C  
T
A
- Free-Air Temperature - °C  
Figure 9.  
Figure 10.  
DIFFERENTIAL OUTPUT VOLTAGE  
PROPAGATION DELAY TIME tP1 or tP2  
vs  
vs  
FREE-AIR TEMPERATURE  
FREE-AIR TEMPERATURE  
1.6  
1.4  
1.4  
V
= 4.5 V to 5.5 V,  
CC  
Figure 3 Load  
V
OD  
Max  
1.2  
1
V
OD  
Nom  
1.2  
Max Delay  
1
V
OD  
Min  
Min Delay  
0.8  
0.6  
0.8  
V
= 3 V to 3.6 V,  
CC  
Figure 4 Load  
0
−50  
50  
100  
150  
0
-50  
0
50  
100  
150  
T
A
- Free-Air Temperature - 5C  
T
A
- Free-Air Temperature - °C  
Figure 11.  
Figure 12.  
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SLLS579CSEPTEMBER 2003REVISED JANUARY 2008  
TYPICAL CHARACTERISTICS (continued)  
PROPAGATION DELAY TIME tP1 or tP2  
vs  
FREE-AIR TEMPERATURE  
3.5  
V
CC  
= 3 V to 3.6 V,  
Figure 4 Load  
3
2.5  
Max Delay  
2
1.5  
Min Delay  
1
0.5  
0
−50  
50  
100  
150  
0
T
A
- Free-Air Temperature - 5C  
Figure 13.  
10  
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Product Folder Link(s): TB5D1M TB5D2H  
TB5D1M, TB5D2H  
www.ti.com  
SLLS579CSEPTEMBER 2003REVISED JANUARY 2008  
APPLICATION INFORMATION  
the device and PCB. JEDEC/EIA has defined  
standardized test conditions for measuring θJA. Two  
commonly used conditions are the low-K and the  
high-K boards, covered by EIA/JESD51-3 and  
EIA/JESD51-7 respectively. Figure 14 shows the  
low-K and high-K values of θJA versus air flow for this  
device and its package options.  
Power Dissipation  
The power dissipation rating, often listed as the  
package dissipation rating, is a function of the  
ambient temperature, TA, and the airflow around the  
device. This rating correlates with the device's  
maximum junction temperature, sometimes listed in  
the absolute maximum ratings tables. The maximum  
junction temperature accounts for the processes and  
materials used to fabricate and package the device,  
in addition to the desired life expectancy.  
The standardized θJA values may not accurately  
represent the conditions under which the device is  
used. This can be due to adjacent devices acting as  
heat sources or heat sinks, to nonuniform airflow, or  
to the system PCB having significantly different  
thermal characteristics than the standardized test  
PCBs. The second method of system thermal  
analysis is more accurate. This calculation uses the  
power dissipation and ambient temperature, along  
with two device and two system-level parameters:  
There are two common approaches to estimating the  
internal die junction temperature, TJ. In both of these  
methods, the device’s internal power dissipation, PD,  
needs to be calculated. This is done by totaling the  
supply power(s) to arrive at the system power  
dissipation:  
θJC, the junction-to-case thermal resistance, in  
degrees Celsius per watt  
θJB, the junction-to-board thermal resistance, in  
degrees Celsius per watt  
θCA, the case-to-ambient thermal resistance, in  
degrees Celsius per watt  
θBA, the board-to-ambient thermal resistance, in  
degrees Celsius per watt.  
S(V   I  
)
Sn  
Sn  
(1)  
and then subtracting the total power dissipation of the  
external load(s):  
S(V   I  
)
Ln  
Ln  
(2)  
The first TJ calculation uses the power dissipation  
and ambient temperature, along with one parameter:  
θJA, the junction-to-ambient thermal resistance, in  
degrees Celsius per watt.  
In this analysis, there are two parallel paths, one  
through the case (package) to the ambient, and  
another through the device to the PCB to the  
ambient. The system-level junction-to-ambient  
thermal impedance,θJA(S), is the equivalent parallel  
impedance of the two parallel paths:  
The product of PD and θJA is the junction temperature  
rise above the ambient temperature. Therefore:  
T
+ T ) (P   q  
)
J
A
D
JA  
(3)  
T
+ T ) (P   q  
)
140  
120  
100  
J
A
D
JA(S)  
(4)  
where  
D, Low−K  
DW, Low−K  
(q ) q )   (q ) q  
)
JC  
CA  
JB  
) q ) q  
BA  
q
+
JA(S)  
(q  
) q  
)
JC  
CA  
JB  
BA  
The device parameters θJC and θJB account for the  
internal structure of the device. The system-level  
parameters θCA and θBA take into account details of  
the PCB construction, adjacent electrical and  
mechanical components, and the environmental  
conditions including airflow. Finite element (FE), finite  
difference (FD), or computational fluid dynamics  
(CFD) programs can determine θCA and θBA. Details  
on using these programs are beyond the scope of  
this data sheet, but are available from the software  
manufacturers.  
80  
DW, High−K  
D, High−K  
60  
40  
0
100  
200  
300  
400  
500  
Air Flow − LFM  
Figure 14. Thermal Impedance vs Air Flow  
Note that θJA is highly dependent on the PCB on  
which the device is mounted, and on the airflow over  
Copyright © 2003–2008, Texas Instruments Incorporated  
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SLLS579CSEPTEMBER 2003REVISED JANUARY 2008  
Load Circuits  
Transmission Line  
The test load circuits shown in Figure 3 and Figure 4  
are based on a recommended pi type of load circuit  
shown in Figure 15. The 100-differential load  
resistor RT at the receiver provide proper termination  
for the interconnecting transmission line, assuming it  
has a 100-characteristic impedance. The two  
resistors RS to ground at the driver end of the  
transmission line link provide dc current paths for the  
emitter follower output transistors. The two resistors  
to ground normally should not be placed at the  
receiver end, as they shunt the termination resistor,  
potentially creating an impedance mismatch with  
undesirable reflections.  
INPUT  
OUTPUT  
R /2  
T
R /2  
T
Recommended Resistor Values:  
For 5 V Nom Supplies, R = 200 , R = 90 Ω  
T
S
For 3.3 V Nom Supplies, R = 100 , R = 30 Ω  
T
S
R
S
Figure 16. A Recommended Y Load Circuit  
An additional load circuit, similar to one commonly  
used with ECL and PECL, is shown in Figure 17.  
Transmission Line  
INPUT  
OUTPUT  
Transmission Line  
R /2  
T
R /2  
T
Recommended Resistor Values:  
For 5 V and 3.3 V Nom Supplies, R = 100 ,  
T
V
T
= V - 2.55 V  
CC  
INPUT  
OUTPUT  
R
= 100  
W
+
V
T
T
_
R
R
S
Recommended Resistor Values:  
For 5-V Nominal Supplies, R = 200 W  
S
S
Figure 17. A Recommended PECL-Style Load  
Circuit  
For 3.3-V Nominal Supplies, R = 75 W  
S
Figure 15. A Recommended pi Load Circuit  
An important feature of all of these recommended  
load circuits is that they ensure that both of the  
emitter follower output transistors remain active  
(conducting current) at all times. When deviating from  
these recommended values, it is important to make  
sure that the low-side output transistor does not turn  
off. Failure to do so increases the tskew2 and VOC(PP)  
values, increasing the potential for electromagnetic  
radiation.  
Another common load circuit, a Y load, is shown in  
Figure 16. The receiver-end line termination of RT is  
provided by the series combination of the two RT/2  
resistors, while the dc current path to ground is  
provided by the single resistor RS. Recommended  
values, as a function of the nominal supply voltage  
range, are indicated in the figure.  
12  
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PACKAGE OPTION ADDENDUM  
www.ti.com  
28-Aug-2010  
PACKAGING INFORMATION  
Status (1)  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
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Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
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TB5D1MDE4  
TB5D1MDW  
TB5D1MDWE4  
TB5D1MDWR  
TB5D1MDWRE4  
TB5D2HD  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
D
D
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
40  
40  
Pb-Free (RoHS)  
Pb-Free (RoHS)  
Pb-Free (RoHS)  
Pb-Free (RoHS)  
Pb-Free (RoHS)  
Pb-Free (RoHS)  
Pb-Free (RoHS)  
Pb-Free (RoHS)  
Pb-Free (RoHS)  
Pb-Free (RoHS)  
Pb-Free (RoHS)  
Pb-Free (RoHS)  
Pb-Free (RoHS)  
Pb-Free (RoHS)  
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Level-1-220C-UNLIM  
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DW  
DW  
DW  
DW  
D
40  
CU NIPDAU Level-2-250C-1YEAR/  
Level-1-220C-UNLIM  
40  
CU NIPDAU Level-2-250C-1YEAR/  
Level-1-220C-UNLIM  
2000  
2000  
40  
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Level-1-220C-UNLIM  
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Level-1-220C-UNLIM  
Purchase Samples  
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TB5D2HDE4  
TB5D2HDR  
D
40  
CU NIPDAU Level-2-250C-1YEAR/  
Level-1-220C-UNLIM  
D
2500  
2500  
40  
CU NIPDAU Level-2-250C-1YEAR/  
Level-1-220C-UNLIM  
TB5D2HDRE4  
TB5D2HDW  
D
CU NIPDAU Level-2-250C-1YEAR/  
Level-1-220C-UNLIM  
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DW  
DW  
DW  
DW  
CU NIPDAU Level-2-250C-1YEAR/  
Level-1-220C-UNLIM  
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TB5D2HDWE4  
TB5D2HDWR  
TB5D2HDWRE4  
40  
CU NIPDAU Level-2-250C-1YEAR/  
Level-1-220C-UNLIM  
2000  
2000  
CU NIPDAU Level-2-250C-1YEAR/  
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CU NIPDAU Level-2-250C-1YEAR/  
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Purchase Samples  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
28-Aug-2010  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
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Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
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14-Jul-2012  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TB5D1MDWR  
TB5D2HDR  
SOIC  
SOIC  
SOIC  
DW  
D
16  
16  
16  
2000  
2500  
2000  
330.0  
330.0  
330.0  
16.4  
16.4  
16.4  
10.75 10.7  
6.5 10.3  
10.75 10.7  
2.7  
2.1  
2.7  
12.0  
8.0  
16.0  
16.0  
16.0  
Q1  
Q1  
Q1  
TB5D2HDWR  
DW  
12.0  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2012  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
TB5D1MDWR  
TB5D2HDR  
SOIC  
SOIC  
SOIC  
DW  
D
16  
16  
16  
2000  
2500  
2000  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
38.0  
38.0  
38.0  
TB5D2HDWR  
DW  
Pack Materials-Page 2  
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