TB5T1_14 [TI]
DUAL DIFFERENTIAL PECL DRIVER/RECEIVER;
| 型号： | TB5T1_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL DIFFERENTIAL PECL DRIVER/RECEIVER 驱动 |
| 文件： | 总17页 (文件大小：429K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TB5T1
www.ti.com
SLLS589B–NOVEMBER 2003–REVISED MAY 2004
DUAL DIFFERENTIAL PECL DRIVER/RECEIVER
In circuits with termination resistors, the line remains
impedance- matched when the circuit is powered
down. The driver does not load the line when it is
powered down.
FEATURES
•
Functional Replacement for the Agere BTF1A
•
Driver Features
– Third-State Logic Low Output
– ESD Protection HBM > 3 kV, CDM > 2 kV
– No Line Loading when Vcc = 0
– Capable of Driving 50-Ω loads
– 2.0-ns Maximum Propagation Delay
– 0.2-ns Output Skew (typical)
All devices are characterized for operation from -40°C
to 85°C.
The logic inputs of this device include internal pull-up
resistors of approximately 40 kΩ that are connected
to VCC to ensure a logical high level input if the inputs
are open circuited.
PIN ASSIGNMENTS
DW AND D PACKAGE
(TOP VIEW)
•
Receiver Features
– High-Input Impedance Approximately 8 kΩ
– 4.0-ns Maximum Propagation Delay
– 50-mV Hysteresis
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RO1
DI1
RI1
RI1
VCC
ED
DO1
– Slew Rate Limited (1 ns min 80% to 20%)
– ESD Protection HBM > 3 kV, CDM > 2 kV
– -1.1-V to 7.1-V Input Voltage Range
Common Device Features
DO1
DO2
DO2
ER
GND
DI2
•
RI2
RI2
RO2
– Common Enable for Each Driver/Receiver
Pair
FUNCTIONAL BLOCK DIAGRAM
– Operating Temperature Range: -40°C to
85°C
DO1
DI1
– Single 5.0 V ± 10% Supply
DO1
– Available in Gull-Wing SOIC (JEDEC
MS-013, DW) and SOIC (D) Package
DO2
DI2
DO2
ED
DESCRIPTION
RI1
The TB5T1 device is a dual differential driver/receiver
circuit that transmits and receives digital data over
balanced transmission lines. The dual drivers trans-
late input TTL logic levels to differential pseudo-ECL
output levels. The dual receivers convert differen-
tial-input logic levels to TTL output levels. Each driver
or receiver pair has its own common enable control
allowing serial data and a control clock to be
transmitted and received on a single integrated cir-
cuit. The TB5T1 requires the customer to supply
termination resistors on the circuit board.
RO1
RI1
RI2
RO2
RI2
ER
ENABLE TRUTH TABLE
ED
0
ER
0
D1
D2
R1
R2
Active
Active
Active
Active
Active
Active
The power-down loading characteristics of the re-
ceiver input circuit are approximately 8 kΩ relative to
the power supplies; hence, it does not load the
transmission line when the circuit is powered down.
1
0
Disabled Disabled
Active Active
Disabled Disabled Disabled Disabled
0
1
Disabled Disabled
1
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TB5T1
www.ti.com
SLLS589B–NOVEMBER 2003–REVISED MAY 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PART NUMBER
TB5T1DW
TB5T1D
PART MARKING
TB5T1
PACKAGE
Gull-Wing SOIC
SOIC
LEAD FINISH
NiPdAu
NiPdAu
SnPb
STATUS
Production
Production
Production
Production
TB5T1
TB5T1LDW
TB5T1LD
TB5T1L
Gull-Wing SOIC
SOIC
TB5T1L
SnPb
POWER DISSIPATION RATINGS
PACK-
AGE
CIRCUIT
BOARD MODEL
POWER RATING THERMAL RESISTANCE, JUNCTION- DERATING FACTOR(1) POWER RATING
TA≤ 25°C
752 mW
1160 mW
814 mW
1200 mW
TO-AMBIENT WITH NO AIR FLOW
TA≥ 25°C
7.5 mW/°C
11.7 mW/°C
8.2 mW/°C
12 mW/°C
TA = 85°C
301 mW
466 mW
325 mW
481 mW
Low-K(2)
High-K(3)
Low-K(2)
High-K(3)
132.8°C/W
85.8°C/W
122.7°C/W
83.1°C/W
D
DW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted with no airflow.
(2) In accordance with the low-K thermal metric definitions of EIA/JESD51-3.
(3) In accordance with the high-K thermal metric definitions of EIA/JESD51-7.
THERMAL CHARACTERISTICS
PARAMETER
PACKAGE
VALUE
48.4
UNIT
D
DW
D
°C/W
°C/W
°C/W
°C/W
Junction-to-board
thermal resistance
θJB
55.2
45.1
Junction-to-case
thermal resistance
θJC
DW
48.1
2
TB5T1
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SLLS589B–NOVEMBER 2003–REVISED MAY 2004
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
0 V to 6 V
Supply voltage, VCC
Magnitude of differential bus (input) voltage, |VRI1 - VRI1|, |VRI2 - VRI2
|
8.4 V
(2)
Human Body Model
All pins
All pins
±3 kV
ESD
(3)
Charged-Device Model
±2 kV
Continuous power dissipation
Storage temperature, Tstg
See Dissipation Rating Table
-65°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(3) Tested in accordance with JEDEC Standard 22, Test Method C101.
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX UNIT
Supply voltage, VCC
4.5
-1.2(1)
0.1
5
5.5
7.2
6
V
V
Bus pin input voltage, VRI1, VRI1, VRI2, or VRI2
Magnitude of differential input voltage, |VRI1 - VRI1|, |VRI2 - VRI2
Operating free-air temperature, TA
|
V
-40
85
°C
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet, unless
otherwise noted.
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
Outputs disabled
MIN
TYP
MAX UNIT
40
40
mA
mA
ICC
Supply current
Outputs enabled
3
TB5T1
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SLLS589B–NOVEMBER 2003–REVISED MAY 2004
THIRD STATE
A TB5T1 driver produces pseudo-ECL levels and has a third state mode, which is different from a conventional
TTL device. When a TB5T1 driver is placed in the third state, the base of the output transistors are pulled low,
bringing the outputs below the active-low level of standard PECL devices. (For example: The TB5T1 low output
level is typically 2.7 V, while the third state noninverting output level is typically 1.2 V.) In a bidirectional,
multipoint bus application, the driver of one device, which is in its third state, can be back driven by another
driver on the bus whose voltage in the low state is lower than the 3-stated device. This could be due to
differences between individual driver's power supplies. In this case, the device in the third state controls the line,
thus clamping the line and reducing the signal swing. If the difference between the driver power supplies is small,
this consideration can be ignored. Again using the TB5T1 driver as an example, a typical supply voltage
difference between separate drivers of > 2 V can exist without significantly affecting the amplitude of the signal.
DRIVER ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
Output high voltage(1)
Output low voltage(1)
TEST CONDITIONS
MIN
VCC - 1.8
VOH - 1.4
0.7
TYP
VCC - 1.3
VOH - 1.2
1.1
MAX
VCC - 0.8
VOH - 0.7
1.4
UNIT
V
VOH
VOL
VOD
VOH
VOL
VOD
V
Differential output voltage, |VOH - VOL
Output high voltage(1)
Output low voltage(1)
|
|
V
VCC - 1.8
VOH - 1.4
0.5
VCC - 1.3
VOH - 1.1
1.1
VCC - 0.8
VOH - 0.5
1.4
V
TA = 0°C to 85°C
V
Differential output voltage, |VOH - VOL
V
VOC(PP) Peak-to-peak common-mode output voltage
CL= 5 pF, See Figure 7
VCC = 4.5 V
230
600
mV
VOZH
VOZD
VIL
Third state output high voltage(1)
Third state diferential output voltage(1) VDOn - VDOn
Input low voltage(3)
DO1, DO2
1.4
-0.47(2)
1.8
2.2
V
-0.6
VCC = 5.5 V
0.8
V
V
VIH
Input high voltage
VCC = 4.5 V
2
VIK
Input clamp voltage
VCC = 4.5 V, II = -5 mA
VCC = 5.5 V, VO = 0 V
VCC = 5.5 V, VOD = 0 V
VCC = 5.5 V, VI = 0.4 V
VCC = 5.5 V, VI = 2.7 V
VCC = 5.5 V, VI = 5.5 V
-1(2)
-250(2)
±10(2)
-400(2)
20
V
mA
mA
µA
µA
µA
pF
IOS
Short-circuit output current(4)
IIL
Input low current
Input high current
Input reverse current
Input Capacitance
IIH
IIH
CIN
100
5
(1) Values are with terminations as per Figure 6.
(2) This parameter is listed using a magnitude and polarity/direction convention, rather than an algebraic convention, to match the original
Agere data sheet.
(3) The input levels and difference voltage provide no noise immunity and should be tested only in a static, noise-free environment.
(4) Test must be performed one lead at a time to prevent damage to the device. No test circuit attached.
4
TB5T1
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SLLS589B–NOVEMBER 2003–REVISED MAY 2004
RECEIVER ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
VCC = 4.5 V, IOL = 8.0 mA
VCC = 4.5 V, IOH = -400 µA
VCC= 5.5 V
MIN TYP
MAX
0.4
UNIT
VOL
VOH
VIL
Output low voltage
V
V
V
V
V
Output high voltage
2.4
2
Enable input low voltage(1)
Enable input high voltage(1)
Enable input clamp voltage
Positive-going differential input threshold voltage(1)
0.8
VIH
VCC = 4.5 V
VIK
VCC = 4.5 V, II = -5 mA
n = 1 or 2
-1(2)
VTH+
VTH-
|VRin - VRin
|
100 mV
-100(2) mV
mV
Negative-going differential input threshold voltage(1) |VRin - VRin
|
n = 1 or 2
VHYST Differential input threshold voltage hysteresis
(VTH+- VTH-
)
50
IOZL
IOZH
IOS
IIL
Off-state output low current (high Z)
Off-state output high current (high Z)
Short circuit output current(3)
Enable input low current
VCC = 5.5 V, VO = 0.4 V
VCC = 5.5 V, VO = 2.4 V
VCC = 5.5 V
-20(2) µA
20 µA
-100(2) mA
-400(2) µA
20 µA
VCC = 5.5 V, VIN = 0.4 V
VCC = 5.5 V, VIN = 2.7 V
VCC = 5.5 V, VIN = 5.5 V
VCC = 5.5V, VIN = -1.2 V
VCC = 5.5V, VIN = 7.2 V
IIH
Enable input high current
IIH
Enable input reverse current
Differential input low current
Differential input high current
Output resistance
100 µA
-2(2) mA
IIL
IIH
1
mA
RO
20
Ω
(1) The input levels and difference voltage provide no noise immunity and should be tested only in a static, noise-free environment.
(2) This parameter is listed using a magnitude and polarity/direction convention, rather than an algebraic convention, to match the original
Agere data sheet.
(3) Test must be performed one lead at a time to prevent damage to the device.
DRIVER SWITCHING CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
1.2
MAX
UNIT
ns
tP1
Propagation delay time, input high to output(1)
Propagation delay time, input low to output(1)
Capacitive delay
CL= 5 pF, See Figure 2 and Figure 6
2
tP2
1.2
0.01
8
2
ns
∆tP
tPHZ
0.03 ns/pF
Propagation delay time,
high-level-to-high-impedance output
CL = 5 pF, See Figure 3 and Figure 6
12
12
12
12
ns
ns
ns
ns
tPLZ
tPZH
tPZL
Propagation delay time,
low-level-to-high-impedance output
7
4
5
Propagation delay time,
high-impedance-to-high-level output
Propagation delay time,
high-impedance-to-low-level output
tskew1
tskew2
tskew(pp)
∆tskew
tTLH
Output skew, |tP1 - tP2
|
CL= 5 pF, See Figure 2 andFigure 6
0.15
0.15
0.1
0.3
1.1
1
ns
ns
ns
ns
ns
ns
Output skew, |tPHH - tPHL|, |tPLH - tPLL
Part-to-part skew(2)
|
Output skew, difference between drivers
Rise time (20%-80%)
0.3
2
0.7
0.7
tTHL
Fall time (80%-20%)
2
(1) Parameters tP1 and tP2 are measured from the 1.5 V point of the input to the crossover point of the outputs (see Figure 2).
(2) tskew(pp) is the magnitude of the difference in propagation delay times between any specified outputs of two devices when both devices
operate with the same supply voltage, at the same temperature, and have identical packages and test circuits.
5
TB5T1
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SLLS589B–NOVEMBER 2003–REVISED MAY 2004
RECEIVER SWITCHING CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
2.5
MAX
UNIT
tPLH
tPHL
tPLH
tPHL
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
4
4
CL = 0 pF(1), See Figure 4 and Figure 8
ns
ns
2.5
3
5.5
5.5
CL = 15 pF, See Figure 4 and Figure 8
CL = 5 pF, See Figure 5 and Figure 9
3
Propagation delay time,
high-level-to-high-impedance output
tPHZ
tPLZ
6
6
12
12
0.7
4
ns
ns
ns
ns
ns
Propagation delay time,
low-level-to-high-impedance output
Load capacitance (CL) = 10 pF, See
Figure 4 and Figure 8
tskew1
Pulse width distortion, |tPHL - tPLH|
Load capacitance (CL) = 150 pF, See
Figure 4 and Figure 8
CL = 10 pF, TA = 75°C, See Figure 4
and Figure 8
0.8
1.4
∆tskew1p-p
Part-to-part output waveform skew(2)
Same part output waveform skew(2)
CL = 10 pF, TA = -40°C to 85°C, See
Figure 4 and Figure 8
1.5
0.3
12
ns
ns
ns
∆tskew
CL = 10 pF, See Figure 4 and Figure 8
Propagation delay time,
high-impedance-to-high-level output
tPZH
3
4
CL = 10 pF, See Figure 5 and Figure 8
Propagation delay time,
high-impedance-to-low-level output
tPZL
12
ns
tTLH
tTHL
Rise time (20%—80%)
Fall time (80%—20%)
1
1
4
4
ns
ns
CL = 10 pF, See Figure 5 and Figure 8
(1) The propagation delay values with a 0 pF load are based on design and simulation.
(2) Output waveform skews are when devices operate with the same supply voltage, same temperature, have the same packages and the
same test circuits.
10
8
t
PLH
6
4
2
0
t
PHL
0
50
100
150
200
C
L
− Load Capacitance − pF
NOTE: This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The total
delay is the sum of the delay due to external capacitance and the intrinsic delay of the device. Intrinsic delay is listed
in the table above as the 0 pF load condition. The incremental increase in delay between the 0 pF load condition and
the actual total load capacitance represents the extrinsic, or external delay contributed by the load.
Figure 1. Typical Propagation Delay vs Load Capacitance at 25°C
6
TB5T1
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SLLS589B–NOVEMBER 2003–REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
2.4 V
1.5 V
0.4 V
INPUT
t
t
t
t
P2
P1
V
V
V
OH
OL
OH
OUTPUTS
OUTPUT
t
PHH
PLL
(V
+ V )/2
OL
OH
V
V
OL
t
PLH
PHL
OH
(V
+ V )/2
OL
OUTPUT
OUTPUT
OH
V
V
V
OL
OH
OL
80%
20%
80%
20%
t
TLH
t
THL
Figure 2. Driver Propagation Delay TImes
2.4 V
ED
1.5 V
0.4 V
t
t
PZH
PHZ
V
V
V
OH
OL
OL
+0.2 V
−0.1 V
OUTPUT
V
OL
OUTPUT −0.47 V
t
t
PLZ
PZL
V
V
OL
−0.1 V
OUTPUT
OL
A. NOTE: In the third state, OUTPUT is 0.47 V (minimum) more negative than OUTPUT.
Figure 3. Driver Enable and Disable Delay Times for a High Input
7
TB5T1
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SLLS589B–NOVEMBER 2003–REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION (continued)
3.7 V
3.2 V
2.7 V
INPUT
INPUT
t
t
PLH
PHL
V
OUTPUT
80%
OH
80%
1.5 V
20%
20%
V
OL
t
t
THL
TLH
Figure 4. Receiver Propagation Delay Times
2.4 V
1.5 V
0.4 V
ER
V
t
t
t
t
PZH
PZL
PLZ
PHZ
OH
OUTPUT
V
0.2 V
OL
0.2 V
0.2 V
0.2 V
Figure 5. Receiver Enable and Disable Timing
Parametric values specified under the Electrical Characteristics and Timing Characteristics sections for the data
transmission driver devices are measured with the following output load circuits.
100 W
C
200 W
C
L
200 W
L
CL includes test−fixture and probe capacitance.
Figure 6. Driver Test Circuit
8
TB5T1
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SLLS589B–NOVEMBER 2003–REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION (continued)
V
OC
V
OH
50 W
50 W
OUTPUTS
V
OL
C
=
P
C
200 W
200 W
C
L
L
2 pF
V
OC
CL includes test−fixture and probe capacitance.
V
OC(PP)
A. NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf = 1 ns, pulse repetition
rate (PRR) = 0.25 Mbps, pulse width = 500 ± 10 ns. CP includes the instrumentation and fixture capacitance within
0,06 m of the D.U.T. The measurement of VOS(PP) is made on test equipment with a -3 dB bandwidth of at least 1
GHz.
Figure 7. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
5 V
2 k
TO OUTPUT
OF DEVICE
UNDER TEST
DIODES TYPE
458E, 1N4148,
OR EQUIVALENT
C
5 k
L
Figure 8. Receiver Propagation Delay Time and Enable Time (tPZH, tPZL) Test Circuit
TO OUTPUT
OF DEVICE
W
500
1.5 V
UNDER TEST
CL
Figure 9. Receiver Disable Time (tPHZ, tPLZ) Test Circuit
9
TB5T1
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SLLS589B–NOVEMBER 2003–REVISED MAY 2004
TYPICAL CHARACTERISTICS
OUTPUT-VOLTAGE
vs
OUTPUT CURRENT, DRIVER
VOL AND VOH EXTREMES
vs
FREE-AIR TEMPERATURE, DRIVER
0
0
V
= 4.5 V to 5.5 V,
CC
T
A
= 255C
Load = 100 W
−0.5
−1
−0.5
V
OH
V
Max
OH
−1
−1.5
−2
−1.5
−2
V
Min
OH
V
Max
OL
−2.5
−3
V
OL
V
Min
OL
−2.5
−3
−3.5
−50
−40
−30
−20
−10
0
−50
0
50
100
150
T
A
− Free-Air Temperature − 5C
I
O
− Output Current − mA
Figure 10.
Figure 11.
DIFFERENTIAL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE, DRIVER
MINIMUM VOH AND VOL
vs
FREE-AIR TEMPERATURE, RECEIVER
1.6
1.4
1.2
4
3.5
3
V
= 4.5 V to 5.5 V
V
CC
= 4.5 V
CC
Load = 100 W
V
OH
Min
V
Max
DD
V
Nom
DD
2.5
2
1.5
1
V
DD
Min
1
VOL Min
50
0.5
0
0.8
−50
0
50
100
150
−50
0
100
150
T − Free−Air T emperature − °C
A
T − Free-Air Temperature − °C
A
Figure 12.
Figure 13.
10
TB5T1
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SLLS589B–NOVEMBER 2003–REVISED MAY 2004
TYPICAL CHARACTERISTICS (continued)
PROPAGATION DELAY TIME tP1 or tP2
vs
FREE-AIR TEMPERATURE, DRIVER
LOW-TO-HIGH PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE, RECEIVER
6
5
4
1.6
V
= 4.5 V to 5.5 V
CC
V
CC
= 5 V
Load = 100 W
1.4
1.2
Max
Max Delay
1
Nom
Min
Min Delay
3
2
0.8
0
−50
50
100
150
−50
0
50
100
150
0
T
A
− Free−Air Temperature − 5C
T − Temperature For Driver− 5C
Figure 14.
Figure 15.
HIGH-TO-LOW PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE, RECEIVER
6
5
4
V
CC
= 5 V
Max
Nom
3
2
Min
−50
0
50
100
150
T
A
− Free−Air Temperature − 5C
Figure 16.
11
TB5T1
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SLLS589B–NOVEMBER 2003–REVISED MAY 2004
APPLICATION INFORMATION
140
Power Dissipation
The power dissipation rating, often listed as the
package dissipation rating, is a function of the ambi-
ent temperature, TA, and the airflow around the
device. This rating correlates with the device's maxi-
mum junction temperature, sometimes listed in the
absolute maximum ratings tables. The maximum
junction temperature accounts for the processes and
materials used to fabricate and package the device,
in addition to the desired life expectancy.
D, Low−K
DW, Low−K
120
100
80
There are two common approaches to estimating the
internal die junction temperature, TJ. In both of these
methods, the device internal power dissipation PD
needs to be calculated This is done by totaling the
supply power(s) to arrive at the system power
dissispation:
DW, High−K
D, High−K
60
40
0
100
200
300
400
500
ǒ
Ǔ
ȍ
Air Flow − LFM
VSn ISn
Figure 17. Thermal Impedance vs Air Flow
and then subtracting the total power dissipation of the
external load(s):
The standardized θJA values may not accurately
represent the conditions under which the device is
used. This can be due to adjacent devices acting as
heat sources or heat sinks, to nonuniform airflow, or
to the system PCB having significantly different ther-
mal characteristics than the standardized test PCBs.
The second method of system thermal analysis is
more accurate. This calculation uses the power
dissipation and ambient temperature, along with two
device and two system-level parameters:
ȍ(
)
VLn ILn
The first TJ calculation uses the power dissipation
and ambient temperature, along with one parameter:
θJA, the junction-to-ambient thermal resistance, in
degrees Celsius per watt.
The product of PD and θJA is the junction temperature
rise above the ambient temperature. Therefore:
•
•
•
•
θJC, the junction-to-case thermal resistance, in
degrees Celsius per watt
θJB, the junction-to-board thermal resistance, in
degrees Celsius per watt
θCA, the case-to-ambient thermal resistance, in
degrees Celsius per watt
θBA, the board-to-ambient thermal resistance, in
ǒ
Ǔ
TJ + TA ) PD qJA
Note that θJA is highly dependent on the PCB on
which the device is mounted and on the airflow over
the device and PCB. JEDEC/EIA has defined
standardized test conditions for measuring θJA. Two
commonly used conditions are the low-K and the
high-K boards, covered by EIA/JESD51-3 and
EIA/JESD51-7 respectively. Figure 17 shows the
low-K and high-K values of θJA versus air flow for this
device and its package options.
degrees Celsius per watt.
In this analysis, there are two parallel paths, one
through the case (package) to the ambient, and
another through the device to the PCB to the ambi-
ent. The system-level junction-to-ambient thermal im-
pedance, θJA(S), is the equivalent parallel impedance
of the two parallel paths:
ǒ
Ǔ
TJ + TA ) PD qJA(S)
where
ǒ
Ǔ
ƫ
ƪǒ
Ǔ
qJC)qCA qJB)qBA
qJA(S)
+
ǒ
Ǔ
qJC)qCA)qJB)qBA
12
TB5T1
www.ti.com
SLLS589B–NOVEMBER 2003–REVISED MAY 2004
Load Circuits
The test load circuits shown in Figure 6 and Figure 7 are based on a recommended pi type of load circuit shown
in Figure 18. The 100-Ω differential load resistor RT at the receiver provide proper termination for the
interconnecting transmission line, assuming it has a 100-Ω characteristic impedance. The two resistors RS to
ground at the driver end of the transmission line link provide dc current paths for the emitter follower output
transistors. The two resistors to ground normally should not be placed at the receiver end, as they shunt the
termination resistor, potentially creating an impedance mismatch with undesirable reflections.
Transmission Line
R
T
= 100 Ω
INPUT
OUTPUT
Recommended Resistor Values:
For 5 V Nom Supplies, R = 200 Ω.
R
S
R
S
S
For 3.3 V Nom Supplies, R = 75 Ω.
S
Figure 18. A Recommended pi Load Circuit
Another common load circuit, a Y load, is shown in Figure 19. The receiver-end line termination of RT is provided
by the series combination of the two RT/2 resistors, while the dc current path to ground is provided by the single
resistor RS. Recommended values, as a function of the nominal supply voltage range, are indicated in the figure.
Transmission Line
INPUT
OUTPUT
R /2
T
R /2
T
Recommended Resistor Values:
For 5 V Nom Supplies, R = 200 Ω, R = 90 Ω
T
S
For 3.3 V Nom Supplies, R = 100 Ω, R = 30 Ω
T
S
R
S
Figure 19. A Recommended Y Load Circuit
An additional load circuit, similar to one commonly used with ECL and PECL, is shown in Figure 20.
Transmission Line
INPUT
OUTPUT
R /2
T
R /2
T
Recommended Resistor Values:
For 5 V and 3.3 V Nom Supplies, R = 100 Ω,
T
V
T
= V − 2.55 V
CC
+
V
T
_
Figure 20. A Recommended PECL-Style Load Circuit
An important feature of all of these recommended load circuits is that they ensure that both of the emitter follower
output transistors remain active (conducting current) at all times. When deviating from these recommended
values, it is important to make sure that the low-side output transistor does not turn off. Failure to do so
increases the tskew2 and VOC(PP) values, increasing the potential for electromagnetic radiation.
13
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
TB5T1D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
40
2500
40
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1YEAR/
Level-1-220C-UNLIM
TB5T1DR
SOIC
SOIC
SOIC
D
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1YEAR/
Level-1-220C-UNLIM
TB5T1DW
DW
DW
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1YEAR/
Level-1-220C-UNLIM
TB5T1DWR
2000
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1YEAR/
Level-1-220C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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