TC213-40 [TI]

SPECIALTY ANALOG CIRCUIT, CDIP24, 2.54 MM PITCH, WINDOWED, CERAMIC, DIP-24;
TC213-40
型号: TC213-40
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

SPECIALTY ANALOG CIRCUIT, CDIP24, 2.54 MM PITCH, WINDOWED, CERAMIC, DIP-24

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TC213  
1024- × 512-PIXEL CCD IMAGE SENSOR  
SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991  
DUAL-IN-LINE PACKAGE  
(TOP VIEW)  
High-Resolution, Solid-State  
Frame-Transfer Image Sensor  
13.5-mm Image-Area Diagonal  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
OUT1  
AMP GND  
OUT2  
ADB  
ABGS  
SAG  
ABGI  
IAG  
1000 (H) × 510 (V) Active Elements in  
Image-Sensing Area  
2
3
Square Pixels  
4
Low Dark Current  
5
SUB  
SUB  
TDB  
SUB  
SUB  
IAG  
Electron-Hole Recombination Antiblooming  
Dynamic Range . . . More Than 60 dB  
High Sensitivity  
6
RST2  
RST1  
CDB  
7
High Photoresponse Uniformity  
High Blue Response  
8
9
SRG1  
SRG2  
TRG  
Single-Phase Clocking  
10  
11  
12  
ABGI  
SAG  
ABGS  
Solid-State Reliability With No Image  
Burn-in, Residual Imaging, Image  
Distortion, Image Lag, or Microphonics  
IDB  
description  
The TC213 is a frame-transfer charge-coupled device (CCD) image sensor that provides very high-resolution  
image acquisition for image-processing applications such as robotic vision, medical X-ray analysis, and  
metrology. The image format measures 12.00 mm horizontally by 6.12 mm vertically; the image-area diagonal  
is 13.5 mm. The image-area pixels are 12-µm square. The image area contains 510 active lines with 1000 active  
pixels per line. Two additional dark reference lines give a total of 512 lines in the image area, and 24 additional  
dark-reference pixels per line give a total of 1024 pixels per horizontal line.  
The storage section of the TC213 contains 512 lines with 1024 pixels per line. This area is protected from  
exposure to light by an aluminum light shield. Photoelectric charge that is generated in the image area of the  
TC213 can be transferred into the storage section in less than 500 µs. After image capture (integration time),  
the readout is accomplished by transferring the charge, one line at a time, into two serial registers located below  
the storage area, each of which contains 512 data elements and 12 dummy elements. One serial-register clocks  
out charge that is generated in the odd-numbered columns of pixels in the imaging area; the other serial-register  
processes charge from the even-numbered columns of the imaging area. The typical serial-register data rate  
is 10 megapixels per second. Three transfer gates are used to isolate the serial registers. If the storage area  
or storage and image areas need to be cleared of all charge, charge may be quickly transferred across the serial  
registers and into the clearing drain, which is located below the serial-register section.  
This MOS device contains limited built-in gate protection. During storage or handling, the device leads should be shorted together  
or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to SUB. Under no  
circumstances should pin voltages exceed absolute maximum ratings. Avoid shorting OUTn to ADB during operation to prevent  
damage to the amplifier. The device can also be damaged if the output terminals are reverse-biased and an excessive current is  
allowed to flow. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling  
Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.  
Copyright 1991, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2-1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TC213  
1024- × 512-PIXEL CCD IMAGE SENSOR  
SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991  
description (continued)  
Gated floating-diffusion detection structures are used with each serial register to convert charge to signal  
voltage. External resets allow the application of off-chip correlated clamp sample-and-hold amplifiers for  
low-noise performance. To provide high output-drive capability, both outputs are buffered by low-noise,  
two-stage, source-follower amplifiers. These two output signals can provide a data rate of 20 megapixels per  
second when combined off chip. An output of 30 frames per second with one field per frame is typical. At room  
temperature, the readout noise is 55 elecrons and a minimum dynamic range of 60 dB is available.  
The blooming protection incorporated into the sensor is based on recombining excess charge with charge of  
opposite polarity in the substrate. This antiblooming is activated by supplying clocking pulses to the  
antiblooming gate, which is an integral part of each image-sensing element. The storage area antiblooming gate  
is clocked only for charge transfer in normal use.  
The TC213 is built using TI-proprietary virtual-phase technology, which provides devices with high blue  
response, low dark signal, good uniformity, and single-phase clocking.  
The TC213 is characterized for operation from –10°C to 40°C.  
functional block diagram  
Top Drain  
19  
TDB  
16  
IAG  
21  
22  
Image Area With  
Blooming Protection  
IAG  
ABGI  
SAG  
15  
ABGI  
24 Dark Reference Elements  
23  
24  
4
14  
13  
SAG  
ABGS  
ADB  
Amplifiers  
ABGS  
6
Storage Area  
RST2  
3
7
1
IDB  
12  
OUT2  
RST1  
OUT1  
10  
9
SRG2  
SRG1  
Multiplexer, Transfer Gates,  
and Serial Registers  
11  
TRG  
Clearing Drain  
12 Dummy  
Elements  
8
CDB  
2
AMP GND  
2-2  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TC213  
1024- × 512-PIXEL CCD IMAGE SENSOR  
SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991  
sensor topology diagram  
1000 Pixels  
22 Pixels  
1 Pixel  
510 Lines  
2 Lines  
1 Pixel  
512 Lines  
Dummy Pixels  
12  
511  
511  
12  
Terminal Functions  
TERMINAL  
NAME NO.  
I/O  
DESCRIPTION  
ABGI  
ABGI  
15  
22  
13  
24  
4
I
I
I
I
I
Antiblooming gate for image area  
Antiblooming gate for image area  
Antiblooming gate for storage area  
Antiblooming gate for storage area  
Supply voltage for amplifier drain bias  
Amplifier ground  
ABGS  
ABGS  
ADB  
AMP GND  
CDB  
2
8
I
I
Supply voltage for clearing drain bias  
Image-area gate  
IAG  
IAG  
16  
21  
12  
1
I
Image-area gate  
IDB  
I
Supply voltage for input diode bias  
Output signal 1  
OUT1  
OUT2  
RST1  
RST2  
O
O
I
3
Output signal 2  
7
Reset gate 1  
6
I
Reset gate 2  
SAG  
SAG  
14  
23  
9
I
Storage-area gate  
I
Storage-area gate  
SRG1  
SRG2  
I
Serial-register gate 1  
10  
5
I
Serial-register gate 2  
SUB  
SUB  
SUB  
SUB  
Substrate and clock return  
Substrate and clock return  
Substrate and clock return  
Substrate and clock return  
Supply voltage for top drain bias  
Transfer gate  
17  
18  
20  
19  
11  
TDB  
TRG  
I
I
All pins of the same name should be connected together externally (i.e., pin 15 to pin 22,  
pin 13 to pin 24, etc.).  
2-3  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TC213  
1024- × 512-PIXEL CCD IMAGE SENSOR  
SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991  
detailed description  
The TC213 consists of four basic functional blocks: (1) the image-sensing area, (2) the image-storage area,  
(3) the multiplexer block with serial registers and transfer gates, and (4) the low-noise signal-processing  
amplifier block with charge-detection nodes. The location of each of these blocks is identified in the functional  
block diagram.  
image-sensing and image-storage areas  
Figures 1 and 2 show cross sections with potential well diagrams and top views of image-sensing elements. As  
light enters the silicon in the image-sensing area, free electrons are generated and collected in the potential  
wells of the sensing elements. During this time, blooming protection is activated by applying a burst of pulses  
to the antiblooming gate inputs every horizontal blanking interval. This prevents blooming caused by the spilling  
of charge from overexposed elements into neighboring elements. After integration is complete, the signal  
charge is transferred into the storage area (see Figure 5).  
There are 24 full columns of elements at the left edge of the image-sensing area that are shielded from incident  
light; these elements provide the dark reference used in subsequent video-processing circuits to restore the  
video black level. There are also two dark lines at the bottom of the image-sensing area that prevent charge  
leakage from the image-sensing area into the image-storage area.  
multiplexer with transfer gates and serial registers  
The multiplexer and transfer gates transfer charge line by line from the image-storage area columns into the  
corresponding serial registers and prepare it for readout. Figure 3 illustrates the layout of the multiplexing gate  
that vertically separates the pixels for input into the serial registers. Figure 4 shows the layout of the interface  
region between the serial-register gates and the transfer gates. Multiplexing is activated during the horizontal  
blanking interval by applying appropriate pulses to the transfer gates and serial registers; the required pulse  
timing is shown in Figure 6. A drain is also included to provide the capability to clear the image-sensing area  
of unwanted charge. Such charge can accumulate in the imager during the start-up of operation or under special  
circumstances when nonstandard timing is desired. The clear timing is given as part of the parallel-transfer  
timing in Figure 5.  
serial-register readout and video processing  
After transfer into the serial registers, the pixels are normally read out 180° out of phase (see Figure 7). Each  
serial register must be reset to the reference level before the next pixel is read out. The timing for the resets and  
their relationships to the serial-register pulses is shown in Figure 8. Figure 8 also shows the timing for the pixel  
clamp and sample and hold needed for an off-chip double-correlated sampling circuit. These two output signals  
can provide a data rate of 20 million pixels per second when combined off chip. After the charge is placed on  
the detection node, it is buffered and amplified by a low-noise, dual-stage source follower. Each serial register  
contains 12 dummy elements that are used to span the distance between the serial register and the output  
amplifier. A schematic is shown in Figure 9. The location of the dummy elements, which are considered to be  
part of the amplifiers, is shown in the functional block diagram. Figure 10 gives the timing for a single frame of  
video. An output of 30 frames per second with one field per frame is typical.  
2-4  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TC213  
1024- × 512-PIXEL CCD IMAGE SENSOR  
SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991  
Light  
12 µm(H)  
Clocked Barrier  
φ-IAG  
φ-ABG  
Virtual Barrier  
Antiblooming  
Clocking Levels  
12 µm(V)  
Antiblooming Gate  
Virtual Well  
Clocked Well  
Accumulated Charge  
Figure 1. Charge-Accumulation Process  
φ-PS  
Clocked Phase  
Virtual Phase  
Channel Stops  
Figure 2. Charge-Transfer Process  
Channel Stops  
Serial-  
Register  
Gate  
Channel  
Stop  
Clocked  
Wells  
Virtual  
Well  
Clocked  
Well  
Multiplexing  
Gate  
Transfer  
Gate  
Figure 3. Multiplexing-Gate Layout  
Figure 4. Interface-Region Layout  
2-5  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TC213  
1024- × 512-PIXEL CCD IMAGE SENSOR  
SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991  
1 µs  
Line 1  
Line 2  
Line 511  
Line 512  
IAG  
SAG  
High  
Intermediate  
Intermediate  
ABGI  
Low  
ABGS  
TRG  
SRG1  
SRG2  
RST1  
RST2  
High  
High  
SRG1 and SRG2 pulses are extended to equal TRG and SAG pulse widths during parallel transfers from the storage area to the  
clearing drain.  
Figure 5. Parallel-Transfer Timing  
2-6  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TC213  
1024- × 512-PIXEL CCD IMAGE SENSOR  
SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991  
CSYNC  
CBLNK  
TRG  
SRG1  
SRG2  
RST1 High  
RST2 High  
CL1 Low  
CL2 Low  
SH1  
SH2  
Low  
Low  
SAG  
ABGS  
Intermediate  
ABGI  
CPOB1  
CPOB2  
IAG  
Low  
SRG1 and SRG2 pulses are extended to equal TRG and SAG pulse widths during horizontal line transfer operation for readout.  
Figure 6. Horizontal Timing  
2-7  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TC213  
1024- × 512-PIXEL CCD IMAGE SENSOR  
SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991  
Dummy  
Black Reference  
2
Image  
1
2
3
11  
12  
1
11  
12  
1
2
3
SRG2  
SRG1  
1
2
3
12  
1
2
12  
1
2
3
NOTE A: A minimum of 524 clock pulses is required to transfer out all elements of a serial register. Overclocking is recommended.  
Figure 7. Start of Serial-Transfer Timing  
2-8  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TC213  
1024- × 512-PIXEL CCD IMAGE SENSOR  
SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991  
Sample-  
and-Hold  
Amplifier  
OUT  
Pixel  
Clamp  
CCD  
Buffer  
SRG  
RST  
CL  
SH  
SRG1  
RST1  
OUT1  
CL1  
SH1  
SRG2  
RST2  
OUT2  
CL2  
SH2  
NOTE A: The video-processing (off-chip) pulses are defined as follows:  
CL1 = Clamp pulse for video from OUT1  
CL2 = Clamp pulse for video from OUT2  
SH1 = Sample pulse for the sample-and-hold amplifier for video 1  
SH2 = Sample pulse for the sample-and-hold amplifier for video 2  
CSYNC = Composite video-sync pulse  
CBLNK = Composite video-blanking pulse  
CPOB1 = Dark-reference clamp pulse for video from OUT1  
CPOB2 = Dark-reference clamp pulse for video from OUT2  
Figure 8. Video-Process Timing  
2-9  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TC213  
1024- × 512-PIXEL CCD IMAGE SENSOR  
SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991  
Reference Generator  
ADB  
Reset Gate  
and  
Output Diode  
CCD Register  
Detection Node  
Two-Stage  
Source-  
Follower  
Amplifier  
Clocked Virtual  
Gate  
Gate  
OUTn  
SRGn  
RSTn  
Figure 9. Buffer Amplifier and Charge-Detection Node  
2-10  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TC213  
1024- × 512-PIXEL CCD IMAGE SENSOR  
SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991  
Horizontal  
Timing  
Vertical  
Timing  
IAG  
SAG  
TRG  
541 Pulses  
512 Pulses  
SRG1  
SRG2  
ABGI  
ABGS  
RST1  
RST2  
CBLNK  
Figure 10. Clock Timing Requirements – Continuous Mode  
2-11  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TC213  
1024- × 512-PIXEL CCD IMAGE SENSOR  
SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991  
spurious nonuniformity specification  
The spurious nonuniformity specification of the TC213 CCD grades 30 and 40 is based on several sensor  
characteristics:  
Amplitude of the nonuniform line or pixel  
Polarity of the nonuniform pixel  
Black  
White  
Nonuniform line or pixel count  
The CCD sensors are characterized in both an illuminated condition and a dark condition. In the dark condition,  
the nonuniformity is specified in terms of absolute amplitude as shown in Figure 11. In the illuminated condition,  
the nonuniformity is specified as a percentage of the total illumination as shown in Figure 12.  
The pixel nonuniformity specification for the TC213 is as follows (CCD video-output signal is 50 mV ±10 mV):  
NONUNIFORMITY TYPE  
TC213-30  
TC213-40  
Maximum amplitude = 1.4 mV  
Line  
Number with amplitude greater than 1 mV is 6  
White spot (40°C)  
White spot (25°C)  
Maximum amplitude = 25 mV  
Maximum amplitude = 8 mV  
Maximum amplitude = 12 mV  
Number with amplitude greater Number with amplitude greater  
than 6 mV = B  
than 10 mV = B  
Maximum amplitude = 20%  
Maximum amplitude = 25%  
Black spot (% of total illumination)  
Total number of nonuniformities  
Number with amplitude greater Number with amplitude greater  
than 10% = C  
than 15% = C  
B + C < 11  
B + C < 51  
mV  
Amplitude  
% of Total  
Illumination  
t
t
Figure 11. Pixel Nonuniformity,  
Dark Condition  
Figure 12. Pixel Nonuniformity,  
Illuminated Condition  
2-12  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TC213  
1024- × 512-PIXEL CCD IMAGE SENSOR  
SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range for ADB, CDB, IDB, TDB (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 15 V  
Input voltage range for ABGI, ABGS, IAG, RST1, RST2, SAG, SRG1, SRG2, TRG . . . . . . . . –15 V to 15 V  
Operating free-air temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10°C to 40°C  
A
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30°C to 85°C  
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTE 1: All voltage values are with respect to the substrate terminal.  
recommended operating conditions  
MIN NOM  
MAX  
UNIT  
V
Supply voltage for ADB, CDB, IDB, TDB  
Substrate bias voltage  
11  
12  
0
13  
V
High level  
1.5  
–11  
1.5  
–11  
1.5  
–11  
1.5  
–11  
5
2
2.5  
–9  
2.5  
–9  
2.5  
–9  
2.5  
–9  
6
IAG  
Low level  
High level  
2
2
SAG  
SRG  
Low level  
High level  
Low level  
High level  
2
Input voltage, V  
I
V
RST1, RST2  
ABGI, ABGS  
Low level  
High level (ABGI only)  
5.5  
§
Intermediate level  
Low level  
–1.5  
–7.5  
1.5  
–1.2  
–7  
– 0.9  
6.5  
2.5  
High level  
2
TRG  
Low level  
–11  
–9  
RST1, RST2, SRG1, SRG2, TRG  
10  
1
Clock frequency, f  
Capacitive load  
IAG, SAG  
MHz  
clock  
ABGI, ABGS  
OUT1, OUT2  
1
8
pF  
Operating free-air temperature, T  
10  
40  
°C  
A
The algebraic convention, in which the least-positive (most negative) value is designated minimum, is used in this data sheet for clock voltage  
levels.  
§
Adjustment is required for optimal performance.  
2-13  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TC213  
1024- × 512-PIXEL CCD IMAGE SENSOR  
SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991  
electrical characteristics over recommended operating ranges of supply voltage and free-air  
temperature  
TYP  
PARAMETER  
MIN  
MAX  
UNIT  
dB  
Dynamic range (see Note 2)  
Charge conversion factor  
60  
6
µV/e  
Charge transfer efficiency (see Note 3)  
0.99990  
18  
Signal response delay time, τ (see Note 4 and Figure 16)  
Gamma (see Note 5)  
20  
0.94  
600  
0.1  
0.08  
60  
22  
0.99  
800  
ns  
0.89  
Output resistance  
1/f noise (5 kHz)  
µV/Hz  
electrons  
Noise voltage  
Random noise (f = 100 kHz)  
Noise equivalent signal  
ADB (see Note 6)  
SRGn (see Note 7)  
ABGx (see Note 8)  
20  
Rejection ratio at 10 MHz  
Supply current  
40  
dB  
30  
9
mA  
IAG, SAG  
ABGI, ABGS  
TRG  
15000  
8000  
350  
Input capacitance, C  
pF  
i
SRG1, SRG2  
200  
All typical values are at T = 25°C.  
A
NOTES: 2. Dynamic range is 20 times the logarithm of the mean noise signal divided by the saturation output signal.  
3. Charge transfer efficiency is one minus the charge loss per transfer in the output register (1046 transfers). The test is performed  
in the dark using an electrical input signal.  
4. Signal-response delay time is the time between the falling edge of the SRG clock pulse and the output signal valid state.  
5. Gamma (γ) is the value of the exponent in the equation below for two points on the linear portion of the transfer function curve (this  
value represents points near saturation):  
Exposure (2)  
Exposure (1)  
Output signal (2)  
Output signal (1)  
6. ADB rejection ratio is 20 times the logarithm of the ac amplitude on OUTn divided by the ac amplitude on ADB.  
7. SRGn rejection ratio is 20 times the logarithm of the ac amplitude on OUTn divided by the ac amplitude on SRGn.  
8. ABGx rejection ratio is 20 times the logarithm of the ac amplitude on OUTn divided by the ac amplitude on ABGx.  
2-14  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TC213  
1024- × 512-PIXEL CCD IMAGE SENSOR  
SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991  
optical characteristics, T = 25°C, integration time = 33 ms (unless otherwise noted)  
A
PARAMETER  
No IR filter  
MIN  
TYP  
518  
64  
MAX  
UNIT  
Measured at V  
(see Note 10)  
U
Sensitivity (see Note 9)  
mV/lx  
With IR filter  
Saturation signal, V  
(see Note 11)  
320  
200  
100  
mV  
mV  
sat  
Maximum usable signal, V  
use  
Blooming overload ratio (see Note 12)  
Image-area well capacity  
Smear (see Note 13)  
3
60 x 10  
electrons  
0.0016  
2
Dark current  
T
A
= 21°C  
0.027  
nA/cm  
TC213-30  
TC213-40  
TC213-30  
TC213-40  
TC213-30  
TC213-40  
5
5
Dark signal (see Note 14)  
Pixel uniformity  
T = 40°C  
A
mV  
8
mV  
mV  
12  
1.4  
1.4  
15%  
Column uniformity  
Shading  
V
O
= 1/2 V (see Note 10)  
U
NOTES: 9. Sensitivity is measured at an integration time of 33 ms with a source temperature of 2859 K. A CM-500 filter is used. Sensitivity is  
measured at any illumination level that gives an output voltage level less than V .  
U
10.  
V is the output voltage that represents the threshold of operation of antiblooming. V 1/2 saturation signal.  
U U  
11. Saturation is the condition in which further increase in exposure does not lead to further increase in output signal.  
12. Blooming is the condition in which charge is induced in an element by light incident on another element. Blooming overload ratio  
is the ratio of blooming exposure to saturation exposure.  
13. Smear is the measure of error induced by transferring charge through an illuminated pixel in shutterless operation. It is equivalent  
to the ratio of the single-pixel transfer time during a fast dump to the exposure time using an illuminated section that is 1/10 of the  
image area vertical height with recommended clock frequencies. Exposure time is 33 ms, the fast dump clocking rate during vertical  
timing is 1 MHz, and the illuminated section is 1/10 of the height of the image section.  
14. Dark-signal level is measured from the dark dummy pixels.  
timing requirements  
MIN  
200  
10  
MAX  
UNIT  
IAG  
SRG  
SAG  
200  
200  
100  
10  
t
r
Rise time  
ns  
TRG  
ABGI, ABGS  
RST1, RST2  
IAG  
200  
10  
SRG  
SAG  
200  
200  
100  
10  
t
f
Fall time  
ns  
TRB  
ABGI, ABGS  
RST1, RST2  
2-15  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TC213  
1024- × 512-PIXEL CCD IMAGE SENSOR  
SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991  
PARAMETER MEASUREMENT INFORMATION  
Blooming Point  
With Antiblooming  
Enabled  
V
O
Blooming Point  
With Antiblooming  
Disabled  
Dependent On  
Well Capacity  
V
sat (min)  
Level Dependent  
Upon Antiblooming  
Gate High Level  
V
use (max)  
V
use (typ)  
DR  
V
n
Lux  
(light input)  
camera white clip voltage  
DR (dynamic range)  
V
n
V
V
= noise floor voltage  
n
= minimum saturation voltage  
sat (min)  
V
= maximum usable voltage  
use (max)  
= typical user voltage (camera white clip)  
V
use (typ)  
NOTES: A.  
V
is defined as the voltage determined to equal the camera white clip. This voltage must be less than V  
.
use (typ)  
use (max)  
B. A system trade-off is necessary to determine the system light sensitivity versus the signal/noise ratio. By lowering the V  
the light sensitivity of the camera is increased; however, this sacrifices the signal/noise ratio of the camera.  
,
use (typ)  
Figure 13. Typical V , V  
Relationship  
sat use  
2-16  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TC213  
1024- × 512-PIXEL CCD IMAGE SENSOR  
SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991  
PARAMETER MEASUREMENT INFORMATION  
100%  
90%  
V
IH  
min  
Intermediate Level  
10%  
V
IL  
max  
0%  
t
r
t
f
Figure 14. Typical Clock Waveform for ABGI, ABGS, IAG, and SAG  
100%  
90%  
V
IH  
min  
Intermediate Level  
10%  
V
IL  
max  
0%  
t
f
t
r
Figure 15. Typical Clock Waveform for RST1, RST2, SRG1, SRG2, and TRG  
1.5 V to 2.5 V  
– 9 V to 11 V  
SRG  
– 9 V  
0%  
OUT  
90%  
100%  
CCD Delay  
τ
10 ns  
15 ns  
Sample  
and  
Hold  
Figure 16. SRG and OUT Waveforms  
2-17  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TC213  
1024- × 512-PIXEL CCD IMAGE SENSOR  
SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991  
APPLICATION INFORMATION  
V
SS  
V
OUT  
GND  
V
V
CC  
CC  
GND  
TMS3473B  
20  
1
2
3
4
5
6
7
8
9
V
IALVL  
I/N  
IAIN  
ABIN  
SS  
Master Oscillator  
CLK  
19  
18  
17  
16  
15  
14  
13  
12  
11  
V
IASR  
ABSR  
V
ABLVL  
IAOUT  
IAG  
ABGI  
GT1  
CC  
ABLVL  
MIDSEL  
SAIN  
PD  
CBLNK  
CL2  
CBLNK ABGS  
CL2  
CL1  
V
GT2  
SAG  
ABOUT  
SAOUT  
CC  
CL1  
CSYNC  
SH2  
GND  
2N3904  
CSYNC RST2  
V
V
CC  
AGB+  
10  
12 V  
OUT 2  
1 kΩ  
SH2  
SH1  
TRG  
RST1  
SRG1  
SRG2  
V
ABG –  
V
V
ABG–  
SS  
SH1  
Parallel Driver  
100 Ω  
V
ABG +  
User-Defined Timer  
TMS3473B  
20  
2N3904  
1
2
3
4
5
6
7
8
9
IALVL  
I/N  
IAIN  
ABIN  
MIDSEL  
SAIN  
PD  
V
SS  
IASR  
ABSR  
19  
18  
17  
16  
15  
14  
13  
12  
11  
12 V  
V
OUT 1  
100 Ω  
V
CC  
1 kΩ  
ABLVL  
IAOUT  
ABOUT  
SAOUT  
ABLVL  
V
CC  
GND  
V
V
AGB+  
TC213  
CC  
10  
V
V
V
SS  
ABG –  
ABG –  
1
2
3
4
5
6
7
8
9
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
OUT1  
ABGS  
AMP GND SAG  
Parallel Driver  
V
OUT2  
ADB  
ABGI  
IAG  
ABG +  
SN28846  
SEL0OUT  
GND  
PD  
SRG3IN  
SRG2IN  
SRG1IN  
TRGIN  
NC  
SUB  
SUB  
TDB  
SUB  
SUB  
IAG  
ABGI  
SAG  
ABGS  
12 V  
RST2  
RST1  
CDB  
SRG1  
SRG2  
TRG  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
1
2
3
4
5
6
7
8
9
V
SS  
SEL0  
NC  
V
CC  
10  
11  
12  
V
CC  
SRG3OUT  
SRG2OUT  
SRG1OUT  
TRGOUT  
IDB  
12 V  
Image Sensor  
SEL1OUT  
V
CC  
10  
V
SEL1  
SS  
Serial Driver  
SN28846  
SEL0OUT  
DC VOLTAGES  
ADB  
12 V  
5 V  
10 V  
2 V  
V
V
V
CC  
SS  
20  
1
2
3
4
5
6
7
8
9
V
SS  
19  
18  
17  
16  
15  
14  
13  
12  
11  
GND  
PD  
SEL0  
NC  
V
CC  
ABLVL  
2.5 V  
4 V  
–6 V  
SRG3IN  
SRG2IN  
SRG1IN  
TRGIN  
NC  
V
CC  
V
V
SRG3OUT  
SRG2OUT  
SRG1OUT  
TRGOUT  
ABG+  
ABG–  
SEL1OUT  
V
CC  
SEL1  
10  
V
SS  
Serial Driver  
SUPPORT CIRCUITS  
APPLICATION  
Serial driver  
DEVICE  
PACKAGE  
FUNCTION  
SN28846DW  
20 pin small outline  
20 pin small outline  
Driver for TRG, SRG1, SRG2, RST1, RST2  
Driver for IAG, SAG, ABGI, ABGS  
TMS3473BDW  
Parallel driver  
Figure 17. Typical Application Circuit Diagram  
2-18  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TC213  
1024- × 512-PIXEL CCD IMAGE SENSOR  
SOCS013B – AUGUST 1989 – REVISED DECEMBER 1991  
MECHANICAL DATA  
The package for the TC213 consists of a ceramic base, a glass window, and a 24-lead frame. The glass window is  
sealed to the package by an epoxy adhesive. The package leads are configured in a dual in-line organization and  
fit into mounting holes with 2,54 mm (0.1 in) center-to-center spacings.  
30,91 (1.217)  
30,05 (1.183)  
2,54 (1.000)  
2,67 (0.105) NOM  
12,50 (0.492) NOM  
4,93 (0.194) MAX  
3,81 (0.150) NOM  
0,33 (0.013)  
0,17 (0.007)  
2,00 (0.079)  
NOM DIA  
+0.01  
(+0.0004)  
6,80 (0.268)  
5,80 (0.228)  
23,29 (0.917)  
22,43 (0.883)  
20,93 (0.824)  
20,83 (0.820)  
22,83 (0.899)  
22,38 (0.881)  
3,75 (0.148)  
2,75 (0.108)  
Package Center  
(see Note C)  
Optical  
Center  
T.P.  
20,93 (0.824)  
20,83 (0.820)  
1,40 (0.055)  
0,64 (0.025)  
6,30 (0.248)  
4,70 (0.185)  
2,54 (0.100)  
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES  
7/94  
NOTES: A. Each pin centerline is located within 2,54 mm (0.1 inch) of its true longitudinal position.  
B. The optical center line and the center line of the ceramic package are not coincident.  
C. Maximum rotation is ±3.5°.  
2-19  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
2-20  
IMPORTANT NOTICE  
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue  
any product or service without notice, and advise customers to obtain the latest version of relevant information  
to verify, before placing orders, that information being relied on is current and complete. All products are sold  
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those  
pertaining to warranty, patent infringement, and limitation of liability.  
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent  
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily  
performed, except those mandated by government requirements.  
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF  
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL  
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR  
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER  
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO  
BE FULLY AT THE CUSTOMER’S RISK.  
In order to minimize risks associated with the customer’s applications, adequate design and operating  
safeguards must be provided by the customer to minimize inherent or procedural hazards.  
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent  
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other  
intellectual property right of TI covering or relating to any combination, machine, or process in which such  
semiconductor products or services might be or are used. TI’s publication of information regarding any third  
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.  
Copyright 1998, Texas Instruments Incorporated  

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