TCA5013ZAHR [TI]
智能卡接口 IC，可支持 1 张用户卡和 3 张 SAM | ZAH | 48 | -40 to 85;
| 型号： | TCA5013ZAHR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 智能卡接口 IC，可支持 1 张用户卡和 3 张 SAM | ZAH | 48 | -40 to 85 电信 电信集成电路 |
| 文件： | 总66页 (文件大小：1429K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TCA5013
ZHCSCU3C –JANUARY 2014–REVISED SEPTEMBER 2019
TCA5013 支持 1 张用户卡和 3 张 SAM 卡的多功能智能卡接口 IC
1 特性
3 说明
1
•
运行电源电压范围为 2.7V 至 5.5V
TCA5013 是专门用于销售点 (POS) 终端的智能卡接口
IC。此器件可实现 POS 终端与 EMV4.3、ISO7816-3
和 ISO7816-10 标准兼容卡的连接。除 1 张用户卡之
外，它最多还支持 3 张安全访问模块 (SAM) 卡。器件
由单电源供电并为所有卡提供电压。器件由标准 I2C 接
口控制并且能够按照 EMV4.3 和 ISO7816-3 标准激活
和取消激活卡。此外，该器件还支持 ISO7816-10 同步
卡。其所具有的 4 字节 FIFO 能够存储 ISO7816-10
类型 1 卡中的 ATR（复位应答）序列。可将同步卡
（ISO7816-10 类型 1 和类型 2）设置为自动激活或手
动激活。该器件具有多种节能模式，还支持通过“时钟
停止”程序或根据 ISO7816 - 3 标准将时钟频率降至最
低许可等级来实现智能卡自身的节能功能。TCA5013
中连接智能卡的所有引脚都具有 IEC 61000-4-2 8kV
接触放电保护。这使得系统无需借助外部 ESD 器件即
能够抵抗磁场中的 ESD。它采用 5mm x 5mm 球状引
脚栅格阵列 (BGA) 封装。器件的引脚分配使所有 IO
引脚均由其它引脚安全包围。这样可防止在器件工作期
间探测安全引脚。
•
•
•
支持 EMV 4.3、ISO7816-3 和 ISO7816-10 标准
支持 1 张用户卡和 3 张安全访问模块卡
所有智能卡接口引脚上均具有 IEC61000-4-2 8kV
接触放电 ESD 保护
•
•
低功耗模式可在不使用时（关断模式下）节能
可在出现短路、卡片拔出、过热或电源故障时自动
使卡取消激活
•
集成式直流/直流升压转换器可在所有卡接口上生成
5V 和 3V 的 VCC
•
•
自动生成卡时钟以同步卡激活
通过 4 字节 FIFO 存储 ISO7816-10 类型 1 卡的
ATR
•
所有智能卡的 IO 和时钟线均可编程设定上升/下降
时间控制
•
•
输入时钟频率高达 26MHz
防篡改封装设计
2 应用
•
•
高端销售点 (POS) 终端
器件信息(1)
支持多张安全访问卡的 EPOS 系统
器件型号
TCA5013
封装
封装尺寸（标称值）
NFBGA (48)
5.00mm x 5.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
简化原理图
VDD=VDDI= 3.3 V
CVDD = 100
µF
CVUP =
10 µF
LVDD =
10 µH
VDDI
100 nF
100 nF
DVUP
10k
PRES
C8
C4
User
Card
Slot
IOUC
CLKUC
RSTUC
VCCUC
10k
10k
10k 10k
200nF
200nF
200nF
GNDUC
SDA
SCL
INT
IOS1
CLKS1
SAM1
Card
Slot
GPIO1
RSTS1
VCCS1
GPIO2
GPIO3
GPIO4
TCA5013
GNDS
IOS2
CLKS2
SAM2
Card
Slot
RSTS2
VCCS2
SHDN
GNDS
IOMC1
CLKIN1
IOMC2
CLKIN2
IOS3
SAM3
Card
Slot
CLKS3
RSTS3
VCCS3
200nF
GNDS
1 µF
Copyright
© 2016, Texas Instruments Incorporated
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCPS253
TCA5013
ZHCSCU3C –JANUARY 2014–REVISED SEPTEMBER 2019
www.ti.com.cn
目录
6.20 Synchronous Type 1 Card Activation Timing
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 Handling Ratings....................................................... 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics—Power Supply and ESD . 6
6.6 Electrical Characteristics—Card VCC ........................ 6
6.7 Electrical Characteristics—Card RST ....................... 6
6.8 Electrical Characteristics—Card CLK ....................... 7
Characteristics ......................................................... 11
6.21 Synchronous Type 2 Card Activation Timing
Characteristics ......................................................... 11
6.22 Card Deactivation Timing Characteristics............. 11
6.23 Typical Characteristics.......................................... 11
Parameter Measurement Information ................ 12
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 17
8.5 Programming........................................................... 38
8.6 Register Maps......................................................... 41
Application and Implementation ........................ 55
9.1 Application Information............................................ 55
9.2 Typical Application ................................................. 55
7
8
9
6.9 Electrical Characteristics—Card Interface IO, C4 and
C8............................................................................... 7
6.10 Electrical Characteristics—PRES ........................... 8
6.11 Electrical Characteristics—IOMC1 and IOMC2 ...... 9
6.12 Electrical Characteristics—CLKIN1 and CLKIN2.... 9
6.13 Electrical Characteristics—A0 and SHDN .............. 9
6.14 Electrical Characteristics—INT ............................... 9
6.15 Electrical Characteristics—GPIO ............................ 9
6.16 Electrical Characteristics—SDA and SCL............. 10
10 Power Supply Recommendations ..................... 57
10.1 Power-On-Reset ................................................... 57
11 Layout................................................................... 57
11.1 Layout Guidelines ................................................. 57
11.2 Layout Example .................................................... 58
12 器件和文档支持 ..................................................... 59
12.1 商标....................................................................... 59
12.2 静电放电警告......................................................... 59
12.3 Glossary................................................................ 59
13 机械、封装和可订购信息....................................... 59
6.17 Electrical Characteristics—Fault Condition
Detection.................................................................. 10
6.18 I2C Interface Timing Requirements....................... 10
6.19 I2C Interface Timing Characteristics ..................... 10
4 修订历史记录
Changes from Revision B (January 2016) to Revision C
Page
•
•
Changed the Pin Configuration view ..................................................................................................................................... 3
Added: (Cold reset sequence) to Figure 6 ........................................................................................................................... 22
Changes from Revision A (July 2014) to Revision B
Page
•
•
•
•
已将数据表标题更改为“TCA5013 支持 1 张用户卡和 3 张 SAM 卡的多功能智能卡接口 IC” ................................................. 1
添加了特性：防篡改封装设计 ................................................................................................................................................. 1
更改了应用.............................................................................................................................................................................. 1
完整版文档.............................................................................................................................................................................. 1
Changes from Original (July 2014) to Revision A
Page
•
发布完整版文档....................................................................................................................................................................... 1
2
Copyright © 2014–2019, Texas Instruments Incorporated
TCA5013
www.ti.com.cn
ZHCSCU3C –JANUARY 2014–REVISED SEPTEMBER 2019
5 Pin Configuration and Functions
ZAH Package
NFBGA 48-Pins
Bottom View
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
G
H
J
PRES
GPIO4
GPIO3
GPIO2
GPIO1
VUP
LX
C8
A0
INT
SHDN
SCL
SDA
LDOCAP
TST4
GNDP
C4
VDD
CLKUC
GNDUC
RSTUC
TST3
IOUC
VCCUC
TST2
IOS3
GND
CLKIN1
IOMC1
IOMC2
VDDI
GND
CLKIN2
RSTS3
GNDS
TST1
IOS2
GNDS
GNDS
IOS1
VCCS1
CLKS3
VCCS3
RSTS2
CLKS2
VCCS2
RSTS1
CLKS1
Not to scale
Copyright © 2014–2019, Texas Instruments Incorporated
3
TCA5013
ZHCSCU3C –JANUARY 2014–REVISED SEPTEMBER 2019
www.ti.com.cn
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
A1
A2
A4
A5
A6
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
C2
C8
D1
D2
D8
D9
E1
E2
E8
E9
F1
F2
F8
F9
G2
G8
H1
H2
H3
H4
H5
H6
H7
H8
H9
J1
NAME
PRES
GPIO4
GPIO3
GPIO2
GPIO1
VUP
INPUT
I/O
User card presence detection
General purpose IO (5-V tolerant)
General purpose IO (5-V tolerant)
General purpose IO (5-V tolerant)
General purpose IO (5-V tolerant)
Boost output terminal
I/O
I/O
I/O
PWR
PWR
I/O
LX
Boost inductor input terminal
User card auxiliary IO (Open Drain)
I2C address selection pin. Connect to VDDI, GND.
Interrupt output (open drain)
Shutdown and reset pin
I2C clock input
C8
A0
INPUT
OUTPUT
INPUT
INPUT
I/O
INT
SHDN
SCL
I2C data
SDA
LDOCAP
TST4
PWR
NA
Internal LDO output. Connect to 1 µf decoupling capacitor.
Test pin. Grounded in application.
Power ground
GNDP
C4
PWR
I/O
User card auxiliary IO (Open drain)
Device main power supply
User card clock
VDD
PWR
OUTPUT
NA
CLKUC
TST3
Test pin. Grounded in application.
Device ground
GND
PWR
INPUT
PWR
I/O
CLKIN1
GNDUC
IOUC
IOMC1
GND
User card external clock input pin
User card ground pin
User card IO pin
I/O
User card microcontroller data IO
Device ground
PWR
OUTPUT
PWR
I/O
RSTUC
VCCUC
IOMC2
CLKIN2
TST2
User card reset output pin
User card VCC pin
SAM microcontroller data IO
User card external clock input pin
Test pin. Grounded in application.
Microcontroller interface supply voltage.
Reset output for SAM3
INPUT
NA
VDDI
PWR
OUTPUT
I/O
RSTS3
IOS3
IO pin for SAM3
GNDS
TST1
PWR
NA
Ground for all SAMs
Test pin. Grounded in application
IO pin for SAM2
IOS2
I/O
GNDS
GNDS
IOS1
PWR
PWR
I/O
Ground for all SAMs
Ground for all SAMs
IO pin for SAM1
VCCS1
CLKS3
VCCS3
RSTS2
CLKS2
VCCS2
RSTS1
CLKS1
PWR
OUTPUT
PWR
OUTPUT
OUTPUT
PWR
OUTPUT
OUTPUT
VCC for SAM1
Clock output for SAM3
J2
VCC for SAM3
J4
Reset output for SAM2
J5
Clock output for SAM2
J6
VCC for SAM2
J8
Reset output for SAM1
J9
Clock output for SAM1
4
Copyright © 2014–2019, Texas Instruments Incorporated
TCA5013
www.ti.com.cn
ZHCSCU3C –JANUARY 2014–REVISED SEPTEMBER 2019
6 Specifications
6.1 Absolute Maximum Ratings(1)(2)
over operating free-air temperature range (unless otherwise noted)(3)
MIN
–0.3
–0.3
MAX
UNIT
V
VDD
Supply voltage range
Interface voltage range
6
4
VDDI
V
VDDI
+
Input voltage range on digital I/O pins referenced to VDDI
Input voltage range on digital I/O pins referenced to VCC
-0.3
-0.3
V
V
0.3
VI
VCC
0.3
+
Load current on GPIO pins
-15
-6
mA
mA
IOL
Load current on INT and SDA pins
(1) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(2) The package thermal impedance is calculated in accordance with JESD 51-7.
(3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 Handling Ratings
MIN
MAX
UNIT
Tstg
Storage temperature range
–65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
–4
4
V(ESD)
Electrostatic discharge
kV
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
-1.5
1.5
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
V
Supply voltage range – DC-DC enabled
Supply voltage Range – DC-DC disabled
Interface voltage range
2.7
5.25
1.65
5.5
5.5
3.6
180
85
VDD
V
VDDI
ICC(TOT)
TA
V
Sum of the currents that can be drawn on all Card VCC pins
Operating temperature range
mA
°C
–40
6.4 Thermal Information
TCA5013
ZAH
THERMAL METRIC(1)
UNIT
48 PINS
96.9
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
59.0
49.4
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
1.9
ψJB
58.6
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2014–2019, Texas Instruments Incorporated
5
TCA5013
ZHCSCU3C –JANUARY 2014–REVISED SEPTEMBER 2019
www.ti.com.cn
6.5 Electrical Characteristics—Power Supply and ESD
VDD = VDDI = 3.3 V; LVDD = 10 µH; CVDD = 10 µF; CVUP = 10 µF; TA = –40°C to 85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
VDD voltage below which SUPL fault is asserted
VDD voltage below which device will shutdown
VDDI voltage below which device will shutdown
Shutdown Mode at Tambient = 25 C
MIN
TYP
MAX
2.7
UNIT
V
VDDTH
VDDSH
VDDITH
IDDSH
VDD supervisor fault threshold
VDD shutdown threshold
VDDI shutdown threshold
VDD Shutdown current
VDD Standby current
2.45
2.0
V
1.4
1.6
V
22
28
µA
µA
IDDST
Shutdown Mode at Tambient = 25°C
300
650
IOMC1 = IOMC2 = VDDI
;
IDDA
CLKIN1 = CLKIN2 = GND; Tambient= 25°C
2
mA
Current consumption per card interface activated
Supply current
VCCUC = VCCS1 = VCCS2 = VCCS3 = 5 V;
fCLKIN1 = fCLKIN2 = fCLKUC = fCLKS1 = 5 MHz;
ICCUC = ICCS1 = 55 mA; ICCS2 = ICCS3 = 2 mA;
Tambient = 25°C
(1)
IDDA1
235
280
mA
IDDISH
IDDIA
VDD Interface shutdown current
VDD Interface supply current
Shutdown Mode at 25°C
3.5
5
µA
µA
All Card VCC = 5 V; CLKIN1 = CLKIN2 = 5 MHz; @ 25°C;
IOMC1 = IOMC2 = VDDI
290
300
Time from
tWAKE
Device wakeup time
SHDN > VIH to
INT < VOL
0.1
1
10
ms
fOSC
Internal Oscillator Frequency
DC-DC switching frequency
Measured on CLKUC, CLKS1,CLKS2,CLKS3
1.2
2.4
5.5
3.5
1.4
MHz
MHz
fDC-DC
If any card VCC is 5 V
VDC-DC
DC-DC output voltage
V
If all card VCC is 3 V or 1.8 V
IEC61000-4-2 level 4 ESD protection
on pins defined in Table 1
VESD-IEC
-8
8
kV
(1) Values highly dependent on external components like boost inductor and external rectifier. The specification is based on 75% boost
efficiency for max value and 85% efficiency for typical value
6.6 Electrical Characteristics—Card VCC
VDD = VDDI = 3.3 V; LVDD = 10 µH; CVDD = 10 µF; CVUP = 10 µF; TA = –40°C to 85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
4.75
2.85
1.71
4.65
2.76
1.62
TYP
MAX
5.25
3.15
1.89
5.35
3.24
1.98
90
UNIT
VCC = 5 V; ICC ≤ 65 mA
5
VCC
Card supply voltage
VCC = 3 V; ICC ≤ 65 mA
VCC = 1.8 V; ICC ≤ 45 mA
VCC = 5 V ; 40 nA.s current spike
VCC = 3 V ; 17.5 nA.s current spike
VCC = 1.8 V ; 11.1 nA.s current spike
Measured on VCC = 5 V, 3 V, 1.8 V
VCC = 5 V
3
V
1.8
V
V
Current pulses I < 100 mA,
t < 400 ns
∆VCC/∆ICC
VRIPPLE
ICC
Load transient response
Peak to peak ripple voltage
Card supply Current
V
mV
65
VCC = 3 V
65
mA
mV
VCC = 1.8 V
45
VDO
Card LDO dropout voltage
ICC = 65 mA
250
6.7 Electrical Characteristics—Card RST
VDD = VDDI = 3.3 V; LVDD = 10 µH; CVDD = 10 µF; CVUP = 10 µF; TA = –40°C to 85°C unless otherwise noted
PARAMETER
Output Low voltage
Output high voltage
Rise time
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VOL - RST
VOH - RST
tR - RST
IOL = -200 µA
0.1 VCC
IOH = 150 µA
0.9 VCC
V
CL = 30 pF ; 10% to 90%
CL = 30 pF ; 90% to 10%
0.1
0.1
µs
µs
tF - RST
Fall time
6
Copyright © 2014–2019, Texas Instruments Incorporated
TCA5013
www.ti.com.cn
ZHCSCU3C –JANUARY 2014–REVISED SEPTEMBER 2019
6.8 Electrical Characteristics—Card CLK
VDD = VDDI = 3.3 V; LVDD = 10 µH; CVDD = 10 µF; CVUP = 10 µF; TA = –40°C to 85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VOL - CLK
VOH - CLK
Output Low voltage
Output high voltage
IOL = -100 µA
IOH = 100 µA
0.1 VCC
0.9 VCC
V
CLK slew rate settings register =
0000b
7
9
CLK slew rate settings register =
0001b
CLK slew rate settings register =
0010b
11
13
13.5
14
15
16
17
18
19
20
21
22
23
25
CLK slew rate settings register =
0011b
CLK slew rate settings register =
0100b
CLK slew rate settings register =
0101b
CLK slew rate settings register =
0110b
CLK slew rate settings register =
0111b
CL = 30 pF ;
10% to 90%;
tR - CLK/ tF - CLK
Rise/Fall time
ns
CLK slew rate settings register =
1000b
CLK slew rate settings register =
1001b
CLK slew rate settings register =
1010b
CLK slew rate settings register =
1011b
CLK slew rate settings register =
1100b
CLK slew rate settings register =
1101b
CLK slew rate settings register =
1110b
CLK slew rate settings register =
1111b
CLKPU-PD-SKEW
Clock pull-up / pull-down skew tR-CLK – tF-CLK / tF-CLK; CL = 30 pF
10
20
55
%
MHz
%
fCLK
D
Frequency on CLK pin
Clock duty cycle
CL = 30 pF
Internal clock = 1.2 MHz; CL = 30 pF
45
6.9 Electrical Characteristics—Card Interface IO, C4 and C8
VDD = VDDI = 3.3 V; LVDD = 10 µH; CVDD = 10 µF; CVUP = 10 µF; TA = –40°C to 85°C unless otherwise noted
PARAMETER
Output Low Voltage
TEST CONDITIONS
MIN
0.9 VCC
0.6 VCC
TYP
MAX UNIT
VOL - C4, C8
VCC = 5 V
IOL = -1 mA
IOH = 20 µA
0.5
V
V
V
V
VOH - C4, C8
VIL - IO, C4, C8
VIH - IO, C4, C8
Output Low Voltage
Output Low Voltage
Output High Voltage
VCC = 5 V, 3 V, 1.8 V
0.4 VCC
VCC = 5 V;
IO fall time register setting = 00b
0.5
0.5
0.5
0.5
VCC= 5 V;
IO fall time register setting = 01b
VOL - IO, 5 V
Output Low Voltage
IOL = -1 mA
V
VCC= 5 V;
IO fall time register setting = 10b
VCC= 5 V;
IO fall time register setting = 11b
Copyright © 2014–2019, Texas Instruments Incorporated
7
TCA5013
ZHCSCU3C –JANUARY 2014–REVISED SEPTEMBER 2019
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Electrical Characteristics—Card Interface IO, C4 and C8 (continued)
VDD = VDDI = 3.3 V; LVDD = 10 µH; CVDD = 10 µF; CVUP = 10 µF; TA = –40°C to 85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VCC= 3 V;
IO fall time register setting = 01b
0.3
VCC= 3 V;
IO fall time register setting = 10b
VOL - IO, 3 V
Output Low Voltage
IOL= -1 mA
0.3
0.3
V
VCC= 3 V;
IO fall time register setting = 11b
VCC= 3 V;
IO fall time register setting = 00b
0.3
VCC= 3 V;
IO fall time register setting = 01b
0.3
IOL= -500
µA
VOL - IO, 3 V, 500uA
Output Low Voltage
Output Low Voltage
V
VCC= 3 V;
IO fall time register setting = 10b
0.3
VCC= 3 V;
IO fall time register setting = 11b
0.3
VCC= 1.8 V;
IO fall time register setting = 11b
VOL - IO, 1.8 V
IOL= -1 mA
0.18
0.18
0.18
0.18
V
V
VCC= 1.8 V;
IO fall time register setting = 01b
VCC= 1.8 V;
IO fall time register setting = 10b
IOL= -500
µA
VOL - IO, 1.8 V, 500uA Output Low Voltage
VCC= 1.8 V;
IO fall time register setting = 11b
From IOMC pin to card IO; CL on card IO = 30 pF;
CL on IOMC = 30 pF; Prop delay measured from
70% VDDI to 70% of VCC for rising edge
Rising edge
tPD - R - IOMC - IO
400
250
ns
ns
propagation delay
From IOMC pin to card IO; CL on card IO = 30 pF;
CL on IOMC = 30 pF; Prop delay measured from
30% VDDI to 30% of VCC for falling edge;
Falling edge
tPD - F - IOMC - IO
propagation delay
CL = 30 pF ; 10% to 90%; IO fall time register setting
= 00b
tFO - IO
IO Line output fall time
IO Line output rise time
68
ns
ns
µs
µs
µs
µs
CL = 30 pF ; 10% to 90%; IO rise time register
setting = 100b
tRO - IO
100
C4, C8 Line output rise
time
tRO - C4, C8
tFO - C4, C8
tRI - IO, C4, C8
tFI - IO, C4, C8
CL = 30 pF ; 10% to 90%
CL = 30 pF ; 90% to 10%
10% to 90%
1.2
1.2
1.2
1.2
C4, C8 Line output fall
time
IO, C4, C8 Input rise
time
IO, C4, C8 Input fall
time
90% to 10%
CI - IO, C4, C8
Input capacitance
Pull-up resistance
F = 1 MHz
10
pF
RPU - IO, C4, C8
IO, C4, C8 pull-up to VCC
4.25
8.1
kΩ
6.10 Electrical Characteristics—PRES
VDD = VDDI = 3.3 V; LVDD = 10 µH; CVDD = 10 µF; CVUP = 10 µF; TA = –40°C to 85°C unless otherwise noted
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
VIL - PRES
VIH - PRES
ILEAK - PRES
Input Low voltage
0.3 VDDI
V
V
Input high voltage
0.7 VDDI
Input leakage current
Voltage on pin = VDDI
1
µA
Time from transition on PRES pin to PRESL bit being
set
tDEB(P)
tDEB(D)
20
ms
µs
Debounce time
Time from transition on PRES pin to start of
deactivation sequence (RST going low)
100
8
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6.11 Electrical Characteristics—IOMC1 and IOMC2
VDD = VDDI = 3.3 V; LVDD = 10 µH; CVDD = 10 µF; CVUP = 10 µF; TA = –40°C to 85°C unless otherwise noted
PARAMETER
TEST CONDITION
MIN
0.8 VDDI
0.7 VDDI
TYP
MAX
UNIT
VOL- IOMC
VOH - IOMC
VIL - IOMC
VIH - IOMC
Output low voltage
IOL = -100 µA
IOH = 20 µA
0.2 VDDI
V
V
V
V
Output high voltage
Input low signal
0.3 VDDI
Input high signal
From Card IO pin to IOMC; CL on card IO = 30 pF;
Prop delay measured from 30% VCC to 30% of VDDI for
falling edge;
Falling edge propagation
delay
tPD - F - IO - IOMC
250
400
ns
ns
From Card IO pin to IOMC; CL on card IO = 30 pF;
Prop delay measured from 70% VCC to 70% of VDDI for
rising edge;
Rising edge propagation
delay
tPD - F - IO - IOMC
tRO - IOMC
tFO - IOMC
tRI - IOMC
tFI - IOMC
CI - IOMC
RPU - IOMC
Output rise time
Output fall time
Input rise time
CL = 30 pF ; 10% to 90%
CL = 30 pF ; 90% to 10%
10% to 90%
1.2
1.2
1.2
1.2
10
µs
µs
µs
µs
pF
kΩ
Input fall time
90% to 10%
Input capacitance
Pull-up resistance
Pull-up to VDDI
11
6.12 Electrical Characteristics—CLKIN1 and CLKIN2
VDD = VDDI = 3.3 V; LVDD = 10 µH; CVDD = 10 µF; CVUP = 10 µF; TA = –40°C to 85°C unless otherwise noted
PARAMETER
Input Low voltage
Input high voltage
Rise time
TEST CONDITION
MIN
TYP
MAX
UNIT
V
VIL - CLKIN
VIH - CLKIN
tR - CLKIN
tF - CLKIN
fCLKIN
0.2 VDDI
0.8 VDDI
V
10% to 90%
90% to 10%
0.1
0.1
26
µs
Fall time
µs
Input clock frequency
MHz
6.13 Electrical Characteristics—A0 and SHDN
VDD = VDDI = 3.3 V; LVDD = 10 µH; CVDD = 10 µF; CVUP = 10 µF; TA = –40°C to 85°C unless otherwise noted
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
V
VIL - A0, SHDN
VIH - A0, SHDN
ILEAK - A0, SHDN
CI - A0, SHDN
RPU - SHDN
input Low voltage
0.2 VDDI
input high voltage
0.8 VDDI
V
Input leakage current
Input Capacitance
Pull-up resistance on SHDN
Voltage on pin = VDDI
Pull-up to VDDI
1
µA
pF
MΩ
10
2.5
6.14 Electrical Characteristics—INT
VDD = VDDI = 3.3 V; LVDD = 10 µH; CVDD = 10 µF; CVUP = 10 µF; TA = –40°C to 85°C unless otherwise noted
PARAMETER
Input leakage current
Output low voltage
TEST CONDITION
Voltage on pin = VDDI
IOL = -3 mA
MIN
TYP
MAX
1
UNIT
µA
ILEAK - INT
VOL - INT
0.2 VDDI
V
6.15 Electrical Characteristics—GPIO
VDD = VDDI = 3.3 V; LVDD = 10 µH; CVDD = 10 µF; CVUP = 10 µF; TA = –40°C to 85°C unless otherwise noted
PARAMETER
Output low voltage
Output low current
Input leakage current
TEST CONDITION
MIN
TYP
MAX
0.2 VDDI
10
UNIT
V
VOL - GPIO
IOL - GPIO
IOL = -10 mA
mA
µA
ILEAK - GPIO
Voltage on pin = VDDI
1
RPU on INT= 10 k; CL on INT 20 pF;
GPIO and INT transition referenced to 0.5 VDDI
TPD - GPIO
State transition on GPIO to INT assertion
4
µs
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6.16 Electrical Characteristics—SDA and SCL
VDD = VDDI = 3.3 V; LVDD = 10 µH; CVDD = 10 µF; CVUP = 10 µF; TA = –40°C to 85°C unless otherwise noted
PARAMETER
Input leakage current
SDA output low voltage
SDA max output low current
Input low signal
TEST CONDITION
MIN
TYP
MAX
UNIT
µA
V
ILEAK - SDA, SCL
VOL - SDA, SCL
IOL - SDA, SCL
VIL - SDA, SCL
VIH - SDA, SCL
Voltage on pin = VDDI
1
0.1 VDDI
10
IOL = -3 mA
VOL = 0.3 V
mA
V
0.2 VDDI
Input high signal
0.8 VDDI
V
6.17 Electrical Characteristics—Fault Condition Detection
VDD = VDDI = 3.3 V; LVDD = 10 µH; CVDD = 10 µF; CVUP = 10 µF; TA = –40°C to 85°C unless otherwise noted
PARAMETER
Shutdown temperature
Shutdown current
TEST CONDITION
MIN
125
160
–15
–70
–20
TYP
MAX
145
260
15
UNIT
°C
TSD
ISD
On card VCC pins
200
mA
mA
mA
mA
On card IO pins
On card CLK pins
On card RST pins
ILIM
Output current limit
70
20
6.18 I2C Interface Timing Requirements(1)
STANDARD MODE
I2C BUS
FAST MODE
I2C BUS
FAST MODE PLUS
(FM+) I2C BUS
PARAMETER
UNIT
MIN
MAX
MIN
MAX
400
MIN
MAX
fscl
tsch
tscl
tsp
I2C clock frequency
I2C clock high time
I2C clock low time
I2C spike time
I2C serial data setup time
I2C serial data hold time
I2C input rise time
100
1000
kHz
μs
μs
ns
ns
ns
ns
ns
μs
μs
μs
μs
μs
4
0.6
1.3
0.26
0.5
4.7
50
50
50
tsds
tsdh
ticr
250
0
100
0
50
0
1000
300
300
300
300
120
120
120
ticf
I2C input fall time
tocf
tbuf
tsts
tsth
tsps
I2C output fall time; 10 pF to 400 pF bus
I2C bus free time between Stop and Start
I2C Start or repeater start condition setup time
I2C Start or repeater start condition hold time
I2C Stop condition setup time
300
4.7
4.7
4
1.3
0.6
0.6
0.6
0.5
0.26
0.26
0.26
4
(1) Refer to the Parameter Measurement Information section for more information.
6.19 I2C Interface Timing Characteristics(1)
PARAMETER
MIN
TYP
MAX
450
UNIT
ns
tvd(data)
tvd(ack)
Valid data time; SCL low to SDA output valid
Valid data time of ACK condition; ACK signal from SCL low to SDA (out) low
450
ns
(1) Refer to Parameter Measurement Information section for more information.
10
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6.20 Synchronous Type 1 Card Activation Timing Characteristics
PARAMETER
TEST CONDITION
MIN TYP MAX UNIT
tS1-RST-HI
CL= 30 pF ; VCC= 5 V; See Figure 4.
60
70
80
15
32
32
90
µs
µs
µs
µs
µs
µs
µs
%
tS1-CLK-HI
CL= 30 pF ; VCC= 5 V; See Figure 4.
CL= 30 pF ; VCC= 5 V; See Figure 4.
CL= 30 pF ; VCC= 5 V; See Figure 4.
CL= 30 pF ; VCC= 5 V; See Figure 4.
CL= 30 pF ; VCC= 5 V; See Figure 4.
CL= 30 pF ; VCC= 5 V; See Figure 4.
CL= 30 pF ; VCC= 5 V; See Figure 4.
10 12.5
tS1-RST-CLK
tS1-CLK-RST
tS1-CLK-LO
tS1-CLK-PER
tS1-ATR-SETUP
Duty cycle
25
25
28
28
80
70
22.5
1
25 27.5
45
50
55
6.21 Synchronous Type 2 Card Activation Timing Characteristics
PARAMETER
TEST CONDITION
MIN TYP MAX UNIT
tS2-VCC-CLK
tS2-CLK-C4
tS2-CLK-HI
CL= 30 pF ; VCC= 5 V; See Figure 5.
5
14
7
20
18
9
µs
µs
µs
CL= 30 pF ; VCC= 5 V; See Figure 5.
CL= 30 pF ; VCC= 5 V; See Figure 5.
22
11
6.22 Card Deactivation Timing Characteristics
PARAMETER
TEST CONDITION
MIN TYP
MAX UNIT
tDEAC-TOTS
CL= 30 pF ; VCC= 5 V; See Figure 7.
CL= 30 pF ; VCC= 5 V; See Figure 7.
CL= 30 pF ; VCC= 5 V; See Figure 7.
CL= 30 pF ; VCC= 5 V; See Figure 7.
0.5
0.6
15
26
ms
µs
µs
µs
tDEAC-RST-CLK
tDEAC-RST-IO
10
22
12
24
45
tDEAC-RST-VCC
6.23 Typical Characteristics
30
CLK Rise Time
CLK Fall Time
25
20
15
10
5
0
Clock Slew Rate Settings Register Value (ns)
C001
CL = 30 pF
Figure 1. CLK Rise/Fall Time vs Clock Slew Rate Settings Register Value
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7 Parameter Measurement Information
t
f
t
r
t
SU;DAT
70 %
30 %
70 %
30 %
SDA
cont.
cont.
t
t
HD;DAT
VD;DAT
t
f
t
HIGH
t
r
70 %
30 %
70 %
30 %
70 %
30 %
70 %
30 %
SCL
t
HD;STA
t
LOW
th
9
clock
1 / f
S
SCL
st
1
clock cycle
t
BUF
SDA
SCL
t
VD;ACK
t
t
t
t
SU;STO
SU;STA
HD;STA
SP
70 %
30 %
Sr
P
S
th
9
clock
002aac938
VIL = 0.3 VDDI
VIH = 0.7 VDDI
Figure 2. Parameter Measurement Information for I2C Timing Characteristics and Requirements
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8 Detailed Description
8.1 Overview
TCA5013 is a smartcard interface IC that enables POS terminals to interface with EMV4.3 and ISO7816-3 and
ISO7816-10 compliant smartcards. The device has 4 smartcard interfaces (1 user card and 3 SAM cards).
TCA5013 is capable of card activation and deactivation per EMV4.3, ISO7816-3 and ISO7816-10 standards.
TCA5013 has two power supply pins - VDD and VDDI. VDD is the main power supply for the device and VDDI is
the reference supply for the interface operating voltage. VDD and VDDI need to ramped to within the
recommended operating conditions for the device to operate properly. Upon power up an internal Power-On-
Reset circuit initializes the digital core with all the registers in their default state as described in Register Maps.
TCA5013 can operate in various functional modes as defined in Device Functional Modes. When one of the
device power supplies is not applied, that is, VDD < VDDSH or VDDI < VDDITH the device is in Power Off Mode. None
of the device functions are available in this mode. Shutdown Mode is the lowest power operating mode in the
device. Shutdown mode is entered by asserting the SHDN = 0 when VDD > VDDSH and VDDI > VDDITH. The device
can detect card insertion and removal even in Shutdown mode. The device is in Standby mode when VDD
>
VDDSH or VDDI > VDDITH and the SHDN pin = 1. When any of the 4 smartcard interfaces is activated, the device
enters active mode (see Active Mode). The user card interface module can be activated in synchronous type 1,
synchronous type 2, asynchronous or manual operation mode. For synchronous type 1 and synchronous type 2
operation modes, the device can automatically generate activation sequences per the ISO7816-10 standard (see
Synchronous Type 1 Operating Mode and Synchronous Type 2 Operating Mode). For asynchronous cards the
device performs the activation sequence and also verifies the response from the card meets the requirements
per ISO7816-3 and EMV4.3 standards (see Asynchronous Operating Mode). The device also supports WARM
reset ( see Warm Reset Sequence) and card deactivation (see Deactivation Sequence) of smartcards per the
ISO7816-3 and EMV4.3 standards. The SAM card interface modules can only be activated in aynchronous
operation mode.
All smartcard interfaces have the standard CLK, IO and RST pins (as defined by EMV4.3 and ISO7816
standards). All these pins are designed to have internal current limiting to prevent device damage when shorted.
CLK and IO pins also provide automatic level translation to the voltage at which the card has been activated.
Rrise time and fall time of the CLK and IO pins can also be controlled using digital register settings (see IO Rise
Time and Fall Time control and CLK Rise Time and Fall Time Control). In addition to the CLK, IO and RST pins
the user card interface also has PRES pin to detect card insertion and removal (see User Card Insertion /
Removal Detection). C4 and C8 pins, as defined by ISO7816-10, are also present on the user card interface (see
User Card Interface Module).
The device has internal boost and LDOs to generate the card activation voltage depending on the operating
voltage required by the specific card being interfaced with. It also has a voltage supervisor that monitors VDD and
VDDI and responds as described in Interrupt Operation . The power management section is described in more
detail in Power Management.
In addition to these functions the device provides 8kV IEC 61000-4-2 ESD protection on all pins that interface to
smartcards. This removes the need for any external ESD protection on the board, thereby providing system
robustness without compromising system security (removable components on secure lines).
TCA5013 is configured using a standard I2C interface that is capable of up to 1 MHz operation. The I2C interface
is also used to read the status of various fault conditions that the device can detect. The I2C operation is
described in detail in I2C Interface Operation.
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8.2 Functional Block Diagram
VDD
LX
VUP
User Card Interface
Module
LDOCAP
LDO
Boost
VCCUC
IOUC
Card VCC LDO
GNDP
GNDP
IO level translator
CLK level translator
RST level translator
User card IO
CLKUC
RSTUC
multiplexer
IOMC1
CLKIN1
VDDI
C4
C8
User card
clock divider
and multiplexer
C4
C8 buffers
&
PRES
PRES detection logic
GNDUC
Voltage
supervisor
Oscillator
SAM 1 Interface Module
VCCS1
IOS1
Card VCC LDO
IO level translator
CLK level translator
RST level translator
IOMC2
SAM card
CLKS1
IO multiplexer
RSTS1
GNDS
CLKIN2
SAM clock
divider and
multiplexer
SAM 2 Interface Module
VCCS2
IOS2
Card VCC LDO
IO level translator
CLK level translator
RST level translator
SCL
SDA
I
2C
interface
CLKS2
RSTS2
GNDS
Digital core
and register map
SAM 3 Interface Module
INT
SHDN
A0
VCCS3
IOS3
Card VCC LDO
IO level translator
CLK level translator
RST level translator
CLKS3
RSTS3
GNDS
GNDP
GPIO1 GPIO2
GPIO3 GPIO4
TST1
TST2
TST3
TST4
14
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8.3 Feature Description
8.3.1 Card Interface Modules
TCA5013 has 1 user card interface module and 3 SAM card interface modules. All card modules have level
translators and an LDO to support interfacing with smartcards operating at different voltages.
8.3.2 SAM Card Interface Modules
All SAM card interface modules can operate per the EMV4.3 and ISO7816-3 standard and support asynchronous
operating mode. All SAM card interface modules have the standard IO, CLK and RST pins. Detailed operation of
these pins is described in section IO operation, CLK operation and RST operation.
8.3.3 User Card Interface Module
User card interface module can also operate per the EMV4.3 and ISO7816-3 standard and support
asynchronous operating mode. In addition, the user card interface module also supports synchronous type 1
operating mode and synchronous type 2 operating mode, per ISO7816-10. Like the SAM card interface modules,
the user card interface module also has IO, CLK, and RST pins. The user card interface module also has a
PRES pin that is used for detection of user card insertion or removal.
C4 and C8 are two pins that are only present on the user card interface. These are open drain bi-directional IOs
that are controlled by the bit [5] and bit [4] of user card synchronous mode settings register (Reg 0x09) when the
card interface is activated. These bits act as both control and status bits for the C4 and C8 signals. If a ‘0’ is
written to either of these bits the corresponding pin is driven low by the TCA5013. However, when a ‘1’ is written
to the register bit, the corresponding pin is pulled up by an internal pull-up resistor. In this state an external
device can drive the pin low. If the pin is driven low, then the corresponding bit in the register changes to reflect
the status of the pin.
8.3.4 Clock Division and Multiplexing
TCA5013 card interface modules all have a CLK pin that provide a clock signal that is used for smartcard
operation. This clock signal is generated based on an internal oscillator or from the CLKIN1/CLKIN2 input clock
signals, by the clock divider and multiplexer circuitry. The user card has a dedicated clock divider and
multiplexer. The user card CLK output can be a configured to be a function of the CLKIN1 frequency or the
internal oscillator frequency. CLKIN2 is shared by all the SAM card interface modules. The CLK output of each
SAM card can be independently configured based on the CLKIN2 frequency or the internal oscillator frequency.
CLK operation section describes the clock division and multiplexing in detail.
8.3.5 IO Multiplexing
IOMC1 and IOMC2 are connected to the IO pins in the card interface modules through IO multiplexer blocks.
The user card IO module has a dedicated IO multiplexer, that can be connect or disconnect IOUC from the
IOMC1 pin. The IOMC2 is connected to the SAM card interface modules IO pins through the SAM IO multiplexer
block. The IOMC2 can only be connected to one of the SAM interface modules at any given time. IO operation
section describes IO multiplexing in detail.
8.3.6 GPIO Operation
The TCA5013 has four 5 V tolerant open drain GPIO pins that can be configured as inputs or outputs through
device settings register (Reg 0x42). If configured as outputs, each is capable of sinking up to 10mA of current. If
configured as inputs they will assert the INT line when a state change occurs on the pin. The minimum pulse
width for transition detection is 10 µs, that is, when a state transition occurs on a GPIO configured as an input, it
needs to hold its state for a minimum of 10 µs in order to guarantee detection by the TCA5013. This, however,
does not imply any glitch rejection on the GPIO pins. The GPIOs are available in Standby Mode and Active
Mode. GPIO state transitions are not tracked in shutdown mode.
8.3.7 Power Management Features
TCA5013 has a DC-DC boost and card LDOs that enable it to generate regulated smart card VCC from its input
power rails (VDD and VDDI). It also has an internal LDO that is used to power its internal circuits. The TCA5013
devices also have a voltage supervisor that monitors the VDD and VDDI rails to ensure they are stable and usable
for smartcard operation.
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Feature Description (continued)
8.3.8 ESD Protection
All the smart card interface pins in the TCA5013 devices are designed with in built IEC61000-4-2 level 4 8kV
contact ESD protection. Table 1 shows a list of pins with the 8kV ESD protection. The pins not listed below all
have 4kV HBM ESD protection.
Table 1. List of Pins with 8kV IEC ESD Protection
PIN
A1
B1
C2
D1
E2
F1
F2
H1
H2
H5
H8
H9
J1
SYMBOL
PRES
C8
TYPE
INPUT
IO
DESCRIPTION
User card presence detection
User card auxiliary IO (Open Drain)
User card auxiliary IO (Open Drain)
User card clock
User card IO
C4
IO
CLKUC
IOUC
OUTPUT
IO
RSTUC
VCCUC
VCCUC
IOS3
OUTPUT
PWR
User card RST
User card VCC
SAM3 RST
OUTPUT
IO
SAM3 IO
IOS2
IO
SAM2 IO
IOS1
IO
SAM1 IO
VCCS1
CLKS3
VCCS3
RSTS2
CLKS2
VCCS2
RSTS1
CLKS1
PWR
SAM1 VCC
OUTPUT
PWR
SAM3 CLK
J2
SAM3 VCC
J4
OUTPUT
OUTPUT
PWR
SAM2 RST
J5
SAM2 CLK
J6
SAM2 VCC
J8
OUTPUT
OUTPUT
SAM1 RST
J9
SAM1 CLK
8.3.9 I2C interface
The device has a standard I2C interface that is used to configure the device and to read the status of the device.
For detailed I2C operation refer to I2C Interface Operation.
16
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8.4 Device Functional Modes
At any given time the TCA5013 can be in one of several different functional modes. Figure 3 diagram shows the
different functional modes and describes how the device transitions from one mode to another. The blue bubbles
represent actual functional modes and the white bubbles represent transitional states that are used to move from
one functional mode to another.
Power off mode
VDD > VDDSH
VDDI > VDDITH
SHDN = 0
VDD < VDDSH
or
VDDI < VDDITH
VDD > VDDSH
VDDI > VDDITH
SHDN = 1
State change
on PRES pin
VDD < VDDSH
or
VDDI < VDDITH
Shutdown mode
Assert INT
SHDN = 1
Deactivate all
card slots
Power on
Reset
SHDN = 0
Standby mode
Deactivate all
card slots
Card
activation
command
VCC fail
Deactivate all
card slots
VCC Check
SHDN = 0
VCC
active
VDD < VDDTH
Or over
temperature
No other
card slot
active
VDDI < VDDITH
Active mode
Over current card
removal or
deactivation
command
Other cards
still active
Deactivate all
card slots
Figure 3. Device Operating Modes
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Device Functional Modes (continued)
8.4.1 Power Off Mode
The TCA5013 is in power off mode when VDD < VDDSH or VDDI < VDDITH. In power off mode none of the device
features are functional and available for use.
8.4.2 Shutdown Mode
TCA5013 is in shutdown mode when all the below conditions are true.
•
•
•
VDD > VDDSH
VDDI > VDDITH
SHDN = 0
Shutdown mode is a low power mode where all circuits except card insertion detection circuitry are shutdown.
Even I2C communication is disabled in shutdown mode. The only active circuit in the device is card insertion
detection circuit on the PRES pin (see User Card Insertion / Removal Detection). Shutdown mode is entered
from Active Mode or Standby Mode by asserting the SHDN pin. When entering shutdown mode from Active
Mode all active card interfaces are automatically deactivated.
8.4.3 Standby Mode
The TCA5013 is in standby mode when all the below conditions are true.
•
•
•
•
VDD > VDDSH
VDDI > VDDITH
SHDN = 1
No card interfaces are activated.
In standby mode, the device I2C and card detection circuits are fully functional. All other circuits are ready to be
activated based on I2C commands received from the microcontroller. Standby mode is entered from shutdown
mode by releasing the SHDN pin or from power down mode by powering up the device or from active mode by
deactivating all card interfaces.
8.4.4 Active Mode
The TCA5013 is in active mode when all the below conditions are true.
•
•
•
•
VDD > VDDSH
VDDI > VDDITH
SHDN = 1
At least one card interface is activated
In active mode, the device is fully functional with at least one of the card interfaces activated. The DC-DC
Boost and card LDOs are active and provide power to the card VCC pins of the active card interfaces. Active
mode can only be entered from standby mode by activating one of the card interfaces. When the device is in
active mode, the individual card interfaces can be active in different operating modes. The user card supports
Asynchronous Operating Mode, Synchronous Type 1 Operating Mode,Synchronous Type 2 Operating Mode,
or Manual Operating Mode. The SAM card interfaces can only be activated in asynchronous activation mode.
18
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Device Functional Modes (continued)
8.4.4.1 User Card Operating Mode Selection
The user card interface in the TCA5013 can be activated in different operating modes. When the
START_ASYNC bit (bit [0]; Reg 0x01) is set the user card interface is activated in asynchronous operating mode.
When START_SYNC bit (bit[0]; Reg 0x09) is set the user card interface is activated in synchronous type1,
synchronous type 2 or manual operating mode. When the START_SYNC bit is set, the operating mode is
determined by the ACTIVATION_TYPE bit (bit [6]; Reg 0x09) and CARD_TYPE bit (bit [7] Reg 0x09).
If ACTIVATION_TYPE bit (bit [6]; Reg 0x09) is set to ‘0’, the user card interface is activated in manual operating
mode. If the ACTIVATION_TYPE bit is set to’1’, the user card interface is set for automatic activation, where it
will be activated in synchronous type 1 or synchronous type 2 operating mode based on CARD_TYPE bit (bit [7]
Reg 0x09). If CARD_TYPE bit is set to ‘1’, the card interface is activated in synchronous type 2 operating mode.
If CARD_TYPE bit is set to ‘0’ the card interface is activated in synchronous type 1 operating mode.
Any changes made to the START_SYNC, START_ASYNC, CARD_TYPE or ACTIVATION_TYPE bits when the
user card interface is active, will be ignored and will have no effect on the device. These new settings will take
effect only on the next card interface activation following deactivation (see Deactivation Sequence).
8.4.4.2 Synchronous Type 1 Operating Mode
Synchronous type 1 operating mode is only supported on the user card interface. To enter synchronous
operating mode, the user card interface goes through the synchronous type 1 activation sequence. Figure 4
shows the synchronous type 1 activation sequence.
CLKIN1 shall be low before the synchronous type 1 activation sequence is initiated. The following bit settings are
required to initiate a synchronous type 1 activation sequence.
•
•
•
ACTIVATION_TYPE (bit [6]; Reg 0x09) = 1
CARD_TYPE (bit [7]; Reg 0x09) = 0
START_SYNC (bit [0]; Reg 0x09) = 1
VCCUC
t
S1-RST-HI
All High levels refer to 0 .9 Vcc
All Low levels refer to 0 .1 Vcc
t
t
t
= t < 0.5 μs
F
S1-RST-CLK
R
S1-CLK-RST
t
RSTUC
CLKUC
S1-CLK-HI
t
t
S1-CLK-LO
S1-CLK-PER
32 Clock cycles (4 Bytes)
t
t
S1-ATR-SETUP
S1-ATR-SETUP
Bit 1 to Bit 30 of
ATR response
Bit 0
Bit 31
IOUC
C 4
C 8
INT
Figure 4. Synchronous Type 1 Activation Sequence
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Device Functional Modes (continued)
Once synchronous type 1 activation has been initiated, the following sequence of events occurs on the user card
interface:
•
•
•
•
•
VCCUC, RSTUC, CLKUC, C4, C8 and IOUC are all default low.
VCC is applied to the VCCUC pin per the SET_VCC_UC bit (bit[7:6]; Reg 0x01).
After VCC is stable RSTUC and CLKUC pulses are applied per tS1-RST-HI and tS1-CLK-HI defined in Table 2.
After VCC is stable, the IOUC line is pulled up to VCC
.
After VCC is stable C4 and C8 reflect the value in their corresponding I2C register bits (bit[5] and bit[4]; Reg
0x09).
•
•
•
RSTUC is held low while the CLKUC line starts oscillating with a frequency of ~40Khz (generated from
internal oscillator).
The IO line is sampled on the 32 rising or falling (based on bit[1]; Reg 0x09) edges of CLK and stored in the
FIFO registers 0AH to 0DH.
At the end of the 32nd CLK pulse, the CLKUC is held low and the CLKUC pin is controlled by the clock
settings register (Reg 0x02).
•
•
•
•
•
IOUC is connected to IOMC1 if IO_EN_UC bit (bit[5] Reg 0x01) is set to 1.
INT_SYNC_COMPLETE bit (Bit[1]; REG 0x41) is set and the INT line is asserted low.
IOMC1 shall stay pulled up to VDDI i.e. IOMC1 shall not be pulled low until INT is asserted.
CLKIN1 shall toggle only after INT is asserted.
RSTUC is controllable by I2C after INT is asserted.
Table 2. Synchronous Type 1 Card Activation Timing Characteristics
MIN
60
TYP
70
MAX
80
UNIT
µs
tS1-RST-HI
tS1-CLK-HI
10
12.5
28
15
µs
tS1-RST-CLK
tS1-CLK-RST
tS1-CLK-LO
tS1-CLK-PER
Duty cycle
25
32
µs
25
28
32
µs
70
80
90
µs
22.5
45
25
27.5
55
µs
50
%
8.4.4.3 Synchronous Type 2 Operating Mode
Synchronous type 2 operating mode is only supported on the user card interface. To enter synchronous
operating mode, the user card interface goes through the synchronous type 2 activation sequence. Figure 5
shows the synchronous type 2 activation sequence.
CLKIN1 shall be low before the synchronous type 2 activation sequence is initiated. The following bit settings are
required to initiate a synchronous type 1 activation sequence.
•
•
•
ACTIVATION_TYPE (bit [6]; Reg 0x09) = 1
CARD_TYPE (bit [7]; Reg 0x09) = 1
START_SYNC (bit [0]; Reg 0x09) = 1
20
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t
S2-VCC-CLK
VCCUC
All High levels refer to 0.9Vcc
All Low levels refer to 0.1Vcc
t
S2-CLK-C4
t
= t < 0.5μs
F
R
CLKUC
t
S2-CLK-HI
C 4
IOUC
INT
RST stays LOW through entire activation
RSTUC
Figure 5. Synchronous Type 2 Activation Sequence
Once synchronous type 2 activation has been initiated, the following sequence of events occur on the user card
interface:
•
•
•
•
•
•
•
•
•
•
•
•
•
VCCUC, RSTUC, CLKUC, C4, C8 and IOUC are all default low.
VCC is applied to the VCCUC pin per the SET_VCC_UC bit (bit[7:6]; Reg 0x01).
A single pulse is applied to CLKUC per the tS2-CLK-HI timing defined in Table 3.
The C4 line is held low through the VCC ramp.
The C4 line is released high per the tS2-CLK-C4 timing defined in Table 3.
After C4 is released CLKUC is controlled by clock settings register (Reg 0x02).
After VCC is stable, the IOUC line is pulled up to VCC
.
After VCC is stable, C8 reflects value in bit [4] Reg 0x09.
IOUC is connected to IOMC1 if IO_EN_UC bit (bit[5] Reg 0x01) is set to 1.
INT_SYNC_COMPLETE bit (Bit[1]; REG 0x41) is set and the INT line is asserted low.
IOMC1 shall stay pulled up to VDDI , that is, IOMC1 shall not be pulled low until INT is asserted.
CLKIN1 shall toggle only after INT is asserted.
RSTUC is controllable by I2C after INT is asserted.
Table 3. Synchronous Type 2 Card Activation Timing Characteristics
MIN
5
TYP
20
18
9
MAX
UNIT
µs
tS2-VCC-CLK
tS2-CLK-C4
tS2-CLK-HI
14
7
22
11
µs
µs
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8.4.4.4 Manual Operating Mode
Manual operating mode is only supported on the user card interface. Unlike the other operating modes, the
manual operating mode does not have a defined activation sequence. CLKIN1 shall be low before the manual
activation sequence is initiated. The following bit settings are required to initiate a synchronous type 1 activation
sequence.
•
•
ACTIVATION_TYPE (bit [6]; Reg 0x09) = 0
START_SYNC (bit [0]; Reg 0x09) = 1
Once manual activation has been initiated the following sequence of events occur on the user card interface.
•
•
•
•
VCCUC, RSTUC, CLKUC, C4, C8 and IOUC are all default low.
VCC is applied to the VCCUC pin per the SET_VCC_UC bit (bit[7:6]; Reg 0x01)
After VCC is stable, the IOUC line is pulled up to VCC
After VCC is stable C4 and C8 reflect the value in their corresponding I2C register bits (bit[5] and bit[4]; Reg
0x09)
•
•
•
•
•
IOUC is connected to IOMC1 if IO_EN_UC bit (bit[5] Reg 0x01) is set to 1.
INT_SYNC_COMPLETE bit (Bit[1]; REG 0x41) is set and the INT line is asserted low.
IOMC1 shall stay pulled up to VDDI i.e. IOMC1 shall not be pulled low until INT is asserted.
CLKIN1 shall toggle only after INT is asserted.
RSTUC is controllable by I2C after INT is asserted.
8.4.4.5 Asynchronous Operating Mode
Asynchronous operating mode is supported on all card interfaces. To enter asynchronous operating mode, the
user card interface goes through the asynchronous activation sequence. Figure 6 shows the asynchronous
activation sequence. CLKIN1 shall be toggling before the asynchronous activation sequence is initiated. The
asynchronous activation sequence is initiated by setting the START_ASYNC bit (bit[0]) of the card interface
settings register (Reg 0x01 for User card, Reg 0x11 for SAM1, Reg 0x21 for SAM1, Reg 0x31 for SAM3) to ‘1’.
VCC
200CLK
cycles
IO ignored
200 CLK cycles
IO ignored
IO
42100CLK
Cycles
(EARLY+MUTE)
42100CLK
Cycles
(EARLY+MUTE)
CLK
RST
EARLY
answer
check
MUTE
answer
check
ATR Valid
Window
EARLY
answer
check
MUTE
answer
check
ATR Reception
Window
Card activation sequence
(Cold reset sequence)
Warm reset sequence
Figure 6. Asynchronous Activation and Warm Reset Sequence
22
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Once asynchronous activation has been initiated, the following sequence of events takes place on the card
interface:
•
•
•
•
VCC, RST, CLK, C4, C8 and IO are all default low.
VCC is applied to the VCC pin per the SET_VCC bits (bit [7:6] of card interface settings register).
After VCC is stable, the IO line is pulled up to VCC
.
After VCC is stable C4 and C8 reflect the value in their corresponding I2C register bits (bit[5] and bit[4]; Reg
0x09).
•
•
IO is connected to IOMC if IO_EN bit (bit[5] of card interface settings register) is set to 1.
The CLK line starts to oscillate based on the card clock settings register. Any change on the IO line during
the first 200 card clock cycles on the CLK pin is ignored.
•
•
After the first 42100 CLK cycles, the RST line is driven high.
If there is a high to low transition on the IO line before RST is high, the EARLY bit (bit[6]) and MUTE bit
(bit[5]) of the card interface status register (Reg 0x00 for user card, Reg 0x10 for SAM1, Reg 0x20 for SAM2
and Reg 0x30 for SAM3) is set and the INT pin is asserted low.
•
•
After RST is high, an internal counter starts counting CLK cycles. If there is a high to low transition on IO pin
before the internal counter reaches the value defined by in the EARLY_COUNT_HI register (Reg 0x03 for
user card, Reg 0x13 for SAM1, Reg 0x23 for SAM2, Reg 0x33 for SAM3) and EARLY_ COUNT_LO Register
(Reg 0x04 for user card, Reg 0x14 for SAM1, Reg 0x24 for SAM2, Reg 0x34 for SAM3) then the EARLY bit
in the card interface status register is set and INT is asserted.
If the internal counter reaches the value defined by MUTE_COUNT_HI register (Reg 0x05 for user card, Reg
0x15 for SAM1, Reg 0x25 for SAM2, Reg 0x35 for SAM3) and MUTE_COUNT_LO (Reg 0x06 for user card,
Reg 0x16 for SAM1, Reg 0x26 for SAM2, Reg 0x36 for SAM3) registers without a high to low transition on
the IO line, then the MUTE bit in the card interface status registers is set and INT pin is asserted low.
If the first high to low transition on IO pin happens very close to the clock edges (within ~10 ns) that defines the
ATR VALID window (see Figure 6), the TCA5013 response would be non-deterministic, that is, it may not be able
to identify whether the transition happened before or after the edge. This implies that the MUTE bit may or may
not be set if the IO transition happens very close to the clock edge defining the end of the ATR VALID window.
Likewise, if the IO transition happens very close to the clock edge defining the beginning of the EARLY window,
it may or may not set the EARLY bit.
8.4.4.6 Warm Reset Sequence
When a card interface is active in asynchronous mode, it is possible to initiate a warm reset sequence on the
card interface. The warm reset sequence is initiated by setting the WARM bit (bit [3]) of the card interface
settings register to ‘1’. Once warm reset is initiated the below sequence of events takes place on the card
interface.
•
•
•
•
•
•
•
•
VCC is already ramped and stable per the SET_VCC bits (bit[7:6] of card interface settings register).
CLK continues to oscillate per the card clock settings register.
RST pin is pulled low (high before warm reset was initiated).
C4 and C8 continue to reflect the value in their corresponding I2C register bits (bit[5] and bit[4]; Reg 0x09).
IO stays connected to IOMC if IO_EN bit (bit5 of card interface settings register) is set to 1.
Any change on the IO line during the first 200 card clock cycles after RST goes low is ignored.
After the first 42100 CLK cycles, the RST line is driven high.
If there is a high tow low transition on the IO line before RST is high, the EARLY bit (bit6) and MUTE bit (bit5)
of the card interface status register (Reg 0x00 for user card, Reg 0x10 for SAM1, Reg 0x20 for SAM2 and
Reg 0x30 for SAM3) is set and the INT pin is asserted low.
•
•
After RST is high, an internal counter starts counting CLK cycles. If there is a high to low transition on IO pin
before the internal counter reaches the value defined by in the EARLY_COUNT_HI register (Reg 0x03 for
user card, Reg 0x13 for SAM1, Reg 0x23 for SAM2, Reg 0x33 for SAM3) and EARLY_ COUNT_LO Register
(Reg 0x04 for user card, Reg 0x14 for SAM1, Reg 0x24 for SAM2, Reg 0x34 for SAM3) then the EARLY bit
in the card interface status register is set and INT is asserted.
If the internal counter reaches the value defined by MUTE_COUNT_HI register (Reg 0x05 for user card, Reg
0x15 for SAM1, Reg 0x25 for SAM2, Reg 0x35 for SAM3) and MUTE_COUNT_LO (Reg 0x06 for user card,
Reg 0x16 for SAM1, Reg 0x26 for SAM2, Reg 0x36 for SAM3) registers without a high to low transition on
the IO line, then the MUTE bit in the card interface status registers is set and INT pin is asserted low.
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8.4.4.7 Deactivation Sequence
After a card interface has been activated in a certain operating mode, it can be deactivated by I2C command or
certain interrupt events (see Interrupt Operation). The deactivation sequence is the same regardless of what
operating mode the card interface is in.
Figure 7 shows the deactivation sequence initiated by card extraction on the user card interface. It is to be noted
that the deactivation sequence starts 100 µs after the transition on PRES. This delay is intended to provide a
debounce period that provides unintended deactivation due to any glitch on the PRES pin. As mentioned
previously any of the card interfaces may be deactivated due to a supervisor fault, over current fault or over
temperature fault. In these cases there is no debounce period and the deactivation sequence is initiated as soon
as the internal fault signal is asserted.
Figure 8 shows the deactivation of any card interface initiated by I2C command. If the card interface is activated
in asynchronous mode, it can be deactivated by clearing (writing ‘0’) the START_ASYNC bit in the card interface
settings register. To deactivate the user card interface when it is activated in synchronous mode, the
START_SYNC bit should be cleared (write ‘0’).
100μs
PRES
t
DEAC-TOT
t
+
two card clock cycles
DEAC-RST-CLK
RST
CLK
IO
t
DEAC-RST-IO
t
DEAC-RST-VCC
VCC
< 0.4V
Figure 7. Deactivation Sequence
24
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<5μs
Rising edge of SCL
corresponding to ACK
I 2
C
SCL
t
DEAC-TOT
t
+ two card clock cycles
DEAC-RST-CLK
RST
CLK
t
DEAC-RST-IO
IO
t
DEAC-RST-VCC
VCC
<0 . 4 V
Figure 8. Card Deactivation Sequence Initiated by I2C Command
Table 4. Card Deactivation Timing Characteristics
MIN
0.4
10
TYP
0.5
12
MAX
0.6
15
UNIT
ms
µs
tDEAC-TOT
tDEAC-RST-CLK
tDEAC-RST-IO
tDEAC-RST-VCC
22
24
26
µs
33
36
39
µs
8.4.5 User Card Insertion / Removal Detection
User card interface module in the TCA5013 has a PRES pin that is used to detect the presence of a card in that
interface. In normal application the signal is connected to a switch that opens or closes when a card is inserted.
Whenever a transition is seen on the PRES pin, the PRESL bit (Reg 0x00, bit 2) will be set and INT pin is
asserted. Because this transition is associated with a mechanical switch, there is an internal debounce of ~20 ms
before the PRESL bit is set and the INT is asserted. If the device sees a transition on the PRESL pin when the
card interface is active, the device initiates a card deactivation sequence (see Deactivation Sequence). TCA5013
is capable of detecting card insertion even when it is in shutdown mode (see Shutdown Mode).
In addition to the PRESL_UC bit mentioned above, there is also a PRES_UC bit (Reg 0x00, bit 2), which
indicates to the host whether or not a card is present in the user card slot. In order to accommodate different
card cage topologies, the TCA5013 can be configured to detect card presence with a low to high or high to low,
transition on the PRES pin. The CARD_DETECT_UC bit (Reg 0x01, bit 2) is used to configure the device for
different card detection topologies. If CARD_DETECT_UC = 0 indicates to the TCA5013 that when a card is
inserted in the slot, the PRES pin shall be low. CARD_DETECT_UC = 1 indicates to the host that when a card is
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inserted in the slot the PRES pin shall be high. The status of the PRES_UC bit is based on the status of the
PRES pin and the CARD_DETECT_UC bit. The truth table in Table 1 shows the PRES_UC bit status based on
the CARD_DETECT_UC bit and the PRES pin. When coming out of power off mode (see Power Off Mode) or
shutdown mode (see Shutdown Mode) the CARD_DETECT_UC = 0. If there is a state transition on the PRES
pin when the device is in shutdown mode, the INT pin asserted (after the 20 ms debounce).
Table 5. Truth Table Defining Status of PRES Bit
CARD DETECT BIT
PRES PIN
PRES BIT
0
0
1
1
0
1
0
1
1
0
0
1
Figure 9 to Figure 14 show timing waveforms of device power up and coming out of shutdown with and without a
card inserted in the system. In below figures’ low to high PRES topology’ means that a high level on the PRES
pin indicates a card is present. In below figures high to low PRES topology’ means that a low level on the PRES
pin indicates a card is present. The below figures also show operation of INT pin and interrupt status register. For
detailed description of the interrupt operation, refer to Interrupt Operation section.
Debounce period
SHDN
released
by µC
20ms
Power on Reset
SHDN
(pull-up)
Card insertion /
extraction
PRES
POR interrupt
PRES bit =0
INT
PRES bit = 1
Interrupt
status
register
CARD
I2C
DETECT=1
read
Figure 9. Card detection in shutdown mode - Low to High PRES Topology
26
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Debounce period
20ms
SHDN
released
by µC
Power on reset
SHDN
pull-up
(
)
PRES
Card insertion/
extraction
POR
interrupt
INT
Interrupt
status
register
read
I2C
Figure 10. Card detection in shutdown mode - High to Low PRES Topology
Power on Reset
VDD /
VDDI
Card
Debounce period
20 ms
PRES
insertion
PRESL
Interrupt
POR interrupt
PRES bit = 1
PRES bit = 1
INT
PRES bit = 0
Interrupt
status
register
read
2
I C
CARD
DETECT = 1
Figure 11. Device power up without card inserted in system - Low to High PRES Topology
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Power on reset
VDD /
VDDI
Card
insertion
PRES
POR interrupt
PRESL
interrupt
PRES Bit = 0
Debounce period
20ms
PRES bit =1
INT
Interrupt
status
register
read
I2C
Figure 12. Device power up without card inserted in system - High to Low PRES Topology
Power on reset
VDD /
VDDI
Debounce period
100 us
Card slot
Card extracted
deactivated
PRES
PRESL
interrupt
POR interrupt
PRES bit = 0
INT
PRES bit =0
PRES bit=1
Debounce period
20ms
Interrupt
status
CARD
I2C
register
read
DETECT = 1
Figure 13. Device Power Up With Card Inserted in System - Low to High PRES Topology
28
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Power on reset
VDD/
VDDI
Card slot
deactivated
Debounce period
100us
Card extracted
PRES
PRESL
Interrupt
POR interrupt
PRES bit =1
PRES bit =0
INT
Debounce period
20ms
Interrupt
status
register
read
I2C
Figure 14. Device Power up with Card Inserted In System - High to Low PRES Topology
8.4.6 IO Operation
All card interfaces in the TCA5013 have an IO pin that connects data, to and from the microcontroller, with the
smartcard. The TCA5013 provides automatic level translation from IOMC pin operating voltage (VDDI) to the
voltage at which the card is activated (VCC).
8.4.6.1 IO Switching Control
The card interface IOs (IOUC, IOS1, IOS2 and IOS3) connect to the IOMC1 and IOMC2 through switches inside
the TCA5013.
The IOUC pin is connected to IOMC1 through an SPST (single-pole single-throw) switch. The switch is controlled
by the IO_EN_UC bit (Reg 0x01, Bit 5).The IO_EN_UC bit shall be set to 1 before card activation is started to
ensure that the host processor is able to receive the ATR response from the smartcard. When an I2C command
is received to open or close the switch, it is immediately implemented regardless of the status of IOUC or IOMC1
pins. It is therefore possible that the switch opens or closes during a rising or falling edge, which could result in a
glitch on the IOUC or IOMC1 pins.
The IOS1, IOS2 and IOS3 all are connected to IOMC2 through a SP3T (single-pole triple-throw) switch, such that
only one of the SAM interfaces can be connected to IOMC2 at any one time. The connection between the
IOMC2 and the SAM card IO pins is controlled by IO_EN_S1 (Reg 0x11, Bit 5), IO_EN_S2 (Reg 0x21, Bit 5),
IO_EN_S3 (Reg 0x31, Bit 5). If any one of the IO_EN bits is set for example, if SAM1 is initially connected by
setting IO_EN of the SAM1 interface settings register to 1. When the IO_EN bit of the SAM2 or SAM3 is set to 1,
the SAM1 gets disconnected and its IO_EN bit will be set to 0. Only one SAM can be connected to the IOUC2 at
one time and whenever the IO_EN bit of any SAM interface settings register is set to 1, all other IO_EN bits get
cleared (set to 0). Similar to the user card, the SAM IO mux can also result in a short duration pulse, if IOUC2 is
not in the same state as the SAMs being switched to/from. Also when making the switch, the TCA5013 uses a
break –before-make switch topology in order to avoid any glitches on the lines due to the switching itself.
8.4.6.2 IO Rise Time and Fall Time control
The rise time and fall time of the card interface IO pins can be controlled using the IO slew rate settings register
(Reg 0x07 for user card and Reg 0x17 for SAMs). The EMV4.3 specification, has strict restrictions on signal
perturbations (overshoot and undershoot during transition). Controlling the rise time and fall time of the signals
can help to meet these requirements.
Table 6 shows the typical IO rise time for different register settings (based on a typical 30 pF load).
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Table 6. IO Rise Time Register Settings
IO SLEW RATE SETTINGS
TYPICAL RISE TIME (ns)
REGISTER BIT [7:5]
000
001
010
011
100
101
110
111
60
60
80
80
100
100
120
120
Table 7 shows the typical IO fall time for different register settings (based on a typical 30 pF load). It should also
be noted that the output low logic level (VOL) is affected by the fall time settings. As the fall time becomes slower
(higher value of fall time) the VOL will be higher. Therefore, it is recommended that the fastest fall time setting
(smallest fall time value) for IO be used whenever possible. Table 7 also shows which settings are usable for the
different VCC voltages, without risk of violating the VOL levels required by the EMV4.3 and ISO7816
specifications.
Table 7. IO Fall Time Register Settings
IO SLEW TYPICAL FALL VCC = 5 V
VCC = 3 V VCC = 1.8 V
RATE
TIME (ns)
SETTINGS
REGISTER
BIT [4:3]
00
01
10
11
68
51
34
17
Usable
Usable
Usable
Usable
Not usable Not usable
Not usable Not usable
Usable
Usable
Not usable
Usable
8.4.6.3 Current Limiting on IO Pin
The card IO pins have a current limiting feature that prevents excess current from being drawn on them. The
actual current limit can vary based on the fall time setting used for the IO pin, but it is always within the limits
defined in Electrical Characteristics—Fault Condition Detection. When an external load tries to draw a current
higher than the limit, the device responds by adjusting the VOH or VOL to limit the current. The device does not
deactivate the card interface when over current limit of the IO pins are reached.
8.4.7 CLK Operation
All card interfaces in the TCA5013 have a CLK pin that provides a clock signal to the smartcard. The TCA5013
provides automatic level translation of the CLK signal from the CLKIN1/CLKIN2 operating voltage (VDDI) to the
voltage at which the card is activated (VCC).
8.4.7.1 CLK Switching
The CLK output on each of the smartcard interfaces can be controlled by the corresponding clock settings
register (Reg 0x02 for user card, Reg 0x12 for SAM1, Reg 0x22 for SAM2, Reg 0x32 for SAM3). The CLKIN1
pin is dedicated for the user card interface while The CLKIN2 is shared between the SAM interfaces. The clock
settings register allows the CLK output to be configured in one of 4 different modes.
A. CLK 0 mode - The CLK output of the card interface is static low.
B. CLK 1 mode - The CLK output of the card interface is static high.
C. CLK div mode - The CLK output is a divided down frequency of the CLKIN1 or CLKIN2 frequency. Bit [4:2] of
clock settings register defines the division ratio.
D. Internal CLK mode - The CLK output is at a fixed frequency (~1.2 MHz) based off the internal oscillator.
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The allowable changes in CLK output can vary depending on the mode in which the interface has been
activated. In asynchronous mode (see Asynchronous Operating Mode), The CLK output can be dynamically
switched from one state to another. Table 8 shows the permitted frequency transitions on CLK pin in
asynchronous mode. Any I2C command that attempts to switch the CLK frequency outside of these state
transitions can result in the change not happening on the output or other unpredictable behavior that could cause
device to lock up. If the device enters such a locked state, it can be reset by toggling SHDN pin.
Table 8. Permitted CLK Switching Operations in Asynchronous Mode
FROM
Internal CLK
Internal CLK
Internal CLK
CLK div
CLK div
CLK div
CLK 0
TO
CLK div
CLK 0
Permitted
Not Permitted
Not Permitted
Permitted
CLK 1
Internal CLK
CLK 0
Permitted
CLK 1
Permitted
CLK div
Internal CLK
CLK1
Permitted
CLK 0
Not Permitted
Not Permitted
Permitted
CLK 0
CLK 1
CLK div
Internal CLK
CLK 0
CLK 1
Not Permitted
Not Permitted
CLK 1
When command sets the device in Internal clock mode or CLK 0 mode or CLK 1 mode, the division ratio is
locked out, that is, when an I2C transaction that sets either one of the bits [7:5] of the card clock settings register
to 1, the remaining bits in the register (bit [4:2]) will not not be updated. It is to be noted that an asynchronous
activation cannot be performed with the internal clock. At the start of the asynchronous activation, if the internal
CLK mode is selected in the clock settings register, then the device shall begin activation based on divide ratio
defined by bit [4:2] of clock settings register. After the activation is completed, the CLK output will switch to
Internal CLK mode. When switching to/from a CLK div mode from/to CLK 0 mode or CLK 1 mode, the device
waits for the input clock (CLKIN1 or CLKIN2) phase to match the static level it will switch to/from and then makes
the transition to ensure that no partial pulses or glitches are seen on the output clock. Similarly, when switching
from one division ratio to another the change happens on the rising clock edges to ensure no glitch on the
output. Figure 15 shows how the change in divide ratio is seen on the CLK pin.
CLKINx/2
CLKINx/4
Output clock frequency transition when changing clock divide ratio
Figure 15. CLK Divide Ratio Change on Card CLK Output
When switching from CLK divide mode to the Internal CLK mode, the device waits for the edges of the internal
and external clock to line up (fall within ~10 ns of each other) and makes the switch on that edge. If the external
clock is close to an exact harmonic of 1.2 MHz, there could be a situation where the rising edges of the two
clocks take very long (milliseconds or seconds) to line up and this would mean the frequency switch at the output
would happen long after the I2C command to make the switch is issued. The CLKSW bit (bit [3]) in the card
interface status register (Reg 0x01 for user card, Reg 0x11 for SAM1, Reg 0x21 for SAM2, Reg 0x31for SAM3)
is set when the internal clock frequency is seen on the CLK pin.
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Internal
Clock
External
Clock
Clock
Output
Figure 16. Output CLK Frequency Transition When Switching From External Clock to Internal Clock
In CLK divide mode, when CLKIN/2, CLKIN/4 or CLKIN/8 division ratios are used, the output duty cycle is not
affected by the duty cycle of the input clock on CLKIN. When the CLKIN/1 and CLKIN/5 division ratios are used,
the output clock duty cycle is a function of the CLKIN1/CLKIN2 duty cycle. For CLKIN/1 the output duty cycle will
be equal to the input duty cycle. For CLKIN/5 the output CLK duty cycle is given by (n+2) / 5, where n is the duty
cycle of the input clk; for example, if the input clk has a 40% duty cycle (n = 0.4) the CLKIN/5 output will have a
(0.4+2) / 5 = 0.48 or 48% duty cycle. In addition to asynchronous mode, the user card interface can also operate
in synchronous mode (see Synchronous Type 1 Operating Mode and Synchronous Type 2 Operating
Mode).When in synchronous mode the user card CLK pin output is controlled by CLK_ENABLE_SYNC (bit [2],
Reg 0x09) in addition to the clock settings register. Figure 17 shows a simplified logical representation of the
user card clock muxing circuit.
User card Clock
settings register
0
1
CLKIN1/8
CLKIN1
CLKIN1/5
CLK
divider CLKIN1/4
circuit
Async
Sync
CLK_UC
CLKIN1/2
CLKIN1/1
User card Clock
settings register
Bit [6:5]
Internal
Oscillator
Sync mode/
Async Mode
0
1
[1:x]
[0:x]
0
1
CLK_SYNC_ENABLE
Figure 17. Clock Muxing Logic in Synchronous Mode
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Unlike all the other bits that control the CLK, the CLK_ENABLE_SYNC can cause the CLK state to transition
instantly. This means that when switching from a static level to a toggling CLK (or vice-versa), there can be
partial pulses (glitches) on the CLK output when CLK_ENABLE_SYNC is switched. In sync mode, the CLK
output can be switched directly from one static level to another, by using the CLK settings register (when
CLK_SYNC_ENABLE = 0).
Table 9. Card CLK Truth Table in Synchronous Mode
CARD CLOCK SETTINGS REGISTER
CLK_ENABLE_SYNC
CARD CLK OUTPUT
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
0
0
1
X
X
X
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
CLKIN1
8.4.7.2 CLK Rise Time and Fall Time Control
The clock slew rate setting register (Reg 0x08 for user card and Reg 0x18 for SAM) is used to control the rise
and fall time of the CLK pin. Table 10 shows the rise and fall time corresponding to each register setting. The
EMV4.3 specification, has strict restrictions on signal perturbations (overshoot and undershoot during transition).
Controlling the rise time and fall time of the CLK signals can help to meet these requirements.
Table 10. CLK Rise and Fall Time Settings
CLOCK SLEW RATE SETTINGS
REGISTER
TYPICAL RISE TIME and FALL
RATE
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
6
7
9
11
13
14
15
16
17
18
19
20
21
22
23
25
8.4.7.3 Current Limiting On CLK Pin
The card CLK pins have a current limiting feature that prevents excess current from being drawn on them. When
an external load tries to draw a current higher than the limit, the device responds by adjusting the VOH or VOL to
limit the current. The device does not deactivate the card interface when over current limit of the CLK pins are
reached.
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8.4.8 RST Operation
The RST pin operation depends on the mode in which the card interface has been activated. For user card
interface and all the SAM card interfaces, in asynchronous mode (see Asynchronous Operating Mode) the RST
pin status is automatically controlled by the TCA5013 internal state machine.
In synchronous mode (Synchronous Type 1 Operating Mode and Synchronous Type 2 Operating Mode) the RST
pin status is controlled by the TCA5013 internal state machine, until the activation sequence is complete. After
activation is complete, the RST pin status is controlled by RST bit (bit [3]) in the user card synchronous mode
settings register (Reg 0x09). This operation is described in further detail in Synchronous Type 1 Operating Mode
and Synchronous Type 2 Operating Mode.
8.4.8.1 Current Limiting On RST
The card RST pins have a current limiting feature that prevents excess current from being drawn on them. When
an external load tries to draw a current higher than the limit, the device responds by adjusting the VOH or VOL to
limit the current. The device does not deactivate the card interface when over current limit of the RST pins are
reached.
8.4.9 Interrupt Operation
The INT pin is an open drain active low output pin that needs to be pulled up to VDDI with an external pull-up
resistor. The pull-up resistor shall be sized such that the rise time of the INT pin is < 100 µs. This is important
since slower rise time could cause POR Interrupt to not be detected by the processor during TCA5013 startup.
Generally speaking faster rise times on the INT line will reduce the chances of missing interrupts. There various
interrupt events in the TCA5013 that can cause the INT pin to be asserted low. These interrupt events are
described in the below sections.
8.4.9.1 Card Insertion And Removal
When card insertion or removal is detected on the user card interface (see User Card Insertion / Removal
Detection) the INT_UC bit (bit[7]) of interrupt status register (Reg 0x41) and the PRESL_UC bit (bit[2]) of User
card interface status register (Reg 0x00) are both set to 1 and the INT pin is asserted low. INT_UC is cleared
and the INT pin is released when the interrupt status register is read. PRESL_UC is cleared only when the user
card interface status register is read.
8.4.9.2 Over Current Fault
When the current drawn on the VCC pin of any of the card interfaces exceeds the over current limit (see
Electrical Characteristics—Fault Condition Detection) the PROT bit (bit[4]) of the card interface status register
(Reg 0x00 for user card, Reg 0x10 for SAM1, Reg 0x20 for SAM2 and Reg 0x30 for SAM3) is set. The interrupt
bit corresponding to the card interface in the interrupt status register (Reg 0x41) is also set and the INT pin is
asserted low. The interrupt bit is cleared and the INT pin is released, when the interrupt status register is read.
The PROT bit is cleared only when the corresponding card interface status register is read.
8.4.9.3 Supervisor Fault
When the voltage on the VDD pin falls below the VDDTH the INT_SUPL bit (bit[2] of Reg 0x41) and The
STAT_SUPL bit (bit[1], Reg 0x10) are both set to 1 and the INT pin is asserted low. The INT_SUPL bit is cleared
and the INT pin is released when the interrupt status register is read. The STAT_SUPL bit clears when the fault
condition goes away, that is, VDD > VDDTH
8.4.9.4 Over Temperature Fault
When the die temperature exceeds a safe operating temperature (typ. 125°C) INT_OTP bit (bit[3], Reg 0x41) and
The STAT_OTP bit (bit[2], Reg 0x10) are both set to 1 and the INT pin is asserted low. The INT_OTP bit is
cleared and the INT pin is released when the interrupt status register is read. The STAT_OTP clears when the
fault condition goes away.
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8.4.9.5 EARLY Fault
In Asynchronous Operating Mode when the ATR response from the smartcard is received before the ‘ATR valid
window’ (see Figure 6) the EARLY bit (bit [6]) of card interface status register (Reg 0x00 for user card, Reg 0x10
for SAM1, Reg 0x20 for SAM2 and Reg 0x30 for SAM3) is set and the INT pin is asserted low. The interrupt bit
corresponding to the card interface in the interrupt status register (Reg 0x41) is also set. The interrupt bit is
cleared and the INT pin is released, when the interrupt status register is read. The EARLY bit is cleared only
when the corresponding card interface status register is read.
8.4.9.6 MUTE Fault
In Asynchronous Operating Mode when the ATR response from the smartcard is received after the ‘ATR valid
window’ (refer to Figure 6) the MUTE bit (bit [5]) of card interface status register (Reg 0x00 for user card, Reg
0x10 for SAM1, Reg 0x20 for SAM2 and Reg 0x30 for SAM3) is set and the INT pin is asserted low. The
interrupt bit corresponding to the card interface in the interrupt status register (Reg 0x41) is also set. The
interrupt bit is cleared and the INT pin is released, when the interrupt status register is read. The EARLY bit is
cleared only when the corresponding card interface status register is read.
8.4.9.7 Synchronous Activation Complete
In synchronous activation mode (see Synchronous Type 1 Operating Mode and Synchronous Type 2 Operating
Mode) once the activation sequence is completed, the INT_SYNC_COMPLETE bit (bit[1]) of interrupt status
register (Reg 0x41) is set and the INT pin is asserted low. The INT_SYNC_COMPLETE bit is cleared and the
INT pin is released when the interrupt status registers is read.
8.4.9.8 VCC Ramp Fault
During any activation sequence if the VCC voltage fails to ramp to programmed value within 5 ms (typ), then the
VCC_FAIL bit (bit[0]) of card interface status register (Reg 0x00 for user card, Reg 0x10 for SAM1, Reg 0x20 for
SAM2 and Reg 0x30 for SAM3) is set and the INT pin is asserted low. The interrupt bit corresponding to the card
interface in the interrupt status register (Reg 0x41) is also set. The interrupt bit is cleared and the INT pin is
released, when the interrupt status register is read. The VCC_FAIL bit is cleared only when the corresponding
card interface status register is read.
8.4.9.9 GPIO Input State Transition
When there is a state change on a GPIO pin configured as an input the INT_GPIO bit (bit[0]) of the interrupt
status register (Reg 0x41) is set and the INT pin is asserted low. The INT_GPIO bit is cleared and the INT pin is
released when the interrupt status register is read.
8.4.9.10 POR Interrupt
Whenever the device comes out of Power Off Mode or Shutdown Mode it goes through a power-on-reset (POR).
Once the device internal power up sequence is completed the INT pin is asserted low without any of the bits in
the interrupt status register (Reg 0x41) being set. Once the interrupt status register is read, the INT pin is
released. When the device is coming out of shutdown mode of power off mode, none of the device functions will
be available until the POR interrupt is asserted.
8.4.10 Power Management
The TCA5013 has power management features that enable the device to generate the appropriate card
activation voltages and monitor the device power supplies for safe and secure system operation.
8.4.10.1 Voltage Supervisor
The TCA5013 has internal voltage supervisors that monitor VDD and VDDI voltages. When VDD falls below VDDTH
all card interfaces are deactivated and the supervisor fault (see Supervisor Fault) is asserted.
The VDDI supervisor monitors the voltage on the VDDI pin. When VDDI falls below VDDITH all card interfaces are
deactivated and the device enters power off mode (see Power Off Mode). When VDDI falls below VDDITH the
supervisor fault is not asserted.
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It is possible that the supervisor fault is asserted during power up If VDDI ramps before VDD (depending on the
VDD ramp rate). If VDD is ramped and stable before VDDI is ramped, the supervisor fault will not be asserted.
Figure 18 shows the operation of voltage supervisor for various combinations of VDD and VDDI
.
VDDTH
VDDSH
VDDITH
Supervisor fault
is asserted
VDD > VDDSH
Supervisor
fault is cleared
VDD < VDDSH
VDD > VDDTH
VDDI < VDDITH
Device stays in
power down
mode
.
VDDI > VDDITH
Device is in
power down
mode
.
VDDI > VDDITH
Device comes
out of POR
.
VDD > VDDTH
VDDI < VDDITH
.
VDD < VDDSH
Device is enters
power down
mode
VDDTH>VDD > VDDSH
VDDI > VDDITH
Device comes out
of POR.
Supervisor fault is
asserted.
Supervisor fault
is cleared
VDDI > VDDITH
Device enters
power down
mode
.
.
VDD > VDDSH
VDDI > VDDITH
.
Device comes
out of POR
Figure 18. Voltage Supervisor Operation
8.4.10.2 DC-DC Boost
TCA5013 contains a DC-DC boost circuit that can step up VDD voltage to generate the required card VCC. The
boost requires an external diode (DVUP) as a high side switch. It also requires an external inductor (LVDD) in
series with the VDD pin. The normal switching frequency of the boost is ~2.4 Mhz. The boost is rated for 180
mA. This implies that the sum of the current drawn on individual card VCC pins cannot exceed 180 mA. If
exceeded it could result in the card VCC falling out of the operating range defined in Electrical
Characteristics—Power Supply and ESD.
The DC_DC bit (Reg 0x42; Bit [7]) can be used to disable the DC-DC boost circuit. The DC-DC boost should be
disabled only in systems where the supply is always guaranteed to be at least 0.25V greater than maximum card
VCC supported on that system, for example, if 5 V cards need to be supported in a system the DC-DC boost can
be disabled if VDD is guaranteed to be above 5.25 V. In systems where DC-DC is not used, the VDD pin shall be
shorted to VUP pin. The LX pin should shorted to GNDP. Shorting to GNDP is recommended to prevent
switching noise from impacting rest of system. Note that LX shall not be connected to anything other than GNDP
in order to prevent excess power loss and/or damage to the part. If DC-DC boost is disabled and the VDD is not
sufficient to activate a card interface at the voltage set by SET_VCC (Reg 0x01, Reg 0x11, Reg 0x21, Reg 0x31;
bit [7:6]), it will result in a VCC ramp fault (See VCC Ramp Fault).
The DC-DC boost is always disabled in standby mode (See Standby Mode). When a card activation command is
received, the DC-DC boost circuit is enabled by the digital core. The boost output voltage depends on voltage at
which the card needs to be activated, that is, based on SET_VCC (Reg 0x01, Reg 0x11, Reg 0x21, Reg 0x31;
bit [7:6]). For 1.8-V and 3-V card activation, the boost output voltage will be ~3.5 V. For 5-V card activations the
boost output voltage will be ~5.5 V. In a scenario where a 3 V or 1.8 V card is active and an I2C command is
received to activate another card with 5 V, the boost output voltage will go up to 5.5 V and the card LDOs (See
LDOs and Load Transient Response) on the already active card interface, will keep the card VCC within
regulation.
Under light load conditions, the DC-DC boost can enter pulse skipping mode in order to improve efficiency. In
pulse skipping mode, the switching frequency is not constant and will be much lower than the normal switching
frequency of 2.4 MHz.
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8.4.10.3 LDOs and Load Transient Response
The TCA5013 has an internal LDO that generates a stable supply for the internal circuits. The input to the
internal LDO is VDD. The output of the internal LDO is connected to the LDOCAP pin. A 1 uF decoupling
capacitor shall be connected to the LDOCAP pin to ensure proper device operation. The internal LDO voltage is
typically 2.65 V but can be lower if VDD is not sufficient.
In addition to the internal LDO, the TCA5013 has a dedicated LDO per card interface to generate the VCC for that
card interface (here on forth, these LDOs are referred to as card LDOs). The card LDOs provide the power
supply for smartcard operation. During the normal operation of the smartcard, the LDO output is subject to load
transients. The EMV4.3 standard defines a load transient envelope shown in Figure 19. The card LDOs are able
to handle these transients, while keeping VCC within limits defined in Electrical Characteristics—Card VCC. An
external 200 nF capacitor shall be connected to their card VCC pins (VCCUC, VCCCS1, VCCS2, VCCS3) to
ensure proper load transient response by the card LDOs.
5V
3V
1.8V
Figure 19. Load Transients defined by EMV4.3
The card LDOs are enabled only when the card interface is activated (see Active Mode). The output voltage is
determined by the card interface settings registers (Reg 0x01, Reg 0x11, Reg 0x21, Reg 0x31). At the start of
the activation sequence, the card LDO is enabled and starts to ramp to the voltage defined in the corresponding
card interface settings register. Once the LDO has been enabled, any changes to the card interface settings
registers will not have any effect on the LDO output voltage. The card also LDOs also have short circuit
protection. When the current drawn exceeds ~150 mA (typ.) the LDO automatically shuts down and the card
interface is deactivated (see Deactivation Sequence).
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8.5 Programming
8.5.1 I2C Interface Operation
The device has a standard bidirectional I2C that is used by the microcontroller to access the device Register
Maps that is used to configure the device and read the status of various fault flags in the device. The interface
consists of the serial clock (SCL) and serial data (SDA) lines and is capable of MHz operation. Both SDA and
SCL must be connected to VDDI through a pull-up resistor. The size of the pull-up resistor is determined by the
amount of capacitance on the I2C lines (for further details refer to I2C standard specification).
I2C communication with this device is initiated by a master (microcontroller) sending a START condition, a high-
to-low transition on the SDA input/output, while the SCL input is high. Only one data bit is transferred during each
clock pulse. A STOP condition is a low-to-high transition on the SDA input/output while the SCL input is high. A
STOP condition shall be sent by the master to indicate to the slave that a particular transaction has been
completed. The data on the SDA line must remain stable during the high phase of the clock period, as changes
in the data line when SCL is high are interpreted as control commands (START or STOP).
Figure 20 shows the definition of an I2C START condition and Figure 21 shows timing of a bit transfer on the I2C
bus. I2C
Figure 20. Definition of Start and Stop Conditions
Figure 21. Bit Transfer
Any number of data bytes can be transferred from the master to slave (TCA5013) between the START and
STOP conditions. Each byte of eight bits is followed by one ACK bit. The master must release the SDA line
before the slave can send an ACK bit. To send an ACK bit the slave pulls down the SDA line during the low
phase of ACK-related clock period, so that the SDA line is stable low during the high phase of the ACK-related
clock period. When the slave is addressed, it generates an ACK after each byte is received. The master is not
required to generate an ACK after each byte that it receives from the slave transmitter
Figure 22 shows the timing diagram for generation of the ACK bit on the I2C interface of the TCA5013
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Programming (continued)
Figure 22. Acknowledgment on I2C Bus
8.5.1.1 I2C Read and Write Procedures
Following the successful acknowledgment of the I2C address byte, the bus master shall send one register
address byte indicating the address of the register on which the read or write operation needs to be performed.
This register address is stored in an internal register and used by the device for subsequent read/write to the
device. After the device address is acknowledged by the slave, all register addresses will be acknowledged even
if an actual register is not defined for that address
The TCA5013 supports an auto increment feature by which multiple bytes can be written to consecutive registers
without requiring the master to send the device address and register address for each data byte. Auto increment
is enabled by setting the MSB of the register address to a 1 (see Figure 23). If auto increment is used to write
the entire register map, the gaps in the register address map need to be written with dummy bytes. If auto
increment is used to read the entire register map then data read from gaps in the register map will be 8’hFF
S
DEVICE ADDRESS
A
REGISTER ADDRESS
A
W
AI
A
A
P
REGISTER DATA
REGISTER DATA*
2nd and subsequent bytes of Register data are written to next register if Auto increment is enabled (AI=1)
2nd and subsequent bytes of register data are ignored if auto increment is disabled (AI=0).
SDA line is controlled by
Master
SDA line is controlled by
Slave
Figure 23. I2C Write Procedure
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Programming (continued)
S
DEVICE ADDRESS
A
AI
REGISTER ADDRESS
A
P
W
S
A
A
A
REGISTER DATA
REGISTER DATA*
R
DEVICE ADDRESS
2nd and subsequent bytes of Register data are read from the next register if Auto increment is enabled (AI=1)
2nd and subsequent bytes of register data are ignored if auto increment is disabled (AI=0).
SDA line is controlled by
Master
SDA line is controlled by
Slave
Figure 24. I2C Read Procedure
S
DEVICE ADDRESS
A
AI
REGISTER ADDRESS
A
W
Sr
A
A
A
REGISTER DATA
REGISTER DATA*
R
DEVICE ADDRESS
2nd and subsequent bytes of Register data are read from the next register if Auto increment is enabled (AI=1)
2nd and subsequent bytes of register data are ignored if auto increment is disabled (AI=0).
SDA line is controlled by
Master
SDA line is controlled by
Slave
Figure 25. I2C Read Procedure with Repeated Start
8.5.1.2 I2C Address Configuration
The I2C address of the TCA5013 can be configured using the A0. The A0 pin shall be connected to VDDI or
GND to select one of the addresses, as shown in Table 11. The last bit in the address byte defines the operation
(read or write)
Table 11. TCA5013 I2C address selection
SLAVE ADDRESS
A0
I2C BUS SLAVE ADDRESS
B7
0
B6
1
B5
1
B4
1
B3
0
B2
0
B1
1
B0
GND
VDDI
W/R
W/R
Write - 72(h), Read – 73(h)
Write - 7C(h), Read – 7D(h)
0
1
1
1
1
1
0
40
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8.6 Register Maps
Memory Map
Address
(Hex)
Register Description
Type
Reset (Hex)
Reset
(Binary)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ACTIVE_UC EARLY_UC
SET_VCC_UC
MUTE_UC
IO_EN_UC
CLK1_UC
PROT_UC CLKSW_UC PRESL_UC
PRES_UC
VCC_FAIL_
UC
00
01
02
03
04
05
06
User Card Interface Status
User Card Interface Settings
User Card Clock Settings
R
00
60
0C
AA
00
A4
74
0000 0000
0110 0000
0000 1100
1010 1010
0000 0000
1010 0100
0111 0100
WARM_UC CARD_DET
ECT_UC
START_AS
YNC_UC
R/W
R/W
R/W
R/W
R/W
R/W
INTERN_CL
K_UC
CLK0_UC
CLK_DIV_UC
Asynchronous Mode ATR EARLY
Counter MSB for User Card
EARLY_COUNT_HI_UC
Asynchronous Mode ATR EARLY
Counter LSB for User Card
EARLY_COUNT_LO_UC
Asynchronous Mode ATR MUTE
Counter MSB for User Card
MUTE_COUNT_HI_UC
Asynchronous Mode ATR MUTE
Counter LSB for User Card
MUTE_COUNT_LO_UC
IO_TF_UC
07
08
User Card IO Slew Rate Settings
User Card Clock Slew Rate Settings
R/W
R/W
80
A0
1000 0000
1010 0000
IO_TR_UC
CLK_SR_UC
CARD_TYP ACTIVATIO
N_TYPE
CLK_ENAB
LE_SYNC
START_SY
NC
09
User Card Synchronous Mode Settings
R/W
76
0111 0110
C4
C8
RST
BYTE1_UC
EDGE
E
0A
0B
0C
0D
Synchronous Mode ATR Byte 1
Synchronous Mode ATR Byte 2
Synchronous Mode ATR Byte 3
Synchronous Mode ATR Byte 4
R
R
R
R
00
00
00
00
0000 0000
0000 0000
0000 0000
0000 0000
BYTE2_UC
BYTE3_UC
BYTE4_UC
ACTIVE_SA EARLY_SA MUTE_SAM PROT_SAM CLKSW_SA
STAT_SUP VCC_FAIL_
10
11
12
13
14
15
16
SAM1 Interface Status
SAM1 Interface Settings
SAM1 Clock Settings
R
00
40
0C
AA
00
A4
74
0000 0000
0100 0000
0000 1100
1010 1010
0000 0000
1010 0100
0111 0100
STAT_OTP
M1
M1
1
1
M1
L
SAM1
IO_EN_SA
M1
WARM_SA
M1
START_AS
YNC_SAM1
R/W
R/W
R/W
R/W
R/W
R/W
SET_VCC_SAM1
INTERN_CL CLK0_SAM CLK1_SAM
K_SAM1
CLK_DIV_SAM1
1
1
Asynchronous Mode ATR EARLY
Counter MSB for SAM1
EARLY_COUNT_HI_SAM1
Asynchronous Mode ATR EARLY
Counter LSB for SAM1
EARLY_COUNT_LO_SAM
1
Asynchronous Mode ATR MUTE
Counter MSB for SAM1
MUTE_COUNT_HI_SAM1
Asynchronous Mode ATR MUTE
Counter LSB for SAM1
MUTE_COUNT_LO_SAM1
IO_TF_SAM
17
18
SAM IO Slew Rate Settings
R/W
R/W
80
A0
1000 0000
1010 0000
IO_TR_SAM
SAM Clock Slew Rate Settings
CLK_SR_SAM
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Register Maps (continued)
Memory Map (continued)
Address
(Hex)
Register Description
Type
Reset (Hex)
Reset
(Binary)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ACTIVE_SA EARLY_SA MUTE_SAM PROT_SAM CLKSW_SA
VCC_FAIL_
SAM2
20
21
22
23
24
25
26
30
31
32
33
34
35
SAM2 Interface Status
SAM2 Interface Settings
SAM2 Clock Settings
R
00
40
0C
AA
00
A4
74
00
40
0C
AA
00
A4
0000 0000
0100 0000
0000 1100
1010 1010
0000 0000
1010 0100
0111 0100
0000 0000
0100 0000
0000 1100
1010 1010
0000 0000
1010 0100
M2
M2
2
2
M2
IO_EN_SA
M2
WARM_SA
M2
START_AS
YNC_SAM2
R/W
R/W
R/W
R/W
R/W
R/W
R
SET_VCC_SAM2
INTERN_CL CLK0_SAM CLK1_SAM
K_SAM2
CLK_DIV_SAM2
2
2
Asynchronous Mode ATR EARLY
Counter MSB for SAM2
EARLY_COUNT_HI_SAM2
Asynchronous Mode ATR EARLY
Counter LSB for SAM2
EARLY_COUNT_LO_SAM
2
Asynchronous Mode ATR MUTE
Counter MSB for SAM2
MUTE_COUNT_HI_SAM2
MUTE_COUNT_LO_SAM2
Asynchronous Mode ATR MUTE
Counter LSB for SAM2
ACTIVE_SA EARLY_SA MUTE_SAM PROT_SAM CLKSW_SA
VCC_FAIL_
SAM3
SAM3 Interface Status
SAM3 Interface Settings
SAM3 Clock Settings
M3
M3
3
3
M3
IO_EN_SA
M3
WARM_SA
M3
START_AS
YNC_SAM3
R/W
R/W
R/W
R/W
R/W
SET_VCC_SAM3
INTERN_CL CLK0_SAM CLK1_SAM
CLK_DIV_SAM3
K_SAM3
3
3
Asynchronous Mode ATR EARLY
Counter MSB for SAM3
EARLY_COUNT_HI_SAM3
Asynchronous Mode ATR EARLY
Counter LSB for SAM3
EARLY_COUNT_LO_SAM
3
Asynchronous Mode ATR MUTE
Counter MSB for SAM3
MUTE_COUNT_HI_SAM3
Asynchronous Mode ATR MUTE
Counter LSB for SAM3
36
40
41
42
43
R/W
R
74
00
00
80
xF
0111 0100
0000 0000
0000 0000
1000 0000
xxxx 1111
MUTE_COUNT_LO_SAM3
PRODUCT_VER
Product Version
Interrupt Status Register
Device Settings
INT_SYNC_
COMPLETE
R
INT_UC
DC_DC
INT_SAM1
INT_SAM2
GPIO4
INT_SAM3
GPIO3
INT_OTP
GPIO2
INT_SUPL
GPIO1
INT_GPIO
R/W
R/W
GPIO4_INP GPIO3_INP GPIO2_INP GPIO1_INP GPIO4_OU GPIO3_OU GPIO2_OU GPIO1_OU
GPIO Settings
UT
UT
UT
UT
TPUT
TPUT
TPUT
TPUT
SYNC_COM
PLETE_MA OTP_MASK
SK
EARLY_UC MUTE_UC_ PROT_UC_
_ MASK MASK MASK
SUPL_MAS GPIO_INT_ PRESL_INT
MASK _ MASK
44
User Card Interrupt Mask Register
R/W
00
0000 0000
K
SAM1 and SAM2 Interrupt Mask
Register
EARLY_SA MUTE_SAM PROT_SAM EARLY_SA MUTE_SAM PROT_SAM VCC_FAIL_ VCC_FAIL_
M1_MASK 1_MASK 1_MASK M2_MASK 2_MASK 2 _MASK SAM_MASK UC_ MASK
45
46
R/W
R/W
00
00
0000 0000
0000 0000
SAM3 and GPIO Interrupt Mask
Register
EARLY_SA MUTE_SAM PROT_SAM GPIO4_INT GPIO3_INT GPIO2_INT GPIO1_INT
M3_MASK 3_MASK 3_MASK _MASK _MASK _MASK _ MASK
42
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Table 12.
REGISTER
ADDRESS
DESCRIPTION
FIELD NAME
BIT
R/W
DEFAULT
0x00
User Card Interface Status
1: Card interface is active (VCC is ramped and stable)
0: Card interface is inactive
0x00
ACTIVE_UC
EARLY_UC
7
6
R
R
1'b0
1'b0
1: Indicates card ATR was received before the ATR valid window.
INT_UC bit is set in interrupt register.
Bit is cleared when the register is read
0x00
0x00
0x00
0x00
1: Indicates card ATR was not received within the ATR valid window.
INT_UC bit is set in interrupt register. Bit is cleared when the register is
read.
MUTE_UC
PROT_UC
CLKSW_UC
5
4
3
R
R
R
1'b0
1'b0
1'b0
1: Indicates over current condition on the card interface. INT_UC bit is
set in interrupt register.
Bit clears when the register is read
1: Indicates the card interface is in internal CLK mode i.e frequency on
CLK pin is ~1.2 Mhz
0: Indicates the card interface is not in internal clock mode.
1: indicates the card has been inserted or extracted. INT_UC bit is set in
interrupt register.
Bit is cleared when the register is read
0x00
0x00
0x00
PRESL_UC
PRES_UC
2
1
0
R
R
R
1'b0
1'b0
1’b0
1: indicates a card is present
0: indicates a card is not present
1: indicates VCC ramp fault on card interface. INT_UC bit is set in
interrupt register.
VCC_FAIL_UC
Bit is cleared when register is read
Table 13.
REGISTER
ADDRESS
DESCRIPTION
User Card Interface Settings
FIELD NAME
BIT
R/W
DEFAULT
0x01
00 : set VCC to 1.8 V
01 : set VCC to 1.8 V
10 : set VCC to 3 V
11 : set VCC to 5 V
0x01
SET_VCC_UC
[7:6]
5
R/W
R/W
2'b01
1'b1
1: IOMC1 is connected IOUC
0: IOMC1 is disconnected from IOUC
0x01
0x01
0x01
IO_EN_UC
1: Warm reset sequence is started on user card interface
Bit is clears when warm reset sequence starts.
Bit is ignored if card interface is in synchronous type 1
operating mode, synchronous type 2 operating mode or
manual operating mode.
WARM_UC
3
2
R/W
R/W
1'b0
1'b0
1 :Low to high transition on PRES pin indicates card insertion
0 : High to low transition on PRES pin indicates card insertion
CARD_DETECT_UC
1: Starts asynchronous activation sequence
0: Starts deactivation sequence
Bit clears when automatic deactivation occurs
Bit is ignored if card interface is in synchronous type 1
operating mode, synchronous type 2 operating mode or
manual operating mode.
0x01
START_ASYNC_UC
0
R/W
1'b0
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DEFAULT
Table 14.
REGISTER
DESCRIPTION
ADDRESS
FIELD NAME
BIT
R/W
0x02
User Card Clock Settings
In asynchronous operating mode
(START_ASYNC=1)
1: CLKUC is set to ~1.2 MHz
0: CLKUC is set by Bit[6] or Bit[5] or Bit[4:2]
In synchronous operating mode
(START_SYNC=1)
0x02
INTERN_CLK_UC
7
R/W
1'b0
1'b0
Bit is ignored in Sync mode
In asynchronous operating mode
(START_ASYNC=1)
1: CLKUC is set to 0
0: CLKUC is set by Bit[5] or Bit[4:2]
In synchronous operating mode
(START_SYNC=1)
0x02
CLK0_UC
6
R/W
1: CLKUC is set to 0
0: CLKUC is set by Bit5.
In asynchronous operating mode
(START_ASYNC=1)
1: CLKUC is set to 1
0: CLKUC is set by Bit[4:2]
In synchronous operating mode
(START_SYNC=1)
0x02
CLK1_UC
5
R/W
1'b0
Usable only is CLK_ENABLE_SYNC=0
1: CLKUC is set to 1
0: CLKUC is set to 1
In asynchronous operating mode
(START_ASYNC=1)
000: CLKUC frequency = CLKIN1
001: CLKUC frequency = CLKIN1/2.
010: CLKUC frequency = CLKIN1/4.
011: CLKUC frequency = CLKIN1/5.
100: CLKUC frequency = CLKIN1/8.
101: CLKUC frequency = CLKIN1/8.
110: CLKUC frequency = CLKIN1/8.
111: CLKUC frequency = CLKIN1/8.
In synchronous operating mode
(START_SYNC=1)
0x02
CLK_DIV_UC
[4:2]
R/W
3'b011
Usable only is CLK_ENABLE_SYNC=1
[111:000] : CLKUC = CLKIN1
Asynchronous Mode ATR EARLY Counter MSB for
User Card
0x03
0x03
0x04
0x04
0x05
MSB (8-bits) of programmable 10-bit clock counter value. EARLY_COUNT_HI_UC
[7:0]
[7:6]
R/W
R/W
8'b10101010
2'b00
Asynchronous Mode ATR EARLY Counter LSB for
User Card
LSB (2-bits) of programmable 10-bit clock counter value. EARLY_COUNT_LO_UC
Asynchronous Mode ATR MUTE Counter MSB for
User Card
MSB (8-bits) of programmable 16-Bit clock counter
0x05
MUTE_COUNT_HI_UC
value.
[7:0]
[7:0]
R/W
R/W
8'b10100100
8'b01110100
Asynchronous Mode ATR MUTE Counter LSB for
User Card
0x06
0x06
0x07
0x07
0x07
0x08
LSB (8-bits) of programmable 16-Bit clock counter value. MUTE_COUNT_LO_UC
User Card IO Slew Rate Settings
3 Bit value defining the rise time of IOUC
2 Bit value defining the fall time of IOUC
User Card Clock Slew Rate Settings
IO_TR_UC
IO_TF_UC
[7:5]
[4:3]
R/W
R/W
3'b100
2'b00
4 Bit value defining the rise time and fall time of the
CLKUC
0x08
CLK_SR_UC
[7:4]
R/W
4'b1010
44
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Table 15.
REGISTER
ADDRESS
DEFAUL
DESCRIPTION
FIELD NAME
BIT
R/W
T
0x09
User Card Synchronous Mode Settings
0: Synchronous Type 1 card activation is selected
1: Synchronous Type 2 card activation is selected
0x09
CARD_TYPE
7
6
R/W
R/W
1'b0
1'b1
1: Automatic activation per bit[7] is selected
0: Manual operating mode is selected
0x09
0x09
ACTIVATION_TYPE
C4
0 :Llow level is driven on C4 or C4 is being driven low externally
1 : C4 is pulled up high by internal pull-up Bit has no effect if
card interface is not active
5
4
R/W
R/W
1'b1
1'b1
0 : Low level is driven on C8 or C8 is being driven low externally
1 : C8 is pulled up high by internal pull-up Bit has no effect if
card interface is not active
0x09
0x09
C8
0 : Low level is driven on RSTUC
1 : High level is driven on RSTUC
Bit has no effect when card interface is not active.
Bit has no effect if card interface is activated in asynchronous
operating mode
RST
3
2
R/W
R/W
1'b0
1'b1
0 : CLKUC is driven low or high based on the clock settings
register (Reg 0x02, Bit [6:5])
1 : CLK output is controlled by CLKIN1
Bit has no effect when card interface is not active.
Bit has no effect if card interface is activated in asynchronous
operating mode
0x09
CLK_ENABLE_SYNC
1 : IO line is sampled on rising edge during synchronous type 1
activation sequence
0 : IO line sampled on falling edge during synchronous type 1
activation sequence
Bit has no effect when card interface is not active.
Bit has no effect if card interface is activated in asynchronous
operating mode
0x09
0x09
EDGE
1
0
R/W
R/W
1'b1
1'b0
1 : Start card interface activation based on bit[7:6]
0: Start deactivation sequence bit clears when automatic
deactivation occurs.
START_SYNC
REGISTER
ADDRESS
DESCRIPTION
FIELD NAME
BIT
R/W
DEFAULT
0x0A
0x0A
0x0B
0x0B
0x0C
0x0C
0x0D
0x0D
Synchronous Mode ATR Byte1
Bit 7 to Bit 0 of ATR response
Synchronous Mode ATR Byte2
Bit 15 to Bit 8 of ATR response
Synchronous Mode ATR Byte3
Bit 23 to Bit 16 of ATR response
Synchronous Mode ATR Byte4
Bit 31 to Bit 24 of ATR response
BYTE1_UC
BYTE2_UC
BYTE3_UC
BYTE4_UC
[7:0]
[7:0]
[7:0]
[7:0]
R
R
R
R
8'b00000000
8'b00000000
8'b00000000
8'b00000000
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DEFAULT
Table 16.
REGISTER
DESCRIPTION
ADDRESS
FIELD NAME
BIT
R/W
0x10
SAM1 Interface Status
1: Card interface is active (VCC is ramped and stable)
0: Card interface is inactive
0x10
ACTIVE_SAM1
7
6
R
R
1'b0
1'b0
1: Indicates card ATR was received before the ATR valid
window. INT_SAM1 bit is set in interrupt register.
Bit is cleared when the register is read
0x10
0x10
0x10
0x10
EARLY_SAM1
1: Indicates card ATR was not received within the ATR valid
window. INT_SAM1 bit is set in interrupt register. Bit is cleared MUTE_SAM1
when the register is read.
5
4
3
R
R
R
1'b0
1'b0
1'b0
1: Indicates over current condition on the card interface.
INT_SAM1 bit is set in interrupt register. Bit clears when the
register is read
PROT_UC_SAM1
CLKSW_SAM1
1: Indicates the card interface is in internal CLK mode i.e
frequency on CLK pin is ~1.2 Mhz
0: Indicates the card interface is not in internal clock mode.
1: Indicates that an over temperature fault condition exists
0: Over temperature fault doesn’t exist
0x10
0x10
STAT_OTP
2
1
R
R
1'b0
1'b0
1: Indicates a supervisor fault condition exists.
0: Supervisor fault condition doesn’t exist.
STAT_SUPL
1: Indicates VCC ramp fault on card interface.
INT_SAM1 bit is set in interrupt register.
Bit is cleared when register is read
0x10
VCC_FAIL_SAM1
0
R
1’b0
0x11
SAM1 Interface Settings
00 : Set VCC to 1.8 V
01 : Set VCC to 1.8 V
10 : Set VCC to 3 V
11 : Set VCC to 5 V
0x11
SET_VCC_SAM1
[7:6]
R/W
2'b01
1: IOMC2 is connected to IOS1
0: IOMC2 is disconnected from IOS1
0x11
0x11
IO_EN_SAM1
WARM_SAM1
5
3
R/W
R/W
1'b0
1'b0
1: Warm reset sequence is started on SAM1
Bit is clears when warm reset sequence starts.
1: Starts activation sequence
0x11
START_ASYNC_SAM1
0
R/W
1'b0
0: Starts deactivation sequence
Bit clears when automatic deactivation occurs
46
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REGISTER
ADDRESS
DESCRIPTION
SAM1 Clock Settings
FIELD NAME
BIT
R/W
DEFAULT
0x12
1 : Card CLK is set to ~1.2 MHz
0 : Card CLK is set by Bit[6], Bit[5] or Bit[4:2]
0x12
INTERN_CLK_SAM1
CLK0_SAM1
7
6
5
R/W
R/W
R/W
1'b0
1'b0
1'b0
1 : Card CLK is set to 0
0 : Card CLK is set by Bit[5] or Bit[4:2]
0x12
0x12
1 : Card CLK is set to 1
0 : Card CLK is set by Bit[4:2]
CLK1_SAM1
000 : CLKS1 frequency = CLKIN2
001 : CLKS1 frequency = CLKIN2/2
010 : CLKS1 frequency = CLKIN2/4
011 : CLKS1 frequency = CLKIN2/5
100: CLKS1 frequency = CLKIN2/8
101: CLKS1 frequency = CLKIN2/8
110: CLKS1 frequency = CLKIN2/8
111: CLKS1 frequency = CLKIN2/8
0x12
CLK_DIV_SAM1
[4:2]
[7:0]
R/W
R/W
3'b011
Asynchronous Mode ATR EARLY Counter MSB for
SAM1
0x13
0x13
0x14
MSB (8-bits) of programmable 10-bit clock counter value
EARLY_COUNT_HI_SAM1
8'b10101010
Asynchronous Mode ATR EARLY Counter LSB for
SAM1
EARLY_COUNT_LO_SAM
1
0x14
LSB (2-bits) of programmable 10-bit clock counter value
[7:6]
R/W
2'b00
Table 17.
REGISTER
ADDRESS
DESCRIPTION
FIELD NAME
BIT
R/W
DEFAULT
0x15
0x15
0x16
0x16
0x17
Asynchronous Mode ATR MUTE counter MSB for SAM1
MSB (8-bits) of programmable 16-bit clock counter value
Asynchronous Mode ATR MUTE counter LSB for SAM1
MSB (8-bits) of programmable 16-bit clock counter value
SAM IO Slew Rate Settings
MUTE_COUNT_HI_SAM1
MUTE_COUNT_LO_SAM1
[7:0]
[7:0]
R/W
R/W
8'b10100100
8'b01110100
3-Bit value defining the rise time of IO pin for all SAM
interfaces
0x17
IO_TR_SAM
IO_TF_SAM
[7:5]
[4:3]
R/W
R/W
3'b100
2'b00
2-Bit value defining the rise time of IO pin for all SAM
interfaces
0x17
0x18
0x18
SAM Clock Slew Rate Settings
4-Bit value defining the rise time and fall time of CLK for all
SAM interfaces
CLK_SR_SAM1
[7:4]
R/W
4'b1010
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DEFAU
Table 18.
REGISTER
DESCRIPTION
ADDRESS
FIELD NAME
BIT
R/W
LT
0x20
SAM2 Interface Status
1: Card interface is active (VCC is ramped and stable)
0: Card interface is inactive
0x20
ACTIVE_SAM2
7
6
R
R
1'b0
1'b0
1: Indicates card ATR was received before the ATR valid window.
INT_SAM2 bit is set in interrupt register.
Bit is cleared when the register is read
0x20
0x20
0x20
0x20
EARLY_SAM2
MUTE_SAM2
1: Indicates card ATR was not received within the ATR valid
window. INT_SAM2 bit is set in interrupt register.
Bit is cleared when the register is read.
5
4
3
0
R
R
R
R
1'b0
1'b0
1'b0
1’b0
1: Indicates over current condition on the card interface. INT_SAM2
bit is set in interrupt register.
Bit clears when the register is read
PROT_UC_SAM2
CLKSW_SAM2
VCC_FAIL_SAM2
1: Indicates the card interface is in internal CLK mode i.e frequency
on CLK pin is ~1.2Mhz
0: Indicates the card interface is not in internal clock mode.
1: indicates VCC ramp fault on card interface. INT_SAM2 bit is set
in interrupt register.
0x20
Bit is cleared when register is read
0x21
SAM2 Interface Settings
00 : set VCC to 1.8 V
01 : set VCC to 1.8 V
10 : set VCC to 3 V
11 : set VCC to 5 V
0x21
SET_VCC_SAM2
[7:6]
R/W
2'b01
1: IOMC2 is connected to IOS2
0: IOMC2 is disconnected from IOS2
0x21
0x21
IO_EN_SAM2
WARM_SAM2
5
3
R/W
R/W
1'b0
1'b0
1: Warm reset sequence is started on SAM2
Bit is clears when warm reset sequence starts.
1: Starts activation sequence
0x21
START_ASYNC_SAM2
0
R/W
1'b0
0: Starts deactivation sequence
Bit clears when automatic deactivation occurs
48
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Table 19.
REGISTER
ADDRESS
DESCRIPTION
SAM2 Clock Settings
FIELD NAME
BIT
R/W
DEFAULT
0x22
1 : Card CLK is set to ~1.2MHz
0 : CLKS2 is set by Bit[6] or Bit [5] or Bit[4:2]
0x22
INTERN_CLK_SAM2
CLK0_SAM2
7
6
5
R/W
R/W
R/W
1'b0
1'b0
1'b0
1 : Card CLK is set to 0
0 : CLKS2 is set by Bit[5] or Bit[4:2]
0x22
0x22
1 : Card CLK is set to 1
0 : CLKS2 is set by Bit[4:2]
CLK1_SAM2
000 : CLKS2 frequency = CLKIN2
001 : CLKS2 frequency = CLKIN2/2
010 : CLKS2 frequency = CLKIN2/4
011 : CLKS2 frequency = CLKIN2/5
100: CLKS2 frequency = CLKIN2/8
101: CLKS2 frequency = CLKIN2/8
110: CLKS2 frequency = CLKIN2/8
111: CLKS2 frequency = CLKIN2/8
0x22
CLK_DIV_SAM2
[4:2]
R/W
3'b011
Asynchronous Mode ATR EARLY Counter MSB for
SAM2
0x23
0x23
0x24
0x24
0x25
0x25
0x26
0x26
MSB (8-bits) of programmable 10-bit clock counter
value.
EARLY_COUNT_HI_SAM2
EARLY_COUNT_LO_SAM2
MUTE_COUNT_HI_SAM2
MUTE_COUNT_LO_SAM2
[7:0]
[7:6]
[7:0]
[7:0]
R/W
R/W
R/W
R/W
8'b10101010
2'b00
Asynchronous Mode ATR EARLY Counter LSB for
SAM2
LSB (2-bits) of programmable 10-bit clock counter
value.
Asynchronous Mode ATR MUTE Counter MSB for
SAM2
MSB (8-bits) of programmable 16-bit clock counter
value.
8'b10100100
8'b01110100
Asynchronous Mode ATR MUTE Counter LSB for
SAM2
MSB (8-bits) of programmable 16-bit clock counter
value.
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DEFAULT
Table 20.
REGISTER
DESCRIPTION
ADDRESS
FIELD NAME
BIT
R/W
0x30
SAM3 Interface Status
1: Card interface is active (VCC is ramped and stable)
0: Card interface is inactive
0x30
ACTIVE_SAM3
7
6
R
R
1'b0
1'b0
1: Indicates card ATR was received before the ATR valid window.
INT_SAM3 bit is set in interrupt register.
Bit is cleared when the register is read
0x30
0x30
0x30
0x30
EARLY_SAM3
MUTE_SAM3
1: Indicates card ATR was not received within the ATR valid
window. INT_SAM3 bit is set in interrupt register.
Bit is cleared when the register is read.
5
4
3
0
R
R
R
R
1'b0
1'b0
1'b0
1’b0
1: Indicates over current condition on the card interface.
INT_SAM3 bit is set in interrupt register
Bit clears when the register is read
PROT_UC_SAM3
CLKSW_SAM3
VCC_FAIL_SAM3
1: Indicates the card interface is in internal CLK mode i.e
frequency on CLK pin is ~1.2Mhz
0: Indicates the card interface is not in internal clock mode.
1: Indicates VCC ramp fault on card interface. INT_SAM3 bit is set
in interrupt register.
0x30
Bit is cleared when register is read
0x31
SAM3 Interface Settings
00 : set VCC to 1.8 V
01 : set VCC to 1.8 V
10 : set VCC to 3V
11 : set VCC to 5V
0x31
SET_VCC_SAM3
[7:6]
R/W
2'b01
1: IOMC2 is connected to IOS3
0: IOMC2 is disconnected from IOS3
0x31
0x31
IO_EN_SAM3
WARM_SAM3
5
3
R/W
R/W
1'b0
1'b0
1: Warm reset sequence is started on SAM3
Bit is clears when warm reset sequence starts.
1: Starts activation sequence
0x31
START_ASYNC_SAM3
0
R/W
1'b0
0: Starts deactivation sequence
Bit clears when automatic deactivation occurs
50
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Table 21.
REGISTER
ADDRESS
DESCRIPTION
SAM3 Clock Settings
FIELD NAME
BIT
R/W
DEFAULT
0x32
1 : CLKS3 is set to ~1.2 Mhz
0 : CLKS3 is set by Bit[6] or Bit [5] or Bit[4:2]
0x32
INTERN_CLK_SAM3
CLK0_SAM3
7
6
5
R/W
R/W
R/W
1'b0
1'b0
1'b0
1 : CLKS3 is set to 0
0 : CLKS3 is set by Bit[5] or Bit[4:2]
0x32
0x32
1 : CLKS3 is set to 1
0 : CLKS3 is set by Bit[4:2]
CLK1_SAM3
000 : CLKS3 frequency = CLKIN2
001 : CLKS3 frequency = CLKIN2/2
010 : CLKS3 frequency = CLKIN2/4
011 : CLKS3 frequency = CLKIN2/5
100: CLKS3 frequency = CLKIN2/8
101: CLKS3 frequency = CLKIN2/8
110: CLKS3 frequency = CLKIN2/8
111: CLKS3 frequency = CLKIN2/8
0x32
CLK_DIV_SAM3
[4:2]
R/W
3'b011
Asynchronous Mode ATR EARLY Counter MSB for
SAM3
0x33
0x33
0x34
0x34
0x35
0x35
0x36
0x36
MSB (8-bits) of programmable 10-bit clock counter
value.
EARLY_COUNT_HI_SAM3
EARLY_COUNT_LO_SAM3
MUTE_COUNT_HI_SAM3
[7:0]
[7:6]
[7:0]
[7:0]
R/W
R/W
R/W
R/W
8'b10101010
2'b00
Asynchronous Mode ATR EARLY Counter LSB for
SAM3
LSB (2-bits) of programmable 10-bit clock counter
value.
Asynchronous Mode ATR MUTE Counter MSB for
SAM3
MSB (8-bits) of programmable 16-bit clock counter
value.
8'b10100100
8'b01110100
Asynchronous Mode ATR MUTE Counter LSB for
SAM3
MSB (8-bits) of programmable 16-bit clock counter
value.
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Table 22.
REGISTER
DESCRIPTION
ADDRESS
FIELD NAME
BIT
R/W
DEFAULT
0x40
0x40
0x41
Product Version
Product Version
PRODUCT_VER
[7:0]
R
8'b00000000
Interrupt Status Register
1: PROT, MUTE, EARLY, VCC_FAIL or PRESL bit set in
User card. INT pin is asserted low when this bit is set.
0 : Bit clears when Register is read
0x41
0x41
0x41
0x41
0x41
0x41
0x41
0x41
INT_UC
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1: PROT, VCC_FAIL, MUTE or EARLY bit set in SAM1. INT
is asserted low when this bit is set.
0 : Bit clears when Register is read
INT_SAM1
INT_SAM2
INT_SAM3
INT_OTP
1: PROT, VCC_FAIL, MUTE or EARLY bit set in SAM2. INT
is asserted low when this bit is set.
0 : Bit clears when Register is read
1: PROT, VCC_FAIL, MUTE or EARLY bit set in SAM3. INT
is asserted low when this bit is set.
0 : Bit clears when Register is read
1: All card interfaces deactivated due to over temperature
fault. INT is asserted low when this bit is set.
0 : Bit clears when Register is read
1: All card interfaces deactivated due to Supervisor fault. INT
is asserted low when this bit is set.
0 : Bit clears when register is read
INT_SUPL
1: Sync card activation sequence complete. INT is asserted
low when this bit is set.
0 : Bit clears when register is read
INT_SYNC_COMPLETE
INT_GPIO
1: One of the GPIO inputs has changes state. INT is asserted
low when this bit is set.
0 : Bit clears when register is read
0x42
Device Settings
1: DC-DC boost is enabled
0: DC-DC boost is disabled
0x42
DC_DC
GPIO4
GPIO3
GPIO2
GPIO1
7
5
4
3
2
R/W
R/W
R/W
R/W
R/W
1'b1
1'b0
1'b0
1'b0
1'b0
1: GPIO4 is configured as input
0: GPIO4 is configured as output
0x42
0x42
0x42
0x42
1: GPIO3 is configured as input
0: GPIO3 is configured as output
1: GPIO2 is configured as input
0: GPIO2 is configured as output
1: GPIO1 is configured as input
0: GPIO1 is configured as output
52
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Table 23.
REGISTER
ADDRESS
DESCRIPTION
FIELD NAME
BIT
R/W DEFAULT
0x43
0x43
0x43
0x43
0x43
GPIO Settings
Reflects level on GPIO4 (read only)
Reflects level on GPIO3 (read only)
Reflects level on GPIO2 (read only)
Reflects level on GPIO1 (read only)
GPIO4_INPUT
7
6
5
4
R
R
R
R
1'b0
1'b0
1'b0
1'b0
GPIO3_INPUT
GPIO2_INPUT
GPIO1_INPUT
Sets level on GPIO4 (Bit is ignored if pin is configured as
input)
0x43
0x43
0x43
GPIO4_OUTPUT
GPIO3_OUTPUT
GPIO2_OUTPUT
GPIO1_OUTPUT
3
2
1
0
R/W
R/W
R/W
R/W
1'b1
1'b1
1'b1
1'b1
Sets level on GPIO3 (Bit is ignored if pin is configured as
input)
Sets level on GPIO2 (Bit is ignored if pin is configured as
input)
Sets level on GPIO1 (Bit is ignored if pin is configured as
input)
0x43
0x44
0x44
User Card Interrupt Mask Register
1: Mask User card EARLY Interrupt
0: Unmask User card EARLY interrupt
EARLY_UC_MASK
MUTE_UC _MASK
PROT_UC_MASK
SYNC_COMPLETE_MASK
OTP_MASK
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1: Mask User Card MUTE Interrupt
0: Unmask User Card MUTE interrupt
0x44
0x44
0x44
0x44
0x44
0x44
0x44
1: Mask User Card PROT Interrupt
0: Unmask User Card PROT interrupt
1: Mask sync card activation complete Interrupt
0: Unmask sync card activation complete interrupt
1: Mask thermal shutdown Interrupt
0: Unmask thermal shutdown interrupt
1: Mask supervisor fault Interrupt
0: Unmask supervisor fault interrupt
SUPL_MASK
1: Mask all GPIO Interrupt
0: Unmask all GPIO interrupt
GPIO_INT_MASK
PRESL_INT_MASK
1: Mask PRESL Interrupt
0: Unmask PRESL interrupt
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DEFAULT
Table 24.
REGISTER
DESCRIPTION
ADDRESS
FIELD NAME
BIT
R/W
0x45
SAM1 and SAM2 Interrupt Mask Register
1: Mask SAM1 EARLY Interrupt
0: Unmask SAM1 EARLY interrupt
0x45
EARLY_SAM1_MASK
MUTE_SAM1 _MASK
PROT_SAM1_MASK
EARLY_SAM2_MASK
MUTE_SAM2 _MASK
PROT_SAM2_MASK
VCC_FAIL_SAM_MASK
VCC_FAIL_UC_MASK
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1: Mask SAM1 MUTE Interrupt
0: Unmask SAM1 MUTE interrupt
0x45
0x45
0x45
0x45
0x45
0x45
1: Mask SAM1 PROT Interrupt
0: Unmask SAM1 PROT interrupt
1: Mask SAM2 EARLY Interrupt
0: Unmask SAM2 EARLY interrupt
1: Mask SAM2 MUTE Interrupt
0: Unmask SAM2 MUTE interrupt
1: Mask SAM2 PROT Interrupt
0: Unmask SAM2 PROT interrupt
1: Mask VCC_FAIL Interrupt on all SAMs
0: Unmask VCC_FAIL Interrupt on all SAMs
1: Mask VCC_FAIL Interrupt on all User Card
0: Unmask VCC_FAIL Interrupt on all User Card
0x45
0x46
0x46
SAM3 and GPIO Interrupt Mask Register
1: Mask SAM3 EARLY Interrupt
0: Unmask SAM3 EARLY interrupt
EARLY_SAM3_MASK
MUTE_SAM3 _MASK
PROT_SAM3_MASK
GPIO4_INT_MASK
GPIO3_INT_MASK
GPIO2_INT_MASK
GPIO1_INT_MASK
7
6
5
4
3
2
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1: Mask SAM3 MUTE Interrupt
0: Unmask SAM3 MUTE interrupt
0x46
0x46
0x46
0x46
0x46
0x46
1: Mask SAM3 PROT Interrupt
0: Unmask SAM3 PROT interrupt
1: Mask GPIO4 Interrupt
0: Unmask GPIO4 interrupt
1: Mask GPIO3 Interrupt
0: Unmask GPIO3 interrupt
1: Mask GPIO2 Interrupt
0: Unmask GPIO2 interrupt
1: Mask GPIO1 Interrupt
0: Unmask GPIO1 interrupt
54
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9 Application and Implementation
9.1 Application Information
TCA5013 is a smartcard interface IC that is used in POS terminals that support EMV 4.3, ISO7816 - 3 and ISO
7816 - 10 smartcards. The below application note provides general guidelines for implementing the device in a
POS terminal.
9.2 Typical Application
VDD=VDDI= 3.3 V
CVDD
=
CVUP
=
LVDD
=
VDDI
100uF
100nF
100nF
10uF
10uH
DVUP
10k
PRES
C8
C4
User
Card
Slot
IOUC
CLKUC
RSTUC
VCCUC
10k
10k
10k 10k
200nF
200nF
200nF
GNDUC
SDA
SCL
INT
IOS1
CLKS1
SAM1
GPIO1
RSTS1
VCCS1
Card
Slot
GPIO2
GPIO3
GPIO4
TCA5013
GNDS
IOS2
CLKS2
SAM2
Card
Slot
RSTS2
VCCS2
SHDN
GNDS
IOMC1
IOS3
CLKIN1
IOMC2
CLKIN2
SAM3
Card
Slot
CLKS3
RSTS3
VCCS3
200nF
GNDS
1uF
Figure 26. POS Terminal Typical Application
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Typical Application (continued)
9.2.1 Design Requirements
For this design example shown below, Table 25 shows the input parameters.
Table 25. Design Parameters
DESIGN PARAMETER
VDD input Voltage range
VDDI input Voltage range
VCC output Voltage range
Sum of all ICC currents
VCC output ripple voltage
EXAMPLE VALUE
2.7 V to 4.2 V
2.7 V to 4.2 V
1.8 V, 3 V, 5 V
180 mA (max)
90 mV (max)
Max load transient supported on
VCC
As defined in the Electrical
Characteristics—Card VCC
9.2.2 Detailed Design Procedure
9.2.2.1 IO Pin Fall Time Setting
The VOL on the IO pin depends on the IO fall time setting shown in Table 7. It also shows the different IO fall time
settings that are usable for different VCC voltage. Care should be taken to select a register setting such that VOL
meets the system requirements.
9.2.2.2 CLK Pin Rise Time And Fall Time Settings
Electrical Characteristics—Card CLK shows the typical rise and fall time of the clock signal for a 30 pF load.
Because most applications will not have a typical 30 pF load, the rise and fall time of the clock signal will need to
be calibrated for the board. EMV 4.3 specifies that the rise/fall time on the clock signal shall not be more than 8%
of the clock period. It is recommended that the slowest fall time setting that meets the EMV requirement be
selected. For systems where multiple clock frequencies will be used, it is recommended that a different fall time
setting be used for each clock frequency.
9.2.3 Application Curves
350
300
250
200
150
100
REG 07H Bit [4:3] 00
REG 07H Bit [4:3] 01
50
REG 07H Bit [4:3] 10
REG 07H Bit [4:3] 11
0
0
200
400
600
800
1000
1200
IOL (ꢀA)
C002
Figure 27. VOL vs IOL for User Card
56
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10 Power Supply Recommendations
The TCA5013 has two power supplies VDD and VDDI. When the device is powering up, the ramp rates of VDD and
VDDI can cause the supervisor fault to be asserted. The supervisor fault at power up can be avoided if VDD is
ramped and stable before VDDI is ramped.
10.1 Power-On-Reset
When the voltage on these pins ramps an internal power-on-reset circuit holds the device in reset condition
unless the voltage on both pins rises above the VPORR voltage defined Table 26. Values in Table 26 are
ensured by design, but are not tested in production.
Table 26. Power On Reset Thresholds
PARAMETER
VPORF
DESCRIPTION
MIN
1.8
TYP
1.85
1.5
MAX
1.95
1.55
2
UNIT
Voltage trip point of POR on falling VDD
Voltage trip point of POR on falling VDDI
Voltage trip point of POR on rising VDD
Voltage trip point of POR on rising VDDI
V
V
V
V
1.4
1.9
1.95
1.5
VPORR
1.45
1.55
11 Layout
11.1 Layout Guidelines
11.1.1 DC-DC Boost Layout Recommendation
Some key guidelines are listed here to be followed for the layout of the DC-DC boost in the TCA5013:
•
•
•
The inductor must be placed close to the LX pin such that the trace resistance between the LX pin and the
inductor terminal is as small as possible.
The 10 µF input capacitor on VDD shall be placed close to the inductor terminal and the two shall be
connected by a copper pour to minimize resistance as much as possible.
The other terminal of the 10 µF capacitor should be connected to GNDP plane by multiple vias to provide a
low resistance path to ground.
•
•
The 100 nF capacitor should be placed as close to VDD pin as possible.
The anode of the schottky diode shall be placed as close as possible to the inductor and shall be connected
to it by a copper pour to minimize resistance as much as possible.
•
The 10 µF output capacitor on VUP should have a very low resistive connection to VUP and GNDP.
11.1.2 Card Interface Layout Recommendations
The card interface layout is important for proper operation of the device and for meeting EMV4.3 electrical
requirements:
•
If possible two 100 nF capacitors should be connected to VCC. One near the TCA5013 and one close to the
card slot.
•
•
If only one 200 nF capacitor is used it should be placed close to the TCA5013.
If possible the CLK trace should be routed on a separate signal layer different from the layer on which the
other card interface traces (IO and RST) are routed. It is also recommended that the two signal layers be
separated by a ground plane if possible.
•
The GNDS, GNDUC and GND pins should be connected to the ground plane with the shortest trace possible
to reduce inductance from the device ground to the ground plane. This is critical in order for the device to
meet the 8 kV IEC protection level on the card interface pins.
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11.2 Layout Example
VIA to VDD plane
Top layer copper pour
Bottom layer copper pour
VIA from top signal layer to bottom signal layer
Solder pad for device pin connection
VIA to GND plane
VDD
10uF
10uH
GNDP
GNDP
VUP
LX
1uF
Figure 28. Example Layout of DC-DC Boost Section of TCA5013
58
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12 器件和文档支持
12.1 商标
All trademarks are the property of their respective owners.
12.2 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
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59
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TCA5013ZAHR
ACTIVE
NFBGA
ZAH
48
3000 RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
RN013
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Mar-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TCA5013ZAHR
NFBGA
ZAH
48
3000
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Mar-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
NFBGA ZAH 48
SPQ
Length (mm) Width (mm) Height (mm)
336.6 336.6 31.8
TCA5013ZAHR
3000
Pack Materials-Page 2
PACKAGE OUTLINE
ZAH0048A
NFBGA - 1.2 mm max height
SCALE 2.500
PLASTIC BALL GRID ARRAY
5.1
4.9
B
A
BALL A1 CORNER
INDEX AREA
5.1
4.9
(0.89)
C
1.2 MAX
SEATING PLANE
0.08 C
0.25
TYP
0.15
BALL TYP
4 TYP
SYMM
(0.5) TYP
J
H
G
F
(0.5) TYP
SYMM
4
E
D
C
TYP
0.35
48X
0.25
B
A
0.15
0.05
C A
C
B
0.5 TYP
1
2
3
4
5
6
7
8
9
0.5 TYP
4221741/A 10/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
ZAH0048A
NFBGA - 1.2 mm max height
PLASTIC BALL GRID ARRAY
48X ( 0.25)
(0.5) TYP
3
4
5
6
7
8
9
1
2
A
B
C
(0.5) TYP
D
E
F
G
H
J
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:15X
0.05 MAX
0.05 MIN
METAL UNDER
SOLDER MASK
(
0.25)
METAL
(
0.25)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4221741/A 10/2014
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SSYZ015 (www.ti.com/lit/ssyz015).
www.ti.com
EXAMPLE STENCIL DESIGN
ZAH0048A
NFBGA - 1.2 mm max height
PLASTIC BALL GRID ARRAY
48X ( 0.25)
(R0.05) TYP
(0.5) TYP
A
1
2
4
5
6
8
9
3
7
(0.5) TYP
B
C
D
E
F
G
H
J
METAL
TYP
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:20X
4221741/A 10/2014
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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