TCA6416APWR [TI]
LOW-VOLTAGE 16-BIT I2C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS; 低压16位I2C和SMBus I / O扩展器，带有中断输出，复位和配置寄存器
| 型号： | TCA6416APWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOW-VOLTAGE 16-BIT I2C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS |
| 文件： | 总32页 (文件大小：881K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TCA6416A
www.ti.com ....................................................................................................................................................................................................... SCPS194–MAY 2009
LOW-VOLTAGE 16-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
1
FEATURES
•
Operating Power-Supply Voltage Range of
1.65 V to 5.5 V
•
•
•
•
•
•
•
•
5-V Tolerant I/O Ports
Active-Low Reset Input (RESET)
Open-Drain Active-Low Interrupt Output (INT)
400-kHz Fast I2C Bus
•
Allows Bidirectional Voltage-Level Translation
and GPIO Expansion Between:
–
–
–
–
1.8-V SCL/SDA and
1.8-V, 2.5-V, 3.3-V, or 5-V P Port
Input/Output Configuration Register
Polarity Inversion Register
2.5-V SCL/SDA and
1.8-V, 2.5-V, 3.3-V, or 5-V P Port
Internal Power-On Reset
Power Up With All Channels Configured as
Inputs
3.3-V SCL/SDA and
1.8-V, 2.5-V, 3.3-V, or 5-V P Port
•
•
•
No Glitch On Power Up
5-V SCL/SDA and
Noise Filter on SCL/SDA Inputs
1.8-V, 2.5-V, 3.3-V, or 5-V P Port
I2C to Parallel Port Expander
Latched Outputs With High-Current Drive
Maximum Capability for Directly Driving LEDs
•
•
•
Low Standby Current Consumption of 3 µA
•
•
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Schmitt-Trigger Action Allows Slow Input
Transition and Better Switching Noise
Immunity at the SCL and SDA Inputs
ESD Protection Exceeds JESD 22
–
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
–
–
–
–
Vhys = 0.18 V Typ at 1.8 V
Vhys = 0.25 V Typ at 2.5 V
Vhys = 0.33 V Typ at 3.3 V
Vhys = 0.5 V Typ at 5 V
1000-V Charged-Device Model (C101)
PW PACKAGE
(TOP VIEW)
RTW PACKAGE
(TOP VIEW)
ZQS PACKAGE
(TOP VIEW)
1
24 VCCP
INT
VCCI
RESET
P00
2
23
SDA
3
22
21
20
19
18
SCL
ADDR
P17
24 23 22 21 20 19
4
E
1
2
3
4
5
6
18
17
16
15
14
13
P00
P01
P02
P03
P04
P05
ADDR
P17
P16
P15
P14
P13
5
P01
D
C
B
A
6
P02
P16
Exposed
Center
Pad
7
P03
P15
8
P04
17 P14
16
15 P12
9
P05
P13
10
11
12
P06
7
8
9 10 11 12
5
4
3
2
1
P07
P11
P10
14
13
GND
The exposed center pad, if used, must be connected
only as a secondary GND or must be left electrically open.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TCA6416A
SCPS194–MAY 2009 ....................................................................................................................................................................................................... www.ti.com
DESCRIPTION/ORDERING INFORMATION
This 16-bit I/O expander for the two-line bidirectional bus (I2C) is designed to provide general-purpose remote I/O
expansion for most microcontroller families via the I2C interface [serial clock (SCL) and serial data (SDA)].
The major benefit of this device is its wide VCC range. It can operate from 1.65 V to 5.5 V on the P-port side and
on the SDA/SCL side. This allows the TCA6416AA to interface with next-generation microprocessors and
microcontrollers on the SDA/SCL side, where supply levels are dropping down to conserve power. In contrast to
the dropping power supplies of microprocessors and microcontrollers, some PCB components, such as LEDs,
remain at a 5-V power supply.
The bidirectional voltage level translation in the TCA6416A is provided through VCCI. VCCI should be connected to
the VCC of the external SCL/SDA lines. This indicates the VCC level of the I2C bus to the TCA6416A. The voltage
level on the P-port of the TCA6416A is determined by the VCCP
.
The TCA6416A consists of two 8-bit Configuration (input or output selection), Input, Output, and Polarity
Inversion (active high) registers. At power on, the I/Os are configured as inputs. However, the system master can
enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or
output is kept in the corresponding input or output register. The polarity of the Input Port register can be inverted
with the Polarity Inversion register. All registers can be read by the system master.
The system master can reset the TCA6416A in the event of a timeout or other improper operation by asserting a
low in the RESET input. The power-on reset puts the registers in their default state and initializes the I2C/SMBus
state machine. The RESET pin causes the same reset/initialization to occur without depowering the part.
The TCA6416A open-drain interrupt (INT) output is activated when any input state differs from its corresponding
Input Port register state and is used to indicate to the system master that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the
remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via
the I2C bus. Thus, the TCA6416A can remain a simple slave device.
The device P-port outputs have high-current sink capabilities for directly driving LEDs while consuming low
device current.
One hardware pin (ADDR) can be used to program and vary the fixed I2C address and allow up to two devices to
share the same I2C bus or SMBus.
ORDERING INFORMATION
TA
PACKAGE(1)(2)
ORDERABLE PART NUMBER
TCA6416AZQSR
TOP-SIDE MARKING
PH416
BGA – ZQS (Pb-free)
Reel of 2500
Reel of 3000
Reel of 2000
–40°C to 85°C
QFN – RTW
TCA6416ARTWR
PH416
TSSOP – PW
TCA6416APWR
PH416
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ZQS Package Terminal Assignments
E
D
C
B
A
P13
P15
P16
ADDR
SCL
5
P11
P14
P17
VCCP
SDA
4
P10
P12
P01
VCCI
INT
3
GND
P07
P04
NB
P06
P05
P03
P02
P00
1
RESET
2
2
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TERMINAL FUNCTIONS
TERMINAL
NO.
DESCRIPTION
NAME
TSSOP
(PW)
QFN
BGA
(RTW)
(ZQS)
1
22
A3
INT
Interrupt output. Connect to VCCI or VCCP through a pullup resistor.
Supply voltage of I2C bus. Connect directly to the VCC of the external I2C master. Provides
voltage-level translation.
2
23
B3
VCCI
3
24
1
A2
A1
C3
B1
C1
C2
D1
E1
D2
E2
E3
E4
D3
E5
D4
D5
C5
C4
B5
A5
A4
B4
RESET
P00
Active-low reset input. Connect to VCCI through a pullup resistor, if no active connection is used.
P-port input/output (push-pull design structure). At power on, P00 is configured as an input.
P-port input/output (push-pull design structure). At power on, P01 is configured as an input.
P-port input/output (push-pull design structure). At power on, P02 is configured as an input.
P-port input/output (push-pull design structure). At power on, P03 is configured as an input.
P-port input/output (push-pull design structure). At power on, P04 is configured as an input.
P-port input/output (push-pull design structure). At power on, P05 is configured as an input.
P-port input/output (push-pull design structure). At power on, P06 is configured as an input.
P-port input/output (push-pull design structure). At power on, P07 is configured as an input.
Ground
4
5
2
P01
6
3
P02
7
4
P03
8
5
P04
9
6
P05
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
7
P06
8
P07
9
GND
P10
10
11
12
13
14
15
16
17
18
19
20
21
P-port input/output (push-pull design structure). At power on, P10 is configured as an input.
P-port input/output (push-pull design structure). At power on, P11 is configured as an input.
P-port input/output (push-pull design structure). At power on, P12 is configured as an input.
P-port input/output (push-pull design structure). At power on, P13 is configured as an input.
P-port input/output (push-pull design structure). At power on, P14 is configured as an input.
P-port input/output (push-pull design structure). At power on, P15 is configured as an input.
P-port input/output (push-pull design structure). At power on, P16 is configured as an input.
P-port input/output (push-pull design structure). At power on, P17 is configured as an input.
Address input. Connect directly to VCCP or ground.
P11
P12
P13
P14
P15
P16
P17
ADDR
SCL
SDA
VCCP
Serial clock bus. Connect to VCCI through a pullup resistor.
Serial data bus. Connect to VCCI through a pullup resistor.
Supply voltage of TCA6416A for P port
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Voltage Translation
Table 1 shows how to set up VCC levels for the necessary voltage translation between the I2C bus and the
TCA6416A.
Table 1. Voltage Translation
VCCI (SDA AND SCL OF I2C MASTER)
(V)
VCCP (P PORT)
(V)
1.8
1.8
1.8
1.8
2.5
2.5
2.5
2.5
3.3
3.3
3.3
3.3
5
1.8
2.5
3.3
5
1.8
2.5
3.3
5
1.8
2.5
3.3
5
1.8
2.5
3.3
5
5
5
5
LOGIC DIAGRAM (POSITIVE LOGIC)
Interrupt
Logic
1
INT
LP Filter
21
ADDR
22
23
SCL
SDA
I2C Bus
Shift
Input
Filter
P17–P10
P07–P00
16 Bits
I/O Port
Register
Control
2
Write Pulse
Read Pulse
VCCI
24
3
VCCP
Power-On
Reset
RESET
12
GND
A. All I/Os are set to inputs at reset.
B. Pin numbers shown are for the PW package.
4
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Simplified Schematic of P0 to P17
Data From
Shift Register
Output Port
Configuration
Register
Register Data
VCCP
Data From
Shift Register
D
Q
Q1
FF
CK
Write Configuration
Pulse
D
Q
Q
Q
FF
CK
P00 to P17
Write Pulse
Q2
ESD Protection Diode
Output
Port
Register
Input
Port
Register
GND
Input Port
D
Q
Q
Register Data
FF
Read Pulse
CK
To INT
Data From
Shift Register
Polarity
D
Q
Q
Register Data
FF
CK
Write Polarity Pulse
Polarity
Inversion
Register
A. On power up or reset, all registers return to default values.
I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The
input voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In
this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on
the SDA input/output, while the SCL input is high (see Figure 1). After the Start condition, the device address
byte is sent, most significant bit (MSB) first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. The address (ADDR) input of the slave device must
not be changed between the Start and the Stop conditions.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (Start or Stop) (see Figure 2).
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A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 1).
Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see
Figure 3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,
the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold
times must be met to ensure proper operation.
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
SDA
SCL
S
P
Stop Condition
Start Condition
Figure 1. Definition of Start and Stop Conditions
SDA
SCL
Data Line
Change
Figure 2. Bit Transfer
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Clock Pulse for
Acknowledgment
Start
Condition
Figure 3. Acknowledgment on the I2C Bus
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Interface Definition
BIT
BYTE
7 (MSB)
L
6
5
4
3
2
1
0 (LSB)
R/W
I2C slave address
I/O data bus
H
L
L
L
L
ADDR
P01
P07
P06
P16
P05
P15
P04
P14
P03
P13
P02
P12
P00
P17
P11
P10
Device Address
The address of the TCA6416A is shown in Figure 4.
Slave Address
AD
DR
0
1
0
0
R/W
0
0
Fixed
Programmable
Figure 4. TCA6416A Address
Address Reference
ADDR
I2C BUS SLAVE ADDRESS
64 (decimal), 40 (hexadecimal)
66 (decimal), 42 (hexadecimal)
L
H
The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read
operation, while a low (0) selects a write operation.
Control Register and Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte, which is
stored in the control register in the TCA6416A. Three bits of this data byte state the operation (read or write) and
the internal registers (input, output, polarity inversion, or configuration) that will be affected. This register can be
written or read through the I2C bus. The command byte is sent only during a write transmission.
Once a new command has been sent, the register that was addressed continues to be accessed by reads until a
new command byte has been sent.
B7 B6
B5 B4 B3 B2 B1 B0
Figure 5. Control Register Bits
Command Byte
CONTROL REGISTER BITS
COMMAND BYTE
POWER-UP
DEFAULT
REGISTER
PROTOCOL
(HEX)
B7
0
B6
0
B5
0
B4
0
B3
0
B2
0
B1
0
B0
0
00
01
02
03
04
05
06
07
Input Port 0
Input Port 1
Output Port 0
Output Port 1
Read byte
Read byte
xxxx xxxx(1)
xxxx xxxx
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
Read/write byte
Read/write byte
1111 1111
1111 1111
0000 0000
0000 0000
1111 1111
1111 1111
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
Polarity Inversion Port 0 Read/write byte
Polarity Inversion Port 1 Read/write byte
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
0
Configuration Port 0
Configuration Port 1
Read/write byte
Read/write byte
0
0
0
0
0
1
1
1
(1) Undefined
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Register Descriptions
The Input Port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether the
pin is defined as an input or an output by the Configuration register. They act only on read operation. Writes to
these registers have no effect. The default value (X) is determined by the externally applied logic level. Before a
read operation, a write transmission is sent with the command byte to indicate to the I2C device that the Input
Port register will be accessed next.
Registers 0 and 1 (Input Port Registers)
BIT
I-07
X
I-06
X
I-05
X
I-04
X
I-03
X
I-02
X
I-01
X
I-00
X
DEFAULT
BIT
I-17
X
I-16
X
I-15
X
I-14
X
I-13
X
I-12
X
I-11
X
I-10
X
DEFAULT
The Output Port registers (registers 2 and 3) shows\ the outgoing logic levels of the pins defined as outputs by
the Configuration register. Bit values in these registers have no effect on pins defined as inputs. In turn, reads
from these registers reflect the value that is in the flip-flop controlling the output selection, NOT the actual pin
value.
Registers 2 and 3 (Output Port Registers)
BIT
O-07
1
O-06
1
O-05
1
O-04
1
O-03
1
O-02
1
O-01
1
O-00
1
DEFAULT
BIT
O-17
1
O-16
1
O-15
1
O-14
1
O-13
1
O-12
1
O-11
1
O-10
1
DEFAULT
The Polarity Inversion registers (register 4 and 5) allow polarity inversion of pins defined as inputs by the
Configuration register. If a bit in these registers is set (written with 1), the corresponding port pin's polarity is
inverted. If a bit in these registers is cleared (written with a 0), the corresponding port pin's original polarity is
retained.
Registers 4 and 5 (Polarity Inversion Registers)
BIT
P-07
0
P-06
0
P-05
0
P-04
0
P-03
0
P-02
0
P-01
0
P-00
0
DEFAULT
BIT
P-17
0
P-16
0
P-15
0
P-14
0
P-13
0
P-12
0
P-11
0
P-10
0
DEFAULT
The Configuration registers (registers 6 and 7) configure the direction of the I/O pins. If a bit in these registers is
set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in these
registers is cleared to 0, the corresponding port pin is enabled as an output.
Registers 6 and 7 (Configuration Registers)
BIT
C-07
1
C-06
1
C-05
1
C-04
1
C-03
1
C-02
1
C-01
1
C-00
1
DEFAULT
BIT
C-17
1
C-16
1
C-15
1
C-14
1
C-13
1
C-12
1
C-11
1
C-10
1
DEFAULT
Power-On Reset
When power (from 0 V) is applied to VCCP, an internal power-on reset holds the TCA6416A in a reset condition
until VCCP has reached VPOR. At that time, the reset condition is released, and the TCA6416A registers and
I2C/SMBus state machine initializes to their default states. After that, VCCP must be lowered to below VPORF and
back up to the operating voltage for a power-reset cycle.
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Reset Input (RESET)
The RESET input can be asserted to initialize the system while keeping the VCCP at its operating level. A reset
can be accomplished by holding the RESET pin low for a minimum of tW. The TCA6416A registers and
I2C/SMBus state machine are changed to their default state once RESET is low (0). When RESET is high (1),
the I/O levels at the P port can be changed externally or through the master. This input requires a pullup resistor
to VCCI, if no active connection is used.
Interrupt Output (INT)
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv, the signal
INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or
when data is read from the port that generated the interrupt. Resetting occurs in the read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur
during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this
pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the
state of the pin does not match the contents of the Input Port register.
The INT output has an open-drain structure and requires pullup resistor to VCCP or VCCI depending on the
application. INT should be connected to the voltage source of the device that requires the interrupt information.
Bus Transactions
Data is exchanged between the master and TCA6416A through write and read commands.
Writes
Data is transmitted to the TCA6416A by sending the device address and setting the least-significant bit (LSB) to
a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which
register receives the data that follows the command byte. There is no limitation on the number of data bytes sent
in one write transmission.
The eight registers within the TCA6416A are configured to operate as four register pairs. The four pairs are input
ports, output ports, polarity inversion ports and configuration ports. After sending data to one register, the next
data byte is sent to the other register in the pair (see Figure 6 and Figure 7). For example, if the first byte is send
to Output Port 1 (register 3), the next byte is stored in Output Port 0 (register 2).
There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register
may be updated independently of the other registers.
SCL
1
2
3
4
5
6
7
8
9
Command Byte
Slave Address
Data to Port 0
Data 0
Data to Port 1
Data 1
AD
DR
SDA
S
0
1
0
0
0
0
0
A
0
0
0
0
0
0
1
0
A 0.7
0.0 A 1.7
1.0 A
P
Start Condition
Acknowledge
From Slave
Acknowledge
From Slave
Acknowledge
From Slave
R/W
Write to Port
Data Out from Port 0
tpv
Data Valid
tpv
Data Out from Port 1
Figure 6. Write to Output Port Register
<br/>
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SCL
SDA
1
2
3
4
5
6
7
8
0
9
1
0
2
0
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
Data to Register
Data to Register
Slave Address
Command Byte
AD
DR
S
0
1
0
0
0
0
A
0
0
0
1
1/0 0/1 A MSB
Data 0
LSB A MSB
Data1
LSB
A
P
Start Condition
Acknowledge
From Slave
Acknowledge
From Slave
Acknowledge
From Slave
R/W
Figure 7. Write to Configuration or Polarity Inversion Registers
Reads
The bus master first must send the TCA6416A address with the LSB set to a logic 0 (see Figure 4 for device
address). The command byte is sent after the address and determines which register is accessed.
After a restart, the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register
defined by the command byte then is sent by the TCA6416A (see Figure 8 and Figure 9).
After a restart, the value of the register defined by the command byte matches the register being accessed when
the restart occurred. For example, if the command byte references Input Port 1 before the restart, and the restart
occurs when Input Port 0 is being read, the stored command byte changes to reference Input Port 0. The original
command byte is forgotten. If a subsequent restart occurs, Input Port 0 is read first. Data is clocked into the
register on the rising edge of the ACK clock pulse. After the first byte is read, additional bytes may be read, but
the data now reflects the information in the other register in the pair. For example, if Input Port 1 is read, the next
byte read is Input Port 0.
Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number
of data bytes received in one read transmission, but when the final byte is received, the bus master must not
acknowledge the data.
Data From Lower
or Upper Byte
Acknowledge
From Slave
Acknowledge
From Slave
Acknowledge
From Slave
Acknowledge
From Master
Slave Address
of Register
Slave Address
AD
DR
AD
DR
Command Byte
S
0
1
0
0
0
0
0
A
A
S
0
1
0
0
0
0
1
A
MSB
Data
LSB A
First Byte
R/W
R/W
At this moment, master transmitter
becomes master receiver, and
slave receiver becomes slave transmitter.
Data From Upper
or Lower Byte
of Register
No Acknowledge
From Master
MSB
LSB NA P
Data
Last Byte
Figure 8. Read From Register
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1
2
3
4
5
6
7
R
1
9
SCL
SDA
Data From Port
Data 1
Slave Address
Data From Port
Data 4
AD
DR
S
0
1
0
0
0
A
A
NA P
0
Start
Condition
NACK From
Master
ACK From
Slave
ACK From
Master
Stop
Condition
R/W
Read From
Port
Data Into
Port
Data 2
Data 3
Data 4
Data 5
t
t
ps
ph
INT is cleared
by Read from Port
INT
t
Stop not needed
to clear INT
t
iv
ir
A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read
Input Port register).
B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from P port (see Figure 8).
Figure 9. Read Input Port Register
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ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCCI
VCCP
VI
Supply voltage range
Supply voltage range
Input voltage range(2)
Output voltage range(2)
Input clamp current
–0.5
–0.5
–0.5
–0.5
6.5
6.5
6.5
6.5
±20
±20
±20
±20
50
V
V
V
VO
V
IIK
ADDR, RESET, SCL
VI < 0
mA
mA
IOK
Output clamp current
INT
VO < 0
P port
SDA
VO < 0 or VO > VCCP
VO < 0 or VO > VCCI
VO = 0 to VCCP
VO = 0 to VCCI
VO = 0 to VCCP
IIOK
Input/output clamp current
mA
P port
SDA, INT
P port
IOL
IOH
Continuous output low current
mA
mA
25
Continuous output high current
Continuous current through GND
Continuous current through VCCP
Continuous current through VCCI
50
200
160
10
ICC
mA
PW package
RTW package
ZQS package
88
θJA
Package thermal impedance(3)
66 °C/W
171
Tstg
Storage temperature range
°C1–6550
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS
MIN
1.65
MAX
5.5
UNIT
VCCI
Supply voltage
Supply voltage
V
VCCP
1.65
5.5
SCL, SDA, RESET
ADDR, P17–P00
SCL, SDA, RESET
ADDR, P17–P00
P17–P00
0.7 × VCCI
0.7 × VCCP
–0.5
5.5
VIH
VIL
High-level input voltage
Low-level input voltage
V
V
5.5
0.3 × VCCI
–0.5 0.3 × VCCP
IOH
IOL
TA
High-level output current
Low-level output current
Operating free-air temperature
10
25
mA
mA
°C
P17–P00
–40
85
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ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, VCCI = 1.65 V to 5.5 V (unless otherwise noted)
PARAMETER
Input diode clamp
TEST CONDITIONS
VCCP
MIN
TYP(1)
MAX UNIT
VIK
II = –18 mA
VI = VCCP or GND, IO = 0
1.65 V to 5.5 V
–1.2
V
voltage
Power-on reset
voltage
VPOR
1.65 V to 5.5 V
1
1.4
V
1.65 V
2.3 V
1.2
1.8
2.6
4.1
1.1
1.7
2.5
4.0
IOH = –8 mA
3 V
4.5 V
P-port high-level
output voltage
VOH
V
1.65 V
2.3 V
IOH = –10 mA
3 V
4.5 V
1.65 V
2.3 V
0.45
0.25
0.25
0.2
IOL = 8 mA
3 V
4.5 V
P-port low-level
output voltage
VOL
V
1.65 V
2.3 V
0.6
0.3
IOL = 10 mA
3 V
0.25
0.2
4.5 V
SDA
INT
VOL = 0.4 V
VOL = 0.4 V
1.65 V to 5.5 V
1.65 V to 5.5 V
3
3
IOL
mA
15
SCL, SDA,
RESET
VI = VCCI or GND
±0.1
II
1.65 V to 5.5 V
µA
ADDR
P port
P port
VI = VCCP or GND
VI = VCCP
±0.1
1
IIH
IIL
µA
µA
1.65 V to 5.5 V
VI = GND
1
3.6 V to 5.5 V
2.3 V to 3.6 V
1.65 V to 2.3 V
3.6 V to 5.5 V
2.3 V to 3.6 V
1.65 V to 2.3 V
10
6.5
4
20
15
9
VI on SDA and RESET = VCCI or GND,
SDA, P port,
ADDR, RESET
VI on P port and ADDR = VCCP
,
IO = 0, I/O = inputs, fSCL = 400 kHz
ICC
(ICCI + ICCP
µA
)
1.5
1
7
VI on SCL, SDA and RESET= VCCI or GND,
SCL, SDA, P port,
ADDR, RESET
VI on P port and ADDR = VCCP
IO = 0, I/O = inputs, fSCL = 0
,
3.2
1.7
0.5
SCL,SDA,
RESET
One input at VCCI – 0.6 V,
Other inputs at VCCI or GND
25
80
ΔICCI
ΔICCP
1.65 V to 5.5 V
µA
One input at VCCP – 0.6 V,
Other inputs at VCCP or GND
P port, ADDR
Ci
SCL
VI = VCCI or GND
VIO = VCCI or GND
VIO = VCCP or GND
1.65 V to 5.5 V
1.65 V to 5.5 V
6
7
7
8
pF
pF
SDA
P port
Cio
7.5
8.5
(1) Except for ICC, all typical values are at nominal supply voltage (1.8-V, 2.5-V, 3.3-V, or 5-V VCC) and TA = 25°C. For ICC, the typical
values are at VCCP = VCCI = 3.3 V and TA = 25°C.
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I2C INTERFACE TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 10)
STANDARD MODE
I2C BUS
FAST MODE
I2C BUS
UNIT
MIN
0
MAX
MIN
0
MAX
fscl
I2C clock frequency
100
400 kHz
tsch
tscl
I2C clock high time
I2C clock low time
I2C spike time
I2C serial data setup time
I2C serial data hold time
I2C input rise time
I2C input fall time
I2C output fall time; 10 pF to 400 pF bus
I2C bus free time between Stop and Start
I2C Start or repeater Start condition setup time
I2C Start or repeater Start condition hold time
I2C Stop condition setup time
Valid data time; SCL low to SDA output valid
4
0.6
1.3
0
µs
µs
4.7
0
tsp
50
50
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
µs
tsds
tsdh
ticr
250
0
100
0
(1)
1000
300
20 + 0.1Cb
300
300
300
(1)
(1)
ticf
20 + 0.1Cb
20 + 0.1Cb
tocf
tbuf
tsts
300
4.7
4.7
4
1.3
0.6
0.6
0.6
tsth
tsps
tvd(data)
4
1
1
1
1
Valid data time of ACK condition; ACK signal from SCL low to SDA
(out) low
tvd(ack)
µs
(1) Cb = total capacitance of one bus line in pF
RESET TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 13)
FAST MODE
I2C BUS
STANDARD MODE
I2C BUS
UNIT
MIN
4
MAX
MIN
MAX
tW
Reset pulse duration
Reset recovery time
4
0
ns
ns
ns
tREC
0
tRESET Time to reset(1)
600
600
(1) Minimum time for SDA to become high or minimum time to wait before doing a START
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 10)
FAST MODE
STANDARD MODE
I2C BUS
I2C BUS
TO
PARAMETER
FROM
UNIT
MIN
MAX
MIN
MAX
4
tIV
Interrupt valid time
Interrupt reset delay time
Output data valid
P port
SCL
INT
INT
4
4
µs
µs
ns
ns
ns
tIR
4
tPV
tPS
tPH
SCL
P7–P0
SCL
400
400
Input data setup time
Input data hold time
P port
P port
0
0
SCL
300
300
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TYPICAL CHARACTERISTICS
TA = 25°C (unless otherwise noted)
SUPPLY CURRENT
vs
TEMPERATURE
STANDBY SUPPLY CURRENT
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
vs
TEMPERATURE
22
20
18
16
14
12
10
8
22
20
18
16
14
12
10
8
2000
1800
1600
1400
1200
1000
800
VCC = 5.5 V
VCC = 5 V
VCC = 5.5 V
VCC = 5 V
VCC = 3.3 V
VCC = 2.5 V
VCC = 1.8 V
VCC = 3.3 V
VCC = 2.5 V
VCC = 1.8 V
600
6
6
400
4
4
VCC = 1.65 V
200
2
2
VCC = 1.65 V
0
0
-40
0
–40 –15
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
-15
10
35
60
85
10
35
60
85
Temperature,TA (°C)
Temperature,TA (°C)
Supply Voltage, VCC (V)
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
50
40
30
20
10
0
30
35
30
25
20
15
10
5
V
= 1.8 V
V
= 1.65 V
V
= 2.5 V
CC
CC
CC
T
= –40°C
T
= –40°C
A
A
25
20
15
10
5
T
= –40°C
A
T
= 25°C
A
T
= 25°C
T
= 25°C
A
A
T
= 85°C
A
T
= 85°C
A
T
= 85°C
A
0
0
0.0
0.5 0.6
0.0
0.5
0.6
0.0
0.5
0.6
0.1
0.2
0.3
0.4
0.1
0.2
0.3
0.4
0.1
0.2
0.3
0.4
Output Low Voltage, V (V)
OL
Output Low Voltage, V (V)
OL
Output Low Voltage, V (V)
OL
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
V
= 3.3 V
V
= 5.0 V
V
= 5.5 V
CC
CC
CC
T
= –40°C
T
= –40°C
A
A
T
= –40°C
A
T
= 25°C
A
T
= 25°C
T
= 25°C
A
A
T
= 85°C
T
= 85°C
A
T
= 85°C
A
A
0.0
0.5
0.6
0.0
0.5
0.6
0.0
0.5
0.6
0.1
0.2
0.3
0.4
0.1
0.2
0.3
0.4
0.1
0.2
0.3
0.4
Output Low Voltage, V (V)
Output Low Voltage, V (V)
Output Low Voltage, V (V)
OL
OL
OL
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TYPICAL CHARACTERISTICS (continued)
TA = 25°C (unless otherwise noted)
I/O LOW VOLTAGE
vs
TEMPERATURE
I/O SOURCE CURRENT
vs
OUTPUT HIGH VOLTAGE
I/O SOURCE CURRENT
vs
OUTPUT HIGH VOLTAGE
250
200
150
100
50
20
15
10
5
25
20
15
10
5
V = 1.8 V
CC
V
= 1.65 V
T
= –40°C
T = –40°C
A
CC
A
V
CC
= 1.8 V, I
SINK
= 10 mA
T
= 25°C
T
= 25°C
A
A
V
= 5 V, I
= 10 mA
CC
SINK
T
= 85°C
A
T
= 85°C
V
CC
= 1.8 V, I
V
= 1 mA
A
SINK
= 5 V, I
SINK
= 1 mA
CC
0
0
0
-40
-15
10
35
60
85
0.0
0.1 0.2
V
0.3
0.4
0.5
0.6
0.0
0.1 0.2
V
0.3
0.4
(V)
0.5
0.6
Temperature,T (°C)
– V
(V)
– V
A
CCP
OH
CCP
OH
I/O SOURCE CURRENT
vs
OUTPUT HIGH VOLTAGE
I/O SOURCE CURRENT
vs
OUTPUT HIGH VOLTAGE
I/O SOURCE CURRENT
vs
OUTPUT HIGH VOLTAGE
35
30
25
20
15
10
5
50
40
30
20
10
0
60
50
40
30
20
10
0
V
= 2.5 V
V
= 5.0 V
T = –40°C
A
T
= –40°C
V
= 3.3 V
CC
CC
CC
A
T
= –40°C
A
T
= 25°C
A
T
= 25°C
A
T
= 25°C
A
T
= 85°C
T
= 85°C
A
A
T
= 85°C
A
0
0.0
0.1 0.2
V
0.3
– V
0.4
(V)
0.5
0.6
0.0
0.1 0.2
V
0.3
0.4
(V)
0.5
0.6
0.0
0.1 0.2
V
0.3
– V
0.4
0.5
0.6
– V
(V)
OH
CCP
OH
CCP
OH
CCP
I/O SOURCE CURRENT
vs
OUTPUT HIGH VOLTAGE
I/O HIGH VOLTAGE
vs
TEMPERATURE
350
300
250
200
150
100
50
70
60
50
40
30
20
10
0
I
= –10 mA
V
= 5.5 V
SOURCE
CC
T
= –40°C
A
V
= 1.8 V
CC
T
= 25°C
A
V
= 5 V
CC
T
= 85°C
A
0
-40
-15
10
35
60
85
0.0
0.1 0.2
V
0.3
– V
0.4
(V)
0.5
0.6
Temperature, T (°C)
A
CCP
OH
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PARAMETER MEASUREMENT INFORMATION
V
CCI
R
= 1 kW
L
SDA
DUT
C
= 50 pF
L
(see Note A)
SDA LOAD CONFIGURATION
Two Bytes for READ Input Port Register
(see Figure 9)
Stop
Condition Condition
(P) (S)
Start
Address
Bit 7
(MSB)
Data
Bit 7
(MSB)
Data
Bit 0
(LSB)
Stop
Condition
(P)
R/W
Bit 0
(LSB)
ACK
(A)
Address
Bit 1
t
t
sch
scl
0.7 ´ V
CCI
SCL
SDA
0.3 ´ V
CCI
t
t
icr
vd
t
t
sts
sp
t
t
icf
t
buf
vd
t
t
sps
ocf
0.7 ´ V
0.3 ´ V
CCI
CCI
t
t
vd(ack)
icr
t
sdh
t
t
icf
sds
t
sth
Repeat Start
Condition
Stop
Condition
VOLTAGE WAVEFORMS
BYTE
DESCRIPTION
I2C address
1
2
Input register port data
A. CL includes probe and jig capacitance. tocf is measured with CL of 10 pF or 400 pF.
B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 10. I2C Interface Load Circuit and Voltage Waveforms
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PARAMETER MEASUREMENT INFORMATION (continued)
V
CCI
R
= 4.7 kW
L
INT
DUT
C
= 100 pF
L
(see Note A)
INTERRUPT LOAD CONFIGURATION
ACK
From Slave
ACK
Start
8 Bits
From Slave
Condition
R/W
1
(One Data Byte)
From Port
Slave Address
Data From Port
Data 2
AD
DR
Data 1
A
1
P
S
0
1
0
3
0
4
0
0
6
A
A
1
2
5
7
8
A
t
B
B
ir
t
ir
INT
A
t
iv
t
sps
A
Data
Into
Port
Address
Data 1
Data 2
0.7 ´ V
0.3 ´ V
CCI
CCI
0.5 ´ V
SCL
INT
CCI
R/W
A
t
iv
t
ir
0.5 ´ V
INT
CCI
Pn
0.5 ´ V
CCP
View A−A
A. CL includes probe and jig capacitance.
View B−B
B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 11. Interrupt Load Circuit and Voltage Waveforms
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PARAMETER MEASUREMENT INFORMATION (continued)
Pn
500 W
DUT
2 ´ V
CCP
C
= 50 pF
L
(see Note A)
500 W
P-PORT LOAD CONFIGURATION
0.7 ´ V
0.3 ´ V
CCP
CCI
SCL
P0
A
P3
Slave
ACK
SDA
Pn
t
pv
(see Note B)
Last Stable Bit
Unstable
Data
WRITE MODE (R/W = 0)
0.7 ´ V
0.3 ´ V
CCI
SCL
Pn
P0
A
P3
CCI
t
ph
t
ps
0.5 ´ V
CCP
READ MODE (R/W = 1)
A. CL includes probe and jig capacitance.
B. tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output.
C. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 12. P Port Load Circuit and Timing Waveforms
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PARAMETER MEASUREMENT INFORMATION (continued)
V
CCI
R
= 1 kW
L
Pn
500 W
SDA
DUT
2 ´ V
CCP
DUT
C = 50 pF
L
(see Note A)
C
= 50 pF
500 W
L
(see Note A)
SDA LOAD CONFIGURATION
P-PORT LOAD CONFIGURATION
Start
SCL
ACK or Read Cycle
SDA
0.3 ´ V
CCI
t
RESET
V
/2
RESET
CCP
t
t
REC
REC
t
W
V
/2
Pn
CCP
t
RESET
A. CL includes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. The outputs are measured one at a time, with one transition per measurement.
D. I/Os are configured as inputs.
E. All parameters and waveforms are not applicable to all devices.
Figure 13. Reset Load Circuits and Voltage Waveforms
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TCA6416A
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APPLICATION INFORMATION
Figure 14 shows an application in which the TCA6416A can be used.
V
V
CCI
CCP
10 kW ( 7)
V
CCI
(1.8 V)
ALARM
(see Note E)
2
24
Subsystem 1
(e.g., Alarm)
10 kW
10 kW 10 kW
10 kW
V
CC
V
V
CCI
CCP
4
5
22
23
P00
SCL
SCL
A
Master
Controller
SDA
INT
SDA
INT
1
3
P01
ENABLE
GND
RESET
RESET
B
6
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
7
8
9
TCA6416A
10
11
13
14
15
16
17
18
19
20
Keypad
21
ADDR
GND
12
A. Device address configured as 0100000 for this example.
B. P00 and P02–P10 are configured as inputs.
C. P01 and P11–P17 are configured as outputs.
D. Pin numbers shown are for the PW package.
E. Resistors are required for inputs (on P port) that may float. If a driver to an input will never let the input float, a resistor
is not needed. Outputs (in the P port) do not need pullup resistors.
Figure 14. Typical Application
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Minimizing ICC When I/Os Control LEDs
When the I/Os are used to control LEDs, normally they are connected to VCC through a resistor as shown in
Figure 14. The LED acts as a diode so, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The ΔICC
parameter in Electrical Characteristics shows how ICC increases as VIN becomes lower than VCC. Designs that
must minimize current consumption, such as battery power applications, should consider maintaining the I/O pins
greater than or equal to VCC when the LED is off.
Figure 15 shows a high-value resistor in parallel with the LED. Figure 16 shows VCC less than the LED supply
voltage by at least 1.2 V. Both of these methods maintain the I/O VIN at or above VCC and prevent additional
supply current consumption when the LED is off.
VCC
LED
100 kW
VCC
Px
Figure 15. High-Value Resistor in Parallel With the LED
3.3 V
5 V
LED
VCC
Px
Figure 16. Device Supplied by a Low Voltage
Power-On Reset Requirements
In the event of a glitch or data corruption, TCA6416A can be reset to its default conditions by using the power-on
reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
The two types of power-on reset are shown in Figure 17 and Figure 18.
V
CC
Ramp-Up
Ramp-Down
Re-Ramp-Up
V
CC_TRR_GND
Time
Time to Re-Ramp
V
V
V
CC_RT
CC_FT
CC_RT
Figure 17. VCC is Lowered Below 0.2 V or 0 V and Then Ramped Up to VCC
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V
CC
Ramp-Down
Ramp-Up
V
CC_TRR_VPOR50
V
drops below POR levels
IN
Time
Time to Re-Ramp
V
V
CC_FT
CC_RT
Figure 18. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC
Table 2 specifies the performance of the power-on reset feature for TCA6416A for both types of power-on reset.
Table 2. RECOMMENDED SUPPLY SEQUENCING AND RAMP RATES(1)(2)
PARAMETER
MIN TYP
MAX UNIT
tFT
Fall rate
See Figure 17
See Figure 17
See Figure 17
See Figure 18
0.1
0.1
1
2000
2000
ms
ms
µs
tRT
Rise rate
tTRR_GND
tTRR_POR50
Time to re-ramp (when VCC drops to GND)
Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV)
1
µs
Level that VCCP can glitch down to, but not cause a functional
disruption when VCCX_GW = 1 µs
VCC_GH
tGW
See Figure 19
See Figure 19
1.2
10
V
Glitch width that will not cause a functional disruption when
VCCX_GH = 0.5 × VCCx
µs
VPORF
VPORR
Voltage trip point of POR on falling VCC
Voltage trip point of POR on fising VCC
0.7
V
V
1.4
(1) TA = 25°C (unless otherwise noted).
(2) Not tested. Specified by design.
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. Figure 19 and Table 2 provide more
information on how to measure these specifications.
V
CC
V
CC_GH
Time
V
CC_GW
Figure 19. Glitch Width and Glitch Height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the
registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based
on the VCC being lowered to or from 0. Figure 20 and Table 2 provide more details on this specification.
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V
CC
V
POR
V
PORF
Time
POR
Time
Figure 20. VPOR
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Jul-2009
PACKAGING INFORMATION
Orderable Device
TCA6416APWR
TCA6416ARTWR
TCA6416AZQSR
Status (1)
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
24
24
24
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
QFN
RTW
ZQS
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
2500 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-May-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TCA6416APWR
TCA6416ARTWR
TSSOP
QFN
PW
24
24
2000
3000
330.0
330.0
16.4
12.4
6.95
4.3
8.3
4.3
1.6
1.5
8.0
8.0
16.0
12.0
Q1
Q2
RTW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-May-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TCA6416APWR
TCA6416ARTWR
TSSOP
QFN
PW
24
24
2000
3000
346.0
346.0
346.0
346.0
33.0
29.0
RTW
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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