TCA8418_技术文档

TCA8418

www.ti.com ......................................................................................................................................................................................... SCPS215–SEPTEMBER 2009

I²C CONTROLLED KEYPAD SCAN IC WITH INTEGRATED ESD PROTECTION

1

FEATURES

APPLICATIONS

•

Smart Phones

PDAs

GPS Devices

MP3 Players

Digital Cameras

•

Operating Power-Supply Voltage Range of

1.65 V to 3.6 V

Supports QWERTY Keypad Operation Plus

GPIO Expansion

18 GPIOs Can Be Configured into Eight Inputs

and Ten Outputs to Support an 8 × 10 Keypad

Array (80 Buttons)

DESCRIPTION/ORDERING INFORMATION

•

ESD Protection Exceeds JESD 22 on all 18

GPIO Pins and non GPIO pins

The TCA8418 is

a keypad scan device with

integrated ESD protection. It can operate from 1.65 V

to 3.6 V and has 18 general purpose inputs/outputs

(GPIO) that can be used to support up to 80 keys via

the I²C interface [serial clock (SCL), serial data

(SDA)].

–

2000-V Human Body Model (A114-A)

1000-V Charged Device Model (C101)

•

Low Standby (Idle) Current Consumption: 3 µA

Polling Current Drain 70 µA for One Key

Pressed

The key controller includes an oscillator that

debounces at 50 µs and maintains a 10 byte FIFO of

key-press and release events which can store up to

10 keys with overflow wrap capability. An interrupt

(/INT) output can be configured to alert key presses

and releases either as they occur, or at maximum

rate. Also, for the YFP package, a CAD_INT pin is

included to indicate the detection of CTRL-ALT-DEL

(i.e., 1, 11, 21) key press action.

•

10 Byte FIFO to Store 10 Key Presses and

Releases

Supports 1-MHz Fast Mode Plus I²C Bus

•

Open-Drain Active-Low Interrupt Output,

Asserted when Key is Pressed and Key is

Released

•

Minimum Debounce Time of 50 µs

The major benefit of this device is it frees up the

processor from having to scan the keypad for presses

and releases. This provides power and bandwidth

savings. The TCA8418 is also ideal for usage with

processors that have limited GPIOs.

Schmitt-Trigger Action Allows Slow Input

Transition and Better Switching Noise

Immunity at the SCL and SDA Inputs: Typical

V_hysat 1.8 V is 0.18 V

•

Latch-Up Performance Exceeds 200 mA Per

JESD 78, Class II

Very Small Packages

–

WCSP (YFP): 2 mm × 2 mm; 0.4 mm pitch

QFN (RTW): 4 mm × 4 mm; 0.5 mm pitch

ORDERING INFORMATION

T_A

–40°C to 85°C

PACKAGE⁽¹⁾⁽²⁾

ORDERABLE PART NUMBER

TOP-SIDE MARKING

PZ418

QFN – RTW

Tape and reel

TCA8418RTWR

TCA8418YFPR

WCSP – YFP

PREVIEW

(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TCA8418

SCPS215–SEPTEMBER 2009......................................................................................................................................................................................... www.ti.com

RTW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

18

17

16

15

14

13

ROW7

ROW6

ROW5

ROW4

ROW3

ROW2

COL9

COL8

COL7

COL6

COL5

COL4

YFP PACKAGE

E

D

C

B

A

E

D

C

B

A

5

4

3

2

1

2

3

4

5

(Laser Marking View)

(Bump View)

YFP Package Terminal Assignments

E

INT

SCL

SDA

V_CC

GND

COL9

COL8

COL7

COL6

4

COL5

COL4

COL3

COL2

COL1

3

COL0

ROW0

ROW1

CAD_INT

ROW2

2

ROW3

ROW4

ROW5

ROW6

ROW7

1

D

C

B

A

RESET

5

2

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TERMINAL FUNCTIONS

TERMINAL

NO.

TYPE

DESCRIPTION

NAME

QFN

(RTW)

WCSP

(YFP)

1

2

A1

B1

C1

D1

E1

A2

C2

D2

E2

A3

B3

C3

D3

E3

A4

B4

C4

D4

E4

ROW7

ROW6

ROW5

ROW4

ROW3

ROW2

ROW1

ROW0

COL0

COL1

COL2

COL3

COL4

COL5

COL6

COL7

COL8

COL9

GND

I/O

–

GPIO or row 7 in keypad matrix

GPIO or row 6 in keypad matrix

GPIO or row 5 in keypad matrix

GPIO or row 4 in keypad matrix

GPIO or row 3 in keypad matrix

GPIO or row 2 in keypad matrix

GPIO or row 1 in keypad matrix

GPIO or row 0 in keypad matrix

GPIO or column 0 in keypad matrix

GPIO or column 1 in keypad matrix

GPIO or column 2 in keypad matrix

GPIO or column 3 in keypad matrix

GPIO or column 4 in keypad matrix

GPIO or column 5 in keypad matrix

GPIO or column 6 in keypad matrix

GPIO or column 7 in keypad matrix

GPIO or column 8 in keypad matrix

GPIO or column 9 in keypad matrix

Ground

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

Active-low reset input. Connect to V_CCthrough a pullup resistor, if no active connection

is used.

20

A5

RESET

I

21

22

23

B5

C5

D5

V_CC

SDA

SCL

Pwr

I/O

I

Supply voltage of 1.65 V to 3.6 V

Serial data bus. Connect to V_CCthrough a pullup resistor.

Serial clock bus. Connect to V_CCthrough a pullup resistor.

Active-low interrupt output. Open drain structure. Connect to V_CCthrough a pullup

resistor.

24

–

E5

B2

INT

O

Active-low interrupt hardware output for 3-key simultaneous press-event. Open drain

structure. Connect to V_CCthrough a pullup resistor.

CAD_INT

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ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

–0.5

MAX

4.6

±20

50

UNIT

V

V_CC

V_I

Supply voltage range

Input voltage range⁽²⁾

Voltage range applied to any output in the high-impedance or power-off state⁽²⁾

Output voltage range in the high or low state⁽²⁾

V

V_O

V

I_IK

Input clamp current

Output clamp current

V_I< 0

mA

I_OK

V_O< 0

P port, SDA

INT

I_OL

Continuous output Low current

V_O= 0 to V_CC

25

mA

I_OH

Continuous output High current

Storage temperature range

P port

50

T_stg

–65

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

THERMAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

UNIT

RTW package

YFP package

37.8

TBD

θ_JA

Package thermal impedance⁽¹⁾

°C/W

(1) The package thermal impedance is calculated in accordance with JESD 51-7.

RECOMMENDED OPERATING CONDITIONS

MIN

1.65

MAX

UNIT

V

V_CC

V_IH

V_IL

I_OH

I_OL

T_A

Supply voltage

3.6

High-level input voltage

Low-level input voltage

High-level output current

Low-level output current

Operating free-air temperature

SCL, SDA, ROW0–7, COL0–9, RESET

ROW0–7, COL0–9

0.7 × V_CC

–0.5

3.6

V

0.3 × V_CC

V

10

25

85

mA

°C

ROW0–7, COL0–9

–40

4

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ELECTRICAL CHARACTERISTICS

over recommended operating free-air temperature range, V_CC= 1.65 V to 3.6 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CCP

MIN TYP MAX UNIT

V_IK

Input diode clamp voltage

I_I= –18 mA

1.65 V to 3.6 V –1.2

1.65 V to 3.6 V

V

V_PORPower-on reset voltage

V_I= V_CCPor GND, I_O= 0

I_OH= –1 mA

1

1.4

1.65 V

2.3 V

1.25

1.2

1.8

2.6

1.1

1.7

2.5

I_OH= –8 mA

ROW0–7, COL0–9 high-level

output voltage

V_OH

3 V

V

1.65 V

2.3 V

I_OH= –10 mA

I_OL= 1 mA

I_OL= 8 mA

3 V

1.65 V

2.3 V

0.4

0.45

0.25

0.6

ROW0–7, COL0–9 low-level

output voltage

V_OL

3 V

V

1.65 V

2.3 V

I_OL= 10 mA

0.3

3 V

0.25

SDA

I_OL

V_OL= 0.4 V

1.65 V to 3.6 V

3

mA

INT and CAD_INT

SCL, SDA, ROW0–7, COL0–9,

RESET

I_I

V_I= V_CCIor GND

1.65 V to 3.6 V

1

µA

kΩ

r_INT

ROW0–7, COL0–9

105

Oscillator

OFF

7

f_SCL= 0 kHz

Oscillator

ON

18

1.65 V

3.6 V

50

90

f_SCL= 400 kHz

f_SCL= 1 MHz

V_Ion SDA,

ROW0–7,

COL0–9 = V_CCor

GND,

I_O= 0, I/O =

inputs,

1 key press

1.65 V

3.6 V

65

153

55

I_CC

µA

f_SCL= 400 kHz

f_SCL= 1 MHz

f_SCL= 400 kHz

f_SCL= 1 MHz

GPI low

(pullup

enable)⁽¹⁾

65

15

24

GPI low

(pullup

disable)

1.65 V to 3.6 V

f_SCL= 400 kHz

f_SCL= 1 MHz

55

65

8

1 GPO

active

C_I

SCL

V_I= V_CCIor GND

V_IO= V_CCor GND

1.65 V to 3.6 V

6

pF

SDA

10 12.5

C_io

ROW0–7, COL0–9

5

6

(1) Assumes that one GPIO is enabled.

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I²C INTERFACE TIMING REQUIREMENTS

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 13)

STANDARD MODE

I²C BUS

FAST MODE

I²C BUS

FAST MODE PLUS (FM+)

I²C BUS

UNIT

MIN

0

MAX

MIN

0

MAX

MIN

0

MAX

f_scl

t_sch

t_scl

t_sp

I²C clock frequency

I²C clock high time

I²C clock low time

I²C spike time

I²C serial data setup time

I²C serial data hold time

I²C input rise time

I²C input fall time

I²C output fall time; 10 pF to 400 pF bus

100

400

1000 kHz

4

0.6

1.3

0.26

0.5

µs

4.7

50

ns

µs

t_sds

t_sdh

t_icr

250

0

100

50

0

(1)

1000 20 + 0.1C_b

300 20 + 0.1C_b

300

120

(1)

t_icf

t_ocf

I²C bus free time between Stop and

Start

I²C Start or repeater Start condition

setup time

t_buf

t_sts

4.7

1.3

0.6

0.5

µs

0.26

I²C Start or repeater Start condition hold

time

I²C Stop condition setup time

t_sth

4

0.6

0.26

µs

t_sps

Valid data time; SCL low to SDA output

valid

t_vd(data)

1

0.9

0.45

Valid data time of ACK condition; ACK

signal from SCL low to SDA (out) low

t_vd(ack)

µs

(1) C_b= total capacitance of one bus line in pF

RESET TIMING REQUIREMENTS

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 16)

STANDARD MODE, FAST

MODE, FAST MODE PLUS

(FM+)

UNIT

I²C BUS

MIN

120⁽¹⁾

MAX

t_W

Reset pulse duration

Reset recovery time

Time to reset

µs

t_REC

t_RESET

(1) The GPIO debounce circuit uses each GPIO input which passes through a two-stage register circuit. Both registers are clocked by the

same clock signal, presumably free-running, with a nominal period of 50uS. When an input changes state, the new state is clocked into

the first stage on one clock transition. On the next same-direction transition, if the input state is still the same as the previously clocked

state, the signal is clocked into the second stage, and then on to the remaining circuits. Since the inputs are asynchronous to the clock,

it will take anywhere from zero to 50 µsec after the input transition to clock the signal into the first stage. Therefore, the total debounce

time may be as long as 100 µsec. Finally, to account for a slow clock, the spec further guard-banded at 120 µsec.

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SWITCHING CHARACTERISTICS

STANDARD MODE,

FAST MODE, FAST

MODE PLUS (FM+)

PARAMETER

FROM

TO

UNIT

I²C BUS

MIN

MAX

Key event or Key

unlock or Overflow

20

60

GPI_INT with

Debounce_DIS_Low

INT

40

120

ROW0–7,

COL0–9

t_IV

Interrupt valid time

µs

GPI_INT with

Debounce_DIS_High

10

20

30

60

CAD_INT

INT, CAD_INT

INT

SCL

t_IR

Interrupt reset delay time

Output data valid

200

400

ns

CAD_INT

ROW0–7,

COL0–9

t_PV

SCL

t_PS

t_PH

Input data setup time

Input data hold time

P port

SCL

0

ns

300

KEYPAD SWITCHING CHARACTERISTICS

STANDARD MODE, FAST MODE, FAST

MODE PLUS (FM+)

I²C BUS

PARAMETER

UNIT

MIN

MAX

25

7

Key press to detection delay

Key release to detection delay

Keypad unlock timer

µs

s

Keypad interrupt mask timer

Debounce

31

60

s

ms

LOGIC DIAGRAM (POSITIVE LOGIC)

Interrupt

Control

INT

Control

Registers

and FIFO

I²C Bus

Control

SCL

SDA

Keypad

Control

ROW0–COL9

Power-On

Reset

V

CC

Oscillator

(32 kHz)

RESET

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At power on, the GPIOs (ROW0–7 and COL0–9) are configured as inputs with internal 100-kΩ pullups enabled.

However, the system master can enable the GPIOs to function as inputs, outputs or as part of the keypad matrix.

GPIOs not used for keypad control can be used to support other control features in the application.

ROW7–ROW0 are configured as inputs in GPIO mode with a push-pull structure, at power-on. In keyscan mode,

each has an open-drain structure with a 100-kΩ pullup resistor and is used as an input.

COL9–COL0 are configured as inputs in GPIO mode with a push-pull structure, at power on. In keyscan mode,

each has an open-drain structure and is used as an output.

The system master can reset the TCA8418E in the event of a timeout or other improper operation by asserting a

low in the /RESET input, while keeping the V_CCat its operating level.

A reset can be accomplished by holding the RESET pin low for a minimum of t_W. The TCA8418E registers and

I²C/SMBus state machine are changed to their default state once RESET is low (0). When RESET is high (1),

the I/O levels at the P port can be changed externally or through the master. This input requires a pull-up resistor

to VCC, if no active connection is used.

The power-on reset puts the registers in their default state and initializes the I²C/SMBus state machine. The

RESET pin causes the same reset/initialization to occur without depowering the part. The RESET pin can also be

used as a shutdown pin, if the phone is closed.

The open-drain interrupt (INT) output is used to indicate to the system master that an input state (GPI or ROWs)

has changed. INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on

this line, the remote input can inform the microcontroller if there is incoming data on its ports without having to

communicate via the I²C bus. Thus, the TCA8418E can remain a simple slave device.

The TCA8418E has key lock capability, which can trigger an interrupt at key presses and releases, if selected

Power-On Reset

When power (from 0 V) is applied to V_CC, an internal power-on reset holds the TCA8418E in a reset condition

until V_CCreaches V_POR. At that time, the reset condition is released, and the TCA8418E registers and I²C/SMBus

state machine initialize to their default states. After that, V_CCmust be lowered below 0.2 V and back up to the

operating voltage for a power-reset cycle.

Power-On Reset Requirements

In the event of a glitch or data corruption, TCA8418E can be reset to its default conditions by using the power-on

reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This

reset also happens when the device is powered on for the first time in an application.

The two types of power-on reset are shown in Figure 1 and Figure 2.

V

CC

Ramp-Up

Ramp-Down

Re-Ramp-Up

V

CC_TRR_GND

Time

Time to Re-Ramp

V

CC_RT

CC_FT

CC_RT

Figure 1. V_CCis Lowered Below 0.2 V or 0 V and Then Ramped Up to V_CC

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V

CC

Ramp-Down

Ramp-Up

V

CC_TRR_VPOR50

V

drops below POR levels

IN

Time

Time to Re-Ramp

V

CC_FT

CC_RT

Figure 2. V_CCis Lowered Below the POR Threshold, Then Ramped Back Up to V_CC

Table 1 specifies the performance of the power-on reset feature for TCA8418E for both types of power-on reset.

Table 1. RECOMMENDED SUPPLY SEQUENCING AND RAMP RATES⁽¹⁾

PARAMETER

MIN TYP

1

MAX UNIT

V_{CC_FT}

Fall rate

See Figure 1

See Figure 2

100

ms

V_{CC_RT}

Rise rate

0.01

V_{CC_TRR_GND}

V_{CC_TRR_POR50}

Time to re-ramp (when V_CCdrops to GND)

0.001

Time to re-ramp (when V_CCdrops to V_{POR_MIN}– 50 mV)

Level that V_CCPcan glitch down to, but not cause a functional

disruption when V_{CCX_GW}= 1 µs

V_{CC_GH}

V_{CC_GW}

See Figure 3

1.2

V

Glitch width that will not cause a functional disruption when

V_{CCX_GH}= 0.5 × V_CCx

µs

V_PORF

V_PORR

Voltage trip point of POR on falling V_CC

Voltage trip point of POR on rising V_CC

0.767

1.033

1.144

1.428

V

(1) T_A= –40°C to 85°C (unless otherwise noted)

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width

(V_{CC_GW}) and height (V_{CC_GH}) are dependent on each other. The bypass capacitance, source impedance, and

device impedance are factors that affect power-on reset performance. Figure 3 and Table 1 provide more

information on how to measure these specifications.

V

CC

V

CC_GH

Time

V

CC_GW

Figure 3. Glitch Width and Glitch Height

V_PORis critical to the power-on reset. V_PORis the voltage level at which the reset condition is released and all the

registers and the I²C/SMBus state machine are initialized to their default states. The value of V_PORdiffers based

on the V_CCbeing lowered to or from 0. Figure 4 and Table 1 provide more details on this specification.

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V

CC

V

POR

V

PORF

Time

POR

Time

Figure 4. V_POR

For proper operation of the power-on reset feature, use as directed in the figures and table above.

Interrupt Output

An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time t_iv, the signal

INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or

data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge

(ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the

ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse.

Each change of the I/Os after resetting is detected and is transmitted as INT.

Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output

cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the

state of the pin does not match the contents of the input port register.

The INT output has an open-drain structure and requires a pullup resistor to V_CCdepending on the application. If

the INT signal is connected back to the processor that provides the SCL signal to the TCA64xxA, then the INT

pin has to be connected to V_CC. If not, the INT pin can be connected to V_CCP

.

For more information on the interrupt output feature, see Control Register and Command Byte and Typical

Applications.

50 Micro-second Interrupt Configuration

The TCA8418 provides the capability of deasserting the interrupt for 50 µs while there is a pending event. When

the INT_CFG bit in Register 0x01 is set, any attempt to clear the interrupt bit while the interrupt pin is already

asserted results in a 50 µs deassertion. When the INT_CFG bit is cleared, processor interrupt remains asserted

if the host tries to clear the interrupt. This feature is particularly useful for software development and edge

triggering applications.

I²C Interface

The bidirectional I²C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be

connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data

transfer may be initiated only when the bus is not busy.

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I²C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on

the SDA input/output, while the SCL input is high (see Figure 5). After the Start condition, the device address

byte is sent, most significant bit (MSB) first, including the data direction bit (R/W).

After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA

input/output during the high of the ACK-related clock pulse. The address (ADDR) input of the slave device must

not be changed between the Start and the Stop conditions.

On the I²C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control

commands (Start or Stop) (see Figure 6).

A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the

master (see Figure 5).

Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop

conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before

the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK

clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see

Figure 7). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,

the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold

times must be met to ensure proper operation.

A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after

the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.

In this event, the transmitter must release the data line to enable the master to generate a Stop condition.

SDA

SCL

S

P

Stop Condition

Start Condition

Figure 5. Definition of Start and Stop Conditions

SDA

SCL

Data Line

Change

Figure 6. Bit Transfer

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Data Output

by Transmitter

NACK

Data Output

by Receiver

ACK

SCL From

Master

1

2

8

9

S

Clock Pulse for

Acknowledgment

Start

Condition

Figure 7. Acknowledgment on the I²C Bus

Device Address

The address of the TCA8418E is shown in Table 2.

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Table 2.

BIT

BYTE

7 (MSB)

6

5

4

3

2

1

0 (LSB)

I²C slave address

0

1

0

1

0

R/W

The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read

operation, while a low (0) selects a write operation.

Control Register and Command Byte

Following the successful acknowledgment of the address byte, the bus master sends a command byte, which is

stored in the control register in the TCA8418E. The command byte indicates the register that will be updated with

information. All registers can be read and written to by the system master.

Table 3 shows all the registers within this device and their descriptions. The default value in all registers is 0.

Table 3. Register Descriptions

REGISTER

DESCRIPTION

ADDRESS

REGISTER NAME

7

6

5

4

3

2

1

0

0×00

Reserved

Configuration register

(interrupt processor

interrupt enables)

OVR_F

LOW_I

EN

GPI_E_ OVR_FL

INT_

CFG

K_LC GPI_IE

0×01

0×02

CFG

AI

KE_IEN

K_ INT

CGF

OW_M

K_IEN

N

OVR_F

LOW_I

NT

N/A

0

N/A

0

N/A

0

K_LC

K_INT

GPI_

INT

INT_STAT

Interrupt status register

N/A 0

Key lock and event

counter register

N/A

0

K_LCK

_EN

KLEC

2

0×03

0×04

0×05

0×06

0×07

0×08

0×09

0×0A

0×0B

0×0C

0×0D

0×0E

0×0F

0×10

0×11

0×12

KEY_LCK_EC

KEY_EVENT_A

KEY_EVENT_B

KEY_EVENT_C

KEY_EVENT_D

KEY_EVENT_E

KEY_EVENT_F

KEY_EVENT_G

KEY_EVENT_H

KEY_EVENT_I

KEY_EVENT_J

KP_LCK_TIMER

Unlock1

LCK2

LCK1

KLEC3

KLEC1 KLEC0

KEA7

0

KEA6

0

KEA5

0

KEA4

0

KEA3

0

KEA2

0

KEA1

0

KEA0

0

Key event register A

Key event register B

Key event register C

Key event register D

Key event register E

Key event register F

Key event register G

Key event register H

Key event register I

Key event register J

KEB7

0

KEB6

0

KEB5

0

KEB4

0

KEB3

0

KEB2

0

KEB1

0

KEB0

0

KEC7

0

KEC6

0

KEC5

0

KEC4

0

KEC3 KEC2 KEC1

KEC0

0

KED7

0

KED6

0

KED5

0

KED4

0

KED3 KED2 KED1

KED0

0

KEE7

0

KEE6

0

KEE5

0

KEE4

0

KEE3

0

KEE2

0

KEE1

0

KEE0

0

KEF7

0

KEF6

0

KEF5

0

KEF4

0

KEF3

0

KEF2

0

KEF1

0

KEF0

0

KEG7

0

KEG6

0

KEG5

0

KEG4

0

KEG3 KEG2 KEG1

KEG0

0

KEH7

0

KEH6

0

KEH5

0

KEH4

0

KEH3 KEH2 KEH1

KEH0

0

KEI7

0

KEI6

0

KEI5

0

KEI4

0

KEI3

0

KEI2

0

KEI1

0

KEI0

0

KEJ7

0

KEJ6

0

KEJ5

0

KEJ64

0

KEJ3

0

KEJ2

0

KEJ1

0

KEJ0

0

Keypad lock 1 to lock 2

timer

KL7

KL6

KL5

KL4

KL3

KL2

KL1

KL0

UK1_

2

Unlock key 1

Unlock key2

UK1_7 UK1_6

UK2_7 UK2_6

UK1_5

UK2_5

UK1_4 UK1_3

UK2_4 UK2_3

UK1_1 UK1_0

UK2_1 UK2_0

UK2_

2

Unlock2

R7IS

0

R6IS

0

R5IS

0

R4IS

0

R3IS

0

R2IS

0

R1IS

0

R0IS

0

GPIO_INT_STAT1

GPIO_INT_STAT2

GPIO interrupt status

C7IS

0

C6IS

0

C5IS

0

C4IS

0

C3IS

0

C2IS

0

C1IS

0

C0IS

0

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Table 3. Register Descriptions (continued)

REGISTER

DESCRIPTION

ADDRESS

0×13

REGISTER NAME

7

6

5

4

3

2

1

0

N/A

0

N/A

0

N/A

0

N/A

0

N/A

0

N/A

0

C9IS

0

C8IS

0

GPIO_INT_STAT3

GPIO interrupt status

GPIO_DAT_STAT1

(read twice to clear)

0×14

GPIO data status

GPIO data out

R7DS

C7DS

R6DS

C6DS

R5DS

C5DS

R4DS

C4DS

R3DS R2DS R1DS

C3DS C2DS C1DS

R0DS

C0DS

C8DS

GPIO_DAT_STAT2

(read twice to clear)

0×15

GPIO_DAT_STAT3

(read twice to clear)

N/A

0

N/A

0

N/A

0

N/A

0

N/A

0

N/A

0

0×16

C9DS

R7DO

0

R6DO

0

R5DO

0

R4DO

0

R3DO R2DO R1DO

R0DO

0

0×17

GPIO_DAT_OUT1

GPIO_DAT_OUT2

GPIO_DAT_OUT3

GPIO_INT_EN1

GPIO_INT_EN2

GPIO_INT_EN3

0

C7DO

0

C6DO

0

C5DO

0

C4DO

0

C3DO C2DO C1DO

C0DO

0

0×18

GPIO data out

0

N/A

0

N/A

0

N/A

0

N/A

0

N/A

0

N/A

0

C9DO

0

C8DO

0

0×19

GPIO data out

R7IE

0

R6IE

0

R5IE

0

R4IE

0

R3IE

0

R2IE

0

R1IE

0

R0IE

0

0×1A

0×1B

0×1C

GPIO interrupt enable

C7IE

0

C6IE

0

C5IE

0

C4IE

0

C3IE

0

C2IE

0

C1IE

0

C0IE

0

N/A

0

N/A

0

N/A

0

N/A

0

N/A

0

N/A

0

C9IE

0

C8IE

0

Keypad or GPIO

selection

ROW7 ROW6

ROW5

0

ROW4 ROW3 ROW2 ROW1 ROW0

0×1D

0×1E

0×1F

KP_GPIO1

KP_GPIO2

KP_GPIO3

0: GPIO

0

1: KP matrix

Keypad or GPIO

selection

COL7

0

COL6

0

COL5

0

COL4

0

COL3 COL2 COL1

COL0

0

0: GPIO

0

1: KP matrix

Keypad or GPIO

selection

N/A

0

N/A

0

N/A

0

N/A

0

N/A

0

N/A

0

COL9

0

COL8

0

0: GPIO

1: KP matrix

ROW7 ROW6

ROW5

0

ROW4 ROW3 ROW2 ROW1 ROW0

0×20

0×21

0×22

GPI_EM1

GPI_EM2

GPI_EM3

GPI event mode 1

GPI event mode 2

GPI event mode 3

0

COL7

0

COL6

0

COL5

0

COL4

0

COL3 COL2 COL1

COL0

0

N/A

0

N/A

0

N/A

0

N/A

0

N/A

0

N/A

0

COL9

0

COL8

0

GPIO data direction

0: input

R7DD

0

R6DD

0

R5DD

0

R4DD

0

R3DD R2DD R1DD

R0DD

0

0×23

0×24

0×25

0×26

0×27

GPIO_DIR1

GPIO_DIR2

0

1: output

GPIO data direction

0: input

C7DD

0

C6DD

0

C5DD

0

C4DD

0

C3DD C2DD C1DD

C0DD

0

1: output

GPIO data direction

0: input

N/A

0

N/A

0

N/A

0

N/A

0

N/A

0

N/A

0

C9DD

0

C8DD

0

GPIO_DIR3

1: output

GPIO edge/level detect

R7IL

0

R6IL

0

R5IL

0

R4IL

0

R3IL

0

R2IL

0

R1IL

0

R0IL

0

GPIO_INT_LVL 1

GPIO_INT_LVL 2

0: low

1: high

GPIO edge/level detect

C7IL

0

C6IL

0

C5IL

0

C4IL

0

C3IL

0

C2IL

0

C1IL

0

C0IL

0

0: low

1: high

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Table 3. Register Descriptions (continued)

REGISTER

DESCRIPTION

ADDRESS

REGISTER NAME

7

6

5

4

3

2

1

0

GPIO edge/level detect

N/A

0

N/A

0

N/A

0

N/A

0

N/A

0

N/A

0

C9IL

0

C8IL

0

0×28

GPIO_INT_LVL 3

0: low

1: high

Debounce disable

R7DD

0

R6DD

0

R5DD

0

R4DD

0

R3DD R2DD R1DD

R0DD

0

0×29

0×2A

0×2B

0×2C

0×2D

DEBOUNCE_DIS 1 0: enabled

1: disabled

0

Debounce disable

C7DD

0

C6DD

0

C5DD

0

C4DD

0

C3DD C2DD C1DD

C0DD

0

DEBOUNCE_DIS 2 0: enabled

1: disabled

0

Debounce disable

N/A

0

N/A

0

N/A

0

C9DD

0

C8DD

0

DEBOUNCE_DIS 3 0: enabled

1: disabled

Debounce time bits

GPIO pullup

R7PD

0

R6PD

0

R5PD

0

R4PD

0

R3PD R2PD R1PD

R0PD

0

GPIO_PULL1

GPIO_PULL2

0: pullup enabled

1: pullup disabled

0

GPIO pullup

0: pullup enabled

1: pullup disabled

C7PD

0

C6PD

0

C5PD

0

C4PD

0

C3PD C2PD C1PD

C0PD

0

GPIO pullup

0: pullup enabled

1: pullup disabled

N/A

0

N/A

0

N/A

0

N/A

0

N/A

0

N/A

0

C9PD

0

C8PD

0

0×2E

0×2F

GPIO_PULL3

Reserved

Configuration Register (Address 0×01)

BIT

NAME

DESCRIPTION

Auto-increment for read and write operations

7

AI

0 = disabled

1 = enabled

GPI event mode configuration

6

5

GPI_E_CFG

0 = GPI events are tracked when keypad is locked

1 = GPI events are not tracked when keypad is locked

Overflow mode

OVR_FLOW_M

0 = disabled; overflow data is lost

1 = enabled.

Overflow data shifts with last event pushing first event out interrupt configuration.

0 = processor interrupt remains asserted (or low) if host tries to clear interrupt while there is

still a pending key press, key release or GPI interrupt

4

INT_CFG

1 = processor interrupt is deasserted for 50 µs and reassert with pending interrupts

Overflow interrupt enable

0 = disabled

3

2

OVR_FLOW_IEN

K_LCK_IEN

1 = enabled

Keypad lock interrupt enable

0 = disabled

1 = enabled

GPI interrupt enable to host processor

0 = disabled

1

GPI_IEN

1 = enabled

Can be used to mask interrupts

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BIT

NAME

DESCRIPTION

Key events interrupt enable to host processor

0

KE_IEN

0 = disabled

1 = enabled Can be used to mask interrupts

Bit 7 in this register is used to determine the programming mode. If it is low, all data bytes are written to the

registers defined command byte. If bit 7 is high, the value of the command byte is automatically incremented

after the byte is written, and the next data byte is stored in the corresponding register. Registers are written in

the sequence shown in Table 3. Once the GPIO_PULL3 register (0×2E) is written to, the command byte returns

to 0 (Configuration register). Registers 0 and 2F are reserved and a command byte that references these

registers is not acknowledged by the TCA8418E.

The keypad lock interrupt enable determines if the interrupt pin is asserted when the key lock interrupt (see

Interrupt Status Register) bit is set.

Interrupt Status Register, INT_STAT (Address 0×02)

BIT

7

NAME

N/A

DESCRIPTION

Always 0

6

N/A

5

N/A

CTRL-ALT-DEL key sequence status. Requires writing a 1 to clear interrupts.

0 = interrupt not detected

4

3

CAD_INT

1 = interrupt detected

Overflow interrupt status. Requires writing a 1 to clear interrupts.

0 = interrupt not detected

OVR_FLOW_INT

1 = interrupt detected

Keypad lock interrupt status. This is the interrupt to the processor when the keypad lock

sequence is started. Requires writing a 1 to clear interrupts.

2

K_LCK_INT

0 = interrupt not detected

1 = interrupt detected

GPI interrupt status. Requires writing a 1 to clear interrupts.

0 = interrupt not detected

1

0

GPI_INT

K_INT

1 = interrupt detected

Can be used to mask interrupts

Key events interrupt status. Requires writing a 1 to clear interrupts.

0 = interrupt not detected

1 = interrupt detected

Key Lock and Event Counter Register, KEY_LCK_EC (Address 0×03)

BIT

NAME

DESCRIPTION

7

N/A

Always 0

Key lock enable

0 = disabled

1 = enabled

6

5

4

K_LCK_EN

LCK2

Keypad lock status

0 = unlock (if LCK1 is 0 too)

1 = locked (if LCK1 is 1 too)

Keypad lock status

LCK1

0 = unlock (if LCK2 is 0 too)

1 = locked (if LCK2 is 1 too)

3

2

KEC3

KEC2

Key event count, Bit 3

Key event count, Bit 2

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BIT

1

NAME

KEC1

KEC0

DESCRIPTION

Key event count, Bit 1

Key event count, Bit 0

0

KEC[3:0]: indicates how many registers have values in it. For example, KS(0000) = 0 events, KS(0001) = 1 event

and KS(1010) = 10 events. As interrupts happen (press or release), the count increases accordingly.

Key Event Registers (FIFO), KEY_EVENT_A–J (Address 0×04–0×0D)

BIT

ADDRESS

REGISTER NAME⁽¹⁾

REGISTER DESCRIPTION

7

6

5

4

3

2

1

0

KEA

7

0

KEA

5

0

KEA

2

0

KEA

0

KEA6

0

KEA4 KEA3

KEA1

0

0×04

KEY_EVENT_A

Key event register A

0

(1) Only KEY_EVENT_A register is shown

These registers – KEY_EVENT_A-J – function as a FIFO stack which can store up to 10 key presses and

releases. The user first checks the INT_STAT register to see if there are any interrupts. If so, then the Key Lock

and Event Counter Register (KEY_LCK_EC, register 0x03) is read to see how many interrupts are stored. The

INT_STAT register is then read again to ensure no new events have come in. The KEY_EVENT_A register is

then read as many times as there are interrupts. Each time a read happens, the count in the KEY_LCK_EC

register reduces by 1. The data in the FIFO also moves down the stack by 1 too (from KEY_EVENT_J to

KEY_EVENT_A). Once all events have been read, the key event count is at 0 and then KE_INT bit can be

cleared by writing a ‘1’ to it.

In the KEY_EVENT_A register, KEA[6:0] indicates the key # pressed or released. A value of 0 to 80 indicate

which key has been pressed or released in a keypad matrix. Values of 97 to 114 are for GPI events.

Bit 7 or KEA[7] indicate if a key press or key release has happened. A ‘0’ means a key release happened. A ‘1’

means a key has been pressed (which can be cleared on a read).

For example, 3 key presses and 3 key releases are stored as 6 words in the FIFO. As each word is read, the

user knows if it is a key press or key release that occurred. Key presses such as CTRL+ALT+DEL are stored as

3 simultaneous key presses. Key presses and releases generate key event interrupts. The KE_INT bit and /INT

pin will not cleared until the FIFO is cleared of all events.

All registers can be read but for the purpose of the FIFO, the user should only read KEY_EVENT_A register.

Once all the events in the FIFO have been read, reading of KEY_EVENT_A register will yield a zero value.

Keypad Lock1 to Lock2 Timer Register, KP_LCK_TIMER (Address 0×0E)

BIT

ADDRESS

REGISTER NAME⁽¹⁾

REGISTER DESCRIPTION

7

6

5

4

3

2

1

0

0×0E

KP_LCK_TIMER

Keypad lock 1 to lock 2 timer

KL7

KL6

KL5

KL4

KL3

KL2

KL1

KL0

(1) Only KEY_EVENT_A register is shown

KL[2:0] are for the Lock1 to Lock2 timer

KL[7:3] are for the interrupt mask timer

The interrupt mask timer should be set for the time it takes for the LCD to dim or turn off.

Unlock1 and Unlock2 Registers, UNLOCK1/2 (Address o0×0F)

BIT

ADDRESS

REGISTER NAME⁽¹⁾

REGISTER DESCRIPTION

Unlock key 1

Unlock key 2

7

6

5

4

3

2

1

0

UK1_ UK1_ UK1 UK1_ UK1_ UK1 UK1_ UK1

_5 _2 _0

0×0F

0×10

Unlock1

Unlock2

7

6

4

3

1

UK2_ UK2_ UK2 UK2_ UK2_ UK2 UK2_ UK2

7

6

_5

4

3

_2

1

_0

(1) Only KEY_EVENT_A register is shown

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UK1[6:0] contains the key number used to unlock key 1

UK2[6:0] contains the key number used to unlock key 2

A ‘0’ in either register means it is disabled. It lasts up to 7 seconds. Needs a second timer up to 31 seconds?

The keypad lock interrupt mask timer generates a first interrupt (K_INT) and then waits for a programmed time

before generating a second interrupt. A second interrupt can only be generated when a timer is enabled due to

an unlock sequence being pressed. The second interrupt is a key lock interrupt. When the interrupt mask timer is

disabled (‘0’), a key lock interrupt will trigger only when the correct and complete unlock sequence is completed.

GPIO Interrupt Status Registers, GPIO_INT_STAT1–3 (Address 0×11–0×13)

These registers are used to check GPIO interrupt status and are cleared on read.

GPIO Data Status Registers, GPIO_DAT_STAT1–3 (Address 0×14–0×16)

These registers show GPIO state when read for inputs and outputs.

GPIO Data Out Registers, GPIO_DAT_OUT1–3 (Address 0×17–0×19)

These registers contain GPIO data to be written to GPIO out driver; inputs are not affected. This is needed so

that the value can be written prior to being set as an output.

GPIO Interrupt Enable Registers, GPIO_INT_EN1–3 (Address 0×1A–0×1C)

These registers enable interrupts for GP inputs only.

Keypad or GPIO Selection Registers, KP_GPIO1–3 (Address 0×1D–0×1F)

A bit value of '0' in any of the unreserved bits puts the corresponding pin in GPIO mode. A '1' in any of these bits

puts the pin in keyscan mode and configured as a row or column accordingly.

GPI Event Mode Registers, GPI_EM1–3 (Address 0×20–0×22)

A bit value of '0' in any of the unreserved bits indicates that it is not part of the event FIFO. A '1' in any of these

bits means it is part of the event FIFO. GPIO Data Direction Registers (GPIO_DIR1-3, Register address of

0x23-0x25) A bit value of '0' in any of the unreserved bits sets the corresponding pin as an input. A '1' in any of

these bits sets the pin as an output. GPIO Edge/Level Detect Registers (GPIO_INT_LVL1-3, Register address of

0x26-0x28) A bit value of '0' indicates that interrupt will be triggered on a high-to-low transition for the inputs in

GPIO mode. A bit value of '1' indicates that interrupt will be triggered on a low-to-high value for the inputs in

GPIO mode.

GPIO Data Direction Registers, GPIO_DIR1–3 (Address 0×23–0×25)

A bit value of '0' in any of the unreserved bits sets the corresponding pin as an input. A '1' in any of these bits

sets the pin as an output. GPIO Edge/Level Detect Registers (GPIO_INT_LVL1-3, Register address of

0x26-0x28) A bit value of '0' indicates that interrupt will be triggered on a high-to-low transition for the inputs in

GPIO mode. A bit value of '1' indicates that interrupt will be triggered on a low-to-high value for the inputs in

GPIO mode.

GPIO Edge/Level Detect Registers, GPIO_INT_LVL1–3 (Address 0×26–0×28)

A bit value of '0' indicates that interrupt will be triggered on a high-to-low transition for the inputs in GPIO mode.

A bit value of '1' indicates that interrupt will be triggered on a low-to-high value for the inputs in GPIO mode.

Debounce Disable Registers, DEBOUNCE_DIS1–3 (Address 0×29–0×2B)

This is for pins configured as inputs. A bit value of ‘0’ in any of the unreserved bits disables the debounce while a

bit value of ‘1’ enables the debounce.

In register DEBOUNCE_DIS3 [7:5] can be used to program the value of the debounce time.

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BIT

ADDRESS

REGISTER NAME⁽¹⁾

REGISTER DESCRIPTION

7

6

5

4

3

2

1

0

Debounce disable

0: enabled

C8D

D

0

N/A

0

N/A

0

N/A C9DD

0×2B

DEBOUNCE_DIS 3

debounce time bits

0

1: disabled

(1) Only KEY_EVENT_A register is shown

DEBOUNCE ENABLED

50 ms

GPI with INTE

INT

VALID HIGH TRIGGER INTERRUPT

VALID LOW TRIGGER INTERRUPT

DEBOUNCE ENABLED

GPI with INTE

INT

VALID HIGH TRIGGER INTERRUPT

VALID LOW TRIGGER INTERRUPT

Debounce disable will have the same effect for GPI mode or for rows in keypad scanning mode. The reset line

always has a 50-µs debounce time.

The debounce time for inputs is the time required for the input to be stable to be noticed. This time is 50 µs.

The debounce time for the keypad is for the columns only. The minimum time is 20 ms. All columns are scanned

once every 20 ms to detect any key presses. Two full scans are required to see if any keys were pressed. If the

first scan is done just after a key press, it will take 20 ms to detect the key press. If the first scan is down much

later than the key press, it will take 40 ms to detect a key press.

GPIO Pull Disable Register, GPIO_PULL1–3 (Address 0×2C–0×2E)

This register enables or disables pullup registers from inputs.

Typical Application

Figure 8 shows an application in which the TCA8418E can be used.

placeholder

Figure 8. Typical Application

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COL COL COL COL COL COL COL COL COL COL

X0

X1

X2

X3

X4

X5

X6

X7

X0

X1

X2

X3

X4

X5

X6

X7

X0

X1

X2

X3

X4

X5

X6

X7

X0

X1

X2

X3

X4

X5

X6

X7

X0

X1

X2

X3

X4

X5

X6

X7

X0

X1

X2

X3

X4

X5

X6

X7

X0

X1

X2

X3

X4

X5

X6

X7

X0

X1

X2

X3

X4

X5

X6

X7

X0

X1

X2

X3

X4

X5

X6

X7

ROW

X1

X2

X3

X4

X5

X6

X7

The 18 GPIOs can be configured to support up to 80 keys. The GPIOs are programmed into rows (maximum of

8) and columns (maximum of 10) to support a keypad. This is done through writing to “Keypad or GPIO

Selection” registers (0x1D – 0x1F). The keypad in idle mode will be configured as Columns being driven low and

Rows as inputs with pull-ups.

When there is a key press or multiple key presses (Short between Column and Row), it will trigger an internal

state machine interrupt. The row that has a pressed key can be determined through reading the “GPIO Data

Status” registers (0x14-0x16).After that, the state machine starts a keyscan cycle to determine the column of the

key that was pressed. The state machine sets one column as an output low and all other columns as high. The

state machine will then walk a zero across the applicable row to determine what keys are being pressed.

Once a key has been pressed for 10ms, the state machine will set the appropriate key/s in the Key Event Status

register with the key-pressed bit set (bit 7). If the K_IEN is set it will then set KE_INT and generate an interrupt to

the host processor. The state machine will continue to poll while there are keys pressed. If a key/s that was in

the key pressed register is released for 10ms or greater, the state machine will set the appropriate keys in the

Key Event Status register with the key pressed bit cleared. If K_IEN is set it will set the K_INT and generate an

interrupt to the host processor.

After receiving an interrupt, the host processor will first read the Interrupt Status register to determine what

interrupt caused the processor interrupt. It will then read the Key Event Register to see what keys where

pressed/released (Bits will then automatically clear on read in those registers). The processor will then write a 1

to the interrupt bit in the interrupt register to clear it and release the host interrupt to the processor. The

processor can see the status of what keys are pressed at any point by reading the KEY_EVENT_A register

(FIFO).

See Key Event Registers (FIFO) for more information.

When all Key_Event Registers are full, any additional events with set the OVR_FLOW_INT bit to 1. This will also

trigger an interrupt to the processor. When the FIFO is not full, new events are added to the next empty

Key_Event register in line. The OVR_FLOW_M bit sets the mode of operation during overflows. Clearing this bit

will cause new incoming events to be ignored and discarded. Setting this bit will overwrite old data with new data

starting with the first event.

20

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Keypad Lock/Unlock

This user can lock the keypad through the lock/unlock feature in this device. Once the keypad is locked, it can

prevent the generation of key event interrupts and recorded key events. The unlock keys can be programmed

with any value of the keys in the keypad matrix or any GPI values that are part of the key event table. When the

keypad lock interrupt mask timer is enabled, the user will need to press two specific keys before an keylock

interrupt is generated or keypad events are recorded. After the keypad is locked, a key event interrupt is

generated any time a user presses a key. This first interrupt also triggers the processor to turn on the LCD and

display the unlock message. The processor will then read the lock status register to see if the keypad is

unlocked. The next interrupt (keylock interrupt) will not be generated unless both unlock keys sequences are

correct. If correct Unlock keys are not pressed before the mask timer expires, the state machine will start over

again.

Ghosting

Supports multiple key presses accurately. Applications requiring three-key combinations (such as

<Ctrl><Alt><Del>) must ensure that the three keys are wired in appropriate key positions to avoid ghosting (or

appearing like a 4th key has been pressed)

GPI Events

A column or row configured as GPI can be programmed to be part of the Key Event Table, hence becomes also

capable of generating Key Event Interrupt. A key Event Interrupt caused by a GPI follow the same process flow

as a Key Event Interrupt caused by a Key press.

GPIs configured as part of the Key Event Table allows for single key switches to be monitored as well as other

GPI interrupts. As part of the Event Table, GPIs are represented with decimal value of 97 (0x61 or 1100001) and

run through decimal value of 114 (0x72 or 1110010).

For a GPI that is set as active high, and is enabled in the Key Event Table, the state-machine will add an event

to the event count and event table whenever that GPI goes high. If the GPI is set to active low, a transition from

high to low will be considered a press and will also be added to the event count and event table. Once the

interrupt state has been met, the state machine will internally set an interrupt for the opposite state programmed

in the register to avoid polling for the released state, hence saving current. Once the released state is achieved,

it will add it to the event table. The press and release will still be indicated by bit 7 in the event register.

The GPI Events can also be used as unlocked sequences. When the GPI_EM bit is set, GPI events will not be

tracked when the keypad is locked. GPI_EM bit must be cleared for the GPI events to be tracked in the event

counter and table when the keypad is locked.

Bus Transactions

Data is exchanged between the master and TCA8418E through write and read commands.

Writes

Data is transmitted to the TCA8418E by sending the device address and setting the least significant bit (LSB) to

a logic 0. The command byte is sent after the address and determines which register receives the data that

follows the command byte. There is no limitation on the number of data bytes sent in one write transmission.

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SCL

SDA

1

2

3

4

5

6

7

8

9

Command Byte

Slave Address

Data to Port

Data 1

AD

DR

S

0

1

0

A

0

1

0

A

0.0 A

P

Start Condition

Acknowledge

From Slave

Acknowledge

From Slave

Acknowledge

From Slave

R/W

Write to Port

Data Out

from Port

Data Valid

t_pv

Figure 9. Write to Output Port Register

SCL

9

1

2

3

4

5

6

7

8

Data to Register

Data

Slave Address

Command Byte

AD

DR

1

SDA

S

0

1

0

A

0

1

A

P

Start Condition

Acknowledge

From Slave

Acknowledge

From Slave

Acknowledge

From Slave

R/W

Figure 10. Write to Configuration or Polarity Inversion Register

Reads

The bus master first must send the TCA8418E address with the LSB set to a logic 0. The command byte is sent

after the address and determines which register is accessed. After a restart, the device address is sent again

but, this time, the LSB is set to a logic 1. Data from the register defined by the command byte then is sent by the

TCA8418E (see Figure 11 and Figure 12). Data is clocked into the register on the rising edge of the ACK clock

pulse.

Data From Lower

or Upper Byte

of Register

Acknowledge

From Slave

Acknowledge

From Slave

Acknowledge

From Slave

Acknowledge

From Master

Slave Address

AD

DR

AD

DR

Command Byte

S

0

1

0

A

S

0

1

0

1

A

Data

A

First Byte

R/W

At this moment, master transmitter

becomes master receiver, and

slave receiver becomes slave transmitter.

Data From Upper

or Lower Byte

of Register

No Acknowledge

From Master

MS

LS NA P

Data

Last Byte

Figure 11. Read From Register

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1

2

3

4

5

6

7

8

9

SCL

SDA

Data from Port

Data 1

Data from Port

Data 4

AD

DR

S

0

1

0

1

A

1

A

A P

R/W

Acknowledge

From Slave

Acknowledge

From Master

Acknowledge

From Master

Read From

Port

Data Into

Port

INT

t_iv

t_ir

Figure 12. Read From Input Port Register

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TYPICAL CHARACTERISTICS

T_A= 25°C (unless otherwise noted)

SUPPLY CURRENT

vs

TEMPERATURE

STANDBY SUPPLY CURRENT

vs

TEMPERATURE

12

11

10

9

1600

1400

1200

1000

800

600

400

200

0

V_CC= 3.6 V

V_CC= 3.3 V

8

V_CC= 3.6 V

7

V_CC= 3.3 V

V_CC= 2.5 V

6

V_CC= 2.5 V

5

4

V_CC= 1.8 V

3

V_CC= 1.65 V

2

1

0

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature, T_A(°C)

SUPPLY CURRENT

vs

SUPPLY VOLTAGE

I/O SINK CURRENT

vs

OUTPUT LOW VOLTAGE

11

10

9

60

V_CC= 1.65 V

50

40

30

20

10

0

T_A= -40°C

8

T_A= 25°C

T_A= 85°C

7

6

5

4

3

2

1

0

1.6

2.0

2.4

2.8

3.2

3.6

0.0

0.1

0.2

0.3

0.4

0.5

0.6

Supply Voltage, V_CC(V)

Output Low Voltage, V_OL(V)

24

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TYPICAL CHARACTERISTICS (continued)

T_A= 25°C (unless otherwise noted)

I/O SINK CURRENT

vs

OUTPUT LOW VOLTAGE

I/O SINK CURRENT

vs

OUTPUT LOW VOLTAGE

70

60

50

40

30

20

10

0

100

80

60

40

20

0

V_CC= 1.8 V

V_CC= 2.5 V

T_A= -40°C

T_A= 25°C

T_A= -40°C

T_A= 25°C

T_A= 85°C

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.0

0.1

0.2

0.3

0.4

0.5

0.6

Output Low Voltage, V_OL(V)

I/O SINK CURRENT

vs

OUTPUT LOW VOLTAGE

I/O SINK CURRENT

vs

OUTPUT LOW VOLTAGE

120

100

80

60

40

20

0

140

120

100

80

V_CC= 3.6 V

V_CC= 3.3 V

T_A= -40°C

T_A= 25°C

T_A= 85°C

T_A= -40°C

T_A= 25°C

T_A= 85°C

60

40

20

0

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.0

0.1

0.2

0.3

0.4

0.5

0.6

Output Low Voltage, V_OL(V)

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TYPICAL CHARACTERISTICS (continued)

T_A= 25°C (unless otherwise noted)

I/O LOW VOLTAGE

vs

TEMPERATURE

I/O SOURCE CURRENT

vs

OUTPUT HIGH VOLTAGE

120

90

60

30

0

20

15

10

5

V_CC= 1.65 V

T_A= -40°C

T_A= 25°C

V_CC= 1.8 V, I_OL= 10 mA

T_A= 85°C

V_CC= 3.3 V, I_OL= 10 mA

V_CC= 1.8 V, I_OL= 1 mA

V_CC= 3.3 V, I_OL= 1 mA

0

-40

-15

10

35

60

85

0.0

0.1

0.2

0.3

0.4

0.5

0.6

Temperature, T_A(°C)

V_CCP- V_OH(V)

I/O SOURCE CURRENT

vs

OUTPUT HIGH VOLTAGE

I/O SOURCE CURRENT

vs

OUTPUT HIGH VOLTAGE

24

18

12

6

36

27

18

9

V_CC= 1.8 V

V_CC= 2.5 V

T_A= -40°C

T_A= 25°C

T_A= -40°C

T_A= 25°C

T_A= 85°C

0

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.0

0.1

0.2

0.3

V_CCP- V_OH(V)

0.4

0.5

0.6

V_CCP- V_OH(V)

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TYPICAL CHARACTERISTICS (continued)

T_A= 25°C (unless otherwise noted)

I/O SOURCE CURRENT

vs

OUTPUT HIGH VOLTAGE

I/O SOURCE CURRENT

vs

OUTPUT HIGH VOLTAGE

44

33

22

11

0

44

33

22

11

0

V_CC= 3.6 V

V_CC= 3.3 V

T_A= -40°C

T_A= 25°C

T_A= -40°C

T_A= 25°C

T_A= 85°C

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.0

0.1

0.2

0.3

0.4

0.5

0.6

V_CCP- V_OH(V)

I/O HIGH VOLTAGE

vs

TEMPERATURE

350

300

250

200

150

100

50

V_CC= 1.8 V, I_OH= -10 mA

V_CC= 3.3 V, I_OH= -10 mA

0

-40

-15

10

35

60

85

Temperature, T_A(°C)

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PARAMETER MEASUREMENT INFORMATION

V

CCI

R

= 1 kW

L

SDA

DUT

C

= 50 pF

L

(see Note A)

SDA LOAD CONFIGURATION

Two Bytes for READ Input Port Register

(see Figure 9)

Stop

Condition Condition

(P) (S)

Start

Address

Bit 7

(MSB)

Data

Bit 7

(MSB)

Data

Bit 0

(LSB)

Stop

Condition

(P)

R/W

Bit 0

(LSB)

ACK

(A)

Address

Bit 1

t

sch

scl

0.7 ´ V

CCI

SCL

SDA

0.3 ´ V

CCI

t

icr

vd

t

sts

sp

t

icf

t

buf

vd

t

sps

ocf

0.7 ´ V

0.3 ´ V

CCI

t

vd(ack)

icr

t

sdh

t

icf

sds

t

sth

Repeat Start

Condition

Stop

Condition

VOLTAGE WAVEFORMS

BYTE

DESCRIPTION

I²C address

1

2

Input register port data

A. C_Lincludes probe and jig capacitance. t_ocfis measured with C_Lof 10 pF or 400 pF.

B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω, t_r/t_f≤ 30 ns.

C. All parameters and waveforms are not applicable to all devices.

Figure 13. I²C Interface Load Circuit and Voltage Waveforms

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PARAMETER MEASUREMENT INFORMATION (continued)

V

CCI

R

= 4.7 kW

L

INT

DUT

C

= 100 pF

L

(see Note A)

INTERRUPT LOAD CONFIGURATION

ACK

From Slave

ACK

Start

8 Bits

From Slave

Condition

R/W

1

(One Data Byte)

From Port

Slave Address

Data From Port

Data 2

AD

DR

Data 1

A

1

P

S

0

1

0

3

0

4

0

6

A

1

2

5

7

8

A

t

B

ir

t

ir

INT

A

t

iv

t

sps

A

Data

Into

Port

Address

Data 1

Data 2

0.7 ´ V

0.3 ´ V

CCI

0.5 ´ V

SCL

INT

CCI

R/W

A

t

iv

t

ir

0.5 ´ V

INT

CCI

Pn

0.5 ´ V

CCP

View A−A

A. C_Lincludes probe and jig capacitance.

View B−B

B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω, t_r/t_f≤ 30 ns.

C. All parameters and waveforms are not applicable to all devices.

Figure 14. Interrupt Load Circuit and Voltage Waveforms

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PARAMETER MEASUREMENT INFORMATION (continued)

Pn

500 W

DUT

2 ´ V

CCP

C

= 50 pF

L

(see Note A)

500 W

P-PORT LOAD CONFIGURATION

0.7 ´ V

0.3 ´ V

CCP

CCI

SCL

P0

A

P3

Slave

ACK

SDA

Pn

t

pv

(see Note B)

Last Stable Bit

Unstable

Data

WRITE MODE (R/W = 0)

0.7 ´ V

0.3 ´ V

CCI

SCL

Pn

P0

A

P3

CCI

t

ph

t

ps

0.5 ´ V

CCP

READ MODE (R/W = 1)

A. C_Lincludes probe and jig capacitance.

B. t_pvis measured from 0.7 × V_CCon SCL to 50% I/O (Pn) output.

C. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω, t_r/t_f≤ 30 ns.

D. The outputs are measured one at a time, with one transition per measurement.

E. All parameters and waveforms are not applicable to all devices.

Figure 15. P Port Load Circuit and Timing Waveforms

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PARAMETER MEASUREMENT INFORMATION (continued)

V

CCI

R

= 1 kW

L

Pn

500 W

SDA

DUT

2 ´ V

CCP

DUT

C = 50 pF

L

(see Note A)

C

= 50 pF

500 W

L

(see Note A)

SDA LOAD CONFIGURATION

P-PORT LOAD CONFIGURATION

Start

SCL

ACK or Read Cycle

SDA

0.3 ´ V

CCI

t

RESET

V

/2

RESET

CCP

t

REC

t

W

V

/2

Pn

CCP

t

RESET

A. C_Lincludes probe and jig capacitance.

B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω, t_r/t_f≤ 30 ns.

C. The outputs are measured one at a time, with one transition per measurement.

D. I/Os are configured as inputs.

E. All parameters and waveforms are not applicable to all devices.

Figure 16. Reset Load Circuits and Voltage Waveforms

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PACKAGE OPTION ADDENDUM

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5-Oct-2009

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

TCA8418RTWR

ACTIVE

QFN

RTW

24

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Oct-2009

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TCA8418RTWR

QFN

RTW

24

3000

330.0

12.4

4.25

1.15

8.0

12.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Oct-2009

*All dimensions are nominal

Device

Package Type Package Drawing Pins

QFN RTW 24

SPQ

Length (mm) Width (mm) Height (mm)

346.0 346.0 29.0

TCA8418RTWR

3000

Pack Materials-Page 2

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provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in

such safety-critical applications.

TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are

specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military

specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at

the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.

TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are

designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated

products in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Amplifiers

Applications

Audio

Automotive

Broadband

Digital Control

Medical

Military

Optical Networking

Security

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

www.ti.com/audio

Data Converters

DLP® Products

DSP

Clocks and Timers

Interface

www.ti.com/automotive

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/medical

www.ti.com/military

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

dsp.ti.com

www.ti.com/clocks

interface.ti.com

logic.ti.com

power.ti.com

microcontroller.ti.com

www.ti-rfid.com

Logic

Power Mgmt

Microcontrollers

RFID

Telephony

Video & Imaging

Wireless

RF/IF and ZigBee® Solutions www.ti.com/lprf

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TCA8418
厂家：	TEXAS INSTRUMENTS
描述：	I2C CONTROLLED KEYPAD SCAN IC WITH INTEGRATED ESD PROTECTION I2C控制键盘扫描，集成ESD保护IC
文件：	总37页 (文件大小：831K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TCA8418 [TI]

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