TCA9534DWR [TI]
具有中断和配置寄存器的 8 位 1.65V 至 5.5V I2C/SMBus I/O 扩展器 | DW | 16 | -40 to 85;型号: | TCA9534DWR |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有中断和配置寄存器的 8 位 1.65V 至 5.5V I2C/SMBus I/O 扩展器 | DW | 16 | -40 to 85 时钟 光电二极管 外围集成电路 |
文件: | 总42页 (文件大小:1731K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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TCA9534
ZHCSCR8D –SEPTEMBER 2014–REVISED OCTOBER 2017
具有中断输出和配置寄存器的 TCA9534 低电压 8 位 I2C 和 SMBUS 低功
耗 I/O 扩展器
1 特性
2 应用
1
•
静电放电 (ESD) 保护性能超过 JESD 22 规范的要
求
•
•
•
•
•
•
服务器
路由器(电信交换设备)
个人计算机
–
2000V 人体放电模型 (A114-A)
1000V 组件充电模式 (C101)
–
个人电子产品(例如:游戏机)
工业自动化
•
•
•
•
•
•
•
低待机电流消耗
I2C 至并行端口扩展器
采用 GPIO 受限处理器的产品
开漏电路低电平有效中断输出
1.65V 至 5.5V 的工作电源电压范围
可耐受 5V 电压的 I/O 端口
400kHz 快速 I2C 总线
3 个硬件地址引脚可在 I2C/SMBus 上支持最多 8
个器件
3 说明
TCA9534 是一款 16 引脚器件,可为两线双向 I2C 总
线(或 SMBus)协议提供 8 位通用并行输入和输出
(I/O) 扩展。该器件可在 1.65V 至 5.5V 的电源电压范
围内运行,从而允许使用各种器件。该器件支持
100kHz(标准模式)和 400kHz(快速模式)时钟频
率。当开关、传感器、按钮、LED、风扇和其它类似器
件需要额外的 I/O 时,I/O 扩展器(如 TCA9534)可
提供简单解决方案。
•
•
•
•
•
•
•
输入和输出配置寄存器
极性反转寄存器
内部加电复位
所用通道在加电时被配置为输入
加电时无毛刺脉冲
TCA9534 的 功能 包括在 INT 引脚上生成的中断。这
样,主设备就知道输入端口何时更改了状态。硬件可选
地址引脚 A0、A1 和 A2 最多允许 8 个 TCA9534 器件
位于同一 I2C 总线上。该器件还可通过电源循环供电以
生成加电复位,从而复位到默认状态 。
SCL/SDA 输入端上的噪声滤波器
具有最大高电流驱动能力的锁存输出,适用于直接
驱动 LED
•
锁断性能超过 100mA,符合 JESD 78 II 类规范的
要求
器件信息(1)
器件型号
TCA9534
封装
TSSOP (16)
SOIC (16)
封装尺寸(标称值)
5.00mm x 4.40mm
10.30mm x 7.50mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
简化电路原理图
VCC
SDA
SCL
Peripheral
Devices
I2C or SMBus
Master
(e.g. Processor)
P0
P1
P2
P3
INT
• RESET,
ENABLE, or
control
inputs
• INT or
status
TCA9534
P4
P5
P6
P7
A0
A1
A2
outputs
• LEDs
GND
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SCPS197
TCA9534
ZHCSCR8D –SEPTEMBER 2014–REVISED OCTOBER 2017
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 17
8.5 Programming........................................................... 17
8.6 Register Maps......................................................... 19
Application and Implementation ........................ 24
9.1 Application Information............................................ 24
9.2 Typical Application ................................................. 24
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ..................................... 5
6.2 ESD Ratings ............................................................ 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 6
6.6 I2C Interface Timing Requirements........................... 7
6.7 Switching Characteristics.......................................... 8
6.8 Typical Characteristics.............................................. 9
Parameter Measurement Information ................ 12
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 16
8.3 Feature Description................................................. 17
9
10 Power Supply Recommendations ..................... 27
10.1 Power-On Reset Requirements ........................... 27
11 Layout................................................................... 29
11.1 Layout Guidelines ................................................. 29
11.2 Layout Example .................................................... 29
12 器件和文档支持 ..................................................... 30
12.1 文档支持................................................................ 30
12.2 接收文档更新通知 ................................................. 30
12.3 社区资源................................................................ 30
12.4 商标....................................................................... 30
12.5 静电放电警告......................................................... 30
12.6 Glossary................................................................ 30
13 机械、封装和可订购信息....................................... 30
7
8
4 修订历史记录
注:之前版本的页码可能与当前版本有所不同。
Changes from Revision C (February 2017) to Revision D
Page
•
•
Changed VIH value From: VCC = 1.65 V to 2.7 V To: VCC = 1.65 V to 5.5 V in the Recommended Operating Condition...... 5
Changed VIL value From: VCC = 1.65 V to 2.7 V To: VCC = 1.65 V to 5.5 V in the Recommended Operating Condition ...... 5
Changes from Revision B (November 2016) to Revision C
Page
•
•
Added MAX value: 2000 to VCC_FT and VCC_RT in Recommended Supply Sequencing and Ramp Rates table................... 27
Changed VCC_TRR MIN value from: "2" to: "1" in Recommended Supply Sequencing and Ramp Rates table .................... 27
Changes from Revision A (September 2014) to Revision B
Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
更新了说明 部分...................................................................................................................................................................... 1
已添加 DW 封装...................................................................................................................................................................... 1
Corrected ESD ratings to reflect ± ratings.............................................................................................................................. 5
VIH values, improved performance in the Recommended Operating Condition..................................................................... 5
Made changes to IOL in the Recommended Operating Condition table ................................................................................. 5
Changed VPORR limits in the Electrical Characteristics table .................................................................................................. 6
Changed VOH at VCC = 1.65 V in the Electrical Characteristics table ..................................................................................... 6
Updated IOL in the Electrical Characteristics table.................................................................................................................. 6
Changed ICC in the Electrical Characteristics table ................................................................................................................ 7
Deleted ΔICC parameter from the Electrical Characteristics table .......................................................................................... 7
Increased the pin capacitance maximum, decreased typical in the Electrical Characteristics table...................................... 7
Updated graphs in Typical Characteristics section ................................................................................................................ 9
Updated Interrupt Output (INT) section ................................................................................................................................ 17
Added the Calculating Junction Temperature and Power Dissipation section..................................................................... 25
2
版权 © 2014–2017, Texas Instruments Incorporated
TCA9534
www.ti.com.cn
ZHCSCR8D –SEPTEMBER 2014–REVISED OCTOBER 2017
•
•
Added VCC_MV to Table 8 ..................................................................................................................................................... 27
Updated Figure 39 ............................................................................................................................................................... 27
Changes from Original (September 2014) to Revision A
Page
•
最初发布的完整版本。............................................................................................................................................................ 1
Copyright © 2014–2017, Texas Instruments Incorporated
3
TCA9534
ZHCSCR8D –SEPTEMBER 2014–REVISED OCTOBER 2017
www.ti.com.cn
5 Pin Configuration and Functions
PW, DW Package
16-Pin TSSOP, SOIC
Top View
16
15
14
13
12
11
10
9
A0
A1
1
2
3
4
5
6
7
8
VCC
SDA
SCL
INT
P7
A2
P0
P1
P2
P6
P3
P5
GND
P4
Pin Functions
PIN
I/O
DESCRIPTION
NO.
1
NAME
A0
I
I
I
Address input. Connect directly to VCC or ground
Address input. Connect directly to VCC or ground
Address input. Connect directly to VCC or ground
2
A1
3
A2
P-port input-output. Push-pull design structure. At power on, P0 is
configured as an input
4
5
6
P0
P1
P2
I/O
I/O
I/O
P-port input-output. Push-pull design structure. At power on, P1 is
configured as an input
P-port input-output. Push-pull design structure. At power on, P2 is
configured as an input
P-port input-output. Push-pull design structure. At power on, P3 is
configured as an input
7
8
9
P3
GND
P4
I/O
—
Ground
P-port input-output. Push-pull design structure. At power on, P4 is
configured as an input
I/O
P-port input-output. Push-pull design structure. At power on, P5 is
configured as an input
10
11
12
P5
P6
P7
I/O
I/O
I/O
P-port input-output. Push-pull design structure. At power on, P6 is
configured as an input
P-port input-output. Push-pull design structure. At power on, P7 is
configured as an input
13
14
15
16
INT
SCL
SDA
VCC
O
Interrupt output. Connect to VCC through a pullup resistor
Serial clock bus. Connect to VCC through a pullup resistor
Serial data bus. Connect to VCC through a pullup resistor
Supply voltage
I/O
I/O
—
4
Copyright © 2014–2017, Texas Instruments Incorporated
TCA9534
www.ti.com.cn
ZHCSCR8D –SEPTEMBER 2014–REVISED OCTOBER 2017
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
MAX
6
UNIT
V
VCC
VI
Supply voltage
(2)
Input voltage
6
V
VO
IIK
Output voltage(2)
6
V
Input clamp current
VI < 0
–20
–20
±20
50
mA
mA
mA
mA
mA
IOK
IIOK
IOL
IOH
Output clamp current
VO < 0
Input-output clamp current
VO < 0 or VO > VCC
VO = 0 to VCC
VO = 0 to VCC
Continuous output low current through a single P-port
Continuous output high current through a single P-port
–50
250
–160
100
150
Continuous current through GND by all P-ports, INT, and SDA
Continuous current through VCC by all P-ports
ICC
mA
TJ(MAX) Maximum junction temperature
Tstg Storage temperature
°C
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
MAX UNIT
VCC
VIH
Supply voltage
1.65
0.7 × VCC
0.7 × VCC
5.5
V
(1)
SCL, SDA
VCC = 1.65 V to 5.5 V
VCC = 1.65 V to 5.5 V
VCC = 1.65 V to 5.5 V
VCC = 1.65 V to 5.5 V
VCC = 3 V to 5.5 V
VCC
High-level input voltage
V
A0, A1, A2, P7–P0
SCL, SDA
5.5
–0.5 0.3 × VCC
VIL
Low-level input voltage
High-level output current
–0.5 0.3 × VCC
V
A0, A1, A2, P7–P0
Any P-port, P7–P0
–0.5 0.2 × VCC
IOH
–10
25
18
9
mA
Tj ≤ 65°C
Tj ≤ 85°C
Tj ≤ 105°C
Tj ≤ 85°C
Tj ≤ 105°C
P00–P07, P10–P17
(2)
IOL
Low-level output current
mA
6
INT, SDA
3
Continuous current through GND All P-ports P7-P0, INT, and SDA
Continuous current through VCC All P-ports P7-P0
Operating free-air temperature
200
–80
ICC
TA
mA
°C
–40
85
(1) The SCL and SDA pins shall not be at a higher potential than the supply voltage VCC in the application, or an increase in leakage
current, II, results.
(2) The values shown apply to specific junction temperatures. See the Calculating Junction Temperature and Power Dissipation section on
how to calculate the junction temperature.
Copyright © 2014–2017, Texas Instruments Incorporated
5
TCA9534
ZHCSCR8D –SEPTEMBER 2014–REVISED OCTOBER 2017
www.ti.com.cn
6.4 Thermal Information
TCA9534
THERMAL METRIC(1)
PW (TSSOP)
16 PINS
122
DW (SOIC)
16 PINS
92.2
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
56.4
53.8
67.1
56.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
10.8
26.4
ψJB
66.5
56.4
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN TYP(1) MAX UNIT
VIK
Input diode clamp voltage II = –18 mA
1.65 V to 5.5 V
–1.2
V
Power-on reset voltage,
VCC rising
VPORR
VI = VCC or GND, IO = 0
1.2
1
1.5
V
Power-on reset voltage,
VCC falling
VPORF
VI = VCC or GND, IO = 0
0.75
V
V
1.65 V
2.3 V
1.2
1.8
2.6
4.1
1
IOH = –8 mA
3 V
4.5 V
P-port high-level output
voltage(2)
VOH
1.65 V
2.3 V
1.7
2.5
4
IOH = –10 mA
3 V
4.5 V
SDA(3)
VOL = 0.4 V
VOL = 0.5 V
VOL = 0.7 V
VOL = 0.4 V
1.65 V to 5.5 V
1.65 V to 5.5 V
1.65 V to 5.5 V
1.65 V to 5.5 V
3
8
IOL
P port(4)
mA
µA
10
3
(5)
INT
SCL, SDA
A0, A1, A2
P port
±1
±1
1
II
VI = VCC or GND
1.65 V to 5.5 V
IIH
IIL
VI = VCC
1.65 V to 5.5 V
1.65 V to 5.5 V
µA
µA
P port
VI = GND
–1
(1) All typical values are at nominal supply voltage (1.8-, 2.5-, 3.3-, or 5-V VCC) and TA = 25°C.
(2) Each P-port I/O configured as a high output must be externally limited to a maximum of 10 mA, and the total current sourced by all I/Os
(P-ports P7-P0) through VCC must be limited to a maximum current of 80 mA.
(3) The SDA pin must be externally limited to a maximum of 12 mA, and the total current sunk by all I/Os (P-ports P7-P0, INT, and SDA)
through GND must be limited to a maximum current of 200 mA.
(4) Each P-port I/O configured as a low output must be externally limited to a maximum of 25 mA, and the total current sunk by all I/Os (P-
ports P7-P0, INT, and SDA) through GND must be limited to a maximum current of 200 mA.
(5) The INT pin must be externally limited to a maximum of 7 mA, and the total current sunk by all I/Os (P-ports P7-P0, INT, and SDA)
through GND must be limited to a maximum current of 200 mA.
6
Copyright © 2014–2017, Texas Instruments Incorporated
TCA9534
www.ti.com.cn
ZHCSCR8D –SEPTEMBER 2014–REVISED OCTOBER 2017
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
5.5 V
MIN TYP(1) MAX UNIT
22
11
8
40
30
19
11
3.9
2.2
1.8
1.5
8.7
4
3.6 V
VI = VCC or GND, IO = 0,
I/O = inputs, fSCL = 400 kHz, no load
Operating mode
2.7 V
1.95 V
5.5 V
5
1.5
0.9
0.6
0.4
1.5
0.9
0.6
0.4
3
3.6 V
ICC
VI = VCC
µA
2.7 V
VI = VCC or GND, IO = 0,
I/O = inputs,
1.95 V
5.5 V
Standby mode
fSCL = 0 kHz, no load
3.6 V
VI = GND
2.7 V
3
1.95 V
1.65 V to 5.5 V
2.2
8
Ci
SCL
VI = VCC or GND
VIO = VCC or GND
pF
pF
SDA
P port
3
9.5
9.5
Cio
1.65 V to 5.5 V
3.7
6.6 I2C Interface Timing Requirements
over operating free-air temperature range (unless otherwise noted) (see Figure 19)
MIN
MAX
UNIT
STANDARD MODE
I2C clock frequency
fscl
0
4
100
50
kHz
µs
µs
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
I2C clock high time
tsch
I2C clock low time
tscl
4.7
I2C spike time
tsp
I2C serial-data setup time
tsds
250
0
I2C serial-data hold time
tsdh
I2C input rise time
ticr
1000
300
I2C input fall time
ticf
I2C output fall time
tocf
10-pF to 400-pF bus
300
I2C bus free time between Stop and Start
I2C Start or repeated Start condition setup
I2C Start or repeated Start condition hold
I2C Stop condition setup
tbuf
4.7
4.7
4
tsts
tsth
tsps
4
tvd(data)
Valid data time
SCL low to SDA output valid
3.45
3.45
400
ACK signal from SCL low to
SDA (out) low
tvd(ack)
Valid data time of ACK condition
I2C bus capacitive load
µs
pF
Cb
FAST MODE
I2C clock frequency
I2C clock high time
I2C clock low time
I2C spike time
fscl
tsch
tscl
tsp
0
0.6
1.3
400
50
kHz
µs
µs
ns
ns
ns
ns
ns
ns
I2C serial-data setup time
I2C serial-data hold time
I2C input rise time
I2C input fall time
tsds
tsdh
ticr
100
0
20
300
300
300
ticf
20 × (VDD / 5.5 V)
20 × (VDD / 5.5 V)
I2C output fall time
tocf
10-pF to 400-pF bus
Copyright © 2014–2017, Texas Instruments Incorporated
7
TCA9534
ZHCSCR8D –SEPTEMBER 2014–REVISED OCTOBER 2017
www.ti.com.cn
I2C Interface Timing Requirements (continued)
over operating free-air temperature range (unless otherwise noted) (see Figure 19)
MIN
1.3
0.6
0.6
0.6
MAX
UNIT
µs
I2C bus free time between Stop and Start
tbuf
I2C Start or repeated Start condition setup
tsts
µs
I2C Start or repeated Start condition hold
tsth
µs
I2C Stop condition setup
tsps
µs
tvd(data)
tvd(ack)
Cb
Valid data time
SCL low to SDA output valid
0.9
0.9
µs
ACK signal from SCL low to
SDA (out) low
Valid data time of ACK condition
I2C bus capacitive load
µs
pF
400
6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted) (see Figure 20 and Figure 21)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
tiv
Interrupt valid time
P port
SCL
INT
INT
4
4
µs
µs
ns
ns
µs
tir
Interrupt reset delay time
Output data valid
tpv
tps
tph
SCL
P7–P0
SCL
350
Input data setup time
Input data hold time
P port
P port
100
1
SCL
8
Copyright © 2014–2017, Texas Instruments Incorporated
TCA9534
www.ti.com.cn
ZHCSCR8D –SEPTEMBER 2014–REVISED OCTOBER 2017
6.8 Typical Characteristics
TA = 25°C (unless otherwise noted)
40
2.2
2
Vcc = 1.65 V
Vcc = 1.8 V
Vcc = 2.5 V
Vcc = 3.3 V
Vcc = 3.6 V
Vcc = 5 V
Vcc = 5.5V
Vcc = 1.65 V
Vcc = 1.8 V
Vcc = 2.5 V
Vcc = 3.3 V
Vcc = 3.6 V
Vcc = 5 V
Vcc = 5.5V
36
32
28
24
20
16
12
8
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
4
0
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TA - Temperature (°C)
TA - Temperature (°C)
D001
D002
Figure 1. Supply Current vs Temperature for Different
Figure 2. Standby Supply Current vs Temperature for
Different Supply Voltage (VCC
Supply Voltage (VCC
)
)
30
25
20
15
10
5
30
25
20
15
10
5
-40èC
25èC
85èC
-40èC
25èC
85èC
VCC = 1.65 V
0
1.5
0
2
2.5
3
3.5
4
4.5
5
5.5
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
VCC - Supply Voltage (V)
VOL - Output Low Voltage (V)
D003
D004
Figure 3. Supply Current vs Supply Voltage for Different
Temperature (TA)
Figure 4. I/O Sink Current vs Output Low Voltage for
Different Temperature (TA) for VCC = 1.65 V
35
60
50
40
30
20
10
0
-40èC
-40èC
25èC
85èC
25èC
30
85èC
25
VCC = 1.8 V
VCC = 2.5 V
20
15
10
5
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
VOL - Output Low Voltage (V)
VOL - Output Low Voltage (V)
D005
D006
Figure 5. I/O Sink Current vs Output Low Voltage for
Different Temperature (TA) for VCC = 1.8 V
Figure 6. I/O Sink Current vs Output Low Voltage for
Different Temperature (TA) for VCC = 2.5 V
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Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
70
80
70
60
50
40
30
20
10
0
-40èC
-40èC
25èC
85èC
25èC
60
85èC
50
VCC = 3.3 V
VCC = 5 V
40
30
20
10
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
VOL - Output Low Voltage (V)
VOL - Output Low Voltage (V)
D007
D009
Figure 7. I/O Sink Current vs Output Low Voltage for
Different Temperature (TA) for VCC = 3.3 V
Figure 8. I/O Sink Current vs Output Low Voltage for
Different Temperature (TA) for VCC = 5 V
300
250
200
150
100
50
90
80
70
60
50
40
30
20
10
0
1.8 V, 1 mA
1.8 V, 10 mA
3.3 V, 1mA
3.3 V, 10 mA
5 V, 1 mA
5 V, 10 mA
-40èC
25èC
85èC
VCC = 5.5 V
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
-40
-15
10
35
60
85
VOL - Output Low Voltage (V)
TA - Temperature (°C)
D010
D011
Figure 9. I/O Sink Current vs Output Low Voltage for
Different Temperature (TA) for VCC = 5.5 V
Figure 10. II/O Low Voltage vs Temperature for Different VCC
and IOL
20
15
10
5
25
-40èC
25èC
85èC
-40èC
25èC
85èC
20
VCC = 1.65 V
VCC = 1.8 V
15
10
5
0
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
VCC-VOH - Output High Voltage (V)
VCC-VOH - Output High Voltage (V)
D012
D013
Figure 11. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 1.65 V
Figure 12. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 1.8 V
10
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Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
40
60
50
40
30
20
10
0
-40èC
25èC
85èC
-40èC
25èC
85èC
35
30
25
20
15
10
5
VCC = 2.5 V
VCC = 3.3 V
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
VCC-VOH - Output High Voltage (V)
VCC-VOH - Output High Voltage (V)
D014
D015
Figure 13. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 2.5 V
Figure 14. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 3.3 V
70
80
-40èC
-40èC
25èC
85èC
25èC
70
60
50
40
30
20
10
0
60
85èC
50
VCC = 5 V
VCC = 5.5 V
40
30
20
10
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
VCC-VOH - Output High Voltage (V)
VCC-VOH - Output High Voltage (V)
D016
D017
Figure 15. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 5 V
Figure 16. I/O Source Current vs Output High Voltage for
Different Temperature (TA) for VCC = 5.5 V
400
18
1.65 V, 10 mA
2.5 V, 10 mA
3.6 V, 10 mA
5 V, 10 mA
5.5 V, 10 mA
1.65 V
1.8 V
2.5 V
3.3 V
5 V
5.5 V
350
300
250
200
150
100
50
15
12
9
6
3
0
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TA - Temperature (°C)
TA - Temperature (°C)
D018
D019
Figure 17. VCC – VOH Voltage vs Temperature for
Different VCC
Figure 18. Δ ICC vs Temperature for
Different VCC (VI = VCC – 0.6 V)
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7 Parameter Measurement Information
VCC
RL = 1 kW
SDA
DUT
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Three Bytes for Complete
Device Programming
Data
Bit 07
(MSB)
Stop
Condition Condition
(P) (S)
Start
Address
Bit 7
Data
Stop
R/W
Bit 0
(LSB)
Address
Bit 6
Address
Bit 1
ACK
(A)
Bit 10 Condition
(MSB)
(LSB)
(P)
tscl
tsch
0.7 ´ VCC
0.3 ´ VCC
SCL
ticr
tsts
tPHL
ticf
tbuf
tsp
tPLH
0.7 ´ VCC
0.3 ´ VCC
SDA
ticf
ticr
tsdh
tsps
tsth
tsds
Repeat
Stop
Condition
Start
Start or
Repeat
Start
Condition
Condition
VOLTAGE WAVEFORMS
BYTE
1
DESCRIPTION
I2C address
P-port data
2, 3
A. CL includes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 19. I2C Interface Load Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
V
CC
R
= 4.7 kΩ
L
INT
DUT
C
= 100 pF
L
(see Note A)
INTERRUPT LOAD CONFIGURATION
ACK
From Slave
ACK
Start
8 Bits
From Slave
Condition
R/W
(One Data Byte)
From Port
Slave Address
Data From Port
Data 2
S
0
1
1
2
0
3
0
4
A2 A1 A0
1
Data 1
A
A
1
P
A
A
5
6
7
8
t
ir
B
B
t
ir
INT
A
tiv
tsps
A
Data
Into
Address
Data 1
Data 2
Port
0.7 × VCC
0.3 × VCC
0.7 × VCC
0.3 × VCC
SCL
INT
R/W
A
t
iv
t
ir
0.7 × VCC
0.3 × VCC
0.7 × VCC
0.3 × VCC
INT
P
n
View A−A
View B−B
A. CL includes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 20. Interrupt Load Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
Pn
500 Ω
DUT
2 x VCC
CL = 50 pF
(see Note A)
500 Ω
P-PORT LOAD CONFIGURATION
0.7 x VCC
0.3 x VCC
SCL
SDA
P0
A
P3
Slave
ACK
tpv
(see Note B)
Last Stable Bit
Unstable Data
WRITE MODE (R/W = 0)
0.7 x VCC
0.3 x VCC
P0
A
P3
SCL
tph
tps
0.7 x VCC
0.3 x VCC
Pn
READ MODE (R/W = 1)
A. CL includes probe and jig capacitance.
B. tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output.
C. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 21. P-Port Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The TCA9534 is an 8-bit I/O expander for the two-line bidirectional bus (I2C) is designed for 1.65-V to 5.5-V VCC
operation. It provides general-purpose remote I/O expansion for most micro-controller families through the I2C
interface (serial clock, SCL, and serial data, SDA, pins).
The TCA9534 open-drain interrupt (INT) output is activated when any input state differs from its corresponding
Input Port register state and is used to indicate to the system master that an input state has changed. The INT
pin can be connected to the interrupt input of a micro-controller. By sending an interrupt signal on this line, the
remote I/O can inform the micro-controller if there is incoming data on its ports without having to communicate
through the I2C bus. Thus, the TCA9534 can remain a simple slave device. The device outputs (latched) have
high-current drive capability for directly driving LEDs.
Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I2C slave address and allow up to
eight devices to share the same I2C bus or SMBus.
The system master can reset the TCA9534 in the event of a timeout or other improper operation by cycling the
power supply and causing a power-on reset (POR). A reset puts the registers in their default state and initializes
the I2C/SMBus state machine.
The TCA9534 consists of one 8-bit Configuration (input or output selection), Input Port, Output Port, and Polarity
Inversion (active high or active low) registers. At power on, the I/Os are configured as inputs. However, the
system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for
each input or output is kept in the corresponding Input Port or Output Port register. The polarity of the Input Port
register can be inverted with the Polarity Inversion register. All registers can be read by the system master.
The TCA9534 is identical to the TCA9554 except for the removal of the internal I/O pullup resistors, which greatly
reduces power consumption when the I/Os are held LOW.
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8.2 Functional Block Diagram
13
Interrupt
Logic
INT
LP Filter
1
A0
2
3
A1
A2
P7−P0
14
15
SCL
SDA
2
Input
Filter
I C Bus
Control
Shift
I/O
8 Bits
Register
Port
Write Pulse
Read Pulse
Power-On
Reset
16
8
VCC
GND
Pin numbers shown are for the PW package.
Figure 22. Functional Block Diagram
Data From
Shift Register
Output Port
Register Data
Configuration
Register
VCC
Data From
Shift Register
Q1
Q
D
FF
CK Q
Write Configuration
Pulse
Q
D
FF
P0 to P7
Write Pulse
CK Q
Q2
ESD Protection
Diode
Output Port
Register
Input Port
Register
GND
Input Port
Register Data
D
Q
FF
Read Pulse
CK
Q
To INT
Polarity
Register Data
Data From Shift
Register
D
FF
Q
Q
Write Polarity
Pulse
CK
Polarity Inversion
Register
At power-on reset, all registers return to default values.
Figure 23. Simplified Schematic Of P0 To P7
16
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8.3 Feature Description
8.3.1 I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input
voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled depending on the state of the output port register. In
this case, there are low impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin must not exceed the recommended levels for proper operation.
8.3.2 Interrupt Output (INT)
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, the
signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original
setting or data is read from the port that generated the interrupt. Resetting occurs in the read mode at the
acknowledge (ACK) bit after the rising edge of the SCL signal. Note that the INT is reset at the ACK just before
the byte of changed data is sent. Interrupts that occur during the ACK clock pulse can be lost (or be very short)
because of the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and
is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the
state of the pin does not match the contents of the Input Port register.
The INT output has an open-drain structure and requires pullup resistor to VCC
8.4 Device Functional Modes
.
8.4.1 Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the TCA9534 in a reset condition
until VCC has reached VPORR. At that point, the reset condition is released and the TCA9534 registers and
SMBus/I2C state machine initializes to their default states. After that, VCC must be lowered to below VPORF and
then back up to the operating voltage for a power-on reset cycle.
8.5 Programming
8.5.1 I2C Interface
The TCA9534 has a standard bidirectional I2C interface that is controlled by a master device in order to be
configured or read the status of this device. Each slave on the I2C bus has a specific device address to
differentiate between other slave devices that are on the same I2C bus. Many slave devices require configuration
upon startup to set the behavior of the device. This is typically done when the master accesses internal register
maps of the slave, which have unique register addresses. A device can have one or multiple registers where
data is stored, written, or read. For more information see the Understanding the I2C Bus application report.
The physical I2C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines
must be connected to VCC through a pullup resistor. The size of the pullup resistor is determined by the amount
of capacitance on the I2C lines. For further details, see the I2C Pullup Resistor Calculation application report.
Data transfer may be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL lines are
high after a STOP condition.
Figure 24 and Figure 25 show the general procedure for a master to access a slave device:
1. If a master wants to send data to a slave:
–
–
–
Master-transmitter sends a START condition and addresses the slave-receiver.
Master-transmitter sends data to slave-receiver.
Master-transmitter terminates the transfer with a STOP condition.
2. If a master wants to receive or read data from a slave:
–
–
–
Master-receiver sends a START condition and addresses the slave-transmitter.
Master-receiver sends the requested register to read to slave-transmitter.
Master-receiver receives data from the slave-transmitter.
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Programming (continued)
–
Master-receiver terminates the transfer with a STOP condition.
{/[
{5!
5ata Çransfer
{Ç!wÇ
{Çhꢀ
Figure 24. Definition of Start and Stop Conditions
{5! line stꢀble while {/[ line is high
{/[
1
0
1
1
1
!/Y
0
0
0
{5!
a{.
.it
.it
.it
.it
.it
.it
[{.
!/Y
.yte: 1010 1010 ( 0x!!h )
Figure 25. Bit Transfer
Table 1 shows the TCA9534 interface definition.
Table 1. Interface Definition Table
BIT
BYTE
7 (MSB)
6
H
5
L
4
L
3
2
1
0 (LSB)
R/W
I2C slave address
Px I/O data bus
L
A2
P3
A1
P2
A0
P1
P7
P6
P5
P4
P0
18
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8.6 Register Maps
8.6.1 Device Address
Figure 26 shows the address byte of the TCA9534.
Slave Address
A2 A1
A0 R/W
0
1
0
0
Hardware
Selectable
Fixed
Figure 26. TCA9534 Address
Table 2 shows the TCA9534 address reference.
Table 2. Address Reference
INPUTS
I2C BUS SLAVE ADDRESS
A2
L
A1
L
A0
L
32 (decimal), 20 (hexadecimal)
33 (decimal), 21 (hexadecimal)
34 (decimal), 22 (hexadecimal)
35 (decimal), 23 (hexadecimal)
36 (decimal), 24 (hexadecimal)
37 (decimal), 25 (hexadecimal)
38 (decimal), 26 (hexadecimal)
39 (decimal), 27 (hexadecimal)
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read
is selected, while a low (0) selects a write operation.
8.6.2 Control Register and Command Byte
Following the successful Acknowledgment of the address byte, the bus master sends a command byte that is
stored in the control register in the TCA9534 (see Figure 27). Two bits of this command byte state the operation
(read or write) and the internal register (input, output, polarity inversion or configuration) that is affected. This
register can be written or read through the I2C bus. The command byte is sent only during a write transmission.
Once a command byte has been sent, the register that was addressed continues to be accessed by reads until a
new command byte has been sent.
0
0
0
0
0
B2 B1 B0
Figure 27. Control Register Bits
Table 3 shows the TCA9534 command byte.
Table 3. Command Byte Table
CONTROL REGISTER BITS
COMMAND BYTE
REGISTER
PROTOCOL
POWER-UP DEFAULT
(HEX)
B1
0
B0
0
0×00
0×01
0×02
0×03
Input Port
Output Port
Read byte
XXXX XXXX
1111 1111
0000 0000
1111 1111
0
1
Read/write byte
Read/write byte
Read/write byte
1
0
Polarity Inversion
Configuration
1
1
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8.6.3 Register Descriptions
The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is
defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these
registers have no effect. The default value, X, is determined by the externally applied logic level. See Table 4.
Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the
Input Port register is accessed next.
Table 4. Register 0 (Input Port Register) Table
BIT
I7
X
I6
X
I5
X
I4
X
I3
X
I2
X
I1
X
I0
X
DEFAULT
The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the
Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. See
Table 5.
Table 5. Register 1 (Output Port Register) Table
BIT
O7
1
O6
1
O5
1
O4
1
O3
1
O2
1
O1
1
O0
1
DEFAULT
The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration
register. If a bit in this register is set (written with 1), the corresponding port pin polarity is inverted. If a bit in this
register is cleared (written with a 0), the corresponding port pin original polarity is retained. See Table 6.
Table 6. Register 2 (Polarity Inversion Register) Table
BIT
N7
0
N6
0
N5
0
N4
0
N3
0
N2
0
N1
0
N0
0
DEFAULT
The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1,
the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is
cleared to 0, the corresponding port pin is enabled as an output. See Table 7.
Table 7. Register 3 (Configuration Register) Table
BIT
C7
1
C6
1
C5
1
C4
1
C3
1
C2
1
C1
1
C0
1
DEFAULT
20
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8.6.3.1 Bus Transactions
Data is exchanged between the master and the TCA9534 through write and read commands.
8.6.3.1.1 Writes
To write on the I2C bus, the master sends a START condition on the bus with the address of the slave, as well
as the last bit (the R/W bit) set to 0, which signifies a write. After the slave sends the acknowledge bit, the master
then sends the register address of the register to which it is designated to write. The slave acknowledges again,
letting the master know it is ready. After this, the master starts sending the register data to the slave until the
master has sent all the data necessary (which is sometimes only a single byte), and the master terminates the
transmission with a STOP condition.
See Table 3 to see list of the internal registers and a description of each one.
Figure 28 shows an example of writing a single byte to a slave register.
ꢄaster controls {5! line
{lave controls {5! line
írite to one register in a device
wegister !ddress ꢁ (8 bits)
5ata .yte to wegister ꢁ (8 bits)
5evice ({lave) !ddress (7 bits)
{
0
1
0
0
!2 !1 !0
0
!
.7 .6 .ꢀ .4 .3 .2 .1 .0
!
57 56 5ꢀ 54 53 52 51 50
!
ꢂ
{Ç!wÇ
w/í=0 !ꢃY
!ꢃY
!ꢃY {Çhꢂ
Figure 28. Write to Register
Figure 29 shows an example of writing to the output port register.
1
3
4
6
7
8
9
2
SCL
Slave Address
Command Byte
Data to Register
S
0
1
0
0
A2 A1 A0
0
A
A
Data 1
A
P
SDA
0
0
0
0
0
0
0
1
ACK From Slave
Start Condition
R/W ACK From Slave
ACK From Slave
Write to
Port
Data Out
From Port
Data 1 Valid
tpv
Figure 29. Write to Output Port Register
Figure 30 shows an example of writing to the configuration or polarity inversion registers.
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3
6
7
8
9
1
4
2
SCL
SDA
Slave Address
Command Byte
Data to Register
Data
S
0
1
0
0
A2 A1 A0
0
A
1 1/0
A
A
P
0
0
0
0
0
0
ACK From Slave
Start Condition
R/W ACK From Slave
ACK From Slave
Data to
Register
Figure 30. Write to Configuration or Polarity Inversion Registers
8.6.3.1.2 Reads
Reading from a slave is very similar to writing, but requires some additional steps. To read from a slave, the
master must first instruct the slave which register it is designated to read from. This is done by the master
starting off the transmission in a similar fashion as the write, by sending the address with the R/W bit equal to 0
(signifying a write), followed by the register address it is designated to read from. When the slave acknowledges
this register address, the master sends a START condition again, followed by the slave address with the R/W bit
set to 1 (signifying a read). This time, the slave acknowledges the read request, and the master releases the
SDA bus but continues supplying the clock to the slave. During this part of the transaction, the master becomes
the master-receiver, and the slave becomes the slave-transmitter.
The master continues to send out the clock pulses but releases the SDA line so that the slave can transmit data.
At the end of every byte of data, the master sends an ACK to the slave, letting the slave know that it is ready for
more data. When the master has received the number of bytes it is expecting, it sends a NACK, signaling to the
slave to halt communications and release the bus. The master follows this up with a STOP condition.
See Table 3 for the list of the internal registers and a description of each one.
If a read is requested by the master after a POR without first setting the command byte through a write, the
device will NACK until a command byte-register address is set as described above.
Figure 31 shows an example of reading a single byte from a slave register.
ꢃaster controls {5! line
{lave controls {5! line
wead from one register in a device
5evice ({lave) !ddress (7 bits)
wegister !ddress ꢁ (8 bits)
5evice ({lave) !ddress (7 bits)
5ata .yte from wegister ꢁ (8 bits)
57 56 5ꢀ 54 53 52 51 50 ꢁ!
{
0
1
0
0
!2 !1 !0
0
!
.7 .6 .ꢀ .4
.2 .1 .0
!
{r
0
1
0
0
!2 !1 !0
1
!
ꢂ
.3
wꢄí=1
{Ç!wÇ
!/Y
!/Y wepeated {Ç!wÇ
!/Y
ꢁ!/Y {Çhꢂ
wꢄí=0
Figure 31. Read from Register
Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number
of data bytes received in one read transmission, but when the final byte is received, the bus master must not
acknowledge the data. See Figure 32.
<br/>
22
Copyright © 2014–2017, Texas Instruments Incorporated
TCA9534
www.ti.com.cn
ZHCSCR8D –SEPTEMBER 2014–REVISED OCTOBER 2017
1
2
3
4
5
6
7
8
9
SCL
Data From Port
Data 1
Slave Address
Data From Port
Data 4
S
0
1
0
0
A2 A1 A0
R/W
1
A
P
NA
A
SDA
Start
Condition
NACK From
Master
ACK From
Slave
ACK From
Master
Stop
Condition
Read From
Port
Data Into
Port
Data 2
Data 3
Data 4
Data 5
t
ph
t
ps
INT
t
iv
t
ir
This figure assumes the command byte has previously been programmed with 00h.
Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (Read
Input Port register).
This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from the P port (see the Reads section for these details).
Figure 32. Read Input Port Register
Copyright © 2014–2017, Texas Instruments Incorporated
23
TCA9534
ZHCSCR8D –SEPTEMBER 2014–REVISED OCTOBER 2017
www.ti.com.cn
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Figure 33 shows an application in which the TCA9534 can be used.
I/O Expanders such as the TCA9534 are commonly used to obtain more general purpose I/Os. There are many
common uses for these additionial I/Os:
•
•
•
•
Inputs from other ICs, such as interrupt signals from sensors
Inputs from physical buttons (for detecting button presses)
Outputs to control RESET or ENABLE signals on other ICs
Outputs for controlling LEDs for visual feedback to a user
9.2 Typical Application
V
CC
100 kΩ
2 kΩ
16
10 kΩ(1) 10 kΩ(1)
(x 3)
10 kΩ
V
CC
VCC
15
14
4
Subsystem 1
SDA
SCL
INT
SDA
P0
(e.g., temperature sensor)
Master
Controller
SCL
INT
5
INT
P1
P2
P3
13
6
7
RESET
GND
Subsystem 2
(e.g., counter)
TCA9534
9
P4
P5
10
A
3
2
A2
Controlled Device
(e.g., CBT device)
11
12
P6
P7
ENABLE
A1
A0
1
B
GND
ALARM
8
Subsystem 3
(e.g., alarm system)
V
CC
The SCL and SDA pins must be tied directly to VCC because if SCL and SDA are tied to an auxiliary power supply
that could be powered on while VCC is powered off, then the supply current, ICC, will increase as a result.
Device address is configured as 0100000 for this example.
P0, P2, and P3 are configured as outputs.
P1, P4, and P5 are configured as inputs.
P6 and P7 are not used and must be configured as outputs.
Figure 33. Application Schematic
24
Copyright © 2014–2017, Texas Instruments Incorporated
TCA9534
www.ti.com.cn
ZHCSCR8D –SEPTEMBER 2014–REVISED OCTOBER 2017
Typical Application (continued)
9.2.1 Design Requirements
9.2.1.1 Calculating Junction Temperature and Power Dissipation
When designing with the TCA9534, it is important that the Recommended Operating Conditions not be violated.
Many of the parameters of this device are rated based on junction temperature. So junction temperature must be
calculated in order to verify that safe operation of the device is met. The basic equation for junction temperature
is shown in Equation 1.
Tj = TA + q ´ P
(
)
JA
d
(1)
θJA is the standard junction to ambient thermal resistance measurement of the package, as seen in Thermal
Information table. Pd is the total power dissipation of the device, and the approximation is shown in Equation 2.
P » ICC_STATIC ´ VCC
(
+
Pd_PORT _L
+
Pd_PORT _H
)
d
å
å
(2)
Equation 2 is the approximation of power dissipation in the device. The equation is the static power plus the
summation of power dissipated by each port (with a different equation based on if the port is outputting high, or
outputting low. If the port is set as an input, then power dissipation is the input leakage of the pin multiplied by
the voltage on the pin). Note that this ignores power dissipation in the INT and SDA pins, assuming these
transients to be small. They can easily be included in the power dissipation calculation by using Equation 3 to
calculate the power dissipation in INT or SDA while they are pulling low, and this gives maximum power
dissipation.
Pd_PORT _L = I ´ VOL
(
OL
)
(3)
Equation 3 shows the power dissipation for a single port which is set to output low. The power dissipated by the
port is the VOL of the port multiplied by the current it is sinking.
Pd_PORT _H = I
(
´ V - VOH
(
CC
)
)
OH
(4)
Equation 4 shows the power dissipation for a single port which is set to output high. The power dissipated by the
port is the current sourced by the port multiplied by the voltage drop across the device (difference between VCC
and the output voltage).
9.2.1.2 Minimizing ICC when I/Os Control LEDs
When the I/Os are used to control LEDs, normally, these are connected to VCC through a resistor as shown in
Figure 33. For a P-port configured as an input, ICC increases as VI becomes lower than VCC. The LED is a diode,
with threshold voltage VT, and when a P-port is configured as an input the LED is off but VI is a VT drop below
VCC
.
For battery-powered applications, it is essential that the voltage of P-ports controlling LEDs is greater than or
equal to VCC when the P-ports are configured as input to minimize current consumption. Figure 34 shows a high-
value resistor in parallel with the LED. Figure 35 shows VCC less than the LED supply voltage by at least VT.
Both of these methods maintain the I/O VI at or above VCC and prevents additional supply current consumption
when the P-port is configured as an input and the LED is off.
V
CC
LED
100 k
V
CC
LEDx
Figure 34. High-Value Resistor in Parallel with LED
Copyright © 2014–2017, Texas Instruments Incorporated
25
TCA9534
ZHCSCR8D –SEPTEMBER 2014–REVISED OCTOBER 2017
www.ti.com.cn
Typical Application (continued)
5 V
3.3 V
LED
V
CC
LEDx
Figure 35. Device Supplied by a Lower Voltage
9.2.2 Detailed Design Procedure
The pullup resistors, RP, for the SCL and SDA lines need to be selected appropriately and take into consideration
the total capacitance of all slaves on the I2C bus. The minimum pullup resistance is a function of VCC, VOL,(max)
and IOL as shown in Equation 5.
,
VCC - VOL(max)
=
Rp(min)
IOL
(5)
The maximum pullup resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation, fSCL
400 kHz) and bus capacitance, Cb as shown in Equation 6.
=
tr
Rp(max)
=
0.8473´Cb
(6)
The maximum bus capacitance for an I2C bus must not exceed 400 pF for standard mode or fast mode
operation. The bus capacitance can be approximated by adding the capacitance of the TCA9534, Ci for SCL or
Cio for SDA, the capacitance of wires, connections, traces, and the capacitance of additional slaves on the bus.
9.2.3 Application Curves
25
20
15
10
5
1.8
1.6
1.4
1.2
1
Standard-mode
Fast-mode
0.8
0.6
0.4
0.2
0
VCC > 2V
VCC <= 2
0
0
50
100 150 200 250 300 350 400 450
Cb (pF)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
D008
D009
Standard-mode
(fSCL= 100 kHz, tr = 1 µs)
Fast-mode
(fSCL= 400 kHz, tr = 300 ns)
VOL = 0.2*VCC, IOL = 2 mA
when VCC ≤ 2 V
VOL = 0.4 V, IOL = 3 mA
when VCC > 2 V
Figure 37. Minimum Pullup Resistance (Rp(min)) vs Pullup
Reference Voltage (VCC
Figure 36. Maximum Pullup Resistance (Rp(max)) vs Bus
Capacitance (Cb)
)
26
Copyright © 2014–2017, Texas Instruments Incorporated
TCA9534
www.ti.com.cn
ZHCSCR8D –SEPTEMBER 2014–REVISED OCTOBER 2017
10 Power Supply Recommendations
10.1 Power-On Reset Requirements
In the event of a glitch or data corruption, the TCA9534 can be reset to its default conditions by using the power-
on reset feature. Power-on reset requires that the device goes through a power cycle to be completely reset.
This reset also happens when the device is powered on for the first time in an application.
The two types of power-on reset are shown in Figure 38 and Figure 39.
V
CC
Ramp-Down
Ramp-Up
V
CC_TRR
V
drops below VPORF – 50 mV
CC
Time
Time to Re-Ramp
V
V
CC_FT
CC_RT
Figure 38. VCC is Lowered Below the PORF Threshold, Then Ramped Back Up to VCC
Table 8 specifies the performance of the power-on reset feature for the TCA9534 for both types of power-on
reset.
Table 8. Recommended Supply Sequencing and Ramp Rates(1)
PARAMETER
MIN
1
MAX
2000
2000
UNIT
ms
VCC_FT
VCC_RT
Fall rate
See Figure 38
See Figure 38
Rise rate
0.1
ms
Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV or when VCC
drops to GND)
VCC_TRR
VCC_GH
VCC_MV
VCC_GW
See Figure 38
See Figure 39
See Figure 39
See Figure 39
1
μs
V
Level that VCCP can glitch down to, but not cause a functional disruption
when VCCX_GW = 1 μs
1.2
10
The minimum voltage that VCC can glitch down to without causing a
reset (VCC_GH must not be violated)
1.5
V
Glitch width that does not cause a functional disruption when VCCX_GH
0.5 × VCCx
=
μs
(1) All supply sequencing and ramp rate values are measured at TA = 25°C
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. Figure 39 and Table 8 provide more
information on how to measure these specifications.
V
CC
V
CC_GH
V
CC_MV
Time
V
CC_GW
Figure 39. Glitch Width and Glitch Height
Copyright © 2014–2017, Texas Instruments Incorporated
27
TCA9534
ZHCSCR8D –SEPTEMBER 2014–REVISED OCTOBER 2017
www.ti.com.cn
VPOR is critical to the power-on reset. VPORR is the voltage level at which the reset condition is released and all
the registers and the I2C-SMBus state machine are initialized to their default states. The value of VPOR differs
based on the VCC being lowered to or from 0. Figure 40 and Table 8 provide more details on this specification.
VCC
VPORR
VPORF
Time
POR
Time
Figure 40. VPOR
28
Copyright © 2014–2017, Texas Instruments Incorporated
TCA9534
www.ti.com.cn
ZHCSCR8D –SEPTEMBER 2014–REVISED OCTOBER 2017
11 Layout
11.1 Layout Guidelines
For printed circuit board (PCB) layout of the TCA9534, common PCB layout practices must be followed but
additional concerns related to high-speed data transfer such as matched impedances and differential pairs are
not a concern for I2C signal speeds.
In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from
each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher
amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors
are commonly used to control the voltage on the VCC pin, using a larger capacitor to provide additional power in
the event of a short power supply glitch and a smaller capacitor to filter out high-frequency ripple. These
capacitors must be placed as close to the TCA9534 as possible. These best practices are shown in Figure 41.
For the layout example provided in Figure 41, it must be possible to fabricate a PCB with only 2 layers by using
the top layer for signal routing and the bottom layer as a split plane for power (VCC) and ground (GND). However,
a 4-layer board is preferable for boards with higher density signal routing. On a 4-layer PCB, it is common to
route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and dedicate the other
internal layer to a power plane. In a board layout using planes or split planes for power and ground, vias are
placed directly next to the surface mount component pad which needs to attach to VCC or GND and the via is
connected electrically to the internal layer or the other side of the board. Vias are also used when a signal trace
needs to be routed to the opposite side of the board, but this technique is not demonstrated in Figure 41.
11.2 Layout Example
LEGEND
Power or GND Plane
To I2C Master
VIA to Power Plane
VCC
VIA to GND Plane
By-pass/De-coupling
capacitors
1
2
3
4
5
6
7
8
A0
VCC
SDA
SCL
INT
P7
16
15
14
13
12
11
10
9
A1
A2
P0
P1
P2
P6
P3
P5
GND
P4
GND
Figure 41. TCA9534 Layout
版权 © 2014–2017, Texas Instruments Incorporated
29
TCA9534
ZHCSCR8D –SEPTEMBER 2014–REVISED OCTOBER 2017
www.ti.com.cn
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档:
•
•
•
•
•
•
《I2C 总线上拉电阻计算》
《I2C 总线在采用中继器时的最高时钟频率》
《逻辑器件简介》
《理解 I2C 总线》
《为新设计挑选合适的 I2C 器件》
《I/O 扩展器 EVM 用户指南》
12.2 接收文档更新通知
如需接收文档更新通知,请访问 ti.com 上的器件产品文件夹。单击右上角的通知我 进行注册,即可每周接收产品
信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
12.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范,
并且不一定反映 TI 的观点;请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中,您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更,恕不另行通知
和修订此文档。如欲获取此数据表的浏览器版本,请参阅左侧的导航。
30
版权 © 2014–2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TCA9534DWR
TCA9534DWT
TCA9534PWR
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
DW
DW
PW
16
16
16
2000 RoHS & Green
250 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
TCA9534
NIPDAU
NIPDAU
TCA9534
PW534
TSSOP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-May-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TCA9534DWR
TCA9534PWR
SOIC
DW
PW
16
16
2000
2000
330.0
330.0
16.4
12.4
10.75 10.7
6.9 5.6
2.7
1.6
12.0
8.0
16.0
12.0
Q1
Q1
TSSOP
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-May-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TCA9534DWR
TCA9534PWR
SOIC
DW
PW
16
16
2000
2000
350.0
356.0
350.0
356.0
43.0
35.0
TSSOP
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DW 16
7.5 x 10.3, 1.27 mm pitch
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016A
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4220721/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SEE
DETAILS
SYMM
1
16
16X (0.6)
SYMM
14X (1.27)
R0.05 TYP
9
8
(9.3)
LAND PATTERN EXAMPLE
SCALE:7X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220721/A 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SYMM
1
16
16X (0.6)
SYMM
14X (1.27)
R0.05 TYP
8
9
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:7X
4220721/A 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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