TCA9546ADR [TI]
具有复位和电压转换的 4 通道、1.65V 至 5.5V I2C/SMBus 开关 | D | 16 | -40 to 85;
| 型号： | TCA9546ADR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有复位和电压转换的 4 通道、1.65V 至 5.5V I2C/SMBus 开关 | D | 16 | -40 to 85 开关 光电二极管 接口集成电路 |
| 文件： | 总31页 (文件大小：848K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TCA9546A
ZHCSDC5B –APRIL 2014–REVISED NOVEMBER 2019
TCA9546A 具有复位功能的低压 4 通道 I2C 和系统管理总线 (SMbus) 开关
1 特性
2 应用
1
•
•
•
•
4 选 1 双向转换开关
•
•
•
•
服务器
与 I2C 总线和 SMBus 兼容
路由器（电信交换设备）
工厂自动化
具有 I2C 从器件地址冲突（多个完全一样的温度传
感器）的产品
低电平有效复位输入
三个地址引脚，I2C 总线上最多支持八个
TCA9546A 器件
•
•
•
•
通过 I2C 总线进行通道选择，可任意组合
上电时所有开关通道取消选定
低 RON 开关
3 说明
TCA9546A 是一款通过 I2C 总线控制的四路双向转换
开关。串行时钟/串行数据 (SCL/SDA) 上行对分散到四
个下行对，或者通道。根据可编程控制寄存器的内容，
可选择任一单独 SCn/SDn 通道或者通道组合。
支持在 1.8V、2.5V、3.3V 和 5V 总线间
进行电压电平转换
•
•
•
•
•
•
•
•
上电时无干扰
支持热插入
一个低电平有效 (RESET) 输入使得 TCA9546A 能够
在其中一个下行 I2C 总线长时间处于低电平状态时恢
复。将 RESET 下拉为低电平会使 I2C 状态机复位，并
且使所有通道取消选中，这一功能与内部加电复位功能
的作用一样。
低待机电流
工作电源电压范围为 1.65V 至 5.5V
5.5V 耐压输入
0 至 400kHz 时钟频率
闩锁性能超过 100mA，符合 JESD 78 规范
ESD 保护性能超过 JESD 22 规范要求
开关上建有导通栅极，这样 VCC 端子引脚便可用于限
制 TCA9546A 传递的最大高压。这允许在每个对上使
用不同的总线电压，以便 1.8V，2.5V 或 3.3V 部件可
以在没有任何额外保护的情况下与 5V 部件通信。对于
每个通道，外部上拉电阻器将总线电压上拉至所需的电
压电平。所有 I/O 引脚为 5.5V 耐压。
–
–
4000V 人体放电模型 (A114-A)
1500V 充电器件模型 (C101)
器件信息(1)
器件名称
TCA9546A
封装
TSSOP (16)
SOIC (16)
封装尺寸（标称值）
5.00mm x 4.40mm
9.90mm x 3.91mm
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
简化应用示意图
Channel 0
Channel 1
VCC
SD0
SC0
SDA
SCL
Slaves A0, A1...AN
Slaves B0, B1...BN
I2C or SMBus
Master
(e.g. Processor)
SD1
SC1
RESET
TCA9546A
Channel 2
Channel 3
SD2
SC2
Slaves C0, C1...CN
Slaves D0, D1...DN
A0
A1
A2
GND
SD3
SC3
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCPS205
TCA9546A
ZHCSDC5B –APRIL 2014–REVISED NOVEMBER 2019
www.ti.com.cn
目录
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 11
8.5 Programming........................................................... 11
8.6 Control Register ...................................................... 14
Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application .................................................. 16
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings .................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions ..................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics.......................................... 5
6.6 I2C Interface Timing Requirements.......................... 6
6.7 Switching Characteristics......................................... 6
6.8 Interrupt and Reset Timing Requirements............... 7
6.9 Typical Characteristics.............................................. 7
Parameter Measurement Information .................. 8
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
9
10 Power Supply Recommendations ..................... 19
10.1 Power-On Reset Requirements ........................... 19
11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
11.2 Layout Example .................................................... 21
12 器件和文档支持 ..................................................... 22
12.1 接收文档更新通知 ................................................. 22
12.2 支持资源................................................................ 22
12.3 商标....................................................................... 22
12.4 静电放电警告......................................................... 22
12.5 Glossary................................................................ 22
13 机械、封装和可订购信息....................................... 22
7
8
4 修订历史记录
Changes from Revision A (February 2015) to Revision B
Page
•
•
Changed the Pin Configuration image appearance ............................................................................................................... 3
Changed VCC = 3.3 V to VCC = 2.5 V in Figure 15................................................................................................................ 16
Changes from Original (April 2014) to Revision A
Page
•
•
•
已添加 向数据表添加了 D 封装............................................................................................................................................... 1
Changed Handling Ratings table to ESD Ratings. ................................................................................................................ 4
Added D package to the Thermal Information table. ............................................................................................................. 4
2
Copyright © 2014–2019, Texas Instruments Incorporated
TCA9546A
www.ti.com.cn
ZHCSDC5B –APRIL 2014–REVISED NOVEMBER 2019
5 Pin Configuration and Functions
D or PW Package
TSSOP and SOIC 16 Pins
Top View
A0
A1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
SDA
SCL
A2
RESET
SD0
SC0
SC3
SD3
SC2
SD2
SD1
SC1
GND
Not to scale
Pin Functions
PIN
DESCRIPTION
NAME
A0
NO.
1
2
Address input 0. Connect directly to VCC or ground.
Address input 1. Connect directly to VCC or ground.
Active low reset input. Connect to VCC or VDPUM(1) through a pull-up resistor, if not used.
Serial data 0. Connect to VDPU0(1) through a pull-up resistor.
Serial clock 0. Connect to VDPU0(1) through a pull-up resistor.
Serial data 1. Connect to VDPU1(1) through a pull-up resistor.
Serial clock 1. Connect to VDPU1(1) through a pull-up resistor.
Ground
Serial data 2. Connect to VDPU2(1) through a pull-up resistor.
Serial clock 2. Connect to VDPU2(1) through a pull-up resistor.
Serial data 3. Connect to VDPU3(1) through a pull-up resistor.
Serial clock 3. Connect to VDPU3(1) through a pull-up resistor.
Address input 2. Connect directly to VCC or ground.
Serial clock line. Connect to VDPUM(1) through a pull-up resistor.
Serial data line. Connect to VDPUM(1) through a pull-up resistor.
Supply power
A1
RESET
SD0
SC0
SD1
SC1
GND
SD2
SC2
SD3
SC3
A2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCL
SDA
VCC
(1) VDPUX is the pull-up reference voltage for the associated data line. VDPUM is the master I2C master reference voltage and VDPU0-VDPU3
are the slave channel reference voltages.
Copyright © 2014–2019, Texas Instruments Incorporated
3
TCA9546A
ZHCSDC5B –APRIL 2014–REVISED NOVEMBER 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
MAX UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
7
7
V
V
II
Input current
±20
±25
±100
±100
400
85
mA
mA
mA
mA
mW
°C
IO
Output current
Continuous current through VCC
Continuous current through GND
Total power dissipation
Operating free-air temperature range
Storage temperature range
Ptot
TA
–40
-65
Tstg
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±4000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
6.3 Recommended Operating Conditions(1)
MIN
1.65
MAX UNIT
VCC
VIH
Supply voltage
5.5
6
V
SCL, SDA
0.7 × VCC
0.7 × VCC
–0.5
High-level input voltage
V
A2–A0, RESET
SCL, SDA
VCC + 0.5
0.3 × VCC
0.3 × VCC
85
VIL
TA
Low-level input voltage
V
A2–A0, RESET
–0.5
Operating free-air temperature
–40
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6.4 Thermal Information
TCA9546A
THERMAL METRIC(1)
D
16 PINS
92.3
PW
16 PINS
122.3
56.6
UNIT
RθJA
RθJCtop
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
52.3
50.1
57.4
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
17.7
10.9
ψJB
49.8
66.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2014–2019, Texas Instruments Incorporated
TCA9546A
www.ti.com.cn
ZHCSDC5B –APRIL 2014–REVISED NOVEMBER 2019
6.5 Electrical Characteristics(1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN TYP(2)
MAX UNIT
Power-on reset voltage, VCC
rising
VI = VCC or
VPORR
VPORF
No load,
No load,
1.2
1.5
V
GND(3)
Power-on reset voltage, VCC
falling(4)
VI = VCC or
GND(3)
0.8
1
5 V
4.5 V to 5.5 V
3.3 V
3.6
2.6
1.6
1.0
4.5
2.8
1.8
1.1
1.9
1.4
0.8
3 V to 3.6 V
2.5 V
Vpass
Switch output voltage
VSWin = VCC
,
ISWout = –100 μA
V
2.3 V to 2.7 V
1.8 V
1.65 V to 1.95 V
0.5
3
VOL = 0.4 V
VOL = 0.6 V
7
IOL
SDA
1.65 V to 5.5 V
1.65 V to 5.5 V
mA
6
10
SCL, SDA
±1
±1
±1
±1
SC3–SC0, SD3–SD0
A2–A0
II
VI = VCC or GND(3)
μA
RESET
5.5 V
3.6 V
2.7 V
1.65 V
5.5 V
3.6 V
2.7 V
1.65 V
5.5 V
3.6 V
2.7 V
1.65 V
5.5 V
3.6 V
2.7 V
1.65 V
50
20
11
6
VI = VCC or GND(3)
fSCL = 400 kHz IO = 0
tr,max = 300 ns
Operating mode
35
14
5
VI = VCC or GND(3)
fSCL = 100 kHz IO = 0
tr,max = 1 µs
2
ICC
μA
1.6
1.0
0.7
0.4
1.6
1.0
0.7
0.4
2
1.3
1.1
0.55
2
VI = GND(3)
IO = 0
Low inputs
Standby mode
1.3
1.1
0.55
VI = VCC
IO = 0
High inputs
SCL or SDA input at 0.6 V,
1.65 V to 5.5 V
1.65 V to 5.5 V
2
2
15
15
Other inputs at VCC or GND(3)
Supply-current
SCL, SDA
change
ΔICC
μA
SCL or SDA input at VCC – 0.6 V,
Other inputs at VCC or GND(3)
A2–A0
4.5
4.5
15
6
6
5.5
19
8
Ci
VI = VCC or GND(3)
1.65 V to 5.5 V
1.65 V to 5.5 V
pF
pF
RESET
SCL, SDA
Cio(OFF)
VI = VCC or GND(3) Switch OFF
(5)
SC3–SC0, SD3–SD0
(1) For operation between specified voltage ranges, refer to the worst-case parameter in both applicable ranges.
(2) All typical values are at nominal supply voltage (1.8-V, 2.5-V, 3.3-V, or 5-V VCC), TA = 25°C.
(3) RESET = VCC (held high) when all other input voltages, VI = GND.
(4) The power-on reset circuit resets the I2C bus logic with VCC < VPORF
.
(5) Cio(ON) depends on internal capacitance and external capacitance added to the SCn lines when channels(s) are ON.
Copyright © 2014–2019, Texas Instruments Incorporated
5
TCA9546A
ZHCSDC5B –APRIL 2014–REVISED NOVEMBER 2019
www.ti.com.cn
Electrical Characteristics(1) (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN TYP(2)
MAX UNIT
4.5 V to 5.5 V
3 V to 3.6 V
4
5
10
13
16
25
16
VO = 0.4 V
IO = 15 mA
IO = 10 mA
20
Ω
45
RON
Switch on-state resistance
2.3 V to 2.7 V
1.65 V to 1.95 V
7
VO = 0.4 V
10
70
6.6 I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5)
STANDARD MODE
I2C BUS
FAST MODE
I2C BUS
UNIT
MAX
MIN
0
MAX
MIN
0
fscl
I2C clock frequency
I2C clock high time
I2C clock low time
I2C spike time
100
400 kHz
tsch
tscl
4
0.6
1.3
μs
μs
4.7
tsp
50
50
ns
ns
μs
ns
ns
ns
μs
μs
μs
μs
μs
μs
tsds
tsdh
ticr
I2C serial-data setup time
I2C serial-data hold time
I2C input rise time
I2C input fall time
250
0(1)
100
0(1)
(2)
1000
300
20 + 0.1Cb
300
300
300
(2)
(2)
ticf
20 + 0.1Cb
20 + 0.1Cb
tocf
I2C output fall time
10-pF to 400-pF bus
300
tbuf
tsts
I2C bus free time between stop and start
I2C start or repeated start condition setup
I2C start or repeated start condition hold
I2C stop condition setup
4.7
4.7
4
1.3
0.6
0.6
0.6
tsth
tsps
tvdL(Data)
tvdH(Data) Valid-data time (low to high)(3)
4
Valid-data time (high to low)(3)
SCL low to SDA output low valid
1
1
SCL low to SDA output high valid
0.6
0.6
ACK signal from SCL low
to SDA output low
tvd(ack)
Cb
Valid-data time of ACK condition
I2C bus capacitive load
1
1
μs
400
400
pF
(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal), in order to
bridge the undefined region of the falling edge of SCL.
(2) Cb = total bus capacitance of one bus line in pF
(3) Data taken using a 1-kΩ pullup resistor and 50-pF load (see Figure 5)
6.7 Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 5)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX UNIT
RON = 20 Ω, CL = 15 pF
RON = 20 Ω, CL = 50 pF
0.3
ns
1
(1)
tpd
Propagation delay time
SDA or SCL
SDn or SCn
(1) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
6
Copyright © 2014–2019, Texas Instruments Incorporated
TCA9546A
www.ti.com.cn
ZHCSDC5B –APRIL 2014–REVISED NOVEMBER 2019
6.8 Interrupt and Reset Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
MAX UNIT
tWL
Pulse duration, RESET low
RESET time (SDA clear)
6
ns
(1)
trst
tREC(STA)
500
ns
ns
Recovery time from RESET to start
0
(1) trst is the propagation delay measured from the time the RESET pin is first asserted low to the time the SDA pin is asserted high,
signaling a stop condition. It must be a minimum of tWL
.
6.9 Typical Characteristics
800
1.8
1.6
1.4
1.2
1
VCC = 5.5V
VCC = 3.3V
VCC = 1.65V
700
600
500
400
300
200
100
0
0.8
0.6
0.4
0.2
25ºC (Room Temperature)
85ºC
-40ºC
0
2
4
6
IOL (mA)
8
10
12
1.5
2
2.5
3
3.5
VCC (V)
4
4.5
5
5.5
D003
D004
Figure 1. SDA Output Low Voltage (VOL) vs Load Current
(IOL) at Three VCC Levels
Figure 2. Standby Current (ICC) vs Supply Voltage (VCC) at
Three Temperature Points
6
30
25ºC (Room Temperature)
85ºC
-40º
5.8
5.6
5.4
5.2
5
25
20
15
10
5
4.8
4.6
4.4
4.2
4
25ºC (Room Temperature)
85ºC
-40ºC
0
0
0.5
1
1.5
2
2.5
VCC (V)
3
3.5
4
4.5
5
5.5
0
0.5
1
1.5
2
2.5
VCC (V)
3
3.5
4
4.5
5
5.5
D006
D001
Figure 3. Slave channel (SCn/SDn) capacitance (Cio(OFF)) vs.
Supply Voltage (VCC) at Three Temperature Points
Figure 4. ON-Resistance (RON) vs Supply Voltage (VCC) at
Three Temperatures
Copyright © 2014–2019, Texas Instruments Incorporated
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TCA9546A
ZHCSDC5B –APRIL 2014–REVISED NOVEMBER 2019
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7 Parameter Measurement Information
VCC
R
L
= 1 kΩ
SDn, SCn
DUT
C
L
= 50 pF
(See Note 1)
Copyright © 2016, Texas Instruments Incorporated
2
I C PORT LOAD CONFIGURATION
Two Bytes for Complete
Device Programming
Stop
Condition Condition
(P) (S)
Start
Address
Bit 7
(MSB)
R/W
Data
Bit 7
(MSB)
Data
Bit 0
(LSB)
Stop
Condition
(P)
ACK
(A)
Address
Bit 6
Address
Bit 1
ACK
(A)
Bit 0
(LSB)
BYTE
DESCRIPTION
2
1
I C address + R/W
2
Control register data
t
scl
t
sch
0.7 × V
0.3 × V
CC
SCL
SDA
CC
t
vd(ACK)
t
icr
t
sts
or t
vdL
t
icf
t
buf
t
sp
t
vdH
0.7 × V
0.3 × V
CC
CC
t
icf
t
icr
t
sdh
t
sps
t
sth
t
Repeat
sds
Stop
Condition
Start
Condition
Start or Repeat
Start Condition
VOLTAGE WAVEFORMS
A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω,
tr/tf ≤ 30 ns.
C. The outputs are measured one at a time, with one transition per measurement.
Figure 5. I2C Interface Load Circuit, Byte Descriptions, and Voltage Waveforms
8
Copyright © 2014–2019, Texas Instruments Incorporated
TCA9546A
www.ti.com.cn
ZHCSDC5B –APRIL 2014–REVISED NOVEMBER 2019
Parameter Measurement Information (continued)
Start
ACK or Read Cycle
SCL
SDA
30%
50%
t
rst
RESET
t
REC
t
WL
Figure 6. Reset Timing
Copyright © 2014–2019, Texas Instruments Incorporated
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TCA9546A
ZHCSDC5B –APRIL 2014–REVISED NOVEMBER 2019
www.ti.com.cn
8 Detailed Description
8.1 Overview
The TCA9546A is a 4-channel, bidirectional translating I2C switch. The master SCL/SDA signal pair is directed to
four channels of slave devices, SC0/SD0-SC3/SD3. Any individual downstream channel can be selected as well
as any combination of the four channels.
The device offers an active-low RESET input which resets the state machine and allows the TCA9546A to
recover should one of the downstream I2C buses get stuck in a low state. The state machine of the device can
also be reset by cycling the power supply, VCC, also known as a power-on reset (POR). Both the RESET function
and a POR will cause all channels to be deselected.
The connections of the I2C data path are controlled by the same I2C master device that is switched to
communicate with multiple I2C slaves. After the successful acknowledgment of the slave address (hardware
selectable by A0 and A1 pins), a single 8-bit control register is written to or read from to determine the selected
channels.
The TCA9546A may also be used for voltage translation, allowing the use of different bus voltages on each
SCn/SDn pair such that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts. This is achieved by using
external pull-up resistors to pull the bus up to the desired voltage for the master and each slave channel.
8.2 Functional Block Diagram
TCA9546A
5
SC0
7
SC1
10
SC2
12
SC3
4
SD0
6
SD1
9
SD2
11
SD3
Switch Control Logic
8
GND
16
3
VCC
Power-On Reset
RESET
14
15
1
2
SCL
SDA
A0
A1
A2
Input Filter
2
I C Bus Control
13
10
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8.3 Feature Description
The TCA9546A is a 4-channel, bidirectional translating switch for I2C buses that supports Standard-Mode (100
kHz) and Fast-Mode (400 kHz) operation. The TCA9546A features I2C control using a single 8-bit control register
in which the four least significant bits control the enabling and disabling of the 4 switch channels of I2C data flow.
Depending on the application, voltage translation of the I2C bus can also be achieved using the TCA9546A to
allow 1.8-V, 2.5-V, or 3.3-V parts to communicate with 5-V parts. Additionally, in the event that communication on
the I2C bus enters a fault state, the TCA9546A can be reset to resume normal operation using the RESET pin
feature or by a power-on reset which results from cycling power to the device.
8.4 Device Functional Modes
8.4.1 RESET Input
The RESET input is an active-low signal that may be used to recover from a bus-fault condition. When this signal
is asserted low for a minimum of tWL, the TCA9546A resets its registers and I2C state machine and deselects all
channels. The RESET input must be connected to VCC through a pull-up resistor.
8.4.2 Power-On Reset
When power is applied to VCC, an internal power-on reset holds the TCA9546A in a reset condition until VCC has
reached VPOR. At this point, the reset condition is released, and the TCA9546A registers and I2C state machine
are initialized to their default states, all zeroes, causing all the channels to be deselected. Thereafter, VCC must
be lowered below V POR to reset the device.
8.5 Programming
8.5.1 I2C Interface
The I2C bus is for two-way two-line communication between different ICs or modules. The two lines are a serial
data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pullup
resistor when connected to the output stages of a device. Data transfer can be initiated only when the bus is not
busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high
period of the clock pulse, as changes in the data line at this time are interpreted as control signals (see Figure 7).
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 7. Bit Transfer
Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the
clock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is high is
defined as the stop condition (P) (see Figure 8).
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Programming (continued)
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 8. Definition of Start and Stop Conditions
A device generating a message is a transmitter; a device receiving is the receiver. The device that controls the
message is the master, and the devices that are controlled by the master are the slaves (see Figure 9).
SDA
SCL
2
I C
Multiplexer
Master
Transmitter/
Receiver
Master
Transmitter/
Receiver
Slave
Transmitter/
Receiver
Master
Transmitter
Slave
Receiver
Slave
Figure 9. System Configuration
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not
limited. Each byte of eight bits is followed by one acknowledge (ACK) bit. The transmitter must release the SDA
line before the receiver can send an ACK bit.
When a slave receiver is addressed, it must generate an ACK after the reception of each byte. Also, a master
must generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. The
device that acknowledges must pull down the SDA line during the ACK clock pulse so that the SDA line is stable
low during the high pulse of the ACK-related clock period (see Figure 10). Setup and hold times must be taken
into account.
12
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Programming (continued)
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Start
Clock Pulse for ACK
Condition
Figure 10. Acknowledgment on the I2C Bus
Data is transmitted to the TCA9546A control register using the write mode shown in Figure 11.
Slave Address
Control Register
S
1
1
1
0
A2 A1 A0
0
A
X
X
X
X
B3 B2 B1 B0
A
P
SDA
Start Condition
R/W ACK From Slave
ACK From Slave
Stop Condition
Figure 11. Write Control Register
Data is read from the TCA9546A control register using the read mode shown in Figure 12.
Slave Address
Control Register
SDA
P
S
1
1
1
1
A
NA
B3 B2 B1 B0
0
A2 A1 A0
0
0
0
0
Start Condition
R/W ACK From Slave
NACK From Master Stop Condition
Figure 12. Read Control Register
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8.6 Control Register
8.6.1 Device Address
Following a start condition, the bus master must output the address of the slave it is accessing. The address of
the TCA9546A is shown in Figure 13. To conserve power, no internal pullup resistors are incorporated on the
hardware-selectable address pins, and they must be pulled high or low.
Slave Address
0
1
1
1
A2 A1
R/W
A0
Hardware
Selectable
Fixed
Figure 13. TCA9546A Address
The last bit of the slave address defines the operation to be performed. When set to a logic 1, a read is selected,
while a logic 0 selects a write operation.
8.6.2 Control Register Description
Following the successful acknowledgment of the slave address, the bus master sends a byte to the TCA9546A,
which is stored in the control register (see Figure 14). If multiple bytes are received by the TCA9546A, it will save
the last byte received. This register can be written and read via the I2C bus.
Channel Selection Bits
(Read/Write)
7
6
5
4
3
2
1
0
X
X
X
X
B3
B2
B1
B0
Channel 0
Channel 1
Channel 2
Channel 3
Figure 14. Control Register
8.6.3 Control Register Definition
One or several SCn/SDn downstream pairs, or channels, are selected by the contents of the control register (see
Table 1). This register is written after the TCA9546A has been addressed. The four LSBs of the control byte are
used to determine which channel or channels are to be selected. When a channel is selected, the channel
becomes active after a stop condition has been placed on the I2C bus. This ensures that all SCn/SDn lines are in
a high state when the channel is made active, so that no false conditions are generated at the time of
connection. A stop condition always must occur right after the acknowledge cycle.
14
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Control Register (continued)
Table 1. Control Register Write (Channel Selection), Control Register Read (Channel Status)(1)
B7
B6
B5
B4
B3
B2
B1
B0
0
COMMAND
Channel 0 disabled
X
X
X
X
X
X
X
1
Channel 0 enabled
Channel 1 disabled
Channel 1 enabled
Channel 2 disabled
Channel 2 enabled
Channel 3 disabled
Channel 3 enabled
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
X
0
1
X
0
X
0
X
0
X
0
X
0
X
0
X
0
No channel selected,
power-up/reset default state
0
(1) Several channels can be enabled at the same time. For example, B3 =0, B2 = 1, B1 = 1, B0 = 0 means that channels 0 and 3 are
disabled, and channels 1 and 2 are enabled. Care should be taken not to exceed the maximum bus capacity.
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9 Application and Implementation
9.1 Application Information
Applications of the TCA9546A contains an I2C (or SMBus) master device and up to four I2C slave devices. The
downstream channels are ideally used to resolve I2C slave address conflicts. For example, if four identical digital
temperature sensors are needed in the application, one sensor can be connected at each channel: 0, 1, 2, and 3.
When the temperature at a specific location needs to be read, the appropriate channel can be enabled and all
other channels switched off, the data can be retrieved, and the I2C master can move on and read the next
channel.
In an application where the I2C bus contain many additional slave devices that do not result in I2C slave address
conflicts, these slave devices can be connected to any desired channel to distribute the total bus capacitance
across multiple channels. If multiple switches will be enabled simultaneously, additional design requirements
must be considered (See Design Requirements and Detailed Design Procedure).
9.2 Typical Application
A typical application of the TCA9546A contains anywhere from 1 to 5 separate data pull-up voltages, VDPUX , one
for the master device (VDPUM) and one for each of the selectable slave channels (VDPU0 – VDPU3). In the event
where the master device and all slave devices operate at the same voltage, then the pass voltage, Vpass = VDPUX
.
Once the maximum Vpass is known, Vcc can be selected easily using Figure 16. In an application where voltage
translation is necessary, additional design requirements must be considered (See Design Requirements).
Figure 15 shows an application in which the TCA9546A can be used.
VDPUM = 1.65 V to 5.5 V
V
CC
= 2.5 V
16
VDPU0 = 1.65 V to 5.5 V
VCC
4
5
15
14
SD0
SC0
SDA
SCL
SDA
Channel 0
2
I C/SMBus
SCL
Master
3
VDPU1 = 1.65 V to 5.5 V
RESET
6
7
SD1
SC1
Channel 1
VDPU2 = 1.65 V to 5.5 V
TCA9546A
9
SD2
Channel 2
10
SC2
VDPU3 = 1.65 V to 5.5 V
13
A2
2
1
8
A1
11
12
SD3
SC3
A0
Channel 3
GND
Figure 15. TCA9546A Typical Application Schematic
16
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Typical Application (continued)
9.2.1 Design Requirements
The A0, A1, and A2 pins are hardware selectable to control the slave address of the TCA9546A. These pins may
be tied directly to GND or VCC in the application.
If multiple slave channels will be activated simultaneously in the application, then the total IOL from SCL/SDA to
GND on the master side will be the sum of the currents through all pull-up resistors, Rp.
The pass-gate transistors of the TCA9546A are constructed such that the VCC voltage can be used to limit the
maximum voltage that is passed from one I2C bus to another.
Figure 16 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated using
data specified in the Electrical Characteristics section of this data sheet). In order for the TCA9546A to act as a
voltage translator, the Vpass voltage must be equal to or lower than the lowest bus voltage. For example, if the
main bus is running at 5 V and the downstream buses are 3.3 V and 2.7 V, Vpass must be equal to or below 2.7 V
to effectively clamp the downstream bus voltages. As shown in Figure 16, Vpass(max) is 2.7 V when the TCA9546A
supply voltage is 4 V or lower, so the TCA9546A supply voltage could be set to 3.3 V. Pull-up resistors then can
be used to bring the bus voltages to their appropriate levels (see Figure 15).
9.2.2 Detailed Design Procedure
Once all the slaves are assigned to the appropriate slave channels and bus voltages are identified, the pull-up
resistors, Rp, for each of the buses need to be selected appropriately. The minimum pull-up resistance is a
function of VDPUX, VOL,(max), and IOL
:
VDPUX - VOL(max)
=
Rp(min)
IOL
(1)
The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation, fSCL
400 kHz) and bus capacitance, Cb:
=
tr
Rp(max)
=
0.8473´Cb
(2)
The maximum bus capacitance for an I2C bus must not exceed 400 pF for fast-mode operation. The bus
capacitance can be approximated by adding the capacitance of the TCA9546A, Cio(OFF), the capacitance of
wires/connections/traces, and the capacitance of each individual slave on a given channel. If multiple channels
will be activated simultaneously, each of the slaves on all channels will contribute to total bus capacitance.
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Typical Application (continued)
9.2.3 TCA9546A Application Curves
25
20
15
10
5
5
Standard-mode
Fast-mode
25ºC (Room Temperature)
85ºC
-40ºC
4
3
2
1
0
0
0
0.5
1
1.5
2
2.5 3
VCC (V)
3.5
4
4.5
5
5.5
0
50
100 150 200 250 300 350 400 450
Cb (pF)
D007
D008
Standard-mode
(fSCL kHz, tr
SPACE
(fSCL kHz, tr)
Standard-mode
(fSCL= 100 kHz, tr = 1 µs)
Fast-mode
(fSCL= 400 kHz, tr= 300 ns)
Figure 16. Pass-Gate Voltage (Vpass) vs Supply Voltage
(VCC) at Three Temperature Points
Figure 17. Maximum Pull-Up resistance (Rp(max)) vs Bus
Capacitance (Cb)
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
VDPUX > 2V
VDPUX <= 2
0
0.5
1
1.5
2
2.5 3
VDPUX (V)
3.5
4
4.5
5
5.5
D009
VOL = 0.2*VDPUX, IOL = 2 mA when VDPUX ≤ 2 V
VOL = 0.4 V, IOL = 3 mA when VDPUX > 2 V
Figure 18. Minimum Pull-Up Resistance (Rp(min)) vs Pull-Up Reference Voltage (VDPUX
)
18
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10 Power Supply Recommendations
The operating power-supply voltage range of the TCA9546A is 1.65 V to 5.5 V applied at the VCC pin. When the
TCA9546A is powered on for the first time or anytime the device needs to be reset by cycling the power supply,
the power-on reset requirements must be followed to ensure the I2C bus logic is initialized properly.
10.1 Power-On Reset Requirements
In the event of a glitch or data corruption, TCA9546A can be reset to its default conditions by using the power-on
reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
A power-on reset is shown in Figure 19.
V
CC
Ramp-Down
Ramp-Up
V
CC_TRR
V
drops below VPORF – 50 mV
CC
Time
Time to Re-Ramp
V
V
CC_FT
CC_RT
Figure 19. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC
Table 2 specifies the performance of the power-on reset feature for TCA9546A for both types of power-on reset.
Table 2. Recommended Supply Sequencing And Ramp Rates(1)
PARAMETER
MIN TYP
MAX UNIT
VCC_FT
VCC_RT
Fall time
See Figure 19
See Figure 19
1
100
100
ms
ms
Rise time
0.1
Time to re-ramp (when VCC drops below VPORF(min) – 50 mV or
when VCC drops to GND)
VCC_TRR
VCC_GH
VCC_GW
See Figure 19
See Figure 20
See Figure 20
40
μs
V
Level that VCC can glitch down to, but not cause a functional
disruption when VCC_GW = 1 μs
1.2
10
Glitch width that will not cause a functional disruption when
VCC_GH = 0.5 × VCC
μs
VPORF
VPORR
Voltage trip point of POR on falling VCC
Voltage trip point of POR on rising VCC
See Figure 21
See Figure 21
0.8
1.25
1.5
V
V
1.05
(1) All supply sequencing and ramp rate values are measured at TA = 25°C
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Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. Figure 20 and Table 2 provide more
information on how to measure these specifications.
V
CC
V
CC_GH
Time
V
CC_GW
Figure 20. Glitch Width and Glitch Height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the
registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based
on the VCC being lowered to or from 0. Figure 21 and Table 2 provide more details on this specification.
V
CC
V
PORR
V
PORF
Time
POR
Time
Figure 21. VPOR
20
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11 Layout
11.1 Layout Guidelines
For PCB layout of the TCA9546A, common PCB layout practices should be followed but additional concerns
related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I2C
signal speeds. It is common to have a dedicated ground plane on an inner layer of the board and pins that are
connected to ground should have a low-impedance path to the ground plane in the form of wide polygon pours
and multiple vias. By-pass and de-coupling capacitors are commonly used to control the voltage on the VCC pin,
using a larger capacitor to provide additional power in the event of a short power supply glitch and a smaller
capacitor to filter out high-frequency ripple.
In an application where voltage translation is not required, all VDPUX voltages and VCC could be at the same
potential and a single copper plane could connect all of pull-up resistors to the appropriate reference voltage. In
an application where voltage translation is required, VDPUM, VDPU0, VDPU1, VDPU2, and VDPU3 may all be on the
same layer of the board with split planes to isolate different voltage potentials.
To reduce the total I2C bus capacitance added by PCB parasitics, data lines (SCn and SDn) should be a short as
possible and the widths of the traces should also be minimized (e.g. 5-10 mils depending on copper weight).
11.2 Layout Example
LEGEND
Polygonal
Copper Pour
Partial Power Plane
VIA to Power Plane
To I2C Master
VIA to GND Plane (Inner Layer)
VDPUM
By-pass/De-coupling
capacitors
GND
VDPU0
VCC
A0
A1
VCC
SDA
SCL
A2
VDPU3
RESET
SD0
SC0
SC3
SD3
SC2
SD2
SD1
SC1
VDPU2
GND
GND
VDPU1
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12 器件和文档支持
12.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 支持资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需本数据表的浏览器版本，请查阅左侧的导航栏
22
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TCA9546ADR
ACTIVE
ACTIVE
SOIC
D
16
16
2500 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
TCA9546A
PW546A
TCA9546APWR
TSSOP
PW
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TCA9546ADR
SOIC
D
16
16
2500
2000
330.0
330.0
16.4
12.4
6.5
6.9
10.3
5.6
2.1
1.6
8.0
8.0
16.0
12.0
Q1
Q1
TCA9546APWR
TSSOP
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TCA9546ADR
SOIC
D
16
16
2500
2000
356.0
356.0
356.0
356.0
35.0
35.0
TCA9546APWR
TSSOP
PW
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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