TCAL9539_技术文档

TCAL9539

ZHCSP01 –JULY 2022

TCAL9539 具有中断输出、复位和配置寄存器的低电压转换、16 位I2C 总线、

SMBus I/O 扩展器

1 特性

3 说明

• 工作电源电压范围为1.08V 至3.6V

• 1.8mV 时具有1µA（典型值）的低待机电流消耗

• 1MHz 快速+ 模式I²C 总线

• 硬件地址引脚，允许在同一I²C/SMBus 总线上支持

两个器件

• 低电平有效复位输入(RESET)

• 开漏低电平有效中断输出(INT)

• 输入或输出配置寄存器

TCAL9539 器件可为两线双向 I²C 总线（或 SMBus）

协议提供通用并行输入/输出 (I/O) 扩展并在 1.08V 至

3.6V V_CC下运行。

该器件支持 100kHz（标准模式）、400kHz（快速模

式）和 1MHz（快速+ 模式）的 I²C 时钟频率。当开

关、传感器、按钮、LED、风扇等设备需要额外使用

I/O 时，I/O 扩展器（如 TCAL9539）可提供简单解决

方案。

• 极性反转寄存器

• 可配置I/O 驱动强度寄存器

• 上拉电阻和下拉电阻配置寄存器

• 内部上电复位

• SCL 或SDA 输入端上有噪声滤波器

• 具有最大高电流驱动能力的锁存输出，适用于直接

驱动LED

• 闩锁性能超过100mA，符合JESD 78 II 类规范的

要求

• ESD 保护性能超过JESD 22 规范要求

TCAL9539 具有灵活的 I/O 端口，可提供旨在增强 I/O

速度、功耗和 EMI 性能的附加特性。此类附加特性包

括：可编程输出驱动强度、可编程上拉和下拉电阻、可

锁存输入、可屏蔽中断、中断状态寄存器和可编程开漏

或推挽输出。

封装信息

封装⁽¹⁾

TSSOP (24)

WQFN (24)

封装尺寸（标称值）

7.80mm × 4.40mm

4.00mm × 4.00mm

器件型号

TCAL9539

– 2000V 人体放电模型(A114-A)

– 1000V 充电器件模型(C101)

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

2 应用

• 服务器

• 路由器（电信交换设备）

• 个人计算机

• 个人电子产品

• 工业自动化

• 游戏机

• 采用GPIO 受限处理器的产品

VCC

Peripheral

P00

P01

P02

P03

P04

P05

P06

P07

Devices

SDA

SCL

I²C or SMBus

INT

Controller

(processor)

RESET,

ENABLE,

or control

inputs

RESET

TCAL9539

INT or

Status

outputs

P10

P11

P12

P13

LEDs

P14

P15

P16

P17

A1

A0

GND

Keypads

简化版原理图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SCPS241

TCAL9539

ZHCSP01 –JULY 2022

www.ti.com.cn

Table of Contents

8.4 Device Functional Modes..........................................15

8.5 Programming............................................................ 15

8.6 Register Maps...........................................................17

9 Application and Implementation..................................25

9.1 Application Information............................................. 25

9.2 Typical Application.................................................... 25

9.3 Power Supply Recommendations.............................27

9.4 Layout....................................................................... 29

10 Device and Documentation Support..........................31

10.1 接收文档更新通知................................................... 31

10.2 支持资源..................................................................31

10.3 Trademarks.............................................................31

10.4 Electrostatic Discharge Caution..............................31

10.5 术语表..................................................................... 31

11 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................5

6.6 Timing Requirements..................................................6

6.7 I²C Bus Timing Requirements.....................................6

6.8 Switching Characteristics............................................8

7 Parameter Measurement Information............................9

8 Detailed Description......................................................13

8.1 Overview...................................................................13

8.2 Functional Block Diagrams....................................... 13

8.3 Feature Description...................................................14

Information.................................................................... 31

11.1 Tape and Reel Information......................................32

11.2 Mechanical Data..................................................... 34

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Date

Revision

Notes

July 2022

*

Initial release

2

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5 Pin Configuration and Functions

INT

A1

1

24

23

22

21

20

19

18

17

16

15

14

13

VCC

SDA

SCL

A0

2

RESET

P00

3

4

P00

P01

P02

P03

P04

P05

1

2

3

4

5

6

18

17

16

15

14

13

A0

P01

5

P17

P16

P15

P14

P13

P12

P11

P10

P17

P16

P15

P14

P13

P02

6

Thermal

Pad

P03

7

P04

8

P05

9

P06

10

11

12

P07

Not to scale

GND

Not to scale

图5-1. PW (TSSOP) Package, 24-Pin

图5-2. RTW (WQFN) Package, 24-Pin

(Top View)

表5-1. Pin Functions

TSSOP WQFN TYPE⁽¹⁾

DESCRIPTION

NAME

(PW)

21

2

(RTW)

18

23

9

A0

I

Address input. Connect directly to V_CCor ground

A1

Address input. Connect directly to V_CCor ground

GND

INT

12

1

Ground

—

22

24

1

O

Interrupt output. Connect to V_CCthrough a pull-up resistor

RESET

P00

P01

P02

P03

P04

P05

P06

P07

P10

P11

P12

P13

P14

P15

P16

P17

SCL

SDA

VCC

3

I

Active-low reset input. Connect to V_CCthrough a pull-up resistor if no active connection is used

P-port input/output (push-pull design structure). At power on, P00 is configured as an input

P-port input/output (push-pull design structure). At power on, P01 is configured as an input

P-port input/output (push-pull design structure). At power on, P02 is configured as an input

P-port input/output (push-pull design structure). At power on, P03 is configured as an input

P-port input/output (push-pull design structure). At power on, P04 is configured as an input

P-port input/output (push-pull design structure). At power on, P05 is configured as an input

P-port input/output (push-pull design structure). At power on, P06 is configured as an input

P-port input/output (push-pull design structure). At power on, P07 is configured as an input

P-port input/output (push-pull design structure). At power on, P10 is configured as an input

P-port input/output (push-pull design structure). At power on, P11 is configured as an input

P-port input/output (push-pull design structure). At power on, P12 is configured as an input

P-port input/output (push-pull design structure). At power on, P13 is configured as an input

P-port input/output (push-pull design structure). At power on, P14 is configured as an input

P-port input/output (push-pull design structure). At power on, P15 is configured as an input

P-port input/output (push-pull design structure). At power on, P16 is configured as an input

P-port input/output (push-pull design structure). At power on, P17 is configured as an input

Serial clock bus. Connect to V_CCthrough a pull-up resistor

4

I/O

I

5

2

6

3

7

4

8

5

9

6

10

11

13

14

15

16

17

18

19

20

22

23

24

7

8

10

11

12

13

14

15

16

17

19

20

21

I/O

Serial data bus. Connect to V_CCthrough a pull-up resistor

Supply voltage

—

(1) I = Input, O = Output, I/O = Input or Output

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.5

MAX

UNIT

V

V_CC

V_I

Supply voltage

4

Input voltage⁽²⁾

V

V_O

I_IK

Output voltage⁽²⁾

4

V

Input clamp current

V_I< 0

±20

50

mA

°C

I_OK

I_IOK

I_OL

I_OH

I_CC

T_J

Output clamp current

V_O< 0

Input-output clamp current

Continuous output low current

Continuous output high current

Continuous current through GND

Continuous current through V_CC

Junction temperature

V_O< 0 or V_O> V_CC

V_O= 0 to V_CC

–50

–200

160

130

150

T_stg

Storage temperature

°C

–65

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/

JEDEC JS-001, all pins⁽¹⁾

±4000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per ANSI/ESDA/

JEDEC specification JS-002, all pins⁽²⁾

±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

3.6

UNIT

V

V_CC

V_IH

V_IL

I_OH

I_OL

T_A

Supply voltage

1.08

High-level input voltage

Low-level input voltage

High-level output current

Low-level output current

Ambient temperature

Junction temperature

All Pins

P00-P17

0.7 * V_CC

3.6

V

-0.5 0.3 * V_CC

V

mA

°C

–10

25

125

–40

T_J

4

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6.4 Thermal Information

Package

THERMAL METRIC ⁽¹⁾

PW (TSSOP)

PINS

101.4

45.2

RTW (WQFN)

PINS

47.1

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

41.2

56.6

26.6

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

6.9

2.2

Ψ_JT

56.2

26.5

Ψ_JB

R_θJC(bot)

NA

15.8

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN TYP MAX UNIT

V_IK

Input diode clamp voltage

1.08 V to 3.6 V

V

I_I= –18 mA

–1.2

V_PORRPower-on reset voltage, V_CCrising

V_PORFPower-on reset voltage, V_CCfalling

V_I= V_CCor GND, I_O= 0

0.85

1.0

0.6 0.75

0.8

1.08 V

1.65 V

2.3 V

3 V

1.4

I_OH= –8 mA; CCX.X =

11b

2.1

2.8

V_OH

P-port high-level output voltage

V

1.08 V

1.65 V

2.3 V

0.75

I_OH= –2.5mA & CCX.X

= 00b; I_OH= –5mA &

CCX.X = 01b; I_OH= –

7.5mA & CCX.X =

1.4

2.1

10b; I_OH= –10mA &

CCX.X = 11b;

3 V

2.8

1.08 V

1.65 V

2.3 V

0.2

0.15

0.1

P ports

I_OL= 8 mA; CCX.X = 11b

V

3.0 V

0.1

I_OL= 2.5 mA and CCX.X 1.08 V

0.25

0.15

0.1

V_OL

Low-level output voltage

= 00b;

I_OL= 5 mA and CCX.X =

01b;

I_OL= 7.5 mA and CCX.X

= 10b;

I_OL= 10 mA and CCX.X

= 11b;

1.65 V

2.3 V

3.0 V

0.1

SDA

INT

V_OL= 0.4 V

V_I= V_CCor GND

V_I= 3.6 V

20

4

I_OL

Low-level output current

Input leakage current

1.08 V to 3.6 V

mA

µA

1.08 V to 3.6 V

0 V

±1

I_I

P ports

SCL, SDA,

RESETZ

I_I

Input leakage current

V_I= V_CCor GND

1.08 V to 3.6 V

±1

A0, A1

±1 µA

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6.5 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN TYP MAX UNIT

3.6 V

11

8

15

10

8

SDA, RESET =VCC, P

ports, ADDR = V_CCor

GND,

I/O = inputs, f_SCL= 400

kHz

2.7 V

Operating mode

(400 kHz)

µA

1.95 V

1.32 V

3.6 V

5

2

5

38

28

18

15

2.5

2.0

1.6

SDA, RESET = VCC, P

ports, ADDR = V_CCor

GND,

I/O = inputs, f_SCL= 1

MHz

2.7 V

Operating mode

(1 MHz)

1.95 V

1.32 V

3.6 V

I_CC

Quiescent current

SDA, RESET = VCC, P

port, ADDR = V_CCor

GND,

I/O = inputs, I_O= 0, f_SCL

0 kHz,

1

0.8

0.6

2.7 V

µA

1.95 V

=

1.32 V

0.6

1.4

-40 °C < T_A≤85 °C

Standby mode

SDA, RESET = VCC. P

port, ADDR = V_CCor

GND,

I/O = inputs, I_O= 0, f_SCL

0 kHz,

3.6 V

2.7 V

1.95 V

7

6

5

1.32 V

4

85 °C < T_A≤125 °C

R_pu(int)internal pull-up resistance

R_pd(int)internal pull-down resistance

P port

70

100

140

kΩ

pF

C_I

Input pin capacitance

SCL

V_I= V_CCor GND

V_IO= V_CCor GND

1.08 V to 3.6 V

2.5

6

3

7

SDA

P port

C_IO

Input-output pin capacitance

6

6.6 Timing Requirements

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

RESET

t_w

Reset pulse duration

Reset recovery time

Time to reset

80

0

ns

t_REC

t_RESET

P-Ports

t_PH

400

Minimum pulse width on P-Port that causes an interrupt

30

ns

6.7 I²C Bus Timing Requirements

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

I²C Bus - Standard Mode

f_scl

t_sch

t_scl

t_sp

I²C clock frequency

I²C clock high time

I²C clock low time

I²C spike time

0

4

100

kHz

µs

ns

4.7

50

t_sds

t_sdh

t_icr

I²C serial-data setup time

I²C serial-data hold time

I²C input rise time

250

0

1000

6

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6.7 I²C Bus Timing Requirements (continued)

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

300

UNIT

ns

t_icf

I²C input fall time

t_ocf

t_buf

t_sts

t_sth

t_sps

I²C output fall time

10-pF to 400-pF bus

300

ns

I²C bus free time between stop and start

I²C start or repeated start condition setup

I²C start or repeated start condition hold

I²C stop condition setup

4.7

4

µs

4

µs

SCL low to SDA

output valid

t_vd(data)

Valid data time

3.45

µs

ACK signal from SCL

low to SDA (out) low

t_vd(ack)

C_b

Valid data time of ACK condition

I²C bus capacitive load

3.45

400

µs

pF

I²C Bus - Fast Mode

f_scl

t_sch

t_scl

t_sp

I²C clock frequency

0

0.6

1.3

400

50

kHz

µs

ns

µs

I²C clock high time

I²C clock low time

I²C spike time

t_sds

t_sdh

t_icr

I²C serial-data setup time

I²C serial-data hold time

I²C input rise time

100

0

20

300

t_icf

I²C input fall time

20 × (V_CC/ 5.5 V)

t_ocf

t_buf

t_sts

t_sth

t_sps

I²C output fall time

10-pF to 400-pF bus

20 × (V_CC/ 5.5 V)

I²C bus free time between stop and start

I²C start or repeated start condition setup

I²C start or repeated start condition hold

I²C stop condition setup

1.3

0.6

SCL low to SDA

output valid

t_vd(data)

Valid data time

0.9

µs

ACK signal from SCL

low to SDA (out) low

t_vd(ack)

C_b

Valid data time of ACK condition

I²C bus capacitive load

0.9

µs

pF

400

I²C Bus - Fast Mode Plus

f_scl

t_sch

t_scl

t_sp

I²C clock frequency

0

0.26

0.5

1000

50

kHz

µs

ns

µs

I²C clock high time

I²C clock low time

I²C spike time

t_sds

t_sdh

t_icr

I²C serial-data setup time

I²C serial-data hold time

I²C input rise time

50

0

120

t_icf

I²C input fall time

20 × (V_CC/ 5.5 V)

t_ocf

t_buf

t_sts

t_sth

t_sps

I²C output fall time

10-pF to 550-pF bus

20 × (V_CC/ 5.5 V)

I²C bus free time between stop and start

I²C start or repeated start condition setup

I²C start or repeated start condition hold

I²C stop condition setup

0.5

0.26

SCL low to SDA

output valid

t_vd(data)

Valid data time

0.45

µs

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6.7 I²C Bus Timing Requirements (continued)

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

µs

ACK signal from SCL

low to SDA (out) low

t_vd(ack)

C_b

Valid data time of ACK condition

I²C bus capacitive load

0.45

550

pF

6.8 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

FROM (INPUT)

TO (OUTPUT)

INT

MIN

TYP

MAX UNIT

t_iv

Interrupt valid time

P port

1

µs

ns

t_ir

Interrupt reset delay time

Output data valid time

Input data setup time

Input data hold time

SCL

INT

t_pv

t_ps

t_ph

SCL

P port

SCL

400

P port

0

300

8

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7 Parameter Measurement Information

V

CC

R

L

= 1 kW

SDA

DUT

C

L

= 50 pF

(see Note A)

SDA LOAD CONFIGURATION

Three Bytes for Complete

Device Programming

Stop

Condition Condition

(P) (S)

Start

Address

Bit 7

(MSB)

R/W

Data

Bit 7

(MSB)

Data

Stop

Address

Bit 6

Address

Bit 1

ACK

(A)

Bit 0

(LSB)

Bit 0 Condition

(LSB)

(P)

t

scl

t

sch

0.7 × V

0.3 × V

CC

SCL

SDA

CC

t

icr

t

sts

t

vd(ack)

t

icf

t

buf

t

vd(data)

t

sp

0.7 × V

0.3 × V

CC

t

icf

t

icr

t

sdh

t

sps

t

sth

t

sds

Repeat

Start

Stop

Condition

Start or

Repeat

Start

Condition

VOLTAGE WAVEFORMS

BYTE

1

DESCRIPTION

2

I C address

2, 3

P-port data

A. C_Lincludes probe and jig capacitance. tocf is measured with C_Lof 10 pF or 400 pF.

B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, Z_O= 50 Ω, t_r/t_f≤30 ns.

C. All parameters and waveforms are not applicable to all devices.

图7-1. I²C Interface Load Circuit and Voltage Waveforms

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V

CC

R

L

= 4.7 kΩ

INT

DUT

C

= 100 pF

(see Note A)

L

INTERRUPT LOAD CONFIGURATION

ACK

From Slave

ACK

Start

Condition

8 Bits

From Slave

R/W

(One Data Byte)

From Port

Slave Address

Data From Port

Data 2

Data 1

A

1

P

S

1

0

1

A1 A0

1

A

1

2

3

4

5

6

7

8

A

t

ir

B

t

ir

INT

A

t

iv

t

sps

A

Data

Into

Port

Address

Data 1

Data 2

0.7 × V

0.3 × V

CC

0.7 × V

0.3 × V

CC

SCL

INT

R/W

A

CC

t

iv

t

ir

0.7 × V

0.3 × V

0.7 × V

0.3 × V

CC

INT

Pn

CC

View A−A

A. C_Lincludes probe and jig capacitance.

View B−B

B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, Z_O= 50 Ω, t_r/t_f≤30 ns.

C. All parameters and waveforms are not applicable to all devices.

图7-2. Interrupt Load Circuit and Voltage Waveforms

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Pn

500 Ω

DUT

2 × V

CC

C

= 50 pF

L

500 Ω

(see Note A)

P-PORT LOAD CONFIGURATION

0.7 × V

CC

SCL

SDA

P0

A

P3

0.3 × V

CC

Slave

ACK

t

pv

(see Note B)

P

n

Last Stable Bit

Unstable

Data

WRITE MODE (R/W = 0)

0.7 × V

0.3 × V

CC

SCL

P0

A

P3

CC

t

ph

t

ps

0.7 × V

0.3 × V

CC

P

n

CC

READ MODE (R/W = 1)

A. C_Lincludes probe and jig capacitance.

B. t_pvis measured from 0.7 × V_CCon SCL to 50% I/O (Pn) output.

C. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, Z_O= 50 Ω, t_r/t_f≤30 ns.

D. The outputs are measured one at a time, with one transition per measurement.

E. All parameters and waveforms are not applicable to all devices.

图7-3. P-Port Load Circuit and Timing Waveforms

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V

CC

Pn

500 Ω

R

L

= 1 kΩ

DUT

2 × V

CC

SDA

DUT

C

L

= 50 pF

500 Ω

(see Note A)

C

L

= 50 pF

(see Note A)

SDA LOAD CONFIGURATION

P-PORT LOAD CONFIGURATION

Start

SCL

ACK or Read Cycle

SDA

0.3

V

CC

t

RESET

V /2

CC

t

REC

t

w

Px

(see Note D)

V /2

CC

t

RESET

A. C_Lincludes probe and jig capacitance.

B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, Z_O= 50 Ω, t_r/t_f≤30 ns.

C. The outputs are measured one at a time, with one transition per measurement.

D. I/Os are configured as inputs.

E. All parameters and waveforms are not applicable to all devices.

图7-4. Reset Load Circuits and Voltage Waveforms

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8 Detailed Description

8.1 Overview

The TCAL9539 digital core consists of 8-bit data registers which allow the user to configure the I/O port

characteristics. At power on or after a reset, the I/Os are configured as inputs. However, the system controller

can configure the I/Os as either inputs or outputs by writing to the Configuration registers. The data for each

input or output is kept in the corresponding Input Port or Output Port register. The polarity of the Input Port

register can be inverted with the Polarity Inversion register. All registers can be read by the system controller.

Additionally, the TCAL9539 has Agile I/O functionality which is specifically targeted to enhance the I/O ports. The

Agile I/O features and registers include programmable output drive strength, programmable pull-up and pull-

down resistors, latchable inputs, maskable interrupts, interrupt status register, and programmable open-drain or

push-pull outputs. These configuration registers improve the I/O by increasing flexibility and allowing the user to

optimize their design for power consumption, speed, and EMI.

Other features of the device include an interrupt that is generated on the INT pin whenever an input port

changes state. The device can be reset to its default state by applying a low logic level to the RESET pin, issuing

a software reset command, or by cycling power to the device and causing a power-on reset. The hardware

selectable address pins allow multiple TCAL9539 devices to be connected to the same I²C bus.

The TCAL9539 open-drain interrupt (INT) output is activated when any input state differs from its corresponding

Input Port register state and is used to indicate to the system controller that an input state has changed. The INT

pin can be connected to the interrupt input of a processor. By sending an interrupt signal on this line, the device

can inform the processor if there is incoming data on the remote I/O ports without having to communicate via the

I²C bus. Thus, the device can remain a simple responder device.

The system controller can reset the device in the event of a timeout or other improper operation by asserting a

low on the RESET input pin or by cycling the power to the V_CCpin and causing a power-on reset (POR). A reset

puts the registers in their default state and initializes the I²C /SMBus state machine. The RESET feature and a

POR cause the same reset/initialization to occur, but the RESET feature does so without needing to power down

the device.

Two hardware pins (A0 and A1) can be used to program and vary the fixed I²C address and allow mutiple

devices to share the same I²C bus or SMBus.

8.2 Functional Block Diagrams

INT

Interrupt Logic

A0

A1

P00-P07

P10-P17

SCL

Input

Filter

I/O

Port

16 Bits

I2C Bus

Control

Shift

Register

SDA

Write Pulse

Read Pulse

RESET

V_CC

Power-On

Reset

GND

A. All I/Os are set to inputs at reset.

图8-1. Logic Diagram (Positive Logic)

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Output Port

Register Data

Data from

Shift Register

Configuration

Register

V

CC

Data from

Shift Register

Q1

Q2

D

Q

FF

Write

Configuration

Pulse

D

Q

CK

Q

P0 to P7

FF

ESD

Protection

Diode

Write Pulse

CK

Output Port

Register

V

SS

Input Port

Register Data

D

Q

FF

Read Pulse

CK

V

CC

Interrupt

Mask

to INT

Input Port

Register

100 k

Pull-Up/Pull-Down

Control

D

Q

Latch

Input Latch

Register

Data from

Shift Register

EN

D

Q

Read Pulse

FF

Input Port

Latch

Write Input

Latch Pulse

Polarity Inversion

Register

CK

Data from

Shift Register

D

Q

FF

Write Polarity

Pulse

CK

A. On power up or reset, all registers return to default values.

图8-2. Simplified Schematic of P0 to P7

8.3 Feature Description

8.3.1 I/O Port

When an I/O is configured as an input, FETs Q1 and Q2 are off (see Figure 8-2), which creates a high-

impedance input. The input voltage may be raised above the supply voltage to a maximum of 3.6V.

If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In

this case, there are low-impedance paths between the I/O pin and either supply or GND. The external voltage

applied to this I/O pin should not exceed the recommended levels for proper operation.

8.3.2 Adjustable Output Drive Strength

The Output drive strength registers allow the user to control the drive level of the GPIO. Each GPIO can be

configured independently to one of the four possible current levels. By programming these bits the user is

changing the number of transistor pairs or 'fingers' that drive the I/O pad. Figure 8-3 shows a simplified output

stage. The behavior of the pad is affected by the Configuration register, the output port data, and the current

control register. When the Current Control register bits are programmed to 10b, then only two of the fingers are

active, reducing the current drive capability by 50%.

Reducing the current drive capability may be desirable to reduce system noise. When the output switches there

is a peak current that is a function of the output drive selection. This peak current runs through the supply and

GND package inductances and creates a noise (some radiated, but more critically Simultaneous Switching

Noise (SSN)). In other words, switching many outputs at the same time will create ground and supply noise. The

output drive strength control through the Output Drive Strength registers allows the user to mitigate SSN issues

without the need of addtional external components.

8.3.3 Interrupt Output (INT)

An interrupt is generated by any rising or falling edge of the port inputs in the input mode provided the interrupt

feature is unmasked. After time t_iv, the INT signal is valid. Resetting the interrupt circuit is achieved when data on

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the port is changed back to the original setting or when data is read from the port that generated the interrupt.

Resetting occurs in the read mode at the acknowledge (ACK) bit after the rising edge of the SCL signal.

Interrupts that occur during the ACK clock pulse can be lost (or be very short) due to the resetting of the interrupt

during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.

Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output

cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the

state of the pin does not match the contents of the Input Port register.

The INT output has an open-drain structure and requires an external pull-up resistor to V_CC

.

8.3.4 Reset Input (RESET)

The RESET input can be asserted to initialize the system while keeping the V_CCsupply at its operating level. A

reset can be accomplished by holding the RESET pin low for a minimum of t_W. The TCAL9539 registers and I²C/

SMBus state machine are changed to their default state once RESET is low (0). When RESET is high (1), the

I/O levels at the P port can be changed externally or through the controller. This input requires a pull-up resistor

to V_CC, if no active connection is used. When RESET is toggled the input port register is updated to reflect the

state of the GPIO pins.

8.3.5 Software Reset Call

The Software Reset call is a command sent from the controller on the I2C bus that instructs all devices that

support the command to be reset to the power-up default state. In order for it to function as expected, the I2C

bus must be functional and no devices can be hanging the bus.

The Software Reset Call is defined as the following steps:

1. A start condition is sent by the I2C bus controller.

2. The address used is the reserved General Call I2C bus address '0000 0000' with the R/W bit set to 0. The

byte sent is 0x00.

3. Any devices supporting the General Call functionality will ACK. If the R/W bit is set to 1 (read), the device will

NACK.

4. Once the General Call address is acknowledged, the controller sends only 1 byte of data equal to 0x06. If

the data byte is any other value, the device will not acknowledge or reset. If more than 1 byte is sent, no

more bytes will be acknowledged, and the device will ignore the I2C message considering it invalid.

5. After the 1 byte of data (0x06) is sent, the controller sends a STOP condition to end the Software Reset

sequence. A repeated START condition will be ignored by the device and no reset is performed.

One the above steps are completed successfully, the device will perform a reset. This will clear all register

values back to power-on defaults. The input port register is also updated to reflect the state of the GPIO pins.

8.4 Device Functional Modes

8.4.1 Power-On Reset

When power (from 0 V) is applied to V_CC, an internal power-on reset holds the TCAL9539 in a reset condition

until the supply has reached V_POR. At that time, the reset condition is released, and the TCAL9539 registers and

I²C/SMBus state machine initializes to their default states. After that, V_CCmust be lowered to below V_PORFand

back up to the operating voltage for a power-reset cycle.

8.5 Programming

8.5.1 I²C Interface

The bidirectional I²C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be

connected to a positive supply through a pull-up resistor when connected to the output stages of a device. Data

transfer may be initiated only when the bus is not busy.

I²C communication with this device is initiated by a controller sending a Start condition, a high-to-low transition

on the SDA input/output, while the SCL input is high (see 图 8-3). After the Start condition, the device address

byte is sent, most significant bit (MSB) first, including the data direction bit (R/ W).

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After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/

output during the high of the ACK-related clock pulse. The address input of the responder device must not be

changed between the Start and the Stop conditions.

On the I²C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control

commands (Start or Stop) (see 图8-4).

A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the

controller (see 图8-3).

Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop

conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before

the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK

clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see 图8-5).

When a responder receiver is addressed, it must generate an ACK after each byte is received. Similarly, the

controller must generate an ACK after each byte that it receives from the responder transmitter. Setup and hold

times must be met to ensure proper operation.

A controller receiver signals an end of data to the responder transmitter by not generating an acknowledge

(NACK) after the last byte has been clocked out of the responder. This is done by the controller receiver by

holding the SDA line high. In this event, the transmitter must release the data line to enable the controller to

generate a Stop condition.

SDA

SCL

S

P

Stop Condition

Start Condition

图8-3. Definition of Start and Stop Conditions

SDA

SCL

Data Line

Change

图8-4. Bit Transfer

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Data Output

by Transmitter

NACK

Data Output

by Receiver

ACK

SCL From

Controller

1

2

8

9

S

Clock Pulse for

Acknowledgment

Start

Condition

图8-5. Acknowledgment on the I²C Bus

表8-1. Interface Definition

BIT

BYTE

7 (MSB)

6

5

4

3

2

1

0 (LSB)

Device I²C address

I/O data bus

H

L

H

A1

A0

R/ W

P00

P10

P07

P17

P06

P16

P05

P15

P04

P14

P03

P13

P02

P12

P01

P11

8.6 Register Maps

8.6.1 Device Address

The address of the TCAL9539 is shown in 图8-6.

R/W

Slave Address

1

0

1

A1 A0

Fixed

Programmable

图8-6. TCAL9539 Address

表8-2. Address Reference

Inputs

I²C BUS RESPONDER ADDRESS

A1

L

A0

L

116 (decimal), 74 (hexadecimal)

117 (decimal), 75 (hexadecimal)

118 (decimal), 76 (hexadecimal)

119 (decimal), 77 (hexadecimal)

L

H

L

H

The last bit of the responder address defines the operation (read or write) to be performed. A high (1) selects a

read operation, while a low (0) selects a write operation.

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8.6.2 Control Register and Command Byte

Following the successful acknowledgment of the address byte, the bus controller sends a command byte, which

is stored in the control register in the TCAL9539. The lower bits of this data byte reflect the internal registers

(input, output, polarity inversion, or configuration) that are affected. Bit 6 in conjunction with the lower three bits

of the Command byte are used to point to the extended features of the device (Agile IO). The command byte is

sent only during a write transmission.

Once a new command has been sent, the register that was addressed continues to be accessed by reads until a

new command byte has been sent. Upon power-up, hardware reset, or software reset, the control register

defaults to 00h.

B7 B6

B5 B4 B3 B2 B1 B0

图8-7. Control Register Bits

表8-3. Command Byte

CONTROL REGISTER BITS

COMMAND BYTE

POWER-UP

DEFAULT

REGISTER

PROTOCOL

(HEX)

B7

0

B6

0

B5

0

B4

0

B3

0

B2

0

B1

0

B0

0

00

01

02

03

04

05

06

07

40

Input Port 0

Input Port 1

Read byte

xxxx xxxx

1111 1111

0000 0000

1111 1111

0

1

Read byte

0

1

0

Output Port 0

Read/write byte

0

1

Output Port 1

0

1

0

Polarity Inversion 0

Polarity Inversion 1

Configuration 0

Configuration 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Output Drive Strength 0 Read/write byte

Output Drive Strength 1 Read/write byte

41

42

1111 1111

Output drive strength

Read/write byte

register 1

0

1

0

1

43

1111 1111

0

1

0

1

0

1

44

45

Input latch register 0

Input latch register 1

Read/write byte

0000 0000

Pull-up/pull-down enable

register 0

0

1

0

1

0

1

0

1

0

1

46

47

48

49

Read/write byte

0000 0000

1111 1111

pull-up/pull-down enable

register 1

pull-up/pull-down selection

register 0

pull-up/pull-down selection

register 1

0

1

0

1

0

1

0

1

0

1

4A

4B

4C

4D

Interrupt mask register 0 Read/write byte

Interrupt mask register 1 Read/write byte

1111 1111

0000 0000

Interrupt status register 0

Interrupt status register 1

Read byte

Output port configuration

register

0

1

0

1

4F

Read/write byte

0000 0000

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8.6.3 Register Descriptions

The Input Port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether the

pin is defined as an input or an output by the Configuration register. The input port registers are read only. Writes

to these registers have no effect. The default value (X) is determined by the externally applied logic level. Before

a read operation, a write transmission is sent with the command byte to indicate to the I²C device that the Input

Port register will be accessed next.

表8-4. Registers 0 and 1 (Input Port Registers)

BIT

I-07

I-06

I-05

I-04

I-03

I-02

I-01

X

I-00

X

DEFAULT

BIT

X

I-17

X

I-16

X

I-15

X

I-14

X

I-13

X

I-12

X

I-11

X

I-10

X

DEFAULT

The Output Port registers (registers 2 and 3) shows the outgoing logic levels of the pins defined as outputs by

the Configuration register. Bit values in these registers have no effect on pins defined as inputs. In turn, reads

from these registers reflect the value that is in the flip-flop controlling the output selection, not the actual pin

value.

表8-5. Registers 2 and 3 (Output Port Registers)

BIT

O-07

O-06

O-05

O-04

O-03

O-02

O-01

1

O-00

1

DEFAULT

BIT

1

O-17

1

O-16

1

O-15

1

O-14

1

O-13

1

O-12

1

O-11

1

O-10

1

DEFAULT

The Polarity Inversion registers (register 4 and 5) allow polarity inversion of pins defined as inputs by the

Configuration register. If a bit in these registers is set (written with 1), the corresponding port pin polarity is

inverted. If a bit in these registers is cleared (written with a 0), the corresponding port pin's original polarity is

retained.

表8-6. Registers 4 and 5 (Polarity Inversion Registers)

BIT

P-07

P-06

P-05

P-04

P-03

P-02

P-01

P-00

0

DEFAULT

BIT

0

P-17

0

P-16

0

P-15

0

P-14

0

P-13

0

P-12

0

P-11

0

P-10

0

DEFAULT

The Configuration registers (registers 6 and 7) configure the direction of the I/O pins. If a bit in these registers is

set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in these

registers is cleared to 0, the corresponding port pin is enabled as an output. Changing a port from an input to an

output configuration will cause any interrupt associated with that port to be cleared.

表8-7. Registers 6 and 7 (Configuration Registers)

BIT

C-07

C-06

C-05

C-04

C-03

C-02

C-01

C-00

DEFAULT

1

BIT

C-17

1

C-16

1

C-15

1

C-14

1

C-13

1

C-12

1

C-11

1

C-10

1

DEFAULT

The output drive strength registers control the output drive level of the P port GPIO buffers. Each GPIO can be

configured independently to the desired output current level by two register control bits. For example, Port P07 is

controlled by register 41 (bits 7 and 6), port P06 is controlled by register 41 (bits 5 and 4), etc. The output drive

level of the GPIO is programmed 00b = 0.25x drive strength, 01b = 0.5x drive strength, 10b = 0.75x drive

strength, or 11b = 1x for full drive strength capability. See Section 9.2 for more details.

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表8-8. Registers 40, 41, 42, and 43 (Output Drive Strength Registers)

BIT

CC-03

CC-02

CC-01

CC-00

DEFAULT

BIT

1

CC-07

1

CC-07

1

CC-06

1

CC-06

1

CC-05

1

CC-05

1

CC-04

1

CC-04

1

DEFAULT

BIT

CC-13

CC-12

CC-11

CC-10

DEFAULT

BIT

1

CC-17

1

CC-17

1

CC-16

1

CC-16

1

CC-15

1

CC-14

1

CC-14

1

CC-14

1

DEFAULT

The input latch registers enable and disable the input latch feature of the P port GPIO pins. These registers are

effective only when the pin is configured as an input port. When an input latch register bit is 0, the corresponding

input pin state is not latched. A state change in the corresponding input pin generates an input. A read of the

input register clears the interrupt. If the input goes back to its initial logic state before the input port register is

read, then the interrupt is cleared.

When an input latch register bit is set to 1, the corresponding input pin state is latched. A change of state of the

input generates an interrupt and the input logic value is loaded into the corresponding bit of the input port

register (registers 0 and 1). A read of the input port register clears the interrupt. However, if the input pin returns

to its initial logic state before the input port register is read, then the interrupt is not cleared and the

corresponding bit of the input port register keeps the logic value that initiated the interrupt. See Figure 16.

For example, if the P04 input was at a logic 0 state and then transitions to a logic 1 state followed by going back

to the logic 0 state, the input port 0 register will capture this change and an interrupt will be generated (if

unmasked). When the read is performed on the input port 0 register, the interrupt is cleared, assuming there

were no additional inputs that have changed, and bit 4 of the input port 0 register will read '1'. The next read of

the input port register bit 4 should now read '0'.

An interrupt remains active when a non-latched input simultaneously switches state with a latched input and then

returns to its original state. A read of the input register reflects only the change of state of the latched input and

also clears the interrupt. If the input latch register changes from a latched to a non-latched configuration, the

interrupt will be cleared if the input logic value returns to its original state.

If the input pin is changed from a latched to a non-latched input, a read from the input port register reflects the

current port logic level. If the input pin is changed from a non-latched to a latched input, the read from the input

register reflects the latched logic level.

表8-9. Registers 44 and 45 (Input Latch Registers)

BIT

DEFAULT

BIT

L-07

L-06

L-05

L-04

L-03

L-02

L-01

0

L-00

0

L-17

L-16

0

L-15

0

L-14

L-13

L-12

L-11

L-10

DEFAULT

0

The pull-up/pull-down enable registers allow the user to enable or disable pull-up/pull-down resistors on the

GPIO pins. Setting the bit to logic 1 enables the selection of pull-up/pull-down resistors. Setting the bit to logic 0

disconnects the pull-up/pull-down resistors from the GPIO pins. The resistors will be disabled when the GPIO

pins are configured as outputs See section 7.4.11. Use the pull-up/pull-down selection registers to select either a

pull-up or pull-down resistor.

表8-10. Registers 46 and 47 (Pull-Up/Pull-Down Enable Registers)

BIT

DEFAULT

BIT

PE-07

PE-06

PE-05

PE-04

PE-03

PE-02

PE-01

PE-00

0

PE-17

PE-16

PE-15

PE-14

PE-13

PE-12

PE-11

PE-10

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表8-10. Registers 46 and 47 (Pull-Up/Pull-Down Enable Registers) (continued)

BIT

PE-07

PE-06

PE-05

PE-04

PE-03

PE-02

PE-01

PE-00

DEFAULT

0

The pull-up/pull-down selection registers allow the user to configure each GPIO to have a pull-up or pull-down

resistor by programming the respective register bit. Setting a bit to a logic 1 selects a 100 kΩpull-up resistor for

that GPIO pin. Setting a bit to logic 0 selects a 100 kΩ pull-down resistor for that GPIO pin. If the pull-up/pull-

down feature is disabled via registers 46 and 47, writing to these registers will have no effect on the GPIO pin.

表8-11. Registers 48 and 49 (Pull-Up/Pull-Down Selection Registers)

BIT

DEFAULT

BIT

PUD-07 PUD-06 PUD-05 PUD-04 PUD-03 PUD-02 PUD-01 PUD-00

1

PUD-17 PUD-16 PUD-15 PUD-14 PUD-13 PUD-12 PUD-11 PUD-10

DEFAULT

1

The Interrupt mask registers are defaulted to logic 1 upon power-on, disabling interrupts during system start-up.

Interrupts may be enabled by setting corresponding mask bits to logic 0.

If an input changes state and the corresponding bit in the interrupt mask register is set to 1, the interrupt is

masked and the interrupt pin is not asserted. If the corresponding bit in the interrupt mask register is set to 0, the

interrupt pin will be asserted.

When an input changes state and the resulting interrupt is masked, setting the interrupt mask register bit to 0

causes the interrupt pin to be asserted. If the interrupt mask bit of an input that is already currently the source of

an interrupt is set to 1, the interrupt pin will be de-asserted.

表8-12. Registers 4A and 4B (Interrupt Mask Registers)

BIT

M-07

M-06

M-05

M-04

M-03

M-02

M-01

M-00

1

DEFAULT

BIT

1

M-17

1

M-16

1

M-15

1

M-14

1

M-13

1

M-12

1

M-11

1

M-10

1

DEFAULT

The Interrupt status registers are read only registers used to identify the source of an interrupt. When read, a

logic 1 indicates that the corresponding input pin was the source of the interrupt. A logic 0 indicates that the input

pin is not the source of an interrupt. When a corresponding bit in the interrupt mask register is set to 1 (masked),

the interrupt status bit will return to logic 0.

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表8-13. Registers 4C and 4D (Interrupt Status Registers)

BIT

DEFAULT

BIT

S-07

S-06

S-05

S-04

S-03

S-02

S-01

S-00

0

S-17

S-16

S-15

S-14

S-13

S-12

S-11

S-10

DEFAULT

0

The output port configuration register selects port-wise push-pull or open-drain I/O stage. A logic 0 configures

the I/O as push-pull (Q1 and Q2 are active, see Figure 8-2). A logic 1 configures the I/O as open-drain (Q1 is

disabled, Q2 is active) and the recommended command sequence is to program this register (4F) before the

Configuration register (06 and 07) sets the port pins as outputs.

ODEN0 configures Port 0X and ODEN1 configures Port 1X.

表8-14. Register 4F (Output Port Configuration Register)

BIT

Reserved

ODEN-1 ODEN-0

DEFAULT

0

8.6.4 Bus Transactions

Data is exchanged between the controller and TCAL9539 through write and read commands.

8.6.4.1 Writes

Data is transmitted to the TCAL9539 by sending the device address and setting the least-significant bit (LSB) to

a logic 0 (see 图 8-6 for device address). The command byte is sent after the address and determines which

register receives the data that follows the command byte. There is no limitation on the number of data bytes sent

in one write transmission.

Twenty-two registers within the TCAL9539 are configured to operate as eleven register pairs. The eleven pairs

are input port, output port, polarity inversion, configuration, output drive strength (two 16-bit registers), input

latch, pull-up/pull-down enable, pull-up/pulldown selection, interrupt mask, and interrupt status registers. After

sending data to one register, the next data byte is sent to the other register in the pair (see 图 8-8 and 图 8-9).

For example, if the first byte is sent to Output Port 1 (register 3), the next byte is stored in Output Port 0 (register

2).

There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register

pair may be updated independently of the other registers.

SCL

SDA

1

2

3

4

5

6

7

8

9

Command Byte

Target Address

Data to Port 0

Data 0

Data to Port 1

Data 1

S

1

0

1

0

A

0

1

0

A 0.7

0.0

A

1.7

1.0 A

P

A1

A0

Start Condition

Acknowledge

From Target

Acknowledge

From Target

Acknowledge

From Target

Stop

Condition

R/W

Write to Port

Data Out from Port 0

t_pv

Data Valid

t_pv

Data Out from Port 1

图8-8. Write to Output Port Register

<br/>

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SCL

1

2

3

4

5

6

7

8

0

9

1

0

2

0

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

2

3

4

5

Data to Register

Target Address

Command Byte

SDA

S

1

0

1

A1 A0

A

0

1

0

A MSB

Data 0

LSB A MSB

Data1

LSB

A

P

Start Condition

Acknowledge

From Target

Acknowledge

From Target

Acknowledge

From Target

Stop

Condition

R/W

图8-9. Write to Configuration or Polarity Inversion Registers

8.6.4.2 Reads

The bus controller first must send the TCAL9539 address with the LSB set to a logic 0 (see 图 8-6 for device

address). The command byte is sent after the address and determines which register is accessed.

After a restart, the device address is sent again, but this time the least significant bit is set to a logic 1. Data from

the register defined by the command byte is sent by the TCAL9539 (see 图 8-10 and 图 8-11). Data is clocked

into the register on the rising edge of the ACK clock pulse. After the first byte is read, additional bytes may be

read, but the data now reflects the information in the other register in the pair. For example, if Input Port 1 is

read, the next byte read is Input Port 0.There is no limit on the number of data bytes received in one read

transmission, but on the final byte received the bus master must not acknowledge the data. After a subsequent

restart, the command byte contains the value of the next register to be read in the pair. For example, if Input Port

1 was read last before the restart, the register that is read after the restart is the Input Port 0.

Data From Lower

or Upper Byte

of Register

Acknowledge

From Target

Acknowledge

From Target

Acknowledge

From Target

Acknowledge

From Controller

Target Address

Command Byte

A1 A0

S

1

0

1

A1

A0

0

A

S

1

0

1

A

MSB

Data

LSB A

First Byte

R/W

At this moment, controller transmitter

becomes controller receiver, and

target receiver becomes target transmitter.

Data From Upper

or Lower Byte

of Register

No Acknowledge

From Controller

MSB

LSB NA

P

Data

Last Byte

Stop

Condition

图8-10. Read From Register

<br/>

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1

2

3

4

5

6

7

R

1

9

SCL

Data From Port

Data 1

Target Address

Data From Port

Data 4

SDA

S

1

0

1

A1

A

NA P

A0

Start

Condition

NACK From

Controller

ACK From

Target

ACK From

Controller

Stop

Condition

R/W

Read From

Port

Data Into

Port

Data 2

Data 3

Data 4

Data 5

t

ps

ph

INT is cleared

by Read from Port

INT

t

Stop not needed

to clear INT

t

iv

ir

A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is

valid (output mode). It is assumed that the command byte previously has been set to 00 (read Input Port register).

B. This figure eliminates the command byte transfer, a restart, and responder address call between the initial responder address call and

actual data transfer from P port (see 图8-10).

图8-11. Read Input Port Register

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9 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

Applications of the TCAL9539 use this device connected as a responder to an I2C controller (processor), and

the I2C bus may contain any number of other responder devices. The TCAL9539 is in a remote location from the

controller, placed close to the GPIOs to which the controller needs to monitor or control.

9.2 Typical Application

图9-1 shows an application in which the TCAL9539 can be used.

Subsystem 1

(Temperature

Sensor)

INT

V

CC

(5 V)

Subsystem 2

(Counter)

100 k

24

2 k

10 k

V

CC

V

CC

100 k

22

23

RESET

A

4

5

P00

SCL

SDA

SCL

P01

Controller

GND

SDA

6

7

P02

P03

1

3

INT

ENABLE

8

9

RESET

P04

P05

B

TCAL9539

V

CC

10

Controlled Switch

(CBT Device)

P06

P07

P10

P11

P12

P13

P14

P15

11

13

14

15

2

ALARM

A1

A0

Keypad

16

17

18

Subsystem 3

(Alarm)

21

19

20

P16

P17

GND

12

A. Device address configured as 1110000 for this example.

B. P00, P02, and P03 are configured as outputs.

C. P01 and P04 to P017 are configured as inputs.

D. Resistors are required for inputs (on P port) that may float. If a driver to an input will never let the input float, a resistor is not needed.

Outputs (in the P port) do not need pullup resistors.

图9-1. Typical Application Schematic

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9.2.1 Design Requirements

表9-1. Design Parameters

DESIGN PARAMETER

Supply Voltage (V_CC

Output current rating, P-port sinking (I_OL

EXAMPLE VALUE

)

1.8 V

25 mA

10 mA

)

Output current rating, P-port sourcing (I_OH

)

I²C bus clock (SCL) speed

1 MHz

9.2.2 Detailed Design Procedure

The pull-up resistors, R_P, for the SCL and SDA lines need to be selected appropriately and take into

consideration the total capacitance of all responders on the I²C bus. The minimum pull-up resistance is a

function of V_CC, V_OL,(max), and I_OL

:

V_CC- V_OL(max)

R_p(min)

=

I_OL

(1)

The maximum pull-up resistance is a function of the maximum rise time, t_r(120 ns for fast-mode-plus operation,

f_SCL= 1 MHz) and bus capacitance, C_b:

t_r

R_p(max)

=

0.8473´C_b

(2)

The maximum bus capacitance for an I²C bus must not exceed 400 pF for standard-mode or fast-mode

operation, or 550pF for fast-mode-plus. The bus capacitance can be approximated by adding the capacitance of

the TCAL9539, C_ifor SCL or C_iofor SDA, the capacitance of wires/connections/traces, and the capacitance of

additional responders on the bus.

9.2.2.1 Minimizing I_CCWhen I/Os Control LEDs

When the I/Os are used to control LEDs, normally they are connected to V through a resistor as shown in 图9-2.

For a P-port configured as an input, current consumption increases as V_Ibecomes lower than V. The LED is a

diode, with threshold voltage V_T, and when a P-port is configured as an input the LED are off, but V_Iis a V_Tdrop

below V_CC

.

For battery-powered applications, it is essential that the voltage of P-ports controlling LEDs is greater than or

equal to V when the P-ports are configured as input to minimize current consumption. 图9-2 shows a high-value

resistor in parallel with the LED. 图 9-3 shows V less than the LED supply voltage by at least V_T. Both of these

methods maintain the I/O V_Iat or above V and prevent additional supply current consumption when the P-port is

configured as an input and the LED is off.

V

CC

LED

100 k

V

CC

LEDx

图9-2. High-Value Resistor in Parallel with LED

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3.3 V

1.8 V

LED

V

CC

LEDx

图9-3. Device Supplied by a Lower Voltage

9.2.3 Application Curves

1.8

1.6

1.4

1.2

1

0.8

0.6

0.4

0.2

0

V_CC> 2V

V_CC<= 2

0

0.5

1

1.5

2

2.5 3

V_CC(V)

3.5

4

4.5

5

5.5

D009

V_OL= 0.2 × V_CC, I_OL= 2 mA when V_CC≤2 V

Standard-mode: f_SCL= 100 kHz, t_r= 1 µs

Fast-mode: f_SCL= 400 kHz, t_r= 300 ns

V_OL= 0.4 V, I_OL= 3 mA when V_CC> 2 V

图9-5. Minimum Pullup Resistance (R_p(min)) vs

Pullup Reference Voltage (V_CC

图9-4. Maximum Pullup Resistance (R_p(max)) vs

)

Bus Capacitance (C_b)

9.3 Power Supply Recommendations

9.3.1 Power-On Reset Requirements

In the event of a glitch or data corruption, TCAL9539 can be reset to its default conditions by using the power-on

reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This

reset also happens when the device is powered on for the first time in an application.

The two types of power-on reset are shown in 图9-6 and 图9-7.

V

CC

Ramp-Up

Ramp-Down

Re-Ramp-Up

V

CC_TRR_GND

Time

Time to Re-Ramp

V

CC_RT

CC_FT

CC_RT

图9-6. V is lowered below 0.2 V or 0 V and then ramped up

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V

CC

Ramp-Down

Ramp-Up

V

CC_TRR_VPOR50

V

drops below POR levels

IN

Time

Time to Re-Ramp

V

CC_FT

CC_RT

图9-7. V is lowered below the POR threshold, then ramped back up

表9-2 specifies the performance of the power-on reset feature for TCAL9539 for both types of power-on reset.

表9-2. Recommended Supply Sequencing and Ramp Rates

PARAMETER^{(1) (2)}

MIN TYP

MAX UNIT

t_FT

Fall rate

0.1

1

2000

ms

μs

See 图9-6

See 图9-7

t_RT

Rise rate

t_{TRR_GND}

t_{TRR_POR50}

Time to re-ramp (when V_CCdrops to GND)

1

Time to re-ramp (when V_CCdrops to V_{POR_MIN}–50 mV)

Level that V can glitch down to, but not cause a functional

disruption when V = 1 μs

V_{CC_GH}

t_GW

1.0

10

V

See 图9-8

Glitch width that will not cause a functional disruption when V =

0.5 × V_CCx

μs

V_PORF

V_PORR

Voltage trip point of POR on falling V_CC

Voltage trip point of POR on rising V_CC

0.6

V

1.0

(1) T_A= 25°C (unless otherwise noted).

(2) Not tested. Specified by design.

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width

(V_{CC_GW}) and height (V_{CC_GH}) are dependent on each other. The bypass capacitance, source impedance, and

device impedance are factors that affect power-on reset performance. 图 9-8 and 表 9-2 provide more

information on how to measure these specifications.

V

CC

V

CC_GH

Time

V

CC_GW

图9-8. Glitch Width and Glitch Height

V_PORis critical to the power-on reset. V_PORis the voltage level at which the reset condition is released and all

the registers and the I²C/SMBus state machine are initialized to their default states. The value of V_PORdiffers

based on the V being lowered to or from 0. 图9-9 and 表9-2 provide more details on this specification.

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V

CC

V

POR

V

PORF

Time

POR

Time

图9-9. V_POR

9.4 Layout

9.4.1 Layout Guidelines

For printed circuit board (PCB) layout of the TCAL9539, common PCB layout practices should be followed but

additional concerns related to high-speed data transfer such as matched impedance and differential pairs are not

a concern for I²C signal speeds.

In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from

each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher

amounts of current that commonly pass through power and ground traces. By-pass and decoupling capacitors

are commonly used to control the voltage on the supply pins, using a larger capacitor to provide additional power

in the event of a short power supply glitch and a smaller capacitor to filter out high-frequency ripple. These

capacitors should be placed as close to the TCAL9539 as possible. These best practices are shown in 图9-10.

For the layout example provided in 图 9-10, it is possible to fabricate a PCB with only 2 layers by using the top

layer for signal routing and the bottom layer as a split plane for power and ground (GND). However, a 4 layer

board is preferable for boards with higher density signal routing. On a 4 layer PCB, it is common to route signals

on the top and bottom layer, dedicate one internal layer to a ground plane, and dedicate the other internal layer

to a power plane. In a board layout using planes or split planes for power and ground, vias are placed directly

next to the surface mount component pad which needs to attach to power or GND and the via is connected

electrically to the internal layer or the other side of the board. Vias are also used when a signal trace needs to be

routed to the opposite side of the board, but this technique is not demonstrated in 图9-10.

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9.4.2 Layout Example

LEGEND

Partial view of plane

(inner layer )

Via to power plane

Via to GND plane

By-pass/de-coupling

capacitors

PW package

1

2

INT

16

15

14

13

16

15

14

13

16

15

14

13

VCC

SDA

SCL

A0

A1

3

RESET

P00

P01

P02

P03

P04

P05

P06

P07

GND

4

5

P17

P16

P15

P14

P13

P12

P11

P10

6

7

8

9

10

11

12

图9-10. TCAL9539 Layout

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10 Device and Documentation Support

10.1 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

10.2 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

10.3 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

10.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

10.5 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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11.1 Tape and Reel Information

REEL DIMENSIONS

TAPE DIMENSIONS

K0

P1

W

B0

Reel

Diameter

Cavity

A0

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

W

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

Reel

Diameter

(mm)

Reel

Width W1

(mm)

Package

Type

Package

Drawing

A0

(mm)

B0

(mm)

K0

(mm)

P1

(mm)

W

(mm)

Pin1

Quadrant

Device

Pins

SPQ

PTCAL9539PWR

PTCAL9538RTWR

TSSOP

WQFN

PW

16

24

2000

3000

330.0

12.4

6.9

5.6

1.6

8.0

12.0

Q1

Q2

RTW

4.25

1.15

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TAPE AND REEL BOX DIMENSIONS

Width (mm)

H

W

L

Device

Package Type

TSSOP

Package Drawing Pins

SPQ

2000

3000

Length (mm) Width (mm)

Height (mm)

35.0

PTCAL9539PWR

PTCAL9538RTWR

PW

16

24

367.0

356.0

367.0

35.0

WQFN

RTW

35.0

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11.2 Mechanical Data

PACKAGE OUTLINE

PW0024A

TSSOP - 1.2 mm max height

S

C

A

L

E

2

.

0

SMALL OUTLINE PACKAGE

SEATING

PLANE

C

6.6

6.2

TYP

A

0.1 C

PIN 1 INDEX AREA

22X 0.65

24

1

2X

7.15

7.9

7.7

NOTE 3

12

13

0.30

24X

4.5

4.3

NOTE 4

0.19

1.2 MAX

B

0.1

C A B

0.25

GAGE PLANE

0.15

0.05

(0.15) TYP

SEE DETAIL A

0.75

0.50

0 -8

A

20

DETAIL A

TYPICAL

4220208/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold ﬂash, protrusions, or gate burrs. Mold ﬂash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead ﬂash. Interlead ﬂash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

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EXAMPLE BOARD LAYOUT

PW0024A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

SYMM

24X (1.5)

(R0.05) TYP

24

1

24X (0.45)

22X (0.65)

SYMM

12

13

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

15.000

SOLDER MASK DETAILS

4220208/A 02/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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TCAL9539

ZHCSP01 –JULY 2022

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EXAMPLE STENCIL DESIGN

PW0024A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

24X (1.5)

SYMM

(R0.05) TYP

24

1

24X (0.45)

22X (0.65)

SYMM

12

13

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

4220208/A 02/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have diﬀerent recommendations for stencil design.

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ZHCSP01 –JULY 2022

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PACKAGE OUTLINE

RTW0024J

WQFN - 0.8 mm max height

S

C

A

L

E

3

.

5

0

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

A

B

PIN 1 INDEX AREA

0.5

0.3

0.2

0.3

4.1

3.9

DETAIL

OPTIONAL TERMINAL

TYPICAL

C

0.8 MAX

SEATING PLANE

0.08 C

0.05

0.00

(0.1)

TYP

2.2 0.1

7

12

SEE TERMINAL

DETAIL

20X 0.5

13

6

4X

2.5

1

18

0.3

0.2

24X

PIN 1 ID

(OPTIONAL)

24

19

0.1

C A

C

B

0.5

0.3

0.05

24X

4221566/A 08/2014

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RTW0024J

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

2.2)

SYMM

19

24

24X (0.6)

1

18

24X (0.25)

SYMM

(3.8)

4X

(0.85)

20X (0.5)

13

6

5X ( 0.2)

VIA

7

12

(3.8)

LAND PATTERN EXAMPLE

SCALE:15X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL

UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4221566/A 08/2014

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

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EXAMPLE STENCIL DESIGN

RTW0024J

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

SYMM

METAL

TYP

(0.59) TYP

19

24

24X (0.6)

1

18

24X (0.25)

(0.59)

TYP

(3.8)

20X (0.5)

13

6

7

12

4X ( 0.98)

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

79% PRINTED SOLDER COVERAGE BY AREA

SCALE:18X

4221566/A 08/2014

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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GENERIC PACKAGE VIEW

RTW 24

4 x 4, 0.5 mm pitch

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224801/A

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TCAL9539
厂家：	TEXAS INSTRUMENTS
描述：	具有中断、复位和灵活 I/O 配置的 16 位低压 I²C 总线/SMBus I/O 扩展器
文件：	总42页 (文件大小：2292K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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