TCAN1042HGD [TI]

具有灵活数据速率的故障保护 CAN 收发器 | D | 8 | -55 to 125;


型号：	TCAN1042HGD
厂家：	TEXAS INSTRUMENTS
描述：	具有灵活数据速率的故障保护 CAN 收发器 \| D \| 8 \| -55 to 125
文件：	总38页 (文件大小：1398K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TCAN1042H, TCAN1042HG

TCAN1042HGV, TCAN1042HV

ZHCSEK9D –MARCH 2016 –REVISED OCTOBER 2021

TCAN1042 具有CAN FD 和故障保护功能的CAN 收发器

• 电信基站状态和控制

1 特性

• 诸如CANopen、DeviceNet、NMEA2000、

ARNIC825、ISO11783、CANaerospace 的CAN

总线标准

• 符合ISO 11898-2:2016 和

ISO 11898-5:2007 物理层标准

• “Turbo”CAN：

3 说明

– 所有器件均支持经典CAN 和2Mbps CAN FD

（灵活数据速率），而“G”选项支持5Mbps

– 具有较短的对称传播延迟时间和快速循环次数，

可增加时序裕量

这款 CAN 收发器系列符合 ISO1189-2 (2016) 高速

CAN（控制器局域网络）物理层标准。所有器件均设

计用于数据速率高达 2Mbps（兆位每秒）的 CAN FD

网络。器件型号包含“G”后缀的器件旨在实现高达

5Mbps 的数据速率，器件型号包含“V”后缀的器件配

有提供 I/O 电平的辅助电源输入，用于设置输入引脚阈

值和 RXD 输出电平。该系列具备低功耗待机模式及远

程唤醒请求特性。此外，所有器件都提供多种保护特性

来提高器件和网络的耐用性。

– 在有负载CAN 网络中实现更快的数据速率

• I/O 电压范围支持3.3V 和5V MCU

• 未供电时具有理想无源行为

– 总线和逻辑引脚处于高阻态

（无负载）

– 在总线和RXD 输出上实现上电/断电无干扰运行

• 保护特性

器件信息

封装⁽¹⁾

– HBM ESD 保护：±16kV

器件型号

封装尺寸

– IEC ESD 保护高达±15kV

– 总线故障保护：±58V（非H 型号）和±70V（H

型号）

SOIC (8)

VSON (8)

4.90mm × 3.91mm

3.00mm x 3.00mm

TCAN1042x

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

– V_CC和V_IO

（仅限V 型号）电源终端具有欠压保护

– 驱动器显性超时(TXD DTO) - 数据速率低至

10kbps

VCC

NC or VIO

VCC or VIO

– 热关断保护(TSD)

• 接收器共模输入电压：±30V

• 典型循环延迟：110ns

CANH

CANL

TSD

Dominant

time-out

TXD

VCC or VIO

• 结温范围为–55°C 至150°C

• 采用SOIC (8) 封装和无引线VSON (8) 封装

(3.0mm x 3.0mm)，提高了自动光学检测(AOI) 能

力

STB

Mode Select

UVP

VCC or VIO

Logic Output

2 应用

MUX

RXD

WUP Monitor

• 所有器件均支持高负载CAN 网络

• 重型机械ISOBUS 应用–

ISO 11783

Low Power Receiver

GND

A. 引脚5 的功能取决于器件；在不含V 后缀的器件上为无连接

(NC) 引脚，在包含V 后缀的器件上为用于I/O 电平转换的V_IO

引脚

• 工业自动化、控制、传感器和驱动系统

• 楼宇、安全和温度控制自动化

B. RXD 逻辑输出在不含“V”后缀的器件上驱动为V_CC，而在包

含“V”后缀的器件上驱动为V_IO。

功能方框图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLLSES7

TCAN1042H, TCAN1042HG

TCAN1042HGV, TCAN1042HV

ZHCSEK9D –MARCH 2016 –REVISED OCTOBER 2021

www.ti.com.cn

Table of Contents

9 Detailed Description......................................................18

9.1 Overview...................................................................18

9.2 Functional Block Diagram.........................................18

9.3 Feature Description...................................................19

9.4 Device Functional Modes..........................................22

10 Application and Implementation................................26

10.1 Application Information........................................... 26

10.2 Typical Applications................................................ 26

11 Power Supply Recommendations..............................29

12 Device and Documentation Support..........................32

12.1 接收文档更新通知................................................... 32

12.2 支持资源..................................................................32

12.3 Trademarks.............................................................32

12.4 Electrostatic Discharge Caution..............................32

12.5 术语表..................................................................... 32

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................4

6 Pin Configurations and Functions.................................5

7 Specifications.................................................................. 6

7.1 Absolute Maximum Ratings ....................................... 6

7.2 ESD Ratings............................................................... 6

7.3 ESD Ratings, Specifications....................................... 7

7.4 Recommended Operating Conditions.........................8

7.5 Thermal Information....................................................8

7.6 Power Rating.............................................................. 8

7.7 Electrical Characteristics.............................................9

7.8 Switching Characteristics..........................................12

7.9 Typical Characteristics..............................................13

8 Parameter Measurement Information..........................14

Information.................................................................... 32

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision C (April 2017) to Revision D (October 2021)

Page

• 删除的器件：TCAN1042、TCAN1042G、TCAN1042GV 和TCAN1042V........................................................1

• Added footnote to the GND pin in the Pin Functions table ................................................................................ 5

• Changed the DRB (VSON) values in the Thermal Information table .................................................................8

• Changed the title in 节9.3.7.1 ......................................................................................................................... 21

• Changed the title in 节9.3.7.2 ......................................................................................................................... 21

Changes from Revision B (August 2016) to Revision C (April 2017)

Page

• 删除了特性“符合2015 年12 月17 日发布的ISO 11898-2 物理层更新草案”................................................1

• 将特性从“符合发布的ISO 11898-2:2007 和ISO 11898-2:2003 物理层标准”更改为“符合ISO

11898-2:2016 和ISO 11898-5:2007 物理层标准”.............................................................................................1

• 将“特性”从“所有器件均支持2Mbps CAN FD..”更改为“所有器件均支持经典CAN 和2Mbps CAN FD..”

............................................................................................................................................................................1

• Changed Charged Device Model (CDM) From: ±750 To: ±1500 in the ESD Ratings table................................6

• Changed TBD to values for the DRB (VSON) Package in the ESD Ratings table.............................................6

• Added the Power Rating table ...........................................................................................................................8

• Changed V_SYMin the Driver Electrical Characteristics table.............................................................................. 9

• Changed V_{SYM_DC}in the Driver Electrical Characteristics table.........................................................................9

• Deleted "V_I= 0.4 sin (4E6 πt) + 2.5 V" from the Test Condition of C_Iin the Receiver Electrical

Characteristics table........................................................................................................................................... 9

• Deleted "V_I= 0.4 sin (4E6 πt)" in the Test Condition of C_IDin the Receiver Electrical Characteristics table....9

• Added "-30 V ≤V_CM≤+30" to the Test Condition of R_IDand R_INin the Receiver Electrical Characteristics

table....................................................................................................................................................................9

• Added Note 2 and Changed 表9-2, BUS OUTPUT column.............................................................................20

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ZHCSEK9D –MARCH 2016 –REVISED OCTOBER 2021

Changes from Revision A (May 2016) to Revision B (August 2016)

Page

• 添加了器件：TCAN1042、TCAN1042G、TCAN1042GV 和TCAN1042V........................................................1

• 将特性从添加了总线故障保护：±70V 更改为总线故障保护：±58V（非H 型号）和±70V（H 型号）............. 1

• 添加了特性“可采用SOIC(8) 封装和无引线VSON(8) 封装...”....................................................................... 1

• Added new devices to the Device Comparison Table ........................................................................................4

• Added the DRB package to the Thermal Information table ............................................................................... 8

• Changed the t_MODETYP value From: 1 µs To: 9 µS in the Switching Characteristics table............................. 12

• Changed Standby Mode section ......................................................................................................................23

Changes from Revision * (March 2016) to Revision A (May 2016)

Page

• 向器件信息表中添加了VSON (8) 引脚封装.......................................................................................................1

• Added the VSON (8) pin package to the Pin Configuration and Functions ....................................................... 5

• Changed OTP to TSD in the Functional Block Diagram ..................................................................................18

• Added Note 2 to 表9-1 ....................................................................................................................................20

• Added Note 1 to 表9-2 ....................................................................................................................................20

• Added pin number to the Layout Example image ............................................................................................31

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5 Device Comparison Table

DEVICE

5-Mbps FLEXIBLE DATA

RATE

3-V LEVEL SHIFTER

INTEGRATED

BUS FAULT PROTECTION

NUMBER

PIN 8 MODE SELECTION

TCAN1042 (Base)

TCAN1042G

±58 V

±70 V

TCAN1042GV

TCAN1042V

Low Power Standby Mode

with Remote Wake

TCAN1042H

TCAN1042HG

TCAN1042HGV

TCAN1042HV

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ZHCSEK9D –MARCH 2016 –REVISED OCTOBER 2021

6 Pin Configurations and Functions

STB

TXD

STB

TXD

GND

V_CC

GND

V_CC

CANH

CANL

CANH

CANL

RXD

图6-2. DRB Package for Base, (H), (G) and (HG)

Devices 8 PIN (VSON) Top View

图6-1. D Package for Base, (H), (G) and (HG)

Devices8 PIN (SOIC) Top View

STB

TXD

GND

V_CC

STB

TXD

GND

V_CC

CANH

CANL

V_IO

CANH

CANL

V_IO

RXD

图6-4. DRB Package for (V), (HV), (GV), and (HGV)

Devices 8 PIN (VSON) Top View

图6-3. D Package for (V), (HV), (GV), and (HGV)

Devices 8 PIN (SOIC) Top View

表6-1. Pin Functions

PINS

TYPE

DESCRIPTION

(V), (GV), (HV),

(HGV)

NAME

(H), (G), (HG)

TXD

GND⁽¹⁾

VCC

RXD

DIGITAL INPUT

GND

CAN transmit data input (LOW for dominant and HIGH for recessive bus states)

Ground connection

POWER

Transceiver 5-V supply voltage

DIGITAL OUTPUT CAN receive data output (LOW for dominant and HIGH for recessive bus states)

No Connect

—

POWER

V_IO

Transceiver I/O level shifting supply voltage (Devices with "V" suffix only)

Low level CAN bus input/output line

—

CANL

CANH

STB

BUS I/O

High level CAN bus input/output line

Standby Mode control input (active high)

DIGITAL INPUT

(1) For DRB (VSON) package options, the thermal pad may be connected to GND in order to optimize the thermal characteristics of the

package.

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7 Specifications

over operating free-air temperature range (unless otherwise noted) ^{(1) (2)}

7.1 Absolute Maximum Ratings

MIN

–0.3

MAX

UNIT

V_CC

V_IO

5-V Bus Supply Voltage Range

I/O Level-Shifting Voltage Range

All Devices

Devices with the "V" Suffix

CAN Bus I/O voltage range (CANH,

CANL)

V_BUS

Devices with the "H" Suffix

All Devices

-70

Logic input terminal voltage range (TXD,

V_{(Logic_Input)}

–0.3

+7 and V_I≤V_IO+ 0.3

V_{(Logic_Output)}

I_O(RXD)

T_J

Logic output terminal voltage range (RXD)

RXD (Receiver) output current

–0.3

–8

+7 and V_I≤V_IO+ 0.3

°C

Virtual junction temperature range (see Thermal Information table)

Storage temperature range (see Thermal Information table)

150

–55

–65

T_STG

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) All voltage values, except differential I/O bus voltages, are with respect to ground terminal.

7.2 ESD Ratings

TEST CONDITIONS

VALUE

UNIT

D (SOIC) Package

All terminals⁽¹⁾

±6000

±16000

±1500

±200

Human Body Model (HBM) ESD stress voltage

CAN bus terminals (CANH, CANL) to GND⁽²⁾

All terminals⁽³⁾

Charged Device Model (CDM) ESD stress voltage

Machine Model (MM)

All terminals⁽⁴⁾

DRB (VSON) Package

All terminals⁽¹⁾

±6000

±16000

±1500

±200

Human Body Model (HBM) ESD stress voltage

CAN bus terminals (CANH, CANL) to GND⁽²⁾

All terminals⁽³⁾

Charged Device Model (CDM) ESD stress voltage

Machine Model (MM)

All terminals⁽⁴⁾

(1) Tested in accordance to JEDEC Standard 22, Test Method A114.

(2) Test method based upon JEDEC Standard 22 Test Method A114, CAN bus is stressed with respect to GND.

(3) Tested in accordance to JEDEC Standard 22, Test Method C101.

(4) Tested in accordance to JEDEC Standard 22, Test Method A115.

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7.3 ESD Ratings, Specifications

TEST CONDITIONS

VALUE

UNIT

D (SOIC) Package

IEC 61000-4-2: Unpowered

Contact Discharge

±15000

±8000

±4000

CAN bus terminals (CANH,

CANL) to GND

System Level Electro-Static Discharge (ESD)

IEC 61000-4-2: Powered on

Contact Discharge

CAN bus terminals (CANH,

CANL) to GND

System Level Electrical fast transient (EFT)

IEC 61000-4-4: Criteria A

DRB (VSON) Package

IEC 61000-4-2: Unpowered

Contact Discharge

±14000

±8000

±4000

CAN bus terminals (CANH,

CANL) to GND

System Level Electro-Static Discharge (ESD)

System Level Electrical fast transient (EFT)

IEC 61000-4-2: Powered on

Contact Discharge

CAN bus terminals (CANH,

CANL) to GND

IEC 61000-4-4: Criteria A

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MAX UNIT

7.4 Recommended Operating Conditions

MIN

4.5

V_CC

5-V Bus Supply Voltage Range

5.5

V_IO

I/O Level-Shifting Voltage Range

RXD terminal HIGH level output current

RXD terminal LOW level output current

I_OH(RXD)

I_OL(RXD)

–2

7.5 Thermal Information

TCAN1042

Thermal Metric⁽¹⁾

TEST CONDITIONS

D (SOIC)

8 Pins

105.8

DRB (VSON)

8 Pins

48.3

UNIT

R_θJA

R_θJB

Junction-to-air thermal resistance

High-K thermal resistance⁽²⁾

°C/W

Junction-to-board thermal resistance⁽³⁾

46.8

17.2

Junction-to-case (top) thermal

resistance⁽⁴⁾

R_θJC(TOP)

Ψ_JT

48.3

8.7

37.6

1.8

°C/W

Junction-to-top characterization

parameter⁽⁵⁾

Junction-to-board characterization

parameter⁽⁶⁾

46.2

17.1

Ψ_JB

T_TSD

Thermal shutdown temperature

Thermal shutdown hysteresis

170

°C

T_{TSD_HYS}

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board,

as specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(4) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(5) The junction-to-top characterization parameter, Ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, Ψ_JBestimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

7.6 Power Rating

PARAMETER

TEST CONDITIONS

POWER DISSIPATION

UNIT

V_CC= 5 V, V_IO= 5 V (if applicable), T_J= 27°C, R_L= 60 Ω, S at 0

V, Input to TXD at 250 kHz, C_{L_RXD}= 15 pF. Typical CAN

operating conditions at 500 kbps with 25% transmission

(dominant) rate.

P_D

Average power dissipation

V_CC= 5.5 V, V_IO= 5.5 V (if applicable), T_J= 150°C, R_L= 50 Ω, S

at 0 V, Input to TXD at 500 kHz, C_{L_RXD}= 15 pF. Typical high

load CAN operating conditions at 1 Mbps with 50% transmission

(dominant) rate and loaded network.

124

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7.7 Electrical Characteristics

Over recommended operating conditions with T_A= –55°C to 125°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX UNIT

Supply Characteristics

See 图8-1, TXD = 0 V, R_L= 60 Ω,

C_L= open, R_CM= open, STB = 0 V, Typical

Bus Load

Normal mode

(dominant)

See 图8-1, TXD = 0 V, R_L= 50 Ω,

C_L= open, R_CM= open, STB = 0 V,

High Bus Load

Normal mode (dominant

–with bus fault)

See 图8-1, TXD = 0 V, STB = 0 V, CANH =

-12 V, R_L= open, C_L= open, R_CM= open

180

2.5

See 图8-1, TXD = V_CCor V_IO, R_L= 50 Ω, C_L

= open, R_CM= open,

STB = 0 V

Normal mode

(recessive)

I_CC

5-V supply current

1.5

0.5

Devices with the "V" suffix (I/O level-

shifting), V_CCnot needed in Standby mode,

See 图8-1,

TXD = V_IO, R_L= 50 Ω, C_L= open,

R_CM= open, STB = V_IO

Standby mode

Devices without the "V" suffix (5-V only),

µA

See 图8-1, TXD = V_CC, R_L= 50 Ω, C_L

open, R_CM= open, STB = V_CC

Normal mode

Standby mode

RXD floating, TXD = STB = 0 or 5.5 V

300

I_IO

I/O supply current

RXD floating, TXD = STB = V_IO

V_CC= 0 or 5.5 V

Rising undervoltage detection on V_CCfor

protected mode

4.2

4.4

UV_VCC

Falling undervoltage detection on V_CCfor

protected mode

All devices

3.8

1.3

4.0

4.25

V_HYS(UVVCC)

UV_VIO

Hysteresis voltage on UV_VCC

200

Undervoltage detection on V_IOfor protected

mode

2.75

Devices with the "V" suffix (I/O level-shifting)

V_HYS(UVVIO)

Hysteresis voltage on UV_VIOfor protected mode

STB Terminal (Mode Select Input)

Devices with the "V" suffix (I/O level-shifting)

Devices without the "V" suffix (5-V only)

Devices with the "V" suffix (I/O level-shifting)

Devices without the "V" suffix (5-V only)

STB = V_CC= V_IO= 5.5 V

0.7 x V_IO

V_IH

V_IL

High-level input voltage

Low-level input voltage

0.3 x V_IO

0.8

I_IH

High-level input leakage current

Low-level input leakage current

Unpowered leakage current

-2

–20

-1

I_IL

STB = 0V, V_CC= V_IO= 5.5 V

-2

µA

I_lkg(OFF)

STB = 5.5 V, V_CC= V_IO= 0 V

TXD Terminal (CAN Transmit Data Input)

Devices with the "V" suffix (I/O level-shifting)

Devices without the "V" suffix (5-V only)

Devices with the "V" suffix (I/O level-shifting)

Devices without the "V" suffix (5-V only)

TXD = V_CC= V_IO= 5.5 V

0.7 x V_IO

V_IH

V_IL

High-level input voltage

Low-level input voltage

0.3 x V_IO

0.8

I_IH

High-level input leakage current

Low-level input leakage current

Unpowered leakage current

Input capacitance

-25

–2.5

–100

–1

I_IL

TXD = 0 V, V_CC= V_IO= 5.5 V

µA

–7

I_lkg(OFF)

C_I

TXD = 5.5 V, V_CC= V_IO= 0 V

V_IN= 0.4 x sin(2 x πx 2 x 10⁶x t) + 2.5 V

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MAX UNIT

7.7 Electrical Characteristics (continued)

Over recommended operating conditions with T_A= –55°C to 125°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

RXD Terminal (Can Receive Data Output)

Devices with the "V" suffix (I/O level-

shifting), See 图8-2,

0.8 × V_IO

I_O= –2 mA.

V_OH

High-level output voltage

Devices without the "V" suffix

(5V only), See 图8-2,

I_O= –2 mA.

4.6

Devices with the "V" suffix (I/O level-

shifting), See 图8-2, I_O= +2 mA.

0.2 x V_IO

V_OL

Low-level output voltage

Devices without the "V" suffix (5-V only),

See 图8-2,

0.2

0.4

I_O= +2 mA.

I_lkg(OFF)

Unpowered leakage current

RXD = 5.5 V, V_CC= 0 V, V_IO= 0 V

µA

–1

Driver Electrical Characteristics

CANH

CANL

2.75

0.5

4.5

See 图8-1 and 图9-3, TXD = 0 V, STB = 0

V, 50 Ω ≤R_L≤65 Ω,

C_L= open, R_CM= open

Bus output voltage

(dominant)

V_O(DOM)

2.25

See 图8-1 and 图9-3, TXD = V_CCor V_IO

V_IO= V_CC, STB = 0 V ,

R_L= open (no load), R_CM= open

Bus output voltage

(recessive)

V_O(REC)

CANH and CANL

0.5 × V_CC

CANH

-0.1

-0.2

0.1

0.2

Bus output voltage

V_O(STB)

See 图8-1 and 图9-3, STB = V_IO, R_L

open (no load), R_CM= open

CANL

(Standby mode)

CANH - CANL

See 图8-1 and 图9-3, TXD = 0 V, STB = 0

V, 45 Ω ≤R_L< 50 Ω,

1.4

1.5

C_L= open, R_CM= open

Differential output

V_OD(DOM)

See 图8-1 and 图9-3, TXD = 0 V, STB = 0

V, 50 Ω ≤R_L≤65 Ω,

C_L= open, R_CM= open

CANH - CANL

voltage (dominant)

See 图8-1 and 图9-3, TXD = 0 V, STB = 0

V, R_L= 2240 Ω, C_L= open, R_CM= open

1.5

See 图8-1 and 图9-3, TXD = V_CC, STB = 0

V, R_L= 60 Ω, C_L= open, R_CM= open

–120

Differential output

V_OD(REC)

CANH - CANL

See 图8-1 and 图9-3, TXD = V_CC, STB = 0

voltage (recessive)

V, R_L= open (no load), C_L= open, R_CM

open

–50

See 图8-1 and 图10-2, STB at 0 V, R_term

60 Ω, C_split= 4.7 nF, C_L= open,

Output symmetry (dominant or recessive)

( V_O(CANH)+ V_O(CANL)) / V_CC

V_SYM

0.9

–0.4

–100

1.1

0.4

V/V

R_CM= open, T_XD= 250 kHz, 1 MHz

DC Output symmetry (dominant or recessive)

See 图8-1 and 图9-3, STB = 0 V,

R_L= 60 Ω, C_L= open, R_CM= open

V_{SYM_DC}

(V_CC–V_O(CANH)–V_O(CANL)

)

See 图9-3 and 图8-7, STB at 0 V, V_CANH

-5 V to 40 V, CANL = open,

TXD = 0 V

Short-circuit steady-state output current,

dominant, Normal mode

I_{OS(SS_DOM)}

See 图9-3 and 图8-7, STB at 0 V, V_CANL

-5 V to 40 V, CANH = open,

TXD = 0 V

100

See 图9-3 and 图8-7, STB at 0 V, –27 V

≤V_BUS≤32 V,

Where V_BUS= CANH = CANL, TXD = V_CC

Short-circuit steady-state output current,

recessive, Normal mode

I_{OS(SS_REC)}

–5

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7.7 Electrical Characteristics (continued)

Over recommended operating conditions with T_A= –55°C to 125°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX UNIT

Receiver Electrical Characteristics

V_CM

V_IT+

Common mode range, Normal mode

-30

+30

900

See 图8-2 and 表8-1, STB = 0 V

Positive-going input threshold voltage, Normal

mode

See 图8-2, 表9-5 and 表8-1,

STB = 0 V, -20 V ≤V_CM≤+20 V

Negative-going input threshold voltage, Normal

mode

V_IT–

V_IT+

V_IT–

V_HYS

500

400

Positive-going input threshold voltage, Normal

mode

1000

See 图8-2, 表9-5 and 表8-1,

STB = 0 V, -30 V ≤V_CM≤+30 V

Negative-going input threshold voltage, Normal

mode

See 图8-2, 表9-5 and 表8-1,

STB = 0 V

Hysteresis voltage (V_IT+- V_IT–), Normal mode

120

Devices with the "V" suffix (I/O level-

shifting), See 图8-2, 表9-5 and 表8-1, STB

= V_IO, 4.5 V ≤V_IO≤5.5 V

-12

-2

Devices with the "V" suffix (I/O level-

shifting), See 图8-2, 表9-5 and 表8-1, STB

= V_IO, 3.0 V ≤V_IO≤4.5 V

V_CM

Common mode range, Standby mode

Input threshold voltage, Standby mode

Devices without the "V" suffix (5V only), See

图8-2, 表9-5 and 表8-1, STB = V_CC

-12

V_IT(STANDBY)

STB = V_CCor V_IO

400

1150

4.8

µA

I_LKG(IOFF)

C_I

Power-off (unpowered) bus input leakage current CANH = CANL = 5 V, V_CC= V_IO= 0 V

Input capacitance to ground (CANH or CANL)

Differential input capacitance (CANH to CANL)

Differential input resistance

TXD = V_CC, V_IO= V_CC

C_ID

R_ID

TXD = V_CC= V_IO= 5 V, STB = 0 V,

-30 V ≤V_CM≤+30 V

kΩ

R_IN

Input resistance (CANH or CANL)

Input resistance matching:

[1 –R_IN(CANH)/ R_IN(CANL)] × 100%

R_IN(M)

V_CANH= V_CANL= 5 V

+2%

–2%

(1) All typical values are at 25°C and supply voltages of V_CC= 5 V and V_IO= 5 V (if applicable), R_L= 60 Ω.

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7.8 Switching Characteristics

Over recommended operating conditions with T_A= -55°C to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾MAX UNIT

Device Switching Characteristics

Total loop delay, driver input (TXD) to receiver

output (RXD), recessive to dominant

t_PROP(LOOP1)

t_PROP(LOOP2)

100

110

160

175

See 图8-4, STB = 0 V,

R_L= 60 Ω,

Total loop delay, driver input (TXD) to receiver

output (RXD), dominant to recessive

C_L= 100 pF, C_L(RXD)= 15 pF

Mode change time, from Normal to Standby or

from Standby to Normal

t_MODE

45 µs

See 图8-3

t_{WK_FILTER}

Filter time for valid wake up pattern

0.5

1.85 µs

Driver Switching Characteristics

Propagation delay time, high TXD to driver

t_pHR

recessive (dominant to recessive)

Propagation delay time, low TXD to driver

dominant (recessive to dominant)

See 图8-1, STB = 0 V,

R_L= 60 Ω,

C_L= 100 pF, R_CM= open

t_pLD

t_sk(p)

t_R

Pulse skew (|t_pHR- t_pLD|)

Differential output signal rise time

Differential output signal fall time

t_F

See 图8-6, STB = 0 V,

R_L= 60 Ω, C_L= open

t_{TXD_DTO}

Dominant timeout

1.2

3.8 ms

Receiver Switching Characteristics

Propagation delay time, bus recessive input to

t_pRH

high output (Dominant to Recessive)

Propagation delay time, bus dominant input to

low output (Recessive to Dominant)

See 图8-2, STB = 0 V,

C_L(RXD)= 15 pF

t_pDL

t_R

t_F

RXD Output signal rise time

RXD Output signal fall time

FD Timing Parameters

Bit time on CAN bus output pins with t_BIT(TXD)

435

155

400

120

-65

530

210

500 ns, all devices

t_BIT(BUS)

t_BIT(RXD)

Δt_REC

Bit time on CAN bus output pins with t_BIT(TXD)

200 ns, G device variants only

Bit time on RXD output pins with t_BIT(TXD)

500 ns, all devices

See 图8-5 , STB = 0 V,

R_L= 60 Ω, C_L= 100 pF,

C_L(RXD)= 15 pF,

550

Bit time on RXD output pins with t_BIT(TXD)

200 ns, G device variants only

220

Δt_REC= t_BIT(RXD)- t_BIT(BUS)

Receiver timing symmetry with t_BIT(TXD)= 500

ns, all devices

Receiver timing symmetry with t_BIT(TXD)= 200

ns, G device variants only

-45

(1) All typical values are at 25°C and supply voltages of V_CC= 5 V and V_IO= 5 V (if applicable), R_L= 60 Ω

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7.9 Typical Characteristics

2.5

1.5

0.5

4.5 4.6 4.7 4.8 4.9

V_CC(V)

5.1 5.2 5.3 5.4 5.5

-55

-35

-15

25 45

Temperature (°C)

105 125

D002

D001

V_IO= 5 V

STB = 0 V

RCM = Open

V_CC= 5 V

C_L= Open

V_IO= 3.3 V

R_L= 60 Ω

C_L= Open

Temp = 25°C

RCM = Open

STB = 0 V

图7-2. V_OD(D)over V_CC

图7-1. V_OD(D)over Temperature

1.48

150

125

100

1.47

1.46

1.45

1.44

1.43

1.42

1.41

-55

-35

-15

25 45

Temperature (°C)

105 125

-35

-15

25 45

Temperature (°C)

105 125

D003

D004

V_CC= 5 V

C_L= Open

V_IO= 3.3 V

R_L= 60 Ω

V_CC= 5 V

V_IO= 3.3 V

R_L= 60 Ω

RCM = Open

STB = 0 V

C_L= 100 pF

C_{L_RXD}= 15 pF

STB = 0 V

图7-3. I_CCRecessive over Temperature

图7-4. Total Loop Delay over Temperature

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8 Parameter Measurement Information

R_CM

CANH

V_CC

50%

t_pLD

0.9V

50%

t_pHR

TXD

R_L

C_L

V_OD

V_CM

V_O(CANH)

90%

10%

CANL

R_CM

V_O(CANL)

V_OD

0.5V

t_R

t_F

图8-1. Driver Test Circuit and Measurement

CANH

1.5V

0.9V

V_ID

I_O

RXD

0.5V

V_ID

t_pDL

t_pRH

V_OH

V_O

C_{L_RXD}

CANL

90%

V_O(RXD)

50%

10%

V_OL

t_F

t_R

图8-2. Receiver Test Circuit and Measurement

表8-1. Receiver Differential Input Voltage Threshold Test

INPUT (See Receiver Test Circuit and Measurement

OUTPUT

V_CANH

V_CANL

-30.5 V

29.5 V

|V_ID|

1000 mV

900 mV

500 mV

400 mV

RXD

-29.5 V

30.5 V

V_OL

-19.55 V

20.45 V

-19.75 V

20.25 V

-29.8 V

30.2 V

-20.45 V

19.55 V

-20.25 V

19.75 V

-30.2 V

29.8 V

V_OH

Open

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CANH

CANL

V_IH

TXD

V_I

R_L

C_L

STB

50%

STB

t_MODE

RXD

V_OH

V_O

C_{L_RXD}

RXD

50%

V_OL

图8-3. t_MODETest Circuit and Measurement

CANH

V_CC

TXD

STB

V_I

C_L

R_L

50%

TXD

CANL

t_PROP(LOOP2)

t_PROP(LOOP1)

RXD

V_OH

V_O

C_{L_RXD}

50%

RXD

V_OL

图8-4. T_PROP(LOOP)Test Circuit and Measurement

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V_I

70%

TXD

CANH

30%

900mV

V_OH

TXD

V_I

R_L

C_L

5 x t_BIT

t_BIT(TXD)

CANL

t_BIT(BUS)

STB

V_DIFF

RXD

500mV

V_O

C_{L_RXD}

70%

RXD

30%

V_OL

t_BIT(RXD)

图8-5. CAN FD Timing Parameter Measurement

CANH

R_L

V_IH

TXD

C_L

V_OD

V_OD(D)

CANL

0.9V

V_OD

0.5V

t_{TXD_DTO}

图8-6. TXD Dominant Timeout Test Circuit and Measurement

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200 ꢀs

I_OS

CANH

CANL

TXD

V_BUS

I_OS

V_BUS

图8-7. Driver Short Circuit Current Test and Measurement

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9 Detailed Description

9.1 Overview

These CAN transceivers meet the ISO11898-2 (2016) High Speed CAN (Controller Area Network) physical layer

standard. They are designed for data rates in excess of 1 Mbps for CAN FD and enhanced timing margin /

higher data rates in long and highly-loaded networks. These devices provide many protection features to

enhance device and CAN robustness.

9.2 Functional Block Diagram

VCC

NC or VIO

VCC or VIO

CANH

CANL

TSD

Dominant

time-out

TXD

VCC or VIO

STB

Mode Select

UVP

VCC or VIO

Logic Output

MUX

RXD

WUP Monitor

Low Power Receiver

GND

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9.3 Feature Description

9.3.1 TXD Dominant Timeout (DTO)

During normal mode (the only mode where the CAN driver is active), the TXD DTO circuit prevents the

transceiver from blocking network communication in the event of a hardware or software failure where TXD is

held dominant longer than the timeout period t_{TXD_DTO}. The DTO circuit timer starts on a falling edge on TXD.

The DTO circuit disables the CAN bus driver if no rising edge is seen before the timeout period expires. This

frees the bus for communication between other nodes on the network. The CAN driver is re-activated when a

recessive signal is seen on the TXD terminal, thus clearing the TXD DTO condition. The receiver and RXD

terminal still reflect activity on the CAN bus, and the bus terminals are biased to the recessive level during a TXD

dominant timeout.

TXD fault stuck dominant: example PCB

failure or bad software

Fault is repaired & transmission

capability restored

TXD

(driver)

t_{TXD_DTO}

Driver disabled freeing bus for other nodes

Bus would be —stuck dominant“ blocking communication for the

whole network but TXD DTO prevents this and frees the bus for

Normal CAN

communication

communication after the time t_{TXD_DTO}

CAN

Bus

Signal

t_{TXD_DTO}

Communication from

other bus node(s)

Communication from

repaired node

RXD

(receiver)

Communication from

other bus node(s)

Communication from

repaired local node

Communication from

local node

图9-1. Example Timing Diagram for TXD DTO

备注

The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum possible

transmitted data rate of the device. The CAN protocol allows a maximum of eleven successive

dominant bits (on TXD) for the worst case, where five successive dominant bits are followed

immediately by an error frame. This, along with the t_{TXD_DTO}minimum, limits the minimum data rate.

Calculate the minimum transmitted data rate by: Minimum Data Rate = 11 / t_{TXD_DTO}

9.3.2 Thermal Shutdown (TSD)

If the junction temperature of the device exceeds the thermal shutdown threshold (T_TSD), the device turns off the

CAN driver circuits thus blocking the TXD-to-bus transmission path. The CAN bus terminals are biased to the

recessive level during a thermal shutdown, and the receiver-to-RXD path remains operational. The shutdown

condition is cleared when the junction temperature drops at least the thermal shutdown hysteresis temperature

(T_{TSD_HYS}) below the thermal shutdown temperature (T_TSD) of the device.

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9.3.3 Undervoltage Lockout

The supply terminals have undervoltage detection that places the device in protected mode. This protects the

bus during an undervoltage event on either the V_CCor V_IOsupply terminals.

表9-1. Undervoltage Lockout 5 V Only Devices (Devices without the "V" Suffix)

V_CC

DEVICE STATE⁽¹⁾

BUS OUTPUT

RXD

> UV_VCC

< UV_VCC

Normal

Per TXD

Mirrors Bus⁽²⁾

Protected

High Impedance

(1) See the V_ITsection of the Electrical Characteristics.

(2) Mirrors bus state: low if CAN bus is dominant, high if CAN bus is recessive.

表9-2. Undervoltage Lockout I/O Level Shifting Devices (Devices with the "V" Suffix)

V_CC

V_IO

DEVICE STATE

BUS OUTPUT

RXD

> UV_VCC

> UV_VIO

Normal

Per TXD

Mirrors Bus⁽¹⁾

STB = High: Standby Mode

Recessive

Bus Wake RXD Request⁽²⁾

< UV_VCC

> UV_VIO

STB =Low: Protected

Mode

High Impedance

High (Recessive)

> UV_VCC

< UV_VCC

< UV_VIO

Protected

High Impedance

(1) Mirrors bus state: low if CAN bus is dominant, high if CAN bus is recessive.

(2) Refer to 节9.4.3.1

备注

After an undervoltage condition is cleared and the supplies have returned to valid levels, the device

typically resumes normal operation within 50 µs.

9.3.4 Unpowered Device

The device is designed to be 'ideal passive' or 'no load' to the CAN bus if it is unpowered. The bus terminals

(CANH, CANL) have extremely low leakage currents when the device is unpowered to avoid loading down the

bus. This is critical if some nodes of the network are unpowered while the rest of the of network remains in

operation. The logic terminals also have extremely low leakage currents when the device is unpowered to avoid

loading down other circuits that may remain powered.

9.3.5 Floating Terminals

These devices have internal pull ups on critical terminals to place the device into known states if the terminals

float. The TXD terminal is pulled up to V_CCor V_IOto force a recessive input level if the terminal floats. The STB

terminal is also pulled up to force the device into low power Standby mode if the terminal floats.

9.3.6 CAN Bus Short Circuit Current Limiting

The device has two protection features that limit the short circuit current when a CAN bus line is short-circuit fault

condition: driver current limiting (both dominant and recessive states) and TXD dominant state time out to

prevent permanent higher short circuit current of the dominant state during a system fault. During CAN

communication the bus switches between dominant and recessive states, thus the short circuit current may be

viewed either as the instantaneous current during each bus state or as an average current of the two states. For

system current (power supply) and power considerations in the termination resistors and common-mode choke

ratings, use the average short circuit current. Determine the ratio of dominant and recessive bits by the data in

the CAN frame plus the following factors of the protocol and PHY that force either recessive or dominant at

certain times:

• Control fields with set bits

• Bit stuffing

• Interframe space

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• TXD dominant time out (fault case limiting)

These ensure a minimum recessive amount of time on the bus even if the data field contains a high percentage

of dominant bits. The short circuit current of the bus depends on the ratio of recessive to dominant bits and their

respective short circuit currents. The average short circuit current may be calculated with the following formula:

I_OS(AVG)= %Transmit × [(%REC_Bits × I_{OS(SS)_REC}) + (%DOM_Bits × I_{OS(SS)_DOM})] + [%Receive × I_{OS(SS)_REC}

]

(1)

Where:

• I_OS(AVG)is the average short circuit current

• %Transmit is the percentage the node is transmitting CAN messages

• %Receive is the percentage the node is receiving CAN messages

• %REC_Bits is the percentage of recessive bits in the transmitted CAN messages

• %DOM_Bits is the percentage of dominant bits in the transmitted CAN messages

• I_{OS(SS)_REC}is the recessive steady state short circuit current

• I_{OS(SS)_DOM}is the dominant steady state short circuit current

备注

Consider the short circuit current and possible fault cases of the network when sizing the power

ratings of the termination resistance and other network components.

9.3.7 Digital Inputs and Outputs

9.3.7.1 Devices with V_CCOnly (Devices without the "V" Suffix):

The 5-V V_CConly devices are supplied by a single 5-V rail. The digital inputs have TTL input thresholds and are

therefore 5 V and 3.3 V compatible. The RXD outputs on these devices are driven to the V_CCrail for logic high

output. Additionally, the TXD and STB pins are internally pulled up to V_CC. The internal bias of the mode pins

may only place the device into a known state if the terminals float, they may not be adequate for system-level

biasing during transients or noisy environments.

备注

TXD pull up strength and CAN bit timing require special consideration when these devices are used

with CAN controllers with an open-drain TXD output. An adequate external pull up resistor must be

used to ensure that the CAN controller output of the microcontroller maintains adequate bit timing to

the TXD input.

9.3.7.2 Devices with V_IOI/O Level Shifting (Devices with "V" Suffix):

These devices use a 5 V V_CCpower supply for the CAN driver and high speed receiver blocks. These

transceivers have a second power supply for I/O level-shifting (V_IO). This supply is used to set the CMOS input

thresholds of the TXD and pins and the RXD high level output voltage. Additionally, the internal pull ups on TXD

and STB are pulled up to V_IO.

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9.4 Device Functional Modes

The device has two main operating modes: Normal mode and Standby mode. Operating mode selection is made

via the STB input terminal.

表9-3. Operating Modes

STB Terminal

LOW

MODE

DRIVER

RECEIVER

RXD Terminal

Normal Mode

Standby Mode

Enabled (ON)

Disabled (OFF)

Enabled (ON)

Mirrors Bus State⁽¹⁾

HIGH

Disabled (OFF) (Low

Power Bus Monitor is

Active)

High (Unless valid WUP

has been received)

(1) Mirrors bus state: low if CAN bus is dominant, high if CAN bus is recessive.

9.4.1 CAN Bus States

The CAN bus has two states during powered operation of the device: dominant and recessive. A dominant bus

state is when the bus is driven differentially, corresponding to a logic low on the TXD and RXD terminal. A

recessive bus state is when the bus is biased to V_CC/ 2 via the high-resistance internal input resistors R_INof the

receiver, corresponding to a logic high on the TXD and RXD terminals.

图9-2. Bus States (Physical Bit Representation)

图9-3. Bias Unit (Recessive Common Mode Bias) and Receiver

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9.4.2 Normal Mode

Select the Normal mode of device operation by setting STB terminal low. The CAN driver and receiver are fully

operational and CAN communication is bi-directional. The driver translates a digital input on TXD to a differential

output on CANH and CANL. The receiver translates the differential signal from CANH and CANL to a digital

output on RXD.

9.4.3 Standby Mode

Activate low power Standby mode by setting STB terminal high. In this mode the bus transmitter will not send

data nor will the normal mode receiver accept data as the bus lines are biased to ground minimizing the system

supply current. Only the low power receiver will be actively monitoring the bus for activity. RXD indicates a valid

wake up event after a wake-up pattern (WUP) has been detected on the Bus. The low power receiver is powered

using only the V_IOpin. This allows V_CCto be removed reducing power consumption further.

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9.4.3.1 Remote Wake Request via Wake Up Pattern (WUP) in Standby Mode

The TCAN1042 family offers a remote wake request feature that is used to indicate to the host microcontroller

that the bus is active and the node should return to normal operation.

These devices use the multiple filtered dominant wake up pattern (WUP) from the ISO11898-2 (2016) to qualify

bus activity. Once a valid WUP has been received the wake request will be indicated to the microcontroller by a

falling edge and low corresponding to a "filtered" dominant on the RXD output terminal.

The WUP consists of a filtered dominant pulse, followed by a filtered recessive pulse, and finally by a second

filtered dominant pulse. These filtered dominant, recessive, dominant pulses do not need to occur in immediate

succession. There is no timeout that will occur between filtered bits of the WUP. Once a full WUP has been

detected the device will continue to drive the RXD output low every time an additional filtered dominant signal is

received from the bus.

For a dominant or recessive signal to be considered "filtered", the bus must continually remain in that state for

more than t_{WK_FILTER}. Due to variability in the t_{WK_FILTER}, the following three scenarios can exist:

1. Bus signals that last less than t_{WK_FILTER(MIN)}will never be detected as part of a valid WUP

2. Bus signals that last more than t_{WK_FILTER(MIN)}but less than t_{WK_FILTER(MAX)}may be detected as part of a

valid WUP

3. Bus signals that last more than t_{WK_FILTER(MAX)}will always be detected as part of a valid WUP

Once the first filtered dominant signal is received, the device is now waiting on a filtered recessive signal, other

bus traffic will not reset the bus monitor. Once the filtered recessive signal is received, the monitor is now waiting

on a second filtered dominant signal, and again other bus traffic will not reset the monitor. After reception of the

full WUP, the device will transition to driving the RXD output pin low for the remainder of any dominant signal that

remains on the bus for longer than t_{WK_FILTER}

Bus Wake via

RXD Request

Wake Up Pattern (WUP)

Filtered

Dominant

Filtered

Dominant

Filtered

Recessive

Waiting for

Filtered

Dominant

Waiting for

Filtered

Recessive

Bus

Bus V_Diff

RXD

≥ t_{WK_FILTER}

Filtered Dominant RXD Output

Bus Wake Via

RXD Requests

图9-4. Wake Up Pattern (WUP)

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9.4.4 Driver and Receiver Function Tables

表9-4. Driver Function Table

INPUTS

OUTPUTS

DEVICE

DRIVEN BUS STATE

CANL⁽¹⁾

STB ⁽¹⁾

TXD^{(1) (2)}

CANH⁽¹⁾

H or Open

Dominant

Recessive

All Devices

H or Open

(1) H = high level, L = low level, X = irrelevant, Z = common mode (recessive) bias to V_CC/ 2. See CAN Bus States for bus state and

common mode bias information.

(2) Devices have an internal pull up to V_CCor V_IOon TXD terminal. If the TXD terminal is open, the terminal is pulled high and the

transmitter remain in recessive (non-driven) state.

表9-5. Receiver Function Table

CAN DIFFERENTIAL INPUTS

DEVICE MODE

BUS STATE

RXD TERMINAL⁽¹⁾

V_ID= V_CANH–V_CANL

Dominant

L⁽²⁾

V_ID≥V_IT+(MAX)

(2)

V_IT-(MIN)< V_ID< V_IT+(MAX)

V_ID≤V_IT-(MIN)

Normal

Recessive

Open

H⁽²⁾

Open (V_ID≈0 V)

(1) H = high level, L = low level, ? = indeterminate.

(2) See Receiver Electrical Characteristics section for input thresholds.

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10 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

10.1 Application Information

These CAN transceivers are typically used in applications with a host microprocessor or FPGA that includes the

data link layer portion of the CAN protocol. Below are typical application configurations for both 5 V and 3.3 V

microprocessor applications. The bus termination is shown for illustrative purposes.

10.2 Typical Applications

Node n

(with termination)

Node 1

Node 2

Node 3

MCU or DSP

CAN

Controller

CAN

Controller

CAN

Controller

CAN

Controller

CAN

Transceiver

CAN

Transceiver

CAN

Transceiver

CAN

Transceiver

R_TERM

图10-1. Typical CAN Bus Application

10.2.1 Design Requirements

10.2.1.1 Bus Loading, Length and Number of Nodes

The ISO 11898-2 Standard specifies a maximum bus length of 40 m and maximum stub length of 0.3 m.

However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a

bus. A large number of nodes requires transceivers with high input impedance such as the TCAN1042 family of

transceivers.

Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO

11898-2. They have made system-level trade-offs for data rate, cable length, and parasitic loading of the bus.

Examples of some of these specifications are ARINC825, CANopen, DeviceNet and NMEA2000.

The TCAN1042 family is specified to meet the 1.5 V requirement with a 50Ω load, incorporating the worst case

including parallel transceivers. The differential input resistance of the TCAN1042 family is a minimum of 30 kΩ. If

100 TCAN1042 family transceivers are in parallel on a bus, this is equivalent to a 300Ω differential load worst

case. That transceiver load of 300 Ω in parallel with the 60Ω gives an equivalent loading of 50 Ω. Therefore, the

TCAN1042 family theoretically supports up to 100 transceivers on a single bus segment. However, for CAN

network design margin must be given for signal loss across the system and cabling, parasitic loadings, network

imbalances, ground offsets and signal integrity thus a practical maximum number of nodes is typically much

lower. Bus length may also be extended beyond the original ISO 11898 standard of 40 m by careful system

design and data rate tradeoffs. For example, CANopen network design guidelines allow the network to be up to

1 km with changes in the termination resistance, cabling, less than 64 nodes and significantly lowered data rate.

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This flexibility in CAN network design is one of the key strengths of the various extensions and additional

standards that have been built on the original ISO 11898-2 CAN standard. In using this flexibility comes the

responsibility of good network design and balancing these tradeoffs.

10.2.2 Detailed Design Procedures

10.2.2.1 CAN Termination

The ISO 11898 standard specifies the interconnect to be a twisted pair cable (shielded or unshielded) with 120-

Ω characteristic impedance (Z_O). Resistors equal to the characteristic impedance of the line should be used to

terminate both ends of the cable to prevent signal reflections. Unterminated drop lines (stubs) connecting nodes

to the bus should be kept as short as possible to minimize signal reflections. The termination may be on the

cable or in a node, but if nodes may be removed from the bus, the termination must be carefully placed so that

two terminations always exist on the network.

Termination may be a single 120-Ω resistor at the end of the bus, either on the cable or in a terminating node. If

filtering and stabilization of the common mode voltage of the bus is desired, then split termination may be used.

(See 图 10-2). Split termination improves the electromagnetic emissions behavior of the network by eliminating

fluctuations in the bus common-mode voltages at the start and end of message transmissions.

Standard Termination

Split Termination

CANH

R_TERM/2

CAN

Transceiver

CAN

Transceiver

R_TERM

C_SPLIT

R_TERM/2

CANL

图10-2. CAN Bus Termination Concepts

The family of transceivers have variants for both 5-V only applications and applications where level shifting is

needed for a 3.3-V microcontroller.

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图10-3. Typical CAN Bus Application Using 5V CAN Controller

图10-4. Typical CAN Bus Application Using 3.3 V CAN Controller

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10.2.3 Application Curves

4.5 4.6 4.7 4.8 4.9

V_CC(V)

5.1 5.2 5.3 5.4 5.5

D005

V_CC= 4.5 V to 5.5 V

C_L= Open

V_IO= 3.3 V

Temp = 25°C

R_L= 60 Ω

STB = 0 V

图10-5. I_CCDominant Current over V_CCSupply Voltage

11 Power Supply Recommendations

These devices are designed to operate from a V_CCinput supply voltage range between 4.5 V and 5.5 V. Some

devices have an output level shifting supply input, V_IO, designed for a range between 3 V and 5.5 V. Both supply

inputs must be well regulated. A bulk capacitance, typically 4.7 μF, should be placed near the CAN transceiver's

main V_CCsupply output, and in addition a bypass capacitor, typically 0.1 μF, should be placed as close to the

device V_CCand V_IOsupply terminals. This helps to reduce supply voltage ripple present on the outputs of the

switched-mode power supplies and also helps to compensate for the resistance and inductance of the PCB

power planes and traces.

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Layout

Robust and reliable bus node design often requires the use of external transient protection device in order to

protect against EFT and surge transients that may occur in industrial environments. Because ESD and transients

have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high-frequency layout techniques must

be applied during PCB design. The family comes with high on-chip IEC ESD protection, but if higher levels of

system level immunity are desired external TVS diodes can be used. TVS diodes and bus filtering capacitors

should be placed as close to the on-board connectors as possible to prevent noisy transient events from

propagating further into the PCB and system.

12.1 Layout Guidelines

• Place the protection and filtering circuitry as close to the bus connector, J1, to prevent transients, ESD and

noise from propagating onto the board. In this layout example a transient voltage suppression (TVS) device,

D1, has been used for added protection. The production solution can be either bi-directional TVS diode or

varistor with ratings matching the application requirements. This example also shows optional bus filter

capacitors C4 and C5. Additionally (not shown) a series common mode choke (CMC) can be placed on the

CANH and CANL lines between the transceiver U1 and connector J1.

• Design the bus protection components in the direction of the signal path. Do not force the transient current to

divert from the signal path to reach the protection device.

• Use supply (V_CC) and ground planes to provide low inductance.

备注

High-frequency currents follows the path of least impedance and not the path of least resistance.

• Use at least two vias for supply (V_CC) and ground connections of bypass capacitors and protection devices to

minimize trace and via inductance.

• Bypass and bulk capacitors should be placed as close as possible to the supply terminals of transceiver,

examples are C1, C2 on the V_CCsupply and C6 and C7 on the V_IOsupply.

• Bus termination: this layout example shows split termination. This is where the termination is split into two

resistors, R6 and R7, with the center or split tap of the termination connected to ground via capacitor C3. Split

termination provides common mode filtering for the bus. When bus termination is placed on the board instead

of directly on the bus, additional care must be taken to ensure the terminating node is not removed from the

bus thus also removing the termination. See the application section for information on power ratings needed

for the termination resistor(s).

• To limit current of digital lines, serial resistors may be used. Examples are R2, R3, and R4. These are not

required.

• Terminal 1: R1 is shown optionally for the TXD input of the device. If an open drain host processor is used,

this is mandatory to ensure the bit timing into the device is met.

• Terminal 5: For "V" variants of the family, bypass capacitors should be placed as close to the pin as possible

(example C6 and C7). For device options without V_IOI/O level shifting, this pin is not internally connected and

can be left floating or tied to any existing net, for example a split pin connection.

• Terminal 8: is shown assuming the mode terminal, STB, will be used. If the device will only be used in normal

mode, R4 is not needed and R5 could be used for the pull down resistor to GND.

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12.2 Layout Example

STB

V_{CC or}V_IO

TXD

GND

V_CC

GND

V_IO

RXD

GND

图12-1. Layout Example

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12 Device and Documentation Support

12.1 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.2 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.3 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.5 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TCAN1042HD

LIFEBUY

ACTIVE

SOIC

RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-55 to 125

1042

TCAN1042HDR

2500 RoHS & Green

Samples

TCAN1042HGD

LIFEBUY

ACTIVE

SOIC

RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-55 to 125

1042

TCAN1042HGDR

2500 RoHS & Green

Samples

TCAN1042HGVD

TCAN1042HGVDR

ACTIVE

SOIC

RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-55 to 125

1042V

2500 RoHS & Green

TCAN1042HVD

LIFEBUY

ACTIVE

SOIC

RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-55 to 125

1042V

TCAN1042HVDR

2500 RoHS & Green

Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

17-Jun-2023

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TCAN1042H, TCAN1042HG, TCAN1042HGV, TCAN1042HV :

Automotive : TCAN1042H-Q1, TCAN1042HG-Q1, TCAN1042HGV-Q1, TCAN1042HV-Q1

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

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22-Jul-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TCAN1042HDR

TCAN1042HGDR

TCAN1042HGVDR

TCAN1042HVDR

SOIC

2500

330.0

12.4

12.5

12.4

6.4

5.2

2.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

22-Jul-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TCAN1042HDR

TCAN1042HGDR

TCAN1042HGVDR

TCAN1042HVDR

SOIC

2500

356.0

340.5

356.0

336.1

356.0

35.0

25.0

35.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

22-Jul-2023

TUBE

T - Tube

height

L - Tube length

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device

Package Name Package Type

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

TCAN1042HD

TCAN1042HGD

TCAN1042HGVD

TCAN1042HVD

SOIC

507

3940

4.32

Pack Materials-Page 3

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TCAN1042HGD [TI]

相关型号：

TCAN1042HGDQ1

TCAN1042HGDR

TCAN1042HGDRBRQ1

TCAN1042HGDRBTQ1

TCAN1042HGDRQ1

TCAN1042HGV

TCAN1042HGV-Q1

TCAN1042HGVD

TCAN1042HGVDQ1

TCAN1042HGVDR

TCAN1042HGVDRBRQ1

TCAN1042HGVDRBTQ1