TCAN1164DMTRQ1 [TI]
具有 LDO 输出和看门狗的汽车类 CAN FD 系统基础芯片 | DMT | 14 | -40 to 125;
| 型号： | TCAN1164DMTRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 LDO 输出和看门狗的汽车类 CAN FD 系统基础芯片 | DMT | 14 | -40 to 125 |
| 文件： | 总70页 (文件大小：2902K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TCAN1164-Q1
ZHCSPG1 – DECEMBER 2021
TCAN1164-Q1 具有 LDO 输出和看门狗的汽车 CAN FD 系统基础芯片
1 特性
3 说明
•
•
•
符合面向汽车应用的 AEC Q100（1 级）标准
TCAN1164-Q1 是一款高速控制器局域网 (CAN) 系
统基础芯片 (SBC)，符合 ISO 11898-2:2016 高速
CAN 规范的物理层要求。该收发器支持传统 CAN 和
CAN FD 网络，数据速率高达 8 兆位/秒 (Mbps)
(TCAN1164-Q1) 或 5Mbps (TCAN1164T-Q1)。
符合 ISO 11898-2:2016 的要求
功能安全质量管理型
– 可帮助进行功能安全系统设计的文档
宽工作输入电压范围
为 CAN 收发器供电的集成 LDO
– 具有 100mA 输出电流能力的 5V LDO
支持高达 8Mbps (TCAN1164-Q1) 的传统 CAN 和
CAN FD
•
•
TCAN1164-Q1 支持宽输入电源电压范围，并且集成了
5V LDO 输出。5V LDO 输出 (VCCOUT) 可在内部为
CAN 收发器提供电压，并在外部提供额外电流。
•
器件信息
– 支持多种模式的看门狗计时器
器件型号
TCAN1164-Q1
TCAN1164T-Q1
封装(1)
封装尺寸（标称值）
4.5mm x 3.00mm
4.5mm x 3.00mm
•
•
•
超时
VSON (14)
VSON (14)
窗口
问答看门狗 (Q&A)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
– 速度高达 5Mbps (TCAN1164T-Q1)
可通过 SPI 编程的工作模式
– 正常模式
录。
•
VSUP
10
VLDO 5V
VCCOUT
3
– 静音模式
VCCOUT
– 待机模式
1
DOMINANT
TIME OUT
TXD
•
•
支持高级 CAN 总线故障检测
定义了未上电时的行为
– 总线和 IO 终端为高阻抗（运行总线或应用上无
负载）
13
12
CANH
CANL
Driver
8
6
SCLK
SDI
•
保护特性：
OVER
TEMP
SPI
11
14
SYSTEM CONTROLLER
SDO
nCS
– ±58V CAN 总线容错
– VSUP 上支持负载突降
– IEC ESD 保护
– 欠压和过压保护
– 热关断保护
– TXD 显性状态超时 (TXD DTO)
支持超宽结温范围
采用无引线 VSON (14) 封装，具有可湿性侧面，提
高了自动光学检测 (AOI) 能力
VCCOUT
UNDER
VOLTAGE
5
4
nRST
RXD
High Speed Receiver
Low Power Receiver
VCCOUT
Logic Output
MUX
WUP
Detect
•
•
2
GND
功能方框图
2 应用
•
•
•
•
高级驾驶辅助系统 (ADAS)
车身电子装置和照明
汽车信息娱乐系统和仪表组
混合动力、电动和动力总成系统
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSFE3
TCAN1164-Q1
ZHCSPG1 – DECEMBER 2021
www.ti.com.cn
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明（续）.........................................................................3
6 Device Comparison Table...............................................4
7 Pin Configurations and Functions.................................5
8 Specifications.................................................................. 6
8.1 Absolute Maximum Ratings........................................ 6
8.2 ESD Ratings............................................................... 6
8.3 ESD Ratings IEC Specification...................................6
8.4 Recomended Operating Conditions............................6
8.5 Thermal Information....................................................7
8.6 Power Supply Characteristics.....................................7
8.7 Electrical Characteristics.............................................8
8.8 Switching Characteristics..........................................10
8.9 Typical Characteristics..............................................13
9 Parameter Measurement Information..........................14
10 Detailed Description....................................................18
10.1 Overview.................................................................18
10.2 Functional Block Diagram.......................................18
10.3 Feature Description.................................................19
10.4 Device Functional Modes........................................37
10.5 Programming.......................................................... 42
11 Application Information Disclaimer........................... 58
11.1 Application Information............................................58
11.2 Typical Application.................................................. 58
11.3 Application Curves.................................................. 60
12 Power Supply Requirements......................................61
13 Layout...........................................................................62
13.1 Layout Guidelines................................................... 62
13.2 Layout Example...................................................... 62
14 Device and Documentation Support..........................63
14.1 Documentation Support.......................................... 63
14.2 接收文档更新通知................................................... 63
14.3 支持资源..................................................................63
14.4 Trademarks.............................................................63
14.5 Electrostatic Discharge Caution..............................63
14.6 术语表..................................................................... 63
15 Mechanical, Packaging, and Orderable
Information.................................................................... 63
4 Revision History
DATE
REVISION
NOTES
December 2021
*
Initial Revision
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5 说明（续）
TCAN1164-Q1 包括许多保护和诊断功能，如 CAN 总线短路检测、热关断 (TSD)、驱动器显性超时 (TXD DTO)
和高达 ±58V 的总线故障保护。
TCAN1164-Q1 支持看门狗功能，通过要求处理器在一个时间窗口内重置看门狗计时器来确保系统正常运行。
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6 Device Comparison Table
DEVICE NUMBER
Description
MAXIMUM DATA RATE
VeLIO(1)
CAN FD SBC with SPI Mode Control,
Reset, Watchdog and 5 V LDO
TCAN1164-Q1
TCAN1164T-Q1
8 Mbps
No
CAN FD SBC with SPI Mode Control,
Reset, Watchdog and 5 V LDO
5 Mbps
Yes
1. Certified according to latest VeLIO (Vehicle LAN Interopability and Optimization) test requirements
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7 Pin Configurations and Functions
TXD
GND
VCCOUT
RXD
1
2
3
4
5
6
7
14
13
12
11
10
9
nCS
CANH
CANL
SDI
Thermal
Pad
nRST
SDO
NC
VSUP
NC
8
SCLK
Not to scale
图 7-1. DMT package, 14 Pin (VSON), Top View
表 7-1. Pin Functions
PIN
TYPE
Description
NAME
TXD
NO.
1
Digital
GND
CAN transmit data input, integrated pull-up
Ground connection
GND
VCCOUT
RXD
nRST
SDO
NC
2
3
Supply
Digital
Digital
Digital
—
5-V LDO regulated output voltage
CAN receive data output
4
5
Reset input/output
6
SPI data output
7
No connect (not internally connected)
SPI clock input
SCLK
NC
8
Digital
—
9
No connect (not internally connected)
Reverse-blocked battery supply input
SPI data input
VSUP
SDI
10
11
12
13
14
Supply
Digital
Bus IO
Bus IO
Digital
CANL
CANH
nCS
Low-level CAN bus input/output line
High-level CAN bus input/output line
SPI chip select (active low)
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8 Specifications
8.1 Absolute Maximum Ratings
over operating virtual junction temperature range (unless otherwise noted)(1)
MIN
–0.3
-0.3
–58
MAX
42
6
UNIT
V
VSUP
Supply voltage range
VCCOUT
VBUS
5 V regulated output
V
CAN bus IO voltage range (CANH, CANL)
Logic input terminal voltage range
Logic output terminal voltage range
Logic output current
58
6
V
V(Logic_Input)
V(Logic_Output)
IO(LOGIC)
TJ
–0.3
–0.3
V
6
V
8
mA
°C
°C
Operating virtual junction temperature range
Storage temperature
–40
-65
150
165
TSTG
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
8.2 ESD Ratings
VALUE
UNIT
HBM classification level 3A for all
pin
±4000
Human body model (HBM), per AEC
Q100-002(1)
HBM classification level 3A for
±8000
±10000
±750
VSUP
,
V(ESD)
Electrostatic discharge
V
HBM classification level 3B for
global pins CANH & CANL
Charged-device model (CDM), per AEC Q100-011
CDM classification level C5 for all pins
(1) AEC-Q100-002 indicates that HBM stresses shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
8.3 ESD Ratings IEC Specification
VALUE
UNIT
CAN bus terminals (CANH & CANL) to
±8000
System level electro-static
discharge (ESD)(1)
IEC 61000-4-2 (150pF, 330Ω)
unpowered contact discharge
GND
VSUP
VESD
±8000
–100
75
Pulse 1
V
Pulse 2
ISO 7637 ISO pulse transients(2)
ISO 7637-3 transient(3)
CAN bus terminals (CANH & CANL) to
GND, VSUP
VTRAN
Pulse 3a
–150
100
Pulse 3b
DCC slow transient pulse
±30
(1) Tested according to IEC 62228-3 CAN Transceiver, Section 6.4; DIN EN 61000-4-2
(2) Tested according to IEC 62228-3 CAN Transceiver, Section 6.3; standard pulse parameters defined in ISO 7637-2
(3) Tested according to ISO 7637-3; electrical transient transmission by capacitive and inductive coupling via lines other than supply line
8.4 Recomended Operating Conditions
MIN
5.5
–2
NOM
MAX UNIT
VSUP
Supply voltage range
28
V
IOH(DO)
IOL(DO)
CVSUP
CVCCOUT
TSDR
Digital output terminal high level output current
Digital output terminal low level output current
VSUP pin capacitance
mA
mA
µF
µF
°C
2
0.1
VCCOUT pin capacitance
10
Thermal shutdown rising
175
180
165
TSDF
Thermal shutdown falling
170
°C
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MIN
NOM
MAX UNIT
TSDW
THYS
Thermal shutdown warning
Thermal shutdown hysterisis
150
°C
°C
15
8.5 Thermal Information
DMT (VSON)
THERMAL METRIC(1)
UNIT
14 PINS
37.7
37.9
14.2
0.7
RΘJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RΘJC(top)
RΘJB
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJB
14.2
4.9
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.6 Power Supply Characteristics
Over recomended operating conditions with TJ = -40°C to 150°C, unless otherwise noted. All typical values are taken at
25°C, VSUP = 12 V, and RL = 60 Ω
PARAMETER
Supply Voltage and Current
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TXD = 0 V, RL = 60 Ω, CL = open
See 图 9-2
60
70
mA
mA
Supply current
Bus biasing active: dominant
TXD = 0 V, RL = 50 Ω, CL = open
See 图 9-2
ISUP
Supply current
Bus biasing active: recessive
TXD = VCCOUT, RL = 50 Ω, CL = open
See 图 9-2
3
mA
Supply current
Standby mode
Bus bias autonomous: inactive
5.5 V < VSUP ≤ 19 V
See 图 9-2
ISUP(STB)
230
60
µA
µA
Supply current
5.5 V < VSUP ≤ 28 V
See 图 9-2
ISUP(BIAS)
Bus bias autonomous: active(1)
UVSUPR
UVSUPF
Under voltage VSUP threshold rising
Under voltage VSUP threshold falling
Ramp Up
4.05
3.9
4.42
4.25
V
V
Ramp Down
VCCOUT Characteristics
VSUP = 5.5 to 18 V
IL = 0 to 100 mA
TXD = VCCOUT
VCCOUT 5 V regulated output
4.9
4.9
5
5.1
5.1
V
V
VSUP = 5.65 to 18 V
IL = 0 to 100 mA
VCCOUT
5 V regulated output
5
TXD = 0 V; VCANH = 0 V
VCCOUT_DROP
∆VCCOUT(∆VSUP)
∆VCCOUT(∆VSUPL)
UVVCCOUTR
UVVCCOUTF
OVCCOUTR
Dropout voltage
5 V LDO, VSUP – VCCOUT, IL = 125 mA
VSUP = 5.5 to 28 V, IL = 10 mA, ΔVCCOUT
IL = 1 to 125 mA, VSUP = 14 V, ΔVCCOUT
Ramp Up
300
650
50
mV
mV
mV
V
Line regulation
Load regulation
50
Under voltage VCCOUT threshold rising
Under voltage VCCOUT threshold falling
Over voltage VCCOUT threshold rising
Over voltage VCCOUT threshold falling
Output current limit
4.25
4.2
4.6
4.45
5.7
4.75
4.7
Ramp Down
V
Ramp Up
6.15
V
OVCCOUTF
Ramp Down
5.47
175
5.65
V
IL_VCCOUT
VCCOUT short to ground
275
mA
VRIP = 0.5 VPP, Load = 10 mA, ƒ = 100 Hz,
CO = 10 μF
PSRRVCCOUT
Power supply rejection ripple rejection
60
dB
(1) After a valid wake-up the total ISUP current is the sum of ISUP(STB) and ISUP(BIAS) (ISUP = ISUP(STB) + ISUP(BIAS)
)
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8.7 Electrical Characteristics
Over recommended operating conditions with TJ = –40°C to 150°C, unless otherwise noted. All typical values are taken at
25°C, VSUP = 12 V, and RL = 60 Ω
PARAMETER
CAN Driver Electrical Characteristics
Dominant output voltage
TEST CONDITIONS
MIN
TYP
MAX UNIT
CANH
CANL
2.75
0.5
4.5
V
V
TXD = 0 V, 50 ≤ RL ≤ 65 Ω, CL = open, RCM
=
Bus biasing active
VO(D)
open
See 图 9-2
Dominant output voltage
2.25
Bus biasing active
TXD = VCCOUT, RL = open (no load), RCM
open
See 图 9-2
=
Recessive output voltage
Bus biasing active
VO(R)
2
0.9
3
1.1
400
3
V
V/V
mV
V
Driver symmetry
Bus biasing active
(VO(CANH) + VO(CANL) ) / VCCOUT
RL = 60 Ω, CSPLIT = 4.7 nF, CL = Open, RCM
Open, TXD = 250 kHz, 1 Mhz, 2.5 MHz
See 图 9-2
=
VSYM
DC Driver symmetry
Bus biasing active
VCCOUT – VO(CANH) – VO(CANL)
RL = 60 Ω, CL = open
See 图 9-2
VSYM_DC
–400
1.5
Differential output voltage
Bus biasing active
Dominant
TXD = 0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open
See 图 9-2
CANH - CANL
Differential output voltage
Bus biasing active
Dominant
TXD = 0 V, 45 Ω ≤ RL ≤ 70 Ω, CL = open
See 图 9-2
VOD(DOM)
CANH - CANL
CANH - CANL
1.4
3.3
5
V
Differential output voltage
Bus biasing active
Dominant
TXD = 0 V, RL = 2240 Ω, CL = open
See 图 9-2
1.5
V
Differential output voltage
Bus biasing active
Bus biasing inactive
Recessive
TXD = VCCOUT, RL = open Ω, CL = open
See 图 9-2
VOD(REC)
CANH - CANL
–50
50
mV
TXD = VCCOUT
CANH
RL = open (no load), CL = open
See 图 9-2
-0.1
-0.1
-0.2
–75
0.1
0.1
0.2
V
V
Pin output voltage
Bus biasing inactive
VO(INACT)
VOD(STB)
IOS(DOM)
IOS(REC)
TXD = VCCOUT
RL = open (no load), CL = open
See 图 9-2
CANL
TXD = VCCOUT
RL = open (no load), CL = open
See 图 9-2
Differential output voltage
Bus biasing inactive
CANH - CANL
V
Short-circuit steady-state output current
Bus biasing active
TXD = 0 V
-15 V ≤ V(CANH) ≤ 40 V
See 图 9-2 and 图 9-8
mA
mA
mA
Dominant
Short-circuit steady-state output current
Bus biasing active
TXD = 0 V
-15 V ≤ V(CANL) ≤ 40 V
See 图 9-2 and 图 9-8
75
3
Dominant
Short-circuit steady-state output current
Bus biasing active
VBUS = CANH = CANL
-27 V ≤ VBUS ≤ 42 V
See 图 9-2 and 图 9-8
–3
Recessive
CAN Receiver Electrical Characteristics
Receiver dominant state input voltage range
Bus biasing active
VIT(DOM)
VIT(REC)
0.9
-3
8
V
V
-12 V ≤ VCM ≤ 12 V
See 图 9-3 and 表 10-14
Receiver recessive state input voltage range
Bus biasing active
0.5
Hysteresis voltage for input threshold
Bus biasing active
VHYS
See 图 9-3 and 表 10-14
80
-5
140
mV
V
VDIFF(MAX)
VDIFF(DOM)
VDIFF(REC)
VCM
Maximum rating of VDIFF
10
8
Receiver dominant state input voltage range
Bus biasing inactive
1.150
V
-12 V ≤ VCM ≤ 12 V
See 图 9-3 and 表 10-14
Receiver recessive state input voltage range
Bus biasing inactive
-3
0.4
12
V
V
Common mode range
See 图 9-3 and 表 10-14
–12
Power-off (unpowered) bus input leakage
current
IOFF(LKG)
VSUP = 0 V, CANH = CANL = 5 V
2.5
µA
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Over recommended operating conditions with TJ = –40°C to 150°C, unless otherwise noted. All typical values are taken at
25°C, VSUP = 12 V, and RL = 60 Ω
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Input capacitance to ground (CANH or CANL)
CI
TXD = VCCOUT
20
pF
(1)
CID
RID
RIN
Differential input capacitance(1)
Differential input resistance
TXD = VCCOUT
10
100
50
pF
kΩ
kΩ
50
25
TXD = VCCOUT
-12 V ≤ VCM ≤ 12 V
Input resistance (CANH or CANL)
Input resistance matching:
[1 – RIN(CANH) / RIN(CANL)] × 100%
RIN(M)
V(CANH) = V(CANL) = 5 V
–1
1
%
TXD Input Characteristics
VIH
High level input voltage
0.7
VCCOUT
VIL
Low level input voltage
High level input leakage current
Low level input leakage current
Pull-up resistance
0.3 VCCOUT
IIH
TXD = VCCOUT
TXD = 0 V
–1
–130
40
0
1
–15
80
µA
µA
kΩ
µA
pF
IIL
RPU
ILKG(OFF)
CI
60
0
Unpowered leakage current
Input Capacitance
TXD = 5.5 V, VSUP = 0 V
–1
1
VIN = 0.4 x sin(2 × π × 2 × 106 × t) + 2.5 V
5
RXD Output Characteristics
VOH
High level output voltage
IO = –2 mA.
IO = 2 mA.
0.8
VCCOUT
VOL
Low level output voltage
Pull-up resistance
0.2 VCCOUT
RPU
40
-5
60
80
5
kΩ
µA
ILKG(OFF)
Unpowered leakage curret
RXD = 5.5 V, VSUP = 0 V
nRST Bidirectional Characteristics
VIH
VIL
High level input voltage
0.8
VCCOUT
Low level input voltage
0.2 VCCOUT
0.2 VCCOUT
VOL
IIH
Low level output voltage
High level input leakage current
Pull-up resistance to VCCOUT
IO = 2 mA.
nRST = VCCOUT
-1
1
µA
kΩ
RPU
160
240
320
SDI Input Characteristics
VIH
High level input voltage
0.8
VCCOUT
VIL
Low level input voltage
High level input leakage current
Low level input leakage current
Pull-up resistance
0.2 VCCOUT
(2)
IIH
SDI = VCCOUT
-1
-130
40
1
-50
80
1
µA
µA
kΩ
µA
pF
IIL
SDI = 0 V
RPU
ILKG(OFF)
CIN
60
Unpowered leakage current
Input capacitance
SDI = 5.5 V, VSUP = 0 V
20 MHz
-1
4
10
SCLK Input Characteristics
VIH
High level input voltage
0.7
VCCOUT
VIL
Low level input voltage
0.3 VCCOUT
(2)
IIH
High level input leakage current
Low level input leakage current
Pull-down resistance
SCLK = VCCOUT
50
-1
40
-1
4
130
1
µA
µA
kΩ
µA
pF
IIL
SCLK = 0 V
RPD
ILKG(OFF)
CIN
60
80
1
Unpowered leakage current
Input capacitance
SCLK = 5.5 V, VSUP = 0 V
20 MHz
10
nCS Input Characteristics
High level input
voltage
VIH
VIL
High level input voltage
Low level input voltage
High level input voltage
Low level input voltage
0.7
VCCOUT
Low level input
voltage
0.3 VCCOUT
IIH
High level input leakage current
Low level input leakage current
Pull-up resistor
nCS = VCCOUT
nCS = 0 V
-1
-130
40
1
-50
80
µA
µA
kΩ
IIL
RPU
60
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Over recommended operating conditions with TJ = –40°C to 150°C, unless otherwise noted. All typical values are taken at
25°C, VSUP = 12 V, and RL = 60 Ω
PARAMETER
Unpowered leakage current
Input capacitance
TEST CONDITIONS
MIN
TYP
MAX UNIT
ILKG(OFF)
CIN
nCS = 5.5 V, VSUP = 0 V
-1
1
µA
pF
20 MHz
4
10
SDO Output Characteristics
VOH
High-level output voltage
IOH = -2 mA
IOL = 2 mA
VnCS = 5.5 V
0.8
-1
VCCOUT
VOL
Low-level output voltage
0.2 VCCOUT
µA
ILKG(OFF)
Unpowered leakage current
1
(1) Test according to ISO 11898-2:2003
(2) Note that there is an internal pull-up resistor to VCCOUT. If externally driven to a higher or lower voltage, the pin leakage measurement
will be increased.
8.8 Switching Characteristics
Over recomended operating conditions with TJ = -40°C to 150°C, unless otherwise noted. All typical values are taken at
25°C, VSUP = 12 V and RL = 60 Ω
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
Supply Switching Characteristics
tPOWER_UP CAN supply power up time
tUV(SUP)
CVCCOUT = 10 µF
See 图 9-9
1.8
4
ms
µs
VSUP filter time (rising and falling)
VCCOUT filter time (rising and falling)
4
25
Time for device to enter sleep
state reset state once UVCCOUT is
reached
tUV(VCCOUT)
30
10
µs
Device Switching Characteristics
tUV(nRST)
Undervoltage detection delay time nRST low
50
1.8
2
µs
µs
ms
s
tWK_FILTER
tWK_TIMEOUT
tSILENCE
Bus time to meet filtered bus requirments for wakeup request
Bus wakeup timeout value
0.5
0.8
See 图 10-15
Time out for bus inactivity
0.9
4
1.2
5
tINACTIVE
Hardware timer for failsafe and power up inactivity(1)
3
min
Time from the start of a dominant-recessive-dominant sequence
until Vsym ≥ 0.1
Each phase: 6 μs
See 图 9-10
tBIAS
250
25
µs
us
Time from switching to CAN active mode to transceiver ready to
transmit
tCAN(ACTIVE)
VCCOUT > UVVCCOUT(R)
RL = 60 Ω, CL = 100 pF, CL(RXD)
15 pF
See 图 9-6
=
=
=
Total loop delay, driver input (TXD) to receiver output (RXD)
Recessive to dominant
tPROP(LOOP1)
100 160
120 175
ns
ns
RL = 60 Ω, CL = 100 pF, CL(RXD)
15 pF
See 图 9-6
Total loop delay, driver input (TXD) to receiver output (RXD)
Dominant to recessive - TCAN1164-Q1
tPROP(LOOP2)
RL = 60 Ω, CL = 100 pF, CL(RXD)
15 pF
See 图 9-6
Total loop delay, driver input (TXD) to receiver output (RXD)
Dominant to recessive - TCAN1164T-Q1
tPROP(LOOP2)
tmode_slp_reset
130 195
50
ns
µs
WUP or LWU event to INH asserted high, see
Driver Switching Characteristics
Propagation delay time, high TXD to driver
tpHR
65
25
82 130
ns
ns
recessive
Propagation delay time, low TXD to driver
dominant
tpLD
RL = 60 Ω, CL = 100 pF, RCM
open
See 图 9-2
=
50
110
50
TCAN1164T-Q1
tsk(p)
tR
Pulse skew (|tpHR - tpLD|)
25
40
95
ns
ns
ns
Differential output signal rise time
Differential output signal fall time
tF
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Over recomended operating conditions with TJ = -40°C to 150°C, unless otherwise noted. All typical values are taken at
25°C, VSUP = 12 V and RL = 60 Ω
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
Propagation delay time, high TXD to driver
recessive
tpHR
tpLD
20
35
40
70
ns
ns
Propagation delay time, low TXD to driver
dominant
RL = 60 Ω, CL = 100 pF, RCM
open
See 图 9-2
=
15
70
20
TCAN1164-Q1
tsk(p)
tR
Pulse skew (|tpHR - tpLD|)
10
40
45
ns
ns
ns
Differential output signal rise time
Differential output signal fall time
tF
RL = 60 Ω, CL = open
See 图 9-7, TXD = 0 V
tTXD_DTO
Dominant timeout
1.2
3.8
ms
Receiver Switching Characteristics
Propagation delay time, bus recessive input to
high RXD
CL(RXD) = 15 pF
See 图 9-3
tpRH
tpRH
tpDL
tR
TCAN1164T-Q1
TCAN1164-Q1
25
25
20
65 140
80 140
ns
ns
ns
ns
ns
Propagation delay time, bus recessive input to
high RXD
CL(RXD) = 15 pF
See 图 9-3
CL(RXD) = 15 pF
See 图 9-3
Propagation delay time, bus dominant input to RXD low output
Output signal rise time (RXD)
50
8
110
CL(RXD) = 15 pF
See 图 9-3
CL(RXD) = 15 pF
See 图 9-3
tF
Output signal fall time (RXD)
5
nRST Characteristics
tnRST
Minimum low time for reset
Input pulse width
Cold crank
15
20
1
µs
ms
ms
tnRST(cold)
tnRST(warm)
Output pulse width
Output pulse width
27
Warm crank
1.5
SPI Switching Characteristics
fSCK SCK, SPI clock frequency
tSCK
Normal, standby, and silent
modes
4
MHz
ns
Normal, standby, and silent
modes; See 图 9-12
SCK, SPI clock period
250
tRSCK
tFSCK
SCK rise time
SCK fall time
See 图 9-11
See 图 9-11
40
40
ns
ns
Normal, standby, and silent
modes; See 图 9-12
tSCKH
tSCKL
SCK, SPI clock high
SCK, SPI clock low
125
125
ns
ns
Normal, standby, and silent
modes; See 图 9-12
tACC
tCSS
tCSH
tCSD
First read access time from chip select
Chip select setup time
50
100
100
50
ns
ns
ns
ns
See 图 9-11
See 图 9-11
See 图 9-11
Chip select hold time
Chip select disable time
Normal, standby, and silent
modes; See 图 9-11
tSISU
tSIH
Data in setup time
Data in hold time
Data out valid
50
50
ns
ns
ns
Normal, standby, and silent
modes; See 图 9-11
Normal, standby, and silent
modes; See 图 9-12
tSOV
80
tRSO
tFSO
SO rise time
SO fall time
See 图 9-12
See 图 9-12
40
40
ns
ns
CAN FD Timing Characteristics
Bit time on CAN bus output pins with tBIT(TXD)
=
=
=
435
155
80
530
210
140
ns
ns
ns
500 ns
RL = 60 Ω, CL = 100 pF
CL(RXD) = 15 pF
ΔtREC = tBIT(RXD) - tBIT(BUS)
See 图 9-6
Bit time on CAN bus output pins with tBIT(TXD)
200 ns
tBIT(BUS)
TCAN1164-Q1
Bit time on CAN bus output pins with tBIT(TXD)
125 ns
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Over recomended operating conditions with TJ = -40°C to 150°C, unless otherwise noted. All typical values are taken at
25°C, VSUP = 12 V and RL = 60 Ω
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
Bit time on CAN bus output pins with tBIT(TXD)
500 ns
=
=
RL = 60 Ω, CL = 100 pF
CL(RXD) = 15 pF
ΔtREC = tBIT(RXD) - tBIT(BUS)
See 图 9-6
450
530
210
ns
ns
tBIT(BUS)
TCAN1164T-Q1
Bit time on CAN bus output pins with tBIT(TXD)
200 ns
155
Bit time on RXD output pins with tBIT(TXD) = 500 ns
Bit time on RXD output pins with tBIT(TXD) = 200 ns
400
120
550
220
ns
ns
RL = 60 Ω, CL = 100 pF
CL(RXD) = 15 pF
ΔtREC = tBIT(RXD) - tBIT(BUS)
See 图 9-6
tBIT(RXD)
Bit time on RXD output pins with tBIT(TXD) = 125
ns
TCAN1164-Q1
80
135
ns
Receiver timing symmetry with tBIT(TXD) = 500 ns
Receiver timing symmetry with tBIT(TXD) = 200 ns
Receiver timing symetry with tBIT(TXD) = 125 ns
-50
-45
-40
20
15
10
ns
ns
ns
RL = 60 Ω, CL = 100 pF
CL(RXD) = 15 pF
ΔtREC = tBIT(RXD) - tBIT(BUS)
See 图 9-6
ΔtREC
TCAN1164-Q1
(1) Timer is reset when the CAN bus changes states.
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8.9 Typical Characteristics
112
108
104
100
96
3
2.75
2.5
-40 C
30 C
150 C
-40 C
50 C
150 C
2.25
2
92
88
1.75
1.5
84
80
4
8
12
16
VSUP (V)
20
24
CLRXD = 15 pF
28
4
6
8
10 12 14 16 18 20 22 24 26 28
VSUP (V)
RL = 60 Ω
CL = 100 pF
RL = 60 Ω
图 8-1. tPROP(LOOP1) over VSUP
图 8-2. VOD(DOM) over VSUP
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9 Parameter Measurement Information
CANH
TXD
RL
CL
CANL
图 9-1. ISUP Test Circuit
RCM
CANH
50%
50%
TXD
TXD
RL
CL
VOD
VCM
VCC
VO(CANH)
tpLD
tpHR
90%
10%
0V
CANL
RCM
0.9V
VO(CANL)
VOD
0.5V
tR
tF
图 9-2. Driver Test Circuit and Measurement
CANH
1.5V
0.9V
VID
IO
RXD
0.5V
0V
VID
tpDL
tpRH
VOH
VO
CL_RXD
CANL
90%
VO(RXD)
50%
10%
VOL
tF
tR
图 9-3. Receiver Test Circuit and Measurement
UVLDO5
nRST
VLDO5
tnRST(warm)
图 9-5. tnRST Warm Start
nRST
tnRST(cold)
图 9-4. tnRST Cold Start
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TXD
VI
70%
tLOOP2
30%
30%
CANH
0V
TXD
VI
5 x tBIT(TXD)
tBIT(TXD)
RL
CL
CANL
tBIT(Bus)
nSLP
0V
900mV
500mV
RXD
VDIFF
VO
CL_RXD
RXD
VOH
70%
30%
VOL
tBIT(RXD)
图 9-6. Transmitter and Receiver Timing Behavior Test Circuit and Measurement
VIH
0V
CANH
TXD
TXD
RL
CL
VOD
VOD(D)
CANL
0.9V
VOD
0.5V
0V
tTXD_DTO
图 9-7. TXD Dominant Timeout Test Circuit and Measurement
200 ꢀs
IOS
CANH
TXD
VBUS
IOS
CANL
VBUS
VBUS
0V
or
0V
VBUS
VBUS
图 9-8. Driver Short-Circuit Current Test and Measurement
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VSUP
4.5V
VCCOUT
CVCCOUT = 10
F
VSUP
0 V
TCAN1164
VSUP
tPOWER_UP
CVSUP
VCCOUT
VO
90%
0 V
图 9-9. tPOWER_UP Timing Measurement
VDIFF
2.0 V
1.15 V
0.4 V
t > tWK_FILTER(MAX)
t > tWK_FILTER(MAX)
t > tWK_FILTER(MAX)
VSYM
0.1
tBias
图 9-10. Test Signal Definition for Bias Reaction Time Measurement
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tCSD
nCS
tCSH
tRSCK
tFSCK
tCSS
CLK
tSISU
tSIH
SDI
MSB In
LSB
In
SDO
图 9-11. SPI AC Characteristic Write
nCS
tSCK
tSCKL
tSCKH
SCLK
tSOV
tRSO
tFSO
SDO
LSB
Out
MSB Out
SDI
图 9-12. SPI AC Characteristic Read
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10 Detailed Description
10.1 Overview
The TCAN1164-Q1 is a high speed Controller Area Network (CAN) system basis chip (SBC) that meets the
physical layer requirements of the ISO 11898-2:2016 high speed CAN specification. The transceiver supports
both classical CAN and CAN FD networks up to 8 megabits per second (Mbps) (TCAN1164-Q1) or 5-Mbps
(TCAN1164T-Q1).
The TCAN1164-Q1 supports a wide input supply range and integrates a 5-V LDO output. The 5-V LDO output
(VCCOUT) supplies the CAN transceiver voltage internally as well as additional current externally.
10.2 Functional Block Diagram
VSUP
10
VLDO 5V
VCCOUT
3
VCCOUT
1
DOMINANT
TIME OUT
TXD
13
12
CANH
CANL
Driver
8
6
SCLK
SDI
OVER
TEMP
SPI
11
14
SYSTEM CONTROLLER
SDO
nCS
VCCOUT
UNDER
VOLTAGE
5
4
nRST
RXD
High Speed Receiver
Low Power Receiver
VCCOUT
Logic Output
MUX
WUP
Detect
2
GND
图 10-1. TCAN1164-Q1
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10.3 Feature Description
10.3.1 VSUP Pin
This pin is connected to the battery supply. It provides the supply to the internal regulators that support the digital
core, the CAN transceiver, and the low power CAN receiver.
10.3.2 VCCOUT Pin
An internal LDO provides power for the integrated CAN transceiver and the VCCOUT output pin. The amount
of current that can be delivered externally is dependent upon the CAN transceiver requirements during normal
operation as well as the ambient operating temperature. When a CAN bus fault takes place that requires
additional current from the LDO, the total available current to external load components may be degraded. This
pin requires a 10 μF external capacitor as close to the pin as possible.
10.3.3 Digital Inputs and Outputs
The TCAN1164-Q1 has a VCCOUT supply that is used to set the digital input thresholds. The input thresholds are
ratio metric to the VCCOUT supply using CMOS input levels. The TXD input is biased to the VCCOUT level to force
a recessive input in case the pin floats. The high level output voltage for the RXD and output pins is driven to the
VCCOUT level as logic-high outputs.
10.3.3.1 TXD Pin
TXD is a digital signal, referenced to VCCOUT, from a CAN controller to the TCAN1164-Q1.
10.3.3.2 RXD Pin
RXD is a digital signal, referenced to VCCOUT, from the TCAN1164-Q1 to a CAN controller.
When a wake event occurs, this pin is pulled low to signal that a wake event has taken place.
10.3.4 GND
GND is the ground pin and it must be connected to the PCB ground.
10.3.5 nRST Pin
The nRST is an bidirectional open drain low side driver with an integrated pull-up resistor to VCCOUT. It can be
pulled low by the device when placed in fail-safe mode.
During initial power-up of the device, a fail-safe mode to reset transition, or an undervoltage event will be
recognized as a cold crank reset condition. The nRST pin will be held low for tnRST(cold) allowing the MCU and
peripheral devices to power-up correctly before data transmission begins.
To enter reset mode from normal mode, or standby mode the nRST must be pulled low for a minimum of time of
tnRST. The TCAN1164-Q1 recognizes this and a watchdog error as a warm crank reset condition and holds the
nRST pin low for tnRST(warm)
.
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nRST
CONTROL and MODE
LOGIC
图 10-2. nRST Circuit
10.3.6 SDO
When nCS is low this pin is the SPI serial data output pin. When nCS is high, the pin will be tri-stated.
10.3.7 nCS Pin
The nCS pin is the SPI chip select pin. When pulled low and a clock is present the device can be written to or
read from.
10.3.8 SCLK
The SCLK pin is the SPI clock. The clock rate should not exceed the max fSCK value.
10.3.9 SDI
When nCS is low this pin is the SPI serial data input pin used for programming the device or requesting data.
10.3.10 CAN Bus Pins
These are the CAN high and CAN low, CANH and CANL, differential bus pins. These pins are connected to the
CAN transceiver.
10.3.11 Local Faults
10.3.11.1 TXD Dominant Timeout (TXD DTO)
While the CAN driver is in active mode a TXD DTO circuit prevents the local node from blocking network
communication in event of a hardware or software failure where TXD is held dominant longer than the time out
period tTXD_DTO. The TXD DTO circuit is triggered by a falling edge on TXD. If no rising edge is seen before
the time out constant of the circuit, tTXD_DTO, expires the CAN driver is disabled releasing the bus lines to the
recessive level. This keeps the bus free for communication between other nodes on the network. The CAN driver
is re-activated on the next dominant to recessive transition on the TXD terminal, thus clearing the dominant time
out. The high-speed receiver and RXD terminal will reflect what is on the CAN bus during a TXD DTO fault. The
TS terminal in driven low during a TXD DTO fault.
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Fault is repaired & transmission capability
restored
TXD fault stuck dominant: example PCB failure or bad software
tTXD_DTO
TXD (driver)
Driver disabled freeing bus for other nodes
Normal CAN communication
Bus would be —stuck dominant“ blocking communication for the whole network but TXD DTO
prevents this and frees the bus for communication after the time tTXD_DTO
.
CAN Bus Signal
tTXD_DTO
Communication from other bus node(s)
Communication from repaired node
RXD (receiver)
Communication from local node
Communication from other bus node(s)
Communication from repaired local node
图 10-3. Timing Diagram for TXD DTO
The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum possible transmitted
data rate of the device. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD)
for the worst case, where five successive dominant bits are followed immediately by an error frame. The
minimum transmitted data rate may be calculated using the minimum tTXD_DTO time and the maximum number of
successive dominant bits (11 bits).
Minimum Data Rate = 11 bits / tTXD_DTO = 11 bits / 1.2 ms = 9.2 kbps
(1)
10.3.11.2 Thermal Shutdown (TSD)
If the junction temperature of the TCAN1164-Q1 exceeds the thermal shutdown threshold, TJ > TSDR, the device
transitions into fail-safe mode and disables the transceiver's transmitter and receiver blocking transmission to
and from the CAN bus. The TSD fault condition is cleared when the device junction temperature falls below
the thermal shutdown temperature threshold, TJ < TSDF. If the fault condition that caused the TSD fault is still
present, the temperature may rise again and the device will enter thermal shutdown again. Prolonged operation
with a TSD fault conditions may affect device reliability.
10.3.11.3 Under/Over Voltage Lockout
The supply terminals implement undervoltage and over voltage detection circuitry. If an undervoltage is detected
the TCAN1164-Q1 transitions into reset mode. The SBC will remain in reset mode until the undervoltage event
clears.
If the over voltage fault is detected the TCAN1164-Q1 transitions into fail-safe mode. These mode changes place
the device in a known state which protect the system from unintended behavior. See 表 10-1
表 10-1. Undervoltage / Over Voltage Lockout
Fault
Mode
Reset
UVCCOUT
OVCCOUT
Fail-safe
10.3.11.4 Unpowered Devices
The device is designed to be an ideal passive or no load to the CAN bus if it is unpowered. The CANH and
CANL pins have low leakage currents when the device is un-powered so they present no load to the bus. This is
critical if some nodes of the network are unpowered while the rest of the of network remains in operation.
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The logic terminals also have low leakage currents when the device is un-powered so they do not load down
other circuits which may remain powered.
10.3.11.5 Floating Terminals
The TCAN1164-Q1 has internal pull-ups and pull-downs on critical pins to ensure a known operating behavior if
the pins are left floating.
The TXD pin is pulled up to VCCOUT which forces a recessive level if the pin floats. This internal bias should not
be relied upon by design but rather a fall-safe option. Special care needs to be taken when the devive is used
with a CAN controller that has open drain outputs. The device implements a weak internal pull-up resistor on the
TXD pin. The CAN bit timing for CAN FD data rates will require special consideration and the pull-up strength
should be considered carfully when using open drain outputs. An adequate external pull-up resistor must be
used to ensure that the TXD output of the CAN controller maintains adequate bit timing input to the CAN device.
表 10-2. Terminal Fail-Safe Biasing
PULL-UP or PULL-DOWN
TERMINAL
COMMENT
Weakly biases TXD toward recessive to prevent bus blockage or TXD
DTO triggering
TXD
Pull-up
nCS
Pull-up
Weakly biases nCS high to prevent un-intended SPI communication
Weakly biased to ground
SCLK
Pull-down
10.3.11.6 CAN Bus Short Circuit Current Limiting
The TCAN1164-Q1 has several protection features that limit the short circuit current during dominant and
recessive when a CAN bus line is shorted. The device has TXD dominant state timeout which prevents
permanently having a higher short circuit current during a dominant state fault.
During CAN communication the bus switches between the dominant and recessive states, thus the short circuit
current may be viewed either as the current during each bus state or as a DC average current. The average
short circuit current should be used when considering system power for the termination resistors and common
mode choke. The percentage dominant is limited by the TXD dominant state timeout and CAN protocol which
has forced state changes and recessive bits such as bit stuffing, control fields, and interframe space. These
ensure that there is a minimum recessive time on the bus even if the data field contains a high percentage of
dominant bits.
The short circuit current of the bus depends on the ratio of recessive to dominant bits and their respective short
circuit currents. The average short circuit current may be calculated using 方程式 2.
IOS(AVG) = %Transmit × [(%REC_Bits × IOS(SS)_REC) + (%DOM_Bits × IOS(SS)_DOM)] + [%Receive × IOS(SS)_REC
]
(2)
Where:
•
•
•
•
•
•
•
IOS(AVG) is the average short circuit current
%Transmit is the percentage the node is transmitting CAN messages
%Receive is the percentage the node is receiving CAN messages
%REC_Bits is the percentage of recessive bits in the transmitted CAN messages
%DOM_Bits is the percentage of dominant bits in the transmitted CAN messages
IOS(SS)_REC is the recessive steady state short circuit current
IOS(SS)_DOM is the dominant steady state short circuit current
The short circuit current and possible fault cases of the network should be taken into consideration when sizing
the power ratings of the termination resistance and other network components.
10.3.11.7 Sleep Wake Error Timer
The sleep wake error (SWE) timer, tINACTIVE, is a timer used to determine if specific external and internal
functions are working. The SWE timer starts when the device enters standby mode and only runs in standby
mode. A mode transistion stops the timer. If the timer times out while the device is in standby mode the WKERR
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interrupt bit in the INT_1 register will be set, register 8'h51[4], and the RXD pin will be pulled low to indicate an
interrupt. The TCAN1164-Q1 will stay in standby mode.
10.3.12 Watchdog
The TCAN1164-Q1 has an integrated watchdog function. The TCAN1164-Q1 provides a window based
watchdog as well as selectable autonomous, time-out or question and answer (Q&A) watchdog using SPI
programming. This function is default disabled. When enabled, the watchdog timer treats a mode transition as
the first watchdog trigger event.
All four versions of the watchdog, autonomous, time-out, window and Q&A are avilable in normal and silent
modes. When in standby mode the device will automactically transistion to a time-out watchdog. If autonomous
has been selected the transistion to standby will keep the autonomous configuration.
10.3.12.1 Watchdog Error Counter
The TCAN1164-Q1 has a watchdog error counter. This counter is an up down counter that increments for every
missed window or incorrect input watchdog trigger event. For every correct input trigger, the counter decrements
but does not drop below zero. The default trigger for this counter is set to trigger a watchdog error event. This
counter can be changed to the fifth or ninth error. The error counter can be read at register 8'h13[3:2].
10.3.12.2 Watchdog SPI Control Programming
The watchdog is configured and controlled using registers 8’h13 through 8’h15. These registers are provided
in table 表 10-3. The TCAN1164-Q1 watchdog can be set as autonomous, time-out, window or question and
answer (Q&A) watchdog by setting 8’h13[7:6] to the method of choice. The time-out and window watchdog timer
is based upon registers 8’h13[5:4] WD prescaler and 8’h14[7:5] WD timer and is in ms. See 表 10-3 for the
achievable times. If using smaller time windows it is suggested to use the time-out version of the watchdog. This
is for times between 4 ms and 64 ms.
表 10-3. Watchdog Window and Time-out Timer Configuration (ms)
WD_TIMER
8'h13[5:4] WD_PRE
(ms)
8'h14[7:5]
000
00
4
01
8
10
12
11
16
001
32
64
96
128
010
128
256
512
2048
10240
RSVD
256
384
512
011
384
512
768
100
1024
4096
20240
RSVD
1536
6144
RSVD
RSVD
2048
8192
RSVD
RSVD
101
110
1111
备注
If timing parameters are changed while the watchdog is running, the WD stops until after the first input
trigger event after the new parameters have been programmed at which time it runs based upon the
new timing parameters.
10.3.12.3 Watchdog Timing
The device provides four methods for setting up the watchdog. If more frequent, < 64 ms, input trigger events
are desired it is suggested to use the Time-out timer as this is an event within the time event and not specific to
an open window.
Autonomous watchdog is a type of time-out watchdog. The difference from time-out is when it is enabled. In
Standby (RXD=High, so no wake event), a wake event impacts the autonomous behavior. The wake event in
standby mode is treated as a watchdog trigger event. Clearing the wake event in Standby will both disable the
Watchdog and set RXD=H. If another wake event takes place while the device is still in standby mode, it will be
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treated as a WD trigger event. Regular time-out watchdog (or any other watchdog) requires a mode transistion to
start the timer. Only Autonomous can do a trigger based on a Wake event. In Normal mode, Autonomous works
like a time-out (always enabled).
When using the window watchdog it is important to understand the closed and open window aspects. The device
is set up with a 50%/50% open and closed window and is based on an internal oscillator with a ± 10% accuracy
range. To determine when to provide the input trigger, this variance needs to be taken into account. Using the
60 ms nominal total window provides a closed and open window that are each 30 ms. Taking the ± 10% internal
oscillator into account means the total window could be 54 ms, tWINDOW, MIN or 66 ms, tWINDOW MAX. The
closed and open window would then be 27 ms, TWDOUT MIN, or 33 ms, TWDOUT MIN. From the 54 ms total
window and 33 ms closed window the total open window is 21 ms. The trigger event needs to happen at the
43.5 ms ± 10.5 ms, safe trigger area. The same method is used for the other window values. 图 10-4 provides
the above information graphically. Once the WD trigger is written, the current Window is terminated and a new
Closed Window is started.
Watchdog Window
Closed Window
Open Window
tWDOUT min
Watchdog Window
Closed Window
Open Window
tWDOUT max
tWINDOW min
tWINDOW max
Safe Trigger area
Watchdog Safe
Trigger Area
Writing FF to 8'h15
图 10-4. Window Watchdog Timing Diagram
10.3.12.4 Question and Answer Watchdog
The TCAN1164-Q1 has a watchdog timer that supports the window watchdog as well as the Q&A watchdog.
节 10.3.12.5 explains the WD initialization events.
10.3.12.4.1 WD Question and Answer Basic information
A Question and Answer (Q&A) watchdog is a type of watchdog where instead of simply resetting the watchdog
via a SPI write or a pin toggle, the MCU reads a ‘question’ from the TCAN1164-Q1 do math based on the
question and then write the computed answers back to the TCAN1164-Q1. The correct answer is a four byte
response. Each byte must be written in order and with the correct timing to have a correct answer.
There are two watchdog windows; referred to as WD Response window #1 and WD Response window #2 (图
10-5 WD QA Windows as example). The size of each window will be 50% of the total watchdog time, which is
selected from the WD_TIMER and WD_PRE register bits.
Each watchdog question and answer is a full watchdog cycle. The general process is the MCU reads the
question, when the question is read, the timer starts. The CPU must perform a mathematical function on the
question, resulting in four bytes of answers. Three of the four answer bytes must be written to the answer
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register within the first window, in correct order. The last answer must be written to the answer register after
the first response window, inside of WD Response Window #2. If all four answer bytes were correct and in the
correct order, then the response is considered good and a new question is generated, starting the cycle over
again. Once the fourth answer is written into WD Response Window #2, that window is terminated and a new
WD Response Window #1 is started.
If anything is incorrect or missed, the response is considered bad and the watchdog question will NOT change.
In addition, an error counter will be incremented. Once this error counter hits a threshold (defined in the
WD_ERR_CNT register field), the watchdog failure action will be performed. Examples of actions are an
interrupt, or reset toggle, etc.
WD RESPONSE WINDOW #1
WD RESPONSE WINDOW #2
Three correct SPI WD question responses have to be scheduled in this
interval, in the correct order:
The final correct SPI WD question Response (WD_ANSWER_RESP_0) has
to be scheduled in this time interval.
‹
‹
‹
WD_ANSWER_RESP_3 followed by
WD_ANSWER_RESP_2 followed by
WD_ANSWER_RESP_1
After the last correct SPI-WD answer response, the next WD question is
generated within 1 sys. clock cycle (typ. 125ns), after which next WD
response WINDOW 1 (Q&A+1) starts
After tWD_RESP_WIN1 time elapsed, WD response WINDOW 2 begins.
Responses (”answers‘) are written to WD_QA_ANSWER register.
The SPI WD question-response sequence order is important.
WD Question
Request
WD Question Response Sequence
SPI WD Question Sequence Responses(2)
SPI Question
Required(1)
RD_WD_
QUESTION
WD_ANSWER
_RESP_0
WD_ANSWER
_RESP_3
WD_ANSWER
_RESP_2
WD_ANSWER
_RESP_1
SPI
Commands
nCS pin
1 internal system clock cycle (1µs)
to generate new WD Question for Q&A+1
Q&A [n]
tWD_RESP_WIN1 + tWD_RESP_WIN2
Q&A [n+1]
A. The MCU is not required to request the WD question. The MCU can start with correct answers, WD_ANSWER_RESP_x bytes
anywhere within RESPONSE WINDOW 1. The new WD question is always generated within one system clock cycle after the final
WD_ANSWER_RESP_0 answer during the previous WD Q&A sequence run.
B. The MCU can schedule other SPI commands between the WD_ANSWER_RESPx responses (even a command requesting the WD
question) without any impact to the WD function as long as the WD_ANSWER_RESP_[3:1] bytes are provided within the RESPONSE
WINDOW 1 and WD_ANSWER_RESP_0 is provided within the RESPONSE WINDOW 2.
图 10-5. WD Q&A Sequence Run for WD Q&A Multi-Answer Mode
10.3.12.4.2 Question and Answer Register and Settings
There are several registers used to configure the watchdog registers, 表 10-4.
表 10-4. List of Watchdog Related Registers
Register
Address
Register Name
Description
0x13
WD_CONFIG_1
Watchdog configuration and action in event of a failure
Sets the time of the window, and shows current error counter value
Register to reset or start the watchdog
0x14
0x15
0x16
0x2D
0x2E
WD_CONFIG_2
WD_INPUT_TRIG
WD_RST_PULSE
WD_QA_CONFIG
WD_QA_ANSWER
Reset pulse width in event of watchdog failure
Configuration related to the QA configuration
Register for writing the calculated answers
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表 10-4. List of Watchdog Related Registers (continued)
Register
Address
Register Name
Description
0x2F
WD_QA_QUESTION
Reading the current QA question
The WD_CONFIG_1 and WD_CONFIG_2 registers mainly deal with setting up the watchdog window time
length. Refer to 表 10-3 to see the options for window sizes, and the required values for the WD_TIMER values
and WD_PRE values. Take note that each of the 2 response windows are half of the selected value. Due to the
need for several bytes of SPI to be used for each watchdog QA event, it is recommended that windows greater
than 64 ms be used when using the QA watchdog functionality.
There are also different actions that can be performed when the watchdog error counter hits the error counter
threshold.
10.3.12.4.3 WD Question and Answer Value Generation
The 4-bit WD question, WD_QA_QUESTION[3:0], is generated by 4-bit Markov chain process. A Markov chain
is a stochastic process with Markov property, which means that state changes are probabilistic, and the future
state depends only on the current state. The valid and complete WD answer sequence for each WD Q&A mode
is as follows:
•
For WD Q&A multi-answer:
1. Three correct SPI WD answers are received during RESPONSE WINDOW 1.
2. One correct SPI WD answer is received during RESPONSE WINDOW 2.
3. In addition to the previously listed timing, the sequence of four responses shall be correct.
The WD question value is latched in the WD_QUESTION[3:0] bits of the WD_QA_QUESTION register and can
be read out at any time.
The Markov chain process is clocked by the 4-bit Question counter at the transition from b1111 to b0000.
This includes the condition of a correct answer (correct answer value and correct timing response). The logic
combination of the 4-bit questions WD_QUESTION [3:0] generation is given in 图 10-6.
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4-bit LFSR Polynomial Equation
WD_Q&A_POLY_CFG [5:4] = 0x00: y = x4 + x3 + 1 (default value)
WD_Q&A_POLY_CFG [5:4] = 0x01: y = x4 + x2 + 1
WD_Q&A_POLY_CFG [5:4] = 0x10: y = x3 + x2 + 1
WD_Q&A_POLY_CFG [5:4] = 0x11: y = x4 + x3 + x2 + 1
Note: if current y value is 0000, next y value will be 0001 and further WD Question generation
process starts from there
X2
X3
X4
X1
Bit 0
Bit 2
Bit 1
Bit 3
Clocked on CNT
0xF -> 0x0
transition
( choice of SEED value determines the order of states )
( programmable through WD_Q&A_POLY_SEED [3:0] register )
X1
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
X2
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
X3
1
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
X4
0
1
0
1
1
1
1
0
0
0
1
0
0
1
1
0
SEED
1
2
x2
00
01
10
11
x1
WD_QUESTION [0]
3
x4
x3
4
5
CNT[1]
00
01
10
11
6
CNT[0]
CNT[3]
CNT[2]
7
8
9
x4
00
01
10
11
10
11
12
13
14
15
x3
x2
WD_QUESTION [1]
x1
CNT[3]
CNT[2]
CNT[1]
CNT[0]
00
01
10
11
Default QUESTION sequence order with default
QUESTION_SEED and FDBK bit values
00
01
10
11
x1
x4
x3
x2
WD_QUESTION [2]
WDT QUESTION
Counter
CNT[0]
CNT[3]
CNT[2]
CNT[1]
00
01
10
11
CNT [0]
CNT[0]
CNT[1]
CNT[2]
CNT[3]
CNT [1]
CNT [2]
CNT [3]
INCR + 1
trigger
VALID WD ANSWER
(i.e. —good“ event)
x3
x2
x1
x4
00
01
10
11
4 valid responses returned by MCU in
correct sequence and timing
WD_QUESTION [3]
CNT[2]
CNT[1]
CNT[0]
CNT[3]
00
01
10
11
Feedback Settings through
WD_ANSW_GEN_CFG [7:6] register bit settings
(default value 0x00 - i.e. signal marked in red)
A. If the current y value is 0000, the next y value is 0001. The next watchdog question generation process starts from that value.
图 10-6. Watchdog Question Generation
表 10-5 contains the answers for each question, as long as the question polynomial and answer generation
configuration are both at their default values.
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表 10-5. Example answers to questions with default settings
QUESTION IN
WD_QUESTION_VALUE
REGISTER
WD ANSWER BYTES (EACH BYTE TO BE WRITTEN INTO WD_QA_ANSWER REGISTER)
WD_ANSWER_RESP_3 WD_ANSWER_RESP_2 WD_ANSWER_RESP_1 WD_ANSWER_RESP_0
WD_QUESTION
WD_ANSW_CNT 2'b11
WD_ANSW_CNT 2'b10
WD_ANSW_CNT 2'b01
WD_ANSW_CNT 2'b00
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
FF
B0
E9
A6
75
3A
63
2C
D2
9D
C4
8B
58
17
4E
01
0F
40
19
56
85
CA
93
DC
22
6D
34
7B
A8
E7
BE
F1
F0
BF
E6
A9
7A
35
6C
23
DD
92
CB
84
57
18
41
0E
00
4F
16
59
8A
C5
9C
D3
2D
62
3B
74
A7
E8
B1
FE
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00
01
10
11
WD_QUESTION [0]
WD_QUESTION [1]
WD_QUESTION [2]
WD_QUESTION [3]
WD_QA_ANSWER [0]
WD_ANSW_CNT [1]
( from WD_QA_QUESTION register )
00
01
10
11
WD_QUESTION [3]
WD_QUESTION [2]
WD_QUESTION [1]
WD_QUESTION [0]
00
01
10
11
WD_QUESTION [0]
WD_QUESTION [1]
WD_QUESTION [2]
WD_QUESTION [3]
WD_QA_ANSWER [1]
00
01
10
11
WD_QUESTION [2]
WD_QUESTION [1]
WD_QUESTION [0]
WD_QUESTION [3]
WD_QUESTION [1]
WD_ANSW_CNT [1]
( from WD_QA_QUESTION register )
WD_QUESTION [0]
WD_QUESTION [3]
WD_QUESTION [1]
WD_QUESTION [1]
00
01
10
11
WD_QA_ANSWER [2]
WD_QUESTION [3]
WD_QUESTION [2]
WD_QUESTION [1]
WD_QUESTION [0]
00
01
10
11
WD_QUESTION [1]
WD_ANSW_CNT [1]
( from WD_QA_QUESTION register )
00
01
10
11
WD_QUESTION [2]
WD_QUESTION [1]
WD_QUESTION [0]
WD_QUESTION [3]
WD_QA_ANSWER [3]
WD_QUESTION [0]
WD_QUESTION [3]
WD_QUESTION [2]
WD_QUESTION [1]
00
01
10
11
WD_QUESTION [3]
WD_ANSW_CNT [1]
( from WD_QA_QUESTION register )
TOKEN [1]
TOKEN [0]
TOKEN [2]
TOKEN [3]
00
01
10
11
WD_QA_ANSWER [4]
WD_ANSW_CNT [0]
( from WD_QA_QUESTION register )
00
01
10
11
WD_QUESTION [3]
WD_QUESTION [2]
WD_QUESTION [1]
WD_QUESTION [0]
WD_QA_ANSWER [5]
WD_ANSW_CNT [0]
( from WD_QA_QUESTION register )
WD_QUESTION [0]
WD_QUESTION [3]
WD_QUESTION [2]
WD_QUESTION [1]
00
01
10
11
WD_QA_ANSWER [6]
WD_ANSW_CNT [0]
( from WD_QA_QUESTION register )
00
01
10
11
WD_QUESTION [2]
WD_QUESTION [1]
WD_QUESTION [0]
WD_QUESTION [3]
WD_QA_ANSWER [7]
WD_ANSW_CNT [0]
( from WD_QA_QUESTION register )
Feedback Settings Controllable through
WD_ANSW_GEN_CFG [7:6] register bit settings
( default value 0x00, signals marked in red )
Expected Answers to be written into
WD_QA_ANSWER register
图 10-7. WD Expected Answer Generation
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表 10-6. Correct and Incorrect WD Q&A Sequence Run Scenarios for WD Q&A Multi-Answer Mode
(WD_CFG = 0b)
WD STATUS BITS IN
NUMBER OF WD ANSWERS
WD_QA_QUESTION REGISTER
ACTION
COMMENTS
RESPONSE
WINDOW 1
RESPONSE
WINDOW 2
QA_ANSW_ERR
WD_ERR(1)
-New WD cycle starts after the end of
RESPONSE WINDOW 2
0 answer
0 answer
0 answer
0 answer
-Increment WD failure counter
-New WD cycle starts with the same WD
question
0b
1b
No answers
-New WD cycle starts after the 4th WD
answer
-Increment WD failure counter
-New WD cycle starts with the same WD
question
4 INCORRECT answer
4 CORRECT answer
1b
0b
0b
1b
0b
1b
0b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
1b
Total WD_ANSW_CNT[1:0] = 4
Total WD_ANSW_CNT[1:0] = 4
-New WD cycle starts after the 4th WD
answer
-Increment WD failure counter
-New WD cycle starts with the same WD
question
0 answer
1 CORRECT answer
1 CORRECT answer
-New WD cycle starts after the end of
RESPONSE WINDOW 2
-Increment WD failure counter
-New WD cycle starts with the same WD
question
Less than 3 CORRECT ANSWER
in RESPONSE WINDOW 1 and 1
CORRECT ANSWER in RESPONSE
WINDOW 2 (Total WD_ANSW_CNT[1:0]
< 4)
1 CORRECT answer
2 CORRECT answer
1 CORRECT answer
0 answer
1 INCORRECT answer
1 INCORRECT answer
-New WD cycle starts after the end of
RESPONSE WINDOW 2
-Increment WD failure counter
-New WD cycle starts with the same WD
question
Less than 3 CORRECT ANSWER
in RESPONSE WINDOW 1 and 1
INCORRECT ANSWER in RESPONSE
WINDOW 2 (Total WD_ANSW_CNT[1:0]
< 4)
1 CORRECT answer
2 CORRECT answer
1 INCORRECT answer
0 answer
4 CORRECT answer
3 CORRECT answer
-New WD cycle starts after the 4th WD
answer
-Increment WD failure counter
-New WD cycle starts with the same WD
question
Less than 3 CORRECT ANSWER in
WIN1 and more than 1 CORRECT
ANSWER in RESPONSE WINDOW 2
(Total WD_ANSW_CNT[1:0] = 4)
1 CORRECT answer
2 CORRECT answer
2 CORRECT answer
0 answer
4 INCORRECT answer
3 INCORRECT answer
-New WD cycle starts after the 4th WD
answer
-Increment WD failure counter
-New WD cycle starts with the same WD
question
Less than 3 CORRECT ANSWER in
RESPONSE WINDOW 1 and more than
1 INCORRECT ANSWER in RESPONSE
WINDOW 2 (Total WD_ANSW_CNT[1:0]
= 4)
1 CORRECT answer
2 CORRECT answer
0 answer
2 INCORRECT answer
-New WD cycle starts after the end of
RESPONSE WINDOW 2
-Increment WD failure counter
-New WD cycle starts with the same WD
question
3 CORRECT answer
Less than 3 INCORRECT ANSWER in
RESPONSE WINDOW 1 and more than
1 CORRECT ANSWER in RESPONSE
WINDOW 2 (Total WD_ANSW_CNT[1:0]
< 4)
1 INCORRECT answer
2 INCORRECT answer
2 CORRECT answer
1 CORRECT answer
-New WD cycle starts after the end of
RESPONSE WINDOW 2
-Increment WD failure counter
-New WD cycle starts with the same WD
question
0 answer
3 INCORRECT answer
2 INCORRECT answer
-New WD cycle starts after the end of
RESPONSE WINDOW 2
-Increment WD failure counter
-New WD cycle starts with the same WD
question
Less than 3 INCORRECT ANSWER in
RESPONSE WINDOW 1 and more than
1 INCORRECT ANSWER in RESPONSE
WINDOW 2 (Total WD_ANSW_CNT[1:0]
< 4)
1 INCORRECT answer
2 INCORRECT answer
1 INCORRECT answer
0 answer
4 CORRECT answer
3 CORRECT answer
-New WD cycle starts after the 4th WD
answer
-Increment WD failure counter
-New WD cycle starts with the same WD
question
0b
1b
1b
1b
Less than 3 INCORRECT ANSWER in
RESPONSE WINDOW 1 and more than
1 CORRECT ANSWER in RESPONSE
WINDOW 2 (Total WD_ANSW_CNT[1:0]
= 4)
1 INCORRECT answer
2 INCORRECT answer
2 CORRECT answer
0 answer
4 INCORRECT answer
3 INCORRECT answer
-New WD cycle starts after the 4th WD
answer
-Increment WD failure counter
-New WD cycle starts with the same WD
question
Less than 3 INCORRECT ANSWER in
RESPONSE WINDOW 1 and more than
1 INCORRECT ANSWER in RESPONSE
WINDOW 2 (Total WD_ANSW_CNT[1:0]
= 4)
1 INCORRECT answer
1b
1b
2 INCORRECT answer
2 INCORRECT answer
3 CORRECT answer
2 CORRECT answer
0 answer
0 answer
-New WD cycle starts after the end of
RESPONSE WINDOW 2
-Increment WD failure counter
-New WD cycle starts with the same WD
Question
0b
0b
1b
1b
Less than 4 CORRECT ANSW in
RESPONSE WINDOW 1 and more than
0 ANSWER in RESPONSE WINDOW 2
(Total WD_ANSW_CNT[1:0] < 4)
1 CORRECT answer
0 answer
-New WD cycle starts after the 4th WD
answer
3 CORRECT answer
1 CORRECT answer
-Decrement WD failure counter
-New WD cycle starts with a new WD
question
0b
0b
CORRECT SEQUENCE
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表 10-6. Correct and Incorrect WD Q&A Sequence Run Scenarios for WD Q&A Multi-Answer Mode
(WD_CFG = 0b) (continued)
WD STATUS BITS IN
WD_QA_QUESTION REGISTER
NUMBER OF WD ANSWERS
ACTION
COMMENTS
RESPONSE
WINDOW 1
RESPONSE
WINDOW 2
QA_ANSW_ERR
WD_ERR(1)
-New WD cycle starts after the 4th WD
answer
3 CORRECT answer
3 INCORRECT answer
3 INCORRECT answer
3 INCORRECT answer
4 CORRECT answer
1 INCORRECT answer
-Increment WD failure counter
-New WD cycle starts with the same WD
question
1b
1b
Total WD_ANSW_CNT[1:0] = 4
-New WD cycle starts after the end of
RESPONSE WINDOW 2
-Increment WD failure counter
-New WD cycle starts with the same WD
question
0 answer
1b
1b
1b
0b
1b
1b
1b
1b
Total WD_ANSW_CNT[1:0] < 4
Total WD_ANSW_CNT[1:0] = 4
Total WD_ANSW_CNT[1:0] = 4
-New WD cycle starts after the 4th WD
answer
-Increment WD failure counter
-New WD cycle starts with the same WD
question
1 CORRECT answer
1 INCORRECT answer
Not applicable
-New WD cycle starts after the 4th WD
answer
-Increment WD failure counter
-New WD cycle starts with the same WD
question
-New WD cycle starts after the 4th WD
answer
-Increment WD failure counter
-New WD cycle starts with the same WD
question
3 CORRECT answer + 1
INCORRECT answer
Not applicable
Not applicable
Not applicable
-New WD cycle starts after the 4th WD
answer
-Increment WD failure counter
-New WD cycle starts with the same WD
question
2 CORRECT answer + 2
INCORRECT answer
4 CORRECT or INCORRECT ANSWER
in RESPONSE WINDOW 1
1b
1b
1 CORRECT answer + 3
INCORRECT answer
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10.3.12.5 Question and Answer WD Example
For this example, we’ll walk through a single sequence with the following configuration settings, 表 10-7.
表 10-7. Example Configuration Settings
Item
Value
Description
Watchdog window size
1024 ms
Window size of 1024 ms
Answer Generation Option
Question Polynomial
0 (default)
0 (default)
9 (default)
15
Answer generation configuration
Polynomial used to generate the question
Polynomial seed used to generate questions
On the 15th fail event, do the watchdog action
Question polynomial seed
WD Error Counter Limit
10.3.12.5.1 Example configuration for desired behavior
表 10-8 register writes will configure the part for the example behavior specified above. Most of the settings are
power on defaults.
表 10-8. Example Register Configuration Writes
Register
Step
Data
1
2
3
WD_CONFIG_1 (0x13)
[W] 0b11011101 / 0xDD
[W] 0b10000000 / 0x80
[W] 0b00001010 / 0x0A
WD_CONFIG_2 (0x14)
WD_QA_CONFIG (0x2D)
10.3.12.5.2 Example of performing a question and answer sequence
The normal sequence summary is as follows:
1. Read the question
2. Calculate the four answer bytes
3. Send three of them within the first response window
4. Wait and send the last byte in the second response window
See 表 10-9 for an example of the first loop sequence.
表 10-9. Example First Loop
Step
Register
Data
Description
WD_INPUT_TRIG
(0x15)
Start the watchdog (since it isn’t started yet), also keep a timer internally to flag
when response window 1 ends and window 2 starts.
1
2
3
4
5
6
[W] 0xFF
WD_QA_QUESTION
(0x2F)
[R] 0x3C
[W] 0x58
[W] 0xA8
[W] 0x57
[W] 0xA7
Read the question. Question is 0x3C
WD_QA_ANSWER
(0x2E)
Write answer 3 (See 表 10-5 example answers to questions with default settings
to see answers)
WD_QA_ANSWER
(0x2E)
Write answer 2
WD_QA_ANSWER
(0x2E)
Write answer 1
WD_QA_ANSWER
(0x2E)
Write answer 0 once window 2 has started
At this point, you can read the WD_QA_QUESTION (0x2F) register to see if the error counter has increased or if
QA ERROR is set.
10.3.13 Bus Fault Detection and Communication
The TCAN1164-Q1 provides advanced bus fault detection. TCAN1164-Q1 is used for illustration purposes. The
device can determine certain fault conditions and set a status/interrupt flag so that the MCU can understand
what the fault is. Detection takes place and is recorded if the fault is present during four dominant to recessive
transitions with each dominant bit being ≥ 2 µs. As with any bus architecture where termination resistors are at
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each end not every fault can be specified to the lowest level, meaning exact location. The fault detection circuitry
is monitoring the CANH and CANL pins (currents) to determine if there is a short to battery, short to ground,
short to each other or opens. From a system perspective, the location of the device can impact what fault can
be detected. See 图 10-8 as an example of node locations and how they can impact the ability to determine
the actual fault location. 图 10-9 through 图 10-13 show the various bus faults based upon the three node
configuration. 表 10-10 shows what can be detected and by which device. Fault 1 is detected as ½ termination
and Fault 2 is detected as no termination.
Bus fault detection is a system-level situation. If the fault is occurring at the ECU then the general
communication of the bus is compromised. For complete coverage of a node a system level diagnostic step
for each node and the ability to communicate this back to a central point is needed.
Device 2
TCAN1164
120
Device 1
CANH
TCAN1164
CANL
120
TCAN1164
Device 3
图 10-8. Three Node Example
Device 2
Device 2
Device 2
Device 2
TCAN1164
Fault 1
TCAN1164
Fault 1
TCAN1164
TCAN1164
Fault 2
Fault 2
120
120
120
120
Device 1
Device 1
Device 1
Device 1
CANH
CANL
CANH
CANL
CANH
CANL
CANH
CANL
TCAN1164
TCAN1164
TCAN1164
TCAN1164
120
120
120
120
TCAN1164
Device 3
TCAN1164
Device 3
TCAN1164
Device 3
TCAN1164
Device 3
ꢀꢁFault 1 is any case where ½ termination is seen
ꢀꢁFault 2 is any case where no termination is seen
图 10-9. Fault 1 and 2 Examples
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Device 2
Device 2
TCAN1164
TCAN1164
Fault 3
Fault 4
120
120
Device 1
Device 1
CANH
CANL
CANH
CANL
TCAN1164
TCAN1164
120
120
TCAN1164
Device 3
TCAN1164
Device 3
图 10-10. Fault 3 and 4 Examples
Device 2
Device 2
TCAN1164
Fault 6
TCAN1164
Fault 5
120
120
VBAT
Device 1
Device 1
TCAN1164
CANH
CANH
CANL
TCAN1164
CANL
120
120
TCAN1164
TCAN1164
Device 3
Device 3
图 10-11. Fault 5 and 6 Examples
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Device 2
Device 2
Device 2
TCAN1164
TCAN1164
Fault 8
Fault 7
TCAN1164
Fault 9
120
120
120
VBAT
CANH
Device 1
Device 1
Device 1
CANH
CANL
CANH
TCAN1164
TCAN1164
TCAN1164
CANL
CANL
120
120
120
TCAN1164
Device 3
TCAN1164
Device 3
TCAN1164
Device 3
图 10-12. Fault 7, 8 and 9 Examples
Device 2
Device 2
TCAN1164
120
Fault 11
TCAN1164
120
Fault 10
VBAT
Device 1
Device 1
CANH
CANL
CANH
CANL
TCAN1164
TCAN1164
120
120
TCAN1164
Device 3
TCAN1164
Device 3
图 10-13. Fault 10 and 11 Examples
表 10-10. Bus Fault Pin State and Detection Table
Fault #
CANH
Open
Open
CANL
Open
Open
Fault Detected
1
2
All positions see this fault as half termination and detect them
Depending upon open location the device detects this as no termination.
Yes but cannot tell the difference between it and Fault 2 and 4; Device 2 and
Device 3 does not see this fault
3
4
Open
Normal
Open
Yes but cannot tell the difference between it and Fault 2 and 3; Device 2 and
Device 3 does not see this fault
Normal
5
6
Shorted to CANL
Shorted to Vbat
Shorted to GND
Normal
Shorted to CANH Yes but not location
Normal
Normal
Yes but not location
7
Yes but cannot tell the difference between this and Fault 10
Yes but cannot tell the difference between this and Fault 11
8
Shorted to Vbat
9
Normal
Shorted to GND Yes but not location
10
11
Shorted to GND
Shorted to Vbat
Shorted to GND Yes but cannot tell the difference between this and Fault 7
Shorted to Vbat
Yes but cannot tell the difference between this and Fault 8
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表 10-11. Bus Fault Interrupt Flags Mapping to Fault Detection Number
DEFAUL
Address BIT(S)
FLAG
DESCRIPTION
FAULT DETECTED
T
7
6
1'b0
RSVD
Reserved
CANBUSTERMOP
EN
1'b0
CAN Bus has one termination point open
Fault 1
R/WC
5
4
1'b0
1'b0
1'b0
1'b0
CANHCANL
CANHBAT
CANLGND
CANH and CANL Shorted Together
CANH Shorted to Vbat
Fault 5
Fault 6
R/WC
R/WC
R/WC
R/WC
8'h54
3
2
CANL Shorted to GND
Fault 9
CANBUSOPEN CAN Bus Open (One of three possible places)
Faults 2, 3 and 4
CANH Shorted to GND or Both CANH &
CANBUSGND
1
0
1'b0
1'b0
Faults 7 and 10
Faults 8 and 11
R/WC
R/WC
CANL Shorted to GND
CANL Shorted to Vbat or Both CANH & CANL
CANBUSBAT
Shorted to Vbat
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10.4 Device Functional Modes
1
1
TJ > TTSD
Fail-safe Mode2
TJ < TTSD
VCCOUT > OVVCCOUT
&
VSUP < UVVSUP(F)
VCCOUT < OVVCCOUT
Reset event
MODE_SEL = 101
Silent Mode
Power Off
VSUP > UVVSUP(R)
Reset
nRST = H
MODE_SEL = 111
VCCOUT < UVVCCOUT
MODE_SEL = 101
Normal Mode
MODE_SEL = 111
MODE_SEL = 100
Standby Mode
1 From any mode except power off
2 To exit fail-safe mode all faults must be cleared
图 10-14. TCAN1164 State Machine
表 10-12. TCAN1164 Mode Overview
Block
Power Off
Reset
Fail-safe
Normal
Standby
Silent
VCCOUT
Off
On
Off
On
On
On
Low Power CAN
RX
Off
Off
Fault determines
Off
Active
Off
CAN Transmitter
CAN Receiver
Off
Off
CAN Autonomous
CAN Autonomous
Off
Off
CAN Active
CAN Active
CAN Autonomous
CAN Autonomous
Off
Active
Entrance
Dependent
RXD
High impedance
VCCOUT
VCCOUT
Mirrors Bus State
Mirrors Bus State
Watchdog
SPI
Off
Off
Off
Active
Active
Active
Active
Active
Active
Disabled
Disabled
Fault determines
10.4.1 Operating Mode Description
10.4.1.1 Normal Mode
This is the normal operating mode of the device. The CAN driver and receiver are fully operational and CAN
communication is bi-directional. The driver is translating a digital input on TXD to a differential output on CANH
and CANL. The receiver is translating the differential signal from CANH and CANL to a digital output on RXD.
The tINACTIVE timer in not active in normal mode.
10.4.1.2 Silent Mode
Silent mode is commonly referred to as listen only and receive only mode. In this mode, the CAN driver is
disabled but the receiver is fully operational and CAN communication is unidirectional into the device. The
receiver is translating the differential signal from CANH and CANL to a digital output on the RXD terminal.
Silent mode is similar to normal mode, excep that TXD is ignored. RXD works just the same as normal mode.
10.4.1.3 Standby Mode
The RXD output pin is asserted low while in standby mode if the a wake event or a fault is detected. Note that a
POR counts as a wake event and will also cause RXD to latch low.
In standby mode a fail-safe timer, tINACTIVE, is enabled. The tINACTIVE timer add an additional layer of protection
by requiring the system controller to configure the TCAN1164-Q1 to normal mode before it expires. This feature
forces the TCAN1164-Q1 to transition to its lowest power mode, standby mode with a SWE interrupt flag set, if
the processor does not come up properly.
10.4.1.3.1 Wake-Up Pattern (WUP) Detection in Standby Mode
The TCAN1164-Q1 is capable of detecting a wake-up pattern (WUP), even while in standby mode.
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The wake-up pattern (WUP) consists of a filtered dominant bus, then a filtered recessive bus time followed by
a second filtered bus time. The first filtered dominant initiates the WUP and the bus monitor is now waiting on
a filtered recessive, other bus traffic do not reset the bus monitor. Once a filtered recessive is received, the bus
monitor is now waiting on a filtered dominant. The other bus traffic do not reset the bus monitor. Immediately
upon receiving of the second filtered dominant, the bus monitor recognizes the WUP and drives the RXD
terminal low.
The WUP consists of:
•
•
•
A filtered dominant bus of at least tWK_FILTER followed by
A filtered recessive bus time of at least tWK_FILTER followed by
A second filtered dominant bus time of at least tWK_FILTER
For a dominant or recessive to be considered “filtered”, the bus must be in that state for more than tWK_FILTER
time. Due to variability in the tWK_FILTER the following scenarios are applicable. Bus state times less than
tWK_FILTER(MIN) are never detected as part of a WUP, and thus no wake request is generated. Bus state times
between tWK_FILTER(MIN) and tWK_FILTER(MAX) may be detected as part of a WUP, and a wake request may be
generated. Bus state times more than tWK_FILTER(MAX) are always detected as part of a WUP, and thus a wake
request is generated. See 图 10-15for the timing diagram of the WUP.
The pattern and tWK_FILTER time used for the WUP and wake request prevents noise and bus stuck dominant
faults from causing false wake requests while allowing any CAN or CAN FD message to initiate a wake request.
ISO11898-2:2016 has two sets of times for a short and long wake-up filter times. The tWK_FILTER timing for the
TCAN1164-Q1 has been picked to be within the min and max values of both filter ranges. This timing has been
chosen such that a single bit time at 500 kbps, or two back to back bit times at 1 Mbps triggers the filter in either
bus state.
For an additional layer of robustness and to prevent false wake-ups, the device implements the tWK_TIMEOUT
timer. For a remote wake-up event to successfully occur, the entire wake-up pattern must be received within the
timeout value. If a the full wake-up pattern is not received before the tWK_TIMEOUT expires, then the internal logic
is reset. The full pattern must then be transmitted again within the tWK_TIMEOUT window.
Wake-Up Pattern (WUP) received in t < tWK_TIMEOUT
Wake Request
Filtered
Dominant
Filtered
Dominant
Filtered
Recessive
Waiting for
Filtered
Waiting for
Filtered
Dominant
Recessive
Bus
Bus VDiff
tWK_FILTER
tWK_FILTER
tWK_FILTER
WUP Detect
图 10-15. Wake-Up Pattern (WUP)
10.4.1.4 Reset Mode
Reset mode is a low power mode of the TCAN1164-Q1 where the nRST pin is asserted low allowing the
controller to power up correctly. In this state the CAN transmitter and receiver are off, the bus pins are biased to
ground, and the transceiver cannot send or receive data.
While in reset mode the receiver actively monitors the CAN bus for a valid wake-up pattern. If a valid wake-up
pattern is received the CAN bus pins transition to the CAN autonomous active state where CANH and CANL
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are internally biased to 2.5 V from the VSUP power rail. The reception of a valid wake-up pattern generates a
wake-up request by the CAN transceiver that is output to the RXD pin.
The TCAN1164-Q1 will enter reset mode due to following conditions:
•
•
Power-on
nRST pulled low externally
The TCAN1164-Q1 will enter reset mode upon clearing any of the following fault conditions and leaving fail-safe
mode:
•
•
TJ < TSDF
Over voltage event
10.4.1.5 Fail-safe Mode
Fail-safe mode is a low power mode in which the TCAN1164-Q1 is in a protected state. While in fail-safe mode
the internal regulator (VCCOUT) is off, the reset pin is low, and the CAN transmitter and receiver are off.
Fail-safe mode is entered if:
•
•
TJ > TSDR
VVCCOUT > OVCCOUTR
Fail-safe mode is exited if all of the following criteria are met:
•
•
•
TJ < TSDF
VVCCOUT < OVCCOUTF
A valid wake-up event exists
If the fault condition is not cleared within tINACTIVE then the device will set the SWE interrupt, but will remain in
standby mode.
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10.4.2 CAN Transceiver
10.4.2.1 CAN Transceiver Operation
The TCAN1164-Q1 CAN transverse has three modes of operation; CAN active, CAN autonomous active, and
CAN autonomous inactive.
10.4.2.2 CAN Transceiver Modes
The TCAN1164-Q1 supports the ISO 11898-2:2016 CAN physical layer standard autonomous bus biasing
scheme. Autonomous bus biasing enables the transceiver to switch between CAN active, CAN autonomous
active, and CAN autonomous inactive which helps to reduce RF emissions.
CAN Active
CAN Transmitter: on2
CAN Receiver: on
RXD: Mirrors CAN bus
CANH & CANL: VCCOUT/2 (~2.5 V)
From any mode
VSUP < UVSUPF
TJ > TSDR
CAN Off
CAN Transmitter: off
CAN Receiver: off
RXD: high
CANH & CANL: floating
CAN Autonomous: Inactive
CAN Transmitter: off
CAN Receiver: off
RXD: wake-up/high
CANH & CANL: bias to GND
CAN Autonomous: Active
CAN Transmitter: off
WUP or (normal & (VCCOUT < UVCCOUTR))
t > tSILENCE & (fail-safe or standby)
VSUP > UVSUPR
TJ < TSDF
CAN Receiver: off
RXD: low signals wake-up1
CANH & CANL: bias to 2.5 V from VSUP
1 Wake-up inactive in normal mode
2 CAN transmitter is on in normal mode. It is off in silent mode.
图 10-16. TCAN1164 CAN Transceiver State Machine
10.4.2.2.1 CAN Off Mode
In CAN off mode the CAN transceiver is switched off and the CAN bus lines are truly floating. In this mode the
device presents no load to the CAN bus while preventing reverse currents from flowing into the device if the
battery or ground connection is lost.
The CAN off state is entered if:
•
•
TJ > TSDR
VSUP < UVSUPF
The CAN transceiver switches between the CAN off state and CAN autonomous inactive mode if:
•
•
VSUP > UVSUPR
TJ < TSDF
10.4.2.2.2 CAN Autonomous: Inactive and Active
When the CAN transceiver is in standby mode the CAN bias circuit is switched off and the transceiver moves to
the autonomous inactive state. In the autonomous inactive state the CAN pins are biased to GND. When a valid
wake-up event occurs the CAN bus is biased to 2.5 V. If the controller does not transition the TCAN1164-Q1 into
normal mode before the tSILENCE timer expires, then the CAN biasing circuit is again switched off and the CAN
pins are biased to ground.
The CAN transceiver switches to the CAN autonomous mode if any of the following conditions are met:
•
The TCAN1164-Q1 transitions from CAN off mode to CAN autonomous inactive
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The CAN transceiver switches between the CAN autonomous inactive mode and CAN autonomous active mode
if:
•
•
A valid wake-up event
The TCAN1164-Q1 transitions to normal mode and no undervoltage faults exist.
The CAN transceiver switches between the CAN autonomous active mode and CAN autonomous inactive mode
if:
•
t > tSILENCE and the TCAN1164-Q1 transitions to standby mode, or fail-safe mode.
10.4.2.2.3 CAN Active
When the TCAN1164-Q1 is in normal mode the CAN transceiver is in active mode. The CAN driver and receiver
are fully operational and CAN communication is bi-directional. The CAN bias voltage in CAN active mode is
derived from:
•
VCCOUT
The CAN transceiver switches between the CAN autonomous inactive or active mode and CAN active mode if:
The TCAN1164-Q1 transitions to normal mode and no undervoltage faults exist.
•
The CAN transceiver blocks its transmitter and receiver after entering CAN active mode if the TXD pin is
asserted low before leaving standby mode. This prevents disruptions to CAN bus in the event that the TXD pin
has a TXD DTO fault.
When the TCAN1164-Q1 is in silent mode the CAN driver is disabled, but the receiver is fully operational. The
CAN bias voltage is derived from the same CAN active mode.
10.4.2.3 Driver and Receiver Function Tables
表 10-13. Driver Function Table
BUS OUTPUTS
DEVICE MODE
TXD INPUTS(1)
DRIVEN BUS STATE(2)
CANH
CANL
Low
High
Low
Dominant
Normal
High or Open
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
Biased to VCCOUT/2
Biased to VCCOUT/2
Biased to GND
Silent
x
x
Standby
(1) x = irrelevant
(2) For bus states and typical bus voltages see 图 10-17
表 10-14. Receiver Function Table
CAN DIFFERENTIAL INPUTS
DEVICE MODE
BUS STATE
RXD TERMINAL
VID = VCANH – VCANL
VID ≥ 0.9 V
Dominant
Indeterminate
Recessive
Open
Low
Indeterminate
High
0.5 V < VID < 0.9 V
VID ≤ 0.5 V
Normal/Silent
Open (VID ≈ 0 V)
VID ≥ 1.15 V
High
Dominant
Indeterminate
Recessive
Open
0.5 V < VID < 1.15 V
VID ≤ 0.4 V
High
Standby
Low if wake-up event persists
Open (VID ≈ 0 V)
10.4.2.4 CAN Bus States
The CAN bus has two logical states during operation: recessive and dominant. See 图 10-17.
A dominant bus state occurs when the bus is driven differentially and corresponds to a logic low on the TXD
and RXD pins. A recessive bus state occurs when the bus is biased to one half of the CAN transceiver supply
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voltage via the high resistance internal input resistors (RIN) of the receiver and corresponds to a logic high on the
TXD and RXD pins.
A dominant state overwrites the recessive state during arbitration. Multiple CAN nodes may be transmitting a
dominant bit at the same time during arbitration, and in this case the differential voltage of the CAN bus will
be greater than the differential voltage of a single CAN driver. The TCAN1164-Q1 CAN transceiver implements
low-power standby modes which enables a third bus state where the bus pins are biased to ground via the high
resistance internal resistors of the receiver.
Standby Mode
Normal Mode
CANH
VDIFF
VDIFF
CANL
Recessive
Dominant
Recessive
Time, t
图 10-17. Bus States
10.5 Programming
10.5.1 Serial Peripheral Interface (SPI) Communication
The SPI communication uses a standard SPI interface. Physically the digital interface pins are nCS (Chip Select
Not), SDI (Serial Data In), SDO (Serial Data Out) and SCLK (Serial Clock). Each SPI transaction is a 16, 24
or 32 bits containing an address and read/write command byte followed by one to three data bytes. The data
shifted out on the SDO pin for the transaction always starts with the Global Status Register (byte). This register
provides the high level status information about the device status. The two data bytes which are the ‘response’ to
the command byte are shifted out next. Data bytes shifted out during a write command is content of the registers
prior to the new data being written and updating the registers. Data bytes shifted out during a read command are
the content of the registers and the registers is not updated.
The SPI data input data on SDI is sampled on the low to high edge of the clock (SCLK). The SPI output data on
SDO is changed on the high to low edge of the clock (SCLK).
10.5.2 Serial Clock Input (SCLK)
This input pin is used to input the clock for the SPI to synchronize the input and output serial data bit streams.
The SPI data input, SDI, is sampled on the falling edge of SPI clock and the SPI data output, SDO, is changed
on the falling edge of the SPI clock. See 图 10-18
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SPI CLOCKING
ACTIONs: C = data capture, S = data shift,
L = load data out, P = process captured data
MODE 0 (CPOL = 0, CPHA = 0)
SCLK
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SDI. SDO
ACTION
L
C
S
C
S
C
S
C
S
C
S
C
S
C
S
C
L
C
S
C
S
C
S
C
S
C
S
C
S
C
S
C
P
P
INTERNAL
CLK
INTERNAL_CLK = !CS xor CLK
图 10-18. SPI Clocking
10.5.3 Serial Data Input (SDI)
The SDI pin is used to let the device know which register address is being read from or written to. During a
write, the number of clock cycles determines how many data bytes up to three will be loaded into sequential
addresses. The minimum number of clock cycles for a write is 16 supporting the initial address and write
command followed by one byte of data as seen in 图 10-19. The TCAN1164-Q1 supports burst read and write.
图 10-20 shows an example of a 32-bit write which includes the initial 7-bit address, write bit and three data
bytes. This all requires 32 clock cycles. Once the SPI is enabled by a low on nCS, the SDI samples the input
data on each rising edge of the SPI clock (SCLK). The data is shifted into an appropriate sized shift register and
after the correct number of clock cycles the shift register is full and the SPI transaction is complete. For a write
command code, the new data is written into the addressed register only after the exact number of clock cycles
have been shifted in by SCLK and the nCS has a rising edge to deselect the device. For a burst write if there are
31 clock cycles of SCLK (1 clock cycle less than the full 3 byte write), the third byte write won’t happen while the
first two bytes write will be executed. If the correct number of clock cycles and data are not shifted in during one
SPI transaction (nCS low), the SPIERR flag is set.
nCS
SCLK
SDI
R/W
= 1
ADDRESS [6:0]
DATA [7:0]
SDO
h’50[7:0]
Interrupt
Register
图 10-19. SPI Write
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Address 00h
Address 55h
Address 56h
Address 57h
Address 58h
Address 5Ah
nCS
SCLK
SDI
R/W
= 1
ADDRESS [6:0] = 56h
DATA [7:0]
DATA [7:0]
DATA [7:0]
SDO
50h[7:0]
Interrupt
Register
图 10-20. 32-bit SPI Burst Write
10.5.4 Serial Data Output (SDO)
This pin is high impedance until the SPI output is enabled via nCS. Once the SPI is enabled by a low on nCS,
the SDO is immediately driven high or low showing the global interrupt register 8'h50, bit 7. The Global Interrupt
register, INT_GLOBAL, is the first byte to be shifted out. The SDO pin provides data out from the device to the
processor. For a write command this is the only data that will be provided on the SDO pin. For a read command
he one to three bytes of data from successive address will be provided on the SDO line. 图 10-21 and 图 10-22
shows examples of a single address read and of a three sequential address read utilizing the 32-bit burst read.
The 32-bit burst read shows the global interrupt register followed by the three requested data bytes.
备注
If a read happens faster than 2 µs after a write the global fault flag status may not reflect any status
change that the write may have initiated.
nCS
SCLK
SDI
R/W
ADDRESS [6:0]
= 0
SDO
h’50[7:0]
Interrupt
Register
DATA [7:0]
图 10-21. SPI Read
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Address 00h
Address 03h
Address 04h
Address 05h
Address 06h
Address 5Ah
nCS
SCLK
SDI
R/W
= 0
ADDRESS [6:0] = 04h
SDO
50h[7:0]
Interrupt
Register
DATA [7:0]
DATA [7:0]
DATA [7:0]
图 10-22. 32-bit SPI Burst Read
10.5.5 Chip Select Not (nCS)
This input pin is used to select the device for a SPI transaction. The pin is active low, so while nCS is high
the Serial Data Output (SDO) pin of the device is high impedance allowing an SPI bus to be designed. When
nCS is low the SDO driver is activated and communication may be started. The nCS pin is held low for a SPI
transaction. A special feature on this device allows the SDO pin to immediately show the Global Fault Flag on a
falling edge of nCS.
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10.5.6 Registers
Device Registers lists the memory-mapped registers for the Device registers. All register offset addresses not
listed in Device Registers should be considered as reserved locations and the register contents should not be
modified.
表 10-15. Device Registers
Address
Acronym
Register Name
Section
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
0h + formula DEVICE_ID_y
Device Part Number
Major Revision
8h
9h
REV_ID_MAJOR
REV_ID_MINOR
Minor Revision
Ah + formula SPI_RSVD_x
SPI reserved registers
Read and Write Test Register SPI
Mode configurations
Watchdog configuration 1
Watchdog configuration 2
Watchdog input trigger
Q and A Watchdog configuration
Q and A Watchdog answer
Q and A Watchdog question
CAN Transceiver Status
Global Interrupts
Fh
Scratch_Pad_SPI
MODE_CNTRL
WD_CONFIG_1
WD_CONFIG_2
WD_INPUT_TRIG
WD_QA_CONFIG
WD_QA_ANSWER
WD_QA_QUESTION
STATUS
10h
13h
14h
15h
2Dh
2Eh
2Fh
40h
50h
51h
52h
53h
54h
56h
57h
58h
59h
INT_GLOBAL
INT_1
Interrupts
INT_2
Interrupts
INT_3
Interrupts
INT_CANBUS
INT_ENABLE_1
INT_ENABLE_2
INT_ENABLE_3
INT_ENABLE_CANBUS
INT_RSVD_y
CAN Bus fault interrupts
Interrupt enable for INT_1
Interrupt enable for INT_2
Interrupt enable for INT_3
Interrupt enable for INT_CANBUS
5Ah +
formula
Interrupt Reserved Register INT_RSVD0 through
INT_RSVD5
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Complex bit access types are encoded to fit into small table cells. Device Access Type Codes shows the codes
that are used for access types in this section.
表 10-16. Device Access Type Codes
Access Type
Code
Description
Read Type
R
R
Read
RH
H
R
Set or cleared by hardware
Read
Write Type
H
H
Set or cleared by hardware
Write
W
W
W1C
1C
W
1 to clear
Write
Reset or Default Value
-n
Value after reset or the default value
Register Array Variables
i,j,k,l,m,n
When these variables are used in a register name,
an offset, or an address, they refer to the value of a
register array where the register is part of a group
of repeating registers. The register groups form a
hierarchical structure and the array is represented
with a formula.
y
When this variable is used in a register name, an
offset, or an address it refers to the value of a
register array.
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10.5.6.1 DEVICE_ID_y Register (Address = 0h + formula) [reset = xxh]
DEVICE_ID_y is shown in 图 10-23 and described in 表 10-17.
Return to Summary Table.
Device Part Number
Offset = 0h + y; where y = 0h to 7h
图 10-23. DEVICE_ID_y Register
7
6
5
4
3
2
1
0
DEVICE_ID
R-xxh
表 10-17. DEVICE_ID_y Register Field Descriptions
Bit
7-0
Field
DEVICE_ID
Type
Reset
Description
R
0b
The DEVICE_ID[1:8] registers determine the part number of the
device.
The reset values and value of each DEVICE_ID register are listed for
the corresponding register address
Address 00h = 54h = T
Address 01h = 43h = C
Address 02h = 41h = A
Address 03h = 4Eh = N
Address 04h = 31h = 1
Address 05h = 31h = 1
Address 06h = 36h = 6
Address 07h = 34h = 4
10.5.6.2 REV_ID_MAJOR Register (Address = 8h) [reset = 00h]
REV_ID_MAJOR is shown in 图 10-24 and described in 表 10-18.
Return to Summary Table.
Major Revision
图 10-24. REV_ID_MAJOR Register
7
6
5
4
3
2
1
0
Major_Revision
R-00h
表 10-18. REV_ID_MAJOR Register Field Descriptions
Bit
7-0
Field
Major_Revision
Type
Reset
Description
R
00h
Major die revision
10.5.6.3 REV_ID_MINOR Register (Address = 9h) [reset = 00h]
REV_ID_MINOR is shown in 图 10-25 and described in 表 10-19.
Return to Summary Table.
Minor Revision
图 10-25. REV_ID_MINOR Register
7
6
5
4
3
2
1
0
Minor_Revision
R-00h
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表 10-19. REV_ID_MINOR Register Field Descriptions
Bit
Field
Minor_Revision
Type
Reset
Description
7-0
R
00h
Minor die revision
10.5.6.4 SPI_RSVD_x Register (Address = Ah + formula) [reset = 00h]
SPI_RSVD_x is shown in 图 10-26 and described in 表 10-20.
Return to Summary Table.
Configuration Reserved Bits Ah to Eh
Offset = Ah + x; where x = 0h to 4h
图 10-26. SPI_RSVD_x Register
7
6
5
4
3
2
1
0
0
0
SPI_RSVD_x
R-00h
表 10-20. SPI_RSVD_x Register Field Descriptions
Bit
7-0
Field
SPI_RSVD_x
Type
Reset
Description
R
00h
SPI reserved registers 0 - 4
10.5.6.5 Scratch_Pad_SPI Register (Address = Fh) [reset = 00h]
Scratch_Pad_SPI is shown in 图 10-27 and described in 表 10-21.
Return to Summary Table.
Read and Write Test Register SPI
图 10-27. Scratch_Pad_SPI Register
7
6
5
4
3
2
1
Scratch_Pad
R/W-00h
表 10-21. Scratch_Pad_SPI Register Field Descriptions
Bit
7-0
Field
Scratch_Pad
Type
Reset
Description
R/W
00h
Read and Write Test Register SPI
10.5.6.6 MODE_CNTRL Register (Address = 10h) [reset = 04h]
MODE_CNTRL is shown in 图 10-28 and described in 表 10-22.
Return to Summary Table.
Mode select and feature enable and disable register
图 10-28. MODE_CNTRL Register
7
6
5
4
3
2
1
RSVD
R-000b
FD_EN
R/W-0b
RSVD
R-0b
MODE_SEL
R/W-100b
表 10-22. MODE_CNTRL Register Field Descriptions
Bit
Field
Type
Reset
000b
0b
Description
7-5
4
RSVD
FD_EN
R
Reserved
R/W
Fault detection enable
0b = Disabled
1b = Enabled
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表 10-22. MODE_CNTRL Register Field Descriptions (continued)
Bit
3
Field
Type
Reset
Description
RSVD
R
0b
Reserved
2-0
MODE_SEL
R/W
100b
Mode of operation select
001b = Reserved
100b = Standby
101b = Silent
111b = Normal
备注
NOTE: The current mode will be read back and all other
values are reserved
10.5.6.7 WD_CONFIG_1 Register (Address = 13h) [reset = 54h]
WD_CONFIG_1 is shown in 图 10-29 and described in 表 10-23.
Return to Summary Table.
Watchdog configuration setup 1
图 10-29. WD_CONFIG_1 Register
7
6
5
4
3
2
1
0
WD_CONFIG
R/W-01b
WD_PRE
R/W-01b
WD_ERR_CNT_SET
R/W-01b
RSVD
R-0b
WD_EN
R/W-0b
表 10-23. WD_CONFIG_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-4
3-2
WD_CONFIG
WD_PRE
R/W
01b
Watchdog configuration
00b = Autonomous
01b = Timeout
10b = Window
11b = Q&A
R/W
R/W
01b
01b
Watchdog prescalar
0b = Factor 1
1b = Factor 2
10b = Factor 3
11b = Factor 4
WD_ERR_CNT_SET
Sets the watchdog event error counter that upon overflow the
watchdog output will trigger
0b = Immediate trigger on each WD event
1b = Triggers on the fifth error event
10b = Triggers on the ninth error event
11b = Triggers on the 15th error event
1
0
RSVD
R
0b
0b
Reserved
WD_EN
R/W
Watchdog enable
0b = Disabled
1b = Enabled
10.5.6.8 WD_CONFIG_2 Register (Address = 14h) [reset = 02h]
WD_CONFIG_2 is shown in 图 10-30 and described in 表 10-24.
Return to Summary Table.
Watchdog configuration setup 2
图 10-30. WD_CONFIG_2 Register
7
6
5
4
3
2
1
0
WD_TIMER
WD_ERR_CNT
RSVD
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图 10-30. WD_CONFIG_2 Register (continued)
R/W-000b
R/H-0001b
R-0b
表 10-24. WD_CONFIG_2 Register Field Descriptions
Bit
Field
WD_TIMER
Type
Reset
Description
7-5
R/W
000b
Sets window or timeout times based upon the WD_PRE setting
See WD_TIMER table
4-1
0
WD_ERR_CNT
RSVD
R/H
R
0001b
0b
Watchdog error counter
Running count of errors up to 15 errors
Reserved
10.5.6.9 WD_INPUT_TRIG Register (Address = 15h) [reset = 00h]
WD_INPUT_TRIG is shown in 图 10-31 and described in 表 10-25.
Return to Summary Table.
Writing FFh resets WD timer if accomplished at appropriate time
图 10-31. WD_INPUT_TRIG Register
7
6
5
4
3
2
1
0
WD_INPUT
W1C-00h
表 10-25. WD_INPUT_TRIG Register Field Descriptions
Bit
7-0
Field
WD_INPUT
Type
Reset
Description
R/W1C
00h
Write FFh to trigger WD
10.5.6.10 WD_QA_CONFIG Register (Address = 2Dh) [reset = 0h]
WD_QA_CONFIG is shown in 图 10-32 and described in 表 10-26.
Return to Summary Table.
Q&A watchdog configuration bits
图 10-32. WD_QA_CONFIG Register
7
6
5
4
3
2
1
0
WD_ANSW_GEN_CFG
R/W-00b
WD_Q&A_POLY_CFG
R/W-00b
WD_Q&A_POLY_SEED
R/W-0000b
备注
Upon power up, WD_Q&A_POLY_SEED will read back 0000b, but the actual seed value is 101b.
Once written to, the read back value and actual value will be the same.
表 10-26. WD_QA_CONFIG Register Field Descriptions
Bit
7-6
5-4
3-0
Field
Type
R/W
R/W
R/W
Reset
Description
WD_ANSW_GEN_CFG
WD_Q&A_POLY_CFG
WD_Q&A_POLY_SEED
00b
WD answer generation configuration
WD q&a polynomial configuration
00b
0000b
WD q&a polynomial seed value loaded when device is in the RESET
state
10.5.6.11 WD_QA_ANSWER Register (Address = 2Eh) [reset = 0h]
WD_QA_ANSWER is shown in 图 10-33 and described in 表 10-27.
Return to Summary Table.
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Q&A watchdog answer bits
图 10-33. WD_QA_ANSWER Register
7
6
5
4
3
2
1
0
WD_QA_ANSWER
R-00h
表 10-27. WD_QA_ANSWER Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
WD_QA_ANSWER
R/W
00h
MCU watchdog q&a answer response byte
10.5.6.12 WD_QA_QUESTION Register (Address = 2Fh) [reset = 0h]
WD_QA_QUESTION is shown in 图 10-34 and described in 表 10-28.
Return to Summary Table.
Q&A watchdog question bits
图 10-34. WD_QA_QUESTION Register
7
6
5
4
3
2
1
0
RSVD
QA_ANSW_ER
R
WD_ANSW_CNT
WD_QUESTION
R-0b
W1C-0b
R-00b
R-0000b
表 10-28. WD_QA_QUESTION Register Field Descriptions
Bit
7
Field
Type
Reset
Description
RSVD
R
0b
Reserved
6
QA_ANSW_ERR
WD_ANSW_CNT
W1C
R
0b
Watchdog q&a answer error flag
5-4
00b
Current state of received watchdog q&a error counter
When WD enabled value will show up as 2'h3
3-0
WD_QUESTION
R
0000b
Current watchdog question value
When WD is enabled value will show up as 4'hC
10.5.6.13 STATUS (address = 40h) [reset = 00h]
STATUS is shown in 表 10-29 and described in 表 10-30.
Return to Summary Table.
CAN transceiver status
表 10-29. STATUS Register
7
6
5
4
3
2
1
0
STATUS_RSVD
R-0000b
CAN_ACTIVE
R/U-0b
TSILENCE
R/U-0b
RSVD
R-0b
TXDDOM
R/U-0b
表 10-30. STATUS Register Field Description
Bit
7-4
3
Field
Type
Reset
0000b
0b
Description
STATUS_RSVD
CAN_ACTIVE
R
Reserved
R/U
CAN active mode
0b = No
1b = Yes
2
1
TSILENCE
RSVD
R/U
R
0b
0b
CAN bus in tSILINCE
0b = No
1b = Yes
Reserved
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表 10-30. STATUS Register Field Description (continued)
Bit
Field
TXDDOM
Type
Reset
Description
0
R/U
0b
TXD Low is preventing entering CAN Active mode
0b = No
1b = Yes
10.5.6.14 INT_GLOBAL Register (Address = 50h) [reset = 0h]
INT_GLOBAL is shown in 图 10-35 and described in 表 10-31.
Return to Summary Table.
Logical OR of all to certain interrupts
图 10-35. INT_GLOBAL Register
7
6
5
4
3
2
1
0
GLOBALERR
RH-0b
INT_1
RH-0b
INT_2
RH-0b
INT_3
RH-0b
INT_CANBUS
RH-0b
RSVD
R-0b
表 10-31. INT_GLOBAL Register Field Descriptions
Bit
7
Field
Type
RH
RH
RH
RH
RH
R
Reset
Description
GLOBALERR
INT_1
0b
Logical OR of all interrupts
Logical OR of INT_1 register
Logical OR of INT_2 register
Logical OR of INT_3 register
Logical OR of INT_CANBUS register
Reserved
6
0b
5
INT_2
0b
4
INT_3
0b
3
INT_CANBUS
RSVD
0b
2-0
0b
10.5.6.15 INT_1 Register (Address = 51h) [reset = 0h]
INT_1 is shown in 图 10-36 and described in 表 10-32.
Return to Summary Table.
Interrupts
图 10-36. INT_1 Register
7
6
5
4
3
2
1
0
WD
CANINT
R/W1C-0b
LWU
WKERR
R/W1C-0b
RSVD
R-0b
CANSLNT
R/W1C-0b
RSVD
R-0b
CANDOM
R/W1C-0b
R/W1C-0b
R/W1C-0b
表 10-32. INT_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
WD
R/W1C
0b
Watchdog event interrupt.
NOTE: This interrupt bit will be set for every watchdog error event
and does not reliy upon the Watchdog error counter
6
5
4
3
2
1
0
CANINT
LWU
R/W1C
R/W1C
R/W1C
R
0b
0b
0b
0b
0b
0b
0b
CAN bus wake up interrupt
Local wake up
WKERR
RSVD
Wake error bit is set when the SWE timer has expired
Reserved
CANSLNT
RSVD
R/W1C
R
CAN silent
Reserved
CANDOM
R/W1C
CAN bus stuck dominant
10.5.6.16 INT_2 Register (Address = 52h) [reset = 40h]
INT_2 is shown in 图 10-37 and described in 表 10-33.
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Return to Summary Table.
Interrupts
图 10-37. INT_2 Register
7
6
5
4
3
2
1
0
RSVD
R-0b
PWRON
R/W1C-1b
OVCCOUT
R/W1C-0b
UVSUP
R/W1C-0b
RSVD
R-0b
UVCCOUT
R/W1C-0b
TSD
TSDW
R/W1C-0b
R/W1C-0b
表 10-33. INT_2 Register Field Descriptions
Bit
7
Field
Type
Reset
Description
RSVD
R
0b
Reserved
6
PWRON
OVCCOUT
UVSUP
RSVD
R/W1C
R/W1C
R/W1C
R
1b
Power on
5
0b
VCCOUT overvoltage
VSUP undervoltage
Reserved
4
0b
3
0b
2
UVCCOUT
TSD
R/W1C
R/W1C
R/W1C
0b
VCCOUT undervoltage
Thermal Shutdown
Thermal Shutdown Warning
1
0b
0
TSDW
0b
10.5.6.17 INT_3 Register (Address 53h) [reset = 0h]
INT_3 is shown in 图 10-38 and described in 表 10-34.
Return to Summary Table.
图 10-38. INT_3 Register
7
6
5
4
3
2
1
0
SPIERR
R/W1C-0b
RSVD
R-00h
表 10-34. INT_3 Register Field Descriptions
Bit
7
Field
Type
R/W1C
R
Reset
Description
SPIERR
RSVD
0b
Sets when SPI status bit sets
Reserved
6-0
00h
10.5.6.18 INT_CANBUS Register (Address = 54h) [reset = 0h]
INT_CANBUS is shown in 图 10-39 and described in 表 10-35.
Return to Summary Table.
CAN bus faults that include shorts and opens
图 10-39. INT_CANBUS Register
7
6
5
4
3
2
1
CANBUSOPEN CANBUSGND
R/W1C-0b R/W1C-0b
0
RESERVED
R-0b
CANHCANL
R/W1C-0b
CANHBAT
R/W1C-0b
CANLGND
R/W1C-0b
CANBUSBAT
R/W1C-0b
表 10-35. INT_CANBUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7:6
5
RESERVED
CANHCANL
CANHBAT
R
0b
Reserved. Reads return 0.
CANH and CANL shorted together
CANH shorted to Vbat
CANL shorted to GND
CAN bus open
R/W1C
R/W1C
R/W1C
R/W1C
0b
4
0b
3
CANLGND
0b
2
CANBUSOPEN
0b
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表 10-35. INT_CANBUS Register Field Descriptions (continued)
Bit
1
Field
Type
Reset
Description
CANBUSGND
CANBUSBAT
R/W1C
R/W1C
0b
CAN bus shorted to GND or CANH shorted to GND
CAN bus shorted to Vbat or CANL shorted to Vbat
0
0b
10.5.6.19 INT_ENABLE_1 Register (Address = 56h) [reset = F3h]
INT_ENABLE_1 is shown in 图 10-40 and described in 表 10-36.
Return to Summary Table.
Interrupt mask for INT_1
图 10-40. INT_ENABLE_1 Register
7
6
5
4
3
2
1
0
WD_ENABLE CANINT_ENAB LWU_ENABLE WKERR_ENAB
RSVD
CANSLNT_EN
ABLE
RSVD
CANDOM_ENA
BLE
LE
LE
R/W-1b
R/W-1b
R/W-1b
R/W-1b
R-0b
R/W-1b
R-0b
R/W-1b
表 10-36. INT_ENABLE_1 Register Field Descriptions
Bit
7
Field
Type
R/W
R/W
R/W
R/W
R
Reset
Description
WD_ENABLE
CANINT_ENABLE
LWU_ENABLE
WKERR_ENABLE
RSVD
1b
Watchdog event interrupt enable
CAN bus wake up interrupt enable
Local wake up enable
Wake error enable
6
1b
5
1b
4
1b
3
0b
Reserved
2
CANSLNT_ENABLE
RSVD
R/W
R
1b
CAN silent enable
1
0b
Reserved
0
CANDOM_ENABLE
R/W
1b
CAN bus stuck dominant enable
10.5.6.20 INT_ENABLE_2 Register (Address = 57h) [reset = 3Fh]
INT_ENABLE_2 is shown in 图 10-41 and described in 表 10-37.
Return to Summary Table.
Interrupt mask for INT_2
图 10-41. INT_ENABLE_2 Register
7
6
5
4
3
2
1
0
RSVD
R-0b
OVCC_ENABL UVSUP_ENAB
RSVD
UVCC_ENABL TSD_ENABLE TSDW_ENABL
E
LE
E
E
R/W-1b
R/W-1b
R-0b
R/W-1b
R/W-1b
R/W-1b
表 10-37. INT_ENABLE_2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RSVD
R
0b
Reserved
OVCC_ENABLE
UVSUP_ENABLE
RSVD
R/W
R/W
R
1b
VCC over voltage enable
VSUP undervoltage enable
Reserved
4
1b
3
0b
2
UVCC_ENABLE
TSD_ENABLE
TSDW_ENABLE
R/W
R/W
R/W
1b
VCC undervoltage enable
Thermal shutdown enable
Thermal shutdown warning enable
1
1b
0
1b
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10.5.6.21 INT_ENABLE_3 Register (Address =58h) [reset = 80h]
INT_ENABLE_3 is shown in 图 10-42 and described in 表 10-38.
Return to Summary Table.
Interrupt mask for INT_3
图 10-42. INT_ENABLE_3 Register
7
6
5
4
3
2
1
0
SPIERR_ENAB
LE
RSVD
R/W-1b
R-00h
表 10-38. INT_ENABLE_3 Register Field Descriptions
Bit
7
Field
Type
R/W
R
Reset
Description
SPIERR_ENABLE
RSVD
1b
SPI error interrupt enable
Reserved
6-0
00h
10.5.6.22 INT_ENABLE_CANBUS Register (Address = 59h) [reset = 7Fh]
INT_ENABLE_CANBUS is shown in 图 10-43 and described in 表 10-39.
Return to Summary Table.
Interrupt mask for INT_CANBUS
图 10-43. INT_ENABLE_CANBUS Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
CANHCANL_E CANHBAT_EN CANLGND_EN CANBUSOPEN CANBUSGND_ CANBUSBAT_
NABLE
ABLE
ABLE
_ENABLE
ENABLE
ENABLE
R/W-1b
R/W-1b
R/W-1b
R/W-1b
R/W-1b
R/W-1b
表 10-39. INT_ENABLE_CANBUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7:6
5
RESERVED
R
0b
Reserved
CANHCANL_ENABLE
CANHBAT_ENABLE
CANLGND_ENABLE
R/W
R/W
R/W
1b
CANH and CANL shorted together enable
CANH shorted to Vbat enable
CANL shorted to GND enable
CAN bus open enable
4
1b
3
1b
2
CANBUSOPEN_ENABLE R/W
1b
1
CANBUSGND_ENABLE
CANBUSBAT_ENABLE
R/W
R/W
1b
CAN bus shorted to GND enable
CAN bus shorted to Vbat enable
0
1b
10.5.6.23 INT_RSVD_y Register (Address = 5Ah + formula) [reset = 00h]
INT_RSVD_y is shown in 图 10-44 and described in 表 10-40.
Return to Summary Table.
Register address 5Ah through 5Fh
Offset = 5Ah + (y * 1h); where y = 0h to 7h
图 10-44. INT_RSVD_y Register
7
6
5
4
3
2
1
0
RESERVED
R-00h
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表 10-40. INT_RSVD_y Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
7-0
R
00h
Reserved
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11 Application Information Disclaimer
备注
以下应用部分中的信息不属于 TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
11.1 Application Information
11.2 Typical Application
Sensor or other
component
VBAT
10
F
0.1
F
VCCOUT
VSUP
10
3
CANH
13
nCS
14
SCLK
8
TCAN1164
SDI
11
6
SDO
CAN FD
Controller
nRST
TXD
5
1
4
CANL
12
Optional:
Terminating
Node
RXD
Optional:
Filtering,
Transient and
ESD
2
GND
图 11-1. Typical Application
11.2.1 Design Requirements
11.2.1.1 Bus Loading, Length and Number of Nodes
A typical CAN application may have a maximum bus length of 40 meters and maximum stub length of 0.3 m.
However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a
bus. A high number of nodes requires a transceiver with high input impedance such as the TCAN1164-Q1
Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO
11898-2 standard. They made system level trade off decisions for data rate, cable length, and parasitic loading
of the bus. Examples of these CAN systems level specifications are ARINC 825, CANopen, DeviceNet, SAE
J2284, SAE J1939, and NMEA 2000.
A CAN network system design is a series of tradeoffs. In the ISO 11898-2:2016 specification the driver
differential output is specified with a bus load that can range from 50 Ω to 65 Ω where the differential output
must be greater than 1.5 V. The TCAN1164-Q1 is specified to meet the 1.5-V requirement down to 50 Ω and is
specified to meet 1.4-V differential output at 45Ω bus load. The differential input resistance of the TCAN1164-Q1
is a minimum of 40 kΩ. If 100 TCAN1164-Q1 devices are in parallel on a bus, this is equivalent to a 400-Ω
differential load in parallel with the nominal 60 Ω bus termination which gives a total bus load of approximately
52 Ω. Therefore, the TCAN1164-Q1 theoretically supports over 100 devices on a single bus segment. However,
for CAN network design margin must be given for signal loss across the system and cabling, parasitic loadings,
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timing, network imbalances, ground offsets and signal integrity thus a practical maximum number of nodes
is often lower. Bus length may also be extended beyond 40 meters by careful system design and data rate
tradeoffs. For example, CANopen network design guidelines allow the network to be up to 1 km with changes in
the termination resistance, cabling, less than 64 nodes and significantly lowered data rate.
This flexibility in CAN network design is one of the key strengths of the various extensions and additional
standards that have been built on the original ISO 11898-2 CAN standard. However, when using this flexibility
the CAN network system designer must take the responsibility of good network design to ensure robust network
operation.
11.2.2 Detailed Design Procedures
11.2.2.1 CAN Termination
Termination may be a single 120-Ω resistor at the end of the bus on either the cable or in a terminating
node. If filtering and stabilization of the common mode voltage of the bus is desired then split termination may
used, see 图 11-2. Split termination improves the electromagnetic emissions behavior of the network by filtering
higher-frequency common-mode noise that may be present on the differential signal lines..
Standard Termination
Split Termination
CANH
CANH
RTERM/2
RTERM
TCAN Transceiver
TCAN Transceiver
CSPLIT
RTERM/2
CANL
CANL
图 11-2. CAN Bus Termination Concepts
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11.3 Application Curves
3
2.75
2.5
-40 C
50 C
150 C
2.25
2
1.75
1.5
4
6
8
10 12 14 16 18 20 22 24 26 28
VSUP (V)
RL = 60 Ω
图 11-3. VOD(D) over VSUP
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12 Power Supply Requirements
The TCAN1164-Q1 is designed to operate from a VSUP input supply voltage range between 5.5 V and 28 V. Input
supplies must be well regulated. A bypass capacitance, typically 100 nF, should be placed close to the device
VSUP supply pin. This helps to reduce supply voltage ripple present on the outputs of the switched-mode power
supplies and also helps to compensate for the resistance and inductance of the PCB power planes and traces.
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13 Layout
13.1 Layout Guidelines
Place the protection and filtering circuitry as close to the bus connector to prevent transients, ESD and noise
from propagating onto the board. The layout example provides information on components around the device
itself. Transient voltage suppression (TVS) device can be added for extra protection. The production solution can
be either bi-directional TVS diode or varistor with ratings matching the application requirements. This example
also shows optional bus filter capacitors.
Design the bus protection components in the direction of the signal path. Do not force the transient current
to divert from the signal path to reach the protection device. Use supply and ground planes to provide low
inductance.
备注
A high-frequency current follows the path of least impedance and not the path of least resistance.
Use at least two vias for supply and ground connections of bypass capacitors and protection devices to minimize
trace and via inductance.
•
•
Bypass and bulk capacitors should be placed as close as possible to the supply terminals of transceiver.
Bus termination: this layout example shows split termination. This is where the termination is split into two
resistors with the center or split tap of the termination connected to ground via capacitor. Split termination
provides common mode filtering for the bus. When bus termination is placed on the board instead of directly
on the bus, additional care must be taken to ensure the terminating node is not removed from the bus thus
also removing the termination.
13.2 Layout Example
CAN Controller
To VIO
RES
RES
CAN Controller
TXD
nCS
CANH
CANL
SDI
GND
VCCOUT
RXD
nRST
SDO
NC
RES
RES
CAP
ESD
Connector
CAN Controller
CAN Controller
CAN Controller
CAN Controller
CAN Controller
RES
VSUP
VBAT
NC
SCLK
CAN Controller
图 13-1. TCAN1164 Example Layout
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14 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
14.1 Documentation Support
14.1.1 Related Documentation
14.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
14.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI
的《使用条款》。
14.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
14.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
14.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
15 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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28-Jul-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TCAN1164DMTRQ1
TCAN1164TDMTRQ1
ACTIVE
ACTIVE
VSON
VSON
DMT
DMT
14
14
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
1164
1164T
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
GENERIC PACKAGE VIEW
DMT 14
3 x 4.5, 0.65 mm pitch
VSON - 0.9 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225088/A
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PACKAGE OUTLINE
DMT0014B
VSON - 1 mm max height
SCALE 3.200
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
4.6
4.4
0.1 MIN
(0.13)
1.0
0.8
SECTION A-A
SCALE 30.000
SECTION A-A
TYPICAL
C
SEATING PLANE
0.08 C
0.05
0.00
1.6 0.1
SYMM
EXPOSED
THERMAL PAD
(0.2) TYP
7
8
(0.19) TYP
A
A
2X
3.9
15
SYMM
4.2 0.1
14
1
12X 0.65
0.35
0.25
14X
0.45
0.35
PIN 1 ID
14X
0.1
C A B
(OPTIONAL)
0.05
C
4225087/B 01/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DMT0014B
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.6)
14X (0.6)
14X (0.3)
SYMM
1
14
2X
(1.85)
12X (0.65)
SYMM
15
(4.2)
(0.69)
TYP
(
0.2) VIA
TYP
8
7
(R0.05) TYP
(0.55) TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225087/B 01/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DMT0014B
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.47)
15
14X (0.6)
1
14
14X (0.3)
(1.18)
12X (0.65)
SYMM
(1.38)
(R0.05) TYP
METAL
TYP
8
7
SYMM
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 15
77.4% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4225087/B 01/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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Copyright © 2022，德州仪器 (TI) 公司
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具有 VIO 和待机功能的汽车类信号改善 CAN FD 收发器 | D | 8 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TCAN1463-Q1
具有 INH 和 WAKE 引脚的低功耗信号改进 CAN FD 收发器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TCAN1463DMTRQ1
具有 INH 和 WAKE 引脚的低功耗信号改进 CAN FD 收发器 | DMT | 14 | -40 to 150Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TCAN1463DRQ1
具有 INH 和 WAKE 引脚的低功耗信号改进 CAN FD 收发器 | D | 14 | -40 to 150Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
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