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TCAN4550

ZHCSJ74A –DECEMBER 2018–REVISED JANUARY 2020

带有集成收发器的 TCAN4550 汽车控制区域网灵活数据速率 (CAN FD) 控

制器

1 特性

3 说明

1

•

带有集成 CAN FD 收发器和串行外设接口 (SPI) 的

CAN FD 控制器

TCAN4550 是带有集成 CAN FD 收发器的 CAN FD 控

制器，支持高达 8Mbps 的数据速率。此 CAN FD 控制

器符合 ISO11898-1:2015 高速控制器局域网 (CAN) 数

据链路层的规范，并满足 ISO11898–2:2016 高速

CAN 规范的物理层要求。TCAN4550 通过串行外设接

口 (SPI) 在 CAN 总线和系统处理器之间提供了一个接

口，同时支持经典 CAN 和 CAN FD，并为不支持

CAN FD 的处理器实现端口扩展或 CAN 支持。

TCAN4550 提供 CAN FD 收发器功能：传输到总线的

差分传输能力和从总线接收的差分接收能力。该器件

支持通过本地唤醒 (LWU) 进行唤醒以及使用实现

ISO11898-2:2016 唤醒模式 (WUP) 的 CAN 总线进行

总线唤醒。

•

CAN FD 控制器支持 ISO 11898-1:2015 和 Bosch

M_CAN 修订版 3.2.1.1

•

符合 ISO 11898-2:2016 的要求

CAN FD 数据速率高达 5Mbps，且 SPI 时钟速率

高达 18MHz

•

向后兼容经典 CAN

工作模式：正常、待机、睡眠和失效防护

为微处理器提供 3.3V 至 5V 输入/输出逻辑支持

在 CAN 总线上具有宽工作范围

–

±42V 总线故障保护

±12V 共模电压

•

优化了未上电时的性能

该器件包含众多可实现器件和 CAN 总线可靠性的保

护特性。这些特性包括失效防护、内部显性状态超

时、宽总线工作范围以及超时看门狗等等。

–

总线和逻辑终端处于高阻态

（运行总线或应用上无负载）

–

加电和断电无干扰运行

器件信息⁽¹⁾

2 应用

器件型号

TCAN4550

封装

VQFN (20)

封装尺寸（标称值）

•

楼宇自动化

4.50mm x 3.50mm

工厂自动化和控制

工业运输

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

简化原理图，CLKIN 来自 MCU

简化原理图，晶振

3

kꢀ

3 kꢀ

10 µF

10 nF

33 kꢀ

V_BAT

330 nF

10 µF

330 nF

10 µF

100 nF

EN

V_IN

V_SUP

V_CCOUT

WAKE

V_SUP

WAKE

FLTR

V_CCOUT

Voltage

Regulator

(e.g.

Voltage

Regulator

(e.g.

INH

V_INT

V_LVRX

V_IO

V_INT

V_LVRX

V_IO

TPSxxxx)

LDO(s)

Filter

V_OUT

Filter

Under

Voltage

Under

Voltage

CNTL

POR

CNTL

POR

V_IO

TCAN4550

100 nF

10 µF

CANH

V_CCINT1

TXD_INT

V_CCINT2

V_LVRXfor LP

RX

V_INT

V_LVRXfor LP

RX

V_INT

V_CC

nWKRQ

TX/RX Data

Buffer

TX/RX Data

Buffer

GPIO3

V_CC

TX/RX CAN-FD

Controller with

Filters

TX/RX CAN-FD

Controller with

Filters

V_IO

2-wire

CAN

bus

V_IO

2-wire

CAN

bus

RST

SCLK

SDI

RST

SCLK

SDI

Reset

SCLK

RXD_INT

CAN-FD

Transceiver

Reset

SCLK

RXD_INT

CAN-FD

Transceiver

SPI slave,

System

Controller

SPI slave,

System

Controller

MOSI

MISO

MOSI

MISO

SDO

MCU

SDO

MCU

CANL

nCS

CANL

nCS

GPIO2

GPIO1

GPIO

nCS

GPIO2

GPIO1

GPIO

GPO2

nINT

GPIO1

GPO2

nINT

GPIO1

Optional:

Terminating

Node

Optional:

Terminating

Node

Optional:

Filtering,

Optional:

Filtering,

Transient and

ESD

GND

OSC1

OSC2

20 MHz

Transient and

ESD

OSC1

OSC2

OSC1

OSC2

40 MHz

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLLSF91

TCAN4550

ZHCSJ74A –DECEMBER 2018–REVISED JANUARY 2020

www.ti.com.cn

8.2 Functional Block Diagram ....................................... 21

8.3 Feature Description................................................. 24

8.4 Device Functional Modes........................................ 27

8.5 Programming .......................................................... 41

8.6 Register Maps......................................................... 44

Application and Implementation ...................... 127

9.1 Application Design Consideration ......................... 127

9.2 Typical Application ............................................... 131

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

9

10 Power Supply Recommendations ................... 134

11 Layout................................................................. 135

11.1 Layout Guidelines ............................................... 135

11.2 Layout Example .................................................. 136

12 器件和文档支持 ................................................... 137

12.1 文档支持 ............................................................. 137

12.2 接收文档更新通知 ............................................... 137

12.3 支持资源.............................................................. 137

12.4 商标..................................................................... 137

12.5 静电放电警告....................................................... 137

12.6 Glossary.............................................................. 138

13 机械、封装和可订购信息..................................... 138

6.3 ESD Ratings, IEC ESD and ISO Transient

Specification............................................................... 4

6.4 Recommended Operating Conditions....................... 5

6.5 Thermal Information.................................................. 5

6.6 Supply Characteristics .............................................. 5

6.7 Electrical Characteristics........................................... 6

6.8 Timing Requirements................................................ 9

6.9 Switching Characteristics.......................................... 9

6.10 Typical Characteristics.......................................... 11

Parameter Measurement Information ................ 11

Detailed Description ............................................ 20

8.1 Overview ................................................................. 20

7

8

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (December 2018) to Revision A

Page

•

Changed description of the GPO1 pin From: Configurable input/output function... To: Configurable output function........... 3

Deleted V_CCOUTSupply Current from the Absolute Maximum Ratings................................................................................... 4

Changed footnote Gauranteed to Specied throughout the electric table. .............................................................................. 6

Changed V_IOvalue I_ILfor SDI, SCK and nCS inputs in test conditions cell from 0 V to 5.25 V............................................. 8

Changed MIN value of V_OHfor nWKRQ from 3 V to 2.8 V..................................................................................................... 8

Added V_IOvalues for t_SOV...................................................................................................................................................... 10

已更改 Power Up Timing diagram VSUP ramp voltage level for INH turn on and timing. .................................................. 16

已删除 CLKOUT from the GPIO1 circuit in 图 20................................................................................................................. 23

已删除 CLKOUT information from the GPO1 Pin section .................................................................................................... 26

已删除 CLKOUT from the GPIO1 pin in 图 28 ..................................................................................................................... 33

已删除 CLKOUT from the GPIO1 pin in 图 29 ..................................................................................................................... 33

已删除 CLKOUT: Off from Sleep Mode section in 图 32...................................................................................................... 34

已删除 CLKOUT: Off From Sleep Mode section in 图 33..................................................................................................... 35

Deleted GPO1_CONFIG from bits 15 and 14 in Figure 41.................................................................................................. 50

Deleted bits 15 and 14 from GPO1_CONFIG from in Table 15........................................................................................... 51

Changed CLKOUT_GPIO1_CONFIG To: GPIO1_CONFIG for GPO1_CONFIG in Table 15............................................. 51

Changed the name of offset 1048 From: TDCE To: TDCR ................................................................................................ 63

已添加 INH Brownout Behavior section in Application section. ......................................................................................... 130

2

TCAN4550

www.ti.com.cn

ZHCSJ74A –DECEMBER 2018–REVISED JANUARY 2020

5 Pin Configuration and Functions

RGY Package

20 Pin (VQFN)

Top View

nWKRQ

GPIO1

SCLK

SDI

2

3

4

5

6

7

8

9

19

18

17

16

15

14

13

12

RST

FLTR

V

IO

Thermal

Pad

V

CCOUT

SDO

INH

nCS

V

SUP

nINT

GND

GPO2

WAKE

Not to scale

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NO.

1

NAME

OSC1

nWKRQ

GPO1

SCLK

SDI

I

External crystal oscillator or clock input

Wake request (active low)

2

DO

DI

3

Configurable output function pin through SPI

SPI clock input

4

5

DI

SPI slave data input from master output

SPI slave data output to master input

SPI chip select

6

SDO

DO

DI

7

nCS

8

nINT

DO

Interrupt pin to MCU (active low)

Configurable output function pin through SPI

9

GPO2

CANL

CANH

WAKE

GND

10

11

12

13

HV Bus I/O Low level CAN bus line

HV Bus I/O High level CAN bus line

HVI

Wake input, high voltage input

Ground connection

GND

HV Supply

In

14

V_SUP

Supply from battery

15

16

17

18

19

20

INH

HVO

Inhibit to control system voltage regulators and supplies (open drain)

V_CCOUT

V_IO

Supply Out 5 V regulated output

Supply In

Digital I/O voltage supply

FLTR

RST

—

DI

O

Internal regulator filter, requires external capacitor to ground

Device reset

OSC2

External crystal oscillator output; when using single input clock to OSC1 this pin should be connected to ground

(1) Note: DI = Digital Input; DO = Digital Output; HV = High Voltage; Thermal PAD and GND Pins must be soldered to GND

3

TCAN4550

ZHCSJ74A –DECEMBER 2018–REVISED JANUARY 2020

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range for – 40 ℃ ≤ T_A≤ 125 ℃ (unless otherwise noted)⁽¹⁾

MIN

MAX

42

6

UNIT

V

V_SUP

Supply voltage

–0.3

–42

V_IO

Supply voltage I/O level shifter

5 V output supply

V

V_CCOUT

V_BUS

V_WAKE

V_INH

V_{Logic_Input}

V_SO

6

V

CAN bus I/O voltage (CANH, CANL)

WAKE pin input voltage

42

6

V

–0.3

–0.5

V

Inhibit pin output voltage

Logic input terminal voltage

Digital output terminal voltage

Digital output current

V

6

V

I_O(SO)

I_O(INH)

I_O(WAKE)

T_J

8

mA

°C

Inhibit output current

4

Wake current if due to ground shift V_(WAKE)≤ V_(GND) – 0.3 V

Junction temperature

3

–40

–65

150

T_stg

Storage temperature

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT

Human body model (HBM) classification level 3A per AEC Q100-002 All

V_(ESD)

Electrostatic discharge

terminal except for CANH and CANL. WAKE terminals which are with

respect to ground only

±4000

±12000

±750

V

(1)

Human body model (HBM) classification level H2 for CANH and

(1)

CANL

Charged device model (CDM)

classification level C5, per AEC

Q100-011

All terminals

(1) Terminals stressed with respect to GND

6.3 ESD Ratings, IEC ESD and ISO Transient Specification

VALUE

UNIT

V

Contact discharge

Air discharge

Contact discharge

Air discharge

Pulse 1

±8000

±15 000

±8000

±15 000

-100

Electrostatic discharge according to IBEE CAN

EMC

V_(ESD)

(1)

V

Electrostatic discharge according to SAEJ2962-

V_(ESD)

(2)

2

V

Pulse 2

75

ISO7637 Transients according to IBEE CAN EMC test spec

CAN bus terminals (CANH and CANL), V_SUPand WAKE

(3)

Pulse 3a

-150

Pulse 3b

100

(1) IEC 61000-4-2 is a system-level ESD test. Results given here are specific to the IBEE LIN EMC Test specification conditions per IEC TS

62228. Different system-level configurations may lead to different results

(2) SAEJ2962-2 Testing performed at 3^rdparty US3 approved EMC test facility, test report available upon request.

(3) ISO7637 is a system-level transient test. Results given here are specific to the IBEE CAN EMC Test specification conditions. Different

system-level configurations may lead to different results.

4

TCAN4550

www.ti.com.cn

ZHCSJ74A –DECEMBER 2018–REVISED JANUARY 2020

6.4 Recommended Operating Conditions

over operating free-air temperature range for – 40 ℃ ≤ T_A≤ 125 ℃ (unless otherwise noted)

MIN

TYP

MAX

24

UNIT

V

V_SUP

Supply voltage

6

3.135

–2

V_IO

Logic pin supply voltage

5.25

V

I_OH(DO)

I_OL(DO)

I_{O (INH)}

C_(FLTR)

C_(VCCOUT)

C_WAKE

T_SDR

Digital terminal high-level output current

Digital terminal low-level output current

INH output current

mA

nF

µF

nF

℃

2

1

Filter pin capacitance See Power Supply Recommendations

V_CCOUTsupply capacitance See Power Supply Recommendations

External WAKE pin capacitance

Thermal shutdown rising

300

10

160

T_SDF

Thermal shutdown falling

150

℃

T_SD(HYS)

Thermal shutdown hysteresis

10

℃

6.5 Thermal Information

TCAN4550

THERMAL METRIC⁽¹⁾

PKG DES (RGY)

UNIT

20 PINS

35.2

28.1

12.8

0.3

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

Ψ_JB

12.7

1.1

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.6 Supply Characteristics

over operating free-air temperature range for – 40 ℃ ≤ T_A≤ 125 ℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

See 图 5 R_L= 60 Ω, C_L

=

open. typical bus load. V_CCOUT

= no load

80 mA

Dominant

See 图 5 R_L= 50 Ω, C_L

=

open, high bus load. V_CCOUT

no load

=

90 mA

180 mA

15 mA

Supply current, normal mode

See 图 5 CANH = - 25 V, R_L

open, C_L= open V_CCOUT= no

load

Dominant with bus fault

Recessive

See 图 5 R_L= 60 Ω, C_L

=

I_SUP

open, R_CM= open, V_CCOUT

no load

=

See 图 5 R_L= 60 Ω, C_L

=

open, -40°C < T_A< 85°C,

V_CCOUT= no load, CANH/L

terminated to 2.5 V

3.5 mA

3.4 mA

Supply current, standby mode

Supply current, sleep mode

See 图 5 RL = 60 Ω, C_L

=

open, -40°C < T_A< 85°C,

V_CCOUT= no load CANH/L

terminated to GND ± 100 mV

SPI bus, OSC/CLKIN disabled:

-40°C < T_A< 85°C, V_IO= 0

I_SUP

25

42

µA

5

TCAN4550

ZHCSJ74A –DECEMBER 2018–REVISED JANUARY 2020

www.ti.com.cn

Supply Characteristics (continued)

over operating free-air temperature range for – 40 ℃ ≤ T_A≤ 125 ℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

CLKIN = 40 MHz, V_IO= 5 V

Crystal = 40 MHz, V_IO= 5 V

Sleep Mode V_IO= 5 V; OSC1 =

MIN

TYP MAX UNIT

800

3

µA

I/O supply current normal

I_VIO

I/O supply current

mode dominant

mA

I_VIO

I/O supply current, sleep mode I/O supply current

V_CCOUTsupply current

CLKIN = 0 V and OSC2 = GND

9

µA

(1)

Normal Mode: V_CCOUT= 5 V;

-40°C < T_A< 85°C See

Section V_CCOUTPin

I_VCCOUT

70 mA

Under voltage detection on V_SUPrising ramp for protected

mode

5.5

4.7

5.9

2.6

V

See Section Under Voltage

Lockout (UVLO) and

Unpowered Device

UV_SUP

Under voltage detection on V_SUPfalling ramp for protected

mode

4.5

Under voltage detection on V_IOrising ramp for protected

mode

2.45

2.25

See Section Under Voltage

Lockout (UVLO) and

Unpowered Device

UV_IO

Under voltage detection on V_IOfalling ramp for protected

mode

2.1

Upon a UV_IOevent this timer

starts and provides time for V_IO

input to return. See section

Thermal Shutdown for

description of thermal shut

down.

(2)

t_UV/TSD

Under voltage filter time and thermal shutdown timer

200

500

ms

(1) When a crystal is used this current will be higher until the crystal's capacitors bleed off their energy. How much current and length of

time to bleed of the energy is system dependent and will not be specified.

(2) Specified by design

6.7 Electrical Characteristics

over operating free-air temperature range for – 40 ℃ ≤ T_A≤ 125 ℃ (unless otherwise noted)

(1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

CAN DRIVER ELECTRICAL CHARACTERISTICS

Bus output voltage (dominant) CANH

See 图 5 and 图 6, TXD_INT = 0 V, EN

= 0 V, 50 Ω ≤ R_L≤ 65 Ω, C_L= open,

R_CM= open

2.75

0.5

4.5

V

V_O(D)

Bus output voltage (dominant) CANL

2.25

See 图 3 and 图 6, TXD_INT = V_IO, R_L

open (no load), R_CM= open

=

V_O(R)

Bus output voltage (recessive)

2

–5.0

–0.1

2.5

3

10

V

V_(DIFF)

Maximum differential voltage rating

See 图 3 and 图 6

Bus output voltage (Standby Mode)

CANH

0.1

Bus output voltage (Standby Mode)

CANL

See 图 3 and 图 6, TXD_INT = V_IO, R_L

open (no load), R_CM= open

=

V_O(STB)

–0.1

–0.2

1.5

0.1

0.2

3

V

Bus output voltage (Standby Mode)

CANH - CANL

See 图 3 and 图 6, TXD_INT = 0 V, 50 Ω

≤ R_L≤ 65 Ω, C_L= open, R_CM= open

V

See 图 3 and 图 6, TXD_INT = 0 V, 45 Ω

≤ R_L≤ 70 Ω, C_L= open, R_CM= open

V_OD(D)

Differential output voltage (dominant)

Differential output voltage (recessive)

1.4

3

V

See 图 3 and 图 6, TXD_INT = 0 V, R_L

2.24 kΩ, C_L= open, R_CM= open

=

1.5

5

V

See 图 3 and 图 6, TXD_INT = V_IO, R_L

60 Ω, C_L= open, R_CM= open

–120

–50

12

50

mV

V_OD(R)

See 图 3 and 图 6, TXD_INT = V_IO, R_L

open (no load), C_L= open, R_CM= open

(1) All TXD_INT, RXD_INT and EN_INT references are for internal nodes that represent the same functions for a physical layer transceiver.

6

TCAN4550

www.ti.com.cn

ZHCSJ74A –DECEMBER 2018–REVISED JANUARY 2020

Electrical Characteristics (continued)

over operating free-air temperature range for – 40 ℃ ≤ T_A≤ 125 ℃ (unless otherwise noted)

(1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Output symmetry (dominant or

recessive)

( VO(CANH) + VO(CANL)) / VCC

See 图 3 and 图 6, R_L= 60 Ω, C_L

open, R_CM= open, C1 = 4.7 nF,

TXD_INT - 250 kHZ, 1 MHz

=

V_SYM

0.9

1.1

V/V

Output symmetry (dominant or

recessive) (VCC – VO(CANH) –

VO(CANL)) with a frequency that

corresponds to the highest bit rate for

which the HS-PMA implementation is

intended, however, at most 1 MHz (2

Mbit/s)

See 图 3 and 图 6, R_L= 60 Ω, C_L

open, R_CM= open, C1 = 4.7 nF

=

V_{SYM_DC}

–300

–100

–5

300

mV

See 图 3 and 图 10, -3.0 V ≤ V_CANH

18.0 V, CANL = open, TXD_INT = 0 V

≤

mA

Short-circuit steady-state output current,

dominant

IOS_DOM

IOS_REC

See 图 3 and 图 10, -3.0 V ≤ V_CANL

≤+18.0 V, CANH = open, TXD_INT = 0 V

100

5

Short-circuit steady-state output current, See 图 3 and 图 10, – 27 V ≤ V_BUS≤ 32

recessive

V_,V_BUS= CANH = CANL

CAN RECEIVER ELECTRICAL CHARACTERISTICS

Receiver dominant state differential input

V_ITdom

0.9

8

V

-12.0 V ≤ V_CANL≤ +12.0 V

-12.0 V ≤ V_CANH≤ +12.0 V See 图 7, 表

3

voltage range, bus biasing active

Receiver recessive state differential input

V_ITrec

–3.0

0.5

voltage range bus biasing active

Hysteresis voltage for input-threshold,

normal modes

V_HYS

See 图 7, 表 3

120

mV

-12.0 V ≤ V_CANL≤ +12.0 V

Receiver dominant state differential input

V_IT(ENdom)

voltage range, bus biasing inactive

(VDiff)

1.15

–3

8

V

-12.0 V ≤ V_CANH≤ +12.0 V See 图 7, 表

3

-12.0 V ≤ V_CANL≤ +12.0 V

-12.0 V ≤ V_CANH≤ +12.0 V See 图 7, 表

3

Receiver recessive state differential input

voltage range, bus biasing inactive

(VDiff)

V_IT(ENrec)

0.4

V_CM

Common mode range: normal

See 图 7, 表 3

–12

12

V

V_CM(EN)

Common mode range: standby mode

Power-off (unpowered) bus input

leakage current

V_CANH= V_CANL= 5 V, V_supto GND via 0

Ω and 47 kΩ resistor

I_IOFF(LKG)

5

µA

Input capacitance to ground (CANH or

CANL)

C_I

25

14

pF

C_ID

Differential input capacitance

TXD_INT = V_CCINT, normal mode: -2.0 V

R_ID

Differential input resistance

≤ V_CANH≤+7.0 V; -2.0 V ≤V_CANL≤ + 7.0

60

100

kΩ

V

Single ended Input resistance (CANH or -2.0 V ≤ V_CANH≤+7.0 V; -2.0 V ≤V_CANL

≤

R_IN

30

–1

50

1

kΩ

%

CANL)

+ 7.0 V

Input resistance matching: [1 –

(R_IN(CANH) / (R_IN(CANL))] × 100%

R_IN(M)

V_CANH= V_CANL= 5.0 V

I_CCOUT= -70 mA to 0 mA; V_SUP= 6 V to

18 V; -40°C < T_A< 85°C

V_CCOUT

V_DROP

5 V output supply

Drop out voltage

Line regulation

4.75

5

5.25

500

50

V

V_CCOUT= 5 V, V_SUP= 12 V, I_CCOUT= 70

mA

300

mV

V_SUP= 6 V to 24 V, ΔV_CCOUT, I_CCOUT

=

ΔV_CC(ΔVSUP)

10 mA

V_SUP= 14 V, I_CCOUT= 1 mA to 70

mA, ΔV_CCOUT,–40℃ ≤ T_A≤ 125℃

ΔV_CC(ΔVSUPL)Load regulation

60

mV

V

UV_CCOUT

Under voltage threshold on V_CCOUT

4.2

4.55

FLTR TERMINAL

V_MEASURE

C_(FLTR)

Voltage measured at FLTR pin

Filter pin capacitor

1.5

V

External filter capacitor

300

330

nF

7

TCAN4550

ZHCSJ74A –DECEMBER 2018–REVISED JANUARY 2020

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MAX UNIT

Electrical Characteristics (continued)

over operating free-air temperature range for – 40 ℃ ≤ T_A≤ 125 ℃ (unless otherwise noted)

(1)

PARAMETER

TEST CONDITIONS

MIN

TYP

INH OUTPUT TERMINAL (HIGH VOLTAGE OUTPUT)

High-level voltage drop INH with respect

to V_SUP

ΔV_H

I_INH= - 0.5 mA

0.5

1

V

I_LKG(INH)

Leakage current

INH = 0 V, Sleep Mode

–0.5

V_SUP–2

–25

0.7

µA

WAKE INPUT TERMINAL (HIGH VOLTAGE INPUT)

V_IH

V_IL

I_IH

High-level input voltage

Low-level input voltage

High-level input current

Low-level input current

Standby mode, WAKE pin enabled

WAKE = V_SUP–1 V

V

V_SUP–3

25

–15

15

µA

I_IL

WAKE = 1 V

Wake up filter time from a wake edge on

WAKE; standby, sleep mode

t_WAKE

WAKE filter time

50

µs

SDI, SCK, GPIO1 INPUT TERMINALS

V_IH

V_IL

I_IH

High-level input voltage

Low-level input voltage

0.7

V_IO

µA

pF

0.3

1

High-level input leakage current

Low-level input leakage current

Input capacitance

Inputs = V_IO= 5.25 V

Inputs = 0 V, V_IO= 5.25 V

18 MHz

–1

I_IL

–100

–5

12

C_IN

10

Unpowered leakage current (SDI and

SCK only)

I_LKG(OFF)

Inputs = 5.25 V, V_IO= V_SUP= 0 V

–1

1

µA

nCS INPUT TERMINAL

V_IH

High-level input voltage

0.7

V_IO

µA

V_IL

Low-level input voltage

0.3

1

I_IH

High-level input leakage current

Low-level input leakage current

Unpowered leakage current

nCS = V_IO= 5.25 V

–1

–50

–1

I_IL

nCS = V_IO= 5.25 V

–5

1

I_LKG(OFF)

nCS = 5.25 V, V_IO= V_SUP= 0 V

RST INPUT TERMINAL

V_IH

High-level input voltage

0.7

V_IO

µA

µs

V_IL

Low-level input voltage

0.3

10

1

I_IH

High-level input leakage current

Low-level input leakage current

Unpowered leakage current

RST = V_IO= 5.25 V

RST = 0 V

1

–1

I_IL

I_LKG(OFF)

RST = V_IO, V_SUP= 0 V

–7.5

30

7.5

t_{PULSE_WIDTH}Width of the input pulse

SDO, GPIO1, GPO2 OUTPUT TERMINAL; nINT (OPEN DRAIIN) and nWKRQ (WHEN PROGRAMMED TO WORK OFF OF VIO AND IS

OPEN DRAIN)

V_OH

V_OL

High-level output voltage

Low-level output voltage

0.8

V_IO

0.2

nWKRQ OUTPUT TERMINAL (DEFAULT INTERNAL VOLTAGE RAIL)

Default value when based upon internal

voltage rail

V_OH

V_OL

High-level output voltage

Low-level output voltage

2.8

3.6

0.7

V

Default value when based upon internal

voltage rail

OSC1 TERMINAL AND CRYSTAL SPECIFICATION

V_IH

V_IL

High-level input voltage

Low-level input voltage

0.85

–0.5

1.10

0.3

V_IO

Clock-In frequency tolerance , see

section Crystal and Clock Input

Requirements

F_OSC1

20 MHz

0.5

%

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TCAN4550

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ZHCSJ74A –DECEMBER 2018–REVISED JANUARY 2020

Electrical Characteristics (continued)

over operating free-air temperature range for – 40 ℃ ≤ T_A≤ 125 ℃ (unless otherwise noted)

(1)

PARAMETER

TEST CONDITIONS

MIN

–0.5

45

TYP

MAX UNIT

Clock-In frequency tolerance, see

section Crystal and Clock Input

Requirements

F_OSC1

40 MHz

0.5

%

t_DC

Input duty cycle

55

60

%

(2)

ESR

Crystal ESR for load capacitance

Ω

(2) Specified by design

6.8 Timing Requirements

over operating free-air temperature range for – 40 ℃ ≤ T_A≤ 125 ℃ (unless otherwise noted)

MIN

TYP

MAX UNIT

MODE CHANGE TIMES (FULL DEVICE)

Standby to normal mode change time based upon SPI

write

t_{MODE_STBY_NOM}

70

200

µs

SPI write to go to Sleep from Normal: INH and nWKRQ

turned off, See 图 17

t_{MODE_NOM_SLP}

WUP or LWU event until INH and nWKRQ asserted, See

图 16

t_{MODE_SLP_STBY}

t_{MODE_SLP_STBY_VCCOUT_ON}

t_{MODE_NOM_STBY}

WUP or LWU event until V_CCOUTon, See 图 16

1.5

ms

µs

SPI write to go to standby from normal mode, See 图 18

200

6.9 Switching Characteristics

over operating free-air temperature range for – 40 ℃ ≤ T_A≤ 125 ℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SWITCHING CHARACTERISTICS (CAN TRANSCEIVER ONLY)

Propagation delay time, high TXD_INT to

Driver Recessive

t_pHR

50

35

85

75

110

100

ns

(1)

Propagation delay time, low TXD_INT to

See 图 6, RST = 0 V. Typical conditions:

R_L= 60 Ω, C_L= 100 pF, R_CM= open

t_pLD

(1)

driver dominant

t_sk(p)

t_R/F

Pulse skew (|t_pHR– t_pLD|)

30

55

40

75

ns

Differential output signal rise time:

8

Propagation delay time, bus recessive

input to high RXD_INT output

t_pRH

t_pDL

35

55

90

ns

See 图 7, typical conditions: CANL = 1.5

V, CANH = 3.5 V.

Propagation delay time, bus dominant

input to RXD_INT low output

35

DEVICE SWITCHING CHARACTERISTICS

See 图 8, RST = 0 V. typical conditions:

R_L= 60 Ω, C_L= 100 pF, C_RXD= 15 pF

t_LOOP

Loop delay⁽²⁾(CAN transceiver only)

235

1.8

ns

µs

Bus time to meet filtered bus

requirements for wake up request

t_{WK_FILTER}

See 图 24, standby mode.

0.5

0.8

Bus wake-up timeout: time that a WUP

t_{WK_TIMEOUT}

must take place within to be considered See 图 24

2.9

1.2

ms

s

valid

Timer is reset and restarted when bus

changes from dominant to recessive or

vice versa.

(3)

t_SILENCE

Timeout for bus inactivity

0.6

(1) All TXD_INT, RXD_INT, EN_INT and CAN transceiver only references are for internal nodes that represent the same functions for a

stand-alone transceiver.

(2) Time span from signal edge on TXD_INT input to next signal edge with same polarity on RXD output, the maximum of delay of both

signal edges is to be considered.

(3) Specified by design

9

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ZHCSJ74A –DECEMBER 2018–REVISED JANUARY 2020

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MAX UNIT

Switching Characteristics (continued)

over operating free-air temperature range for – 40 ℃ ≤ T_A≤ 125 ℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

Time required for the processor to clear

wake flag or put the device into normal

mode upon power up, power on reset or

after wake event otherwise the device

t_INACTIVE

2

4

6

min

(3)

will enter sleep mode

Time from the start of a dominant-

recessive-dominant sequence

Each phase 6 µs until V_sym≥ 0.1. See

图 12

t_Bias

250

5

µs

(3)

t_{Power_Up}

t_{TXD_INT_DTO}

Power up time on V_SUP

See 图 15

Dominant time out⁽⁴⁾(CAN transceiver

See 图 25, R_L= 60 Ω, C_L= open

1

ms

only)⁽¹⁾

TRANSMITTER AND RECEIVER SWITCHING CHARACTERISTICS

Transmitted recessive bit width @ 2

t_Bit(Bus)2M

435

155

80

530

210

135

ns

Mbps

See 图 7, RST = 0 V typical conditions:

R_L= 60 Ω, C_L= 100 pF, C_RXD= 15 pF

Transmitted recessive bit width @ 5

Mbps

t_Bit(Bus)5M

Transmitted recessive bit width @ 8

Mbps

See 图 7, RST = 0 V typical conditions:

R_L= 60 Ω, C_L= 100 pF, C_RXD= 15 pF

(5)

t_Bit(Bus)8M

t_Bit(RXD)2M

t_Bit(RXD)5M

Received recessive bit width @ 2 Mbps

Received recessive bit width @ 5 Mbps

400

120

550

220

ns

See 图 7, RST = 0 V typical conditions:

R_L= 60 Ω, C_L= 100 pF, C_RXD= 15 pF,

See 图 7, RST = 0 V typical conditions:

R_L= 60 Ω, C_L= 100 pF, C_RXD= 15 pF

(5)

t_Bit(RXD)8M

Received recessive bit width @ 8 Mbps

80

135

ns

Receiver Timing symmetry @ 2 Mbps

Receiver Timing symmetry @ 5 Mbps

–65

–45

30

5

40

15

ns

See 图 7, RST = 0 V typical conditions:

R_L= 60 Ω, C_L= 100 pF, C_RXD= 15 pF

(6)

Δt_Rec

SPI SWITCHING CHARACTERISTICS

(3)

f_SCK

t_SCK

t_RSCK

t_FSCK

t_SCKH

t_SCKL

t_CSS

t_CSH

t_CSD

t_SISU

t_SIH

SCK, SPI clock frequency

18

MHz

ns

(3)

SCK, SPI clock period

See 图 14

56

(3)

SCK rise time

See 图 13

10

(3)

SCK fall time

See 图 13

(3)

SCK, SPI clock high

See 图 14

18

28

125

5

(3)

SCK, SPI clock low

See 图 14

(3)

Chip select setup time

See 图 13

(3)

Chip select hold time

See 图 13

(3)

Chip select disable time

See 图 13

(3)

Data in setup time

See 图 13

(3)

Data in hold time

See 图 13

10

(3)

t_SOV

t_RSO

t_FSO

Data out valid

V_IO= 3.135 V to 5.25 V, See 图 14

See 图 14

20

10

(3)

SO rise time

(3)

SO fall time

See 图 14

(4) The TXD_INT dominant time out (t_{TXD_INT_DTO}) disables the driver of the transceiver once the TXD_INT has been dominant longer than

t_{TXD_INT_DTO}, which releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only

transmit dominant again after TXD_INT has been returned HIGH (recessive). While this protects the bus from local faults, locking the

bus dominant, it limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on

TXD_INT) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the

t_{TXD_INT_DTO}minimum, limits the minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11/ t_{TXD_INT_DTO}

=

11 bits / 1.2 ms = 9.2 kbps.

(5) Characterized but not 100% tested

(6) Δt_Rec= t_Bit(RXD)– t_Bit(Bus)

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TCAN4550

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6.10 Typical Characteristics

38

36

34

32

30

28

26

24

22

20

105

100

95

90

85

80

75

70

65

60

55

50

45

40

35

-40 °C

25 °C

55 °C

85 °C

100 °C

125 °C

-40 °C

25 °C

55 °C

85 °C

100 °C

125 °C

6

8

10

12

14

16

18

20

22

24

D001

6

8

10

12

14

16

18

20

22

24

D003

V_SUP(V)

V_CCOUT= 0 V

I_CCOUT= 0 mA

CAN Bus Load = 60 Ω

V_CCOUT= 5 V

I_CCOUT= 70 mA

CAN Transceiver Off

图 1. I_SUPvs V_SUPSleep Mode

图 2. I_SUPCurrent Across Temperature and V_SUPLDO Output

Only.

7 Parameter Measurement Information

注

All TXD_INT, RXD_INT and EN_INT references are for internal nodes that represent the

same functions for a physical layer transceiver. In test mode these can be brought out to

pins to test the transceiver or CAN FD controller.

Standby Mode (Low

Normal Mode

Power)

CANH

V_diff

CANL

Recessive

Dominant

Recessive

Time, t

图 3. Bus States (Physical Bit Representation)

11

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Parameter Measurement Information (接下页)

CANH

V_CC/2

A

B

RXD_INT

Bias

Unit

CANL

图 4. Simplified Recessive Common Mode Bias Unit and Receiver

注

A: Classic CAN and CAN FD modes

B: Standby and Sleep Modes (Low Power)

CANH

TXD_INT

R_L

C_L

CANL

图 5. Supply Test Circuit

R_CM

CANH

V_CC

50%

TXD_INT

0 V

R_L

C_L

V_OD

V_CM

V_O(CANH)

t_pLD

t_pHR

90%

10%

CANL

R_CM

0.9 V

V_O(CANL)

V_OD

0.5 V

t_R

t_F

图 6. Driver Test Circuit and Measurement

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Parameter Measurement Information (接下页)

CANH

1.5 V

RXD_INT

I_O

0.9 V

V_ID

0.5 V

0 V

V_ID

t_pDL

t_pRH

V_OH

V_O

C_{L_RXD_INT}

CANL

90%

70%

V_{O(RXD_INT)}

30%

10%

V_OL

t_F

t_R

图 7. Receiver Test Circuit and Measurement

R_CM

CANH

V_I

TXD_INT

V_I

t_LOOP

Falling

edge

R_L

C_L

V_CM

70%

TXD_INT

30%

CANL

R_CM

EN_INT

0 V

5 x t_{BIT(TXD_INT)}

t_{BIT(TXD_INT)}

RXD_INT

t_BIT(Bus)

V_O

C_{L_RXD_INT}

900 mV

V_Diff

500 mV

V_OH

70%

RXD_INT

30%

V_OL

t_LOOP

rising

edge

t_{BIT(RXD_INT)}

图 8. Transmitter and Receiver Timing Behavior Test Circuit and Measurement

CANH

V_IH

TXD_INT

30%

TXD_INT

R_L

C_L

V_OD

0 V

V_OD(D)

CANL

0.9 V

V_OD

0.5 V

0 V

t_{TXD_INT_DTO}

图 9. TXD_INT Dominant Timeout Test Circuit and Measurement

13

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Parameter Measurement Information (接下页)

200 ꢀs

I_OS

CANH

TXD_INT

V_BUS

I_OS

CANL

V_BUS

0 V

or

0 V

V_BUS

图 10. Driver Short-Circuit Current Test and Measurement

V_SUP

V_WAKE

V_SUP- 2

V_WAKE

V_SUP- 3

V_SUP

INH

0 V

C_VSUP

t_WAKE

TCAN4550

OR

t_WAKE

V_WAKE

INH = H

INH

V_SUP-1 V

图 11. t_WAKEWhile Monitoring INH Output

V_DIFF

2.0 V

1.15 V

0.4 V

t > t_{WAKE_FILTER(MAX)}

V_SYM

0.1

t_Bias

图 12. Test Signal Definition for Bias Reaction Time Measurement

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Parameter Measurement Information (接下页)

t_CSD

nCS

t_CSH

t_RSCK

t_FSCK

t_CSS

SCLK

t_SISU

t_SIH

SDI

MSB In

LSB

In

SDO

图 13. SPI AC Characteristic Write

nCS

t_SCK

t_SCKL

t_SCKH

SCLK

t_SOV

t_RSO

t_FSO

SDO

LSB

Out

MSB Out

SDI

图 14. SPI AC Characteristic Read

15

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Parameter Measurement Information (接下页)

14 V

~ 5.5 V

UV_SUP

V_SUP

1.67 V to

4.14 V

14 V

V_SUPœ 1V

INH

t_{Power_Up}

nWKRQ

V_IO

V_IOon and ramp time are system dependent and not specified

FLTR

V_CCOUT

t_{MODE_SLP_STBY_VCCOUT_ON}

UV_CCOUTCleared

CLKIN is dependent on external source

and timing will not be specified

t_CRYSTAL

V_IOrequired for Crystal/CLKIN to work.

This is the stable internal clock.

Crystal/CLKIN

STANDBY MODE

Transceiver Ready

nINT

图 15. Power Up Timing

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Parameter Measurement Information (接下页)

14V

V_SUP

Wake Event

WUP or LWU

14V

V_SUPœ 1V

INH

t_{MODE_SLP_STBY}

nWKRQ

V_IO

V_IOon and ramp time are system dependent and not specified

FLTR

V_CCOUT

t_{MODE_SLP_STBY_VCCOUT_ON}

UV_CCOUTCleared

V_IOrequired for Crystal/CLKIN to work.

This is the stable internal clock.

CLKIN is dependent on external source

and timing will not be specified

t_CRYSTAL

Crystal/CLKIN

nINT

STANDBY MODE

Transceiver Ready

图 16. Sleep to Standby Timing

17

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Parameter Measurement Information (接下页)

14V

V_SUP

SPI Mode

Change

Normal to

Sleep CMD

14V

V_SUPœ 1V

INH

t_{MODE_NOM_SLP}

nWKRQ

V_IO

V_IOoff and ramp time are system dependent and not specified

FLTR

EN_VCCOUT_S

t_SILENCEExpires

V_CCOUToff ramp time is system dependent and not specified

V_CCOUT

Crystal/CLKIN

V_IOrequired for Crystal/CLKIN to work.

Mode

NOM:SLP

Sleep Mode

Normal Mode

图 17. Normal to Sleep Timing

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Parameter Measurement Information (接下页)

14 V

V_SUP

SPI Mode

Change

Normal to

Standby CMD

14 V

INH

nWKRQ

Low

High

V_IO

FLTR

5 V

V_CCOUT

Crystal/CLKIN

Mode

NOM:SLP

Standby Mode

Normal Mode

t_{MODE_NOM_STBY}

Transceiver

图 18. Normal to Standby Timing

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8 Detailed Description

8.1 Overview

The TCAN4550 is a CAN FD controller with an integrated CAN FD transceiver supporting data rates up to 5

Mbps. The CAN FD controller meets the specifications of the ISO 11898-1:2015 high speed Controller Area

Network (CAN) data link layer and meets the physical layer requirements of the ISO 11898-2:2016 High Speed

Controller Area Network (CAN) specification providing an interface between the CAN bus and the CAN protocol

controller supporting both classical CAN and CAN FD up to 5 megabits per second (Mbps). The TCAN4550

provides CAN FD transceiver functionality: differential transmit capability to the bus and differential receive

capability from the bus. The device includes many protection features providing device and CAN bus robustness.

The device can also wake up via remote wake up using CAN bus implementing the ISO 11898-2:2016 Wake Up

Pattern (WUP). Input/Output support for 3.3 V and 5 V microprocessors using V_IOpin for seamless interface. The

TCAN4550 has a Serial Peripheral Interface (SPI) that connects to a local microprocessor for the device's

configuration; transmission and reception of CAN frames. The SPI interface supports clock rates up to 18 MHz.

The CAN bus has two logical states during operation: recessive and dominant. See 图 3 and 图 4.

In the recessive bus state, the bus is biased to a common mode of 2.5 V via the high resistance internal input

resistors of the receiver of each node. Recessive is equivalent to logic high. The recessive state is also the idle

state.

In the dominant bus state, the bus is driven differentially by one or more drivers. Current flows through the

termination resistors and generates a differential voltage on the bus. Dominant is equivalent to logic low. A

dominant state overwrites the recessive state.

During arbitration, multiple CAN nodes may transmit a dominant bit at the same time. In this case, the differential

voltage of the bus is greater than the differential voltage of a single driver.

Transceivers with low power Standby Mode have a third bus state where the bus terminals are weakly biased to

ground via the high resistance internal resistors of the receiver. See 图 3 and 图 4. The TCAN4550 supports auto

biasing, see CAN Bus Biasing

The TCAN4550 has the ability to provide a single-ended clock output (GPIO1) based upon the crystal or single-

ended clock input on OSC1. Many of the pins can be configured for multiple purposes and are described in more

detail in Feature Description section. Much of the parametric data is based on internal links like the

TXD/RXD_INT which represent the TXD and RXD of a standalone CAN transceiver. The TCAN4550 has a test

mode that maps these signals to an external pin in order to perform compliance testing on the transceiver

(TXD/RXD_INT_PHY) and CAN core (TXD/RXD_INT_CAN) independently.

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8.2 Functional Block Diagram

V_SUP

V_CCOUT

FLTR

WAKE

INH

V_INT

V_LVRX

LDO(s)

Filter

V_IO

Under

Voltage

CNTL

POR

TCAN4550

V_IO

CANH

V_CCINT1

TXD_INT

RXD_INT

V_CCINT2

V_INT

V_LVRXfor LP

RX

nWKRQ

TX/RX Data

Buffer

TX/RX CAN-FD

Controller with

Filters

V_IO

RST

SCLK

SDI

CAN-FD

Transceiver

SPI slave,

System

Controller

SDO

CANL

nCS

GPO2

nINT

GPIO1

GND

OSC2

OSC1

40 MHz

注

•

OSC1 pin is either a crystal or external clock input

When OSC1 is used as an external clock input pin OSC2 must be connected directly

to ground

•

When using an external clock input on OSC1 the input voltage should be the same as

the V_IOvoltage rail

The recommended crystal or clock rate to meet CAN FD 5 Mbps rates is 40 MHz

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Functional Block Diagram (接下页)

V_CCINT1

Transceiver Block Diagram

V_SUP

TXD_INT_PHY

TXD_INT

CANH

CANL

DOMINANT

TIME OUT

DRIVER

TXD_INT

Communication Bus

OVER

TEMP

EN_INT

MODE AND CONTROL LOGIC

V_SUP

WAKE

INH_CNTL

V_SUP

V_LVRX

UNDER

VOLTAGE

M

U

X

INH

WAKE UP LOGIC /

MONITOR

RXD_INT_PHY

RXD_INT

LOGIC

OUTPUT

Low Power Standby Bus

Receiver & Monitor

RXD_INT

图 19. CAN Transceiver Block Diagram

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Functional Block Diagram (接下页)

V_IO

Chip

Reset

RST

V_IO

SCLK

SDI

V_IO

SDI

V_IO

SDO

nCS

V_IO

GPI

V_IO

RXD_INT_CAN

Test Mode

TXD_INT_PHY

GPI01

GPO

SPI & I/O

Controller

V_IO

Test Mode

TXD_INT_CAN

GPO2

RXD_INT_PHY

GPO2 œ for all non test mode

V_IO

Test Mode

EN_INT

nINT

3P6_SLEEP

WKRQ_3P6_SLEEP

WKRQ_VIO

nWKRQ

图 20. SPI and Digital IO Block Diagram

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8.3 Feature Description

8.3.1 V_SUPPin

This pin connects to the battery supply. It provides the supply to the internal regulators that support the digital

core, CAN transceiver and V_CCOUT. This Pin requires a 100 nF capacitor at the pin. See Power Supply

Recommendations for more information. Upon power up; V_SUPneeds to rise above UV_SUPrising threshold.

8.3.2 V_IOPin

The V_IOpin provides the digital IO voltage to match the microprocessor IO voltage thus avoiding the

requirements for a level shifter. V_IOsupports IO pins SPI IO, GPO1 and GPO2. It also provides power to the

oscillator block supporting the crystal or CLKIN pins. It supports a range of 3.3 V to 5 V ± 5% nominal value

providing the widest range of controller support. This pin requires a 100 nF capacitor at the pin. See Power

Supply Recommendations for more information.

8.3.3 V_CCOUTPin

An internal LDO provides power for the integrated CAN transceiver and the V_CCOUTpin for a total available

current of 125 mA. The amount of current that can be sourced is dependent upon the CAN transceiver

requirements during normal operation. When a bus fault takes place that requires all the current from the LDO,

the device is not able to source current to external components. During sleep mode this regulator is disabled and

no current is provided. Once in the other active modes the regulator is enabled for normal operation. This pin

requires a 10 µF external capacitor as close to the pin as possible. See Power Supply Recommendations for

more information.

8.3.4 GND

This pin is a ground pin as is the thermal pad. Both need to connect to a ground plane to support heat

dissipation.

8.3.5 INH Pin

The INH pin is a high voltage output pin that provides voltage from the V_SUPminus a diode drop to enable an

external high voltage regulator. These regulators are usually used to support the microprocessor and V_IOpin.

The INH function is on in all modes but sleep mode. In sleep mode the INH pin is turned off, going into a high Z

state. This allows the node to be placed into the lowest power state while in sleep mode. If this function is not

required it can be disabled by setting register 16'h0800[9] = 1 using the SPI interface. If not required in the end

application to initiate a system wake-up, INH can be left floating.

注

This terminal should be considered a "high voltage logic" terminal. It is not a power output

thus should be used to drive the EN terminal of the system’s power management device.

It should be not used as a switch for power management supply itself. This terminal is not

reverse battery protected and thus should not be connected outside of the system module.

8.3.6 WAKE Pin

The WAKE pin is used for a high voltage device local wake up (LWU). This function is explained further in Local

Wake Up (LWU) via WAKE Input Terminal section. The pin is defaulted to bi-directional edge trigger, meaning it

recognizes a LWU on either a rising or falling edge of WAKE pin transition. This default value can be changed

via a SPI command that disables the function, make it a rising edge only or a falling edge only. This is done by

using register 16'h0800[31:30]. Pin requires a 10 nF capacitor to ground for improved transient immunity in

applications that route WAKE externally. If local wake-up functionality is not needed in the end application,

WAKE can be tied directly to V_SUPor GND.

8.3.7 FLTR Pin

This pin is used to provide filtering for the internal digital core regulator. Pin requires 300 nF of capacitance to

ground. See Power Supply Recommendations for more information.

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Feature Description (接下页)

8.3.8 RST Pin

The RST pin is a device reset pin. It has a weak internal pull down resistor for normal operation. If

communication has stopped with the TCAN4550, the RST pin can be pulsed high and then back low for greater

than t_{PULSE_WIDTH}to perform a power on reset to the device. This resets the device to the default settings and

puts the device into standby mode. If the device was in normal or standby mode the INH and nWKRQ pins

remain active (on) and do not toggle; see 图 21. If the device is in sleep mode and reset is toggled the device

enters standby mode and at that time INH and nWKRQ turns on; see 图 22.

After a RST has taken place, a wait time of ≥ 700 µs should be used before reading or writing to the TCAN4550.

14V

V_SUP

t_{PULSE_WIDTH}

RST

14V

INH

nWKRQ

Low

High

V_IO

≥ 700 µs

Device ready to be

read and written to

Device SPI

Access

Standby Mode

Normal

or

Standby

Mode

图 21. Timing for RST Pin in Normal and Standby Modes

14V

V_SUP

t_{PULSE_WIDTH}

RST

14V

≥ 250 µs

INH

Low

Float

nWKRQ

Low

High

V_IO

≥ 700 µs

Device ready to be

read and written to

Device SPI

Access

Standby Mode

Sleep Mode

图 22. Timing for RST Pin in Sleep Mode

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Feature Description (接下页)

8.3.9 OSC1 and OSC2 Pins

These pins are used for a crystal oscillator. The OSC1 pin can also be used as a single-ended clock input from

the microprocessor or some other clock source. See Application Design Consideration section for further

information on the functions of these pins. It is recommended to provide a 40 MHz crystal or CLKIN to support

CAN FD data rates.

8.3.10 nWKRQ Pin

This pin is a dedicated wake up request pin from a bus wake (WUP) request, local wake (LWU) request and

power on (PWRON). The nWKRQ pin is defaulted to a wake enable based upon a wake event. In this

configuration the output is pulled low and latched to serve as an enable for a regulator that does not use the INH

pin to control voltage level. The nWKRQ pin can be configured by setting 16'h0800[8] = 1 as an interrupt pin that

pulls the output low, but once the wake interrupt flag is cleared it releases the output back to a high. This pin

defaults to an internal 3.6 V rail that is active during sleep mode. In this configuration, if a wake event takes

place, the nWKRQ pin switches from high to low. This output can be configured to be powered from the V_IOrail

through SPI programming, 16'h0800[19]. When powered off of the V_IOpin, the device does not insert an interrupt

until the V_IOrail is stable. When configured for V_IO, this pin is an open drain output and requires an external pull

up resistor to V_IOrail. This configuration bit is saved for all modes of operation and does not reset in sleep mode.

As some external regulators or power management chips may need a digital logic pin for a wake up request, this

pin can be used.

注

•

This pin is active low and is logical OR of CANINT, LWU and WKERR register

16'h0820 that are not masked

If a pull-up resistor is placed on this pin it must be configured for power from the V_IO

rail

8.3.11 nINT Interrupt Pin

The nINT is a dedicated open drain global interrupt output pin. This pin needs an external pull-up resistor to V_IO

to function properly. All interrupt requests are reflected by this pin when pulled low.

In test mode, this pin is used as an EN pin input for testing the CAN transceiver and is shown as EN_INT

throughout the document. When this pin is high, the device is in normal mode and when low it is in standby

mode. This is accomplished by writing 0 to register 16'h0800[0].

注

This pin is an active low and is the logical OR of all faults in registers 16'h0820 and

16'h0824 that are not masked.

8.3.12 GPO1 Pin

This pin defaults out as the M_CAN_INT 1 (active low) interrupt. The functionality of the pin can be changed to a

configurable output function pin by setting register 16'h0800[15:14] = 00. The GPO function is further configured

by using register 16'h0800[11:10]. To configure the pin to support a watchdog input timer reset pin use SPI

register 16'h0800[15:14] = 10.

When in test mode the GPIO1 pin is used to provide the input signal for the transceiver (TXD_INT_PHY) or the

input to the M_CAN core (RXD_INT_CAN). This is accomplished by first putting the device into test mode using

register 16'h0800[21] = 1 and then selecting which part of the device is to be tested by setting register

16'h0800[0]

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Feature Description (接下页)

8.3.13 GPO2 Pin

The GPO2 pin is an open drain configurable output function pin that provides selected interrupts. This pin needs

an external pull-up resistor to V_IOto function properly. The output function can be changed by using register

16'h0800[23:22] and can be configured as a watchdog output reset pin.

In test mode, this pin becomes the RXD_INT_PHY transceiver output or TXD_INT_CAN CAN Controller output

pin.

8.3.14 CANH and CANL Bus Pins

These are the CAN high and CAN low differential bus pins. These pins are connected to the CAN transceiver

and the low voltage WUP CAN receiver. The functionality of these is explained throughout the document. See

section CAN Bus Biasing for can bus biasing.

8.4 Device Functional Modes

The TCAN4550 has several operating modes: normal, standby, and sleep modes and two protected modes. The

first three mode selections are made by the SPI register. The two protected modes are modified standby modes

used to protect the device or bus. The TCAN4550 automatically goes from sleep to standby mode when

receiving a WUP or LWU event. See 表 1 for the various modes and what parts of the device are active during

the each mode.

The TCAN4550 state diagram figure, see 图 23, shows the biasing of the CAN bus in each of the modes of

operation.

表 1. Mode Overview

Low

Power

CAN RX

Memory &

Configuratio

n

WAKE

CAN TX/

RX

Mode

RST Pin

nINT

nWKRQ

INH

GPO2

WD

SPI

GPIO1

OSC

V_CCOUT

Normal

L

On

Off

On

Off

On

Off

On

Saved

Standby

On/

TSD

Protected

L

On

Off

Saved

Mode

Dependen

t

UV_IO

Protected

L

Off

On

Off

On

Off

On

Off

Saved

Sleep

Off

Partial Saved

注

•

In test mode the watchdog (WD) function can be used for Mode 01 CAN FD. The pin

function for WD is used by other pins in this mode but WD_ACTION

reg16'h0800[17:16] = 00 and 01 are available and WD_BIT reg16'h0800[18] is how the

timer would be reset.

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RST Pin: Set high to

reset device. Once

finished set back low

UVLO V_SUP

Continued decrease below UV_SUP

low the device will reset and clear

everything and come back on as if

a power up sequence has taken

place entering standby mode

Resets Sleep

Core

Power On

Start Up

Normal Mode

TSD = 1

Power Off

TSD Protected

Standby Mode

Normal Mode

SPI Write

MO = 01

RST: L

Wake Sources: WAKE

INH: H

Wake Pin: Active

All GPIO: Active

SPI: Active

RST: L

Wake Sources: CAN, WAKE

INH: H

RST: L

INH: H

SPI Write

MO = 10

Wake Pin: Active

All GPIO: Active

SPI: Active

Wake Pin: Active

All GPIO: Active

SPI: Active

SPI Write

MO = 00

Sleep Mode

RST: L

Wake Sources: CAN, WAKE

INH: floating

TSD = 1

OSC: Active

V_CCOUT: Off

Timer Start

OSC: Active

V_CCOUT: Enabled

OSC: Active

V_CCOUT: Enabled

SWE timer

times out

Wake Pin: Active

nINT Pin: Off

nWKRQ Pin: Active

Other GPIO: Off

SPI: Off

TSD = 1 &

Timer Expires

TSD = 0 &

Timer Expires

TSD State

TSD Timer

Wake-up Event:

CAN bus

or

SPI Write

MO = 00

OSC: Off

V_CCOUT: Off

WAKE Pin

UV_IO= 1

NOTE: Upon a wake event the device will

transition into Standby mode and must be

reconfigured using SPI

UV_IOProtected

UV_IO= 0

RST: L

Wake Sources: CAN, WAKE

INH: H

Normal Mode

UV_IO= 1

UV_IOState

UV_IOTimer

UV_IO= 1 &

Timer Expires

Wake Pin: Active

All GPIO: Off

SPI: Off

Note:

ñ

OSC: Off

V_CCOUT: On

Timer Start

UV_IOProtected status will lose the CLKIN/Crystal. During this time the digital core will reset and the M_CAN will have to be

reprogrammed. If timer times out and UV_IO= 1 the device goes to sleep at which time all are cleared.

If a Thermal Shutdown and UV_IOevent take place at the same time the device will enter sleep mode until the faults are rectified

ñ

图 23. Device State Diagram

8.4.1 Normal Mode

This is the normal operating mode of the device. The CAN driver and receiver are fully operational and CAN

communication is bi-directional. The driver translate a digital input on the internal TXD_INT signal from the CAN

FD controller to a differential output on CANH and CANL. The receiver translates the differential signal from

CANH and CANL to a digital output on the internal RXD_INT signal to the CAN FD controller. Normal mode is

enabled or disabled via the SPI interface.

注

If an under voltage event has taken place and cleared, the interrupt flags have to be

cleared before the device can enter normal mode.

8.4.2 Standby Mode

In standby mode, the bus transmitter does not send data nor will the normal mode receiver accept data. There

are several blocks that are active in this mode. The low power CAN receiver is active, monitoring the bus for the

wake up pattern (WUP). The wake pin monitor is active. The SPI interface is active so that the microprocessor

can read and write registers in the memory for status and configuration. The INH pin is active in order to supply

an enable to the V_IOcontroller if this function is used. The nWKRQ pin is low in this mode in the default

configuration and can also be used as a digital enable pin to an external regulator or power management

integrated circuit (PMIC). All other blocks are put into the lowest power state possible. This is the only mode that

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the TCAN4550 automatically switches to without a SPI transaction. The device goes from sleep mode to standby

mode automatically upon a bus WUP event or a local wake up from the wake pin. Upon entry to Standby Mode,

only one wake interrupt is given (either LWU, CANINT). New wake interrupts is not given in standby mode unless

the device changes to normal or sleep mode and then back to standby. This prevents CAN traffic from spamming

the processor with interrupts while in standby, and it gives the processor the first wake interrupt that was issued.

Upon power up, a power on reset or wake event from sleep mode the TCAN4550 enters standby mode. This

starts a four minute timer, t_INACTIVE, that requires the processor to either reset the interrupt flags or configure the

device to normal mode. This feature makes sure the node is in the lowest power mode if the processor does not

come up properly. This automatic mode change also takes place when the device has been put into sleep mode

and receives a wake event, WUP or LWU. To disable this feature for sleep events register 16'h0800[1]

(SWE_DIS) must be set to one. This will not disable the feature when powering up or when a power on reset

takes place.

8.4.3 Sleep Mode

Sleep mode is similar to the standby mode except the SPI interface and INH is disabled. As the low power CAN

receiver is powered off of V_SUPthe implementer can turn off V_IO. The nWKRQ pin is powered off the V_SUPsupply

internal logic level regulator. This allows the TCAN4550 to provide an interrupt to the MCU when a wake event

takes place with out requiring V_IOto be up. When the device goes into sleep mode the power to the registers and

memory is removed to conserve power. This requires the device to be re-configured prior to being put into

normal mode. As the SPI interface is turned off the only ways to exit sleep mode is by a wake up event, RST pin

toggle or power cycle. A sleep mode status flag is provided to determine if the device entered sleep mode

through normal operation or if a fault caused the mode change. Register 16'h0820[23] provides the status. If a

fault causes the device to enter sleep mode, this flag is set to a one.

注

Difference between sleep and standby mode

•

Sleep mode reduces whole node power by shutting off INH/nWKRQ to MCU VREG

and shuts off SPI.

•

Standby mode reduces TCAN4550 power as INH and nWKRQ is enabled turning on

node MCU VREG and SPI interface is active.

注

When entering sleep mode it is possible for the TCAN4550 to assert an interrupt due to

UV_CCOUTevent as the LDO is powering down. This interrupt should be ignored or can be

masked out by using 16'h830[22] before initiating the go to sleep command.

8.4.3.1 Bus Wake via RXD_INT Request (BWRR) in Sleep Mode

As the TCAN4550 supports low power sleep mode and uses a wake up from the CAN bus mechanism called bus

wake via RXD_INT Request (BWRR). Once this pattern is received, the TCAN4550 automatically switches to

standby mode and inserts an interrupt onto the nINT and nWKRQ pins to indicate to a host microprocessor that

the bus is active, and it should wake up and service the TCAN4550. The low power receiver and bus monitor are

enabled in sleep mode to allow for RXD_INT Wake Requests via the CAN bus. A wake up request is output to

the internal RXD_INT (driven low) as shown in 图 25. The wake logic monitors RXD_INT for transitions (high to

low) and reactivate the device to standby mode based on the RXD_INT Wake Request. The CAN bus terminals

are weakly pulled to GND during this mode, see 图 4.

These devices use the wake up pattern (WUP) from ISO 11898-2:2016 to qualify bus traffic into a request to

wake the host microprocessor. The bus wake request is signaled to the integrated CAN FD controller by a falling

edge and low corresponding to a “filtered” bus dominant on the RXD_INT terminal (BWRR).

The wake up pattern (WUP) consists of

•

A filtered dominant bus of at least t_{WK_FILTER}followed by

A filtered recessive bus time of at least t_{WK_FILTER}followed by

A second filtered dominant bus time of at least t_{WK_FILTER}

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Once the WUP is detected, the device starts issuing wake up requests (BWRR) on the RXD_INT signal every

time a filtered dominant time is received from the bus. The first filtered dominant initiates the WUP and the bus

monitor is now waiting on a filtered recessive, other bus traffic does not reset the bus monitor. Once a filtered

recessive is received, the bus monitor is now waiting on a filtered dominant and again, other bus traffic does not

reset the bus monitor. Immediately upon receiving of the second filtered dominant the bus monitor recognizes the

WUP and transition to BWRR output. Immediately upon verification receiving a WUP the device transitions the

bus monitor into BWRR mode, and indicates all filtered dominant bus times on the RXD_INT internal signal by

driving it low for the dominant bus time that is in excess of t_{WK_FILTER}, thus the RXD_INT output during BWRR

matches the classical 8 pin CAN devices that used the single filtered dominant on the bus as the wake up

request mechanism from ISO 11898-2:2016.

For a dominant or recessive to be considered “filtered”, the bus must be in that state for more than t_{WK_FILTER}

time. Due to variability in the t_{WK_FILTER}the following scenarios are applicable.

•

Bus state times less than t_{WK_FILTER(MIN)}are never detected as part of a WUP, and thus no BWRR is

generated.

Bus state times between t_{WK_FILTER(MIN)}and t_{WK_FILTER(MAX)}may be detected as part of a WUP and a BWRR

may be generated.

Bus state times more than t_{WK_FILTER(MAX)}is always detected as part of a WUP, and thus, a BWRR is always

be generated.

See 图 24 for the timing diagram of the WUP.

The pattern and t_{WK_FILTER}time used for the WUP and BWRR prevents noise and bus stuck dominant faults from

causing false wake requests while allowing any CAN or CAN FD message to initiate a BWRR. If the device is

switched to normal mode or an under voltage event occurs on V_CCthe BWRR is lost. The WUP pattern must

take place within the t_{WK_TIMEOUT}time otherwise the device is in a state waiting for the next recessive and then a

valid WUP pattern.

Bus Wake via RXD

Request

Wake Up Pattern (WUP) where t ≤ t_{WK_TIMEOUT}

Filtered

Dominant

Filtered

Dominant

Filtered

Recessive

Waiting for

Filtered

Dominant

Waiting for

Filtered

Recessive

Bus

Bus V_Diff

≥ t_{WK_FILTER}

Filtered Dominant RXD Output

Bus Wake Via RXD Requests

RXD_INT

t_{MODE_SLP_STBY}

INH

nWKRQ

图 24. Wake Up Pattern (WUP) and Bus Wake via RXD_INT Request (BWRR)

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Fault is repaired & transmission capability

restored

TXD fault stuck dominant: example PCB failure or bad software

t_{TXD_DTO}

TXD_INT (driver)

Driver disabled freeing bus for other nodes

Normal CAN communication

Bus would be —stuck dominant“ blocking communication for the whole network but TXD DTO

prevents this and frees the bus for communication after the time t_{TXD_DTO}

.

CAN Bus

Signal

t_{TXD_DTO}

Communication from other

bus node(s)

Communication from repaired

node

RXD_INT

(receiver)

Communication from other

bus node(s)

Communication from repaired

local node

Communication from local

node

图 25. Example timing diagram with TXD_INT DTO

8.4.3.2 Local Wake Up (LWU) via WAKE Input Terminal

The WAKE terminal is a high voltage input terminal which can be used for local wake up (LWU) request via a

voltage transition. The terminal triggers a LWU event on either a low to high or high to low transition as it has bi-

directional input thresholds. This terminal may be used with a switch to V_SUPor ground. If the terminal is not used

it should be pulled to ground or V_SUPto avoid unwanted wake up events.

The LWU circuitry is active in sleep mode and standby mode. If a valid LWU event occurs, the device transitions

to standby mode. The LWU circuitry is not active in normal mode. To minimize system level current consumption,

the internal bias voltages of the terminal follows the state on the terminal. The wake filter time for a valid wake to

avoid glitches on wake pin is provided by filter value of t_WAKE(MIN). A constant high level on WAKE has an internal

pull up to V_SUPand a constant low level on WAKE has an internal pull down to GND. On power up, this may look

like a LWU event and could be flagged as such.

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Wake

Threshold

Not Crossed

t ≤ t_WAKE

No Wake

UP

t ≥ t_WAKE

Wake UP

Wake

Local Wake Request

INH

RXD_INT

*

Mode

Sleep Mode

Standby Mode

图 26. Local Wake Up – Rising Edge

Wake

Threshold

Not Crossed

t ≤ t_WAKE

No Wake

UP

t ≥ t_WAKE

Wake UP

Wake

Local Wake Request

INH

*

RXD_INT

Mode

Sleep Mode

Standby Mode

图 27. Local Wake Up – Falling Edge

注

RXD_INT is an internal signal and can be seen in Transceiver test mode when V_IOis

present.

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8.4.4 Test Mode

The TCAN4550 includes a test mode that has four configurations. Two are enabled by the SPI interface using

the configuration register by setting register bit 16'h0800[21] = 1. In this mode the transceiver TXD_INT_PHY or

CAN core RXD_INT_CAN can be mapped to the GPIO1 pin and RXD_INT_PHY or TXD_INT_CAN can be

mapped to the GPO2 pin. EN_INT pin is mapped to the nINT pin, see 图 28 and 图 29. This is accomplished by

setting register 16'h0800[0] to 0 for transceiver testing or 1 for M_CAN core testing. This mapping is only valid

when in test mode. There are two M_CAN core specific test modes entered using SPI but written to the M_CAN

core registers directly, see 图 30 and 图 31.

EN_INT

nINT

GPIO1

TXD_INT_PHY

V_CCINT2

CANH

CANL

SCLK

SDI

TX

RX

SPI slave,

System

Controller

MCAN

Core

SDO

nCS

RXD_INT_PHY

GPO2

图 28. Transceiver Test Mode

GPIO1

RXD_INT_CAN

V_CCINT2

CANH

CANL

SCLK

SDI

TX

SPI slave,

System

Controller

MCAN

Core

SDO

nCS

RX

TXD_INT_CAN

GPO2

图 29. SPI and M_CAN Core Test Mode

V_CCINT2

CANH

CANL

SCLK

SDI

= 1

TX

RX

SPI slave,

System

Controller

MCAN

Core

SDO

nCS

图 30. M_CAN Internal Loop Back Test Mode

V_CCINT2

CANH

CANL

SCLK

SDI

TX

RX

SPI slave,

System

Controller

MCAN

Core

SDO

nCS

图 31. M_CAN External Loop Back Test Mode

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8.4.5 Failsafe Feature

The TCAN4550 has three methods the failsafe feature is used in order to reduce node power consumption for a

node system issue. Failsafe is the method the device uses to enter sleep mode from various other modes when

specific issues arise. This feature uses the Sleep Wake Error (SWE) timer to determine if the node processor

can communicate to the TCAN4550. The SWE timer is default enabled through the SWE_DIS; 16'h0800[1] = 0

but can be disabled by writing a one to this bit. Even when the timer is disabled, a power on reset re-enables the

timer and thus be active. Failsafe Feature is default disabled but can be enabled by writing a one to

16'h0800[13], FAILSAFE_EN.

Upon power up the SWE timer starts, t_INACTIVE, the processor has typically four minutes to configure the

TCAN4550, clear the PWRON flag or configure the device for normal mode; see 图 32. This feature cannot be

disabled. If the device has not had the PWRON flag cleared or been placed into normal mode, it enters sleep

mode. The device wakes up if the CAN bus provides a WUP or a local wake event takes place, thus entering

standby mode. Once in standby mode t_SILENCEand t_INACTIVEtimers starts. If t_INACTIVEexpires, the device re-enters

sleep mode.

The second failure mechanism that causes the device to use the failsafe feature, if enabled, is when the device

receives a CANINT, CAN bus wake (WUP) or WAKE pin (LWU), while in sleep mode such that the device leaves

sleep mode and enters standby mode. The processor has four minutes to clear the flags and place the device

into normal mode. If this does not happen the device enters sleep mode.

The third failure mechanism that causes the device to use the failsafe feature is when in standby or normal mode

and the CANSLNT flag persists for t_INACTIVE, the device enters sleep mode. Examples of events that could create

this are CLKIN or Crystal stops working, processor is no longer working and not able to exercise the SPI bus, a

go-to-sleep command comes in and the processor is not able to receive it or is not able to respond. See state

diagram 图 33.

Standby Mode

Power On

Start Up

SWE Timer

t_INACTIVE

No &

Cleared

Does timer

Expire and PWRON

flag cleared?

Stays in STBY mode

or switches to Normal

mode if programmed

Timed out

Sleep Mode

RST: L

Wake Sources: CAN, WAKE

INH: floating

Wake Pin: Active

nINT Pin: Off

nWKRQ Pin: Active

Other GPIO: Off

SPI: Off

OSC: Off

V_CCOUT: Off

图 32. Power On Failsafe Feature

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Normal Mode

0800[13] = 1

Fail Safe Mode En

Bus Inactivity

t_SILENCEtimer

expires

Standby Mode

0800[13] = 1

setting CANSLNT

flag

Fail Safe Mode En

Bus Inactivity

SWE Timer

t_INACTIVE

Monitoring CAN

No &

Cleared

Activity detected

leaving device in

current mode or

placing in selected

mode

Does timer

Expire and required

expire?

flags cleared?

Timed out

Sleep Mode

RST: L

Wake Sources: CAN, WAKE

INH: floating

Wake Pin: Active

nINT Pin: Off

nWKRQ Pin: Active

Other GPIO: Off

SPI: Off

OSC: Off

CLKOUT: Off

V_CCOUT: Off

图 33. Normal and Standby Failsafe Feature

8.4.6 Protection Features

The TCAN4550 has several protection features that are described as follows.

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8.4.6.1 Watchdog Function

The TCAN4550 contains a watchdog (WD) timeout function. When using the WD timeout function the WD runs

continuously. The WD is default enabled and can be configured with four different timer values. WD is active in

normal and standby modes and off in sleep mode. Once the device enters standby or normal mode the timer

does not start until the first input trigger event. This event can be either writing a one to register 16'h0800[18] or if

selected, by changing the voltage level on the GPIO1 pin either high or low when configured for watchdog input.

If the first trigger is not set the watchdog is disabled. The first trigger can happen in standby mode or normal

mode. This is system implementation specific. While the timer is running, a SPI command writing a one to

16'h0800[18] resets the WD_TIMER timer or if configured for pin control the GPIO1 behaves as the watchdog

input bit.

The TCAN4550 has two ways of setting the trigger bit: via a SPI command and, if selected, through a GPI

(GPIO1 configured as GPI). When a GPI pin is used any rising or falling edge resets the timer. A watchdog event

can be conveyed back to the microprocessor in two methods: interrupt on nINT pin or, if selected, the GPO2 pin

can be programmed to toggle upon a WD timeout. A timeout can initiate one of three actions by the TCAN4550:

interrupt, INH toggle plus putting the device into standby mode or toggle watchdog output reset pin if enabled.

The input CLKIN or crystal values needs to be entered into reg 16'h0800[27] and is either 20 MHz or 40MHz.

See 表 2 for the register settings for the watchdog function.

注

•

If the device enters UV_IOprotected mode, the watchdog timer is held in reset. When

the device returns to standby mode, the timer resumes counting.

Once the command to enter sleep mode takes place, the WD timer is turned off and

does not trigger a watchdog event.

If the any of the watchdog registers needs to be changed, the watchdog must be

disabled and the change made and then re-enabled.

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表 2. Watchdog Registers and Descriptions

Address

BIT(S)

Field

Type

Reset

DESCRIPTION

WD_TIMER: Watchdog timer

00 = 60 ms

29:28

27

WD_TIMER

R/W

2'b00

01 = 600 ms

10 = 3 s

11 = 6 s

CLK_REF: CLKIN/Crystal frequency reference

0 = 20 MHz

CLK_REF

R/W

1'b1

1 = 40 MHz

GPO2_CONFIG: GPO2 configuration

00 = No action

GPO2_CONFI

G

23:22

2'b00

01 = M_CAN_INT 0 interrupt (active low)

10 = Watchdog output

11 = Mirrors nINT pin

WD_BIT_SET: write a 1 to reset timer: if times out; this bit is set and then

the selected action from register 16'h0800[17:16] takes place.

18

WD_BIT_SET

WD_ACTION

W1C

R/W

1'b0

Note: This is a self-clearing bit. Writing a 1 resets the timer and then the bit

clears.

16'h0800

WD_ACTION: Selected action when WD_TIMER times out

00 = Set interrupt flag and if a pin is configure to reflect WD output as an

interrupt the pin shows a low.

01 = Pulse INH pin and place device into standby mode – high - low - high

≈300ms

17:16

2'b00

10 = Pulse watchdog output pin if enabled – high - low - high ≈300ms

11 = Reserved

Note: Interrupt flag is always set for a WD timeout event.

GPIO1_CONFIG: GPIO1 Pin Function Select

00 = GPO

GPIO1_CONFI

G

15:14

RW

2'b01

1'b1

01 = Reserved

10 = GPI – Automatically becomes a WD input trigger pin.

11 = Reserved

WD_EN - Watchdog Enable

0 = Disable

3

WD_EN

RXU

1 = Enabled

8.4.6.2 Driver and Receiver Function

The TXD_INT and RXD_INT are internal signal paths that behave like the TXD and RXD pins for a physical layer

transceiver. During normal operation they are not accessible to external pins. The TCAN4550 provides a test

mode that maps these signals to external pins see Test Mode. The digital logic input and output levels for these

devices are CMOS levels with respect to V_IOfor compatibility with protocol controllers having 3.3 V to 5 V logic or

I/O. 表 3 and provides the states of the CAN driver and CAN receiver in each mode.

表 3. Driver Function Table

BUS OUTPUTS

DEVICE MODE

TXD_INT INPUT

DRIVEN BUS STATE

Dominant

CANH

CANL

L

H

Z

L

Z

Normal

H or Open

Biased Recessive

Weak Pull to GND

Standby

Sleep

X

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表 4. Receiver Function Table Normal and Standby Modes

CAN DIFFERENTIAL INPUTS

V_ID= V_CANH– V_CANL

DEVICE MODE

BUS STATE

RXD_INT TERMINAL

V_ID≥ 0.9 V

Dominant

Undefined

Recessive

Dominant

Undefined

Recessive

Open

L

Normal

0.5 V < V_ID< 0.9 V

V_ID≤ 0.5 V

Undefined

H

V_ID≥ 1.15 V

Standby/Sleep

Any

0.4 V < V_ID< 1.15 V

V_ID≤ 0.4 V

See 图 24

Open (V_ID≈ 0 V)

H

8.4.6.3 Floating Terminals

There are internal pull ups and pull downs on critical terminals to place the device into known states if the

terminal floats. See 表 5 for details on terminal bias conditions.

表 5. Terminal Bias

TERMINAL

SCLK

SDI

PULL UP or PULL DOWN

COMMENT

Pull up

Weakly biases input

nCS

Weakly biases input so the device is not selected

Weakly biases output when using internal voltage rail. When using

open drain configuration an external pull up is be needed.

nWKRQ

RST

Pull up

Pull down

Weakly biases RST terminal towards normal operation mode

注

The internal bias should not be relied upon as only termination, especially in noisy

environments but should be considered a failsafe protection. Special care needs to be

taken when the device is used with MCUs utilizing open drain outputs.

8.4.6.4 TXD_INT Dominant Timeout (DTO)

The TCAN4550 supports dominant state timeout. This is an internal function based upon the TXD_INT path. The

transceiver can be tested for this by placing the device into test mode and putting a dominant on the GPO1 pin

and monitor the GPO2 for RXD_INT_PHY. The TXD_INT DTO circuit prevents the local node from blocking

network communication in the event of a hardware or software failure where TXD_INT is held dominant (low)

longer than the timeout period t_{TXD_INT_DTO}. The TXD_INT DTO circuit is triggered by a falling edge on TXD_INT.

If no rising edge is seen before the timeout constant of the circuit, t_{TXD_INT_DTO}, the CAN driver is disabled. This

frees the bus for communication between other nodes on the network. The CAN driver is re-activated when a

recessive signal (high) is seen on TXD_INT terminal, thus clearing the dominant timeout. The receiver remains

active and the RXD_INT terminal reflects the activity on the CAN bus and the bus terminals is biased to

recessive level during a TXD_INT DTO fault.

注

The minimum dominant TXD_INT time allowed by the TXD_INT DTO circuit limits the

minimum possible transmitted data rate of the device. The CAN protocol allows a

maximum of eleven successive dominant bits (on TXD_INT) for the worst case, where five

successive dominant bits are followed immediately by an error frame.

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8.4.6.5 CAN Bus Short Circuit Current Limiting

This device has several protection features that limit the short circuit current when a CAN bus line is shorted.

These include CAN driver current limiting. The device has TXD_INT dominant timeout which prevents

permanently having the higher short circuit current of dominant state in case of a system fault. During CAN

communication the bus switches between dominant and recessive states, thus the short circuit current may be

viewed either as the current during each bus state or as a DC average current. For system current and power

considerations in the termination resistors and common mode choke ratings the average short circuit current

should be used. The percentage dominant is limited by the TXD_INT dominant timeout and CAN protocol which

has forced state changes and recessive bits such as bit stuffing, control fields, and inter frame space. These

ensure there is a minimum recessive amount of time on the bus even if the data field contains a high percentage

of dominant bits.

注

The short circuit current of the bus depends on the ratio of recessive to dominant bits and

their respective short circuit currents. The average short circuit current may be calculated

using 公式 1.

I_OS(AVG)= %Transmit x [(%REC_Bits x IOS(SS)_REC) + (%DOM_Bits x IOS(SS)_DOM)] + [%Receive x

IOS(SS)_REC]

(1)

Where

•

I_OS(AVG)is the average short circuit current.

%Transmit is the percentage the node is transmitting CAN messages.

%Receive is the percentage the node is receiving CAN messages.

%REC_Bits is the percentage of recessive bits in the transmitted CAN messages.

%DOM_Bits is the percentage of dominant bits in the transmitted CAN messages.

IOS(SS)_REC is the recessive steady state short circuit current and IOS(SS)_DOM is the dominant steady

state short circuit current.

注

The short circuit current and possible fault cases of the network should be taken into

consideration when sizing the power ratings of the termination resistance, other network

components, and the power supply used to generate V_SUP

.

8.4.6.6 Thermal Shutdown

This is a device preservation event. If the junction temperature of the device exceeds the thermal shut down

threshold, the device turns off the internal 5 V LDO for the CAN transceiver thus blocking the signal to bus

transmission path as well as turning of the ability to source current and voltage to the V_CCOUTpin. A thermal shut

down interrupt flag is set and an interrupt is inserted so that the microprocessor is informed. If this event

happens, other interrupt flags may be set as an example a bus fault where the CAN bus is shorted to V_bat. When

this happens the digital core and SPI interface are still active. After a time of ≈ 300 ms the device checks the

temperature of the junction. The thermal shutdown (TSD) timer starts when TSD fault event starts and exits to

standby mode when a TSD fault is not present when the TSD timer is expired. While in thermal shut down

protected mode a SPI write to change the device to either Normal or Standby mode is ignored while writes to

change to sleep mode is accepted.

注

If a thermal shut down event happens while the device is experiencing a V_IOunder voltage

event the device enters sleep mode.

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8.4.6.7 Under Voltage Lockout (UVLO) and Unpowered Device

The TCAN4550 monitors the V_SUP, V_IOand V_CCOUTpin for undervoltage events. These voltage rails have under

voltage detection circuitry which places the device into a protected state if an under voltage fault occurs for

UV_SUPand UV_IO. This protects the bus during an under voltage event on these terminals. If V_SUPis in under

voltage, the device loses the source needed to keep the internal regulators active. This causes the device to go

into a state where communication between the microprocessor and the TCAN4550 is disabled. The TCAN4550

is not able to receive information from the bus, and thus does not pass any signals from the bus, including any

Bus Wake via BWRR signals to the microprocessor. See 表 6.

8.4.6.7.1 UV_SUPand UV_CCOUT

When V_SUPdrops to UV_SUPlevel, the V_CCCAN transceiver regulator loses the ability to maintain 5 V output. At

this point, the UV_CCOUTinterrupt flag is set and the TCAN4550 turns off the regulator and place the CAN

transceiver into a standby state. If V_SUPreturns to minimum levels the device enters standby mode. If V_SUP

continues to decrease to the power on reset level, the TCAN4550 shuts everything down. When V_SUPreturns to

acceptable levels the device will come up the same as initial power on. All registers are cleared and the device

has to be reconfigured.

8.4.6.7.2 UV_IO

If V_IOdrops below UV_IOunder the voltage detection threshold, several functions are disabled. The transceiver

switchs off until V_IOhas recovered. The input clock or crystal circuits are disabled and the IO between the

TCAN4550 and microprocessor is not active. When UV_IOtriggers the t_UVtimer starts. If the timer times out and

the UV_IOis still there, the device enters sleep mode, see 图 23. Once in sleep mode a wake event is required to

place the TCAN4550 into standby mode and enables the INH pin. As registers are cleared in sleep mode the

UV_IOinterrupt flag is lost. If the UV_IOevent is still in place, the cycle repeats. If during a thermal shut down event

a UV_IOevent happens, the device automatically enters sleep mode.

The device is designed to be an "ideal passive" or “no load” to the CAN bus if the device is unpowered. The bus

terminals (CANH, CANL) have extremely low leakage currents when the device is unpowered so it does not load

the bus. This is critical if some nodes of the network are unpowered while the rest of the of network remains

operational. Logic terminals also have extremely low leakage currents when the device is unpowered, so they do

not load other circuits which may remain powered.

The UVLO circuit monitors both rising and falling edge of a power rail when ramping and declining.

表 6. Under Voltage Lockout I and O Level Shifting Devices

V_SUP

V_IO

V_CCOUT

> UV_CCOUT

< UV_CCOUT

NA

DEVICE STATE

Normal

BUS

RXD_INT

> UV_SUP

< UV_SUP

> UV_SUP

< UV_SUP

> UV_VIO

< UV_VIO

Per TXD_INT

High Impedance

Recessive

Mirrors Bus

Protected

High (Recessive)

High Impedance

> UV_CCOUT

NA

High Impedance

注

Once an under voltage condition and interrupt flags are cleared and the V_SUPsupply has

returned to valid level, the device typicallys need t_{MODE_CHANGE}to transition to normal

operation. The host processor should not attempt to send or receive messages until this

transition time has expired. If EN is low and V_SUPhas an under voltage event, the device

goes into a protected mode which disables the wake up receiver and places the RXD_INT

output into a high impedance state.

8.4.6.7.3 Fault and M_CAN Core Behavior:

During a UV_CCOUTor TSD fault the TCAN4550 automatically does the following to keep the M_CAN core in a

known state. A write of 1 to CCCR.INIT will be issued anytime there is a transition from Normal → Standby. Any

currently pending TX or RX processing is halted. Once the device re-enters Normal mode, a write of 0 to

CCCR.INIT is issued, and any pending messages (TXBRP active bits) is automatically transmitted.

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8.4.7 CAN FD

The TCAN4550 performs CAN communication according to ISO 11898-1:2015 and Bosch CAN protocol

specification 3.2.1.1.

8.5 Programming

The TCAN4550 uses 32 bit accesses. The TCAN4550 provides 2K bytes of MRAM that is fully configurable for

TX/RX buffer/FIFO as needed based upon the system needs. To avoid ECC errors right after initialization, the

MRAM should be zeroed out during the initialization, power up, power on reset and wake events, a process thus

ensuring ECC is properly calculated.

注

At power up, MRAM values are unknown and thus ECC values is not valid. It is important

that at least 2 words (8 bytes) of payload data be written into any TX buffer element, even

if the DLC is less than 8. Failure to do this results in a M_CAN BEU error, which puts the

TCAN4550 device into initialization mode, and require user intervention before CAN

communication can continue. One way to avoid this, the MRAM should be zeroed out after

power up, a power on reset or coming out of sleep mode.

8.5.1 SPI Communication

The SPI communication uses a standard SPI interface. Physically the digital interface pins are nCS (Chip Select

Not), SDI (Slave Data In), SDO (Slave Data Out) and SCLK (SPI Clock). Each SPI transaction is a 32 bit word

containing a command byte followed by two address bytes and length bytes. The data shifted out on the SDO pin

for the transaction always starts with the Global Status Register (byte). This register provides the high level

status information about the device status. The two data bytes which are the ‘response’ to the command byte are

shifted out next. Data bytes shifted out during a write command is content of the registers prior to the new data

being written and updating the registers. Data bytes shifted out during a read command are the current content

of the registers and the registers will not be updated.

The SPI input data on SDI is sampled on the low to high edge of the SCLK. The SPI output data on SDO is

changed on the high to low edge of the SCLK.

8.5.1.1 Chip Select Not (nCS):

This input pin is used to select the device for a SPI transaction. The pin is active low, so while nCS is high the

SDO pin of the device is high impedance allowing a SPI bus to be designed. When nCS is low the SDO driver is

activated and communication may be started. The nCS pin is held low for a SPI transaction. A special feature on

this device allows the SDO pin to immediately show the Global Fault Flag on a falling edge of nCS.

8.5.1.2 SPI Clock Input (SCLK):

This input pin is used to input the clock for the SPI to synchronize the input and output serial data bit streams.

The SPI Data Input is sampled on the rising edge of SCLK and the SPI Data Output is changed on the falling

edge of the SCLK.

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Programming (接下页)

SPI CLOCKING

ACTIONs: C = data capture, S = data shift,

L = load data out, P = process captured data

MODE 0 (CPOL = 0, CPHA = 0)

SCLK

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

SDI. SDO

ACTION

L

C

S

C

S

C

S

C

S

C

S

C

S

C

S

C

L

C

S

C

S

C

S

C

S

C

S

C

S

C

S

C

P

INTERNAL

CLK

INTERNAL_CLK = !CS xor CLK

图 34. SPI Clocking

8.5.1.3 SPI Data Input (SDI):

This input pin is used to shift data into the device. Once the SPI is enabled by a low on nCS the SDI samples the

input shifted data on each rising edge of the SCLK. The data is shifted into a 32 bit shift register. If the command

code was a write, the new data is written into the addressed register only after exactly 32 bits have been shifted

in by SCLK and the nCS has a rising edge to deselect the device. If there are not exactly a multiple of 32 bits

shifted in to the device, the during one SPI transaction (nCS low) the last word of the transfer is ignored, the

SPIERR flag is set.

注

Due to needing multiples of 32 bits on each SPI transaction, the device should be wired

for parallel operation of the SPI as a bus with control to the device via nCS and not as a

daisy chain of shift registers.

8.5.1.4 SPI Data Output (SDO):

This pin is high impedance until the SPI output is enabled via nCS. Once the SPI is enabled by a low on nCS,

the SDO is immediately driven high or low showing the Global Fault Flag status which is also the first bit (bit 32)

to be shifted out if the SPI is clocked. Once SCLK begins, on the first low to high edge of the clock the SDO

retains the Global Fault Flag which is bit 31 of the shift. On the first falling edge of SCLK, the shifting out of the

data continues with each falling edge on SCLK until all 32 bits have been shifted out the shift register.

8.5.2 Register Descriptions

The Addresses for each area of the device are as follows:

•

Register 16'h0000 through 16'h000C are Device ID and SPI Registers

Register 16'h0800 through 16'h083C are device configuration registers and Interrupt Flags

Register 16'h1000 through 16'h10FC are for M_CAN

Register 16'h8000 through 16'h87FF is for MRAM.

The start address must be word aligned (32-bit). Any time the registers are accessed, bits [1:0] of the address

are ignored as the addresses are always word (32-bit/4-byte) aligned. As an example for accessing the M_CAN

registers, for the register 0x1004, give the SPI address 1004, 1005, 1006 or 1007, and access register 1004. The

registers are 32 bit and only 1004 is valid in this example.

When entering the MRAM start address, the 0x8000 prefix is not necessary. For example, if the desired start

address is 0x8634, then bits SA[15:0] is 0x0634.

表 7 provides programming op Codes.

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Programming (接下页)

表 7. Access Commands

NAME

OP CODE

DESCRIPTION

USAGE

< WRITE_B_FL > <2 address bytes>

<1 length bytes>

WRITE_B_FL (burst: one

SPI transfer Length: fixed)

Write one or more

addresses

8'h61

< READ_B_FL > <2 address bytes>

<1 length bytes>

READ_B_FL (burst: one

SPI transfer Length: fixed)

Read one or more internal

SPI addresses

8'h41

Notes:

•

The two low order address bits is ignored

A length of 8’h00 indicates 256 words to be transferred

WRITE_B_FL

nCS

SCLK

SDI

LENGTH[7:0]

=8'H02

CMD: WRITE_B_FL = 8'h61

Reg0820[7:0]

ADDRESS [15:8]

ADDRESS [7:0]

SDO

nCS

SCLK

SDI

DATA_0[31:24]

DATA_0[23:16]

DATA_0[15:8]

DATA_0[7:0]

SDO

nCS

SCLK

SDI

DATA_1[31:24]

DATA_1[23:16]

DATA_1[15:8]

DATA_1[7:0]

SDO

图 35. Write

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READ_B_FL

nCS

SCLK

SDI

CMD: READ_B_FL

= 8'h41

LENGTH[7:0]

=8'H02

ADDRESS [15:8]

ADDRESS [7:0]

SDO

Reg0820[7:0]

nCS

SCLK

SDI

SDO

DATA_0[31:24]

DATA_0[23:16]

DATA_0[15:8]

DATA_0[7:0]

nCS

SCLK

SDI

SDO

DATA_1[31:24]

DATA_1[23:16]

DATA_1[15:8]

DATA_1[7:0]

图 36. Read (Command OpCode 8h41)

8.6 Register Maps

The TCAN4550 has a comprehensive register set with 32 bit addressing. The register is broken down into

several sections:

•

Device ID and Interrupt/Diagnostic Flag Registers: 16'h0000 to 16'h002F.

Device Configuration Registers: 16'h0800 to 16'h08FF .

Interrupt/Diagnostic Flag and Enable Flag Registers: 16'h0820/0824 and 16'h0830.

CAN FD Register Set: 16'h1000 to 16'h10FF.

注

All addresses are the lower order 16 address bit within the defined 32 bit address space.

Upper 16 address bits are ignored.

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Register Maps (接下页)

8.6.1 Device ID and Interrupt/Diagnostic Flag Registers: 16'h0000 to 16'h002F

This register block provided the device name and revision level. It provides all the interrupt flags as well.

Table 8. Device ID and Interrupt/Diagnostic Flag Registers

TCAN4550

VALUE

ADDRESS

REGISTER

ACCESS

DEVICE_ID[7:0] "T"

54

R

DEVICE_ID[15:8] "C"

DEVICE_ID[23:16] "A"

DEVICE_ID[31:24] "N"

DEVICE_ID[39:32] "4"

DEVICE_ID[47:40] "5"

DEVICE_ID[55:48] "5"

DEVICE_ID[63:56] "0"

43

‘h0000

41

4E

34

35

‘h0004

35

30

SPI_2_revision, 8’h00 (Reserved), REV_ID Major, REV_ID Minor REV_ID

Major

‘h0008

‘h000C

00

R

Status

Table 9. Device Configuration Access Type Codes

Access Type

Code

Description

Read Type

R

Read

Write Type

W

Write

WC

Reset or Default Value

-n

Value after reset or the default value

Undefined

U

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8.6.1.1 DEVICE_ID1[31:0] (address = h0000) [reset = h4E414354]

Figure 37. Device ID1

31

23

15

7

30

22

14

6

29

21

13

5

28

27

26

18

10

2

25

17

9

24

16

8

DEVICE_ID1[31:24]

RO

20

19

DEVICE_ID1[23:16]

RO

12

DEVICE_ID1[15:8]

RO

11

4

3

1

0

DEVICE_ID1[7:0]

RO

Table 10. Device ID Field Descriptions

Bit

31:0

Field

DEVICE_ID1[31:0]

Type

Reset

Description

RO

h4E41435

4

DEVICE_ID1[31:0]

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8.6.1.2 DEVICE_ID2[31:0] (address = h0004) [reset = h30353534]

Figure 38. Device ID2

31

23

15

7

30

22

14

6

29

21

13

5

28

27

26

18

10

2

25

17

9

24

16

8

DEVICE_ID2[31:24]

RO

20

19

DEVICE_ID2[23:16]

RO

12

DEVICE_ID2[15:8]

RO

11

4

3

1

0

DEVICE_ID2[7:0]

RO

Table 11. Device ID Field Descriptions

Bit

31:0

Field

DEVICE_ID2[31:0]

Type

Reset

Description

RO

h3035353

4

DEVICE_ID2[63:32]

47

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ZHCSJ74A –DECEMBER 2018–REVISED JANUARY 2020

www.ti.com.cn

8.6.1.3 Revision (address = h0008) [reset = h00110201]

Figure 39. Revision

31

23

15

7

30

22

14

6

29

21

13

5

28

27

26

18

10

2

25

17

9

24

16

8

SPI_2_REVISION

RO

20

12

19

11

RSVD

RO

REV_ID MAJOR

RO

4

3

1

0

REV_ID MINOR

RO

Table 12. Revision Field Descriptions

Bit

Field

Type

RO

Reset

h00

Description

31:24

23:16

15:8

7:0

SPI_2_REVISION

RSVD

Revision version of the SPI module

Reserved

RO

h11

REV_ID MAJOR

REV_ID MINOR

RO

h02

Device REV_ID Major

Device REV_ID Minor

RO

h01

48

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8.6.1.4 Status (address = h000C) [reset = h0000000U]

Figure 40. Status

31

23

30

22

29

28

27

26

25

24

RSVD

RO

Internal_read_e Internal_write_e Internal_error_l Read_fifo_unde Read_fifo_empt Write_fifo_overf

rror

og_write

W1C

rflow

W1C

y

low

W1C

21

20

19

18

17

16

RSVD

RO

SPI_end_error Invalid_comma Write_overflow write_underflow Read_overflow read_underflow

nd

W1C

13

W1C

12

W1C

11

W1C

10

W1C

9

W1C

8

15

7

14

6

RSVD

RO

5

4

3

2

1

0

RSVD

RO

Write_fifo_avail Read_fifo_avail Internal_access Internal_error_i SPI_error_interr

Interrupt

able

_active

nterrupt

upt

RO

Table 13. Status Field Descriptions

Bit

Field

Type

RO

Reset

1’b0

Description

31:30

29

RSVD

Reserved

Internal_read_error

Internal_write_error

Internal_error_log_write

Read_fifo_underflow

Read_fifo_empty

Write_fifo_overflow

RSVD

W1C

RO

Internal read received an error response

Internal write received an error response

Entry written to the Internal error log

28

27

26

Read FIFO underflow after 1 or more read data words returned

Read FIFO empty for first read data word to return

Write/command FIFO overflow

25

24

23:22

21

Reserved

SPI_end_error

W1C

SPI transfer did not end on a byte boundary

Invalid SPI command received

20

Invalid_command

Write_overflow

19

SPI write sequence had continue requests after the data transfer

was completed

18

17

16

write_underflow

Read_overflow

read_underflow

W1C

1’b0

SPI write sequence ended with less data transferred then

requested

SPI read sequence had continue requests after the data transfer

was completed

SPI read sequence ended with less data transferred then

requested

15:8

7:6

5

RSVD

RO

8’h00

1’b0

Reserved

RSVD

Write_fifo_available

write fifo empty entries is greater than or equal to the

write_fifo_threshold

4

Read_fifo_available

RO

1’b0

Read fifo entries is greater than or equal to the

read_fifo_threshold

3

2

1

0

Internal_access_active

Internal_error_interrupt

SPI_error_interrupt

Interrupt

RO

U

Internal Multiple transfer mode access in progress

Unmasked Internal error set

1’b0

U

Unmasked SPI error set

Value of interrupt input level (active high)

49

TCAN4550

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www.ti.com.cn

8.6.2 Device Configuration Registers: 16'h0800 to 16'h08FF

Registers not listed are reserved and return h’00.

Table 14. Device Configuration Registers

ADDRESS

0800

REGISTER

VALUE

ACCESS

R/W/U

R/W

R/W/U

R

Modes of Operation and Pin Configurations

Timestamp Prescalar

Read and Write Test Registers

ECC and TDR Registers

Reserved

h'C8000468

h’00000002

h’00000000

h'00000000

h’00000000

h'00000000

h’FFFFFFFF

h'00000000

0804

0808

080C – 0810

0814 -081C

0820

Interrupt Flags

R

0824

MCAN Interrupt Flags

Reserved

R

0829 – 082F

0830

R

Interrupt Enable

R/W

R

0834 – 083F

Reserved

NOTE

The following bits are being saved when entering sleep mode and will show up bold in

register maps.

•

16'h0800 bits 0, 1, 8, 9, 10, 11, 13, 14, 15, 19, 21, 22, 23, 30 and 31.

16'h0820 bits 18, 19 and 21

16'h0830 bits 14 and 15

8.6.2.1 Modes of Operation and Pin Configuration Registers (address = h0800) [reset = hC8000468]

Figure 41. Modes of Operation and Pin Configuration Registers

31

WAKE_CONFIG

R/W

30

29

28

27

CLK_REF

R/W

26

RSVD

R

25

RSVD

R

24

RSVD

R

WD_TIMER

R/W

23

22

21

20

19

18

17

16

GPO2_CONFIG

TEST_MODE_

EN

RSVD

nWKRQ_VOLT WD_BIT_SET

WD_ACTION

R/W

AGE

R/W

R

R/W

15

14

13

12

11

10

9

8

FAIL_SAFE_E

N

RSVD

GPO1_GPO_CONFIG

INH_DIS

nWKRQ_CON

FIG

R

R/W

R

R/W

7

6

5

4

3

2

1

0

MODE_SEL

R/W/U

RSVD

WD_EN

DEVICE_RESE

T

SWE_DIS

TEST_MODE_

CONFIG

R

R/W/U

R/W

Table 15. Modes of Operation and Pin Configuration Registers Field Descriptions

Bit

Field

Type

Reset

Description

WAKE_CONFIG: Wake pin configuration

00 = Disabled

31:30

WAKE_CONFIG

R/W

2’b11

01 = Rising edge

10 = Falling edge

11 = Bi-Directional – either edge

50

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Table 15. Modes of Operation and Pin Configuration Registers Field Descriptions (continued)

Bit

Field

Type

Reset

Description

WD_TIMER: Watchdog timer

00 = 60 ms

29:28

WD_TIMER

R/W

2’b00

01 = 600 ms

10 = 3 s

11 = 6 s

CLK_REF: CLKIN/Crystal Frequency Reference

27

CLK_REF

RSVD

R/W

R

1'b1

0 = 20 MHz

1 = 40 MHz

26:24

3'b000

Reserved

GPO2_CONFIG: GPO2 Pin GPO Configuration

00 = No Action

01 = MCAN_INT 0 interrupt (Active low)

10 = Watchdog output

23:22

GPO2_CONFIG

R/W

2’b00

11 = Mirrors nINT pin (Active low)

See NOTE section

TEST_MODE_EN: Test mode enable. When set device is in test

mode

0 = Disabled

1 = Enabled

21

20

19

TEST_MODE_EN

RSVD

R/W

R

1'b0

1’b0

Reserved

nWKRQ_VOLTAGE: nWKRQ Pin GPO buffer voltage rail

configuration: See

0 = Internal voltage rail

nWKRQ_VOLTAGE

R/W

1 = VIO voltage rail

WD_BIT_SET: Write a 1 to reset timer: if times out this bit will

set and then the selected action from 0800[17:16] will take

place. (TCAN4x50 Only otherwise reserved) This is a self-

clearing bit. Writing a 1 resets the timer and then the bit clears

18

WD_BIT_SET

WD_ACTION

R/W

1’b0

WD_ACTION: Selected action when WD_TIMER times out

00 = Set interrupt flag and if a pin is configure to reflect WD

output as an interrupt the pin will show a low.

01 = Pulse INH pin and placedevice into standby mode – high to

low to high ≈300ms

17:16

2’b00

10 = Pulse watchdog output pin if enabled – high to low to high

≈300ms

11 = Reserved

NOTE: Interrupt flag is always set for a WD timeout event.

GPIO1_CONFIG: GPIO1 Pin Function Select

00 = GPO

01 = Reserved

10 = GPI – Automatically becomes a WD input trigger pin.

11 = Reserved

GPIO1_CONFIG

R/W

2’b00

FAIL_SAFE_EN: Fail safe mode enable:

0 = Disabled

1 = Enabled

13

FAIL_SAFE_EN

R/W

R

1'b0

NOTE: Excludes power up fail safe.

12

RSVD

Reserved

GPIO1_GPO_CONFIG: GPIO1 pin GPO1 function select

00 = SPI fault Interrupt (Active low)

11:10

GPIO1_GPO_CONFIG

R/W

2’b01

01 = MCAN_INT 1 (Active low)

10 = Under voltage or thermal event interrupt (Active low)

11 = Reserved

INH_DIS: INH Pin Disable

0 = Pin enabled

1 = Pin disabled

9

8

INH_DIS

R/W

1'b0

nWKRQ_CONFIG: nWKRQ Pin Function

0 = Mirrors INH function

nWKRQ_CONFIG

1 = Wake request interrupt

51

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www.ti.com.cn

Table 15. Modes of Operation and Pin Configuration Registers Field Descriptions (continued)

Bit

Field

Type

Reset

Description

MODE_SEL: Mode of operation select

00 = Sleep

01 = Standby

10 = Normal

7:6

MODE_SEL

R/W

2'b01

11 = Reserved

See NOTE section

5

4

RSVD

R

1'b1

1'b0

If this bit is written to it must be a 1

Reserved

WD_EN: Watchdog Enable

0 = Disabled

3

WD_EN

R/X/U

1’b1

1 = Enabled

DEVICE_RESET: Device Reset

0 = Current configuration

1 = Device resets to default

NOTE: Same function as RST pin

2

DEVICE_RESET

R/WC

1'b0

SWE_DIS: Sleep Wake Error Disable:

0 = Enabled

1 = Disabled

NOTE: This disables the device from starting the four minute

timer when coming out of sleep mode on a wake event. If this is

enabled a SPI read or write must take place within this four

minute window or the device will go back to sleep. This does not

disable the function for initial power on or in case of a power on

reset.

1

0

SWE_DIS

R/W

1'b0

Test Mode Configuration

0 = Phy Test with TXD/RXD_INT_PHY and EN_INT are mapped

to external pins

TEST_MODE_CONFIG

1 = CAN Controller test with TXD/RXD_INT_CAN mapped to

external pins

NOTE

The Mode of Operation changes the mode but will read back the mode the device is

currently in.

When the device is changing the device to normal mode a write of 0 to CCCR.INIT is

automatically issued and when changing from normal mode to standby or sleep modes

a write of 1 to CCCR.INIT is automatically issued.

•

When GPO1 is configured as a GPO for interrupts the interrupts list represent the

following and are active low:

–

00: SPI Fault Interrupt. Matches SPIERR if not masked

01: MCAN_INT:1 m_can_int1.

10: Under Voltage or Thermal Event Interrupt: Logical OR of UV_CCOUT,UV_SUP

,

UV_VIO, TSD faults that are not masked.

When GPO1 is configured as a GPO for interrupts the interrupts list represent the

following and are active low:

–

00: SPI Fault Interrupt. Matches SPIERR if not masked

01: MCAN_INT:1 m_can_int1.

10: Under Voltage or Thermal Event Interrupt: Logical OR of UV_CCOUT,UV_SUP

,

UV_VIO, TSD faults that are not masked.

nWKRQ pin defaults to a push-pull active low configuration based off an internal

voltage rail. When configuring this to work off of V_IOthe pin becomes and open drain

output and a external pull up resistor to the V_IOrail is required.

52

TCAN4550

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8.6.2.2 Timestamp Prescalar (address = h0804) [reset = h00000002]

Figure 42. Timestamp Prescalar

31

23

15

7

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

24

16

8

RSVD

R

RSVD

R

RSVD

R

1

0

Timestamp Prescalar

R/W

Table 16. EMC Enhancement and Timestamp Prescalar Field Descriptions

Bit

Field

Type

R

Reset

8’h00

Description

Reserved

31:24

23:16

15:8

RSVD

R

Writing to this register resets the internal timestamp counter to 0

and will set the internal CAN clock divider used for MCAN

Timestamp generation to (Timestamp Prescalar x 8)

7:0

Timestamp Prescalar

R/W

8'h02

53

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8.6.2.3 Test Register and Scratch Pad (address = h0808) [reset = h00000000]

Saved in sleep mode

Figure 43. Test and Scratch Pad Register

31

23

15

7

30

22

14

6

29

21

13

5

28

27

26

18

10

2

25

17

9

24

16

8

Test Read and Write

R/W

20

19

Test Read and Write

R/W

12

11

Scratch Pad 1

R/W

4

3

1

0

Scratch Pad 2

R/W

Table 17. Test and Scratch Pad Register Field Descriptions

Bit

Field

Type

RW

Reset

8’h00

Description

31:24

23:16

15:8

7:0

Test Read and Write

Scratch Pad 1

Test Read and Write Register

R/W

Bits 15:8 are saved when device is configured for sleep mode

Bits 7:0 are saved when device is configured for sleep mode

Scratch Pad 2

54

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8.6.2.4 Test Register (address = h080C) [reset = h00000000]

Figure 44. Test Register

31

30

29

21

28

20

12

27

26

18

25

17

24

16

RSVD

R

23

RSVD

R

22

RSVD

R

19

ECC_ERR_FORCE_BIT_SEL

R/W

15

14

13

11

10

9

8

RSVD

R

RSVD

ECC_ERR_FO ECC_ERR_CH

RSVD

RCE

ECK

R

5

R/W

R

2

R

1

R

0

7

6

4

3

RSVD

R

Table 18. Test Register Field Descriptions

Bit

Field

Type

R

Reset

8’h00

2'b00

Description

Reserved

31:24

23:22

RSVD

R

6’b0000 ECC_ERR_FORCE_BIT_SEL

00

000000 = Bit 0

000001 = Bit 1

....

21:16

ECC_ERR_FORCE_BIT_SEL

R/W

100110 = Bit 38

All other bit combinations are Reserved

3’b000 Reserved

ECC_ERR_FORCE

15:13

12

RSVD

R

ECC_ERR_FORCE

R/W

1’b0

0 = No Force

1 = Force a single bit ECC error

ECC_ERR_CHECK

11

10

ECC_ERR_CHECK

RSVD

R/W

R

1’b0

1b'0

0 = No Single Bit ECC error detected

1 = Single Bit ECC error detected

Reserved

10'b000 Reserved

9:0

RSVD

R

000000

0

55

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8.6.3 Interrupt/Diagnostic Flag and Enable Flag Registers: 16'h0820/0824 and 16'h0830

This register block provides all the interrupt flags for the device. As the M-CAN interrupt flags 16'h0824 are

described in 16'h1050 MCAN register description section and will be shown here but need to go to 16'h1050 for

description. 16h’0830 is Interrupt enable to trigger an interrupt for 16'h0820.

8.6.3.1 Interrupts (address = h0820) [reset = h00100000]

Figure 45. Interrupts

31

CANBUSNOM

RU

30

RSVD

R

29

RSVD

R

28

RSVD

R

27

RSVD

R

26

RSVD

R

25

RSVD

R

24

RSVD

R

23

RSVD

R

22

21

20

19

18

17

RSVD

R

16

UVSUP

R/WC

UVIO

R/WC

PWRON

R/WC/U

TSD

R/WC

WDTO

RU/WC

ECCERR

R/WC

15

14

13

12

RSVD

R

11

RSVD

R

10

9

RSVD

R

8

CANINT

R/WC

LWU

R/WC

WKERR

R/WC

CANSLNT

R/WC

CANDOM

R/WC

7

GLOBALERR

R

6

nWKRQ

R

5

CANERR

R

4

RSVD

R

3

SPIERR

R

2

RSVD

R

1

M_CAN_INT

R

0

VTWD

R

Table 19. Interrupts Field Descriptions

Bit

31

Field

CANBUSNOM

Type

Reset

Description

CAN Bus normal (Flag and Not Interrupt)

Will change to 1 when in normal mode after first Dom to Rec

transition

RU

1'b0

30:24

23

RSVD

SMS

R

7b'0000 Reserved

000

R/WC

1'b0

Sleep Mode Status (Flag & Not an interrupt) Only sets when

sleep mode is entered by a WKERR, UVIO timeout, or

UVIO+TSD fault

22

21

20

19

18

17

16

15

14

13

12

11

10

9

UVSUP

UVIO

R/WC

1'b0

Under Voltage V_SUPand UV_CCOUT

Under Voltage V_IO

Power ON

PWRON

TSD

R/WC/U 1'b1

R/WC 1'b0

RU/WC 1'b0

Thermal Shutdown

Watchdog Time Out

Reserved

WDTO

RSVD

R

1'b0

ECCERR

CANINT

LWU

R/WC

R

Uncorrectable ECC error detected

Can Bus Wake Up Interrupt

Local Wake Up

Wake Error

WKERR

RSVD

Reserved

RSVD

R

Reserved

CANSLNT

RSVD

R/WC

R

CAN Silent

Reserved

8

CANDOM

GLOBALERR

WKRQ

CANERR

RSVD

R/WC

R

CAN Stuck Dominant

Global Error (Any Fault)

Wake Request

CAN Error

7

6

R

5

R

4

R

RSVD

3

SPIERR

RSVD

R

SPI Error

2

R

Reserved

56

TCAN4550

www.ti.com.cn

ZHCSJ74A –DECEMBER 2018–REVISED JANUARY 2020

Table 19. Interrupts Field Descriptions (continued)

Bit

1

Field

Type

R

Reset

1'b0

Description

M_CAN_INT

VTWD

M_CAN global INT

0

R

1'b0

Global Voltage, Temp or WDTO

GLOBALERR: Logical OR of all faults in registers 0x0820-0824.

WKRQ: Logical OR of CANINT, LWU and WKERR.

CANBUSNOM is not an interrupt but a flag. In normal mode after the first dominant-recessive transition it will set.

It will reset to 0 when entering Standby or Sleep modes or when a bus fault condition takes place in normal

mode.

CANERR: Logical OR of CANSLNT and CANDOM faults.

SPIERR: Will be set if any of the SPI status register 16'h000C[30:16] is set.

•

In the event of a SPI underflow, the error is not detected/alerted until the start of the next SPI transaction.

16'h0010[30:16] are the mask for these errors

VTWD: Logical or of UV_CCOUT, UVSUP, UVVIO, TSD, WDTO (Watchdog time out) and ECCERR.

CANINT: Indicates a WUP has occurred; Once a CANINT flag is set, LWU events will be ignored. Flag can be

cleared by changing to Normal or Sleep modes.

LWU: Indicates a local wake event, from toggling the WAKE pin, has occurred. Once a LWU flag is set, CANINT

events will be ignored. Flag can be cleared by changing to Normal or Sleep modes.

WKERR: If the device receives a wake up request WUP and does not transition to Normal mode or clear the

PWRON or Wake flag before t_INACTIVE, the device will transition to Sleep Mode. After the wake event, a Wake

Error (WKERR) will be reported and the SMS flag will be set to 1.

NOTE

PWRON Flag is cleared by either writing a 1 or by going to sleep mode or normal mode

from standby mode.

57

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8.6.3.2 MCAN Interrupts (address = h0824) [reset = h00000000]

Figure 46. MCAN Interrupts

31

30

29

ARA

R

28

PED

R

27

PEA

R

26

WDI

R

25

BO

R

24

EW

R

RSVD

R

23

EP

R

22

ELO

R

21

BEU

R

20

BEC

R

19

DRX

R

18

TOO

R

17

MRAF

R

16

TSW

R

15

TEFL

R

14

TEFF

R

13

TEFW

R

12

TEFN

R

11

TFE

R

10

TCF

R

9

TC

R

8

HPM

R

7

RF1L

R

6

RF1F

R

5

RF1W

R

4

RF1N

R

3

RF0L

R

2

RF0F

R

1

RF0W

R

0

RF0N

R

Table 20. MCAN Interrupts Field Descriptions

Bit

Field

RSVD

ARA

PED

PEA

Type

R

Reset

1'b0

1’b0

Description

31:30

29

Reserved

R

ARA: Access to Reserved Address

28

R

PED: Protocol Error in Data Phase (Data Bit Time is used)

27

R

PEA: Protocol Error in Arbitration Phase (Nominal Bit Time is

used)

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

WDI

R

1'b0

1’b0

1'b0

1’b0

1'b0

1’b0

1'b0

WDI: Watchdog Interrupt

BO

BO: Bus_Off Status

EW

EW: Warning Status

EP

EP: Error Passive

ELO

ELO: Error Logging Overflow

BEU: Bit Error Uncorrected

BEU

BEC

DRX

TOO

MRAF

TSW

TEFL

TEFF

TEFW

TEFN

TFE

BEC: Bit Error Corrected

DRX: Message stored to Dedicated Rx Buffer

TOO: Timeout Occurred

MRAF: Message RAM Access Failure

TSW: Timestamp Wraparound

TEFL: Tx Event FIFO Element Lost

TEFF: Tx Event FIFO Full

TEFW: Tx Event FIFO Watermark Reached

TEFN: Tx Event FIFO New Entry

TFE: Tx FIFO Empty

TCF

TCF: Transmission Cancellation Finished

TC: Transmission Completed

HPM: High Priority Message

RF1L: Rx FIFO 1 Message Lost

RF1F: Rx FIFO 1 Full

TC

8

HPM

RF1L

RF1F

RF1W

RF1N

RF0L

RF0F

RF0W

RF0N

7

6

5

RF1W: Rx FIFO 1 Watermark Reached

RF1N: Rx FIFO 1 New Message

RF0L: Rx FIFO 0 Message Lost

RF0F: Rx FIFO 0 Full

4

3

2

1

RF0W: Rx FIFO 0 Watermark Reached

RF0N: Rx FIFO 0 New Message

0

58

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ZHCSJ74A –DECEMBER 2018–REVISED JANUARY 2020

8.6.3.3 Interrupt Enables (address = h0830 ) [reset = hFFFFFFFF]

Figure 47. 32-bit, 4 Rows

31

RSVD

R

30

RSVD

R

29

RSVD

R

28

RSVD

R

27

RSVD

R

26

RSVD

R

25

RSVD

R

24

RSVD

R

23

RSVD

R

22

21

20

RSVD

R

19

18

RSVD

R

17

RSVD

R

16

UVSUP

R/W

UVIO

R/W

TSD

R/W

ECCERR

R/W

15

14

13

RSVD

R

12

RSVD

R

11

RSVD

R

10

CANSLNT

R/W

9

RSVD

R

8

CANDOM

R

CANINT

R/W

LWU

R/W

7

6

5

4

3

2

1

0

RSVD

R

Table 21. Interrupt Enables Field Descriptions

Bit

31:24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

Field

Type

R

Reset

8'hFF

1'b1

8’hFF

Description

RSVD

UVSUP

Reserved

R

Reserved

R/W

R

Under Voltage V_SUPand UV_CC

Under Voltage V_IO

Reserved

RSVD

TSD

R/W

R

Thermal Shutdown

Reserved

RSVD

ECCERR

CANINT

LWU

R

Reserved

R/W

R

Uncorrectable ECC error detected

Can Bus Wake Up Interrupt

Local Wake Up

Reserved

RSVD

R

Reserved

R

Reserved

CANSLNT

RSVD

R/W

R

CAN Silent

Reserved

8

CANDOM

RSVD

R/W

R

CAN Stuck Dominant

Reserved

7:0

59

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ZHCSJ74A –DECEMBER 2018–REVISED JANUARY 2020

www.ti.com.cn

8.6.4 CAN FD Register Set: 16'h1000 to 16'h10FF

The following tables provide the CAN FD programming register sets starting at 16'h1000.

The MRAM and start address for the following registers has special consideration:

•

SIDFC (0x1084)

XIDFC (0x1088)

RXF0C (0x10A0)

RXF1C (0x10B0)

TXBC (0x10C0)

TXEFC (0x10F0)

The start address must be word aligned (32-bit) in the MRAM. The 2 least significant bits are ignored on a write

to ensure this behavior.

When entering the MRAM start address, the 0x8000 prefix is NOT necessary. For example, if the desired start

address is 0x8634, then bits SA[15:0] will be 0x0634.

Table 22. Legend

Code

Description

Read

R

C

d

Clear on Write

date

n

Value after Reset

Protected Set

Protected Write

Release

p

P

r

S

t

Set on Read

Test Value

Undefined

Write

U

W

X

Reset on Read

Table 23. CAN FD Register Set

ADDRESS

1000

1004

1008

100C

1010

1014

1018

101C

1020

1024

1028

102C

1030

1034

1038

103C

1040

1044

SYMBOL

CREL

ENDN

CUST

DBTP

TEST

RWD

NAME

RESET

ACC

R

Core Release Register

rrrd dddd

Endian Register

8765 4321

0000 0000

0000 0A33

0000 0000

0000 0019

0600 0A03

0000 0000

FFFF 0000

0000 FFFF

0000 0000

0000 0707

R

Customer Register

R

Data Bit Timing & Prescaler Register

Test Register

RP

RWPp

RP

RC

RP

RC

R

RAM Watchdog

CCCR

NBTP

TSCC

TSCV

TOCC

TOCV

RSVD

ECR

CC Control Register

Nominal Bit Timing & Prescaler Register

Timestamp Counter Configuration

Timestamp Counter Value

Timeout Counter Configuration

Timeout Counter Value

Reserved

R

Reserved

R

Reserved

R

Error Counter Register

Protocol Status Register

RX

RXS

PSR

60

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ZHCSJ74A –DECEMBER 2018–REVISED JANUARY 2020

Table 23. CAN FD Register Set (continued)

ADDRESS

1048

104C

1050

1054

1058

105C

1060

1064

1068

106C

1070

1074

1078

107C

1080

1084

1088

108C

1090

1094

1098

109C

10A0

10A4

10A8

10AC

10B0

10B4

10B8

10BC

10C0

10C4

10C8

10CC

10D0

10D4

10D8

10DC

10E0

10E4

10E8

10EC

10F0

10F4

10F8

10FC

SYMBOL

TDCR

RSVD

IR

NAME

Transmitter Delay Compensation Register

Reserved

RESET

ACC

RP

R

0000 0000

1FFF FFFF

0000 0000

Interrupt Register

RW

R

IE

Interrupt Enable

ILS

Interrupt Line Select

Interrupt Line Enable

Reserved

ILE

RSVD

GFC

Reserved

R

Reserved

R

Reserved

R

Reserved

R

Reserved

R

Reserved

R

Reserved

R

Global Filter Configuration

Standard ID Filter Configuration

Extended ID Filter Configuration

Reserved

RP

R

SIDFC

XIDFC

RSVD

XIDAM

HPMS

NDAT1

NDAT2

RXF0C

RXF0S

RXF0A

RXBC

RXF1C

RXF1S

RXF1A

RXESC

TXBC

TXFQS

TXESC

TXBRP

TXBAR

TXBCR

TXBTO

TXBCF

TXBTIE

TXBCIE

RSVD

TXEFC

TXEFS

TXEFA

RSVD

Extended ID and MASK

High Priority Message Status

New Data 1

RP

R

RW

RP

R

New Data 2

Rx FIFO 0 Configuration

Rx FIFO 0 Status

Rx FIFO 0 Acknowledge

Rx Buffer Configuration

Rx FIFO 1 Configuration

Rx FIFO 1 Status

RW

RP

R

Rx FIFO 1 Acknowledge

Rx Buffer/FIFO Element Size Configuration

Tx Buffer Configuration

Tx FIFO/Queue Status

Tx Buffer Element Size Configuration

Tx Buffer Request Pending

Tx Buffer Add Request

Tx Buffer Cancellation Request

Tx Buffer Transmission Occurred

Tx Buffer Cancellation Finished

Tx Buffer Transmission Interrupt Enable

Tx Buffer Cancellation Finished Interrupt Enable

Reserved

RW

RP

R

RP

R

RW

R

RW

R

Reserved

R

Tx Event FIFO Configuration

Tx Event FIFO Status

Tx Event FIFO Acknowledge

Reserved

RP

R

RW

R

61

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www.ti.com.cn

Table 24. CAN FD Register Set Description

Offset

Name

Bit Pos.

7:0

MSB

LSB

Access

Day[7:0] (two digit, BCD-Coded)

R

15:8

23:16

31:24

7:0

Month[15:8] (two digit, BCD-Coded)

1000

CREL

SUBSTEP[7:4] (One digit, BCD-Coded)

REL[7:4] (One digit, BCD-Coded)

Year[3:0] (one digit, BCD-Coded)

STEP[3:0] (one digit, BCD-Coded)

ETV[7:0] (Endianness Test Value)

15:8

23:16

31:24

7:0

ETV[15:8] (Endianness Test Value)

ETV[23:16] (Endianness Test Value)

ETV[31:24] (Endianness Test Value)

1004

1008

100C

1010

1014

1018

101C

1020

1024

1028

ENDN

CUST

DBTP

TEST

RWD

15:8

23:16

31:24

7:0

DTSEG2(Data Time Seg before Sample Point)

Reserved

DSJW (Data (Re)Synchronization Jump Width)

RP

R

15:8

23:16

31:24

7:0

DTSEG1(Data Time Seg before Sample Point)

DBRP (Data Bit Rate Prescaler)

TDC

Reserved

RX

TX

LBCK

Reserved

RP-U

R

15:8

23:16

31:24

7:0

Reserved

R

WDC (Watchdog Configuration)

WDV (Watchdog Counter Value)

Reserved

RP

R

15:8

23:16

31:24

7:0

R

Reserved

R

TEST

NISO

DAR

TXP

MON

EFBI

CSR

CSA

ASM

CCE

INIT

RWp

RP

R

15:8

23:16

31:24

7:0

PXHD

Reserved

BRSE

FDOE

CCCR

NBTP

TSCC

TSCV

TOCC

Reserved

R

Reserved

NTSEG2 (Nominal time Segment After Sample Point)

RP

15:8

23:16

31:24

7:0

NTSEG1 (Nominal Time Segment Before Sample Point)

NBRP[7:0] (Nominal Bit Rate Prescaler)

NSJW[6;0] (Nominal (RE)Synchronization Jump Width)

NBRP[8]

TSS[1:0] Timestamp Select

RP

R

Reserved

15:8

23:16

31:24

7:0

Reserved

TCP (Timestamp Counter Prescaler)

RP

R

Reserved

RC

R

TSC[15:0] (Timestamp Counter)

15:8

23:16

31:24

7:0

Reserved

R

Reserved

TOS (Timeout SEL)

ETOC

RP

R

15:8

23:16

31:24

7:0

Reserved

RP

RC

R

TOP[15:0] (Timeout Period)

TOC[15:0] (Timeout Counter)

15:8

23:16

31:24

31:0

7:0

102C

1030 – 103C

1040

TOCV

RSVD

ECR

Reserved

R

Reserved

R

TEC (Transmit Error Counter)

REC (Receive Error Counter)

CEL (CAN Error Logging)

Reserved

R

15:8

23:16

31:24

R

X

R

62

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Table 24. CAN FD Register Set Description (continued)

Offset

Name

Bit Pos.

7:0

MSB

LSB

Access

RS

RSX

R

BO

EW

EP

ACT (Activity)

RBRS RESI

LEC (Last Error Code)

DLEC ( Data Phase Last Error Code)

15:8

23:16

31:24

7:0

Reserved

PXE

RFDF

1044

PSR

TDCV[6:0] (Transmitter Delay Compensation Value)

Reserved

R

Reserved

TDCF (Transmitter Delay Compensation Filter Window Length)

RP

R

15:8

23:16

31:24

31:0

7:0

TDCO (Transmitter Delay Compensation Offset)

1048

104C

1050

TDCR

RSVD

IR

Reserved

R

RF1L

TEFL

EP

RF1F

TEFF

ELO

RF1W

TEFW

BEU

RF1N

TEFN

BEC

RF0L

TFE

RF0F

TCF

RF0W

TC

RF0N

HPM

R/W

R

15:8

23:16

31:24

7:0

DRX

TOO

MRAF

BO

TSW

Reserved

ARA

PED

PEA

WDI

EW

RF1LE

TEFLE

EPE

RF1FE

TEFFE

ELOE

RF1WE

TEFWE

BEUE

ARAE

RF1WL

TEFWL

BEUL

RF1NE

TEFNE

BECE

PEDE

RF1NL

TEFNL

BECL

PEDL

RF0LE

TFEE

DRXE

PEAE

RF0LL

TFEL

DRXL

PEAL

RF0FE

TCFE

TOOE

WDIE

RF0FL

TCFL

TOOL

WDIL

RF0WE

TCE

RF0NE

HPME

TSWE

EWE

15:8

23:16

31:24

7:0

1054

1058

IE

MRAFE

BOE

Reserved

RF1LL

TEFLL

EPL

RF1FL

TEFFL

ELOL

RF0WL

TCL

RF0NL

HPML

TSWL

EWL

15:8

23:16

31:24

7:0

ILS

MRAFL

BOL

Reserved

ARAL

Reserved

EINT1

EINT0

15:8

23:16

31:24

31:0

7:0

Reserved

105C

1060 – 107C

1080

ILE

RSVD

GFC

Reserved

R

Reserved

ANFS

ANFE

RRFS

RRFE

RP

R

15:8

23:16

31:24

7:0

Reserved

R

FLSS[7:2] (Filter List Standard Start Address)

Reserved

RP

R

15:8

23:16

31:24

7:0

FLSS[15:8] (Filter List Standard Start Address)

LSS (List Size Standard)

Reserved

1084

SIDFC

FLESA[7:2] (Filter List Extended Start Address)

Reserved

RP

R

15:8

23:16

31:24

31:0

7:0

FLESA[15:8] (Filter List Extended Start Address)

LSE (List Size Extended)

1088

108C

1090

XIDFC

RSVD

XIDAM

Reserved

R

EIDM[7:0] (Extended ID AND MASK)

EIDM[15:8] (Extended ID AND MASK)

EIDM[23:16] (Extended ID AND MASK)

RP

15:8

23:16

31:24

Reserved

EIDM[28:24] (Extended ID AND MASK)

BIDX (Buffer Index)

MSI (Message Storage

Index)

7:0

R

15:8

23:16

31:24

7:0

FLST

FIDX (Filter Index)

Reserved

R

1094

HPMS

R

ND7

ND6

ND5

ND4

ND3

ND2

ND1

ND9

ND0

ND8

R/W

15:8

ND15

ND23

ND31

ND39

ND47

ND55

ND63

ND14

ND22

ND30

ND38

ND46

ND54

ND62

ND13

ND21

ND29

ND37

ND45

ND53

ND61

ND12

ND20

ND28

ND36

ND44

ND52

ND60

ND11

ND19

ND27

ND35

ND43

ND51

ND59

ND10

ND18

ND26

ND34

ND42

ND50

ND58

1098

109C

NDAT1

NDAT2

23:16

31:24

7:0

ND17

ND25

ND33

ND41

ND49

ND57

ND16

ND24

ND32

ND40

ND48

ND56

15:8

23:16

31:24

63

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www.ti.com.cn

Table 24. CAN FD Register Set Description (continued)

Offset

Name

Bit Pos.

7:0

MSB

LSB

Access

RP

R

F0SA[7:2] (RX FIFO 0 Start Address)

F0SA[15:8] (RX FIFO 0 Start Address)

Reserved

15:8

23:16

31:24

7:0

10A0

RXF0C

Reserved

F0OM

F0S (RX FIFO 0 Size)

F0WM (RX FIFO 0 Watermark)

Reserved

15:8

23:16

31:24

7:0

Reserved

R

10A4

10A8

10AC

10B0

10B4

10B8

10BC

10C0

10C4

10C8

10CC

10D0

10D4

RXF0S

RXF0A

RXBC

Reserved

R

Reserved

R

Reserved

F0A (RX FIFO 0 Acknowledge Index)

R/W

R

15:8

23:16

31:24

7:0

Reserved

R

RBSA[7:2] (RX Buffer Configuration)

RBSA[15:8] (RX Buffer Configuration)

Reserved

RP

R

15:8

23:16

31:24

7:0

Reserved

R

F1SA[7:2] (RX FIFO 1 Start Address)

RP

R

15:8

23:16

31:24

7:0

F1SA[15:8] (RX FIFO 1 Start Address)

RXF1C

RXF1S

RXF1A

RXESC

TXBC

Reserved

F1S (RX FIFO 1 Size)

F1WM (RX FIFO 1 Watermark)

F1FL (RX FIFO 1 Fill Level)

F1GI (RX FIFO 1 Get Index)

F1PI (RX FIFO 1 Put Index)

Reserved

F1OM

Reserved

15:8

23:16

31:24

7:0

Reserved

R

Reserved

DMS (Data Message Status)

Reserved

R

RF1L

F1F

R

F1AI (RX FIFO 1 Acknowledge Index)

Reserved

R/W

R

15:8

23:16

31:24

7:0

Reserved

R

Reserved

R

Reserved

F1DS (RX FIFO 1 Data Field Size)

Reserved

F0DS (RX FIFO 0 Data Field Size)

RBDS (RX Buffer Data Field Size)

RP

R

15:8

23:16

31:24

7:0

Reserved

TBSA[7:2] (TX Buffer Start Address)

TBSA[15:8] (TX Buffer Start Address)

NDTB (Number of Dedicated Transmit Buffers)

R

Reserved

RP

R

15:8

23:16

31:24

7:0

Reserved

Reserved TFQM

Reserved

TFQS (Transmit FIFO/Queue Size)

TFFL (TX FIFO Free Level)

15:8

23:16

31:24

7:0

TFGI (TX FIFO Get Index)

R

TXQFS

TXESC

TXBRP

TXBAR

TXBCR

TFQF

TFQP (TX FIFO/Queue Put Index)

R

Reserved

R

Reserved

TBDS (TX Buffer Data Field Size)

RP

R

15:8

23:16

31:24

7:0

Reserved

R

TRP7

TRP15

TRP23

TRP31

AR7

TRP6

TRP5

TRP13

TRP21

TRP29

AR5

TRP4

TRP3

TRP11

TRP19

TRP27

AR3

TRP2

TRP10

TRP18

TRP26

AR2

TRP1

TRP9

TRP17

TRP25

AR1

TRP0

TRP8

TRP16

TRP24

AR0

R

15:8

23:16

31:24

7:0

TRP14

TRP22

TRP30

AR6

TRP12

TRP20

TRP28

AR4

R

R/W

RW

15:8

23:16

31:24

7:0

AR15

AR23

AR31

CR7

AR14

AR22

AR30

CR6

AR13

AR21

AR29

CR5

AR12

AR20

AR28

CR4

AR11

AR19

AR27

CR3

AR10

AR18

AR26

CR2

AR9

AR8

AR17

AR25

CR1

AR16

AR24

CR0

15:8

23:16

31:24

CR15

CR23

CR31

CR14

CR22

CR30

CR13

CR21

CR29

CR12

CR20

CR28

CR11

CR19

CR27

CR10

CR18

CR26

CR9

CR8

CR17

CR25

CR16

CR24

64

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ZHCSJ74A –DECEMBER 2018–REVISED JANUARY 2020

Table 24. CAN FD Register Set Description (continued)

Offset

Name

Bit Pos.

7:0

MSB

LSB

TO0

Access

R

TO7

TO6

TO14

TO22

TO30

CF6

TO5

TO13

TO21

TO29

CF5

TO4

TO12

TO20

TO28

CF4

TO3

TO11

TO19

TO27

CF3

TO2

TO10

TO18

TO26

CF2

TO1

TO9

15:8

23:16

31:24

7:0

TO15

TO23

TO31

CF7

TO8

R

10D8

TXBTO

TO17

TO25

CF1

TO16

TO24

CF0

R

15:8

23:16

31:24

7:0

CF15

CF23

CF31

TIE7

CF14

CF22

CF30

TIE6

CF13

CF21

CF29

TIE5

CF12

CF20

CF28

TIE4

CF11

CF19

CF27

TIE3

CF10

CF18

CF26

TIE2

CF9

CF8

R

10DC

10E0

TXBCF

TXBTIE

CF17

CF25

TIE1

CF16

CF24

TIE0

R

RW

R

15:8

23:16

31:24

7:0

TIE15

TIE23

TIE31

CFIE7

CFIE15

CFIE23

CFIE31

TIE14

TIE22

TIE30

CFIE6

CFIE14

CFIE22

CFIE30

TIE13

TIE21

TIE29

CFIE5

CFIE13

CFIE21

CFIE29

TIE12

TIE20

TIE28

CFIE4

CFIE12

CFIE20

CFIE28

TIE11

TIE19

TIE27

CFIE3

CFIE11

CFIE19

CFIE27

TIE10

TIE18

TIE26

CFIE2

CFIE10

CFIE18

CFIE26

TIE9

TIE8

TIE17

TIE25

CFIE1

CFIE9

CFIE17

CFIE25

TIE16

TIE24

CFIE0

CFIE8

CFIE16

CFIE24

15:8

23:16

31:24

31:0

7:0

10E4

10E8 - 10EC

10F0

TXBCIE

RSVD

Reserved

EFSA[7:2] (Event FIFO Start Address)

EFSA[15:8] (Event FIFO Start Address)

Reserved

RP

15:8

23:16

31:24

7:0

TXEFC

Reserved

EFS (Event FIFO Size)

EFWM (Event FIFO Watermark)

EFFL (Event FIFO Fill Level)

Reserved

15:8

23:16

31:24

7:0

Reserved

EFGI (Event FIFO Get Index)

EFPI (Event FIFO Put Index)

10F4

TXEFS

Reserved

TEFL

EFA (Event FIFO Acknowledge Index)

EFF

R

RW

R

15:8

23:16

31:24

31:0

Reserved

10F8

10FC

TXEFA

RSVD

R

65

TCAN4550

ZHCSJ74A –DECEMBER 2018–REVISED JANUARY 2020

www.ti.com.cn

8.6.4.1 Core Release Register (address = h1000) [reset = hrrrddddd]

Figure 48. Core Release Register

31

23

15

7

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

24

16

8

REL[3:0]

R

STEP[3:0]

R

SUBSTEP[3:0]

R

YEAR[3:0]

R

MONTH[7:0]

R

1

0

DAY[7:0]

R

Table 25. Core Release Register Field Descriptions

Bit

Field

Type

R

Reset

Description

31:28

27:24

23:20

19:16

15:8

REL[3:0]

STEP[3:0]

r

one digit, BCD-coded

two digit, BCD-coded

R

r

SUBSTEP[3:0]

YEAR[3:0]

R

r

R

d

MONTH[7:0]

DAY[7:0]

R

7:0

R

66

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ZHCSJ74A –DECEMBER 2018–REVISED JANUARY 2020

8.6.4.2 Endian Register (address = h1004) [reset = h87654321]

Figure 49. Endian Register

31

23

15

7

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

24

16

8

ETV[31:24]

R

ETV[23:16]

R

ETV[15:8]

R

1

0

ETV[7:0]

R

Table 26. Endian Register Field Descriptions

Bit

Field

Type

R

Reset

0x87

0x65

0x43

0x21

Description

31:24

23:16

15:8

7:0

ETV[31:24]

ETV[23:16]

ETV[15:8]

ETV[7:0]

Endianness Test Value

R

67

TCAN4550

ZHCSJ74A –DECEMBER 2018–REVISED JANUARY 2020

www.ti.com.cn

8.6.4.3 Customer Register (address = h1008) [reset = h00000000]

Figure 50. Customer Register

31

23

15

7

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

24

16

8

RSVD

R

RSVD

R

RSVD

R

1

0

RSVD

R

Table 27. Customer Register Field Descriptions

Bit

31:0

Field

Type

Reset

Description

RSVD

R

h0000000 Reserved

0

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8.6.4.4 Data Bit Timing & Prescaler (address = h100C) [reset = h0000A33]

Figure 51. Data Bit Timing & Prescaler

31

30

22

29

21

13

5

28

20

12

4

27

19

11

3

26

25

17

9

24

16

8

RSVD

R

23

TDC

n

18

DBRP[4:0]

RP

RSVD

R

15

14

RSVD

R

10

DTSEG1[4:0]

RP

7

6

2

1

0

DTSEG2[3:0]

RP

DSJW[3:0]

RP

Table 28. Data Bit Timing & Prescaler Field Descriptions

Bit

Field

Type

Reset

Description

31:24

RSVD

R

0x0

Reserved

Transmitter Delay Compensation

0 – TDC Disabled

23

TDC

RP

0x0

1 – TDC Enabled

22:21

20:16

15:13

12:8

7:4

RSVD

R

0x0

0xA

0x3

Reserved

DBRP[4:0]

RSVD

RP

R

Data Bit Rate Prescaler

Reserved

DTSEG1[4:0]

DTSEG2[3:0]

DSJW[3:0]

RP

Data time Segment before sample point

Data (Re)Synchronization Jump Width

2:0

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8.6.4.5 Test Register (address = h1010 ) [reset = h00000000]

Figure 52. Test Register

31

23

15

30

22

14

6

29

21

13

5

28

RSVD

R

27

19

11

3

26

18

10

2

25

17

9

24

16

8

20

RSVD

R

12

RSVD

R

7

RX

R

4

1

0

TX[1:0]

RP

LBCK

RP

RSVD

R

Table 29. Test Register Field Descriptions

Bit

Field

Type

R

Reset

0x0

Description

Reserved

31:24

23:16

15:8

RSVD

R

0x0

R

0x0

Receive Pin (m_can_rx)

0 – CAN Bus is Dominant

1 – CAN Bus is Recessive

7

RX

R

U

Control of Transmit Pin (m_can_tx)

00 – Reset Value, updated at the end of the CAN bit time

01 – Sample Point can be monitored at PIN m_can_tx

10 – Dominant (‘0’) level at pin

6:5

TX[1:0]

RP

0x0

11 – Recessive (‘1’) level at pin

LBCK: Loop Back Mode

4

LBCK

RSVD

RP

R

0

0 – Reset Value, Loop Back Mode is Disabled

1 – Loop Back Mode is Enabled

3:0

0x0

Reserved

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8.6.4.6 RAM Watchdog (address = h1014) [reset = h00000000]

Figure 53. RAM Watchdog

31

23

15

7

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

24

16

8

RSVD

R

RSVD

R

WDV[7:0]

R

1

0

WDC[7:0]

RP

Table 30. RAM Watchdog Field Descriptions

Bit

Field

Type

R

Reset

0x0

Description

31:24

23:16

15:8

7:0

RSVD

Reserved

RSVD

R

0x0

Reserved

WDV[7:0]

WDC[7:0]

R

0x0

Watchdog Counter Value

Watchdog Configuration

RP

0x0

71

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8.6.4.7 Control Register (address = h1018) [reset = 0000 0019]

Figure 54. Control Register

31

23

30

22

29

21

28

20

27

19

11

26

18

10

25

17

24

16

RSVD

R

RSVD

R

15

NISO

RP

14

TXP

RP

13

EFBI

RP

12

PXHD

RP

9

8

RSVD

R

BRSE

RP

FDOE

RP

7

6

5

4

3

CSA

R

2

1

0

TEST

Rp

DAR

RP

MON

Rp

CSR

R/W

ASM

Rp

CCE

RP

INIT

R/W

Table 31. Control Register Field Descriptions

Bit

Field

Type

R

Reset

0x0

Description

Reserved

31:24

23:16

RSVD

R

0x0

Reserved

Non ISO Operation

0 – CAN FD Frame format according to ISO 11898-1:2015

1 – CAN FD Frame format according to Bosch CAN FD

Specification V1.0

15

14

13

NISO

TXP

RP

0

Transmitter Pause

0 – Transmitter Pause Disabled

1 – Transmitter Pause Enabled

Edge Filtering during Bus Integration

0 – Edge Filtering Disabled

1 – Two Consecutive Dominant tq required to detect an edge for

hard synchronization

EFBI

Protocol Exception Handling Disable

0 – Protocol Exception Handling Enabled

1 – Protocol Exception Handling Disabled

12

11:10

9

PXHD

RSVD

BRSE

RP

R

0

0x0

0

Reserved

Bit Rate Switch Enable

0 – Bit Rate Switching for Transmission Disabled

1 – Bit Rate Switching for Transmission Enabled

RP

FD Operation Enable

8

7

FDOE

TEST

RP

Rp

0

0 – FD Operation Disabled

1 – FD Operation Enabled

Test Mode Enable

0 – Normal Mode of Operation, Register TEST Holds Reset

Value

1 – Test Mode, Write Access to Register TEST Enabled

Disable Automatic Retransmission

0 – Automatic Retransmission of Messages not Transmitted

Successfully Enabled

1 – Automatic Retransmission Disabled

6

5

DAR

RP

Rp

0

Bus Monitoring Mode is Disabled

0 – Bus Monitoring Mode is Disabled

1 – Bus Monitoring Mode is Enabled

MON

Clock Stop Request

0 – No clock Stop is requested

1 – Clock Stop Requested. When requested first INIT and then

CSA will be set after all pending transfer request have

completed and the CAN bus reached idle

See NOTE section

4

CSR

R/W

1

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Table 31. Control Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

Clock Stop Acknowledge

0 – No Clock Stop Requested

1 – m_can may be set in power down by stopping m_can-hclk

and m_can_cclk

3

CSA

ASM

R

1

Restricted Operation Mode

0 – Normal CAN Operation

1 – Restricted Operation Mode Active

2

1

0

Rp

0

1

Configuration Change Enable

0 – CPU has no write access to the protected configuration

registers

1 – CPU has write access to the protected configuration

registers (While CCCR.INIT =1)

CCE

INIT

RP

Initialization

0 – Normal Operation

1 – Initialization has started

R/W

NOTE

The TCAN4550 handles stop request through hardware. The means that a 1 should not

be written to CCCR.CSR (Clock Stop Request) as this will interfere with normal operation.

If a Read-Modify-Write operation is performed in Standby mode a CSR = 1 will be read

back but a 0 should be written to it.

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8.6.4.8 Nominal Bit Timing & Prescaler Register (address = h101C) [reset = h06000A03]

Figure 55. Nominal Bit Timing & Prescaler Register

31

23

15

30

22

14

6

29

21

13

5

28

NSJW[6:0]

RP

27

19

11

3

26

18

10

2

25

17

9

24

NBRP[8]

RP

20

16

NBRP[7:0]

RP

12

4

8

NTSEG1[7:0]

RP

7

RSVD

R

1

0

NTSEG2[6:0]

RP

Table 32. Nominal Bit Timing & Prescaler Register Field Descriptions

Bit

Field

Type

Reset

Description

Nominal (RE)Synchronization Jump Width

0x00 - 0x7F – Valid values are 0 to 127 - The actual

interpretation by the hardware of this value is such that one

more than the value programmed here is used.

31:25

NSJW[6:0]

RP

0x3

Nominal Bit Rate Prescaler

0x000 - 0x1FF – Value by which the oscillator frequency is

divided for generating the bit time quanta. Valid values are 0 to

511. - The actual interpretation by the hardware of this value is

such that one more than the value programmed here is used.

24:16

NBRP[8:0]

RP

0x0

Nominal Time Segment Before Sample Point)

0x01-0xFF – Valid values are 1 to 255 - The actual interpretation

by the hardware of this value is such that one more than the

value programmed here is used.

15:8

7

NTSEG1[7:0]

RSVD

RP

R

0xA

0

Reserved

Nominal Time Segment After Sample Point

0x01-0x7F – Valid values are 1 to 127 - The actual interpretation

by the hardware of this value is such that one more than the

value programmed here is used.

6:0

NTSEG2[6:0]

RP

0x3

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8.6.4.9 Timestamp Counter Configuration (address = h1020) [reset = h00000000]

Figure 56. Timestamp Counter Configuration

31

23

15

7

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

24

16

8

RSVD

R

RSVD

R

TCP[3:0]

RP

RSVD

R

1

0

RSVD

R

TSS[1:0]

RP

Table 33. Timestamp Counter Configuration Descriptions

Bit

Field

Type

R

Reset

0x0

Description

31:24

23:20

RSVD

Reserved

R

0x0

Reserved

Timestamp Counter Prescaler

19:16

TCP[3:0]

RP

0x0

0x0 - 0xF – Configures timestamp and timeout counters time

unit in multiples of CAN bit times [1…16]

15:8

7:2

RSVD

R

0x0

Reserved

Timestamp Select

00 – Timestamp counter value always 0x0000

01 – Timestamp counter value incremented according to TCP

10 – External timestamp counter value used

11 – Same as "00"

1:0

TSS[1:0]

RP

0x0

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8.6.4.10 Timestamp Counter Value (address = h1024) [reset = h00000000]

Figure 57. Timestamp Counter Value

31

23

15

7

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

24

16

8

RSVD

R

RSVD

R

TSC[15:8]

RC

1

0

TSC[7:0]

RC

Table 34. Timestamp Counter Value Field Descriptions

Bit

Field

Type

R

Reset

0x0

Description

Reserved

31:24

23:20

15:8

RSVD

R

0x0

Reserved

Timestamp Counter

The internal/external Timestamp Counter value is captured on

start of frame (both Rx and Tx). When TSCC.TSS = “01”, the

Timestamp Counter is incremented in multiples of CAN bit times

[1…16] depending on the configuration of TSCC.TCP. A wrap

around sets interrupt flag IR.TSW. Write access resets the

counter to zero. When TSCC.TSS = “10”, TSC reflects the

external

TSC[7:0]

RC

0x0

Timestamp Counter value. A write access has no impact.

7:0

Timestamp Counter

The internal/external Timestamp Counter value is captured on

start of frame (both Rx and Tx). When TSCC.TSS = “01”, the

Timestamp Counter is incremented in multiples of CAN bit times

[1…16] depending on the configuration of TSCC.TCP. A wrap

around sets interrupt flag IR.TSW. Write access resets the

counter to zero. When TSCC.TSS = “10”, TSC reflects the

external

TSC[7:0]

RC

0x0

Timestamp Counter value. A write access has no impact.

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8.6.4.11 Timeout Counter Configuration (address = h1028) [reset = hFFFF0000]

Figure 58. Timeout Counter Configuration

31

23

15

7

30

22

14

6

29

21

13

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

24

16

8

TOP[15:8]

R

TOP[7:0]

R

RSVD

R

5

RSVD

R

1

0

TOS[1:0]

RP

ETOC

RP

Table 35. Timeout Counter Configuration Field Descriptions

Bit

Field

Type

Reset

Description

Timeout Period

31:24

23:16

TOP[15:8]

RP

0xFF

Start value of the timeout counter (down-counter). Configures

the timeout period

Timeout Period

TOP[7:0]

RP

0xFF

Start value of the timeout counter (down-counter). Configures

the timeout period

15:8

7:3

RSVD

R

0x0

Reserved

Timeout Select

When operating in Continuous mode, a write to TOCV presets

the counter to the value configured by TOCC.TOP and

continues down-counting. When the Timeout Counter is

controlled by one of the FIFOs, an empty FIFO presets the

counter to the value configured by TOCC.TOP. Down-counting

is started when the first FIFO element is stored

00 – Continuous Operation

01 – Timeout controlled by TX Event FIFO

10 – Timeout controlled by Rx FIFO 0

11 – Timeout controlled by Rx FIFO 1

2:1

TOS[1:0]

RP

0x0

Enable Timeout Counter

0 – Timeout counter disabled

1 – Timeout counter enabled

0

ETOC

0

77

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8.6.4.12 Timeout Counter Value (address = h102C) [reset = h0000FFFF]

Figure 59. Timeout Counter Value

31

23

15

7

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

24

16

8

RSVD

R

RSVD

R

TOC[15:8]

RC

1

0

TOC[7:0]

RC

Table 36. Timeout Counter Value Field Descriptions

Bit

Field

Type

R

Reset

0x0

Description

Reserved

31:24

23:16

RSVD

R

0x0

Reserved

Timeout Counter

The Timeout Counter is decremented in multiples of CAN bit

times [1…16] depending on the configuration of TSCC.TCP.

When decremented to zero, interrupt flag IR.TOO is set and the

Timeout Counter is stopped. Start and reset/restart conditions

are configured via TOCC.TOS

15:8

7:0

TOC[15:8]

TOC[7:0]

RC

0xFF

Timeout Counter

The Timeout Counter is decremented in multiples of CAN bit

times [1…16] depending on the configuration of TSCC.TCP.

When decremented to zero, interrupt flag IR.TOO is set and the

Timeout Counter is stopped. Start and reset/restart conditions

are configured via TOCC.TOS

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8.6.4.13 Reserved (address = h1030 - h103C) [reset = h00000000]

Figure 60. Reserved

31

23

15

7

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

24

16

8

RSVD

R

RSVD

R

RSVD

R

1

0

RSVD

R

Table 37. Reserved Field Descriptions

Bit

31:0

Field

Type

Reset

Description

RSVD

R

0

Reserved

79

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8.6.4.14 Error Counter Register (address = h1040) [reset = h00000000]

Figure 61. Error Counter Register

31

23

30

22

14

6

29

21

13

5

28

20

12

4

27

19

26

18

10

2

25

17

9

24

16

8

RSVD

R

CEL[7:0]

X

15

RP

R

11

REC[6:0]

R

7

3

1

0

TEC[7:0]

R

Table 38. Error Counter Register Field Descriptions

Bit

Field

Type

Reset

Description

31:24

RSVD

R

0x0

Reserved

CAN Error Logging

The counter is incremented each time when a CAN protocol

error causes the Transmit Error Counter or the Receive Error

Counter to be incremented. It is reset by read access to CEL.

The counter stops at 0xFF; the next increment of TEC or REC

sets interrupt flag IR.ELO

23:16

CEL[7:0]

RP

X

R

0x0

0

0 – The Receive Error Counter is below the error passive level

of 128

1 – The Receive Error Counter has reached the error passive

level of 128

15

Actual state of the Receive Error Counter, values between 0 and

127

14:8

7:0

REC[6:0]

TEC[7:0]

R

0x0

Actual state of the Transmit Error Counter, values between 0

and 255

NOTE

When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC

when a CAN protocol error is detected, but CEL is still incremented.

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8.6.4.15 Protocol Status Register (address = h1044) [reset = h00000707]

Figure 62. Protocol Status Register

31

30

22

29

21

28

20

27

26

18

10

2

25

17

24

16

8

RSVD

R

23

RSVD

R

19

TDCV[6:0]

R

15

RSVD

R

14

PXE

X

13

RFDF

X

12

RBRS

X

11

RESI

X

9

DLEC[2:0]

S

7

BO

R

6

EW

R

5

EP

R

4

3

1

LEC[2:0]

S

0

ACT[1:0]

R

Table 39. Protocol Status Register Field Descriptions

Bit

Field

Type

R

Reset

0x0

Description

Reserved

31:24

23

RSVD

R

0x0

Transmitter Delay Compensation Value

0x00-0x7F – Position of the secondary sample point, defined by

the sum of the measured delay from m_can_tx to m_can_rx and

TDCR.TDCO. The SSP position is, in the data phase, the

number of mtq between the start of the transmitted bit and the

secondary sample point. Valid values are 0 to 127 mtq.

22:16

TDCV[6:0]

R

0x0

15

14

RSVD

PXE

R

X

0

Reserved

Protocol Exception Event

0 – No protocol exception event occurred since last read access

1 – Protocol exception event occurred

Received a CAN FD Message

This bit is set independent of acceptance filtering

0 – Since this bit was reset by the CPU, no CAN FD message

has been received

13

RFDF

X

0

1 – Message in CAN FD format with FDF flag set has been

received

BRS flag of last received CAN FD Message

This bit is set together with RFDF, independent of acceptance

filtering.

0 – Last received CAN FD message did not have its BRS flag

set

12

11

RBRS

X

0

1 – Last received CAN FD message had its BRS flag set

ESI flag of last received CAN FD Message

This bit is set together with RFDF, independent of acceptance

filtering.

0 – Last received CAN FD message did not have its ESI flag set

1 – Last received CAN FD message had its ESI flag set

RESI

0

Data Phase Last Error Code

Type of last error that occurred in the data phase of a CAN FD

format frame with its BRS flag set. Coding is the same as for

LEC. This field will be cleared to zero when a CAN FD format

frame with its BRS flag set has been transferred (reception or

transmission) without error.

10:8

DLEC[2:0]

0x7

Bus_Off Status

7

6

BO

R

0

0 – The M_CAN is not Bus_Off

1 – The M_CAN is in Bus_Off state

Warning Status

0 – Both error counters are below the Error_Warning limit of 96

1 – At least one of error counter has reached the Error_Warning

limit of 96

EW

81

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Table 39. Protocol Status Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

Error Passive

0 – The M_CAN is in the Error_Active state. It normally takes

part in bus communication and sends an active error flag when

an error has been detected

5

EP

R

0

1 – The M_CAN is in the Error_Passive state

Activity

Monitors the module’s CAN communication state.

00 – Synchronizing - node is synchronizing on CAN

communication

4:3

ACT[1:0]

R

0x0

01 – Idle - node is neither receiver nor transmitter

10 – Receiver - node is operating as receiver

11 – Transmitter - node is operating as transmitter

Last Error Code

The LEC indicates the type of the last error to occur on the CAN

bus. This field will be cleared to ‘0’ when a message has been

transferred (reception or transmission) without error.

0 – No Error: No error occurred since LEC has been reset by

successful reception or transmission

1 – Stuff Error: More than 5 equal bits in a sequence have

occurred in a part of a received message where this is not

allowed.

2 – Form Error: A fixed format part of a received frame has the

wrong format.

3 – AckError: The message transmitted by the M_CAN was not

acknowledged by another node.

4 – Bit1Error: During the transmission of a message (with the

exception of the arbitration field), the device wanted to send a

recessive level (bit of logical value ‘1’), but the monitored bus

value was dominant.

2:0

LEC[2:0]

S

0x7

5 – Bit0Error: During the transmission of a message (or

acknowledge bit, or active error flag, or overload flag), the

device wanted to send a dominant level (data or identifier bit

logical value ‘0’), but the monitored bus value was recessive.

During Bus_Off recovery this status is set each time a sequence

of 11 recessive bits has been monitored. This enables the CPU

to monitor the proceeding of the Bus_Off recovery sequence

(indicating the bus is not stuck at dominant or continuously

disturbed).

6 – CRCError: The CRC check sum of a received message was

incorrect. The CRC of an incoming message does not match

with the CRC calculated from the received data.

7 – NoChange: Any read access to the Protocol Status Register

re-initializes the LEC to ‘7’. When the LEC shows the value ‘7’,

no CAN bus event was detected since the last CPU read access

to the Protocol Status Register.

NOTE

When a frame in CAN FD format has reached the data phase with BRS flag set, the next

CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed

stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error

82

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NOTE

The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting

or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own

accord, stopping all bus activities. Once CCCR.INIT has been cleared by the CPU, the

device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits)

before resuming normal operation. At the end of the Bus_Off recovery sequence, the Error

Management Counters will be reset. During the waiting time after the resetting of

CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error

code is written to PSR.LEC, enabling the CPU to readily checkup whether the CAN bus is

stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery

sequence. ECR.REC is used to count these sequences.

83

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8.6.4.16 Transmitter Delay Compensation Register (address = h1048) [reset = h00000000]

Figure 63. Transmitter Delay Compensation Register

31

23

30

22

14

6

29

21

13

5

28

20

12

4

27

19

26

18

10

2

25

17

9

24

16

8

RSVD

R

RSVD

R

15

RSVD

R

11

TDCO[6:0]

RP

7

RSVD

R

3

1

0

TDCF[6:0]

RP

Table 40. Transmitter Delay Compensation Register Field Descriptions

Bit

Field

Type

R

Reset

0x0

0

Description

31:24

23:16

15

RSVD

Reserved

R

Reserved

R

Reserved

Transmitter Delay Compensation Offset

0x00-0x7F - Offset value defining the distance between the

measured delay from m_can_tx to m_can_rx and the secondary

sample point. Valid values are 0 to 127 mtq.

14:8

7

TDCO[6:0]

RSVD

RP

R

0x0

0

Reserved

Transmitter Delay Compensation Filter Window Length

0x00-0x7F - Defines the minimum value of the SSP position,

dominant edges on m_can_rx that would result in an earlier SSP

position are ignored for transmitter delay measurement. The

feature is enabled when TDCF is configured to a value greater

than TDCO. Valid values are 0 to 127 mtq.

6:0

TDCF[6:0]

RP

0x0

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8.6.4.17 Reserved (address = h104C) [reset = h00000000]

Figure 64. Reserved

31

23

15

7

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

24

16

8

RSVD

R

RSVD

R

RSVD

R

1

0

RSVD

R

Table 41. Reserved Field Descriptions

Bit

31:0

Field

Type

Reset

Description

RSVD

R

0

Reserved

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8.6.4.18 Interrupt Register (address = h1050) [reset = h00000000]

Figure 65. Interrupt Register

31

30

29

28

27

26

25

BO

24

RSVD

R

ARA

R/W

PED

R/W

PEA

R/W

WDI

R/W

EW

R/W

23

EP

22

21

20

19

18

17

16

ELO

R/W

BEU

R/W

BEC

R/W

DRX

R/W

TOO

R/W

MRF

R/W

TSW

R/W

15

14

13

12

11

10

9

8

TEFL

R/W

TEFF

R/W

TEFW

R/W

TEFN

R/W

TFE

R/W

TCF

R/W

TC

HPM

R/W

7

6

5

4

3

2

1

0

RF1L

R/W

RF1F

R/W

RF1W

R/W

RF1N

R/W

RF0L

R/W

RF0F

R/W

RF0W

R/W

RF0N

R/W

Table 42. Interrupt Register Field Descriptions

Bit

Field

Type

Reset

Description

31:30

RSVD

R

0x0

Reserved

Access to Reserved Address

29

ARA

PED

PEA

WDI

BO

R/W

0

0 – No access to reserved address occurred

1 – Access to reserved address occurred

Protocol Error in Data Phase (Data Bit Time is used)

0 – No protocol error in data phase

1 – Protocol error in data phase detected (PSR.DLEC ≠ 0,7)

28

27

26

25

24

23

22

Protocol Error in Arbitration Phase (Nominal Bit Time is used)

0 – No protocol error in arbitration phase

1 – Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7)

Watchdog Interrupt

0 – No Message RAM Watchdog event occurred

1 – Message RAM Watchdog event due to missing READY

Bus_Off Status

0 – Bus_Off status unchanged

1 – Bus_Off status changed

Warning Status

0 – Error_Warning status unchanged

1 – Error_Warning status changed

EW

Error Passive

0 – Error_Passive status unchanged

1 – Error_Passive status changed

EP

ELO: Error Logging Overflow

0 – CAN Error Logging Counter did not overflow

1 – Overflow of CAN Error Logging Counter occurred

ELO

Bit Error Uncorrected

Message RAM bit error detected, uncorrected. Controlled by

input signal m_can_aeim_berr[1] generated by an optional

external parity / ECC logic attached to the Message RAM. An

uncorrected Message RAM bit error sets CCCR.INIT to ‘1’. This

is done to avoid transmission of corrupted data.

21

20

BEU

BEC

R/W

0

0 – No bit error detected when reading from Message RAM

1 – Bit error detected, uncorrected (e.g. parity logic)

Bit Error Corrected

Message RAM bit error detected and corrected. Controlled by

input signal m_can_aeim_berr[0] generated by an optional

external parity / ECC logic attached to the Message RAM.

0 – No bit error detected when reading from Message RAM

1 – Bit error detected and corrected (e.g. ECC)

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Table 42. Interrupt Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

Message stored to Dedicated Rx Buffer

The flag is set whenever a received message has been stored

into a dedicated Rx Buffer.

0 – No Rx Buffer updated

1 – At least one received message stored into an Rx Buffer

19

DRX

TOO

R/W

0

Timeout Occurred

0 – No timeout

18

R/W

0

1 – Timeout reached

Message RAM Access Failure

The flag is set, when the Rx Handler

•

has not completed acceptance filtering or storage of an

accepted message until the arbitration field of the following

message has been received. In this case acceptance

filtering or message storage is aborted and the Rx Handler

start processing of the following message

•

was not able to write a message to the Message RAM. In

this case message storage is aborted.

In both cases the FIFO put index is not updated resp. the New

Data flag for a dedicated Rx Buffer is not set, a partly stored

message is overwritten when the next message is stored to this

location. The flag is also set when the Tx Handler was not able

to read a message from the Message RAM in time. In this case

message transmission is aborted. In case of a Tx Handler

access failure the M_CAN is switched into Restricted Operation

Mode. To leave restricted Operation Mode, the Host CPU has to

reset CCCR.ASM.

17

MRF

R/W

0

0 – No Message RAM access failure occurred

1 – Message RAM access failure occurred

Timestamp Wraparound

16

15

TSW

R/W

0

0 – No timestamp counter wrap-around

1 – Timestamp counter wrapped aroundo

Tx Event FIFO Element Lost

0 – No Tx Event FIFO element lost

1 – Tx Event FIFO element lost, also set after write attempt to

Tx Event FIFO of size zero

TEFL

Tx Event FIFO Full

14

13

12

11

10

9

TEFF

TEFW

TEFN

TFE

R/W

0

0 – Tx Event FIFO not full

1 – Tx Event FIFO full

Tx Event FIFO Watermark Reached

0 – Tx Event FIFO fill level below watermark

1 – Tx Event FIFO fill level reached watermark

Tx Event FIFO New Entry

0 – Tx Event FIFO unchanged

1 – Tx Handler wrote Tx Event FIFO element

Tx FIFO Empty

0 – Tx FIFO non-empty

1 – Tx FIFO empty

Transmission Cancellation Finished

0 – No transmission cancellation finished

1 – Transmis

TCF

Transmission Completed

0 – No transmission completed

1 – Transmission completed

TC

High Priority Message

0 – No high priority message received

1 – High priority message received

8

HPM

Rx FIFO 1 Message Lost

0 – No Rx FIFO 1 message lost

1 – Rx FIFO 1 message lost, also set after write attempt to Rx

FIFO 1 of size zero

7

6

RF1L

RF1F

R/W

0

Rx FIFO 1 Full

0 – Rx FIFO 1 not full

1 – Rx FIFO 1 full

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Table 42. Interrupt Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

Rx FIFO 1 Watermark Reached

5

RF1W

R/W

0

0 – Rx FIFO 1 fill level below watermark

1 – Rx FIFO 1 fill level reached watermark

Rx FIFO 1 New Message

4

3

RF1N

RF0L

R/W

0

0 – No new message written to Rx FIFO

1 – New message written to Rx FIFO 1

Rx FIFO 0 Message Lost

0 – No Rx FIFO 0 message lost

1 – Rx FIFO 0 message lost, also set after write attempt to Rx

FIFO 0 of size zero

Rx FIFO 0 Full

2

1

0

RF0F

RF0W

RF0N

R/W

0

0 – Rx FIFO 0 not full

1 – Rx FIFO 0 full

Rx FIFO 0 Watermark Reached

0 – Rx FIFO 0 fill level below watermark

1 – Rx FIFO 0 fill level reached watermark

Rx FIFO 0 New Message

0 – No new message written to Rx FIFO 0

1 – New message written to Rx FIFO 0

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8.6.4.19 Interrupt Enable (address = h1054) [reset = h00000000]

The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will be

signaled on an interrupt line.

•

0 – Interrupt disabled

1 – Interrupt enabled

Figure 66. Interrupt Enable Register

31

30

29

28

27

26

25

24

RSVD

R

ARAE

R/W

PEDE

R/W

PEAE

R/W

WDIE

R/W

BOE

R/W

EWE

R/W

23

22

21

20

19

18

17

16

EPE

R/W

ELOE

R/W

BEUE

R/W

BECE

R/W

DRXE

R/W

TOOE

R/W

MRAFE

R/W

TSWE

R/W

15

14

13

12

11

10

9

8

TEFLE

R/W

TEFFE

R/W

TEFW

R/W

TEFNE

R/W

TFEE

R/W

TCFE

R/W

TCE

R/W

HPME

R/W

7

6

5

4

3

2

1

0

RF1LE

R/W

RF1FE

R/W

RF1WE

R/W

RF1NE

R/W

RF0LE

R/W

RF0FE

R/W

RF0WE

R/W

RF0NE

R/W

Table 43. Interrupt Enable Field Descriptions

Bit

31:30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

Field

Type

R

Reset

0x0

0

Description

RSVD

ARAE

PEDE

PEAE

WDIE

BOE

Reserved

R/W

Access to Reserved Address Enable

Protocol Error in Data Phase Enable

Protocol Error in Arbitration Phase Enable

Watchdog Interrupt Enable

0

Bus_Off Status Interrupt Enable

Warning Status Interrupt Enable

Error Passive Interrupt Enable

EWE

0

EPE

0

ELOE

BEUE

BECE

DRXE

TOOE

MRAFE

TSWE

TEFLE

TEFFE

TEFW

TEFNE

TFEE

TCFE

TCE

0

Error Logging Overflow Interrupt Enable

Bit Error Uncorrected Interrupt Enable

Bit Error Corrected Interrupt Enable

0

Message stored to Dedicated Rx Buffer Interrupt Enable

Timeout Occurred Interrupt Enable

0

Message RAM Access Failure Interrupt Enable

Timestamp Wraparound Interrupt Enable

Tx Event FIFO Event Lost Interrupt Enable

Tx Event FIFO Full Interrupt Enable

0

Tx Event FIFO Watermark Reached Interrupt Enable

Tx Event FIFO New Entry Interrupt Enable

Tx FIFO Empty Interrupt Enable

0

Transmission Cancellation Finished Interrupt Enable

Transmission Completed Interrupt Enable

High Priority Message Interrupt Enable

Rx FIFO 1 Message Lost Interrupt Enable

Rx FIFO 1 Full Interrupt Enable

0

8

HPME

RF1LE

RF1FE

RF1WE

RF1NE

RF0LE

0

7

0

6

0

5

0

Rx FIFO 1 Watermark Reached Interrupt Enable

Rx FIFO 1 New Message Interrupt Enable

Rx FIFO 0 Message Lost Interrupt Enable

4

0

3

0

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Table 43. Interrupt Enable Field Descriptions (continued)

Bit

2

Field

Type

R/W

Reset

Description

RF0FE

RF0WE

RF0NE

0

Rx FIFO 0 Full Interrupt Enable

Rx FIFO 0 Watermark Reached Interrupt Enable

Rx FIFO 0 New Message Interrupt Enable

1

0

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8.6.4.20 Interrupt Line Select (address = h1058) [reset = h00000000]

The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt

Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be

enabled via ILE.EINT0 and ILE.EINT1.

•

0 – Interrupt assigned to interrupt line m_can_int0

1 – Interrupt assigned to interrupt line m_can_int1

Figure 67. Interrupt Line Select Register

31

30

29

28

27

26

25

24

RSVD

R

ARAL

R/W

PEDL

R/W

PEAL

R/W

WDIL

R/W

BOL

R/W

EWL

R/W

23

22

21

20

19

18

17

16

EPL

R/W

ELOL

R/W

BEUL

R/W

BECL

R/W

DRXL

R/W

TOOL

R/W

MRAFL

R/W

TSWL

R/W

15

14

13

12

11

10

9

8

TEFLL

R/W

TEFFL

R/W

TEFWL

R/W

TEFNL

R/W

TFEL

R/W

TCFL

R/W

TCL

R/W

HPML

R/W

7

6

5

4

3

2

1

0

RF1LL

R/W

RF1FL

R/W

RF1WL

R/W

RF1NL

R/W

RF0LL

R/W

RF0FL

R/W

RF0WL

R/W

RF0NL

R/W

Table 44. Interrupt Line Select Field Descriptions

Bit

31:30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

Field

Type

R

Reset

0x0

0

Description

RSVD

ARAL

PEDL

PEAL

WDIL

BOL

Reserved

R/W

Access to Reserved Address Line

Protocol Error in Data Phase Line

0

Protocol Error in Arbitration Phase Line

Watchdog Interrupt Line

0

Bus_Off Status Interrupt Line

EWL

0

Warning Status Interrupt Line

EPL

0

Error Passive Interrupt Line

ELOL

BEUL

BECL

DRXL

TOOL

MRAFL

TSWL

TEFLL

TEFFL

TEFWL

TEFNL

TFEL

0

Error Logging Overflow Interrupt Line

Bit Error Uncorrected Interrupt Line

Bit Error Corrected Interrupt Line

0

Message stored to Dedicated Rx Buffer Interrupt Line

Timeout Occurred Interrupt Line

0

Message RAM Access Failure Interrupt Line

Timestamp Wraparound Interrupt Line

Tx Event FIFO Event Lost Interrupt Line

Tx Event FIFO Full Interrupt Line

0

Tx Event FIFO Watermark Reached Interrupt Line

Tx Event FIFO New Entry Interrupt Line

Tx FIFO Empty Interrupt Line

0

TCFL

TCL

0

Transmission Cancellation Finished Interrupt Line

Transmission Completed Interrupt Line

High Priority Message Interrupt Line

Rx FIFO 1 Message Lost Interrupt Line

Rx FIFO 1 Full Interrupt Line

0

8

HPML

RF1LL

RF1FL

RF1WL

RF1NL

RF0LL

0

7

0

6

0

5

0

Rx FIFO 1 Watermark Reached Interrupt Line

Rx FIFO 1 New Message Interrupt Line

Rx FIFO 0 Message Lost Interrupt Line

4

0

3

0

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Table 44. Interrupt Line Select Field Descriptions (continued)

Bit

2

Field

Type

R/W

Reset

Description

RF0FL

RF0WL

RF0NL

0

Rx FIFO 0 Full Interrupt Line

Rx FIFO 0 Watermark Reached Interrupt Line

Rx FIFO 0 New Message Interrupt Line

1

0

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8.6.4.21 Interrupt Line Enable (address = h105C) [reset = h00000000]

Figure 68. Interrupt Line Enable Register

31

23

15

7

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

24

16

8

RSVD

R

RSVD

R

RSVD

R

1

0

RSVD

R

EINT1

R/W

EINT0

R/W

Table 45. Interrupt Line Enable Field Descriptions

Bit

Field

Type

R

Reset

0x0

Description

Reserved

31:24

23:16

15:8

7:2

RSVD

R

0x0

Reserved

R

0x0

Reserved

R

0x0

Reserved

Enable Interrupt Line 1

1

0

EINT1

EINT0

R/W

R/w

0

0 - Interrupt line m_can_int1 disabled

1 - Interrupt line m_can_int1 enabled

Enable Interrupt Line 0

0 - Interrupt line m_can_int0 disabled

1 - Interrupt line m_can_int0 enabled

93

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8.6.4.22 Reserved (address = h1060 - h107C) [reset = h00000000]

Figure 69. Reserved

31

23

15

7

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

24

16

8

RSVD

R

RSVD

R

RSVD

R

1

0

RSVD

R

Table 46. Reserved Field Descriptions

Bit

31:0

Field

Type

Reset

Description

RSVD

R

0

Reserved

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8.6.4.23 Global Filter Configuration (address = h1080) [reset = h00000000]

Figure 70. Global Filter Configuration Register

31

23

15

7

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

24

16

8

RSVD

R

RSVD

R

RSVD

R

1

0

RSVD

R

ANFS[1:0]

RP

ANFE[1:0]

RP

RRFS

RP

RRFE

RP

Table 47. Global Filter Configuration Field Descriptions

Bit

Field

Type

R

Reset

0x0

Description

Reserved

31:24

23:16

15:8

7:6

RSVD

R

0x0

R

0x0

R

0x0

Accept Non-matching Frames Standard

Defines how received messages with 11-bit IDs that do not

match any element of the filter list are treated.

00 - Accept in Rx FIFO 0

01 - Accept in Rx FIFO 1

10 - Reject

5:4

3:2

ANFS[1:0]

ANFE[1:0]

RP

0x0

11 - Reject

Accept Non-matching Frames Extended

Defines how received messages with 29-bit IDs that do not

match any element of the filter list are treated.

00 - Accept in Rx FIFO 0

01 - Accept in Rx FIFO 1

10 - Reject

11 - Reject

Reject Remote Frames Standard

1

0

RRFS

RRFE

RP

0

0 - Filter remote frames with 11-bit standard IDs

1 - Reject all remote frames with 11-bit standard IDs

Reject Remote Frames Extended

0 - Filter remote frames with 29-bit extended IDs

1 - Reject all remote frames with 29-bit extended IDs

95

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8.6.4.24 Standard ID Filter Configuration (address = h1084) [reset = h00000000]

The MRAM and start address for this register, FLSSA, has special consideration.

•

The start address must be word aligned (32-bit) in the MRAM. The 2 least significant bits are ignored on a

write to ensure this behavior.

•

When entering the MRAM start address, the 0x8000 prefix is NOT necessary. For example, if the desired

start address is 0x8634, then bits SA[15:0] will be 0x0634.

Figure 71. Standard ID Filter Configuration Register

31

23

15

7

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

24

16

8

RSVD

R

LSS[7:0]

RP

FLSSA[15:8]

RP

1

0

FLSSA[7:0]

RP

Table 48. Standard ID Filter Configuration Field Descriptions

Bit

Field

Type

Reset

Description

31:24

RSVD

R

0x0

Reserved

List Size Standard

0 - No standard Message ID filter

1-128 - Number of standard Message ID filter elements

>128 - Values greater than 128 are interpreted as 128

23:16

LSS[7:0]

RP

0x0

Filter List Standard Start Address

Start address of standard Message ID filter list

15:0

FLSSA[15:0]

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8.6.4.25 Extended ID Filter Configuration (address = h1088) [reset = h00000000]

The MRAM and start address for this register, FLSEA, has special consideration.

•

The start address must be word aligned (32-bit) in the MRAM. The 2 least significant bits are ignored on a

write to ensure this behavior.

•

When entering the MRAM start address, the 0x8000 prefix is NOT necessary. For example, if the desired

start address is 0x8634, then bits SA[15:0] will be 0x0634.

Figure 72. Extended ID Filter Configuration Register

31

30

22

14

6

29

21

13

5

28

20

12

4

27

26

18

10

2

25

17

9

24

16

8

RSVD

R

23

RSVD

R

19

LSE[6:0]

RP

15

11

FLSEA[15:8]

RP

7

3

1

0

FLSEA[7:0]

RP

Table 49. Extended ID Filter Configuration Field Descriptions

Bit

Field

Type

R

Reset

0x0

0

Description

Reserved

31:24

23

RSVD

R

List Size Extended

0 - No extended Message ID filter

1-64 - Number of extended Message ID filter elements

>64 - Values greater than 64 are interpreted as 64

22:16

15:0

LSE[6:0]

RP

0x0

Filter List Extended Start Address

Start address of extended Message ID filter list

FLSEA[15:0]

97

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8.6.4.26 Reserved (address = h108C) [reset = h00000000]

Figure 73. Reserved

31

23

15

7

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

24

16

8

RSVD

R

RSVD

R

RSVD

R

1

0

RSVD

R

Table 50. Reserved Field Descriptions

Bit

31:0

Field

Type

Reset

Description

RSVD

R

0

Reserved

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8.6.4.27 Extended ID AND Mask (address = h1090) [reset = h1FFFFFFF]

Figure 74. Extended ID AND Mask Register

31

23

15

7

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

24

16

8

RSVD

R

EIDM[28:24]

RP

EIDM[23:16]

RP

EIDM[15:8]

RP

1

0

RP-0xFF

RP

Table 51. Extended ID AND Mask Field Descriptions

Bit

Field

Type

Reset

Description

Reserved

31:30

RSVD

R

2'b00

Extended ID Mask

For acceptance filtering of extended frames the Extended ID

29:24

EIDM[28:24]

RP

6'b011111 AND Mask is ANDed with the Message ID of a received frame.

Intended for masking of 29-bit IDs in SAE J1939. With the reset

value of all bits set to one the mask is not active.

Extended ID Mask

For acceptance filtering of extended frames the Extended ID

0xFFFFFF AND Mask is ANDed with the Message ID of a received frame.

Intended for masking of 29-bit IDs in SAE J1939. With the reset

value of all bits set to one the mask is not active.

23:0

EIDM[23:16] to EIDM[7:0]

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8.6.4.28 High Priority Message Status (address = h1094) [reset = h00000000]

Figure 75. High Priority Message Status Register

31

23

30

22

14

6

29

21

13

5

28

20

12

4

27

19

26

18

10

2

25

17

9

24

16

8

RSVD

R

RSVD

R

15

FLST

R

11

FIDX[6:0]

R

7

3

1

0

MSI[1:0]

R

BIDX[5:0]

R

Table 52. High Priority Message Status Field Descriptions

Bit

Field

Type

R

Reset

0x0

Description

Reserved

Filter List

31:24

23:16

RSVD

R

0x0

Indicates the filter list of the matching filter element.

0 - Standard Filter List

1 - Extended Filter List

15

FLST

R

0x0

Filter Index

14:8

FIDX[6:0]

Index of matching filter element.

Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1.

Message Storage Indicator

00 - No FIFO selected

7:6

5:0

MSI[1:0]

R

0x0

01 - FIFO message lost

10 - Message stored in FIFO 0

11 - Message stored in FIFO 1

Buffer Index

BIDX[5:0]

Index of Rx FIFO element to which the message was stored.

Only valid when MSI[1] = ‘1’

100

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8.6.4.29 New Data 1 (address = h1098) [reset = h00000000]

Figure 76. New Data 1 Register

31

30

29

28

27

26

25

24

ND31

R/W

ND30

R/W

ND29

R/W

ND28

R/W

ND27

R/W

ND26

R/W

ND25

R/W

ND24

R/W

23

22

21

20

19

18

17

16

ND23

R/W

ND22

R/W

ND21

R/W

ND20

R/W

ND19

R/W

ND18

R/W

ND17

R/W

ND16

R/W

15

14

13

12

11

10

9

8

ND15

R/W

ND14

R/W

ND13

R/W

ND12

R/W

ND11

R/W

ND10

R/W

ND9

R/W

ND8

R/W

7

6

5

4

3

2

1

0

ND7

R/W

ND6

R/W

ND5

R/W

ND4

R/W

ND3

R/W

ND2

R/W

ND1

R/W

ND1

R/W

Table 53. New Data 1 Field Descriptions

Bit

Field

Type

Reset

Description

The register holds the New Data flags of Rx Buffers 0 to 31. The

flags are set when the respective Rx Buffer has been updated

from a received frame. The flags remain set until the Host clears

them. A flag is cleared by writing a ’1’ to the corresponding bit

position. Writing a ’0’ has no effect. A hard reset will clear the

register.

31:0

ND31 to ND0

R/W

0

0 - Rx Buffer not updated

1 - Rx Buffer updated from new message

101

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8.6.4.30 New Data 2 (address = h109C) [reset = h00000000]

Figure 77. New Data 2 Register

31

30

29

28

27

26

25

24

ND63

R/W

ND62

R/W

ND61

R/W

ND60

R/W

ND59

R/W

ND58

R/W

ND57

R/W

ND56

R/W

23

22

21

20

19

18

17

16

ND55

R/W

ND54

R/W

ND53

R/W

ND52

R/W

ND51

R/W

ND50

R/W

ND49

R/W

ND48

R/W

15

14

13

12

11

10

9

8

ND47

R/W

ND46

R/W

ND45

R/W

ND44

R/W

ND43

R/W

ND42

R/W

ND41

R/W

ND40

R/W

7

6

5

4

3

2

1

0

ND39

R/W

ND38

R/W

ND37

R/W

ND36

R/W

ND35

R/W

ND34

R/W

ND33

R/W

ND32

R/W

Table 54. New Data 2 Field Descriptions

Bit

Field

Type

Reset

Description

The register holds the New Data flags of Rx Buffers 32 to 63.

The flags are set when the respective Rx Buffer has been

updated from a received frame. The flags remain set until the

Host clears them. A flag is cleared by writing a ’1’ to the

corresponding bit position. Writing a ’0’ has no effect. A hard

reset will clear the register

31:0

ND63 to ND32

R/W

0

0 - Rx Buffer not updated

1 - Rx Buffer updated from new message

102

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8.6.4.31 Rx FIFO 0 Configuration (address = h10A0) [reset = h00000000]

The MRAM and start address for this register, F0SA, has special consideration.

•

The start address must be word aligned (32-bit) in the MRAM. The 2 least significant bits are ignored on a

write to ensure this behavior.

•

When entering the MRAM start address, the 0x8000 prefix is NOT necessary. For example, if the desired

start address is 0x8634, then bits SA[15:0] will be 0x0634.

Figure 78. Rx FIFO 0 Configuration Register

31

F0OM

RP

30

22

14

6

29

21

13

5

28

20

12

4

27

F0WM[6:0]

RP

26

18

10

2

25

17

9

24

16

8

23

RSVD

R

19

F0S[6:0]

RP

15

11

F0SA[15:8]

RP

7

3

1

0

F0SA[7:0]

RP

Table 55. Rx FIFO 0 Configuration Field Descriptions

Bit

Field

Type

Reset

Description

FIFO 0 Operation Mode

FIFO 0 can be operated in blocking or in overwrite mode

0 - FIFO 0 blocking mode

31

F0OM

RP

0

1 - FIFO 0 overwrite mode

Rx FIFO 0 Watermark

0 - Watermark interrupt disabled

1-64 - Level for Rx FIFO 0 watermark interrupt (IR.RF0W)

>64 - Watermark interrupt disabled

32:24

23

F0WM[6:0]

RSVD

RP

R

0x0

0

Reserved

Rx FIFO 0 Size

0 - No Rx FIFO 0

22:16

15:0

F0S[6:0]

RP

0x0

1-64 - Number of Rx FIFO 0 elements

>64 - Values greater than 64 are interpreted as 64

The Rx FIFO 0 elements are indexed from 0 to F0S-1

Rx FIFO 0 Start Address

Start address of Rx FIFO 0 in Message RAM

F0SA[15:0]

0x00

103

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8.6.4.32 Rx FIFO 0 Status (address = h10A4) [reset = h00000000]

Figure 79. Rx FIFO 0 Status Register

31

23

15

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

RF0L

R

24

F0F

R

RSVD

R

17

16

RSVD

R

F0PI[5:0]

R

9

8

RSVD

R

F0GI[5:0]

R

7

RSVD

R

1

0

F0FL[6:0]

R

Table 56. Rx FIFO 0 Status Field Descriptions

Bit

Field

Type

Reset

Description

31:26

RSVD

R

0x0

Reserved

Rx FIFO 0 Message Lost

This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is

reset, this bit is also reset.

0 - No Rx FIFO 0 message lost

1 - Rx FIFO 0 message lost; also set after write attempt to Rx

FIFO 0 of size zero

25

RF0L

R

0

Note: Overwriting the oldest message when RXF0C.F0OM = ‘1’

will not set this flag

Rx FIFO 0 Full

24

F0F

R

0

0 - Rx FIFO 0 not full

1 - Rx FIFO 0 full

23:22

21:16

15:14

13:8

7

RSVD

R

0x0

0

Reserved

Rx FIFO 0 Put Index

Rx FIFO 0 write index pointer, range 0 to 63

F0PI[5:0]

RSVD

Reserved

Rx FIFO 0 Get Index

Rx FIFO 0 read index pointer, range 0 to 63

F0GI[5:0]

RSVD

Reserved

Rx FIFO 0 Fill Level

Number of elements stored in Rx FIFO 0, range 0 to 64.

6:0

F0FL[6:0]

0x0

104

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8.6.4.33 Rx FIFO 0 Acknowledge (address = h10A8) [reset = h00000000]

Figure 80. Rx FIFO 0 Acknowledge Register

31

23

15

7

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

24

16

8

RSVD

R

RSVD

R

RSVD

R

1

0

RSVD

R

F0AI[5:0]

R/W

Table 57. Rx FIFO 0 Acknowledge Field Descriptions

Bit

Field

Type

R

Reset

0x0

Description

Reserved

31:24

23:16

15:8

7:6

RSVD

R

0x0

Reserved

R

0x0

Reserved

R

0x0

Reserved

Rx FIFO 0 Acknowledge Index

After the Host has read a message or a sequence of messages

from Rx FIFO 0 it has to write the buffer index of the last

element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO

0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill

Level RXF0S.F0FL.

5:0

F0AI[5:0]

R/W

0x0

105

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8.6.4.34 Rx Buffer Configuration (address = h10AC) [reset = h00000000]

Figure 81. Rx Buffer Configuration Register

31

23

30

22

29

28

27

26

25

17

24

16

RSVD

21

20

19

18

RSVD

R

15

7

14

6

13

5

12

4

11

3

10

2

9

1

8

0

RBSA[15:8]

RP

RBSA[7:0]

RP

Table 58. Rx Buffer Configuration Field Descriptions

Bit

Field

Type

R

Reset

0x0

Description

31:24

23:16

RSVD

Reserved

R

0x0

Reserved

Rx Buffer Start Address

15:0

RBSA[15:0]

RP

0x0

Configures the start address of the Rx Buffers section in the

Message RAM . Also used to reference debug messages A,B,C

106

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8.6.4.35 Rx FIFO 1 Configuration (address = h10B0) [reset = h00000000]

The MRAM and start address for this register, F1SA, has special consideration.

•

The start address must be word aligned (32-bit) in the MRAM. The 2 least significant bits are ignored on a

write to ensure this behavior.

•

When entering the MRAM start address, the 0x8000 prefix is NOT necessary. For example, if the desired

start address is 0x8634, then bits SA[15:0] will be 0x0634.

Figure 82. Rx FIFO 1 Configuration Register

31

F10M

RP

30

22

14

6

29

21

13

5

28

20

12

4

27

F1WM[6:0]

RP

26

18

10

2

25

17

9

24

16

8

23

RSVD

R

19

F1S[6:0]

RP

15

11

F1SA[15:8]

RP

7

3

1

0

F1SA[7:0]

RP

Table 59. Rx FIFO 1 Configuration Field Descriptions

Bit

Field

Type

Reset

Description

FIFO 1 Operation Mode

FIFO 1 can be operated in blocking or in overwrite mode

0 - FIFO 1 blocking mode

31

F10M

RP

0

1- FIFO 1 overwrite mode

Rx FIFO 1 Watermark

0 - Watermark interrupt disabled

1-64 - Level for Rx FIFO 1 watermark interrupt (IR.RF1W)

>64 - Watermark interrupt disabled

30:24

23

F1WM[6:0]

RSVD

RP

R

0x0

0

Reserved

Rx FIFO 1 Size

0 - No Rx FIFO 1

20:16

15:0

F1S[6:0]

RP

0x0

1-64 - Number of Rx FIFO 1 elements

>64 - Values greater than 64 are interpreted as 64

The Rx FIFO 1 elements are indexed from 0 to F1S - 1

Rx FIFO 1 Start Address

Start address of Rx FIFO 1 in Message RAM

F1SA[15:0]

107

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8.6.4.36 Rx FIFO 1 Status (address = h10B4) [reset = h00000000]

Figure 83. Rx FIFO 1 Status Register

31

23

15

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

26

18

10

2

25

RF1L

R

24

F1F

R

DMS[1:0]

R

RSVD

R

17

16

RSVD

R

F1PI[5:0]

R

9

8

RSVD

R

F1GI[5:0]

R

3

7

RSVD

R

1

0

F1FL[6:0]

R

Table 60. Rx FIFO 1 Status Field Descriptions

Bit

Field

Type

Reset

Description

Debug Message Status

00 - Idle state, wait for reception of debug messages, DMA

request is cleared

01 - Debug message A received

10 - Debug messages A, B received

11 - Debug messages A, B, C received, DMA request is set

31:30

29:26

DMS[1:0]

RSVD

R

0x0

R

0x0

Reserved

Rx FIFO 1 Message Lost

This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is

reset, this bit is also reset

0 - No Rx FIFO 1 message lost

1 - Rx FIFO 1 message lost, also set after write attempt to Rx

FIFO 1 of size zero

25

RF1L

R

0

Note: Overwriting the oldest message when RXF1C.F1OM = ‘1’

will not set this flag.

Rx FIFO 1 Full

24

F1F

R

0

0 - Rx FIFO 1 not full

1 - Rx FIFO 1 full

23:22

21:16

15:14

13:8

7

RSVD

R

0x0

0

Reserved

Rx FIFO 1 Put Index

Rx FIFO 1 write index pointer, range 0 to 63

F1PI[5:0]

RSVD

Reserved

Rx FIFO 1 Get Index

Rx FIFO 1 read index pointer, range 0 to 63.

F1GI[5:0]

RSVD

Reserved

Rx FIFO 1 Fill Level

Number of elements stored in Rx FIFO 1, range 0 to 64.

6:0

F1FL[6:0]

0x0

108

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8.6.4.37 Rx FIFO 1 Acknowledge (address = h10B8) [reset = h00000000]

Figure 84. Rx FIFO 1 Acknowledge Register

31

23

15

7

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

24

16

8

RSVD

R

RSVD

R

RSVD

R

1

0

RSVD

R

F1AI[5:0]

R/W

Table 61. Rx FIFO 1 Acknowledge Field Descriptions

Bit

Field

Type

R

Reset

0x0

Description

Reserved

31:24

23:16

15:8

7:6

RSVD

R

0x0

Reserved

R

0x0

Reserved

R

0x0

Reserved

Rx FIFO 1 Acknowledge Index

After the Host has read a message or a sequence of messages

from Rx FIFO 1 it has to write the buffer index of the last

element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO

1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill

Level RXF1S.F1FL.

5:0

F1AI[5:0]

R/W

0x0

109

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8.6.4.38 Rx Buffer/FIFO Element Size Configuration (address = h10BC) [reset = h00000000]

Figure 85. Rx Buffer/FIFO Element Size Configuration Register

31

23

15

30

22

14

6

29

21

28

20

12

4

27

19

11

26

18

10

2

25

17

24

16

8

RSVD

R

RSVD

R

13

RSVD

R

9

RBDS[2:0]

RP

7

RSVD

R

5

3

RSVD

R

1

0

F1DS[2:0]

RP

F0DS[2:0]

RP

Table 62. Rx Buffer/FIFO Element Size Configuration Field Descriptions

Bit

Field

Type

R

Reset

0x0

Description

Reserved

31:24

RSVD

R

0x0

R

0x0

Rx Buffer Data Field Size

000 - 8 byte data field

001 - 12 byte data field

010 - 16 byte data field

011 - 20 byte data field

100 - 24 byte data field

101 - 32 byte data field

110 - 48 byte data field

111 - 64 byte data field

10:8

RBDS[2:0]

RSVD

RP

R

0x0

0

7

Reserved

Rx FIFO 1 Data Field Size

000 - 8 byte data field

001 - 12 byte data field

010 - 16 byte data field

011 - 20 byte data field

100 - 24 byte data field

101 - 32 byte data field

110 - 48 byte data field

111 - 64 byte data field

6:4

3

F1DS[2:0]

RSVD

RP

R

0x0

0

Reserved

Rx FIFO 0 Data Field Size

000 - 8 byte data field

001 - 12 byte data field

010 - 16 byte data field

011 - 20 byte data field

100 - 24 byte data field

101 - 32 byte data field

110 - 48 byte data field

111 - 64 byte data field

2:0

F0DS[2:0]

RP

0x0

110

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8.6.4.39 Tx Buffer Configuration (address = h10C0) [reset = h00000000]

The MRAM and start address for this register, TBSA, has special consideration.

•

The start address must be word aligned (32-bit) in the MRAM. The 2 least significant bits are ignored on a

write to ensure this behavior.

•

When entering the MRAM start address, the 0x8000 prefix is NOT necessary. For example, if the desired

start address is 0x8634, then bits SA[15:0] will be 0x0634.

Figure 86. Tx Buffer Configuration Register

31

RSVD

R

30

TFQM

RP

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

24

16

8

TFQS[5:0]

RP

23

15

7

22

14

6

RSVD

R

NDTB[5:0]

RP

TBSA[15:8]

RP

1

0

TBSA[7:0]

RP

Table 63. Tx Buffer Configuration Field Descriptions

Bit

Field

Type

Reset

Description

31

RSVD

R

0

Reserved

Tx FIFO/Queue Mode

0 - Tx FIFO operation

1 - Tx Queue operation

30

TFQM

RP

0

Transmit FIFO/Queue Size

0 - No Tx FIFO/Queue

1-32 - Number of Tx Buffers used for Tx FIFO/Queue

>32 - Values greater than 32 are interpreted as 32

29:24

23:22

21:16

TFQS[5:0]

RSVD

RP

R

0x0

Reserved

Number of Dedicated Transmit Buffers

0 - No Dedicated Tx Buffers

1-32 - Number of Dedicated Tx Buffers

>32 - Values greater than 32 are interpreted as 32

NDTB[5:0]

RP

Tx Buffers Start Address

Start address of Tx Buffers section in Message RAM

Note: Be aware that the sum of TFQS and NDTB may be not

greater than 32. There is no check for erroneous configurations.

The Tx Buffers section in the Message RAM starts with the

dedicated Tx Buffers.

15:0

TBSA[15:0]

RP

0x0

111

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8.6.4.40 Tx FIFO/Queue Status (address = h10C4) [reset = h00000000]

Figure 87. Tx FIFO/Queue Status Register

31

23

15

7

30

22

29

28

20

12

4

27

19

11

3

26

25

17

9

24

16

8

RSVD

R

21

TFQF

R

18

TFQPI[4:0]

R

RSVD

R

14

RSVD

R

13

10

TFGI[4:0]

R

6

5

2

1

0

RSVD

R

TFFL[5:0]

R

Table 64. Tx FIFO/Queue Status Field Descriptions

Bit

Field

Type

R

Reset

0x0

Description

Reserved

31:24

23:22

RSVD

R

0x0

Tx FIFO/Queue Full

21

TFQF

R

0

0 - Tx FIFO/Queue not full

1 - Tx FIFO/Queue full

Tx FIFO/Queue Put Index

Tx FIFO/Queue write index pointer, range 0 to 31.

20:16

15:13

TFQPI[4:0]

RSVD

R

0x0

Reserved

Tx FIFO Get Index

12:8

7:6

TFGI[4:0]

RSVD

R

0x0

Tx FIFO read index pointer, range 0 to 31. Read as zero when

Tx Queue operation is configured (TXBC.TFQM = ‘1’).

Reserved

Tx FIFO Free Level

Number of consecutive free Tx FIFO elements starting from

TFGI, range 0 to 32. Read as zero when Tx Queue operation is

configured (TXBC.TFQM = ‘1’)

Note: In case of mixed configurations where dedicated Tx

Buffers are combined with a Tx FIFO or a Tx Queue, the Put

and Get Indices indicate the number of the Tx Buffer starting

with the first dedicated Tx Buffers

5:0

TFFL[5:0]

R

0x0

Example: For a configuration of 12 dedicated Tx Buffers and a

Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth

buffer of the Tx FIFO

112

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8.6.4.41 Tx Buffer Element Size Configuration (address = h10C8) [reset = h00000000]

Figure 88. Tx Buffer Element Size Configuration Register

31

23

15

7

30

22

14

6

29

21

13

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

24

16

8

RSVD

R

RSVD

R

RSVD

R

5

RSVD

R

1

0

TBDS[2:0]

RP

Table 65. Tx Buffer Element Size Configuration Field Descriptions

Bit

Field

Type

R

Reset

0x0

Description

Reserved

31:24

23:16

15:8

7:3

RSVD

R

0x0

R

0x0

R

0x0

Tx Buffer Data Field Size

000 - 8 byte data field

001 - 12 byte data field

010 - 16 byte data field

011 - 20 byte data field

100 - 24 byte data field

101 - 32 byte data field

110 - 48 byte data field

111 - 64 byte data field

2:0

TBDS[2:0]

RP

0x0

Note: In case the data length code DLC of a Tx Buffer element

is configured to a value higher than the Tx Buffer data field size

TXESC.TBDS, the bytes not defined by the Tx Buffer are

transmitted as “0xCC” (padding bytes).

113

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8.6.4.42 Tx Buffer Request Pending (address = h10CC) [reset = h00000000]

Figure 89. Tx Buffer Request Pending Register

31

TRP31

R

30

TRP30

R

29

TRP29

R

28

TRP28

R

27

TRP27

R

26

TRP26

R

25

TRP22

R

24

TRP24

R

23

TRP23

R

22

TRP22

R

21

TRP21

R

20

TRP20

R

19

TRP19

R

18

TRP18

R

17

TRP17

R

16

TRP16

R

15

TRP15

R

14

TRP14

R

13

TRP13

R

12

TRP12

R

11

TRP11

R

10

TRP10

R

9

TRP9

R

8

TRP8

R

7

TRP7

R

6

TRP6

R

5

TRP5

R

4

TRP4

R

3

TRP3

R

2

TRP2

R

1

TRP1

R

0

TRP0

R

Table 66. Tx Buffer Request Pending Field Descriptions

Bit

Field

Type

Reset

Description

Transmission Request Pending

Each Tx Buffer has its own Transmission Request Pending bit.

The bits are set via register TXBAR.

The bits are reset after a requested transmission has completed

or has been cancelled via register TXBCR. TXBRP bits are set

only for those Tx Buffers configured via TXBC. After a TXBRP

bit has been set, a Tx scan is started to check for the pending

Tx request with the highest priority (Tx Buffer with lowest

Message ID).

A cancellation request resets the corresponding transmission

request pending bit of register TXBRP. In case a transmission

has already been started when a cancellation is requested, this

is done at the end of the transmission, regardless whether the

transmission was successful or not. The cancellation request

bits are reset directly after the corresponding TXBRP bit has

been reset.

After a cancellation has been requested, a finished cancellation

is signaled via TXBCF

31:0

TRP31 to TRP0

R

0

•

after

successful

transmission

together

with

the

corresponding TXBTO bit

when the transmission has not yet been started at the point

of cancellation

when the transmission has been aborted due to lost

arbitration

when an error occurred during frame transmission

In DAR mode all transmissions are automatically cancelled if

they are not successful. The corresponding TXBCF bit is set for

all unsuccessful transmissions.

0 - No transmission request pending

1- Transmission request pending

Note: TXBRP bits which are set while a Tx scan is in progress

are not considered during this particular Tx scan. In case a

cancellation is requested for such a Tx Buffer, this Add Request

is cancelled immediately, the corresponding TXBRP bit is reset.

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8.6.4.43 Tx Buffer Add Request (address = h10D0) [reset = h00000000]

Figure 90. Tx Buffer Add Request Register

31

30

29

28

27

26

25

24

AR31

R/W

AR30

R/W

AR29

R/W

AR28

R/W

AR27

R/W

AR26

R/W

AR25

R/W

AR24

R/W

23

22

21

20

19

18

17

16

AR23

R/W

AR22

R/W

AR21

R/W

AR20

R/W

AR19

R/W

AR18

R/W

AR17

R/W

AR16

R/W

15

14

13

12

11

10

9

8

AR14

R/W

AR14

R/W

AR13

R/W

AR12

R/W

AR11

R/W

AR10

R/W

AR9

R/W

AR8

R/W

7

6

5

4

3

2

1

0

AR7

R/W

AR6

R/W

AR5

R/W

AR4

R/W

AR3

R/W

AR2

R/W

AR1

R/W

AR0

R/W

Table 67. Tx Buffer Add Request Field Descriptions

Bit

Field

Type

Reset

Description

Add Request

Each Tx Buffer has its own Add Request bit. Writing a ‘1’ will set

the corresponding Add Request bit; writing a ‘0’ has no impact.

This enables the Host to set transmission requests for multiple

Tx Buffers with one write to TXBAR. TXBAR bits are set only for

those Tx Buffers configured via TXBC. When no Tx scan is

running, the bits are reset immediately, else the bits remain set

until the Tx scan process has completed.

31:0

AR31 to AR0

R/W

0

0 - No transmission request added

1 - Transmission requested added

Note: If an add request is applied for a Tx Buffer with pending

transmission request (corresponding TXBRP bit already set),

this add request is ignored.

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8.6.4.43.1 Tx Buffer Cancellation Request (address = h10D4 [reset = h00000000]

Figure 91. Tx Buffer Cancellation Request Register

31

30

29

28

27

26

25

24

CR31

R/W

CR30

R/W

CR29

R/W

CR28

R/W

CR27

R/W

CR26

R/W

CR25

R/W

CR24

R/W

23

22

21

20

19

18

17

16

CR23

R/W

CR22

R/W

CR21

R/W

CR20

R/W

CR19

R/W

CR18

R/W

CR17

R/W

CR16

R/W

15

14

13

12

11

10

9

8

CR15

R/W

CR14

R/W

CR13

R/W

CR12

R/W

CR11

R/W

CR10

R/W

CR9

R/W

CR8

R/W

7

6

5

4

3

2

1

0

CR7

R/W

CR6

R/W

CR5

R/W

CR4

R/W

CR3

R/W

CR2

R/W

CR1

R/W

CR0

R/W

Table 68. Tx Buffer Cancellation Request Field Descriptions

Bit

Field

Type

Reset

Description

Cancellation Request

Each Tx Buffer has its own Cancellation Request bit. Writing a

‘1’ will set the corresponding Cancellation Request bit; writing a

‘0’ has no impact. This enables the Host to set cancellation

requests for multiple Tx Buffers with one write to TXBCR.

TXBCR bits are set only for those Tx Buffers configured via

TXBC. The bits remain set until the corresponding bit of TXBRP

is reset.

31:0

CR31 to CR0

R/W

0

0 - No cancellation pending

1 - Cancellation pending

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8.6.4.43.2 Tx Buffer Add Request Transmission Occurred (address = h10D8) [reset = h00000000]

Figure 92. Tx Buffer Add Request Transmission Occurred Register

31

TO31

R

30

TO30

R

29

TO29

R

28

TO28

R

27

TO27

R

26

TO26

R

25

TO25

R

24

TO24

R

23

TO23

R

22

TO22

R

21

TO21

R

20

TO20

R

19

TO19

R

18

TO18

R

17

TO17

R

16

TO16

R

15

TO15

R

14

TO14

R

13

TO13

R

12

TO12

R

11

TO11

R

10

TO10

R

9

TO9

R

8

TO8

R

7

TO7

R

6

TO6

R

5

TO5

R

4

TO4

R

3

TO3

R

2

TO2

R

1

TO1

R

0

TO0

R

Table 69. Tx Buffer Add Request Transmission Occurred Field Descriptions

Bit

Field

Type

Reset

Description

Transmission Occurred

Each Tx Buffer has its own Transmission Occurred bit. The bits

are set when the corresponding TXBRP bit is cleared after a

successful transmission. The bits are reset when a new

transmission is requested by writing a ‘1’ to the corresponding

bit of register TXBAR.

31:0

TO31 to TO0

R

0

0 - No transmission occurred

1 - Transmission occurred

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8.6.4.43.3 Tx Buffer Cancellation Finished (address = h10DC) [reset = h00000000]

Figure 93. Tx Buffer Cancellation Finished Register

31

CF31

R

30

CF30

R

29

CF29

R

28

CF28

R

27

CF27

R

26

CF26

R

25

CF25

R

24

CF24

R

23

CF23

R

22

CF22

R

21

CF21

R

20

CF20

R

19

CF19

R

18

CF18

R

17

CF17

R

16

CF16

R

15

CF15

R

14

CF14

R

13

CF13

R

12

CF12

R

11

CF11

R

10

CF10

R

9

CF9

R

8

CF8

R

7

CF7

R

6

CF6

R

5

CF5

R

4

CF4

R

3

CF3

R

2

CF2

R

1

CF1

R

0

CF0

R

Table 70. Tx Buffer Cancellation Finished Field Descriptions

Bit

Field

Type

Reset

Description

Cancellation Finished

Each Tx Buffer has its own Cancellation Finished bit. The bits

are set when the corresponding TXBRP bit is cleared after a

cancellation was requested via TXBCR. In case the

corresponding TXBRP bit was not set at the point of

cancellation, CF is set immediately. The bits are reset when a

new transmission is requested by writing a ‘1’ to the

corresponding bit of register TXBAR.

31:0

CF31 to CF0

R

0

0 - No transmit buffer cancellation

1 - Transmit buffer cancellation finished

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8.6.4.43.4 Tx Buffer Transmission Interrupt Enable (address = h10E0) [reset = h00000000]

Figure 94. Tx Buffer Transmission Interrupt Enable Register

31

30

29

28

27

26

25

24

TIE31

R/W

TIE30

R/W

TIE29

R/W

TIE28

R/W

TIE27

R/W

TIE26

R/W

TIE25

R/W

TIE24

R/W

23

22

21

20

19

18

17

16

TIE23

R/W

TIE22

R/W

TIE21

R/W

TIE20

R/W

TIE19

R/W

TIE18

R/W

TIE17

R/W

TIE16

R/W

15

14

13

12

11

10

9

8

TIE15

R/W

TIE14

R/W

TIE13

R/W

TIE12

R/W

TIE11

R/W

TIE10

R/W

TIE9

R/W

TIE8

R/W

7

6

5

4

3

2

1

0

TIE7

R/W

TIE6

R/W

TIE5

R/W

TIE4

R/W

TIE3

R/W

TIE2

R/W

TIE1

R/W

TIE0

R/W

Table 71. Tx Buffer Transmission Interrupt Enable Field Descriptions

Bit

Field

Type

Reset

Description

Transmission Interrupt Enable

Each Tx Buffer has its own Transmission Interrupt Enable bit.

0 - Transmission interrupt disabled

TIE31 to TIE0

R/W

0

1 - Transmission interrupt enable

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8.6.4.43.5 Tx Buffer Cancellation Finished Interrupt Enable (address = h10E4) [reset = h00000000]

Figure 95. Tx Buffer Cancellation Finished Interrupt Enable Register

31

30

29

28

27

26

25

24

CFIE31

R/W

CFIE30

R/W

CFIE29

R/W

CFIE28

R/W

CFIE27

R/W

CFIE26

R/W

CFIE25

R/W

CFIE24

R/W

23

22

21

20

19

18

17

16

CFIE23

R/W

CFIE22

R/W

CFIE21

R/W

CFIE20

R/W

CFIE19

R/W

CFIE18

R/W

CFIE17

R/W

CFIE16

R/W

15

14

13

12

11

10

9

8

CFIE15

R/W

CFIE14

R/W

CFIE13

R/W

CFIE12

R/W

CFIE11

R/W

CFIE10

R/W

CFIE9

R/W

CFIE8

R/W

7

6

5

4

3

2

1

0

CFIE7

R/W

CFIE6

R/W

CFIE5

R/W

CFIE4

R/W

CFIE3

R/W

CFIE2

R/W

CFIE1

R/W

CFIE0

R/W

Table 72. Tx Buffer Cancellation Finished Interrupt Enable Field Descriptions

Bit

Field

Type

Reset

Description

Bit 31:0 CFIE[31:0]: Cancellation Finished Interrupt Enable

Each Tx Buffer has its own Cancellation Finished Interrupt

Enable bit.

31:0

CFIE31 to CFIE0

RW

0

0 - Cancellation finished interrupt disabled

1 - Cancellation finished interrupt enabled

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8.6.4.43.6 Reserved (address = h10E8) [reset = h00000000]

Figure 96. Reserved

31

23

15

7

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

24

16

8

RSVD

R

RSVD

R

RSVD

R

1

0

RSVD

R

Table 73. Reserved Field Descriptions

Bit

31:0

Field

Type

Reset

Description

RSVD

R

0

Reserved

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8.6.4.43.7 Reserved (address = h10EC) [reset = h00000000]

Figure 97. Reserved

31

23

15

7

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

24

16

8

RSVD

R

RSVD

R

RSVD

R

1

0

RSVD

R

Table 74. Reserved Field Descriptions

Bit

31:0

Field

Type

Reset

Description

RSVD

R

0

Reserved

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8.6.4.43.8 Tx Event FIFO Configuration (address = h10F0) [reset = h00000000]

The MRAM and start address for this register, EFSA, has special consideration.

•

The start address must be word aligned (32-bit) in the MRAM. The 2 least significant bits are ignored on a

write to ensure this behavior.

•

When entering the MRAM start address, the 0x8000 prefix is NOT necessary. For example, if the desired

start address is 0x8634, then bits SA[15:0] will be 0x0634.

Figure 98. Tx Event FIFO Configuration Register

31

23

15

7

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

24

16

8

RSVD

R

EFWM[5:0]

RP

RSVD

R

EFS[5:0]

RP

EFSA[15:8]

RP

1

0

EFSA[7:0]

RP

Table 75. Tx Event FIFO Configuration Field Descriptions

Bit

Field

Type

Reset

Description

31:30

29:24

23:22

RSVD

R

0x0

Reserved

Event FIFO Watermark

0 - Watermark interrupt disabled

1-32 - Level for Tx Event FIFO watermark interrupt (IR.TEFW)

>32 - Watermark interrupt disabled

EFWM[5:0]

RSVD

RP

R

0x0

Reserved

Event FIFO Size

0 - Tx Event FIFO disabled

21:16

15:0

EFS[5:0]

RP

0x0

1-32 - Number of Tx Event FIFO elements

>32 - Values greater than 32 are interpreted as 32

The Tx Event FIFO elements are indexed from 0 to EFS - 1

Event FIFO Start Address

Start address of Tx Event FIFO in Message RAM

EFSA[15:0]

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8.6.4.43.9 Tx Event FIFO Status (address = h10F4) [reset = h00000000]

Figure 99. Tx Event FIFO Status Register

31

23

15

7

30

29

21

13

5

28

20

12

4

27

19

11

3

26

25

TEFL

R

24

EFF

R

RSVD

R

22

RSVD

R

18

EFPI[4:0]

R

17

16

14

RSVD

R

10

REFGI[4:0]

R

9

8

6

2

1

0

RSVD

R

EFFL[5:0]

R

Table 76. Tx Event FIFO Status Field Descriptions

Bit

Field

Type

Reset

Description

31:26

RSVD

R

0x0

Reserved

Tx Event FIFO Element Lost

This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is

reset, this bit is also reset.

0 - No Tx Event FIFO element lost

1 - Tx Event FIFO element lost, also set after write attempt to Tx

Event FIFO of size zero.

25

TEFL

EFF

R

0

Event FIFO Full

0 - Tx Event FIFO not full

1 - Tx Event FIFO full

24

R

0

23:21

20:16

15:13

12:8

7:6

RSVD

R

0x0

Reserved

Event FIFO Put Index

Tx Event FIFO write index pointer, range 0 to 31.

EFPI[4:0]

RSVD

Reserved

Event FIFO Get Index

Tx Event FIFO read index pointer, range 0 to 31.

REFGI[4:0]

RSVD

Reserved

Event FIFO Fill Level

Number of elements stored in Tx Event FIFO, range 0 to 32

5:0

EFFL[5:0]

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8.6.4.43.10 Tx Event FIFO Acknowledge (address = h10F8) [reset = h00000000]

Figure 100. Tx Event FIFO Acknowledge Register

31

23

15

7

30

22

14

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

25

17

9

24

16

8

RSVD

R

RSVD

R

RSVD

R

6

RSVD

R

2

1

0

EFAI[4:0]

R/W

Table 77. Tx Event FIFO Acknowledge Field Descriptions

Bit

Field

Type

R

Reset

0x0

Description

31:24

23:16

15:18

7:5

RSVD

Reserved

R

0x0

Reserved

R

0x0

Reserved

R

0x0

Reserved

Event FIFO Acknowledge Index

After the Host has read an element or a sequence of elements

from the Tx Event FIFO it has to write the index of the last

element read from Tx Event FIFO to EFAI. This will set the Tx

Event FIFO Get Index TXEFS.EFGI to EFAI + 1 and update the

Event FIFO Fill Level TXEFS.EFFL.

4:0

EFAI[4:0]

E/W

0x0

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8.6.4.43.11 Reserved (address = h10FC) [reset = h00000000]

Figure 101. Reserved

31

23

15

7

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

24

16

8

RSVD

R

RSVD

R

RSVD

R

1

0

RSVD

R

Table 78. Reserved Field Descriptions

Bit

31:0

Field

Type

Reset

Description

RSVD

R

0

Reserved

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9 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Design Consideration

9.1.1 Crystal and Clock Input Requirements

Selecting the crystal or clock input depends upon system implementation. To support 2 and 5 Mbps CAN FD the

clock in or crystal needs to have 0.5% frequency accuracy. The minimum value of 20 MHz is needed to support

CAN FD with a rate of 2 Mbps. The recommended value for CLKIN or crystal is 40 MHz to meet CAN FD rates

up to 5 Mbps data rates in order to support higher data throughout. If a crystal is used see the manufacturer’s

documentation on proper biasing.

注

The TCAN4550 was evaluated with the NX2016SA 20MHz and 40MHz crystals

9.1.2 Bus Loading, Length and Number of Nodes

A typical CAN application can have a maximum bus length of 40 m and maximum stub length of 0.3 m. However,

with careful design, users can have longer cables, longer stub lengths, and many more nodes to a bus. A high

number of nodes require a transceiver with high input impedance such as this transceiver family.

Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO

11898-2:2016 standard. They made system level trade off decisions for data rate, cable length, and parasitic

loading of the bus. Examples of these CAN systems level specifications are ARINC825, CANopen, DeviceNet,

SAE J2284, SAE J1939, and NMEA200.

A CAN system design is a series of tradeoffs. In ISO 11898-2:2016 the driver differential output is specified with

a bus load that can range from 50 Ω to 65 Ω where the differential output must be greater than 1.5 V. The

TCAN4550 is specified to meet the 1.5 V requirement with a across this load range and is specified to meet 1.4

V differential output at 45 Ω bus load. The differential input resistance of this family of transceiver is a minimum

of 30kΩ. If 167 of these transceivers are in parallel on a bus, this is equivalent to an 180 Ω differential load in

parallel with the 60 Ω from termination gives a total bus load of 45 Ω. Therefore, this family theoretically supports

over 167 transceivers on a single bus segment with margin to the 1.2 V minimum differential input voltage

requirement at each receiving node. However for CAN network design margin must be given for signal loss

across the system and cabling, parasitic loadings, timing, network imbalances, ground offsets and signal integrity

thus a practical maximum number of nodes is much lower. Bus length may also be extended beyond the original

ISO 11898-2:2016 standard of 40 m by careful system design and data rate tradeoffs. For example CANopen

network design guidelines allow the network to be up to 1km with changes in the termination resistance, cabling,

less than 64 nodes and significantly lowered data rate.

This flexibility in CAN network design is one of its key strengths allowing for these system level network

extensions and additional standards to build on the original ISO 11898-2 CAN standard. However, when using

this flexibility the CAN network system designer must take the responsibility of good network design to ensure

robust network operation.

9.1.3 CAN Termination

The standard CAN bus interconnection to be a single twisted pair cable (shielded or unshielded) with 120 Ω

characteristic impedance (ZO).

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Application Design Consideration (接下页)

9.1.3.1 Termination

Resistors equal to the characteristic impedance of the line should be used to terminate both ends of the cable to

prevent signal reflections. Unterminated drop-lines (stubs) connecting nodes to the bus should be kept as short

as possible to minimize signal reflections. The termination may be in a node but is generally not recommended,

especially if the node may be removed from the bus. Termination must be carefully placed so that it is not

removed from the bus. System level CAN implementations such as CANopen allow for different termination and

cabling concepts for example to add cable length.

Node 2

Node 3

Node n

(with termination)

MCU or DSP

Node 1

MCU or DSP

CAN

Controller

CAN

Controller

MCU or DSP

TCAN4550

R_TERM

TCAN4550

TCAN1051/G

TCAN1042/G

R_TERM

图 102. Typical CAN Bus

Termination may be a single 120 Ω resistor at each end of the bus, either on the cable or in a terminating node.

If filtering and stabilization of the common mode voltage of the bus is desired then “split termination” may be

used, see 图 103. Split termination improves the electromagnetic emissions behavior of the network by

eliminating fluctuations in the bus common mode voltage levels at the start and end of message transmissions.

Split Termination

Standard Termination

CANH

R_TERM/2

CAN

Transceiver

CAN

Transceiver

R_TERM

C_SPLIT

R_TERM/2

CANL

图 103. CAN Bus Termination Concepts

9.1.3.2 CAN Bus Biasing

Bus biasing can be normal biasing, active in normal mode and inactive in low-power mode. Automatic voltage

biasing is where the bus is active in normal mode but is controlled by the voltage between CANH and CANL in

lower power modes. See Figure 图 104 for the state diagram on how the TCAN4550 performs automatic biasing.

Figure 图 105 provides the bus biasing based upon the mode of operation.

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Application Design Consideration (接下页)

Recessive state > t_WK-FILTER

Wait

Bus Biasing Inactive

Power On

Dominant state > t_WK-FILTER

t_{WK_TIMEOUT}

1

Bus Biasing Inactive

Recessive state > t_WK-FILTER

t_{WK_TIMEOUT}

2

Bus Biasing Inactive

Dominant state > t_WK-FILTER

On implementation

enters Normal Mode

t_SILENCEexpired and implementation

In low power mode

3

Bus Biasing Active

From all other nodes

Low Power Mode:

Dominant state > t_WK-FILTER

Normal Mode: Dominant state

Low Power Mode:

Recessive state > t_WK-FILTER

Normal Mode: Recessive state

t_SILENCEexpired and implementation

In low power mode

4

Bus Biasing

Active

图 104. Automatic bus biasing state diagram

129

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Application Design Consideration (接下页)

Power Up &

Reset

Prog to

Sleep

Prog to

Normal

Sleep Mode

Bus Bias: GND

Standby Mode

Bus Bias: GND

Normal Mode

Bus Bias: 2.5 V

Fail-Safe

WAKE Pin

Prog to

Sleep

Prog to

Standby or

Fault

Yes

t_SILENCE

Expired

Yes

t_SILENCE

Expired

No

t_SILENCE

Expired

WAKE

Standby Mode

Bus Bias: 2.5 V

Sleep Mode

Bus Bias: 2.5 V

WUP

t_SILENCE

Expired

图 105. Bus Biasing Based on Modes of Operation

9.1.4 INH Brownout Behavior

A brownout condition takes place when V_SUPramps down below the minimum recommended operation

conditions and then ramps back above the recommended operating conditions. 图 106 provides the behavior of

the INH pin based upon process, voltage and temperature during this condition. Once V_SUPdrops below the

digital core going into reset, the device will have to be reprogrammed as all registers will be set back to default.

~ 5.5 V

UV_SUPrise

V_SUP

Digital core out

of reset

UV_SUPfall

~ 4.7 V

~ 3.6 V

~ 4.25 V

Digital core into reset

1.67 V > INH on > 4.15 V

1.42 V < INH off < 3.14 V

INH

图 106. INH Brownout Behavior

130

TCAN4550

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9.2 Typical Application

The TCAN4550 is typically used in applications with a host microprocessor or FPGA that does not include the

link layer portion of the CAN protocol. Below is a typical application configuration for 3.3 V microprocessor

applications.

3 kꢀ

10 µF

10 nF

33 kꢀ

V_BAT

330 nF

10 µF

100 nF

EN

V_IN

V_SUP

WAKE

FLTR

V_CCOUT

Voltage

Regulator

(e.g.

INH

V_INT

V_LVRX

V_IO

TPSxxxx)

LDO(s)

Filter

V_OUT

Under

Voltage

CNTL

POR

TCAN4550

V_IO

100 nF

10 µF

CANH

V_CCINT1

TXD_INT

V_CCINT2

V_LVRXfor LP

RX

V_INT

V_CC

nWKRQ

TX/RX Data

Buffer

GPIO3

TX/RX CAN-FD

Controller with

Filters

V_IO

2-wire

CAN

bus

RST

SCLK

SDI

Reset

SCLK

RXD_INT

CAN-FD

Transceiver

SPI slave,

System

Controller

MOSI

MISO

SDO

MCU

CANL

nCS

GPIO2

GPIO1

GPIO

GPO2

nINT

GPIO1

Optional:

Terminating

Node

Optional:

Filtering,

GND

OSC1

OSC2

Transient and

ESD

40 MHz

图 107. Typical CAN Applications for TCAN4550 for 3.3 V µC and Crystal

Note: Add decoupling capacitors as needed.

131

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Typical Application (接下页)

3 kꢀ

10 µF

10 nF

33 kꢀ

V_BAT

330 nF

10 µF

100 nF

EN

V_IN

V_SUP

WAKE

FLTR

V_CCOUT

Voltage

Regulator

(e.g.

INH

V_INT

V_LVRX

V_IO

TPSxxxx)

LDO(s)

Filter

V_OUT

Under

Voltage

CNTL

POR

V_IO

TCAN4550

100 nF

10 µF

CANH

V_CCINT1

TXD_INT

V_CCINT2

V_LVRXfor LP

RX

V_INT

nWKRQ

TX/RX Data

Buffer

GPIO3

V_CC

TX/RX CAN-FD

Controller with

Filters

V_IO

2-wire

CAN

bus

RST

SCLK

SDI

Reset

SCLK

RXD_INT

CAN-FD

Transceiver

SPI slave,

System

Controller

MOSI

MISO

SDO

MCU

CANL

nCS

GPIO2

GPIO1

GPIO

GPO2

nINT

GPIO1

Optional:

Terminating

Node

Optional:

Filtering,

GND

OSC1

OSC2

Transient and

ESD

20 MHz

OSC1

OSC2

图 108. Typical CAN Applications for TCAN4550 for 3.3 V µC; Clock from MCU

9.2.1 Detailed Requirements

The TCAN4550 works with 3.3 V and 5 V microprocessors when using the V_IOpin from the microprocessor

voltage regulator. The bus termination is shown for illustrative purposes.

9.2.2 Detailed Design Procedures

The TCAN4550 is designed to work in application using the ISO 11898 standard supporting bus loads from 50 Ω

to 65 Ω. As the TCAN4550 supports CAN FD data rates up to 8 Mbps it is recommended to use a 40 MHz

crystal and keep trace lengths matched and short as feasible between the processor and device. As the CAN

stub length are defined in the standard it is recommended to design the system according to these. As the

TCAN4550 CAN transceiver is self-powered but also allows for up to 70 mA at 5 V to be sourced on V_CCOUT, the

system design needs to account for the CAN transceiver requirements when determining the load the LDO is to

support. With this and the high temperature and input voltage range it is recommended to use a high-k board

using proper thermal dissipation methods to ensure the highest performance.

132

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Typical Application (接下页)

9.2.3 Application Curves

54

53.7

53.4

53.1

52.8

52.5

52.2

51.9

51.6

51.3

51

125

120

115

110

105

100

95

-40 °C

25 °C

55 °C

85 °C

100 °C

125 °C

-40 °C

25 °C

55 °C

85 °C

100 °C

125 °C

90

85

80

75

70

65

60

55

50

50.7

45

6

8

10

12

14

16

18

20

22

24

D002

6

8

10

12

14

16

18

20

22

24

D004

V_SUP(V)

V_CCOUT= Off

CAN Bus State =

Dominant

CAN Bus Load =

I_CCOUT= 70 mA

CAN Bus State =

Dominant

CAN Bus Load =

60 Ω

图 109. I_SUPAcross V_SUPand Temperature

图 110. I_SUPAcross V_SUP, Temperature and V_CCOUTwith

Maximum Load Current

9.2.4 Application Curves

图 111 and 图 112 shows the behavior of the 5 V LDO in relationship to I_SUP, V_SUP, LDO load of 70 mA, CAN bus

dominant and ambient temperature. The I_SUPcurrent is based upon a 70 mA load on V_CCOUTand the CAN bus

held dominant for about a total of 120 mA. As can be seen, an ambient temperature of 125°C can cause a

thermal shut down event when V_SUPreaches 20 V and V_CCOUTis providing 70 mA to a load. The load on the

CAN bus is 60 Ω. When the CAN bus load is 50 Ω a VSUP of 19 V and ambient temperature of 125 can trigger a

thermal shut down event. The reason the curve shows I_SUPleveling out to approximately 74.5 mA is due to

thermal shut down where the device shuts off the LDO and CAN transceiver. The device cools below TSD

leaving thermal shutdown quickly. When the TSD event goes away the device then enters standby mode, turning

on the LDO. The 74.5 mA is the 70 mA LDO load and a dominant on the CAN bus in standby mode. This is

happening quickly enough that LDO shut off is not seen. If the TSD event is prolonged the current would drop to

micro-amps and V_CCOUTwould be 0 V once the decoupling capacitor discharges.

140

120

100

80

5.5

5

4.5

4

3.5

3

2.5

2

60

40

1.5

1

-40°C

25°C

55°C

85°C

105°C

125°C

-40°C

25°C

55°C

85°C

105°C

125°C

20

0.5

0

3

6

9

12

15

V_SUP(V)

18

21

24

27

30

D003

0

3

6

9

12

15

V_SUP(V)

18

21

24

27

30

D005

V_CCOUT= 5 V at 70

mA

CAN Bus =

Dominant

CAN Load = 60 Ω

V_CCOUT= 5 V at 70

mA

CAN Bus =

Dominant

CAN Load = 60 Ω

图 111. I_SUPvs V_SUPCAN Dominant with 70 mA Load on

图 112. V_CCOUTvs V_SUP

V_CCOUT

133

TCAN4550

ZHCSJ74A –DECEMBER 2018–REVISED JANUARY 2020

www.ti.com.cn

10 Power Supply Recommendations

The TCAN4550 is designed to operate off of the battery V_bat. It has internal regulators to reduce the voltage to

acceptable low power levels supporting the CAN FD controller, CAN transceiver and low voltage CAN receiver.

In order to support a wide range of microprocessors the SPI and GPIO are powered off of the V_IOpin which

supports levels from V to 5.5 V. Bulk capacitance, should be placed on the V_SUPand the V_IOvoltage rails where

system requirements are met. It is recommended that a capacitance of a 100 nF is placed near the TCAN4550

V_SUPand the V_IOsupply terminals. The FLTR terminal requires a minimum of 300 nF capacitance to ground to

regulate the internal digital power rail. V_CCOUTneeds a minimum capacitance to ground of 10 µF at the terminal.

注

•

The capacitance values selected should take into consideration the degradation over

time such that the values do not fall below the minimum values shown

Above is a minimum amount of capacitance but due to system considerations more

may be needed

134

TCAN4550

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ZHCSJ74A –DECEMBER 2018–REVISED JANUARY 2020

11 Layout

Robust and reliable bus node design often requires the use of external transient protection device in order to

protect against EFT and surge transients that may occur in industrial environments. Because ESD and transients

have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high-frequency layout techniques must

be applied during PCB design. The family comes with high on-chip IEC ESD protection, but if higher levels of

system level immunity are desired external TVS diodes can be used. TVS diodes and bus filtering capacitors

should be placed as close to the on-board connectors as possible to prevent noisy transient events from

propagating further into the PCB and system.

11.1 Layout Guidelines

Place the protection and filtering circuitry as close to the bus connector, J1, to prevent transients, ESD and noise

from propagating onto the board. The layout example provides information on components around the device

itself. Transient voltage suppression (TVS) device can be added for extra protection, shown as D1. The

production solution can be either a bi-directional TVS diode or a varistor with ratings matching the application

requirements. This example also shows optional bus filter capacitors C10 and C11. A series common mode

choke (CMC) is placed on the CANH and CANL lines between TCAN4550 and connector J1.

Design the bus protection components in the direction of the signal path. Do not force the transient current to

divert from the signal path to reach the protection device. Use supply and ground planes to provide low

inductance.

注

High-frequency currents follows the path of least impedance and not the path of least

resistance.

Use at least two vias for supply and ground connections of bypass capacitors and protection devices to minimize

trace and via inductance.

•

Bypass and bulk capacitors should be placed as close as possible to the supply terminals of transceiver,

examples are C3, C4 and C5 on the FLTR, V_IO, V_CCOUT, pins and C6 and C7 on the V_SUPsupply.

•

Bus termination: this layout example shows split termination. This is where the termination is split into two

resistors, R5 and R6, with the center or split tap of the termination connected to ground via capacitor C9. Split

termination provides common mode filtering for the bus. When bus termination is placed on the board instead

of directly on the bus, additional care must be taken to ensure the terminating node is not removed from the

bus thus also removing the termination.

•

As terminal 8 (nINT) and 9 (GPO2) are open drain an external resistor to V_IOis required. These can have a

value between 2 kΩ and 10 kΩ.

Terminal 12 (WAKE) is a bi-directional triggered wake up input that is usually connected to an external switch.

It should be configured as shown with a 10 nF (C8) to GND where R2 is 33 kΩ and R3 is 3 kΩ.

Terminal 15 (INH) can be left floating if not used but a 100 kΩ pull-down resistor can be used to discharge the

INH to a sufficient level when the INH output is high-Z.

135

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ZHCSJ74A –DECEMBER 2018–REVISED JANUARY 2020

www.ti.com.cn

11.2 Layout Example

GND

Crystal

40 MHz

50 Ω

Traces for Pin 1 and 20

need to be Matched length

C1

GND

C2

19

nWKRQ

GPIO1

SCLK

2

RST

FLTR

C3

GND

V_IO

C4

GND

SDI

V_CCOUT

C5

GND

SDO

INH

R1

GND

nCS

V_IO

V_SUP

C6

C7

GND

C8

R7

R6

nINT

V_IO

R2

9

12

V_SUP

GPO2

R3

WAKE

To Switch

Choke

R5

R4

C9

C11

C10

CANH

CANL

GND

D1

J1

图 113. Example Layout

136

TCAN4550

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12 器件和文档支持

12.1 文档支持

12.1.1 相关文档

12.1.1.1 CAN 收发器物理层标准：

•

ISO 11898-2:2016：低功耗模式高速媒介访问单元

ISO 8802-3: CSMA/CD – 作为 ISO11898-2 碰撞检测的参考

CAN FD 1.0 规范和论文

Bosch“CAN 位计时配置”，第 6 届国际 CAN 会议 (ICC) 上的论文，1999 年。复制到本系统规范的 DCAN IP

CAN 控制器规范中多次引用了该论文。

•

SAE J2284-2：针对适用于汽车类应用的 250kbps 高速 CAN (HSC)

SAE J2284-3：针对适用于汽车类应用的 500kbps 高速 CAN (HSC)

Bosch M_CAN 控制器局域网修订版 3.2.1.1（2016 年 3 月 24 日）

12.1.1.2 EMC 要求：

•

SAE J2962-2：针对 CAN 收发器的 US3 要求

CAN、LIN、FR V1.3 的硬件要求

12.1.1.3 符合性测试要求：

HS_TRX_Test_Spec_V_1_0：GIFT/ICT CAN 的高速物理层测试要求

•

12.1.1.4 支持文档

•

“A Comprehensible Guide to Controller Area Network”, Wilfried Voss, Copperhill Media Corporation

“CAN System Engineering: From Theory to Practical Applications”, 2nd Edition, 2013; Dr. Wolfhard Lawrenz,

Springer.

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 支持资源

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.4 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

137

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www.ti.com.cn

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查看左侧的导航栏。

138

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Apr-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TCAN4550RGYR

TCAN4550RGYT

VQFN

RGY

20

3000

250

330.0

180.0

12.4

3.8

4.8

1.18

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Apr-2022

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TCAN4550RGYR

TCAN4550RGYT

VQFN

RGY

20

3000

250

367.0

213.0

367.0

191.0

38.0

35.0

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RGY 20

3.5 x 4.5, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FGLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4225264/A

www.ti.com

PACKAGE OUTLINE

RGY0020C

VQFN - 1 mm max height

S

C

A

L

E

3

.

0

PLASTIC QUAD FLATPACK - NO LEAD

3.6

3.4

B

A

PIN 1 INDEX AREA

4.6

4.4

0.1 MIN

(0.05)

SECTION A-A

SCALE 30.000

SECTION A-A

TYPICAL

C

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

2.2 0.1

2X 1.5

SYMM

EXPOSED

THERMAL PAD

(0.2) TYP

10

11

14X 0.5

9

12

4.2 0.1

3.2 0.1

21

SYMM

2X

3.5

A

2

19

0.3

0.2

1

20

PIN 1 ID

(OPTIONAL)

20X

0.1

0.05

C A B

4X 0.25 0.05

0.5

0.3

20X

4223814/A 06/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RGY0020C

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(2.2)

4X (0.75)

(0.85)

SYMM

1

20

20X (0.6)

2

19

20X (0.25)

(R0.05) TYP

(1.35)

(4.2)

4X

21

SYMM

(3.2)

(4.3)

14X (0.5)

12

9

(

0.2) TYP

VIA

10

4X (0.25)

11

2X (0.75)

(3.3)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:18X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4223814/A 06/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RGY0020C

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X (0.98)

20

2X (0.25)

1

2X (0.2)

20X (0.6)

2

19

24X (0.25)

4X

(1.43)

(R0.05) TYP

21

SYMM

4X

(4.3)

(0.82)

TYP

14X (0.5)

12

9

EXPOSED METAL

TYP

10

11

4X (0.75)

(0.59) TYP

SYMM

(3.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 21

80% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4223814/A 06/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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型号：	TCAN4550RGYT
厂家：	TEXAS INSTRUMENTS
描述：	具有集成收发器的 CAN FD 控制器 \| RGY \| 20 \| -40 to 125 控制器
文件：	总147页 (文件大小：2794K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TCAN4550RGYT [TI]

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