TCM320AC36IDW [TI]
VOICE-BAND AUDIO PROCESSORS VBAPE; 语音频带音频处理器VBAPE型号: | TCM320AC36IDW |
厂家: | TEXAS INSTRUMENTS |
描述: | VOICE-BAND AUDIO PROCESSORS VBAPE |
文件: | 总23页 (文件大小:319K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAP )
SLWS003C – MAY 1992 – REVISED APRIL – 1998
Single 5-V Operation
Selectable Between 8-Bit Companded and
13-Bit (Dynamic Range) Linear Conversion:
– TCM320AC36 . . . µ-Law and Linear
Modes
– TCM320AC37 . . . A-Law and Linear
Modes
Low Power Consumption:
– Operating Mode . . . 40 mW Typ
– Standby Mode . . . 5 mW Typ
– Power-Down Mode . . . 3 mW Typ
Combined A/D, D/A, and Filters
Programmable Volume Control in Linear
Mode
Extended Variable-Frequency Operation
– Sample Rates up to 16 kHz
– Pass-Band up to 7.2 kHz
300 Hz – 3.6 kHz Passband with Specified
Master Clock
Electret Microphone Bias Reference
Voltage Available
Designed for Standard 2.048-MHz Master
Clock for U.S. Analog, U.S. Digital, CT2,
DECT, GSM, and PCS Standards for
Hand-Held Battery-Powered Telephones
Drive a Piezo Speaker Directly
Compatible With All Digital Signal
Processors (DSPs)
PT PACKAGE
(TOP VIEW)
DW OR N PACKAGE
(TOP VIEW)
PDN
EARA
EARB
MICBIAS
MICGS
MICIN
VMID
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
48 47 46 45 44 43 42 41 40 39 38 37
EARGS
V
GND
36
35
34
33
32
31
30
29
28
27
26
25
VMID
NC
AGND
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
CC
MICMUTE
DCLKR
DIN
FSR
EARMUTE
LINSEL
TSX/DCLKX
DOUT
FSX
2
3
AV
4
CC
NC
5
CLK
NC
NC
NC
6
7
8
9
DV
CC
10
11
12
DGND
LINSEL
NC
NC
MICMUTE
NC
13 14 15 16 17 18 19 20 21 22 23 24
NC – No internal connection
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VBAP is a trademark of Texas Instruments Incorporated.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAP )
SLWS003C – MAY 1992 – REVISED APRIL – 1998
description
The TCM320AC36 and TCM320AC37 voice-band audio processor (VBAP) integrated circuits are designed to
perform the transmit encoding (A/D conversion) and receive decoding (D/A conversion) together with transmit
and receive filtering for voice-band communications systems. Cellular telephone systems are targeted in
particular; however, these integrated circuits can function in other systems including digital audio,
telecommunications, and data acquisition.
These devices are pin-selectable for either of two modes, companded and linear, providing data in two formats.
In the companded mode, data is transmitted and received in 8-bit words. In the linear mode, 13 bits of data, and
either three bits of gain-setting control data, or three zero bits of padding to create a 16-bit word, are sent and
received.
Thetransmitsectionisdesignedtointerfacedirectlywithanelectretmicrophoneelement. Themicrophoneinput
signal (MICIN) is buffered and amplified, with provision for setting the amplifier gain to accommodate a range
of signal input levels. The amplified signal is passed through antialiasing and band-pass filters. The filtered
signal is then applied to the input of a compressing analog-to-digital converter (COADC) when companded
mode is selected. Otherwise, the analog-to-digital converter performs a linear conversion. The resulting data
is then clocked out of DOUT as a serial data stream.
The receive section takes a frame of serial data on DIN and converts it to analog through an expanding
digital-to-analog converter (EXDAC) when the companded mode is selected; otherwise, a linear conversion is
performed. The analog signal then passes through switched capacitor filters, which provide out-of-band
rejection, (sin x)/x correction functions, and smoothing. The filtered signal is sent to the earphone amplifier. The
earphone amplifier has a differential output with adjustable gain and is designed to minimize static power
dissipation.
A single on-chip high-precision band-gap circuit generates all voltage references, eliminating the need for
externalreferencevoltages. AninternalreferencevoltageequaltoV /2, VMID, isusedtodevelopthemidlevel
CC
virtual ground for all the amplifier circuits and the microphone bias circuit. Another reference voltage, MICBIAS,
can supply bias current for the microphone.
The TCM320AC3xC devices are characterized for operation from 0°C to 70°C. The TCM320AC3xI devices are
characterized for operation from –40°C to 85°C.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAP )
SLWS003C – MAY 1992 – REVISED APRIL – 1998
functional block diagram
LINSEL
15
6
Transmit
Third-Order
Antialias
Transmit
Sixth-Order
Low Pass
Transmit
First-Order
High Pass
MICMUTE
Input
Output
13
Logic
ADC
DOUT
FSX
18
Buffer
MICIN
12
19
MICGS
256 kHz
8 kHz
Band-Gap
Voltage
Reference
VMID
A/D
Autozero
Converter
Voltage
Reference
17
VMID
VMID
Generator
20
MICBIAS
14
TSX/DCLKX
CLK
256 kHz
8 kHz
Clock
Generator
Clock
Control
11
7
D/A
Converter
Voltage
DCLKR
Reference
9
256 kHz
FSR
2
EARA
EARB
3
Receive
Buffer
Receive
Filter
Input
Logic
8
Earphone
Amplifier
DAC
DIN
4
EARGS
10
EARMUTE
15
LINSEL
5
16
GND
1
V
CC
PDN
Terminal numbers shown are for the DW and N packages.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAP )
SLWS003C – MAY 1992 – REVISED APRIL – 1998
Terminal Functions
TERMINAL
NO.
DW, N
I/O
DESCRIPTION
NAME
PT
34
4
AGND
AV
—
—
11
Ground return for all internal analog circuits
5-V supply voltage for all internal analog circuits
CC
CLK
19
I
I
Clock input. In the fixed-data-rate mode, CLK is the master clock input as well as the transmit and
receive data clock input . In the variable-data-rate mode, CLK is the master clock input only (digital).
DCLKR
7
14
Selection of fixed- or variable-data-rate operation. When DCLKR is connected to V , the device
CC
operates in the fixed-data-rate mode. When DCLKR is not connected to V , the device operates in
CC
the variable-data-rate mode, and DCLKR becomes the receive data clock (digital).
Ground return for all internal digital circuits
DGND
DIN
—
8
27
15
I
Receive data input. Input data is clocked in on consecutive negative transitions of the receive data
clock, which is CLK for a fixed data rate and DCLKR for a variable data rate (digital).
DOUT
13
21
O
Transmit data output. Transmit data is clocked out on consecutive positive transitions of the transmit
data clock, which is CLK for a fixed data rate and DCLKX for a variable data rate (digital).
DV
—
2
9
44
45
46
5-V supply voltage for all internal digital circuits
CC
EARA
EARB
EARGS
O
O
I
Earphone output. EARA forms a differential drive when used with the EARB signal (analog).
Earphone output. EARB forms a differential drive when used with the EARA signal (analog).
3
4
Earphone gain set input of feedback signal for the earphone output. The ratio of an external potential
divider network connected across EARA and EARB adjusts the power amplifier gain. Maximum gain
occurs when EARGS is connected to EARB. Minimum gain occurs when EARGS is connected to
EARA. Earphone frequency response correction is performed using an RC approach (analog).
EARMUTE
FSR
10
9
17
16
I
I
Earphone output mute control signal. When EARMUTE is low, the output amplifier is disabled and no
audio is sent to the earphone (digital).
Frame-synchronizationclock input for the receive channel. In the variable-data-rate mode, this signal
must remain high for the duration of the time slot. The receive channel enters the standby condition
when FSR is TTL-low for five frames or longer. The device enters a production test-mode condition
when either FSR or FSX is held high for five frames or longer (digital).
FSX
12
20
I
I
Frame synchronization clock input for the transmit channel. FSX operates independently of FSR, but
also in an analogous manner to FSR. The transmit channel enters the standby condition when FSX
is low for five frames or longer. The device enters a production test-mode condition when either FSX
or FSR is held high for five frames or longer (digital).
GND
16
15
—
Ground return for all internal circuits
LINSEL
26
Linearselectioninput. Whenlow, LINSELselectslinearcoding/decoding. Whenhigh, LINSEL selects
compandedcoding/decoding. Companding code on the ’AC36 is µ-law, and companding code on the
’AC37 is A-law (digital).
MICBIAS
MICGS
20
19
42
41
O
O
Microphone bias. MICBIAS voltage for the electret microphone is equal to VMID.
Output of the internal microphone amplifier. MICGS is used as the feedback to set the microphone
amplifier gain. If sidetone is required, it is accomplished by connecting a series network between
MICGS and EARGS (analog).
MICIN
18
6
40
11
43
I
I
I
Microphone input. Electret microphone input to the internal microphone amplifier (analog)
Microphoneinput mute control signal. When MICMUTE is active (low), zero code is transmitted (dig.).
Power-down input. When PDN is low, the device powers down to reduce power consumption (digital).
MICMUTE
PDN
1
TSX/DCLKX
14
22 I/O Transmit time slot strobe (active-low output) or data clock (input) for the transmit channel. In the
fixed-data-rate mode, TSX/DCLKX is an open-drain output that pulls to ground and is used as an
enable signal for a 3-state buffer. In the variable-data-rate mode, DCLKX becomes the transmit data
clock input (digital).
V
CC
VMID
5
—
5-V supply voltage for all internal circuits
V /2 bias voltage reference. A pair of external, low-leakage, high-frequency capacitors (1 µF and
CC
17
36
O
470 pF) should be connected between VMID and ground for filtering.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAP )
SLWS003C – MAY 1992 – REVISED APRIL – 1998
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
CC
Output voltage range at DOUT, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Input voltage range at DIN, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
O
I
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Voltage value is with respect to GND.
DISSIPATION RATING TABLE
DERATING FACTOR
T
A
≤ 25°C
T
= 70°C
T = 85°C
A
POWER RATING
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING
A
DW
N
1025 mW
8.2 mW/°C
9.2 mW/°C
7.1 mW/°C
656 mW
533 mW
1150 mW
736 mW
598 mW
PT
1075 mW
756 mW
649 mW
recommended operating conditions (see Note 2)
MIN
4.5
MAX
UNIT
V
Supply voltage, V
(see Note 3)
5.5
CC
High-level input voltage, V
2.2
V
IH
Low-level input voltage, V
0.8
V
IL
Load resistance between EARA and EARB, R (see Note 4)
600
Ω
L
Load capacitance between EARA and EARB, C (see Note 4)
113
70
nF
L
TCM320AC36C, TCM320AC37C
TCM320AC36I, TCM320AC37I
0
Operating free-air temperature, T
°C
A
–40
85
NOTES: 2. To avoid possible damage to these CMOS devices and resulting reliability problems, the power-up sequence detailed in the system
reliability features paragraph should be followed.
3. Voltages at analog inputs, outputs, and V
are with respect to GND.
CC
R and C should not be applied simultaneously.
L
4.
L
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAP )
SLWS003C – MAY 1992 – REVISED APRIL – 1998
electrical characteristics over recommended ranges of supply voltage and free-air temperature
(unless otherwise noted)
supply current, f
or f
= 2.048 MHz, outputs not loaded, V
= 5 V, T = 25°C
DCLKR
DCLKX
CC A
PARAMETER
TEST CONDITIONS
PDN is high with CLK signal present
PDN is low for 500 µs
MIN
MAX
9.9
0.85
2
UNIT
Operating
Power down
I
Supply current from V
mA
CC
CC
Standby–both PDN is high with FSX and FSR held low
PDN is high with either FSX or FSR pulsing with the
other held low
Standby – one
6
digital interface
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
High-level output voltage
Low-level output voltage
I
I
= –3.2 mA,
= 3.2 mA,
V
V
= 5 V
= 5 V
2.4
4.6
0.2
OH
OH
CC
DOUT
0.4
10
10
V
OL
OL
CC
I
I
High-level input current, any digital input
Low-level input current, any digital input
Input capacitance
V = 2.2 V to V
CC
µA
µA
pF
pF
IH
I
V = 0 to 0.8 V
IL
I
C
C
5
5
i
Output capacitance
o
†
All typical values are at V
= 5 V, T = 25°C.
A
CC
microphone interface
†
PARAMETER
Input offset voltage at MICIN
TEST CONDITIONS
MIN
TYP
MAX
±5
UNIT
mV
nA
V
V = 0 to 5 V
I
IO
1
I
IB
Input bias current at MICIN
Unity-gain bandwidth, open loop at MICIN
Input capacitance at MICIN
Large-signal voltage amplification at MICGS
VMID
±200
B
1
5
MHz
pF
C
i
A
V
10000
V/V
µA
1
1
I
O
max
Maximum output current
MICBIAS
(source only)
mA
†
All typical values are at V
= 5 V, T = 25°C.
CC
A
speaker interface
†
PARAMETER
AC output voltage
Output offset voltage at EARA, EARB (single-ended) Relative to GND
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
3
Vpp
O(PP)
80 mVpk
OO
I
I
Input leakage current at EARGS
Maximum output current
Output resistance at EARA, EARB
Gain change
V = 0.5 V to (V
CC
– 0.5) V
±200
±5
nA
mA
Ω
I(lkg)
I
max
R = 600 Ω
L
O
r
1
o
EARMUTE low, max level when muted
–80
dB
†
All typical values are at V
= 5 V, T = 25°C.
A
CC
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAP )
SLWS003C – MAY 1992 – REVISED APRIL – 1998
transmit gain and dynamic range, companded mode (µ-law or A-law) or linear mode selected, V
= 5 V,
UNIT
CC
T = 25°C (unless otherwise noted) (see Notes 5 and 6)
A
PARAMETER
TEST CONDITIONS
MIN
MAX
0.982
0.985
1.001
4
Companded mode selected, µ-law (’AC36)
Companded mode selected, A-law (’AC37)
Linear mode selected (’AC36 and ’AC37)
Companded mode selected, µ-law (’AC36)
Companded mode selected, A-law (’AC37)
Linear mode selected (’AC36 and ’AC37)
0-dB input signal
Transmit reference-signal level (0 dB) (see Note 7)
Vrms
Overload-signal level (MICIN at unity gain)
Absolute gain error
4
Vpp
4
±1
dB
dB
MICIN to DOUT at 3 dBm0 to –36 dBm0
MICIN to DOUT at –37 dBm0 to –40 dBm0
MICIN to DOUT at –41 dBm0 to –50 dBm0
MICIN to DOUT at –51 dBm0 to –55 dBm0
±0.5
±1
Gain error with input level relative to gain at –10 dBm0
Gain variation
±1.5
±2
dB
dB
dB
V
CC
±10%,
T
A
= 0°C to 70°C
±0.5
NOTES: 5. Unlessotherwisenoted,theanaloginputis0dB,1020-Hzsinewave,where0dBisdefinedasthezero-referencepointofthechannel
under test.
6. The input amplifier is set for inverting unity gain.
7. The reference-signal level, which is input to the transmit channel, is defined as a value 3 dB below the full-scale value of 2 V.
transmit filter transfer, companded mode (µ-law or A-law) or linear mode selected, over recommended
ranges of supply voltage and free-air temperature, CLK = 2.048 MHz, FSX = 8 kHz (see Note 6)
PARAMETER
TEST CONDITIONS
MIN
–10
MAX
0
UNIT
f
f
f
f
f
f
f
= 50 Hz
MICIN
MICIN
MICIN
MICIN
MICIN
MICIN
MICIN
= 200 Hz
–1.8
0
= 300 Hz to 3 kHz
= 3.3 kHz
= 3.4 kHz
= 4 kHz
±0.15
0.04
–0.1
–14
–32
Input amplifier set for unity gain,
noninverting maximum gain output signal
at MICIN is 0 dB
Gain relative to input signal gain at
1.02 kHz
–0.35
–1
dB
≥4.6 kHz
NOTE 6. The input amplifier is set for inverting unity gain.
transmit idle channel noise and distortion, companded mode with µ-law or A-law selected, over
recommended ranges of supply voltage and operating free-air temperature (see Note 8)
PARAMETER
Transmit noise, psophometrically weighted
Transmit noise, C-message weighted
TEST CONDITIONS
MICIN connected to MICGS through a 10-kΩ resistor
MICIN connected to MICGS through a 10-kΩ resistor
MICIN to DOUT at 0 dBm0 to –17 dBm0
MICIN to DOUT at –18 dBm0 to –23 dBm0
MICIN to DOUT at –24 dBm0 to –29 dBm0
MICIN to DOUT at –30 dBm0 to –35 dBm0
MICIN to DOUT at –36 dBm0 to –45 dBm0
CCITT G.712 (7.1), R2
MIN
MAX
UNIT
–71
dB0p
10 dBrnC0
36
34
30
24
16
49
51
Transmit signal-to-distortion ratio with sine-wave input
dB
Intermodulation distortion, 2-tone CCITT method,
composite power level –13 dBm0
dB
CCITT G.712 (7.2), R3
NOTE 8: Transmit noise, linear mode: 200 µVrms is equivalent to –74 dB (referenced to device 0-dB level).
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAP )
SLWS003C – MAY 1992 – REVISED APRIL – 1998
transmit idle channel noise and distortion, linear mode selected, over recommended ranges of supply
voltage and operating free-air temperature (see Notes 6 and 8)
PARAMETER
TEST CONDITIONS
MICIN connected to MICGS through a 10-kΩ resistor
MICIN to DOUT at –6 dBm0
MIN
MAX
UNIT
Transmit noise, C-message weighted
200 µVrms
50
48
40
35
20
18
MICIN to DOUT at –12 dBm0
MICIN to DOUT at –18 dBm0
Transmit signal-to-distortion ratio with sine-wave input
dB
MICIN to DOUT at –24 dBm0
MICIN to DOUT at –40 dBm0
MICIN to DOUT at –45 dBm0
NOTES: 6. The input amplifier is set for inverting unity gain.
8. Transmit noise, linear mode: 200 µVrms is equivalent to –74 dB (referenced to device 0-dB level).
receive gain and dynamic range, companded mode (µ-law or A-law) or linear mode selected, V
= 5 V,
CC
T = 25°C (unless otherwise noted) (see Notes 9 and 10)
A
PARAMETER
TEST CONDITIONS
MIN
MAX
0.736
0.739
0.751
3
UNIT
Companded mode selected, µ-law (’AC36)
Companded mode selected, A-law (’AC37)
Linear mode selected (’AC36 and ’AC37)
Companded mode selected, µ-law (’AC36)
Companded mode selected, A-law (’AC37)
Linear mode selected (’AC36 and ’AC37)
0-dB input signal
Receive reference-signal level (0 dB) (see Note 11)
Vrms
Overload-signal level
Absolute gain error
3
Vpp
dB
3
±1
DIN to EARA and EARB at 3 dBm0 to –36 dBm0
DIN to EARA and EARB at –37 dBm0 to –40 dBm0
DIN to EARA and EARB at –41 dBm0 to –50 dBm0
DIN to EARA and EARB at –51 dBm0 to –55 dBm0
±0.5
±1
Gain error with output level relative to gain at –10 dBm0
dB
±1.5
±2
Gain variation
V
CC
±10%,
T
A
= 0°C to 70°C
±0.5
dB
NOTES: 9. Receive output is measured differentially in the maximum gain configuration. To set the output amplifier for maximum gain, EARGS
is connected to EARB and the output is taken between EARA and EARB. All output levels are (sin x)/x corrected.
10. Unless otherwise noted, the digital input is a word stream generated by passing a 0-dB sine wave at 1020 Hz through an ideal
encoder, where 0 dB is defined as the zero reference.
11. This reference-signal level is measured at the speaker output of the receive channel with the gain of the output speaker amplifier
set to unity.
receive filter transfer, companded mode (µ-law or A-law) or linear mode selected, over recommended ranges
of supply voltage and operating free-air temperature, FSR = 8 kHz (see Note 9)
PARAMETER
TEST CONDITIONS
MIN
–0.5
MAX
0.15
UNIT
f
f
f
f
f
f
f
= < 200 Hz
= 200 Hz
DIN
DIN
DIN
DIN
DIN
DIN
DIN
0.15
= 300 Hz to 3 kHz
= 3.3 kHz
±0.15
0.03
Gain relative to gain at 1.02 kHz
DIN = 0 dBm0
–0.35
dB
= 3.4 kHz
–1 –0.18
–14
= 4 kHz
= > 4.6 kHz
–30
NOTE 9. Receive output is measured differentially in the maximum gain configuration. To set the output amplifier for maximum gain, EARGS is
connected to EARB and the output is taken between EARA and EARB. All output levels are (sin x)/x corrected.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAP )
SLWS003C – MAY 1992 – REVISED APRIL – 1998
receiveidlechannelnoiseanddistortion, compandedmodewithµ-laworA-lawselected, overrecommended
ranges of supply voltage and operating free-air temperature (see Note 9)
PARAMETER
TEST CONDITIONS
DIN = 11010101 (A-law)
MIN
MAX
– 75
5
UNIT
dB0p
Receive noise, psophometrically weighted
Receive noise, C-message weighted
DIN = 11111111 (µ-law)
dBrnc0
DIN to EARA and EARB at 0 dBm0 to –18 dBm0
DIN to EARA and EARB at –19 dBm0 to –24 dBm0
36
34
30
23
17
Receive signal-to-distortion ratio with sine-wave input DIN to EARA and EARB at –25 dBm0 to –30 dBm0
DIN to EARA and EARB at –31 dBm0 to –38 dBm0
dB
DIN to EARA and EARB at –39 dBm0 to –45 dBm0
NOTE 9. Receive output is measured differentially in the maximum gain configuration. To set the output amplifier for maximum gain, EARGS is
connected to EARB and the output is taken between EARA and EARB. All output levels are (sin x)/x corrected.
receive idle channel noise and distortion, linear mode selected, over recommended ranges of supply voltage
and operating free-air temperature (see Notes 9 and 12)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Receive noise, C-message weighted
DIN = 00000000
200 µVrms
DIN to EARA and EARB at 0 dBm0 to –6 dBm0
DIN to EARA and EARB at –7 dBm0 to –12 dBm0
DIN to EARA and EARB at –13 dBm0 to –18 dBm0
DIN to EARA and EARB at –19 dBm0 to –24 dBm0
DIN to EARA and EARB at –25 dBm0 to –40 dBm0
DIN to EARA and EARB at –41 dBm0 to –45 dBm0
CCITT G.712 (7.1), R2
50
48
38
32
18
15
50
54
Receive signal-to-distortion ratio with sine-wave input
dB
Intermodulation, 2-tone CCITT distortion method,
composite power level –13 dBm0
dB
CCITT G.712 (7.2), R3
NOTES: 9. Receive output is measured differentially in the maximum gain configuration. To set the output amplifier for maximum gain, EARGS
is connected to EARB and the output is taken between EARA and EARB. All output levels are (sin x)/x corrected.
12. Receive noise, linear mode: 200 µVrms is equivalent to –71 dB (referenced to device 0-dB level).
power supply rejection and crosstalk attenuation over recommended ranges of supply voltage and
operating free-air temperature
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
Idle channel, supply signal = 100 mVrms,
f = 0 to 30 kHz (measured at DOUT)
Supply voltage rejection, transmit channel
–30
–30
dB
Idle channel, supply signal = 100 mVrms,
EARGS connected to EARB,
f = 0 to 30 kHz (measured differentially between EARA
and EARB)
Supply voltage rejection, receive channel
dB
MICIN = 0 dB, f = 1.02 kHz, unity transmit gain,
EARGS connected to EARB,
measured differentially between EARA and EARB
Crosstalk attenuation, transmit-to-receive
(differential)
68
68
dB
dB
DIN = 0 dBm0, f = 1.02 kHz, unity transmit
gain, measured at DOUT
Crosstalk attenuation, receive-to-transmit
†
All typical values are at V
= 5 V, T = 25°C.
A
CC
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAP )
SLWS003C – MAY 1992 – REVISED APRIL – 1998
timing requirements
clock timing requirements over recommended ranges of supply voltage and operating free-air temperature
(see Figure 1 through Figure 4)
†
MIN NOM
MAX
10
UNIT
t
t
Transition time, CLK and DCLKX/DCLKR
Duty cycle, CLK
ns
45%
45%
50%
50%
55%
55%
Duty cycle, DCLKX/DCLKR
†
All typical values are at V
= 5 V, T = 25°C.
A
CC
transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 2)
MIN
MAX
UNIT
t
t
Setup time, FSX high before CLK↓
Hold time, FSX high after CLK↓
20
468
ns
su(FSX)
20
468
ns
h(FSX)
receive timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 1)
MIN
20
MAX
468
UNIT
ns
t
t
t
t
Setup time, FSR high before CLK↓
Hold time, FSR high after CLK↓
su(FSR)
h(FSR)
su(DIN)
h(DIN)
20
468
ns
Setup time, DIN high or low before CLK↓
Hold time, DIN high or low after CLK↓
20
ns
20
ns
transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode (see Figure 4)
MIN
40
MAX
UNIT
ns
t
t
Setup time, FSX high before DCLKX↓
Hold time, FSX high after DCLKX↓
t
–40
–35
su(FSX)
c(DCLKX)
35
t
ns
h(FSX)
c(DCLKX)
receive timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode (see Figure 3)
MIN
40
MAX
UNIT
ns
t
t
t
t
Setup time, FSR high before DCLKR↓
Hold time, FSR high after DCLKR↓
su(FSR)
h(FSR)
su(DIN)
h(DIN)
35
t
–35
ns
c(DCLKR)
Setup time, DIN high or low before DCLKR↓
Hold time, DIN high or low after DCLKR↓
30
ns
30
ns
switching characteristics
propagation delay times over recommended ranges of operating conditions, fixed-data-rate mode,
C = 0 to 10 pF (see Figure 2)
L
PARAMETER
From CLK bit 1 high to DOUT bit 1 valid
TEST CONDITIONS
MIN
MAX
35
UNIT
ns
t
t
t
t
t
pd1
pd2
pd3
pd4
pd5
From CLK high to DOUT valid, bits 2 to n
From CLK bit n low to DOUT bit n Hi-Z
From CLK bit 1 high to TSX active (low)
From CLK bit n low to TSX inactive (high)
35
ns
30
30
ns
R
R
= 1.24 kΩ
= 1.24 kΩ
40
ns
pullup
pullup
ns
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAP )
SLWS003C – MAY 1992 – REVISED APRIL – 1998
propagation delay times over recommended ranges of operating conditions, variable-data-rate mode (see
Figure 4)
PARAMETER
FSX high to DOUT bit 1 valid
TEST CONDITIONS
MIN
MAX
30
UNIT
ns
t
t
t
C
C
= 0 to 10 pF
= 0 to 10 pF
pd6
pd7
pd8
L
L
DCLKX high to DOUT valid, bits 2 to n
FSX low to DOUT bit n Hi-Z
40
ns
20
ns
PARAMETER MEASUREMENT INFORMATION
All timing parameters are referenced to V and V . Bit 1 = MSB (most significant bit) and is clocked in first on DIN
IH
IL
or clocked out first on DOUT. Bit n = LSB (least significant bit) and is clocked in last on DIN or is clocked out last on
DOUT. N = 8 for the companded mode, and N = 16 for the linear mode.
Receive Time Slot
0
1
2
3
4
N–2
N–1
N
N+1
80%
80%
20%
CLK
FSR
20%
t
su(FSR)
t
h(FSR)
See Note B
See Note A
1
t
h(DIN)
N–2
N–1
N
2
3
4
N–1
N
1
DIN
See Note C
t
su(DIN)
NOTES: A. This window is allowed for FSR high.
B. This window is allowed for FSR low.
C. Transitions are measured at 50%.
Figure 1. Fixed-Data Rate Mode, Receive Side Timing Diagram
Transmit Time Slot
0
1
2
3
4
N–2
N–1
N
N+1
80%
80%
CLK
FSX
20%
20%
t
su(FSX)
t
h(FSX)
See Note B
See Note A
t
t
pd3
pd2
1
2
3
N–2
N–1
t
N
DOUT
See Note C
t
pd1
pd5
80%
TSX
20%
t
pd4
NOTES: A. This window is allowed for FSX high.
B. This window is allowed for FSX low (t
C. Transitions are measured at 50%.
max determined by data collision considerations).
h(FSX)
Figure 2. Fixed-Data Rate Mode, Transmit Side Timing Diagram
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAP )
SLWS003C – MAY 1992 – REVISED APRIL – 1998
PARAMETER MEASUREMENT INFORMATION
Receive Time Slot
4
0
1
2
3
N–2
N–1
N
N+1
80%
80%
20%
80%
DCLKR
FSR
20%
t
t
su(FSR)
h(FSR)
See Note A
N
t
See Note B
N–1
su(DIN)
max determined by data collision considerations).
h(DIN)
N–2
N–1
1
2
3
4
N
1
DIN
See Note C
t
NOTES: A. This window is allowed for FSR high (t
B. This window is allowed for FSR low.
C. Transitions are measured at 50%.
su(FSR)
Figure 3. Variable-Data Rate Mode, Receive Side Timing Diagram
Transmit Time Slot
0
1
2
3
4
N–2
N–1
N
N+1
80%
80%
80%
DCLKX
FSX
20%
h(FSX)
20%
t
t
su(FSX)
t
pd7
See Note A
t
See Note B
t
pd8
pd6
DOUT
1
2
3
4
N–2
N–1
N
See Note C
NOTES: A. This window is allowed for FSX high.
B. This window is allowed for FSX low without data repetition.
C. Transitions are measured at 50%.
Figure 4. Variable-Data Rate Mode, Transmit Side Timing Diagram
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAP )
SLWS003C – MAY 1992 – REVISED APRIL – 1998
PRINCIPLES OF OPERATION
general
system reliability features
The device should be powered up and initialized as follows:
1. Apply GND.
2. Apply V
.
CC
3. Connect all clocks.
4. Apply TTL high to PDN.
5. Apply synchronizing pulses to FSX and/or FSR.
Eventhough the VBAP is heavily protected against latch-up, it is still possible to cause it to latch up under certain
improper power conditions. To help ensure that latch-up does not occur, a reverse-biased Schottky diode (with
a forward voltage drop of less than or equal to 0.4 V — 1N5711 or equivalent) should be connected between
V
(power supply) and GND.
CC
On the transmit channel, digital outputs DOUT and TSX are held in the high-impedance state for approximately
four frames (500 µs) after power up or application of V . After this delay, DOUT, TSX, and signaling are
CC
functional and occur in the correct time slot. The analog circuits on the transmit side require approximately
60 ms to reach their equilibrium value due to the autozero circuit settling time. To further enhance system
integrity, DOUT and TSX are placed in the high-impedance state after an interruption of CLK.
power-down and standby operations
To minimize power consumption, a power-down mode and three standby modes are provided.
For power down, an external low signal is applied to PDN. In the absence of a signal, PDN is internally pulled
up to a high logic level and the device remains active. In the power-down mode, the average power consumption
is reduced to 3 mW.
Three standby modes give the user the option of placing the entire device on standby, placing only the transmit
channel on standby, or placing only the receive channel on standby. To place the entire device on standby, both
FSX and FSR are held low. For transmit-only operation (receive channel on standby), FSX is pulsing and FSR
is held low. For receive-only operation (transmit section on standby), FSR is pulsing and FSX is held low. When
the entire device is in standby mode, power consumption is reduced to 5 mW. See Table 1 for power-down and
standby procedures.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAP )
SLWS003C – MAY 1992 – REVISED APRIL – 1998
PRINCIPLES OF OPERATION
Table 1. Power-Down and Standby Procedures
TYPICAL POWER
CONSUMPTION
DEVICE STATUS
PROCEDURE
DIGITAL OUTPUT STATUS
PDN = high,
FSX = pulses,
FSR = pulses
Power on
40 mW
Digital outputs active but not loaded
PDN = low,
FSX, FSR = X
Power down
3 mW
5 mW
TSX and DOUT in the high-impedance state
TSX and DOUT in the high-impedance state
†
FSX = low,
FSR = low,
PDN = high
Entire device on standby
mode
FSX = low,
FSR = pulses,
PDN = high
Only transmit channel in
standby mode
TSX and DOUT in the high-impedance state within five
frames
20 mW
20 mW
FSR = low,
FSX = pulses,
PDN = high
Only receive channel in
standby mode
Digital outputs active but not loaded
†
X = don’t care
fixed-data-rate timing
Fixed-data-rate timing, selected by connecting DCLKR to V , uses the master clock (CLK), frame
CC
synchronization clocks (FSX and FSR), and the TSX output. FSX and FSR are inputs that set the sampling
frequency. Data is transmitted on DOUT on the positive transitions of CLK following the rising edge of FSX. Data
is received on DIN on the falling edges of CLK following FSR. A D/A conversion is performed on the received
digital word, and the resulting analog sample is held on an internal sample-and-hold capacitor until transferred
to the receive filter. The data word is eight bits long in the companded mode and 16 bits long in the linear mode.
variable-data-rate timing
Variable-data-rate timing is selected by connecting DCLKR to the receive data clock. In this mode, the master
clock (CLK) controls the switched-capacitor filters, while data transfer into DIN and out of DOUT is controlled
by DCLKR and DCLKX respectively. This allows the data to be transferred in and out of the device at any rate
up to the frequency of the master clock. DCLKR and DCLKX must be synchronous with CLK.
While the FSX input is high, data is transmitted from DOUT on consecutive positive transitions of DCLKX.
Similarly, while the FSR input is high, the data word is received at DIN on consecutive negative transitions of
DCLKR. The transmitted data word at DOUT is repeated in all remaining time slots in the frame as long as
DCLKX is pulsed and FSX is held high. This feature, which allows the data word to be transmitted more than
once per frame, is available only with variable-data-rate timing.
asynchronous operations
To avoid crosstalk problems associated with special interrupt circuits, the design includes separate converters,
filters, and voltage references on the transmit and receive sides. This allows completely independent operation
of the two channels. In either timing mode, the master clock, data clock, and time-slot strobe must be
synchronized at the beginning of each frame.
precision voltage references
A precision band-gap reference voltage is generated internally and is used to supply all the references required
for operation of both the transmit and receive channels. The gain in each channel is trimmed during the
manufacturing process. This ensures very accurate, stable gain performance over variations in supply voltage
and device temperature.
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAP )
SLWS003C – MAY 1992 – REVISED APRIL – 1998
PRINCIPLES OF OPERATION
conversion laws
The TCM320AC36 provides µ-law companding operation that approximates the CCITT G.711
recommendation. The TCM320AC37 provides A-law companding operation that approximates the CCITT
G.711 recommendation. The linear mode of operation uses a 13-bit two’s-complement format and is the same
for both the TCM320AC36 and the TCM320AC37.
transmit operation
microphone input
The microphone input amplifier is designed specifically to interface to electret-type microphone elements, as
shown in Figure 5. The VMID buffer circuit provides a voltage (MICBIAS) equal to 1/2 V
as a reference for
CC
the microphone amplifier and a bias voltage to the electret microphone. The microphone amplifier output
(MICGS) is used in conjunction with a feedback network and applied to the amplifier inverting input (MICIN) to
set the amplifier gain. In the companded mode, when the MICIN signal level decreases to a level near the noise
floor, the VBAP mutes the signal and outputs zero bits while continuing to monitor the signal level. When the
input level once again exceeds the noise threshold, the mute is released and normal operation resumes. Input
hysteresis is provided to ensure noiseless transitions into and out of the muted condition. VMID appears at a
terminal to provide a place to filter the VMID voltage.
VMID
VMID Reference
For Amplifiers
V
DD
17
1 µF
470 pF
VMID
Generator
+
VMID Buffer
+
MICBIAS
20
–
–
2 kΩ
10 kΩ
MICGS
19
Microphone Amplifier
3.3 µF
MICIN
18
+
–
+
To Transmit Filters
10 kΩ
Electret
Microphone
MICMUTE
6
TCM320AC36/37 VBAP
NOTE A: Terminal numbers shown are for the DW and N packages.
Figure 5. Typical Microphone Interface
microphone mute function
The MICMUTE input causes the digital circuitry to transmit all zero code on DOUT.
transmit filter
A low-pass antialiasing section is included on the device and achieves a 35-dB attenuation at the sampling
frequency. No external components are required to provide the necessary antialiasing function for the
switched-capacitor section of the transmit filter.
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAP )
SLWS003C – MAY 1992 – REVISED APRIL – 1998
PRINCIPLES OF OPERATION
encoding
The encoder internally samples the output of the transmit filter and holds each sample on an internal
sample-and-hold capacitor. The encoder performs an A/D conversion on a switched-capacitor array. Digital
data representing the sample is transmitted on the first 8 or 16 data clock cycles of the next frame.
The autozero circuit corrects for dc offset on the input signal to the encoder using the sign-bit averaging
technique. The sign bit from the encoder output is long-term averaged and subtracted from the input to the
encoder.
data word structure
The data word is eight bits long in the companded mode and all eight bits represent one audio data sample.
The sign bit is the first bit transmitted.
The data word is 16 bits long in the linear mode. The first 13 bits comprise the audio data sample, and the last
three bits form the volume control word in the receive direction (DIN) and are zero pad bits in the transmit
direction (DOUT). The sign bit is transmitted first.
receive operation
decoding
In the companded mode, the serial data word is received at DIN on the first eight clock cycles in fixed-data rate
and on the last eight clock cycles in variable-data rate. In the linear mode, the serial data word is received at
DIN on the first 13 clock cycles. D/A conversion is performed, and the corresponding analog sample is held on
an internal sample-and-hold capacitor. This sample is transferred to the receive filter.
receive filter
The receive section of the filter provides pass-band flatness and stop-band rejection that approximates both
the AT&T D3/D4 specification and CCITT recommendation G.712 when operated at the recommended
frequencies. The filter contains the required compensation for the (sin x)/x response of such decoders.
receive buffer
The receive buffer contains the volume control.
earphone amplifier
The earphone audio-output amplifier has a balanced output, as shown in Figure 6, to allow maximum flexibility
in output configuration. The output amplifier is designed to directly drive a piezo earphone in the differential
configuration without any additional external components. The output can also be used to drive a single-ended
load with the output signal voltage centered around V /2.
CC
The receive-channel output level can be adjusted between specified limits by connecting an external resistor
network to EARGS.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAP )
SLWS003C – MAY 1992 – REVISED APRIL – 1998
PRINCIPLES OF OPERATION
–
+
4
2
EARGS
EARA
_
+
IN
_
+
3
EARB
VMID
NOTE A: Terminal numbers shown are for the DW and N packages.
Figure 6. Earphone Audio-Output Amplifier Configuration and Internal Gain-Setting Network
receive data format
In the companded mode, eight bits of data are received. The sign bit is the first bit received (see Table 2).
In the linear mode, 16 bits of data are received. The first 13 bits are the D/A code, and the remaining three bits
form the volume control word (see Table 2). The volume control function is actually an attenuation control in
which the first bit received is the most significant. The maximum volume occurs when all three volume control
bits are zero. Eight levels of attenuation are selectable in 3-dB steps, giving a maximum attenuation of 21 dB
when all bits are 1s. The volume control bits are not latched into the VBAP and must be present in each received
data word.
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAP )
SLWS003C – MAY 1992 – REVISED APRIL – 1998
PRINCIPLES OF OPERATION
Table 2. Receive-Data Bit Definitions
BIT NO.
COMPANDED MODE
LINEAR MODE
LD12
LD11
LD10
LD9
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
CD7
CD6
CD5
CD4
CD3
CD2
CD1
CD0
–
LD8
LD7
LD6
LD5
LD4
–
LD3
–
LD2
–
LD1
–
LD0
–
V2
–
V1
–
V0
Volume control and other control bits always follow the PCM data in time:
Companded Mode:
MSB
(sign bit)
LSB
CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0
Companded Data
Linear Mode:
MSB
(sign bit)
LSB
LD12 LD11 LD10 LD9 LD8 LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0
V2
V1
V0
Linear Data
Time
Volume Control
where:
CD7–CD0 = Data word when in companded mode
LD12–LD0= Data word when in linear mode
V2, V1, V0 = Volume (attenuation control) 000 = maximum volume, 3 dBm0
111 = minimum volume, –18 dBm0
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAP )
SLWS003C – MAY 1992 – REVISED APRIL – 1998
APPLICATION INFORMATION
output gain set design considerations (see Figure 7)
EARA and EARB are low-impedance complementary outputs. The voltages at the nodes are:
V
V
V
at EARA
at EARB
O+
O–
OD
= V
– V
(total differential response)
O–
O+
R1 and R2 are a gain-setting resistor network with the center tap connected to EARGS.
A value greater than 10 kΩ and less than 100 kΩ for R1 + R2 is recommended because of the following:
The parallel combination R1 + R2 and R sets the total loading. The total capacitance at EARGS and the
L
parallel combination of R1 and R2 define a time constant that has to be minimized to avoid inaccuracies.
V represents the maximum available digital mW output response (V = 0.751 Vrms).
A
A
V
= A × V
A
OD
1 + (R1/R2)
4 + (R1/R2)
where A =
2
4
3
V
V
EARA
EARGS
EARB
O+
R1
R2
Digital mW Sequence
IAW CCITT G.712
DIN
V
O
R
L
O–
NOTE A: Terminal numbers shown are for the DW and N packages.
Figure 7. Gain-Setting Configuration
higher clock frequencies and sample rates
The VBAP is designed to work with sample rates up to 16 kHz where the frequency of the frame sync determines
the sampling frequency. However, there is a fundamental requirement to maintain the ratio of the master clock
frequency, f
, to the frame sync frequency, f
/f
. This ratio for the VBAP is 2.048 MHz/8 kHz, or 256
CLK
FSR FSX
master clocks per frame sync. For example, to operate the VBAP at a sampling rate of f
and f
equal to
FSR
FSX
16 kHz, f
must be 256 times 16 kHz, or 4.096 MHz. If the VBAP is operated above an 8-kHz sample rate,
CLK
however, it is expected that the performance becomes somewhat degraded. Exact parametric specifications
for rates up to 16-kHz sample rate are not specified at this time.
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAP )
SLWS003C – MAY 1992 – REVISED APRIL – 1998
MECHANICAL DATA
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PIN SHOWN
PINS **
0.050 (1,27)
16
20
24
28
DIM
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
0.410
0.510
0.610
0.710
A MAX
(10,41) (12,95) (15,49) (18,03)
16
9
0.400
0.500
0.600
0.700
A MIN
(10,16) (12,70) (15,24) (17,78)
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.293 (7,45)
Gage Plane
0.010 (0,25)
1
8
0°–8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.012 (0,30)
0.004 (0,10)
0.104 (2,65) MAX
4040000/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAP )
SLWS003C – MAY 1992 – REVISED APRIL – 1998
MECHANICAL DATA
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PIN SHOWN
PINS **
14
16
18
20
DIM
0.775
(19,69)
0.775
(19,69)
0.920
(23.37)
0.975
(24,77)
A MAX
A
16
9
0.745
(18,92)
0.745
(18,92)
0.850
(21.59)
0.940
(23,88)
A MIN
0.260 (6,60)
0.240 (6,10)
1
8
0.070 (1,78) MAX
0.020 (0,51) MIN
0.310 (7,87)
0.290 (7,37)
0.035 (0,89) MAX
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0°–15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
0.010 (0,25) NOM
14/18 PIN ONLY
4040049/C 08/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAP )
SLWS003C – MAY 1992 – REVISED APRIL – 1998
MECHANICAL DATA
PT (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
M
0,08
0,50
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
Gage Plane
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,45
1,35
0,75
0,45
Seating Plane
0,10
1,60 MAX
4040052/B 03/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-136
D. This may also be a thermally-enhanced plastic package with leads connected to the die pads.
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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