TCM320AC46_技术文档

ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢁꢇ ꢈ

ꢉ ꢊꢋꢊ ꢌꢆꢍ ꢎꢏꢐꢌꢏ ꢑꢒ ꢊꢓꢆꢐꢔ ꢕꢑ ꢓꢕ ꢋꢀ ꢊꢌꢖꢆꢁꢊꢓ ꢖꢑ ꢌ ꢓ ꢔꢒ ꢏ

ꢗ

SLWS001 − D4091, JUNE 1993

DW OR N PACKAGE

(TOP VIEW)

• Single 5-V Operation

• Low Power Consumption:

Operating Mode . . . 55 mW Typ

Standby Mode . . . 8 mW Typ

Power-Down Mode . . . 3 mW Typ

PDN

MICBIAS

MICGS

MICIN

VMID

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

EARA

EARB

EARGS

• Combined ADC, DAC, and Filters

V

GND

CC

• Extended Variable-Frequency Operation

MICMUTE

DCLKR

DIN

15 LINSEL

Pass-Band up to 10 kHz

14

13

12

11

TSX/DCLKX

DOUT

FSX

• Electret Microphone Bias Reference

FSR

Voltage Available

EARMUTE

CLK

• Directly Drives a Piezo Speaker

• Compatible With All DSPs

• Selectable Between 8-Bit, µ-Law

Companded and 13-Bit Linear Conversion

• Programmable Volume Control in Linear

Mode

• Designed for Standard 2.048-MHz Master

Clock for U.S. Analog, U.S. Digital, CT2,

Battery-Powered Telephones

description

The general-purpose audio interface for digital signal processors (DSPs) is designed to perform the transmit

encoding (A/D conversion) and receive decoding (D/A conversion) together with transmit and receive filtering

for voice-band audio systems. In particular, cellular telephone systems are targeted; however, this integrated

circuit can function in several systems, including digital audio, multimedia telecommunications, noise

cancellation, and other data acquisition.

The converted data is available in two formats. The formats are pin selectable between companded and linear.

When the device is in the companded mode, data is transmitted and received in eight-bit words. When the linear

mode is selected, 13 bits of data are sent and received, padded with trailing zeros or volume control bits to

provide a 16-bit word.

The transmit section is designed to directly interface with an electret microphone element. A reference voltage

equal to V /2, called VMID, is used to develop the midlevel virtual ground for all the amplifier circuits and the

CC

microphone bias circuit. A reference voltage called MICBIAS can be used to supply bias current for the

microphone. The microphone input signal (MICIN) is buffered and amplified with provision for setting the

amplifier gain to accommodate a range of signal input levels. The amplified signal is passed through antialiasing

and band-pass filters. The filtered signal is then input to a compressing analog-to-digital converter (COADC)

if companded mode is selected; otherwise, the analog-to-digital converter performs a linear conversion.

Caution. These devices have limited built-in protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ꢏ

ꢌ

ꢑ

ꢧ

ꢔ

ꢢ

ꢐ

ꢁ

ꢠ

ꢀ

ꢡ

ꢕ

ꢛ

ꢑ

ꢙ

ꢋ

ꢚ

ꢔ

ꢆ

ꢀ

ꢆ

ꢘ

ꢙ

ꢣ

ꢚ

ꢛ

ꢡ

ꢜ

ꢝ

ꢞ

ꢟ

ꢘ

ꢛ

ꢙ

ꢘ

ꢠ

ꢤ

ꢡ

ꢢ

ꢜ

ꢣ

ꢙ

ꢟ

ꢞ

ꢝ

ꢠ

ꢛ

ꢚ

ꢤ

ꢀꢣ

ꢢ

ꢥ

ꢠ

ꢦ

ꢘ

ꢡ

ꢞ

ꢠ

ꢟ

ꢘ

ꢟ

ꢛ

ꢜ

ꢙ

ꢢ

ꢧ

ꢞ

ꢙ

ꢟ

ꢣ

ꢠ

ꢨ

Copyright  1993, Texas Instruments Incorporated

ꢜ

ꢛ

ꢡ

ꢟ

ꢛ

ꢜ

ꢝ

ꢟ

ꢛ

ꢠ

ꢤ

ꢘ

ꢚ

ꢘ

ꢡ

ꢣ

ꢜ

ꢟ

ꢩ

ꢟ

ꢣ

ꢜ

ꢛ

ꢚ

ꢪ

ꢞ

ꢕ

ꢙ

ꢝ

ꢣ

ꢠ

ꢟ

ꢞ

ꢙ

ꢧ

ꢞ

ꢜ

ꢧ

ꢫ

ꢞ

ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ

ꢜ

ꢞ

ꢙ

ꢟ

ꢬ

ꢨ

ꢏ

ꢜ

ꢛ

ꢧ

ꢢ

ꢡ

ꢟ

ꢘ

ꢛ

ꢙ

ꢤ

ꢜ

ꢛ

ꢡ

ꢣ

ꢠ

ꢘ

ꢙ

ꢭ

ꢧ

ꢛ

ꢣ

ꢠ

ꢙ

ꢛ

ꢟ

ꢙ

ꢣ

ꢡ

ꢣ

ꢠ

ꢞ

ꢜ

ꢘ

ꢦ

ꢬ

ꢘ

ꢙ

ꢡ

ꢦ

ꢢ

ꢧ

ꢣ

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77001

ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢁ ꢇꢈ

ꢉꢊꢋ ꢊꢌ ꢆ ꢍ ꢎꢏꢐꢌ ꢏꢑ ꢒ ꢊꢓꢆꢐ ꢔꢕ ꢑ ꢓꢕ ꢋ ꢀꢊ ꢌ ꢖꢆꢁꢊ ꢓꢖ ꢑ ꢌꢓꢔ ꢒꢏ

ꢗ

SLWS001 − D4091, JUNE 1993

description (continued)

The receive section takes a frame of serial data on DIN and converts it to analog through an expanding

digital-to-analog converter (EXDAC) if the companded mode is selected; otherwise, a linear conversion is

performed. The analog signal then passes through switched-capacitor filters, which provide out-of-band

rejection, (sin x)/x correction functions, and smoothing. The filtered signal is sent to the earphone amplifier. The

earphone amplifier has a differential output with adjustable gain that is designed to minimize static power

dissipation.

A single on-chip, high-precision band-gap circuit generates all voltage references, eliminating the need for

external reference voltages.

The TCM320AC46 device is characterized for operation from 0°C to 70°C.

functional block diagram

LINSEL

15

6

Transmit

Third-Order

Antialias

Transmit

Sixth-Order

Low Pass

Transmit

First-Order

High Pass

MICMUTE

MICIN

13

12

Input

Buffer

Output

Logic

DOUT

FSX

ADC

18

19

MICGS

256 kHz

8 kHz

Band-Gap

Voltage

Reference

VMID

Autozero

A/D

17

20

Converter

Voltage

Reference

VMID

Generator

MICBIAS

14

TSX/DCLKX

CLK

256 kHz

8 kHz

11

7

Clock

Generator

Clock

Control

D/A

DCLKR

Converter

Voltage

Reference

9

256 kHz

FSR

2

EARA

EARB

3

Receive

Buffer

Receive

Filter

Input

Logic

8

Earphone

Amplifier

DIN

DAC

15

4

EARGS

10

EARMUTE

5

16

GND

1

LINSEL

V

PDN

CC

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77001

ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢁ ꢇꢈ

ꢉ ꢊꢋꢊ ꢌꢆꢍ ꢎꢏꢐꢌꢏ ꢑꢒ ꢊꢓꢆꢐꢔ ꢕꢑ ꢓꢕ ꢋꢀ ꢊꢌꢖꢆꢁꢊ ꢓ ꢖꢑ ꢌꢓ ꢔ ꢒꢏ

ꢗ

SLWS001 − D4091, JUNE 1993

Terminal Functions

NAME

CLK

I/O

DESCRIPTION

NO.

11

I

In the fixed-data-rate mode, CLK is the master clock input as well as the transmit and receive data clock input.

In the variable-data-rate mode, CLK serves only as the master clock input.

DCLKR

7

I

Selects fixed- or variable-data-rate operation. When DCLKR is connected to V , the device operates in the

CC

fixed-data-rate mode. When DCLKR is not connected to V , the device operates in the variable-data-rate mode

CC

and DCLKR becomes the receive data clock.

DIN

8

I

Receive data input. Input data is clocked in on consecutive negative transitions of the receive data clock, which

is CLK for a fixed data rate and DCLKR for a variable data rate.

DOUT

13

O

Transmit data output. Transmit data is clocked out on consecutive positive transitions of the transmit data clock,

which is CLK for a fixed data rate and DCLKX for a variable data rate.

EARA

EARB

EARGS

2

3

4

O

I

Earphone output. EARA forms a differential drive when used with the EARB signal.

Earphone output. EARB forms a differential drive when used with the EARA signal.

Earphone gain set input of feedback signal for the earphone output. The ratio of an external potential divider

network connected across EARA and EARB adjusts the power amplifier gain. Maximum gain occurs when

EARGS is connected to EARB, and minimum gain occurs when EARGS is connected to EARA. Earphone

frequency response correction is performed using an external RC filter.

EARMUTE

FSR

10

9

I

Earphone output mute control signal. When EARMUTE is low, the output amplifier is disabled and no audio is

sent to the earphone.

Frame synchronization clock input for receive channel. In the variable-data-rate mode, FSR must remain high

for the duration of the time slot. The receive channel enters the standby state when FSR is TTL low for five frames

or longer. The device enters a production test-mode condition when either FSR or FSX is held high for five frames

or longer.

FSX

12

I

Frame synchronization clock input for transmit channel. FSX operates independently of, but in an analogous

manner to, FSR. The transmit channel enters the standby state when FSX is low for five frames or longer. The

device enters a production test-mode condition when either FSX or FSR is held high for five frames or longer.

GND

16

15

Ground return for all internal analog and digital circuits

LINSEL

I

Linear selection input. When low, LINSEL selects linear coding/decoding. When high, LINSEL selects

companded coding/decoding. The companded mode is µ-law.

MICBIAS

MICGS

20

19

O

Bias voltage equal to VMID for the electret microphone

Output of the internal microphone amplifier. MICGS used as the feedback to set the microphone amplifier gain.

If sidetone is required, it is accomplished by connecting a series network between MICGS and EARGS.

MICIN

18

6

I

Electret microphone input to the internal microphone amplifier

MICMUTE

Microphone input mute control signal. When MICMUTE is active (low), the input amplifier is disabled, the

microphone current is switched off, and zero code is transmitted.

PDN

1

I

Power-down input. When low, the device powers down to reduce power consumption.

TSX/DCLKX

14

I/O Transmit time slot strobe (active-low output) or data clock (input) for the transmit channel. In the fixed-data-rate

mode, this is an open-drain output that pulls to ground and is used as an enable signal for a 3-state buffer. In

the variable-data-rate mode, DCLKX becomes the transmit data clock input.

V

CC

VMID

5

5-V supply voltage for all internal analog and digital circuits

17

O

V

/2 bias voltage reference. An external, low-leakage, high-frequency 1-µF capacitor should be connected

CC

to VMID for filtering.

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77001

ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢁ ꢇꢈ

ꢉꢊꢋ ꢊꢌ ꢆ ꢍ ꢎꢏꢐꢌ ꢏꢑ ꢒ ꢊꢓꢆꢐ ꢔꢕ ꢑ ꢓꢕ ꢋ ꢀꢊ ꢌ ꢖꢆꢁꢊ ꢓꢖ ꢑ ꢌꢓꢔ ꢒꢏ

ꢗ

SLWS001 − D4091, JUNE 1993

general information

system reliability features

The device should be powered up and initialized as follows:

1. GND is applied.

2. V

is applied.

CC

3. All clocks are connected.

4. TTL high is applied to PDN.

5. FSX and/or FSR synchronization pulses are applied.

Even though the device is heavily protected against latch-up, it is still possible to cause it to latch-up under

certain improper power conditions where excess current is forced into or out of one or more terminals. To assure

that latch-up will not occur, it is good design practice to put a reverse-biased Schottky diode between V

supply) and GND.

(power

CC

On the transmit channel, digital outputs DOUT and TSX are held in the high-impedance state for approximately

four frames (500 µs) after power up or application of V . After this delay, DOUT, TSX, and signaling are

CC

functional and occur in the proper time slot. The analog circuits on the transmit side require approximately 60

ms to reach their equilibrium value due to the autozero circuit settling time. To further enhance system integrity,

DOUT and TSX are placed in the high-impedance state after an interruption of CLK.

power-down and standby operations

To minimize power consumption, a power-down mode and three standby modes are provided.

For power down, an external low signal is applied to PDN. In the absence of a signal, PDN is internally pulled

up to a high logic level and the device remains active. In the power-down mode, the average power consumption

is reduced to 3 mW.

The standby modes give the user the options of putting the entire device on standby, putting only the transmit

channel on standby, or putting only the receive channel on standby. To place the entire device on standby, both

FSX and FSR are held low. For transmit-only operation, FSX is pulsed and FSR is held low. For receive-only

operation, FSR is pulsed and FSX is held low. In the standby mode with both transmit and receive on standby,

power consumption is reduced to 8 mW. See Table 1 for power-down and standby procedures.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77001

ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢁ ꢇꢈ

ꢉ ꢊꢋꢊ ꢌꢆꢍ ꢎꢏꢐꢌꢏ ꢑꢒ ꢊꢓꢆꢐꢔ ꢕꢑ ꢓꢕ ꢋꢀ ꢊꢌꢖꢆꢁꢊ ꢓ ꢖꢑ ꢌꢓ ꢔ ꢒꢏ

ꢗ

SLWS001 − D4091, JUNE 1993

Table 1. Power-Down and Standby Procedures

TYPICAL POWER

CONSUMPTION

DEVICE STATUS

PROCEDURE

DIGITAL OUTPUT STATUS

PDN = high,

FSX = pulses,

FSR = pulses

Power on

55 mW

Digital outputs active but not loaded

PDN = low,

FSX/FSR = X/X

Power down

3 mW

8 mW

TSX and DOUT in the high-impedance state

FSX = low,

FSR = low,

PDN = high

Entire device on standby

FSX = low,

FSR = pulses,

PDN = high

Only transmit on standby

Only receive on standby

20 mW

TSX and DOUT in the high-impedance state within 5 frames

Digital outputs active but not loaded

FSR = low,

FSX = pulses,

PDN = high

fixed-data-rate timing

Fixed-data-rate timing is selected by connecting DCLKR to V . It uses the master clock (CLK), frame

CC

synchronization clocks (FSX and FSR), and the TSX output. FSX and FSR are inputs that set the sampling

frequency. Data is transmitted on DOUT on the positive transitions of CLK following the rising edge of FSX. Data

is received on DIN on the falling edges of CLK following FSR. A D/A conversion is performed on the received

digital word, and the resulting analog sample is held on an internal sample-and-hold capacitor until transferred

to the receive filter. The data word is eight bits long in the companded mode and sixteen bits long in the linear

mode.

variable-data-rate timing

Variable-data-rate timing is selected by connecting DCLKR to the receive data clock. In this mode, the master

clock (CLK) controls the switched-capacitor filters, while data transfer into DIN and out of DOUT is controlled

by DCLKR and DCLKX, respectively. This allows the data to be transferred into and out of the device at any rate

up to the frequency of the master clock. DCLKR and DCLKX must be synchronous with CLK.

While the FSX input is high, data is transmitted from DOUT on consecutive positive transitions of DCLKX.

Similarly, while the FSR input is high, the data word is received at DIN on consecutive negative transitions of

DCLKR. The transmitted data word at DOUT is repeated in all remaining time slots in the frame as long as

DCLKX is pulsed and FSX is held high. This feature, which allows the data word to be transmitted more than

once per frame, is available only with variable-data-rate timing.

asynchronous operations

In order to avoid crosstalk problems associated with special interrupt circuits, the design includes separate

converters, filters, and voltage references on the transmit and receive sides to allow completely independent

operation of the two channels. In either timing mode, the master clock, data clock, and time slot strobe must

be synchronized at the beginning of each frame.

precision voltage references

A precision band-gap reference voltage is generated internally and is used to supply all the references required

for operation of both the transmit and receive channels. The gain in each channel is trimmed during the

manufacturing process. This process ensures very accurate, stable gain performance over variations in supply

voltage and device temperature.

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77001

ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢁ ꢇꢈ

ꢉꢊꢋ ꢊꢌ ꢆ ꢍ ꢎꢏꢐꢌ ꢏꢑ ꢒ ꢊꢓꢆꢐ ꢔꢕ ꢑ ꢓꢕ ꢋ ꢀꢊ ꢌ ꢖꢆꢁꢊ ꢓꢖ ꢑ ꢌꢓꢔ ꢒꢏ

ꢗ

SLWS001 − D4091, JUNE 1993

conversion laws

The TCM320AC46 provides µ-law companding operation. The linear mode utilizes a 13-bit 2s complement

format.

transmit operation

microphone input

The microphone input amplifier is designed to simplify interface to electret-type microphone elements as shown

in Figure 1. The VMID buffer circuit provides a voltage (MICBIAS) equal to V /2 as a reference for the

CC

microphone amplifier and a bias voltage to the electret microphone. The microphone amplifier output (MICGS)

is used in conjunction with a feedback network to the amplifier inverting input (MICIN) to set the amplifier gain.

VMID is brought out to provide a place to filter the VMID voltage.

microphone mute function

The MICMUTE input disables the microphone amplifier and attenuates the signal on the MICGS output to a level

that is 80 dB or more down from the signal on the MICIN input. MICMUTE also causes the digital circuitry to

transmit all zero code on DOUT.

VMID

17

VMID Reference

for Amplifiers

1 µF

VMID Buffer

VMID Generator

+

−

MICBIAS

20

2 kΩ

+

−

MICGS

>10 kΩ

19

Microphone Amplifier

0.1 µF

MICIN

18

−

+

To Transmit Filter

MICMUTE

6

Microcontroller

Electret

Microphone

TCM320AC46

Figure 1. Typical Microphone Interface

transmit filter

A low-pass antialiasing section is included on the device. This section provides 35-dB attenuation at the

sampling frequency. No external components are required to provide the necessary antialiasing function for the

switched-capacitor section of the transmit filter.

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77001

ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢁ ꢇꢈ

ꢉ ꢊꢋꢊ ꢌꢆꢍ ꢎꢏꢐꢌꢏ ꢑꢒ ꢊꢓꢆꢐꢔ ꢕꢑ ꢓꢕ ꢋꢀ ꢊꢌꢖꢆꢁꢊ ꢓ ꢖꢑ ꢌꢓ ꢔ ꢒꢏ

ꢗ

SLWS001 − D4091, JUNE 1993

encoding

The encoder internally samples the output of the transmit filter and holds each sample on an internal

sample-and-hold capacitor. The encoder performs an analog-to-digital conversion on a switched-capacitor

array. Digital data representing the sample is transmitted on the first eight or 16 data clock cycles of the next

frame.

The autozero circuit corrects for dc offset on the input signal to the encoder using the sign-bit averaging

technique. The sign bit from the encoder output is long-term averaged and subtracted from the input to the

encoder.

data word structure

The data word is eight bits long in the companded mode. All eight bits represent one audio data sample. The

sign bit is the first bit transmitted.

The data word is 16 bits long in the linear mode. The first 13 bits comprise the audio data sample, and the last

three bits are volume control in the receive direction (DIN) and zeros in the transmit direction (DOUT). The sign

bit is transmitted first.

receive operation

decoding

In the companded mode, the serial data word is received at DIN on the first eight clock cycles in fixed-data rate

and the last eight clock cycles in variable-data rate. The serial data word is received at DIN on the first 13 clock

cycles in the linear mode. Digital-to-analog conversion is performed, and the corresponding analog sample is

held on an internal sample-and-hold capacitor. This sample is transferred to the receive filter.

receive filter

The receive section of the filter provides pass-band flatness. The filter contains the required compensation for

the (sin x)/x response of such decoders.

receive buffer

The receive buffer contains the volume control.

earphone amplifier

The earphone amplifier has a balanced output to allow maximum flexibility in output configuration. The output

amplifier is designed to directly drive a piezo earphone in the differential configuration without any additional

external components. The output can also be used to drive a single-ended load with the output signal voltage

centered around V /2.

CC

The receive-channel output level can be adjusted between specified limits by connecting an external resistor

network to EARGS.

receive data format

Eight bits of data are received in the companded mode and are valid. The sign bit is the first bit received (see

Table 2).

Sixteen bits of data are received in the linear mode. The first 13 bits are the D/A code, and the remaining three

bits form the volume control word (see Table 2). The volume control function is actually an attenuation control

where the first bit received is the most significant. The maximum volume occurs when all three volume control

bits are zero. Eight levels of attenuation are selectable in 3-dB steps, giving a maximum attenuation of 21 dB,

when all bits are 1s. The volume control bits are not latched into the device and must be present in each received

data word.

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77001

ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢁ ꢇꢈ

ꢉꢊꢋ ꢊꢌ ꢆ ꢍ ꢎꢏꢐꢌ ꢏꢑ ꢒ ꢊꢓꢆꢐ ꢔꢕ ꢑ ꢓꢕ ꢋ ꢀꢊ ꢌ ꢖꢆꢁꢊ ꢓꢖ ꢑ ꢌꢓꢔ ꢒꢏ

ꢗ

SLWS001 − D4091, JUNE 1993

Table 2. Receive Data Bit Definitions

BIT NO.

COMPANDED MODE

LINEAR MODE

LD12

LD11

LD10

LD9

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

CD7

CD6

CD5

CD4

CD3

CD2

CD1

CD0

−

LD8

LD7

LD6

LD5

LD4

−

LD3

−

LD2

−

LD1

−

LD0

−

V2

−

V1

−

V0

relationship between data word and frame sync

Volume control and other control bits always follow the PCM data in time:

Bit No.

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

FSX/FSR

Fixed Data Rate

Variable Data Rate

FSX/FSR

Command Word

Companded Mode:

MSB

LSB

(sign bit)

CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0

Companded Data

Linear Mode: MSB

(sign bit)

LD12 LD11 LD10 LD9 LD8 LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0

LSB

V2

V1

V0

Volume Control

Linear Data

Time

where:

CD7−CD0 = Data word when in companded mode

−− = Unused bits in companded mode

V2, V1, V0 = Volume (attenuation control) 000 = maximum volume, 3 dBm0

111 = minimum volume, −18 dBm0

LD12−LD0= Data word when in linear mode

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77001

ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢁ ꢇꢈ

ꢉ ꢊꢋꢊ ꢌꢆꢍ ꢎꢏꢐꢌꢏ ꢑꢒ ꢊꢓꢆꢐꢔ ꢕꢑ ꢓꢕ ꢋꢀ ꢊꢌꢖꢆꢁꢊ ꢓ ꢖꢑ ꢌꢓ ꢔ ꢒꢏ

ꢗ

SLWS001 − D4091, JUNE 1993

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V

CC

Output voltage range at DOUT, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V

Input voltage rangeat DIN, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V

O

I

Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table

Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: Voltage value is with respect to GND.

DISSIPATION RATING TABLE

≤ 25°C DERATING FACTOR

T

A

T = 70°C

A

POWER RATING

PACKAGE

POWER RATING

ABOVE T = 25°C

A

DW

N

1025 mW

8.2 mW/°C

9.2 mW/°C

656 mW

1150 mW

736 mW

recommended operating conditions (see Note 2)

MIN

4.5

MAX

UNIT

V

Supply voltage, V

CC

(see Note 3)

5.5

High-level input voltage, V

IH

2.2

V

Low-level input voltage, V

IL

0.8

V

Load resistance between EARA and EARB, R (see Note 4)

50

Ω

L

Load capacitance between EARA and EARB, C (see Note 4)

113

70

nF

°C

L

Operating free-air temperature, T

0

A

NOTES: 2. To avoid possible damage to these CMOS devices and resulting reliability problems, the following sequence should be followed when

applying power:

1. Connect to GND.

2. Connect V

3. Connect the input signals.

.

CC

When removing power, follow the preceding steps in reverse order.

3. Voltages at analog inputs and outputs and V

are with respect to GND.

4. R and C should not be applied simultaneously.

CC

L

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

supply current, f

or f

= 2.048 MHz, outputs not loaded

DCLKR

DCLKX

PARAMETER

TEST CONDITIONS

MIN

MAX

14

UNIT

Operating

Power down

PDN is high with CLK signal present

PDN is low for 500 µs

1.5

2.5

10

I

Supply current from V

CC

mA

CC

Standby − both PDN is high with FSX and FSR missing for 500 µs

Standby − one PDN is high with FSX and FSR missing for 500 µs

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77001

ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢁ ꢇꢈ

ꢉꢊꢋ ꢊꢌ ꢆ ꢍ ꢎꢏꢐꢌ ꢏꢑ ꢒ ꢊꢓꢆꢐ ꢔꢕ ꢑ ꢓꢕ ꢋ ꢀꢊ ꢌ ꢖꢆꢁꢊ ꢓꢖ ꢑ ꢌꢓꢔ ꢒꢏ

ꢗ

SLWS001 − D4091, JUNE 1993

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted) (continued)

digital interface

†

PARAMETER

High-level output voltage

TEST CONDITIONS

MIN TYP

MAX

UNIT

V

I

= −3.2 mA,

= 3.2 mA,

V

= 5 V

2.4

4.6

0.2

OH

CC

DOUT

Low-level output voltage

High-level input current

Low-level input current

Input capacitance

0.4

20

V

OL

CC

I

Any digital input

V = 2.2 V to V

CC

µA

pF

IH

I

V = 0 to 0.8 V

IL

I

C

5

i

Output capacitance

o

‡

microphone interface

†

PARAMETER

Input offset voltage at MICIN

Input bias current at MICIN

TEST CONDITIONS

V = 0 to 5 V

MIN TYP

MAX

15

UNIT

mV

nA

V

IO

1

I

IB

200

B

Unity-gain bandwidth, open loop at MICIN

Input capacitance at MICIN

1

MHz

pF

C

5

i

A

V

Large-signal voltage amplification at MICGS

Output level at MICGS with MICMUTE active

10000

V/V

V = 4 V

I

−80 dBm0

VMID

MICBIAS

1

µA

I

Maximum output current

O(max)

mA

‡

speaker interface

†

PARAMETER

Input leakage at EARGS

AC output voltage peak-to-peak

TEST CONDITIONS

MIN TYP

MAX

300

3

UNIT

I

IL

V = 0 to 5 V

nA

I

V

PP

O(PP)

OO

V

Output offset voltage at EARA, EARB (single-ended) Relative to GND

Output resistance at EARA, EARB

100

1

mV

Ω

R

o

I

Maximum output current

Large-signal voltage amplification

Gain change

R

= 600 Ω

L

8

mA

V/V

dB

O(max)

A

4

V

EARMUTE low, max level when muted

−80

†

‡

All typical values are at V

CC

= 5 V, T = 25°C.

A

All parameters are measured between MICIN and GND (unless otherwise noted).

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77001

ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢁ ꢇꢈ

ꢉ ꢊꢋꢊ ꢌꢆꢍ ꢎꢏꢐꢌꢏ ꢑꢒ ꢊꢓꢆꢐꢔ ꢕꢑ ꢓꢕ ꢋꢀ ꢊꢌꢖꢆꢁꢊ ꢓ ꢖꢑ ꢌꢓ ꢔ ꢒꢏ

ꢗ

SLWS001 − D4091, JUNE 1993

transmit gain and dynamic range, companded or linear mode, µ-law or A-law, V

otherwise noted) (see Notes 5 and 6)

= 5 V, T = 25°C (unless

A

CC

PARAMETER

TEST CONDITIONS

Linear mode selected

MIN

MAX

1.001

0.982

4

UNIT

Transmit reference-signal level (0 dB) (see Note 7)

Vrms

Companded mode selected, µ-law

Linear mode selected

Overload-signal level

Absolute gain error

V

PP

Companded mode selected, µ-law

0-dB input signal

4

2

dB

MICIN to DOUT at 3 dBm0 to −40 dBm0

MICIN to DOUT at −41 dBm0 to −50 dBm0

MICIN to DOUT at −51 dBm0 to −55 dBm0

0.8

2

Gain error with input level relative to gain at −10 dB

Gain variation

dB

2.5

0.5

V

CC

10%,

T = 0°C to 70°C

A

transmit filter transfer, linear mode or µ-law selected, over recommended ranges of supply voltage and

free-air temperature, CLK = 2.048 MHz, FSX = 8 kHz (see Note 6)

PARAMETER

TEST CONDITIONS

Input signal = 50 Hz

MIN

−10

MAX

0

UNIT

Input signal = 200 Hz

Input signal = 300 Hz to 3 kHz

Input signal = 3.3 kHz

Input signal = 3.4 kHz

Input signal = 4 kHz

−1.8

0

0.35

0.2

0

Input amplifier set for unity gain,

noninverting maximum gain output signal

at MICIN is 0 dB

Gain relative to input signal gain at

1.02 kHz

−0.55

−2.8

dB

−11

Input signal ≥4.6 kHz

−30

transmit idle channel noise and distortion, companded mode, µ-law, over recommended ranges of supply

voltage and operating free-air temperature (see Note 8)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Transmit noise, C-message weighted

MICIN connected to MICGS through a 10-kΩ resistor

MICIN to DOUT at 0 dBm0 to −30 dBm0

MICIN to DOUT at −31 dBm0 to −40 dBm0

MICIN to DOUT at−41 dBm0 to −45 dBm0

27 dBrnC0

32

25

18

Transmit signal-to-distortion ratio with sine-wave input

dB

transmit idle channel noise and distortion, linear mode, over recommended ranges of supply voltage and

operating free-air temperature (see Notes 6 and 8)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Transmit noise

MICIN connected to MICGS through a 10-kΩ resistor

MICIN to DOUT at 0 dBm0 to −6 dBm0

MICIN to DOUT at −7 dBm0 to −12 dBm0

MICIN to DOUT at −13 dBm0 to −18 dBm0

MICIN to DOUT at −19 dBm0 to −24 dBm0

MICIN to DOUT at −25 dBm0 to −45 dBm0

−60

dB

47

42

38

30

15

Transmit signal-to-distortion ratio with sine-wave input

dB

NOTES: 5. Unless otherwise noted, the analog input is 0 dB, 1020-Hz sine wave, where 0 dB is defined as the zero-reference point of the channel

under test.

6. The input amplifier is set for inverting unity gain.

7. This reference-level signal, which is input to the transmit channel, is defined as a value 3 dB below the full-scale value of 2 V.

8. Transmit noise, linear mode: 200 µVrms is equivalent to −74 dB (referenced to device 0-dB level).

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77001

ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢁ ꢇꢈ

ꢉꢊꢋ ꢊꢌ ꢆ ꢍ ꢎꢏꢐꢌ ꢏꢑ ꢒ ꢊꢓꢆꢐ ꢔꢕ ꢑ ꢓꢕ ꢋ ꢀꢊ ꢌ ꢖꢆꢁꢊ ꢓꢖ ꢑ ꢌꢓꢔ ꢒꢏ

ꢗ

SLWS001 − D4091, JUNE 1993

receive gain and dynamic range, linear mode, µ-law or A-law, V

= 5 V, T = 25°C (unless otherwise noted)

A

CC

(see Notes 9 and 10)

PARAMETER

TEST CONDITIONS

Linear mode selected

MIN

MAX

0.751

0.736

3

UNIT

Receive reference-signal level (0 dB) (see Note 11)

Vrms

Companded mode selected, µ-law

Linear mode selected

Overload-signal level

Absolute gain error

V

PP

Companded mode selected, µ-law

0-dB input signal

3

2

dB

DIN to EARA and EARB at 3 dBm0 to −40 dBm0

DIN to EARA and EARB at −41 dBm0 to −50 dBm0

DIN to EARA and EARB at −51 dBm0 to −55 dBm0

0.8

2

Gain error with output level relative to gain at −10 dBm0

Gain variation

dB

2.5

0.5

V

CC

10%,

T = 0°C to 70°C

A

receive filter transfer over recommended ranges of supply voltage and operating free-air temperature (see

Note 8)

PARAMETER

TEST CONDITIONS

Input signal = < 200 Hz

MIN

MAX

0.35

0.2

UNIT

Input signal = 200 Hz

Input signal = 300 Hz to 3 kHz

Input signal = 3.3 kHz

Input signal = 3.4 kHz

Input signal = 4 kHz

−0.8

−0.55

−2

Gain relative to input signal gain at 1.02 kHz Input signal at DIN is 0 dBm0

dB

0

−11

−28

Input signal > 4.6 kHz

receive idle channel noise and distortion, companded mode, µ-law, over recommended ranges of supply

voltage and operating free-air temperature (see Note 8)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Receive noise, C-message weighted

DIN = 11111111

DIN to EARA and EARB at 0 dBm0 to −30 dBm0

17 dBrnC0

32

25

18

Receive signal-to-distortion ratio with sine-wave input DIN to EARA and EARB at −31 dBm0 to −40 dBm0

DIN to EARA and EARB at −41 dBm0 to −45 dBm0

dB

receive idle channel noise and distortion, linear mode over recommended ranges of supply voltage and

operating free-air temperature (see Note 8)

PARAMETER

TEST CONDITIONS

DIN = 00000000(linear)

MIN

MAX

UNIT

Receive noise

−60

dB

DIN to EARA and EARB at 0 dBm0 to −6 dBm0

DIN to EARA and EARB at −6 dBm0 to −12 dBm0

DIN to EARA and EARB at −13 dBm0 to −18 dBm0

DIN to EARA and EARB at −19 dBm0 to −24 dBm0

DIN to EARA and EARB at −25 dBm0 to −45 dBm0

48

42

38

30

14

Receive signal-to-distortion ratio with sine-wave input

dB

NOTES: 8. Transmit noise, linear mode: 200 µVrms is equivalent to −74 dB (referenced to device 0-dB level).

9. Receive output is measured differentially in the maximum gain configuration. To set the output amplifier for maximum gain, EARGS

is connected to EARB and the output is taken between EARA and EARB. All output levels are (sin x)/x corrected.

10. Unless otherwise noted, the digital input is a word stream generated by passing a 0-dB sine wave at 1020 Hz through an ideal encoder

where 0 dB is defined as the zero reference.

11. This reference-signal level is measured at the speaker output of the receive channel with the gain of the output speaker amplifier set

to unity.

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77001

ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢁ ꢇꢈ

ꢉ ꢊꢋꢊ ꢌꢆꢍ ꢎꢏꢐꢌꢏ ꢑꢒ ꢊꢓꢆꢐꢔ ꢕꢑ ꢓꢕ ꢋꢀ ꢊꢌꢖꢆꢁꢊ ꢓ ꢖꢑ ꢌꢓ ꢔ ꢒꢏ

ꢗ

SLWS001 − D4091, JUNE 1993

power supply rejection and crosstalk attenuation over recommended ranges of supply voltage and operating

free-air temperature

†

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT

Idle channel, supply signal = 100 mVrms,

f = 0 to 30 kHz (measured at DOUT)

Supply voltage rejection ratio, transmit channel

−30

dB

Idle channel, supply signal = 100 mVrms,

EARGS connected to EARB,

f = 0 to 30 kHz (measured differentially between EARA

and EARB)

Supply voltage rejection ratio, receive channel

dB

MICIN = 0 dB, f = 1.02 kHz, unity transmit gain,

EARGS connected to EARB,

measured differentially between EARA and EARB

Crosstalk attenuation, transmit-to-receive

(differential)

55

dB

DIN = 0 dBm0, f = 1.02 kHz, unity transmit

gain, measured at DOUT

Crosstalk attenuation, receive-to-transmit

†

All typical values are at V

CC

= 5 V, T = 25°C.

A

clock timing requirements over recommended ranges of supply voltage and operating free-air temperature

(see Figures 2, 3, 4, and 5)

†

MIN TYP

MAX

10

UNIT

t

Transition time, CLK and DCLK

Duty cycle, CLK

ns

45%

50%

55%

Duty cycle, DCLK

†

All typical values are at V

CC

= 5 V, T = 25°C.

A

transmit timing requirements over recommended ranges of supply voltage and operating free-air

temperature, fixed-data-rate mode (see Figure 3)

MIN

20

MAX

468

UNIT

ns

t

Setup time, FSX

Hold time, FSX

su(FSX)

20

468

ns

h(FSX)

receive timing requirements over recommended ranges of supply voltage and operating free-air

temperature, fixed-data-rate mode (see Figure 2)

MIN

20

MAX

468

UNIT

ns

t

Setup time, FSR

Hold time, FSR

Setup time, DIN

Hold time, DIN

su(FSR)

h(FSR)

su(DIN)

h(DIN)

20

468

ns

20

ns

20

ns

transmit timing requirements over recommended ranges of supply voltage and operating free-air

temperature, variable-data-rate mode (see Figure 5)

MIN

40

MAX

UNIT

ns

t

Setup time, FSX

Hold time, FSX

t

−40

−35

su(FSX)

c(DCLKX)

35

ns

h(FSX)

c(DCLKX)

13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77001

ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢁ ꢇꢈ

ꢉꢊꢋ ꢊꢌ ꢆ ꢍ ꢎꢏꢐꢌ ꢏꢑ ꢒ ꢊꢓꢆꢐ ꢔꢕ ꢑ ꢓꢕ ꢋ ꢀꢊ ꢌ ꢖꢆꢁꢊ ꢓꢖ ꢑ ꢌꢓꢔ ꢒꢏ

ꢗ

SLWS001 − D4091, JUNE 1993

receive timing requirements over recommended ranges of supply voltage and operating free-air

temperature, variable-data-rate mode (see Figure 4)

MIN

40

MAX

UNIT

ns

t

Setup time, FSR

Hold time, FSR

Setup time, DIN

Hold time, DIN

su(FSR)

h(FSR)

su(DIN)

h(DIN)

35

t

−35

ns

c(DCLKR)

30

ns

30

ns

propagation delay times over recommended ranges of operating conditions, fixed-data-rate mode,

C = 0 to 10 pF (see Figures 2 and 3)

L

TEST CONDITIONS

MIN

MAX

35

UNIT

ns

t

From CLK bIt 1 high to DOUT bit 1 valid

From CLK high to DOUT valid, bits 2 to n

From CLK bit n low to DOUT bit n Hi-Z

From CLK bit 1 high to TSX active (low)

From CLK bit n low to FSX inactive (high)

pd1

pd2

pd3

pd4

pd5

35

ns

30

ns

R

= 1.24 kΩ

40

ns

pullup

ns

propagation delay times over recommended ranges of operating conditions, variable-data-rate mode (see

Figures 4 and 5)

TEST CONDITIONS

MIN

MAX

30

UNIT

ns

t

FSX high to DOUT bit 1 valid

DCLKX high to DOUT valid, bits 2 to n

FSX low to DOUT bit n Hi-Z

C

= 0 to 10 pF

pd6

pd7

pd8

L

40

ns

20

ns

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77001

ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢁ ꢇꢈ

ꢉ ꢊꢋꢊ ꢌꢆꢍ ꢎꢏꢐꢌꢏ ꢑꢒ ꢊꢓꢆꢐꢔ ꢕꢑ ꢓꢕ ꢋꢀ ꢊꢌꢖꢆꢁꢊ ꢓ ꢖꢑ ꢌꢓ ꢔ ꢒꢏ

ꢗ

SLWS001 − D4091, JUNE 1993

PARAMETER MEASUREMENT INFORMATION

All timing parameters are referenced to V and V . Bit 1 = MSB (most significant bit) and is clocked in first on DIN

IH

IL

or clocked out first on DOUT. Bit n = LSB (least significant bit) and is clocked in last on DIN or is clocked out last on

DOUT. N = 8 for the companded mode, and N = 16 for the linear mode.

Receive Time Slot

0

1

2

3

4

N−2

N−1

N

N+1

80%

CLK

FSR

20%

t

su(FSR)

t

h(FSR)

80%

20%

See Note B

See Note A

2

t

h(DIN)

N−1

N

1

3

4

N−2

N

1

DIN

See Note C

t

su(DIN)

NOTES: A. This window is allowed for FSR high.

B. This window is allowed for FSR low.

C. Transitions are measured at 50%.

Figure 2. Fixed-Data-Rate, Receive Side Timing Diagram

Transmit Time Slot

0

1

2

3

4

N−2

N−1

N

N+1

CLK

80%

20%

t

su(FSX)

t

h(FSX)

80%

FSX

20%

See Note B

See Note A

1

t

pd2

pd3

2

3

N−2

N−1

N

DOUT

See Note C

t

pd1

t

pd5

t

pd4

80%

TSX

20%

NOTES: A. This window is allowed for FSX high.

B. This window is allowed for FSX low (t

C. Transitions are measured at 50%.

max determined by data collision considerations).

h(FSX)

Figure 3. Fixed-Data-Rate, Transmit Side Timing Diagram

15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77001

ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢁ ꢇꢈ

ꢉꢊꢋ ꢊꢌ ꢆ ꢍ ꢎꢏꢐꢌ ꢏꢑ ꢒ ꢊꢓꢆꢐ ꢔꢕ ꢑ ꢓꢕ ꢋ ꢀꢊ ꢌ ꢖꢆꢁꢊ ꢓꢖ ꢑ ꢌꢓꢔ ꢒꢏ

ꢗ

SLWS001 − D4091, JUNE 1993

PARAMETER MEASUREMENT INFORMATION

Receive Time Slot

0

1

2

3

4

N−2

20%

N−1

N

N+1

80%

DCLKR

20%

t

c(DCLKR)

t

su(FSR)

h(FSR)

FSR

20%

See Note B

N−1

See Note A

N

t

h(DIN)

N−1

See Note C

1

2

3

4

N−2

N

1

DIN

t

su(DIN)

NOTES: A. This window is allowed for FSR high (t

B. This window is allowed for FSR low.

C. Transitions are measured at 50%.

max determined by data collision considerations).

su(FSR)

Figure 4. Variable-Data-Rate, Receive Side Timing Diagram

Transmit Time Slot

0

1

2

3

4

N−2

N−1

N

N+1

80%

20%

DCLKX

FSX

t

h(FSX)

t

c(DCLKR)

su(FSX)

80%

t

pd7

See Note A

See Note B

t

pd8

t

pd6

2

DOUT

1

3

4

N−2

N−1

N

See Note C

NOTES: A. This window is allowed for FSX high.

B. This window is allowed for FSX low without data repetition.

C. Transitions are measured at 50%.

Figure 5. Variable-Data-Rate, Transmit Side Timing Diagram

APPLICATION INFORMATION

output gain set design considerations (see Figure 6)

EARA and EARB are low-impedance complementary outputs. The voltages at the nodes are:

V

at EARA

at EARB

O+

O−

OD

= V

− V

(total differential response)

O+

O−

R1 and R2 are a gain-setting resistor network with the center tap connected to EARGS.

A value greater than 10 kΩ and less than 100 kΩ for R1 + R2 is recommended because of the following:

The parallel combination R1 + R2 and R sets the total loading. The total capacitance at EARGS and the

L

parallel combination of R1 and R2 define a time constant that has to be minimized to avoid inaccuracies.

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77001

ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢁ ꢇꢈ

ꢉ ꢊꢋꢊ ꢌꢆꢍ ꢎꢏꢐꢌꢏ ꢑꢒ ꢊꢓꢆꢐꢔ ꢕꢑ ꢓꢕ ꢋꢀ ꢊꢌꢖꢆꢁꢊ ꢓ ꢖꢑ ꢌꢓ ꢔ ꢒꢏ

ꢗ

SLWS001 − D4091, JUNE 1993

APPLICATION INFORMATION

V represents the maximum available digital mW output response (V = 1.06 Vrms).

A

V

= A × V

A

OD

1 + (R1/R2)

4 + (R1/R2)

where A =

2

4

3

EARA

EARGS

EARB

R1

R2

Digital mW Sequence

Per CCITT G.712

DIN

R

V

O

L

V

O+

V

O−

Figure 6. Gain-Setting Configuration

higher clock frequencies and sample rates

The TCM320AC46 is designed to work with sample rates up to 24 kHz where the frequency of the frame sync

determines the sampling frequency. However, there is a fundamental requirement to maintain the ratio of master

clock frequency, f

, to frame sync frequency, f

/f

. This ratio for the device is 2.048 MHz/8 kHz or 256

CLK

FSR FSX

master clocks per frame sync. For example, to operate the TCM320AC46 at a sampling rate of f

and f

FSX

FSR

equal to 16 kHz, f

must be 256 times 16 kHz, or 4.096 MHz. If the TCM320AC46 is operated above an 8-kHz

CLK

sample rate, however, it is expected that the performance will be degraded.

17

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77001

ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢁ ꢇꢈ

ꢉꢊꢋ ꢊꢌ ꢆ ꢍ ꢎꢏꢐꢌ ꢏꢑ ꢒ ꢊꢓꢆꢐ ꢔꢕ ꢑ ꢓꢕ ꢋ ꢀꢊ ꢌ ꢖꢆꢁꢊ ꢓꢖ ꢑ ꢌꢓꢔ ꢒꢏ

ꢗ

SLWS001 − D4091, JUNE 1993

18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77001

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,

and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are

sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

applications using TI components. To minimize the risks associated with customer products and applications, customers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,

or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information

published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a

warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual

property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied

by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive

business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional

restrictions.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all

express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not

responsible or liable for any such statements.

TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably

be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing

such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and

acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products

and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be

provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in

such safety-critical applications.

TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are

specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military

specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at

the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.

TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are

designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated

products in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Applications

Audio

Automotive

Broadband

Digital Control

Medical

Amplifiers

Data Converters

DSP

Clocks and Timers

Interface

amplifier.ti.com

dataconverter.ti.com

dsp.ti.com

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/audio

www.ti.com/automotive

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/medical

www.ti.com/military

Logic

Military

Power Mgmt

Microcontrollers

RFID

power.ti.com

microcontroller.ti.com

www.ti-rfid.com

Optical Networking

Security

Telephony

Video & Imaging

Wireless

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

RF/IF and ZigBee® Solutions www.ti.com/lprf

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TCM320AC46
厂家：	TEXAS INSTRUMENTS
描述：	GEBERAL-PURPOSE AUDIO INTERFACE FOR DSP GEBERAL ，通用音频接口， DSP
文件：	总19页 (文件大小：254K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TCM320AC46 [TI]

相关型号：

TCM320AC46CDW

TCM320AC46CDWR

TCM320AC46CN

TCM320AC46CN

TCM320AC46DW

TCM320AC46DWR

TCM320AC46IDW

TCM320AC46IDW

TCM320AC46N

TCM320AC54

TCM320AC54CDW

TCM320AC54CDWR