TCM4400ETQFP_技术文档

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

Applications Include GSM 900,

PCS 1900, and DCS 1800 Cellular

Telephones

80-Pin TQFP (0.4 mm or 0.5 mm Lead

Pitch) or 80-Ball MicroStar BGA

Packages

MCU and DSP Serial Interface

Five Ports Auxiliary A/D

Meets JTAG Testability Standard (IEEE

Std 1131.1-1990)

Baseband Codec-GMSK Modulator

With On-Chip Burst Buffer

Voice Codec Features: Microphone

Amplifier and Bias Source,

Single 3-V Supply Voltage

Internal Voltage Reference

Extended RF Control Voltages

Advanced Power Management

GSM-Digital Audio Interface (DAI)

Programmable Gain Amplifiers, Volume

Control, and Side-Tone Control

description

The TCM4400E global system for mobile communication (GSM) baseband RF interface circuit is designed for

GSM 900 , PCS1900, and DCS 1800 European digital cellular telecommunication systems. It performs the

interface and processing of voice signals, generates baseband in-phase (I) and quadrature (Q) signals, and

controls the signals between a digital signal processor (DSP) and associated RF circuits.

The TCM4400E includes a second serial interface for use with a microcontroller. Through this interface, a

microcontroller can access all the internal registers that can be accessed through the DSP digital serial

interface. This option is intended for applications in which part of the L1 software is implemented in the

microcontroller.

A four-pin parallel port is dedicated to the full control of the digital audio interface (DAI) to the GSM system

simulator; the DAI consists of system simulator reset (SSRST) control, clock generation, and rate adaptation

with the DSP.

The voice processing portion of the device includes microphone and earphone amplifiers, analog-to-digital

(A/D) and digital-to-analog (D/A) converters, speech digital filtering, and a serial port.

The baseband processing portion of the device includes a two-channel uplink path, a two-channel downlink

path, a serial port, and a parallel port. The uplink path performs Gaussian minimum shift keying (GMSK)

modulation and D/A conversion, and it has smoothing filters to provide the external RF circuit with I and Q

baseband signals. The downlink path performs antialiasing, A/D conversion, and channel separation filtering

of the baseband I and Q signals. The serial port allows baseband data exchange with the DSP, and the parallel

port controls precise timing signals.

Auxiliary RF functions such as automatic frequency control (AFC), automatic gain control (AGC), power control,

and analog monitoring are also implemented in the TCM4400E. Internal functional blocks of the device can be

separately and automatically powered down with GSM RF windows.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

MicroStar BGA is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

80-Pin TQFP PACKAGE

(TOP VIEW)

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

BFSX

BCLKX

BDX

BDR

BCLKR

BFSR

BULIP

BULIN

BULQP

BULQN

1

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

2

3

4

AV

5

DD2

AV

6

SS2

AV

BDLIN

BDLIP

BDLQN

BDLQP

VMID

7

DD1

V

8

REF

IBIAS

VGAP

9

10

11

12

13

14

15

16

17

18

19

20

AV

SS1

RESET

DV

SS3

VFS

VDX

VDR

AV

SS3

APC

AFC

AGC

ADCMID

VCLK

SSRST

SSDX

SSDR

SSCLK

AV

DD5

DV

DD3

AV

DD3

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

GGM PACKAGE

(TOP VIEW)

K

J

K2

J2

K3

J3

K4

J4

H4

K5

J5

H5

K6

J6

H6

K7

J7

H7

K8

J8

K9

J9

NC

J1

NC

J10

H10

G10

F10

E10

D10

C10

B10

AV

DD3

SSCLK

DV

DD3

AV

SS4

TRST

SSDX

ADCMID

AGC

H

H1

G1

F1

E1

D1

C1

B1

H2

G2

F2

H3

G3

F3

H8

G8

F8

E8

D8

C8

B8

A8

H9

G9

F9

E9

D9

C9

B9

SSDR

MICIN

AV

DD5

AFC

APC

VDR

G

F

AV

VCLK

SSRST

RESET

SS3

VMID

DV

SS3

VFS

VDX

IBIAS

BDLQP

BDLIN

BDLQN

E

E2

D2

E3

D3

AV

SS1

BFSR

BDLIP

AV

DD2

SS2

AV

D

C

B

A

DD1

V

REF

BDR

TCK

BULQP

BCLKR

C2

B2

C3

B3

A3

C4

B4

A4

C5

B5

A5

C6

B6

C7

B7

A7

BDX

BFSX

TDI

BULIP

BCLKX

MCLK

TDO

NC

1

A2

2

A6

6

A9

9

NC

10

3

4

5

7

8

NC – No internal connection

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

functional block diagram

45

47

Auxiliary DAC

Analog AGC

AGC

APC

GSM Windows

Timing

Interface

Main Clock

Generator

JTAG

Interface

Power

Management

APC (D/A)

RF TX Ramp

60

75

78

76

77

BULIP

USEL

UCLK

UDX

Baseband Uplink GMSK Modulator

Internal Burst RAM

Automatic Offset Compensation

8-Bit DAC and Smoothing Filter

MCU

Serial

Interface

59

57

BULIN

BULQN

58

UDR

BULQP

Bus

Controller

1

3

2

6

4

BFSX

BDX

53

54

52

51

BDLIP

BDLIN

BDLQN

BDLQP

DSP

Serial

Interface

Baseband Downlink I/Q Path

Automatic Offset Compensation

10-Bit ADC and Antialiasing Filter

BCLKX

BFSR

BDR

5

BCLKR

AGC, AFC

APC Output

Swing Control

43

46

AV

DD5

16

13

14

15

VCLK

VFS

Voiceband

Serial

Interface

Voice Uplink 13 Bit ADC

Two Analog Inputs

Programmable Gain

Bandpass Digital Filter

VDX

VDR

AFC (D/A)

VTCXO Control

AFC

Side-tone

36

37

38

39

40

ADIN1

ADIN2

ADIN3

ADIN4

ADIN5

Voice Downlink 13 Bit DAC

Auxiliary Earphone Output

Programmable Volume

Smoothing Filter

20

17

18

19

SSCLK

SSRST

SSDX

Auxiliary

10 Bits

5 Inputs ADC

I

-V

VMID

Bias

REF REF

DAI

Interface

Bandpass Digital Filter

SSDR

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

Terminal Functions

TERMINAL

NO.

QFP BGA

I/O

DESCRIPTION

NAME

ADCMID

ADIN1

ADIN2

ADIN3

ADIN4

ADIN5

AFC

44

36

37

38

39

40

46

45

47

29

34

7

H8

J7

I/O Reference voltage of auxiliary A/D converters; decoupling only (analog)

I

Auxiliary 10-bit ADC input 1 (analog)

H7

K8

J8

Auxiliary 10-bit ADC input 2 (analog)

I

Auxiliary 10-bit ADC input 5 (analog)

I

Auxiliary 10-bit ADC input 4 (analog)

K9

G9

H10

G10

K5

H6

D1

D9

J9

I

Auxiliary 10-bit ADC input 3 (analog)

O

I

Automatic frequency control DAC output (analog)

Automatic gain control DAC output (analog)

AGC

APC

Automatic power control DAC output (analog)

AUXI

Auxiliary (high-level) speech signal input (analog)

Auxiliary downlink (voice codec) amplifier output, single-ended (analog)

Analog positive power supply (bandgap, internal common-mode generator, bias current generator).

Analog positive power supply (baseband CODEC)

Analog positive power supply (auxiliary RF functions)

Analog positive power supply (voice codec)

AUXO

O

AV

DD1

DD2

DD3

DD4

DD5

SS1

SS2

SS3

SS4

56

41

30

43

11

55

48

31

72

5

J5

H9

E3

D10

G8

H5

A5

C1

B1

C3

C2

C6

C5

D2

B2

E8

E9

E10

F8

Analog positive power supply (output stages of auxiliary RF functions).

Analog negative power supply (bandgap, internal common-mode generator, bias current generator).

Analog negative power supply (baseband CODEC)

Analog negative power supply (auxiliary RF functions)

Analog negative power supply (voice codec)

BCAL

I

Baseband uplink or downlink offset calibration enable (timing interface)

BCLKR

BCLKX

BDR

I/O DSP serial interface clock input. This clock signal is provided by the DSP or the TCM4400E (digital/3-state).

2

O

I

DSP serial interface clock output. The frequency is the same as MCLK (digital/3-state).

DSP serial interface serial data input (digital)

4

BDX

3

O

I

DSP serial interface serial data output (digital/3-state)

BENA

BDLON

BFSR

71

74

6

Burst transmit or receive enable (depends on status of BULON and BDLON) (digital)

Power on of baseband downlink (timing interface)

I

DSP serial interface receive frame synchronization input (digital)

DSP serial interface transmit frame synchronization output (digital/3-state)

In-phase baseband input (–) downlink path (analog)

BFSX

1

O

I

BDLIN

BDLIP

BDLQN

BDLQP

BULIN

BULIP

BULON

BULQN

BULQP

54

53

52

51

59

60

73

57

58

80

66

42

I

In-phase baseband input (+) downlink path (analog)

I

Quadrature baseband input (–) downlink path (analog)

Quadrature baseband input (+) downlink path (analog)

In-phase baseband output (–) uplink path (analog)

I

C9

B10

B5

D8

C10

A2

B7

J10

O

I

In-phase baseband output (+) uplink path (analog)

Serial clock input (serial interface) (digital)

O

Negative quadrature baseband output. BULQN is an uplink path (analog)

Positive quadrature baseband output. BULQN is an uplink path (analog)

Digital positive power supply (baseband and timing serial interfaces)

Digital positive power supply (baseband CODEC)

DV

DD1

DD2

DD3

Digital positive power supply (auxiliary RF functions)

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

Terminal Functions (Continued)

TERMINAL

NO.

QFP BGA

I/O

DESCRIPTION

NAME

DV

21

79

J2

Digital positive power supply (voiceband codec and serial interface)

Digital negative power supply (baseband and timing serial interfaces)

DD4

SS1

DV

B3

DV

65

49

22

33

32

25

35

9

A8

F10

K2

J6

Digital negative power supply (baseband CODEC)

Digital negative power supply (auxiliary RF functions)

Digital negative power supply (voiceband codec and serial interface)

Earphone amplifier output (–) (analog)

SS2

SS3

SS4

EARN

O

EARP

K6

K3

K7

E1

B6

J4

Earphone amplifier output (+) (analog)

GNDA1

GNDA2

IBIAS

Analog signal ground for the microphone amplifier and auxiliary input

Signal return (ground) for AUXO output

I/O Internal bias reference current adjust. IBIAS adjusts the reference current with an external resistor (analog).

MCLK

70

26

I

Master system clock input (13 MHz)

MICBIAS

Microphone bias supply output. MICBIAS is also used to decouple bias supply with an external capacitor

(analog).

MICIP

MICIN

PWRDN

RESET

SSCLK

SSDR

SSDX

SSRST

TCK

27

28

23

12

20

19

18

17

64

63

62

69

68

67

61

24

78

77

76

75

16

15

14

13

10

50

K4

H4

J3

I

Positive microphone amplifier input (analog)

Negative microphone amplifier input (analog)

Power-down mode control input (digital), active high

Device global hardware reset (digital), active low

DAI external 104 kHz clock output (digital)

I

F1

J1

I

O

I

H2

H1

G3

C8

B8

A9

A6

C7

A7

B9

H3

A3

C4

B4

A4

G2

G1

F3

F2

E2

F9

DAI data transfer input. SSDR connects to GSM-SS TDAI (digital/pullup).

DAI data transfer output SSDX connects to GSM-SS RDAI (digital).

DAI reset input (digital/pullup)

O

I

Scan test clock (digital/pulldown)

TDI

I

Scan path input (for testing purposes) (digital/pullup)

Scan path output (for testing purposes) (digital/3-state)

TDO

I

TEST1

TEST2

TEST3

TMS

I/O Test I/O (digital/3-state & pullup)

O

I

Test output (digital)

JTAG test mode select (digital/pullup)

TRST

UCLK

UDR

I

JTAG serial interface & boundary scan register reset (digital/pullup), active low.

MCU interface clock input (digital)

I

MCU interface data transfer input (digital)

UDX

O

I

MCU interface data transfer output (digital/3-state)

MCU serial interface select (digital)

USEL

VCLK

VDR

O

I

Voiceband serial interface clock output (digital/3-state)

Voiceband serial interface receive data input (digital)

Voiceband serial interface transmit data output (digital/3-state)

Voiceband serial interface transmit frame synchronization output (digital/3-state)

VDX

O

VFS

VGAP

VMID

I/O Bandgap reference voltage. VGAP decouples with an external capacitor (analog)

O

Baseband uplink midrail voltage output. VMID serves as a reference common-mode voltage for a RF device

when directly dc coupled (analog)

V

REF

8

D3

I/O Reference voltage V decouples with an external capacitor (analog).

REF

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, AV , DV

Maximum voltage on any input, V max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to 6 V

DD

I

+0.3 V / V –0.3 V

SS

DD

Storage temperature, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

J

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: Voltage measurements with respect to GND.

recommended operating conditions

MIN NOM

MAX

3.3

UNIT

Vdc

°C

Supply voltage range (AV , DV

DD

)

2.7

–25

3.0

DD

Operating temperature range

85

Digital I/O voltage with respect to DV

SS

–0.3

DV

AV

+ 0.3

Vdc

V

DD

Analog I/O voltage with respect to AV

+ 0.3

SS

DD

Difference between any AV

DD

or DV

0.3

V

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

digital inputs and outputs

PARAMETER

Low-level output current with digital pad lower than 0.1 V (CMOS)

Low-level output current with digital pad lower than 0.4 V (TTL)

MIN

0

TYP

MAX

40

1

UNIT

µA

mA

µA

mA

V

0

High-level output current with digital pad higher than V –0.1 V (CMOS)

DD

–40

–1

0

High-level output current with digital pad higher than V –0.4 V (TTL)

DD

0

Minimum high-level input voltage, V

V

–0.3

dd

IH

IL

Maximum low level input voltage, V

Vss+0.3

15

V

Output current on high impedance state outputs

Input current (any input) when input high

–15

–1

µA

Input current (standard inputs) when input low

1

Input current (inputs with pullup TMS, TDI ,TEST1 ,TEST2) when input low

15

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted) (continued)

voltage references

REFERENCE

Voltage on band gap (used for all other references)

Band gap output resistance

MIN

TYP

1.22

200

0.1

MAX

UNIT

Vdc

KΩ

µF

VGAP

VREF

VMID

1.16

1.28

Band gap external decoupling capacitance

Band gap start time ( bit CHGUP=0 )

100

2.5

ms

Band gap start time ( bit CHGUP=1)

ms

Voltage reference of GMSK internal ADC and DAC : V

Voltage reference output resistance

1.66

1.75

200

0.1

1.84

Vdc

KΩ

µF

VREF

Voltage reference external decoupling capacitance

Voltage reference start time ( bit CHGUP=0 )

Voltage reference start time ( bit CHGUP=1)

300

10

ms

Common-mode reference for baseband uplink: V

Load resistance on Vmid output

(Bit SELVMID=0)

(Bit SELVMID=1)

–10% Vdd/2

10%

1.45

Vdc

KΩ

Vdc

µA

VMID

1.25

10

1.35

VMID

MICBIAS Microphone-driving voltage (Bit MICBIAS=0)

Microphone-driving voltage(Bit MICBIAS=1)

1.80

2.25

450

350

2.00

2.5

2.20

2.75

Microphone-bias current drive capability (Bit MICBIAS= 1)

Microphone-bias current drive capability (Bit MICBIAS=0 )

ADCMID DC bias reference of the auxiliary ADCs

ADCMID external decoupling capacitance

500

400

µA

–10% Vdd/2

10%

Vdc

µF

0.1

IBIAS

Bias current adjust external resistance

100

KΩ

master clock input (MCLK)

PARAMETER

MIN

NOM

MAX

UNIT

Master clock signal frequency

Master clock duty cycle (Sinewave)

Maximum peak-to-peak amplitude

Minimum peak-to-peak amplitude

Common-mode input voltage

13

MHz

40%

60%

1.3

Vpp

Vdc

0.5

+0.5

V

–0.5

SS

DD

Input resistance at 13MHz (MCLK to ground)

Input capacitance at 13 MHz (MCLK to ground)

4.1

5

6.5

18

KΩ

12.5

15

pf

baseband uplink path

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

bit

I and Q D/A converters resolution

Dynamic range on each output

8

Centered on V

V

VREF

Vpp

kΩ

VMID

†

Differential output dynamic range with OUTLEV bit = 0

Differential output dynamic range with OUTLEV bit = 1

Output load resistance, differential

Output load capacitance, differential

Output common-mode voltage

BULQP-BULQN or BULIP-BULIN

2 x V

VREF

BULQP-BULQN or BULIP-BULIN

8/15 x V

VREF

10

50

pF

Programmable by bit SELVMID

V

VMID

Hi-Z

and BULQP–BULQN=0 corresponding to a phase angle of 0°.

I & Q output state in power down

†

Initial value after reset and at beginning of each burst are BULIP–BULIN=V

REF

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted) (continued)

dc accuracy – baseband uplink path

PARAMETER

MIN

TYP

±100

0

MAX

UNIT

mV

Offset error before calibration

†

Offset error after calibration

–7

7

mV

†

Calibration must be performed in normal operation mode.

dynamic parameters – baseband uplink path

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

1.5

UNIT

dB

Absolute gain error relative to V

Measured with 67.7 kHz sinewave

–1.5

0

VREF

100 kHz

200 kHz

250 kHz

400 kHz

600 KHz

–3

dB

–34

–37

–65

–72

dB

Maximumoutputrandommodulationspectrumrelativetoin-band

averagelevel. MeasuredbyaverageFFTsofrandomburstsusing

a window with 30 kHz bandwidth.

dB

800 KHz

–72

dB

smoothing filters characteristics – baseband uplink path

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Group delay

0 Hz to 100 kHz

1.5

µs

I and Q channels gain matching – baseband uplink path

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Gain matching between channels

0 Hz to 96 kHz

Measured on 67.7 kHZ sinewave

–1

0

1

dB

–0.42 –0.27 –0.12

I and Q gain unbalance

Programmable with bits IQSEL, G1, and G0

dB

–0.68 –0.53 –0.38

–0.93 –0.78 –0.63

baseband uplink path global characteristics

PARAMETER

MIN

TYP

MAX

6°

UNIT

peak

rms

‡

GMSK phase trajectory error

1.5°

Power supply rejection

55

dB

‡

After software calibration through BBAloop

timing requirements of baseband uplink path

programmable delays – baseband uplink path (see Figure 1)

§

MIN NOM

MAX

UNIT

t

Setup time, BENA before APC↑

Bits DELU of register BULRUDEL

Bits DELD of register BULRUDEL

Bit APCSPD = 0

0

15 1/4-bit

su1

Hold time, ramp-down from BENA low

h1

1/16-bit

64

t , t

r f

Transition time, APC

0

Bit APCSPD = 1

1/8-bit

§

Bit is relative to GSM bit = 1/270 kHz. Units can be a fractional part of the GSM bit as noted. Values in the above table are given for system

information only.

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

timing requirements of baseband uplink path (continued)

fixed delays – baseband uplink path (see Figure 1)

†

MIN NOM

MAX UNIT

t

Setup time, BULON↑ to BCAL↑

Pulse duration, BCAL high

15

132

0

µs

su2

w1

Setup time, BCAL low before BENA↑

Pulse duration, BENA high

su3

w2

N effective duration of burst controlled by BENA

(Digital delay of modulator)

N–32

32

1/4-bit

1/4 bit

bit

Hold time, modulation low after BENA low

Hold time, BULON↓ after APC low

Input-to-output modulator delay

h2

1

h3

1.5

bit

dd(mod)

†

Bit is relative to GSM bit = 1/270 kHz. Units can be a fractional part of the GSM bit as noted. Values in the above table are given for system

information only.

baseband downlink path

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Vpp

kΩ

Centered on external common

Dynamic range on each input

V

VREF

mode (V

)

BDLCOM

Differential input dynamic range

DLQP–DLQN or DLIP–DLIN

2*V

VREF

Differential input resistance at BDLQP–BDLQN or

BDLIP–BDLIN

130

1.5

90

200

270

6.5

180

12

Differential input capacitance at BDLQP–BDLQN or

BDLIP–BDLIN

4

pF

Single ended input resistance at BDLQPor BDLQN or BDLIP

or BDLIN to ground.

130

8

kΩ

Single ended input capacitance at BDLQP or BDLQN or

BDLIP or BDLIN to ground.

6

pF

V

External common-mode input voltage: V

0.8

V

DD

/2

V

–0.8

BDLCOM

DD

Maximum digital code value on

16-bit I and Q samples.

Range of digital output data

±21060

dc accuracy – baseband downlink path

PARAMETER

TEST CONDITIONS

MIN

TYP

0

MAX

UNIT

LSB

‡

Offset error before calibration

Offset error after calibration,

Offset correction range

–60

–2

60

2

‡

± 21 on 16-bit I and Q words

0

Full scale

‡

The LSB corresponds to the one of the ADC which is specified with 66 dB dynamic range (±1024),which means 11-bit, but the output data bits

are transmitted through the serial interface with 16-bit words. On top of that, the decimation ratio of 24 (6.5 MHz/270 kHz) makes the maximum

code on a 16-bit word to be 21060 instead of 32767. So one LSB of the ADC corresponds to a value of 21060/1024 = 20.57 on the 16-bit output

serial words on I and Q.

channel characteristics

frequency response – baseband downlink path

PARAMETER

MIN

–0.3

–4

TYP

MAX

0.25

0.3

UNIT

< 67.5 Hz

67.5 kHz

96 kHz

Frequency response of the total path with values referenced to 18 kHz

dB

135 kHz

200 kHz

400 kHz

–40

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

channel characteristics (continued)

SNR vs signal level–baseband downlink path

PARAMETER

TEST CONDITIONS

MIN

21

26

36

46

50

55

30

TYP

MAX

UNIT

dB

–50 dBm0 200 kHz bandwidth

–40 dBm0

–30 dBm0

Signal level

–20 dBm0

–10 dBm0

–5 dBm0

0 dBm0

Idle channel noise, 0 Hz –200 kHz

–66

dBm0

gain characteristics of the baseband downlink path

PARAMETER

TEST CONDITIONS

at –10 dBm0 and 18 kHz

0 dBm0

MIN

–11

TYP

MAX

–9

UNIT

Absolute gain error relative to V

–10

dB

VREF

–0.25

0.25

–5 dBm0

–10 dBm0 Reference level

–20 dBm0

0

dB

Gain tracking error. Over the range 3 dBm0 to – 50 dBm0 at

18 kHz with reference –10 dBm0

–0.25

–0.50

0.25

0.50

–30 dBm0

–40 dBm0

–50 dBm0

group delay – baseband downlink path

PARAMETER

MIN

TYP

MAX

UNIT

Group delay

0 Hz to 100 kHz

28

µs

I and Q channels matching – baseband downlink path

PARAMETER

TEST CONDITIONS

18 kHz sinewave

MIN

–0.5

–8

TYP

MAX

0.5

8

UNIT

dB

Gain matching between channels

Delay matching between channels

0 Hz to 96 kHz

18 kHz sinewave

ns

baseband downlink path global characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Power supply rejection, 0 Hz –100 kHz band

70

dB

timing requirements of baseband downlink path (see Figure 2)

†

MIN NOM

MAX UNIT

t

Setup time, BDLON↑ to BCAL↑

Pulse duration, BCAL

5

60

µs

su4

w3

su5

w4

su6

h4

Setup time BCAL low before BENA↑

Pulse duration, BENA high

0

N effective duration of burst controlled by BENA

N

1/4-bit

µs

Setup time, BENA↑ before DATAOUT VALID

Hold time, DATAOUT VALID after BENA↓

Hold time, BDLON low after BENA low

24.3

28

3.7

µs

0

µs

h5

†

Values in the above table are given for system information only.

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

automatic power control (APC)

APC level (8-bit DAC)

PARAMETER

TEST CONDITIONS

MIN

–1

TYP

MAX

1

UNIT

LSB

µs

Integral nonlinearity (best fitting)

Shaper at maximum full scale Load 10 kΩ, 50 pF

Differential nonlinearity

Settling time

–1

1

10

APC shaper (5-bit DAC)

PARAMETER

TEST CONDITIONS

MIN

–1

MAX

UNIT

LSB

µs

Integral nonlinearity (best fitting )

Differential nonlinearity

1

–1

†

Settling time

†

Value given for system information only.

APC output stage

PARAMETER

TEST CONDITIONS

MIN

2.0

0

TYP

MAX

2.4

20

UNIT

V

Output voltage at shape=31 & level =255

Output voltage at shape=0 & level=xx

Output voltage at shape=0 & level =xx

Output voltage at shape=xx & level = 0

Output voltage in power-down

DC power supply sensitivity

2.2

Bit APCMODE = 0

Bit APCMODE =1

mV

V

80

120

0

160

5

0

1%

50

Output impedance in power-down

Load resistance

20

Ω

10

kΩ

pF

Load capacitance

monitoring ADC

10-bit ADC

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LSB

µs

Integral nonlinearity (Best fitting)

Differential nonlinearity

Input signal range < 0.95 V

–4

–2

4

2

VREF

†

Conversion time

Input range

10

0

V

VREF

10

V

Input leakage current

Input capacitance

–10

µA

25

pF

†

Value given for system information only.

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

automatic Gain Control (AGC)

AGC 10-bit DAC

PARAMETER

TEST CONDITIONS

Best fitting line

MIN

–1

TYP

MAX

1

UNIT

LSB

µs

Integral nonlinearity

Differential nonlinearity

Settling time

–1

1

From AUXAGC load

100

AGC output stage

PARAMETER

TEST CONDITIONS

MIN

1.9

TYP

2.2

0.24

0

MAX

2.4

UNIT

Output voltage with code max

Offset voltage with code 000

Output voltage in power down

DC power supply sensitivity

Output impedance in power down

Load resistance

V

0.18

0.30

1%

50

200

kΩ

pF

10

Load capacitance

automatic frequency control (AFC)

AFC 13-bit DAC

PARAMETER

TEST CONDITIONS

MIN

TYP

2

MAX

UNIT

AFCCK1=1

AFCCK0 = 1

AFCCK0 = 0

AFCCK0 = 1

AFCCK0 = 0

AFCCK1=1

AFCCK1=0

Best fitting line

1

Sampling frequency, f

MHz

s

0.5

0.25

±1

Integral nonlinearity from 0 to 75% output range

Differential nonlinearity from 0 to 75% output range

Settling time

LSB

µs

±1

1

DC power-supply sensitivity

Over power supply range

1%

AFC output stage

PARAMETER

TEST CONDITIONS

MIN

TYP

25

33

2.5

3

MAX

UNIT

kΩ

nF

V

Internal output resistance (±30 % tolerance)

External filtering capacitance

Output voltage with code max

Output voltage with code min

Output voltage in power down

2.0

0

2.8

6

mV

V

0

Output impedance in power down

25

kΩ

13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

voice uplink path

global characteristics of voice uplink path

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Inputs 3 dBm0 (maximum digital sample amplitude)

with PGA gain, set to 0dB (default value)

Maximum input range (MICP – MICN)

32.5

mVrms

Nominal reference level (MICP – MICN)

Differential input resistance (MICP – MICN)

Micro-amplifier gain

–10

140

27

dBm0

kΩ

90

200

dB

Inputs 3 dBm0 (maximum digital sample amplitude)

with PGA gain, set to 0dB (default value)

Maximum input range at AUXI

365

mVrms

Nominal reference level at AUXI

Input resistance at AUXI

Auxi amplifier gain

–10

220

6

dBm0

kΩ

140

300

dB

PGA absolute gain

4.6

dB

VULPGA code =10000

VULPGA code = 10111

VULPGA code = 11000

VULPGA code = 11001

VULPGA code = 11010

VULPGA code = 11011

VULPGA code = 00000 (default)

VULPGA code = 00001

VULPGA code = 00010

VULPGA code = 00011

VULPGA code = 00100

VULPGA code = 00101

VULPGA code = 00110 (ref)

VULPGA code = 00111

VULPGA code = 01000

VULPGA code = 01001

VULPGA code = 01010

VULPGA code = 01011

VULPGA code = 01100

VULPGA code = 10001

VULPGA code = 10010

VULPGA code = 10011

VULPGA code = 10100

VULPGA code = 10101

VULPGA code = 10110

–12 dB

–11 dB

–10 dB

–9 dB

–8 dB

–7 dB

–6 dB

–5 dB

–4 dB

–3 dB

–2 dB

–1 dB

0 dB

–12.7 –12.2 –11.7

–11.3 –10.8 –10.3

–10.6 –10.1

–9.6

–8.5

–7.5

–6.5

–5.7

–4.6

–3.6

–2.5

–1.4

–0.5

–9.5

–8.5

–7.5

–6.7

–5.6

–4.6

–3.5

–2.4

–1.5

–9

–8

–7

–6.2

–5.1

–4.1

–3

–1.9

–1

PGA gain step

0

dB

1 dB

0.7

1.4

2.6

3.6

4.5

5.3

6.4

7.4

8.6

9.6

10.5

11.5

1.2

1.9

3.1

4.1

5

1.7

2.4

2 dB

3 dB

3.6

4 dB

4.6

5 dB

5.5

6 dB

5.8

6.9

7.9

9.1

10.1

11

6.3

7 dB

7.4

8 dB

8.4

9 dB

9.6

10 dB

11 dB

12 dB

10.6

11.5

12.5

12

Power supply rejection, 0 Hz –100 kHz band

70

dB

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

voice uplink path (continued)

frequency response of the voiceband uplink path

PARAMETER

MIN

TYP

–37.4

–25.9

–16.5

MAX

–20

–15

–10

1

UNIT

TEST CONDITIONS

100 Hz

150 Hz

200 Hz

300 Hz

–2 –1.46

0

1000 Hz

2000 Hz

3000 Hz

3400 Hz

3600 Hz

3800 Hz

4000 Hz

>4600 Hz

Reference point is 1000 Hz

–1.5 –0.58

–1.5 –0.77

1

Frequency response (Gain relative to reference gain at

1 kHz)

dB

–2

–1

–12.4

–23.3

–35

1

–6

–18

–30

–40

>–52

psophometric SNR vs signal level of the voiceband uplink path

PARAMETER

TEST CONDITIONS

MIN

35

40

42

45

42

40

30

25

TYP

MAX

UNIT

3 dBm0

0 dBm0

–5 dBm0

–10 dBm0

–20 dBm0

–30 dBm0

–40 dBm0

–45 dBm0

0 Hz –4 kHz

Signal to noise + distortion

dB

Maximum idle channel noise

–72 dBm0

Crosstalk with the downlink path

Downlink path loaded with 150 Ω

–66

dB

gain characteristics of the voiceband uplink path

PARAMETER

TEST CONDITIONS

at 0dBm0 and 1KHz

MIN

–1

TYP

MAX

1

UNIT

Absolute gain error

dB

at –10dBm0 and 1KHz

–11

–10

–9

3 dBm0

–0.25

0.25

0 dBm0

–5 dBm0

–10 dBm0 Reference level

–20 dBm0

0

Gain tracking error. Over the range 3 dBm0 to – 45 dBm0 at

1 kHz with reference –10 dBm0

dB

–0.25

–0.35

–0.50

0.25

0.35

0.50

–30 dBm0

–40 dBm0

–45 dBm0

15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

voice downlink path

global characteristics of voice downlink path

PARAMETER

TEST CONDITIONS

MIN

3.1

1.2

120

30

TYP

3.92

1.5

MAX

100

UNIT

With 5% distortion and with 150 Ω

Maximum output swing

Vpp

(EARP – EARN)

With 5% distortion and with 33 Ω

Output swing 3.9Vpp

150

33

Ω

Minimum output resistive load at EARP_EARN

Output swing 1.5Vpp

Maximum output capacitive load at EARP_EARN

Earphone amplifier gain

pF

dB

0

Hi-Z

1.96

1.2

Earphone amplifier state in power down

Maximum output swing (AUXO), 5% distortion, maximum

Minimum output resistive load at AUXO

Maximum output capacitive load at AUXO

Auxo amplifier gain

Load = 1 kΩ

1.6

1.0

Vpeak

kΩ

AC coupled

100

pF

–6

Hi-Z

0

dB

Auxo amplifier state in power down

VOLCTL code = 010

–1

–7

1

VOLCTL code = 110

–6

–5

VOLCTL code = 000 (default & reference)

VOLCTL code = 100

–12

–18

–24

Volume control gains

dB

–19

–25

–17

–23

VOLCTL code = 011

VOLCTL code =101 or 001 or 111 (mute)

VDLPGA code = 0000 (default) –6 dB

–40

–6.5

–5.5

–4.5

–3.7

–2.3

–1.7

–6.0

–5.0

–4.0

–3.2

–1.8

–1.2

0

–5.5

–4.5

–3.5

–2.7

–1.3

–0.7

VDLPGA code = 0001

VDLPGA code = 0010

VDLPGA code = 0011

VDLPGA code = 0100

VDLPGA code = 0101

VDLPGA code = 0110 (ref.)

VDLPGA code = 0111

VDLPGA code = 1000

VDLPGA code = 1001

VDLPGA code = 1010

VDLPGA code = 1011

VDLPGA code = 1100

–5 dB

–4 dB

–3 dB

–2 dB

–1 dB

0 dB

PGA gain steps

dB

1 dB

0.5

1.4

2.6

3.4

4.3

5.5

1.0

1.5

2.4

3.6

4.4

5.3

6.5

2 dB

1.9

3 dB

3.1

4 dB

3.9

5 dB

4.8

6 dB

6.0

VDLST code = 1101

VDLST code = 1100

VDLST code = 0110

VDLST code = 0010

VDLST code = 0111

VDLST code = 0011

VDLST code = 0000 (ref.)

VDLST code = 0100

VDLST code = 0001

VDLST code = 1000

In the band

–23 dB

–20 dB

–17 dB

–14 dB

–11 dB

–8 dB

–5 dB

–2 dB

1 dB

–24.6 –24.1 –22.6

–21.1 –20.6 –18.5

–18.3 –17.8 –17.3

–14.8 –14.3 –13.8

–12.3 –11.8 –11.3

Sidetone gain steps

dB

–8.8

–5.9

–2.1

0.7

–8.3

–4.8

–1.6

1.2

–7.8

–4.3

–1.1

1.7

Mute

–55

60

–50

Power supply rejection, 0 Hz –100 kHz

NOTE: All parameters are given for a 150 Ω load, unless specified.

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

voice downlink path (continued)

frequency response of the voiceband downlink path

PARAMETER

TEST CONDITIONS

MIN

TYP

–5.8

–3.6

–2.5

–1.4

0

MAX

–5

–2

1

UNIT

100 Hz

150 Hz

200 Hz

300 Hz

–3

–1

1

1000 Hz

2000 Hz

3000 Hz

3400 Hz

Reference point

–0.6

1

Frequency response (Gain relative to

reference gain at 1 kHz)

dB

–1 –0.15

–3 –0.35

–9.0

1

–6

3600 Hz

–21.0

–32.0

–60.0

–15

–28

3800 Hz

4000 Hz

>4600 Hz

psophometric SNR vs signal level of the voiceband downlink path

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

–45 dBm0

–40 dBm0

–30 dBm0

–20 dBm0

–10 dBm0

–5 dBm0

25

30

40

42

45

42

40

35

Signal level

dB

0 dBm0

3 dBm0

Idle channel noise, 0 Hz –4 kHz

Crosstalk with the uplink path

–71

–50

dBm

dB

gain characteristics of the voiceband downlink path

PARAMETER

TEST CONDITIONS

at 0 dbm0 and 1 kHz

at –10 dbm0 and 1 kHz

MIN

–1.8

TYP

0

MAX

0.2

UNIT

Absolute gain error

dB

–11.8

–0.25

–10

–9.8

0.25

3 dBm0

0 dBm0

–5 dBm0

Gain tracking error. Over the range 3 dBm0 to – 45 dBm0 at

1 kHz with reference –10 dBm0 PGA gain = 0dB. Volume

control = –12 dB

–10 dBm0 Reference level

–20 dBm0

0

dB

–0.25

–0.35

–0.50

0.25

0.35

0.50

–30 dBm0

–40 dBm0

–45 dBm0

17

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

power consumption

consumption by circuit block

CIRCUIT BLOCK

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ADC

DVDD3

0.013

0.021

0.027

0.054

0.683

0.133

0.108

0.442

2.240

1.550

0.163

2.810

9.310

0.460

4.910

1.490

0.122

0.204

0.181

0.144

0.183

4.170

3.000

1.380

2.990

1.200

0.115

AFC

AGC

APC

AVDD3

AVDD5

AVDD3

AVDD5

DVDD3

AVDD3

AVDD5

AVDD4

AVDD1

DVDD2

AVDD2

DVDD2

AVDD2

DVDD1

DVDD4

AVDD4

DVDD4

AVDD4

DVDD4

AVDD4

mA

Auxiliary input stage

Auxiliary output stage

Band gap

mA

Baseband downlink

Baseband uplink

mA

BBIF

BDL Active

mA

Clock generator BBIF

Clock generator Idle

Clock generator TIIF

Clock generator VBIF

Digital modulator

Earphone output stage

Microphone input stage

Voiceband downlink

Voiceband uplink

mA

current consumption for typical configurations

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

13-MHz clock applied; PWRDN active;

Band-gap voltage reference off

Deep power down

200

µA

Power down with AFC active

AFC + GMSK – Rx

AFCprogrammedwithinternal50-kΩ and1-MHzclock

0.7

14

19

27

1.1

16

21

30

mA

Paging

Audio + GMSK – Tx + APC + AFC

Audio + GMSK – Rx +AGC+ AFC

Transmit burst

Receive burst

18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

MCU serial interface timing requirements (see Figure 3)

PARAMETER

MIN NOM

MAX

UNIT

ns

t

Setup time, UCLK stable before USEL↓

Hold time, UDX valid after USEL↓

Hold time, UDX valid after UCLK↑

20

su10

20

ns

v1

ns

v2

Sequential transfer delay between 16-bit word acquisition t pulse duration, USEL high

w

3000

20

ns

h9

Hold time, UCLK↑ after USEL↓

Hold time, UCLK unknown after USEL↑

Setup time, data valid before UCLK↓

Hold time, data valid after UCLK↓

Cycle time, ULCK

ns

h10

h11

su11

h12

c

20

ns

20

ns

20

ns

154

ns

DSP serial interface timing requirements (see Figure 4)

PARAMETER

MIN NOM

MAX

UNIT

BCLKX BCLKX signal frequency ( Burst mode or Continuous mode depending on bit BCLKMODE)

BCLKX BCLKX duty cycle

13

MHz

40%

20

50%

60%

t

Setup time, BFSX high before BCLKX ↓

Hold time, BFSX high after BCLKX ↓

Setup time, BDX valid before BCLKX ↓

Hold time, BDX valid after BCLKX ↓

ns

su12

20

h12

20

su13

h13

20

(Output BCLKDIR = 0)

(Input BCLKDIR = 1)

4.33

50%

BCLKR BCLKR signal frequency

MHz

13

BCLKR BCLKR duty cycle

40%

20

60%

t

Setup time, BFSR high before BCLKR ↓

ns

su14

Hold time, BFSR high after BCLKR ↓

Setup time, BDR valid before BCLKR ↓

Setup time, BDR valid after BCLKR ↓

20

h14

20

su16

h15

20

voice timing requirements (see Figure 5)

PARAMETER

VCLK signal frequency ( Burst mode or Continuous mode depending on bit VCLKMODE)

MIN NOM

MAX

UNIT

VCLK

520

kHz

VCLK duty cycle

40%

100

50%

60%

t

Setup time, VFS high before VCLK ↓

Hold time, VFS high after VCLK ↓

Setup time, VDX valid before VCLK ↓

Hold time, VDX valid after VCLK ↓

Setup time, VDR valid before VCLK ↓

ns

su7

h6

su8

h8

su9

t

h7

Hold time, VDR valid after VCLK ↓

100

ns

19

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PARAMETER MEASUREMENT INFORMATION

uplink timing considerations

Figure 1 shows the timing diagram for the uplink operation.

Timing for power up, offset calibration, data transmission, and power ramp-up are driven by control bits applied

to BULON (base uplink on), BCAL (calibration) and BENA (enable). The burst content including guard bits, tail

bits, and data bits is sent by the DSP by way of the DSP interface and then stored by the TCM4400E in a burst

buffer. Transmission start is indicated by the control bit BENA when the BULON is active. The transmission,

sequencing, and power ramp-up are then controlled by an on-chip burst sequencer with a one-quarter-bit timing

accuracy. For a detailed description of the baseband in length path, see the functional description of the

baseband uplink path in the Principles of Operation section.

BULON

t

su2

t

BCAL

BENA

w1

t

h2

t

su3

t

w2

MODULATION

APC

t

h1

t

r1

t

f1

t

su1

t

h3

Figure 1. Uplink Timing Diagram

20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PARAMETER MEASUREMENT INFORMATION

downlink timing considerations

Figure 2 shows the timing diagram for downlink operation.

Timing control of the baseband downlink path is controlled by bits DLON (downlink on), BCAL (calibration) and

BENA (enable) when BDLON is active (see the topic, timing and interface). BDLON controls the power up of

the baseband downlink path, BCAL controls the start and duration of the autocalibration sequence, and BENA

controls the beginning and the duration of data transmission to the DSP, using the DSP serial interface.

The power-down sequence is controlled with two bits, the first bit (BBDLW of PWDNRG1 register) determines

whether the baseband downlink path can be powered down with external GSM receive window activation

(BDLON); the second bit (BBDLPD of PWDNRG1 register) controls the activation of the baseband downlink

path. See the topic, power-down functional description, for more details about power-down control.

BDLON

t

su4

BCAL

t

w3

t

h5

su5

BENA

t

w4

DATAOUT

t

h4

su6

Figure 2. Downlink Timing Sequence

21

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PARAMETER MEASUREMENT INFORMATION

microcontroller serial interface timing considerations

Figure 3 shows the timing diagram for the microcontroller serial interface.

The microcontroller serial interface is designed to be compliant with 8-bit standard synchronous serial ports.

The microcontroller operates on 16-bit words; this interface consists of four pins.

UCLK:

UDR:

UDX:

A clock provided by the microcontroller to control access to baseband, voiceband, and auxiliary

functions registers

An input terminal to control read and write access to baseband, voiceband, and auxiliary functions

registers

An output terminal to transmit data from read access of baseband, voiceband, and auxiliary

functions registers

USEL:

An input terminal to enable read and write access to baseband, voiceband, and auxiliary functions

registers through the microcontroller interface

t

h10

USEL

UCLK

t

su10

t

h11

t

c

t

h10

t

h9

t

v2

t

su11

UDR

UDX

t

h12

v1

Hi-Z

Figure 3. Microcontroller Serial Interface Timing Waveforms

(Mode Rising Edge Without Delay)

22

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PARAMETER MEASUREMENT INFORMATION

DSP serial port timing considerations

Figure 4 shows the timing diagram for DSP serial port operation.

Six pins are used for the serial port interface; see Figure 14. The terminal BCLKR is an I/O port for the serial

clock used to control the reception of the data BDR. At reset BCLKR is configured as an output and the clock

frequency is set to MCLK/3 (4.333 MHz with MCLK = 13 MHz); the clock signal is running permanently. The port

BCLKR can be reconfigured as an input by programming an internal register. In this case BCLKR is provided

bytheDSPandcanruninburstmodetoreducepowerconsumption. Thereceiveframesynchronization(BFSR)

identifies the beginning of a data packet transfer on port BDR.

The transmitted serial data (BDX) is the serial data input; the transmit frame synchronization (BFSX) is used

to initiate the transmission of data. The transmit clock (BCLKX) is provided by the GSM baseband and voice

A/D and D/A converters with a frequency of MCLK. The downlink data bus (BFSX, BCLKX, BDX) can be driven

to VSS or placed in high-impedance when no data is to be transferred to the DSP. The bit BCLKDIR of the

register BCTLREG controls the direction of the BCLKR clock.

Similar to the voice serial interface, an extra clock cycle must be generated, since the last 16-bit word received

on the DSP serial interface is latched on the next two falling BCLKR edges, following the least significant bit

(LSB). As for the voice serial interface, one extra clock period is generated on the BCLKX before the first

synchronization BFSX of downlink data sequence.

BCLKX

t

su13

su12

t

h14

h13

BFSX

BDX

A15

A14

A13

A12

A3

A2

A1

A0

MSB

LSB

a. Burst-Mode Serial-Port Transmit Operation

BCLKR

t

su14

su15

t

h15

h14

BFSR

BDR

A15

A14

A13

A12

A3

A2

A1

A0

B15

B14

B13

MSB

LSB

b. Burst-Mode Serial-Port Receive Operation

Figure 4. DSP Serial Port Timings

23

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PARAMETER MEASUREMENT INFORMATION

voiceband serial interface timing considerations

Figure 5 shows the timing diagram for both transmit and receive voiceband serial interface operation.

The signal VCLK is the output serial clock used to control the transmission or reception of the data (see

Figure 5). The transmitted serial data (VDX) is the serial data output; the frame synchronization (VFS) is used

to initiate the transfer of transmit and receive data. The received data (VDR) is the serial data input.

Each serial port includes four registers that include the data transmit register (DXR), the data receive register

(DRR), the transmit shift register (XSR), and the receive shift register (RSR).

The voice serial interface has the same structure and timing diagram as the serial interface; one extra cycle is

generated before VFS, and two extra cycles are generated after the LSB.

XLOAD and RLOAD are internal signals.

VCLK

t

su7

su8

h6

t

h8

VFS

VDX

A15

MSB

A14

A13

A12

A3

A2

A1

A0

LSB

XLOAD

DXR

Loaded

XSR

Loaded

a. Audio-Serial-Port Transmit Operation

VCLK

t

su9

t

h7

VFS

VDR

A15

A14

A13

A12

A3

A2

A1

LSB

A0

MSB

RLOAD

DDR

Loaded

b. Audio-Serial-Port Receive Operation

Figure 5. Voiceband Serial Interface Timing Waveforms

24

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLE OF OPERATION

baseband uplink path

Traditional transmit and receive terms can be confusing when describing a cellular telephone two-way

communication. This document uses the terms uplink, meaning from a user device to a remote station, and

downlink meaning from a remote station, whether earthbound or satellite, to indicate the signal-flow direction.

The modulator circuit in the baseband uplink path performs the Gaussian minimum shift keying (GMSK) in

accordance with the GSM specification 5.04. The data to be modulated flows from the DSP through the serial

interface, it is differentially encoded, and it is applied to the input of the GMSK modulator. The GMSK modulator,

implemented with digital logic and a sin/cos look-up table in ROM, generates the I and Q components (words)

with an interpolation ratio of 16.

These digital I and Q words are sampled at a 4.33 MHz rate and applied to the inputs of a pair of high-speed

8-bit DACs. The analog outputs are then processed by third-order Bessel filters to reduce image frequencies

due to sampling and to obtain a spectrum consistent with GSM specification 05.05 (see Figure 6).

MAGNITUDE

vs

FREQUENCY

0

–20

–40

–60

–80

–100

–120

6

10

6

2×10

6

3×10

6

4×10

6

5×10

6

6×10

0

Frequency – MHz

NOTE A: Conformance with GSM Rec 05.05: simulated spectrum of an infinite modulation of random data with a Blackman

Harris analysis window.

Figure 6. Typical GSM Modulation Spectrum

Full-differential buffered signals are available at ULIP, ULIN, ULQP, and ULQN. These signals are suitable for

use in the RF circuit for generating a phase-modulated signal of the form:

s(t) = A Cos (2 Pi fc t + Phi (t, alpha))

where fc is the RF carrier frequency, and Phi (t, alpha) is the phase component generated by the GMSK

modulator from the differential encoded data.

25

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

baseband uplink path (continued)

Timing for power up, offset calibration, data transmission, and power ramp-up is driven by control bits applied

to BULON (base uplink on), BCAL (calibration) and BENA (enable) (see Figure 1). The entire content of a burst,

including guard bits, tail bits, and data bits, is sent by the DSP using the DSP interface and then stored by the

TCM4400E in a burst buffer. Transmission start is indicated by the control bit BENA when the BULON is active.

The transmission, sequencing, and power ramp-up are then controlled by an on-chip burst timing control circuit

having a one-quarter-bit timing accuracy (see Figure 7). All data related to a burst to be transmitted, such as

bit data, ramp-up & ramp-down delay programmation, have to be loaded before the rising edge of BENA.

The burst length is determined by the time during which the BENA signal is active. Effective burst length is equal

to the duration of BENA + 32 one-quarter bits. The tail of the burst is controlled internally, which means that the

modulation is maintained for 32 one-quarter bits after BENA turns off to generate the ramp-down sequence and

complete modulation.

For each burst, the power control level can be controlled by using the serial interfaces to write the power level

value into the power register of the auxiliary RF power control circuitry. The power ramp-up and ramp-down

sequences are controlled by the burst sequencer, while the shape of the power control is generated internally

by dedicated circuitry, which drives the power control 5-bit and 8-bit D/A converters.

To minimize phase error, the I and Q channel dc offset can be minimized using offset calibration. Each channel

includes an offset register in which a value corresponding to the required dc offset is stored, controlling the dc

offset of the I channel and Q channel D/A converters. This value is set by a calibration sequence. Starting and

stopping the calibration sequence is controlled by the control bit BCAL using the timing interface when BULON

is active. During the calibration sequence, the digital value of I and Q is forced to zero so that only the offset

register value drives the D/A converters, and a low-offset comparator senses the dc level at the BULIP/BULIN

and BULQP/BULQN outputs and modifies the content of the offset registers to minimize the dc offset (see

Figure 7).

Gain unbalance can be introduced between I and Q channels to allow compensation of imperfections in RF

circuits. This gain unbalance is controlled through the mean of three program bits: IQSEL,G1, and G0 of

baseband uplink register BULCTL.

The power-down function is controlled with two bits. The first bit (BBULW of the PWDNRG1 register),

determines whether the baseband uplink path can be powered down with external GSM transmit window

activation (BULON). The second bit (BBULPD of the PWDNREG1 register) controls the activation of the

baseband uplink path. For more details about power-down control, see the power-down functional description

section.

26

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

baseband uplink path (continued)

–

+

Timing Interface

Din

Offset

Register

Burst

Register

Burst Timing

Control

Cosine

Table

8-Bit

DAC

Low-Pass

Filter

270 kHz

BULIP

BULIN

Differential

Encoder

Gaussian

Filter

Integrator

fs = 16 x 270 kHz

I/Q Gain Unbalance

Sine

Table

Low-Pass

Filter

BULQP

BULQN

8-Bit

DAC

Power

Register

Ramp-Up

Shaper

Offset

Register

–

+

To Power

Control DAC

Figure 7. Functional Structure of the Baseband Uplink Path

baseband downlink path

The baseband downlink path includes two identical circuits for processing the baseband I and Q components

generated by the RF circuits. The first stage of the downlink path is a continuous-time second-order antialiasing

filter (see Figure 8) that prevents aliasing due to sampling in the A/D converter. This filter also serves as an

adaptation stage (input impedance and common-mode level) between external-world and on-chip circuitry.

TYPICAL FREQUENCY RESPONSE OF THE

ANTIALIASING FILTER

10

0

–10

–20

–30

–40

–50

–60

–70

2

3

10

4

10

5

10

6

10

7

10

f – Frequency – Hz

Figure 8. Antialiasing Filter

27

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

baseband downlink path (continued)

The antialiasing filter is followed by a third-order sigma-delta modulator that performs A/D conversion at a

sampling rate of 6.5 MHz. The A/D converter provides 3-bit words that are fed to a digital filter (see Figure 9)

that performs the decimation by a ratio of 24 to lower the sampling rate down to 270.8 KHz and the channel

separation by rejecting enough of the adjacent channels to allow the demodulation performances required by

the GSM specification. Figure 10 shows the frequency response curve for the downlink digital filter and Figure

11 shows the in-band response curve for the same digital filter.

The baseband downlink path includes an offset register in which the value representing the channel dc offset

is stored; this value is subtracted from the output of the digital filter before transmitting the digital samples to

the DSP using the serial interface. Upon reset, the offset register is loaded with 0 and updated with the BCAL

calibrating signal (see Figure 2).

The content of the offset register results from a calibration sequence. The input BDLIP is shorted with the input

BDLIN, and the input BDLQP is shorted with the input BDLQN. The digital outputs are evaluated and the values

are stored in the corresponding offset registers in accordance with the dc offset of the GSM baseband and voice

A/D and D/A downlink path. When the external autocalibration sequence is selected, the inputs BDLIP and

BDLIN and the inputs BDLQP and BDLQN remain connected to the external circuitry. The digital outputs are

evaluated, and the values stored in the corresponding offset registers take into account the dc offset of the

external circuitry.

Timing control of the baseband downlink path is controlled by bits BDLON (downlink on), BCAL (calibration),

and BENA (enable) when BDLON is active (please see timing interface section). BDLON controls the power

up of the baseband downlink path; BCAL controls the start and duration of the autocalibration sequence (which

can be internal or external depending on bit EXTCAL of PWDNRG1 register); and BENA controls the beginning

and the duration of data transmission to the DSP by using the DSP serial interface. To avoid transmission of

irrelevant data corresponding to the settling time of the digital filter, the eight first I&Q computed samples are

not sent to the DSP; first data are transmitted though the DSP interface about 30 µs after the BENA rising edge.

The power-down sequence is controlled with two bits. The first bit (BBDLW of PWDNRG1 register) determines

whether the baseband downlink path can be powered down with external GSM receive window activation

(BDLON): The second bit, BBDLPD of register PWDNRG1, controls the activation of the baseband downlink

path. Please see power-down functional description section for more details about power-down control.

Offset

Calibration

Register

SUB

Antialiasing

Filter

Sigma-Delta

Modulator

SINC

Filter

FIR

Filter

BDLIP

BDLIN

To Baseband

Serial Interface

fs1 = 6.5 MHz

fs2 = 1.08 MHz

fs3 = 270.8 kHz

BDLQP

BDLQN

Antialiasing

Filter

SINC

Filter

FIR

Filter

Sigma-Delta

Modulator

SUB

Offset

Calibration

Register

Figure 9. Functional Structure of the Baseband Downlink Path

28

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

baseband downlink path (continued)

10

0

–10

–20

–30

–40

–50

–60

–70

–80

0

50

100

150

200

f – Frequency – kHz

Figure 10. Downlink Digital Filter Frequency Response

0.4

0.2

0

–0.2

–0.4

0

10

20

30

40

50

60

70

80

f – Frequency – kHz

Figure 11. Downlink Digital Filter In-Band Response

29

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

auxiliary RF functions

The auxiliary RF functions include the following:

Automatic frequency control

Auxiliary analog converter (Automatic gain control)

RF power control

Monitoring

Each of these functions is discussed in the following paragraphs.

automatic frequency control (AFC)

The automatic frequency control function consists of a DAC converter optimized for high-resolution dc

conversion. The AFC digital interface includes two registers that can be written using the serial interfaces. The

content of these registers controls a 13-bit DAC, whose purpose is to correct frequency shifts of the oscillator

maintaining the master clock frequency in a 0.1 ppm range.

Optimizing the AFC function depends on the type of oscillator used and whether its sampling frequency is

programmable. This means that the lower the selected frequency the lower the resolution and power

consumption. Using a high-quality resonance oscillator filter permits the AFC circuit to operate at low frequency.

Thus, a low-cost oscillator permits operation at a higher internal frequency to ensure 13-bit resolution.

The AFC value is programmed with registers AUXAFC1, which contains the ten LSBs, and AUXAFC2, which

contains the three MSBs. The three MSBs are sent to the DAC through a shadow register the contents of which

is updated when LSBs are written in AUXAFC1, so proper operation of the AFC is ensured by writing the MSB’s

first and then the LSBs.

Internal resistance and output voltage swing selection are controlled with bit AFZ of AUXCTL2 register. Power

down is controlled with two bits: the first bit, AFCPN of AUXCTL1 register, determines whether the AFC can be

powered down from the external PWRDN terminal; the second bit, AFCPD of AUXCTL1 register, controls the

activation of the the AFC function. See the topic, power-down functional description for more details about

power-down control.

The auxiliary analog functions of the GSM baseband A/D and D/A conversions are independently powered from

the AV

external terminal.

DD5

auxiliary analog converter (automatic gain control (AGC))

The auxiliary analog converter control function includes a register which can be written to using the serial

interfaces and a 10-bit D/A converter that provides a control signal to set the gain of the RF section receive

amplifier. The 10-bit D/A converter is accessed through the internal register AUXAGC.

Power down is controlled with two bits. The first bit (AGCW of AUXCTL2 register) determines whether the AGC

can be powered down with the external GSM receive window activation (BDLON). The second bit (AGCPD of

AUXCTL2 register) controls the activation of AGC function. See the topic, power-down functional description

for more details about power-down control.

The auxiliary analog functions of the GSM baseband A/D and D/A conversions are independently powered from

the AV

external terminal.

DD5

30

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

RF power control

The RF power control section includes a register that is written to using the serial interfaces. An 8-bit D/A

converter processes the content of this register and determines the gain of the RF section power amplifier.

The reference of the 8-bit D/A converter (accessed by register AUXAPC) is provided by the ramp-up-shaper

D/A converter, which is a 5-bit D/A converter controlled by the APCRAM registers located in random access

memory (RAM). This area of RAM contains sixty-four 10-bit words. These are read from address 0 through

address 62 during the ramp-up sequence. They are read from 63 through 1 during the ramp-down sequence

at a rate of 4 MHz when bit APCSPD is at zero or at a rate of 2 MHz when bit APCSPD is at 1. The ramp-up

parameters are obtained from the five least significant bits of the RAM words. The ramp-down parameters are

obtained from the most significant bits of the RAM words. Content of address 0 must be identical with content

of address 1. Content of address 62 must be identical with content of address 63.

This RAM is loaded once, and its content determines the shape of the ramp-up and ramp-down control signal.

This means these control signals can be adapted to the response of the power amplifier used in the RF section.

The shape and timing of ramp-up and ramp-down waveforms are independent.

Timing of the ramp-up and ramp-down sequences is controlled internally; however, programming of the delay

register allows adjusting the power-control start time in a 4-bit range in 1/4-bit steps. The contents of the delay

register are referenced to the BENA signal, which determines the beginning of the burst-signal modulation. This

feature allows adjusting the timing of the control signal versus the I and Q components within 1/4-bit accuracy

as defined in the specification GSM 05.05.

When APC is in power-down mode or when APC level is zero, the analog output is driven to V ; see

SS

Figure 12. During inactivity periods, the APC output is switched to V to give low-current consumption to the

SS

power amplifier (drain cutoff current of the RF amplifier);

BULON

BENA

Level 255

Level 1

Level 0

APC OUT

Offset = 120 mV

Figure 12. APC Output When APCMODE = 0

An offsetoftypically120mV(2Vswing)isaddedtotheAPCoutputtoensurelevelDAClinearity. BitAPCMODE

controls how this offset is added. When APCMODE is zero the APC output is given by

APCout = Shape value * ( Level value + Offset)

31

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

RF power control (continued)

When APCMODE is one (see Figure 13) the APC output is given by formula

APCout = ( Shape value * Level value ) + Offset

BULON

BENA

Level 255

Level 1

APC OUT

Offset = 120 mV

Level 0

Figure 13. APC Output When APCMODE = 1

Power down is controlled with two bits. The first bit (APCW of AUXCTL2 register) determines whether the APC

canbepowereddownbyactivatingexternalGSMtransmitwindowactivation(BULON):Thesecondbit(APCPD

of AUXCTL2 register) controls the activation of APC function. See the topic, power-down functional description,

for more details about power-down control. The auxiliary analog functions of the GSM baseband A/D and D/A

conversions are independently powered from the AV

terminal.

DD5

monitoring

The monitoring section includes a 10-bit A/D converter and one result register that allows monitoring of five

external analog values such as the temperature and the battery voltage. The selection of the input and reading

of the control registers is done using the serial interfaces.

The selection of the input channel is done with the bits ADCCH0 – ADCCH2 of the AUXCTL1 register; the data

is read from the AUXADC register. Power down is controlled with two bits. The first bit (ADCPN of AUXCTL1

register) determines whether the A/D converter can be powered down from the external PWRDN terminal. The

second bit (ADCPD of AUXCTL1 register) controls the activation of the A/D conversion function. See the topic,

power-down functional description, for more details about power-down control.

Conversion is started with a write access to the AUXCTL1 register. During the conversion, the ADCEOC bit of

BSTATUS register stays at 1 and resets to 0 when the converted data is loaded into the AUXADC register. This

way the power consumption of the main parts of the converter is limited to the useful part of the conversion time.

32

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

voice codec

The voice coder/decoder (codec) circuitry processes analog audio components in the uplink path and applies

this signal to the voice signal interface for eventual baseband modulation. In the downlink path, the codec

circuitrychangesvoice-componentdatareceivedfromthevoiceserialinterfaceintoanalogaudio. Thefollowing

paragraphs describe these uplink/downlink functions in more detail.

voice uplink path

The voice uplink path includes two input stages; refer to Figure 14. The first stage is a microphone amplifier,

compatible with an electret-type microphone, that contains a FET-buffer with an open-drain output, that has a

gain of typically 27 dB, and provides an external voltage of 2 V to 2.5 V to bias the microphone. The auxiliary

audio input can be used as an alternative source for a higher level speech signal. This stage performs

single-ended to differential conversion and provides a gain of 6 dB. When auxiliary audio input is used, the

microphone input is disabled and powered down. If both microphone and auxiliary amplifiers are powered up

at the same time, only the signal of the microphone amplifier will be transmitted to the voice uplink path.

The resulting fully differential signal is fed to a programmable gain amplifier that allows adjustment of the level

of the speech signal to the dynamic range of the A/D converter, which is determined by the value of the internal

voltage reference. Programmable gain can be set from –12 dB to +12 dB in 1-dB steps. It is programmed with

bits VULPG to VULPG4 of VBCTL1 register.

Analog-to-digital conversion is made with a third-order sigma-delta modulator whose sampling rate is 1 MHz.

Output of the A/D converter is fed to a speech digital filter, which performs the decimation down to 8 KHz and

band limits the signal with both low-pass and high-pass transfer functions. The speech samples are then

transmitted to the DSP, using the voice serial interface, at a rate of 8 kHz.

Programmable functions of the voice uplink path, power-up, input selection and gain are controlled by the DSP

or the MCU using the serial interfaces. The uplink voice path can be powered down with the bit VULON of the

VBCTL1 internal register.

Bias

MICBIAS

Generator

Side Tone

to Voice Downlink

Microphone

Amplifier

27 dB

MICIP

MICIN

IIR

Bandpass

Filter

SINC

Filter

To Voice

Serial Interface

PGA

+16.6 –7.4 dB

Sigma-Delta

Modulator

Auxiliary

Amplifier

6 dB

f

= 1 MHz

f

= 40 KHz

f

= 8 kHz

AUXI

s1

s2

s3

Figure 14. Uplink Path Block Diagram

33

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

voice downlink path

The voice downlink path receives speech samples at an 8-kHz rate from the voice serial interface and converts

them to analog signals to drive the external speech transducer.

The digital speech coming from the voice serial interface is first fed to a speech-digital infinite-duration impulse

response (IIR) filter, which has two functions (see Figure 15). The first function is to interpolate the input signal

and increase the sampling rate form 8 kHz up to 1 MHz to permit D/A conversion by an oversampling digital

modulator. The second function is to band limit the speech signal, using both low-pass and high-pass transfer

functions.

The interpolated and band-limited signal is fed to a second-order sigma-delta modulator and sampled at 1 MHz

to generate a 1-bit oversampled signal that drives a 1-bit D/A converter.

Due to the oversampling conversion, the analog signal obtained at the output of the one-bit D/A converter is

mixed with high frequency noise. This noise is filtered by a switched-capacitor third-order low-pass filter and

the remaining signal is fed to a programmable gain amplifier (PGA) to adjust the volume control. Volume control

is done in 6-dB steps from 0 dB through –24 dB; in the mute state, attenuation is higher than 40 dB. A fine

adjustment of gainispossiblefrom–6to+6dBin1-dBstepstocalibratethesystem, dependingontheearphone

characteristics. This configuration is programmed using the VBCTL2 register.

The PGA output is fed to two output stages: the earphone amplifier that provides a full differential signal on the

terminals EARP/EARN and an auxiliary output amplifier that provides a single-ended signal on terminal AUXO.

Both earphone and auxiliary output amplifiers can be active at the same time. The downlink voice path can be

powered down with bit VDLON of the VBCTL2 internal register.

A side-tone path is connected between the output of the voice uplink PGA and the input of the voice downlink

PGA. This path provides seven programmable gains (+1 dB, –2dB, –5 dB, –8 dB, –11 dB, –14 dB, –17 dB,

–20 dB, –23 dB) and one mute position. Side-tone path gain can be selected by a programming bit at register

address 23.

Side-Tone

–23 to+1dB

Auxiliary

Amplifier

–6 dB

From Voice Uplink PGA

AUXO

Smoothing

Filter

Volume Count

and PGA

One-Bit DAC

Low-Pass Filter

+3 dB

Sigma_Delta

Modulator

–3 dB

Earphone

Amplifier

0 dB

SINC

Interpolation

Filter

IIR

Bandpass

Filter

EARP

EARN

From Voice

Serial Interface

0 +24 dB and

–6 +6 dB

f

= 1 MHz

f

= 40 KHz

f

= 8 KHz

s1

s2

s3

Figure 15. Downlink Path Block Diagram

34

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

DAI interface

This digital audio interface (DAI) consists of four terminals: SSRST, SSCLK, SSDR, and SSDX. It is compatible

with the digital audio interface described in the GSM recommendation 11.10. This interface is designed to offer

minimum CPU overhead during audio tests and speech transcoding tests and to minimize the extra hardware

and the number of external terminals of the mobile system (MS). With this interface the DSP does not have to

deal with rate adaptation. In normal operation the DSP works with an 8-kHz sampling rate with a 16-bit word

format and frame synchronization, but the DAI interface works with an 8-kHz sampling rate with a 13-bit word

format without frame synchronization. The DSP (or the MCU) does not have real time constraints with SSRST,

since the reset of the internal transmitters is done automatically.

The DAI is controlled with four internal bits of VBCTL3 register:

DAION:

VDAI:

When 0, the DAI block is put in low power. When 1, the DAI block is active.

This bit controls the start of the clock SSCLK. The falling edges of SSRST automatically resets the

VDAI.

DAIMD 0/1: These two bits are used to switch the internal data path of the three types of DAI tests:

Tests of acoustic performance of the uplink/downlink voice path

Tests of speech decoder/DTX functions (downlink path)

Tests of speech encoder/DTX functions (uplink path)

In order to correctly execute these tests, the bits DAION/VULON/VDLON must be reset before starting the DAI

test. In the case of acoustic tests the following must be set with the sequence: DAION and VDAI, then VULON,

and finally VDLON. In case of vocoder tests, when the speech samples are ready to be exchanged with the

system simulator, the bits DAION and VDAI must be set at the same time.

35

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

JTAG interface

TCM4400E provides a JTAG interface according to IEEE Std1149.1. This interface uses five dedicated IOs:

TCK (test clock), TMS (test mode select), TDI (scan input), TDO (scan output), and TRST (test reset). Inputs

TMS,TDI, and TRST contain a pullup device which makes their state high when they are not driven. Output TDO

is a 3-state output which is Hi-Z except when data are shifted between TDI and TDO. TRST input is intended

for proper initialization of the state machine test access port (TAP) and boundary scan cells. System RESET

is sent into the device through a boundary-scan register, which has to be initialized by TRST to allow the RESET

signal to be propagated into the device; a good practice should be to connect RESET and TRST terminals

together.

standard user instructions available.

NAME

BYPASS

OPCODE

11111

DESCRIPTION

Connects the by-pass register between TDI and TDO.

SAMPLE/PRELOAD

00010

Connects the boundary scan register between TDI and TDO. This mode captures a snapshot of the state

of the digital I/Os of the device.

EXTEST

00000

Connects the boundary scan register between TDI and TDO. This mode captures the state of the input

terminals and forces the state of the output pins. This mode is intended for printed-circuit board

connections testing between devices.

IDCODE

INTEST

00001

00011

Connects the identification register between TDI and TDO. This is the default configuration at reset.

Connects the boundary scan register between TDI and TDO. This mode forces the internal system input

signals via the parallel latches of the boundary register and captures internal system outputs. The mode

performs device internal tests independently of the state of its input terminals. In this mode the internal

system master clock is derived from TCK and is active in the run-test-idle state of the state machine to

allow step-by-step operation of the device.

JTAG interface scan chains description

bypass register

0

1

TDI

TDO

instruction register

0

5

4

3

2

1

TDI

TDO

identification register

0

1

0

1

0

1

0

1

0

1

TDI

32

31

30

29

13

28

12

27

11

26

10

25

9

24

23

7

22

6

21

20

4

19

3

18

2

17

1

0

1

0

5

16

15

14

8

TDO

36

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

boundary scan register

PWRDN

SSCLK

OUT

SSDR

IN

SSDX

OUT

SSRST

IN

VCLK

OUT

VDR

IN

CTL

TDI

VDX

OUT

VFS

OUT

RESET

IN

BFSR

IN

BCLKR

OUT

CTL

IN

BDR

IN

BDX

OUT

BCLKX

OUT

BFSX

OUT

UCLKR

IN

CTL

UCDR

IN

UCDX

OUT

UCSEL

IN

BDLON

IN

BULON

IN

BCAL

IN

BENA

IN

CTL

TDO

power-down functional description

During certain mobile activity (such as paging, conversation mode, or idle) it is possible to disable some

TCM4400E functions in order to lower the power consumption. For example, it is possible to disable the internal

functions dedicated to radio transmission during GSM-idle mode. It is also possible to disable the internal

demodulator path during transmit window.

There are three ways to control the power consumption of the internal blocks as described in the following

paragraphs.

direct control with internal register

With this method these internal blocks are powered down:

•

DAI GSM tests: bit DAION of register VBCTL3

Transmit and receive voice path: bit VULON of register VBCTL1 and bit VDLON of register VBCTL2

37

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

radio window activation control

These internal blocks are powered up with the control of two bits. The first bit enables the window control of the

block activity; the second bit enables the power down.

First bit (PN):If cleared to 0, the function is powered down with the control of the corresponding GSM window

(BDLON/BULON terminal). If this first bit is set to 1, the power down is only controlled by the

second bit.

Second bit (PD): This bit is functionally associated with the first one. When this bit is loaded with 1, the function

is in power-down mode.

During transmit windows designated by the activity of the BULON terminal:

–

Automatic power control (APC): bits APCW and APCPD of register AUXCTL2 are paired.

Baseband uplink path: bits BBULW and BBULPD of register PWDNRG1 are paired.

External reference voltage buffers VMID: bits VMIDW and VMIDPD are paired.

During receive windows designated by the activity of the BDLON terminal:

–

Automatic gain control (AGC): bits AGCW and AGCPD of register AUXCTL2 are paired.

Baseband downlink path: bits BBDLW and BBDLPD of register PWDNRG1 are paired.

external terminal PWRDN control

These internal blocks are powered under the control of two bits. The first bit enables the external terminal

PWRDN control of the block activity, the second bit enables the power down. Terminal PWRDN is active high.

First bit (PN):

If cleared to 0, the function is powered down with the control of PWRDN terminal. If this first

bit is set to 1, the power down is only controlled by the second bit (PD).

Second bit (PD): This bit is functionally associated with the first one. When this bit is set to 1, the function is

in power-down mode.

–

For the digital serial interface to the DSP, bits BBSIPN and BBSIPD of register PWDNRG2 are paired.

For the timing interface, bits TIMGPN and TIMGPD of register PWDNRG2 are paired.

For the auxiliary A/D converters, bits ADCPN and ADCPD of register AUXCTL1 are paired.

For the automatic frequency control (AFC) block, bits AFCPN and AFCPD of register AUXCTL1 are

paired.

–

For the external reference voltage buffers MICBIAS, bits VREFPN and VREFPD of register PWDNRG2

are paired.

Fortheinternalreferenceband-gapbuffers, bitVGAPPNdetermineswhetherthebandgappowerdown

is under control of the PWRDN bit.

38

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

DSP voiceband serial interface

Voiceband serial digital interface consists of a bidirectional serial port. Both receive and transmit operations are

double buffered, thus allowing a continuous communication stream. The serial port is fully static and, thus,

functions with any arbitrary low-clocking frequency.

The transfer mode available on this port is:

Clock frequency

520 kHz

16-bit data packet

frame synchronization

VCLK is the output serial clock used to control the transmission or reception of the data, (see Figure 5). VCLK

can run in burst mode or continuous mode, depending on the VCLKMODE bit. The transmitted serial data (VDX)

is the serial data output; the frame synchronization (VFS) is used to initiate the transfer of transmit and receive

data. The received data (VDR) is the serial data input.

Each serial port includes four registers: the data transmit register (DXR), the data receive register (DRR), the

transmit shift register (XSR), and the receive shift register (RSR).

The voice serial interface has the same structure and timing diagram as the serial interface. One extra cycle

is generated before VFS, and two extra cycles are generated after the least significant bit (see Figure 5).

39

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

voltage references

Voltage and current generators are integrated inside the GSM converter. Some additional components are

required for the decoupling and regulation of the internal references. In addition, the internal buffers are

automatically shut down with the corresponding functions being powered down.

There are six terminals reserved for voltage references decoupling and use: VGAP, IBIAS, VREF, MICBIAS,

and VMID (see Table 1):

VGAP:

IBIAS:

VREF:

This terminal is connected to the internal band gap reference voltage. It must be externally

connected to a 0.1-µF capacitor. The band gap drives the current generator and the voltage

reference. This bandgap may be powered down by the PWRDN pin, depending on bit VGAPPN

of register PWDNRG2.

This terminal is connected to the current reference. It must be externally connected to a 100 kΩ

resistor. As this block is connected to the AFC function, the power down is controlled with similar

means. The current generator is shut down with the same bits as the band gap – one bit for the

power down selection of a hardware solution (with the external PWRDN terminal).

This terminal is connected to the internal reference voltage. It must be externally connected to a

0.1-µF capacitor. This band gap may be powered down with the control of the bits VREFPN and

VREFPD of the register PWDNRG2. This voltage reference is internally connected to three

buffers corresponding to the blocks of speech downlink, speech uplink, and GMSK downlink. The

two first blocks are powered down with the inactivity of the corresponding speech blocks. This last

block is shut down outside the radio downlink activations.

VMID:

This buffer gives the V /2 or 1.35 V common-mode output voltage of the baseband uplink path.

DD

This voltage value is selected with the SELVMID bit.

MICBIAS:

ADCMID:

This buffer is designed to drive an electret-type microphone. The output voltage can be chosen

by software (bit MICBIAS of VBCTL1 register) between the value 2 V to 2.5 V.

For decoupling purposes, the ADCMID terminal is connected to the internal comparison threshold

of the ADC. Setup time before the ADC is powered on is dependent on the value of the external

decoupling capacitor.

Table 1. Voltage References

REFERENCE VOLTAGE

DEFINITION

VGAP

VREF

1.22 V Band gap used for all other references

1.75 V Voltage reference of GMSK internal ADC and DAC

VMID

AV /2 Common-mode reference for uplink/downlink GMSK

DD2

MICBIAS

ADCMID

2 V / 2.5 V Microphone-driving voltage

/2 Voltage dc biasing of the auxiliary ADCs

A

VDD3

40

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

MCU serial baseband digital interface

The GSM baseband and voice A/D and D/A conversion provide two digital serial 16-bit interfaces intended for

use with the DSP and a microcontroller device. Through this interface a microcontroller can access all the

internal registers that can be accessed through the DSP digital serial interface.

This option is intended for an application in which a part of layer-1 software is implemented into the

microcontroller needs access to some functions implemented into the GSM baseband and voice A/D and D/A

conversion circuitry.

serial interface

The microcontroller serial interface is designed to be compliant with 8-bit standard synchronous serial ports.

This interface consists of four terminals (see Figure 3 for timing diagram).

UCLK:

UDR:

A clock provided by the microcontroller to GSM baseband and voice A/D and D/A conversion

AninputterminaloftheGSMbasebandandvoiceA/DandD/Acomponentsintendedforreception

of data

UDX:

An output terminal of the GSM baseband and voice A/D and D/A components intended for

transmission of data

USEL:

An input terminal of GSM baseband and voice A/D and D/A components intended for activation

of the serial interface

When USEL = V , the serial interface is deactivated and UDX is placed in a high-impedance state. A high level

DD

on USEL resets the internal serial interface; the 16-bit transfers must be completed with USEL = V

.

SS

The external MCU initiates data transfer by driving the selection terminal and sending a clock signal. For both

the GSM baseband and voice A/D and D/A components, the MCU data is shifted out of the shift registers on

one edge of the clock and latched into the shift registers on the opposite clock edge.

As a result, both controllers send and receive data simultaneously. For the MCU portion, the software

determines whether the data is meaningful or dummy data. On the GSM baseband and voice A/D and D/A

conversion portion, dummy data is data with all zeroes.

The 16-bit word data format is identical to the DSP data format. After a read-register command, there is a

sequential transfer delay between two 16-bit word acquisitions to let the internal sequencer extract the data

going from internal registers to the serial shift register.

Three internal bits control the data serial flow as follows:

•

UDIR determines whether data is transferred with MSB or LSB first.

UPOL determines the polarity of the clock.

UPHA determines the insertion of a half-clock period in the data serial flow.

With UPOL and UPHA there are four clock schemes (see Table 2):

•

Falling edge without delay. The MCU serial interface transmits data on the falling edge of the UCLK and

receives data on the rising edge of the UCLK.

Falling edge with delay. The MCU serial interface transmits data one half-cycle ahead of the fallingedge

of the UCLK and receives data on the falling edge of the UCLK.

Rising edge without delay. The MCU serial interface transmits data on the rising edge of the UCLK and

receives data on the falling edge of the UCLK.

Rising edge with delay. The MCU serial interface transmits data one half-cycle ahead of the rising edge

of the UCLK and receives data on the rising edge of the UCLK.

41

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

serial interface (continued)

Table 2. Microcontroller Clocking Schemes

UPOL

UPHA

MCU CLOCKING SCHEME

Falling edge without delay

Falling edge with delay

1

0

1

0

1

0

Rising edge without delay

Rising edge with delay

DSP/MCU serial interface

The DSP/MCU serial interface not only configures the GSM baseboard and voice A/D and D/A conversion but

alsotransmitsdatatotheDSPduringdownlinkburstreactions. Thefollowingparagraphsdescribetheoperation

of the serial interface in more detail.

DSP serial digital interface

The DSP serial digital interface (Figure 16) is used to transfer the baseband transmit and receive data, and it

is also used to access all internal programming registers of the device (baseband codec, voice codec, and

auxiliary RF functions). The format for the serial interface is 16 bits.

The baseband serial digital interface is a bidirectional (transmit/receive) serial port. Both receive and transmit

operations are double buffered and permit a continuous communication stream (16-bit data packets). The serial

port is fully static and functions with any arbitrary, low-clocking frequency.

Six terminals are used for the serial port interface (see Figure 4 for timing diagram). BCLKR is an I/O port for

the serial clock used to control the reception of the data BDR. At reset BCLKR is configured as an output and

the clock frequency is set to MCLK/3 (4.333 MHz with MCLK = 13 MHz); the clock signal is running permanently.

The port BCLKR can be reconfigured as an input by programming an internal register. In this case BCLKR is

provided by the DSP. It can run in burst mode to reduce power consumption. The receive frame synchronization

(BFSR) is used to identify the beginning of a data packet transfer on port BDR.

The transmitted serial data (BDX) is the serial data input; the transmit frame synchronization (BFSX) is used

to initiate the transmission of data. The transmit clock (BCLKX) is provided by the GSM baseband and voice

A/D and D/A converters with a MCLK frequency. The clock signal BCLKX can run in burst mode or continuous

mode, depending on the BCLKMODE bit. The downlink data bus (BFSX, BCLKX, BDX) can be driven to VSS

or placed in a high-impedance state when no data is to be transferred to the DSP. The BCLKDIR bit of the

BCTLREG register controls the direction of the BCLKR clock.

As with the voice serial interface, on extra clock cycle must be generated because the last 16-bit word received

on the DSP serial interface is latched on the next two falling BCLKR edges following the LSB. As for the voice

serial interface, one extra clock period is generated on the BCLKX before the first synchronization BFSX of the

downlink data sequence.

42

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

Data Bus

16

Load

DRR

DXR

Control

Logic

Control

Logic

16

RSR

XSR

Clear

Clock

Clear

Clock

Byte/Word

Counter

Byte/Word

Counter

BDR

BFSR BCLKR BCLKX BFSX

BDX

Figure 16. DSP Serial Digital Interface

timing interface

The timing interface performs accurate timing control of baseband uplink and downlink paths. The timing

interface is a parallel asynchronous port with four control signals, refer to Figure 17. The BDLON bit controls

power on the downlink path of the baseband codec; the BULON bit controls power on the uplink path of the

baseband codec, and the BCAL bit controls the calibration of the active parts of the baseband codec selected

by BULON or BDLON.

The BENA bit controls the transmission of the reception of burst depending on which part of the baseband codec

is selected by the signals BULON or BDLON. These asynchronous inputs are internally synchronized with the

uplink and downlink internal clocks and stored in timing register TR. The timing register, TR, is a 6-bit register

containing the bits defined in Table 3.

Table 3. 6-Bit TR Register

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

ULON

ULCAL

ULSEND

DLON

DLCAL DLREC

TR bit signification

ULON:

Ifsetto1, thisbitturnsontheuplinkpathofthebasebandcodec;ifclearedto0, theuplinkpath

is in power-down mode.

ULCAL:

When this bit is set to 1, the uplink offset autocalibration is active.

ULSEND:

A transition from 0 to 1 of ULSEND initiates the emission of a burst. The burst information

data, burst length, and power level need to be loaded in the corresponding registers using the

serial interface.

DLON:

If set at 1, this bit turns on the downlink path of the baseband codec; if cleared to 0, the

downlink path is in power-down mode.

DLCAL:

DLREC:

When this bit is set at 1, the downlink offset autocalibration is active.

A transition from 0 to 1 of DLREC initiates the transmission of data from the baseband codec

to the DSP using the serial interface.

43

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

BDLON

BCAL BULON

BENA

CKDL

CKUL

DLON DLCAL DLREC ULON ULCAL ULSEND

Figure 17. Timing Interface

DSP/MCU serial interface operation and format

The DSP/MCU serial interface configures the GSM baseband, the voice A/D and D/A converters (read and write

operation in internal registers), and transmits RF data to the DSP during the reception of a burst by the downlink

path of the GSM baseband and voice A/D and D/A circuitry.

During reception of a burst (bit DLR of the status register is 1) and DSP serial interface and associated internal

bus are dedicated to the transfer of RF data from the GSM baseband A/D and D/A converters to the DSP. During

this period only a write operation of internal registers can be done through the DSP serial interface. However,

all registers can be accessed by the serial MCU interface.

During transmission of a burst (bit ULX of the status register is 1) no read or write operation can be done in the

registers of the baseband uplink part of the GSM baseband, APC RAM, and APC shape register.

Writing or reading registers using the serial interface is done by transferring 16-bit words to the serial interface.

Each word is split into three fields as shown in Table 4.

Table 4. Read/Write Data Word

DATA

10

ADDRESS

R/W

15

14

13

12

11

9

8

7

6

5

4

3

2

1

1 / 0

When writing to internal registers observe the following convention:

Bit 0

: A 0 indicates a write operation.

: This field contains the address of the register to be accessed.

Bits 1 to 5

Bits 6 to 15 : This field contains the data to be written into the internal register.

When reading from internal registers observe the following convention:

Bit 0

: A 1 indicates a read operation.

Bits 1 to 5

: This field contains the address of the register to be accessed.

Bits 6 to 15 : This field is an irrelevant status in a read request operation.

44

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

Read operation from the downlink baseband codec is done using the TX part of the DSP/MCU serial interface

in the following 16-bit word format given in Table 5.

Table 5. 16-Bit Word Format

DATA

10

D4

ADDRESS

15

14

13

12

11

9

8

7

6

5

4

3

2

1

0

D9

D8

D7

D6

D5

D3

D2

D1

D0

A4

A3

A2

A1

A0

During reception of a burst, transfer of RF data from the downlink baseband codec is done using the transmit

part of the DSP serial interface in the following 16-bit word format: As the I and Q samples are coded with 16-bit

words, the data rate is 270833 × 16 × 2 which equals 8.66 Mbps. I & Q samples are differentiated by setting the

LSB to zero for I samples and to one for Q samples. Since the digital clock MCLK is 13 MHz, transfer is done

at 13 Mbps in burst mode. During burst reception the DSP serial interface is idled about 33% of the time.

Table 6. Format of 16-Bit Word Transfer

DATA

8

I/Q

0

15

14

13

12

11

10

9

7

6

5

4

3

2

1

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

DSP/MCU serial interface registers

The following internal register buffers are accessed using the DSP/MCU serial interface during manual

operation of the TCM4400E.

baseband uplink ramp delay register

Each bit position of the baseband uplink ramp-delay register is given in Table 7.

Table 7. Uplink Ramp-Delay Register

BULRUDEL: BASEBAND UPLINK RAMP DELAY REG.

ADDRESS: 1

R/W

RESERVD

IBUFPTR DELD3 DELD2 DELD1 DELD0 DELU3 DELU2 DELU1 DELU0

0

1

1 / 0

R = 0

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

<––– ACCESS TYPE

<–––VALUE AT RESET

DELU0 to DELU3

DELD0 to DELD3

IBUFPTR

: Value of the delay of ramp-up start versus the rising edge of BENA

: Value of the delay of ramp-down start versus the falling edge of BENA

: Writing a 1 in this bit initializes the pointer of the burst buffer to the base address.

(This is not a toggle bit and has to be set back to 0 to allow writing into the burst

buffer).

RESERVD

R/W

: Reserved bits for testing purposes

: A 1 indicates a read operation; a 0 indicates a write operation.

45

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

baseband uplink data buffer

The baseband uplink data buffer is used to transmit the uplink burst data. The uplink data buffer contents are

shown in Table 8.

Table 8. Uplink Data Buffer

BULDATA: BASEBAND UPLINK DATA BUFFER

ADDRESS: 2 (16 WORDS)

W

0

BIT0

BIT1

BIT2

BIT3

BIT4

BIT5

BIT6

BIT7

BIT8

BIT9

0

1

0

BIT10

BIT20

BIT30

BIT40

BIT50

BIT60

BIT70

BIT80

BIT90

BIT11

BIT21

BIT31

BIT41

BIT51

BIT61

BIT71

BIT81

BIT91

BIT12

BIT22

BIT32

BIT42

BIT52

BIT62

BIT72

BIT82

BIT92

BIT13

BIT23

BIT33

BIT43

BIT53

BIT63

BIT73

BIT83

BIT93

BIT14

BIT24

BIT34

BIT44

BIT54

BIT64

BIT74

BIT84

BIT94

BIT15

BIT25

BIT35

BIT45

BIT55

BIT65

BIT75

BIT85

BIT95

BIT16

BIT26

BIT36

BIT46

BIT56

BIT66

BIT76

BIT86

BIT96

BIT17

BIT27

BIT37

BIT47

BIT57

BIT67

BIT77

BIT87

BIT97

BIT18

BIT28

BIT38

BIT48

BIT58

BIT68

BIT78

BIT88

BIT98

BIT19

BIT29

BIT39

BIT49

BIT59

BIT69

BIT79

BIT89

BIT99

BIT100 BIT101 BIT102 BIT103 BIT104 BIT105 BIT106 BIT107 BIT108 BIT109

BIT110 BIT111 BIT112 BIT113 BIT114 BIT115 BIT116 BIT117 BIT118 BIT119

BIT120 BIT121 BIT122 BIT123 BIT124 BIT125 BIT126 BIT127 BIT128 BIT129

BIT130 BIT131 BIT132 BIT133 BIT134 BIT135 BIT136 BIT137 BIT138 BIT139

BIT140 BIT141 BIT142 BIT143 BIT144 BIT145 BIT146 BIT147 BIT148 BIT149

BIT150 BIT151 BIT152 BIT153 BIT154 BIT155 BIT156 BIT157 BIT158 BIT159

W

1

W

1

W

1

W

1

W

1

W

1

W

1

W

1

W

1

W

1

<–––ACCESS TYPE

<–––VALUE AT RESET

Bit 0 – Bit 159 are the bits composing the sequence of the transmitted burst, bit 0 is transmitted first. For a normal

burst, the uplink data buffer is loaded as follows:

Bit 0 to 3

: 4 guard bits

Bit 4 to 6

: 3 tail bits

Bit 7 to 66

Bit 67 to 92

Bit 93 to 92

: 58 data bits

: 26 training sequence bits

: 58 training sequence bits

Bit 151 to 153 : 3 tail bits

Bit 154 to 159 : 8 guard bits

At reset and after each transmission, the burst buffer is reinitialized with guard bits (all bits = 1). An address

pointer is incremented after each word written into the buffer so that next write operation affects the next word

of the buffer. This address pointer is set to the base address (Word 0) by a RESET, after transmission of a burst

or by setting the IBUFPTR bit to 1( this bit has to be set back to zero to release the address pointer).

46

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

baseband uplink I and Q offset registers

The baseband uplink I and Q offset registers contain the offset values for the I and Q components, respectively,

as shown in Tables 9 and 10.

Table 9. Uplink I Offset Register

BULIOFF: BASEBAND UPLINK I OFFSET REGISTER

ADDRESS: 3 R/W

1/0

<–ACCESS TYPE

<–VALUE AT RESET

RESERVD ULIOFF8 ULIOFF7 ULIOFF6 ULIOFF5 ULIOFF4 ULIOFF3 ULIOFF2 ULIOFF1 ULIOFF

0 0 0 1 1

R

0

R/W

0

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

ULIOFF0 to ULIOFF1 : Integration bits during calibration (to minimize sensitivity to noise)

ULIOFF2 to ULIOFF8 : Value of the offset on I channel

RESERVD

R/W

: Reserved bits for testing purposes

: A 1 indicates a read operation; a 0 indicates a write operation.

Table 10. Uplink Q Offset Register

BULQOFF: BASEBAND UPLINK Q OFFSET REGISTER

ADDRESS: 4

R/W

RESERVD ULQOFF8 ULQOFF7 ULQOFF6 ULQOFF5 ULQOFF4 ULQOFF3 ULQOFF2 ULQOFF1 ULQOFF0

0

1

0

1/0

R

0

R/W

0

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

<–ACCESS TYPE

<–VALUE AT RESET

ULQOFF0 to ULQOFF1: Integration bits during calibration (to minimize sensitivity to noise)

ULQOFF2 to ULQOFF8: Value of the offset on Q channel

RESERVD

R/W

: Reserved bits for testing purposes

: A 1 indicates a read operation; a 0 indicates a write operation.

baseband uplink I and Q D/A conversion registers

The I and Q component values generated by the I and Q uplink D/A converter during the conversion of analog

data are written to and read from the uplink I and Q D/A converter registers as shown in Tables 11 and 12.

Table 11. Uplink I DAC Register

BULIDAC: BASEBAND UPLINK I DAC REGISTER

ADDRESS: 6 R/W

RESERVD

0

1

0

1/0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

<–ACCE0S TYPE

<–VALUE AT RESET

RESERVD

: Reserved bits for testing purposes

47

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

Table 12. Uplink Q DAC Register

BULQDAC: BASEBAND UPLINK Q DAC REGISTER

ADDRESS: 5 R/W

RESERVD

0

1

0

1/0

R

0

R

0

R

0

R

1

R

1

R

1

R

1

R

1

R

1

R

1

<–ACCE0S TYPE

<–VALUE AT RESET

RESERVD

: Reserved bits for testing purposes

Power down register No. 2

The values in each bit position of power-down register No. 2 have the meaning outlined in Table 13.

Table 13. PWDNRG2 Register

PWDNRG2: REGISTER FOR POWERING DOWN

ADDRESS: 8 R/W

RESERVD RESERVD

TIMGPN

R/W

0

TIMGPD

R/W

0

BBSIPN

R/W

0

BBSIPD

R/W

0

VGAPPN

R/W

0

CHGUP

R/W

0

VREFPN

R/W

0

VREFPD

R/W

0

1

0

1/0

R = 0

0

R = 0

0

<–ACCESS TYPE

<–VALUE AT RESET

VREFPN: If cleared to 0, the internal reference voltage is powered down under the control of terminal

PWRDN and bit VREFPD. If bit VREFPN is set to 1, the power down is only controlled by bit

VREFPD.

VREFPD: This bit is functionally associated with bit VREFPN.

VGAPPN: If cleared to 0, the internal reference VGAP is powered down under the control of terminal

PWRDN. If this bit is set to 1, the VGAP is not placed in power-down mode.

TIMGPN: If cleared to 0, the internal reference VGAP is powered down under the control of terminal

PWRDN. If this bit is set to 1, the power-down control is only controlled by bit TIMPGD

TIMGPD: This bit is functionally associated with bit TIMGPN.

BBSIPN: If cleared to 0, the baseband serial interface is powered down under the control of terminal

PWRDN. If this bit is set to 1, the power down is only controlled by bit BBSIPD.

BBSIPD: This bit is functionally associated with bit BBSIPN. When this bit is set to 1, baseband serial

interface is in power-down mode.

CHGUP: This bit is used for testing purposes to accelerate the bandgap settling time.

RESRVD: Reserved bits for testing purpose

48

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

power down register No. 1

The values in each bit position of power down register No. 1 have the meaning outlined in Table 14.

Table 14. PWDNRG1 Register

PWDNRG1: REGISTER FOR POWERING DOWN

ADDRESS: 7 R/W

SELVMID

R/W

0

BALOOP

R/W

0

VMIDW

R/W

0

VMIDPD

R/W

0

BBULW

R/W

0

BBULPD

R/W

0

BBDLW

R/W

0

BBDLPD

R/W

0

EXTCAL

R/W

0

BBRST

R/W

0

1

1/0

<–ACCESS TYPE

<–VALUE AT RESET

BBRST:

This is the digital reset of the baseband codec (active at 1); the uplink burst buffer is loaded with

all 1s and the memory and registers of the downlink digital filter is cleared to 0. This is not a

toggle bit as it has to be set to 0 to remove the reset condition.

EXTCAL: Downlink autocalibration mode (at 0: autocalibration; at 1: external calibration)

BBULW:

Ifclearedto0, thebasebanduplinkpathispowereddownunderthecontroloftheGSMtransmit

window (BULON terminal). If this bit is set to 1, the power down is only controlled by bit

BBULPD.

BBULPD: This bit is functionally associated with bit BBULW. When this bit is set to 1, the baseband uplink

path is in power-down mode.

BBDLW:

If cleared to 0, the baseband downlink path is powered down under the control of GSM receive

window (BDLON terminal). If this bit is set to 1, the power down is only controlled by bit

BBDLPD.

BBDLPD: This bit is functionally associated with bit BBDLW. When this bit is set to 1, the baseband

downlink path is in power-down mode.

VMIDW:

If cleared to 0, the VMID output driver is powered down under the control of GSM transmit

window (BULON terminal). If this bit is set to 1, the power down is only controlled by bit

VMIDPD.

VMIDPD: This bit is functionally associated and paired with bit VMIDW. When VMIDW bit is set to 1, the

VMID output driver is active. When VMIDPD bit is set to 1, the VMID output driver is in

power-down mode.

BALOOP: When set to 1, the internal analog loop of I and Q uplink terminals are connected to I and Q

downlink terminals.

SELVMID: When cleared to 0, this sets the common-mode voltage of the baseband uplink and VMID at

V

/2; when set to 1, these voltages are set to 1.35 V.

DD

49

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

baseband control register (see Table 15)

The values in the baseband control register bit positions determine whether the data is shifted left or right. Note

that the microcontroller unit (MCU) clocking scheme determines on which edge of the clock that data is received

or transmitted using the serial interface.

Table 15. Baseband Control Register

BCTLREG: BASEBAND CONTROL REGISTER

ADDRESS: 9

R/W

RESERVD RESERVD RESERVD MCLKBP BCLKMODE BIZBUS

BCLKDIR

R/W

0

UDIR

R/W

0

UPHA

R/W

0

UPOL

R/W

0

1

0

1

1/0

R = 0

0

R = 0

0

R = 0

0

R /W

0

R /W

0

R/W

0

<–ACCESS TYPE

<–VALUE AT RESET

UDIR:

This bit determines whether the data is shifted in from right (see serial register description) to

left, MSB first (bit value 0), or from left to right, LSB first (bit value 1).

BCLKMODE:When cleared to 0, BLCKX runs in the burst mode; when set to 1, BCLKX is continuous.

MCLKBP:

Whenclearedto0, MCLKsignalpassesthroughtheclockslicer;whensetto1, theclockslicer

is bypassed (in this case, the signal at the MCLK terminal must be digital).

MCU clocking schemes

Falling edge without delay: The MCU serial interface transmits data on the falling edge of the UCLK and

receives data on the rising edge of UCLK.

Falling edge with delay:

TheMCUserialinterfacetransmitsdataonehalf-cycleaheadofthefallingedge

of the UCLK and receives data on the falling edge of the UCLK.

Rising edge without delay: The MCU serial interface transmits data on the rising edge of the UCLK and

receives data on the falling edge of the UCLK.

Rising edge with delay:

The MCU serial interface transmits data one half-cycle ahead of the rising edge

of the UCLK and receives data on the rising edge of UCLK.

Table 16. MCU Clocking Schemes

UPOL

UPHA

MCU CLOCKING SCHEME

Falling edge without delay

1

0

1

0

1

0

Falling edge with delay

Rising edge without delay

Rising edge with delay

BCLKDIR: Direction of the BCLKR port ( 0 –> Output, 1–> Input).

BIZBUS:

When set to 1, BDX, BCLKX, BFSX are in hi-Z when there is nothing to transfer to the DSP;

when cleared to 0, DBX, BCLKX, BFSX are set to V when there is nothing to transfer to the

SS

DSP.

RESRVD:

Reserved bits for testing purpose

50

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

voiceband uplink control register

The values in the voiceband uplink control register bit positions control not only the power level of the audio in

the uplink path but also set the gain of the PGA from –12 dB to 12 dB in 1 dB steps. Bit MICBIAS and VULMIC

and VULAUX are shifted by one position to the left. This is shown in Table 17.

Table 17. Voiceband Uplink Control Register

VBCTL1: VOICEBAND UPLINK CONTROL REGISTER

ADDRESS: 10 R/W

VDXMUTE

MICBIAS

R /W

0

VULMIC

R/W

0

VULAUX

R/W

0

VULPG4

R/W

0

VULPG3

R/W

0

VULPG2

R/W

0

VULPG1

R/W

0

VULPG0

R/W

0

VULON

R/W

0

1

0

1

0

1/0

R/W

0

<–ACCESS TYPE

<–VALUE AT RESET

VULON:

Power on the uplink path of the audio codec

VULAUX:

VULMICL:

MICBIAS:

Enables the auxiliary input amplifier if bit VULON is 1

Enables the microphone input amplifier if bit VULON is 1

When MICBIAS = 0, the analog bias for the electret-type microphone and external

decoupling is driven to 2 V; when the value is 1, the bias is 2.5 V.

VDXMUTE:

When VDXMUTE = 1, the VDX output is forced to zero, when the value is 0, VDX is

transmitted normally. To avoid cutting a VDX word during transmission due to

asynchronism of writing this bit via DSP or MCU serial interface, VDXMUTE is internally

resynchronized with the 8 KHz voice frame.

VULPG (0–4):

Gain of the voice uplink programmable gain amplifier (–12 dB to 12 dB in 1 dB step), see

Table 18.

51

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

Table 18. Uplink PGA Gain

VULPG 4 VULPG 3 VULPG 2 VULPG 1 VULPG 0

RELATIVE GAIN

–12 dB

–11 dB

–10 dB

–9 dB

–8 dB

–7 dB

–6 dB

–5 dB

–4 dB

–3 dB

–2 dB

–1 dB

0 dB

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1 dB

2 dB

3 dB

4 dB

5 dB

6 dB

7 dB

8 dB

9 dB

10 dB

11 dB

12 dB

voiceband downlink control register

The values in the voiceband downlink control register bit positions control the audio power level in the downlink

path. Earphone volume is set (three bits VOLCTL0 –VOLCTL2) and PGA gain is set from –6 dB to 6 dB in 1

dB steps. This is shown in Table 19.

Table 19. Voiceband Downlink Control Register

VBCTL2: VOICEBAND DOWNLINK CONTROL REGISTER

ADDRESS: 11 R/W

VDLAUX

R/W

0

VDLEAR

R/W

0

VOLCTL2

R/W

0

VOLCTL1

R/W

0

VOLCTL0

R/W

0

VDLG3

R/W

0

VDLG2

R/W

0

VDLG1

R/W

0

VDLG0

R/W

0

VDLON

R/W

0

1

0

1

1 / 0

<–ACCESS TYPE

<–VALUE AT RESET

VDLON:

VDLEAR:

VDLAUX:

Power on of the downlink path of the audio codec

Enables the earphone amplifier if the VDLON bit is 1

Enables the auxiliary output amplifier if the VDLON bit is 1

VGLG (0–3) 1 dB:

Gainofthevoice-downlinkprogrammablegainamplifier(–6dBto6dBin1-dBsteps);

see Table 20.

52

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

Table 20. Downlink PGA Gain

VDLG3 VDLG2 VDLG1 VDLG0 RELATIVE GAIN

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

–6 dB

–5 dB

–4 dB

–3 dB

–2 dB

–1 dB

0 dB

2

3

4

5

6

7

1 dB

8

2 dB

9

3 dB

10

11

12

13

14

15

4 dB

5 dB

6 dB

–6 dB

VOLCTL (0–2):

Volume control (0, –6 ,–12, 18, –24, Mute), see Table 21.

Table 21. Volume Control Gain Settings

VOLCTL2 VOLCTL1 VOLCTL0 RELATIVE GAIN

0

1

2

3

4

5

6

7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0 dB

–6 dB

–12 dB

–18 dB

–24 dB

Mute

53

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

voiceband control register

The values in the voiceband control register have the meaning shown in Table 22.

Table 22. Voiceband Control Register

VBCTL3: VOICEBAND CONTROL REGISTER

ADDRESS: 12 R/W

RESERVD RESERVD VCLKMODE

DAIMD1

R/W

0

DAIMD0

R/W

0

VDAI

R/W

0

DAION

R/W

0

VALOOP

R/W

0

VIZBUS

R/W

0

VRST

R/W

0

1

0

1 / 0

R = 0

0

R = 0

0

R /W

0

<–ACCESS TYPE

<–VALUE AT RESET

VALOOP:

When set to 1, the internal analog loop of output samples are sent to the audio input

terminal; standard audio paths are connected together, and auxiliary audio paths are

connected together.

VIZBUS:

When set to 1, VFS, VCLK, and VDX are put in a hi-Z state when there is nothing to transfer

to the DSP. When cleared to 0, VFS and VCLK are put in V when there is nothing to

SS

transfer to the DSP, and the VDX bus drives an undefined value (value depends on the

previous serial data transfers).

VRST:

When1, resetsthedigitalpartsoftheaudiocodec(digitalfilterandmodulator). Thisisnota

toggle bit and has to be set to 0 to remove the reset condition

DAION:

VDAI:

When cleared to 0, the DAI block is in power down; when set to 1, the DAI block is active.

Writing a 1 to this bit starts the SSCLK (104 kHz DAI clock) on reception of the first sample.

This bit is automatically reset to 0 by SSRST after reception of the last sample.

RESERVD:

Reserved bits for testing

DAIMD (0–1): DAI mode selection as given in Table 23.

VCLKMODE: When cleared to 0, allows selection of VCLK in burst mode. When set to 1, allows selection

of VCLK in continuous mode.

Table 23. DAI Mode Selection

DAIMD1 DAIMD0

DAI MODE

0

1

0

1

0

1

Normal operation (no tested device using DAI)

Test of speech decoder / DTX functions (downlink)

Test of speech encoder / DTX functions (uplink)

Test of acoustic devices and A/D and D/A (voice path)

54

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

auxiliary functions control register 1

Thebitvaluesintheauxiliaryfunctionscontrolregister1resetstheAPCgeneratorortheAFCmodulator, selects

the A/D counter input, and selects the AFC sampling frequency. This is shown in Table 24.

Table 24. AUX Functions Control Register 1

UXCTL1: AUXILIARY FUNCTIONS CONTROL REGISTER

ADDRESS: 13 R/W

AFCPN

R/W

0

AFCPD

R/W

0

ADCPN

R/W

0

ADCPD

R/W

0

AFCCK1

R/W

0

AFCCK0

R/W

0

ADCCH2

R/W

0

ADCCH1

R/W

0

ADCCH0

R/W

0

ARST

R/W

0

1

0

1

1/0

<–ACCESS TYPE

<–VALUE AT RESET

ARST:

Reset of the digital parts for the auxiliary function (APC generator and AFC modulator).

This is not a toggle bit and has to be set to 0 to remove the reset condition.

ADCCH (0–2):

Selection of the input of the A/D converter; see Table 25.

Table 25. A/D Converter Selection

ADCCH2

ADCCH1

ADCCH0 A/D CONVERTER INPUT SELECTION

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A/D conversion of ADIN1

A/D conversion of ADIN2

A/D conversion of ADIN3

A/D conversion of ADIN4

A/D conversion of ADIN5

AFCCK (0–1): Selection of the sampling frequency of the AFC, see Table 26.

Table 26. AFC Selection

AFCCK1

AFCCK0

AFC INTERNAL FREQUENCY

0

1

0

1

0

1

0.25 MHz

0.50 MHz

1 MHz

2 MHz

AFCPN:

AFCPD:

If cleared to 0, the AFC block is powered down under the control of the PWRDN terminal. If

this bit is set to 1, the power down is only controlled by bit AFCPD.

This bit is functionally associated and paired with bit AFCPN. When the AFCPN bit is 1, the

AFC block is active. When the AFCPD bit is set to 1, the AFCPD block is in power-down

mode.

ADCPN:

ADCPD:

Ifclearedto0, theauxiliaryADCblockispowereddownwhenunderthecontrolofPWRDN.

If this bit is set to 1, the power down is only controlled by bit ADCPD.

This bit is functionally associated and paired with bit ADCPN. When the ADCPN bit is set to

1, an auxiliary ADC is active. When the ADCPD bit is set to 1, the auxiliary ADCPD is in

power-down mode.

55

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

automatic frequency control registers (1 and 2)

TherearetwoAFCcontrolregisters;eachis10bitswide. AFCcontrolregisterNo. 1containstheleastsignificant

bit of the AFC D/A converter output. AFC control register No. 2 contains the most significant bit of the AFC D/A

converter input. See Tables 27 and 28. The AFC value is loaded after writing to the AFC MSB register (first) and

then the LSB register (second) .

Table 27. AFC Control Register 1

AUXAFC1: AUTOMATIC FREQUENCY CONTROL REG1

ADDRESS: 14 R/W

1/0

BIT9

R/W

0

BIT8

R/W

0

BIT7

R/W

0

BIT6

R/W

0

BIT5

R/W

0

BIT4

R/W

0

BIT3

R/W

0

BIT2

R/W

0

BIT1

R/W

0

BIT0

R/W

0

1

0

<–ACCESS TYPE

<–VALUE AT RESET

BIT 9–0:

LSB input of the 13-bit AFC D/A converter in 2s complement.

Table 28. AFC Control Register 2

AUXAFC2: AUTOMATIC FREQUENCY CONTROL REG2

ADDRESS: 15

R/W

RESRVD

R = 0

0

RESRVD

R = 0

0

RESRVD

R = 0

0

RESRVD

R = 0

0

RESRVD

R = 0

0

RESRVD

R = 0

0

RESRVD

R = 0

0

BIT12

R/W

0

BIT11

R/W

0

BIT10

R/W

0

1

1/0

<–ACCESS TYPE

<–VALUE AT RESET

BIT 12–10:

MSB input of the 13-bit AFC D/A converter in 2s complement.

automatic power control register

The values in the automatic power control (APC) register set the operating conditions for the APC circuit, see

Table 29.

Table 29. APC Register

AUXAPC: AUTOMATIC POWER CONTROL REGISTER

ADDRESS: 16

R/W

RESERVD RESERVD

BIT7

R/W

0

BIT6

R/W

0

BIT5

R/W

0

BIT4

R/W

0

BIT3

R/W

0

BIT2

R/W

0

BIT1

R/W

0

BIT0

R/W

0

1

0

1/0

R = 0

0

R = 0

0

<–ACCESS TYPE

<–VALUE AT RESET

BIT 7–0:

Input of the 8-bit level APC DAC.

Reserved bits for testing

RESERVD:

56

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

automatic frequency control registers (1 and 2)

The content of the APC RAM describes the shape of the ramp-up and ramp-down control; see Table 30.

Table 30. APC Ramp Control

APCRAM: AUTOMATIC POWER CONTROL RAM

ADDRESS: 17 (64 Words)

W

0

RDWN WORD0 (5 BIT)

RUP WORD0 ( 5 BIT)

RUP WORD2 (5 BIT)

. . .

1

0

1

RDWN WORD1 (5BIT)

0

. . .

1

. . .

0

. . .

0

. . .

0

. . .

1

. . .

0

. . .

RDWNWORD62 (5BIT)

RDWNWORD63 (5BIT)

RUP WORD62 (5 BIT)

RUP WORD63 (5 BIT)

1

0

1

0

W

X

W

X

W

X

W

X

W

X

W

X

W

X

W

X

W

X

W

X

<—ACCESS TYPE

<—VALUE AT RESET

Actual shape values (five bits long) are contained in the shape D/A converter input register as shown in

Table 31.

Table 31. Shape DAC Input Register

APCSHAP: SHAPE DAC INPUT REGISTER

ADDRESS: 18

R/W

RESERVD RESERVD RESERVD RESERVD RESERVD

BIT4

R/W

0

BIT3

R/W

0

BIT2

R/W

0

BIT1

R/W

0

BIT0

R/W

0

1

0

1

0

1/0

R = 0

0

R = 0

0

R = 0

0

R = 0

0

R = 0

0

<–ACCESS TYPE

<–VALUE AT RESET

BIT 4–0:

Input of the 5-bit APC DAC.

Reserved bits for testing

RESERVD:

AGC control register

The AGC control register is 10-bits wide and controls operations of the analog AGC circuit as shown in Table 32.

Table 32. Analog AGC Gain Control Register

AUXAGC: AUTOMATIC GAIN CONTROL REGISTER

ADDRESS: 19

R/W

BIT9

R/W

0

BIT8

R/W

0

BIT7

R/W

0

BIT6

R/W

0

BIT5

R/W

0

BIT4

R/W

0

BIT3

R/W

0

BIT2

R/W

0

BIT1

R/W

0

BIT0

R/W

0

1

0

1

1/0

<–ACCESS TYPE

<–VALUE AT RESET

BIT 9 to 0:

Input of the 10-bit AAGC DAC.

Reserved bits testing.

RESERVD:

57

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

auxiliary functions control register 2 (see Table 33)

The values in the auxiliary function control register No. 2 set the operation parameters as described below:

APCSPD:

IAPCPTR:

When cleared to 0, the APC clock is at 4 MHz; when set to 1, the APC clock is at 2 MHz.

Setting to 1 initializes the pointer of the APC RAM to the base address. This is not a toggle

bit and has to be set to 0 to set APC RAM operational.

APCMODE:

AGCW:

Select the equation used for APC waveform generation.

If cleared to 0, the automatic gain control path is powered down with the control of GSM

receive window (BDLON terminal) and AGCPD bit. If the AGCPD bit is set to 1, the

power down is controlled by AGCPD bit.

AGCPD:

APCW:

This bit is functionally associated with AGCW bit. When this bit is set to 1, the automatic

gain control path is in power-down mode.

If 0, the RF power control path is down powered with the control of GSM transmit window

(BULON)and with the control of APCPD bit. If the APCPD bit is set to 1, power down is only

controlled by APCPD bit.

APCPD:

ThisbitisfunctionallyassociatedwiththeBBULWbit. Whenthisbitissetto1, theRFpower

control path is in power-down mode.

Table 33. AUX Functions Control Register No. 2

AUXCTL2: AUXILIARY FUNCTIONS CONTROL REGISTER

AGCW AGCPD APCW APCPD IAPCTR APCMODE RESERVD RESERVD APCSPD RESERVD

ADDRESS: 20

R/W

1

0

1

0

1/0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R

0

R

0

R/W

0

R

0

<–ACCESS TYPE

<–VALUE AT RESET

auxiliary A/D converter output register

This register is read-only; however, if there is an attempt to write into it, an A/D conversion operation starts; see

Table 34. When the A/D conversion is finished, the AUXADC register is loaded and the A/D converter is

automatically down powered. During the conversion process the ADCEOC bit of the BSTATUS register is set.

This bit is reset automatically after AUXADC is loaded.

Table 34. AUX A/D Converter Output Register

AUXADC: AUXILIARY A/D CONVERTER OUTPUT REGISTER

ADDRESS: 21

R

BIT9

R/W

0

BIT8

R/W

0

BIT7

R/W

0

BIT6

R/W

0

BIT5

R/W

0

BIT4

R/W

0

BIT3

R/W

0

BIT2

R/W

0

BIT1

R/W

0

BIT0

R/W

0

1

0

1

0

1

1/0

<–ACCESS TYPE

<–VALUE AT RESET

BIT 9 to 0:

Output pf the 10-bit monitoring ADC.

58

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

baseband status register

The baseband status register stores the baseband status as described in Table 35.

Table 35. Baseband Status Register

BSTATUS: BASEBAND STATUS REGISTER

ADDRESS: 22

R

RESERVD

R = 0

0

ADCEOC

RAMPTR

BUFPTR

ULON

ULCAL

ULX

R

DLON

DLCAL

DLR

R

1

0

1

0

1

R

0

R

0

R

0

R

0

R

0

R

0

R

0

<–ACCESS TYPE

0

<–VALUE AT RESET

DLR:

This bit is set to 1 during conversion of a burst in the downlink path.

This bit is set to 1 during offset calibration of the downlink path.

When set to 1, it indicates that the downlink path is powered on.

This bit is set to 1 during transmission of the burst in the uplink path.

This bit is set to 1 during offset calibration of the uplink path.

When set to 1, it indicates that the uplink path is powered on.

DLCAL:

DLON:

ULX:

ULCAL:

ULON:

BUFPTR:

RAMPTR:

ADCEOC:

When set to 1, it indicates that the pointer of the burst buffer is at address zero.

When set to 1, it indicates that the pointer of the APC RAM is at address zero.

(ADC-end of conversion) when this bit is set to 1, an ADC conversion is in process.

Voiceband control register 4 (address 23)

Voicebandcontrolregister4(VBCTL4)isaread/writeregister(seeTable36)andcontainsthefourprogramming

bits of VDLST as shown in Table 37.

Table 36. Voiceband Control Register 4

VBCTL4: VOICEBAND CONTROL REGISTER 4

ADDRESS: 23

R/W

RESERVD RESERVD RESERVD RESERVD RESERVD RESERVD VDLST3 VDLST2 VDLST1 VDLST0

1

0

1

1/0

R=0

0

R=0

0

R=0

0

R=0

0

R=0

0

R=0

0

R/W

0

R/W

0

R/W

0

R/W

0

<–ACCESS TYPE

<–VALUE AT RESET

Table 37. VDLST Status

VDLST3 VDLST2 VDLST1 VDLST0

SIDE TONE GAIN

Mute

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

–23 dB

–20 dB

–17 dB

–14 dB

–11 dB

–8 dB

–5 dB (nominal)

–2 dB

+1 dB

59

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

PRINCIPLES OF OPERATION

baseband uplink register (address 24)

The baseband uplink register (BULCTL) is a 3-bit register (see Table 38) that permits mismatch compensation

in the RF transmit mixer, and 1 bit (OUTLEV) to set the differential output dynamic range (V ) to 2 times V

PP

ref

when OUTLEV = 0 or to 8/15 V when OUTLEV = 1. Gain mismatches of 0 dB, –0.25 dB, –0.5 dB, and –0.75

ref

dB are permitted between the I and Q channel as shown in Table 39.

Table 38. Uplink Register BULCTL

BULCTL: BASEBAND UPLINK CONTROL REGISTER

ADDRESS: 24 R/W

RESERVD RESERVD RESERVD RESERVD RESERVD RESERVD

OUTLEV

R/W

0

IQSEL

R/W

0

G1

R/W

0

G0

R/W

0

1

0

1/0

R=0

0

R=0

0

R=0

0

R=0

0

R=0

0

R=0

0

<–ACCESS TYPE

<–VALUE AT RESET

Table 39. BLKCTL Register

BIT2

BIT1

BIT0

G0

0

GAIN I

GAIN Q

IQSEL

G1

0

1

0 dB

–0.25 dB

–0.50 dB

–0.75 dB

0 dB

0

1

0

0 dB

1

0 dB

0

0 dB

0

1

0 dB

– 0.25 dB

–0.50 dB

–0.75 dB

1

0

0 dB

1

0 dB

power on status register (address 25)

The power-on status register is a 9 bit read-only register which displays the status power-on / power-down of

the functions having several power on/off controls. When the function is in power-on the corresponding bit is

at 1.

Table 40. Power On Register PWONCTL

PWONCTL: POWER-ON STATUS REGISTER

ADDRESS: 25

R/W

RESERVD

BGAPON

VREFON

BBIFON

TIMIFON

VMIDON

AFCON

ADCON AGCON

APCON

1

0

1

1/0

R=0

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

<–ACCESS TYPE

<–VALUE AT RESET

60

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

MECHANICAL DATA

PET (S-PQFP-G80)

PLASTIC QUAD FLATPACK

0,23

0,13

0,40

M

0,08

60

41

61

40

80

21

0,13 NOM

1

20

7,60 TYP

Gage Plane

10,20

SQ

9,80

0,25

12,20

SQ

0,05 MIN

11,80

0°–7°

1,05

0,95

0,75

0,45

Seating Plane

0,07

1,20 MAX

4147704/A 12/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

61

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

MECHANICAL DATA

PN (S-PQFP-G80)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

60

M

0,08

41

61

40

0,13 NOM

80

21

1

20

Gage Plane

9,50 TYP

0,25

12,20

SQ

11,80

0,05 MIN

0°–7°

14,20

SQ

13,80

0,75

0,45

1,45

1,35

Seating Plane

0,08

1,60 MAX

4040135 /B 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

62

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

MECHANICAL DATA

GGM (S-PBGA-N80)

PLASTIC BALL GRID ARRAY

10,10

9,90

SQ

7,20 TYP

0,80

0,40

0,80

K

J

H

G

F

E

D

C

B

A

0,40

1

2

3

4

5

6

7

8

9

10

0,95

0,85

1,40 MAX

Seating Plane

0,10

0,55

0,45

0,12

0,08

M

0,08

0,45

0,35

4145257-2/B 11/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. MicroStar BGA configuration

MicroStar BGA is a trademark of Texas Instruments.

63

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

Customers are responsible for their applications using TI components.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

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型号：	TCM4400ETQFP
厂家：	TEXAS INSTRUMENTS
描述：	GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT GSM / DCS基带和语音A / D和D / A射频接口电路射频分布式控制系统 GSM DCS
文件：	总64页 (文件大小：886K)
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