TDA2EGAHQABCQ1 [TI]
适用于 ADAS 应用且具有图形和视频加速功能的 SoC 处理器（23mm 封装） | ABC | 760 | -40 to 125;
| 型号： | TDA2EGAHQABCQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于 ADAS 应用且具有图形和视频加速功能的 SoC 处理器（23mm 封装） | ABC | 760 | -40 to 125 |
| 文件： | 总393页 (文件大小：5014K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
适用于高级驾驶辅助系统 (ADAS) 的 TDA2Ex SoC
23mm 封装（ABC 封装）
器件版本 2.0
1 器件概述
1.1 特性
1
• 专为 ADAS 应用设计的 架构
• 支持视频、图像和图形处理
• 六个高速集成电路间 (I2C) 端口
• 10 个可配置 UART/IrDA/CIR 模块
• 4 个多通道串行外设接口 (McSPI)
• 四路 SPI 接口 (QSPI)
– 全高清视频（1920 x 1080p，60fps）
– 多个视频输入和视频输出
• Arm® Cortex®-A15 微处理器子系统
• SATA 接口
• C66x 浮点超长指令字 (VLIW) 数字信号处理器
• 8 个多通道音频串行端口 (McASP) 模块
• 超高速 USB 3.0 双角色设备
• 高速 USB 2.0 双角色设备
• 高速 USB 2.0 On-The-Go
(DSP)
– 目标代码与 C67x 和 C64x+ 完全兼容
– 每周期最多 32 次 16 x 16 位定点乘法
• 高达 512KB 的片上 L3 RAM
• 3 级 (L3) 和 4 级 (L4) 互连
• DDR3/DDR3L 存储器接口 (EMIF) 模块
– 最高支持 DDR3-1333 (667MHz)
– 高达 2GB 的单芯片选择
• 双核 Arm® Cortex®-M4 图像处理单元 (IPU)
• IVA-HD 子系统
• 四个多媒体卡/安全数字/安全数字输入输出接口
( MMC™/ SD®/SDIO)
• 带有两个 5Gbps 通道的 PCI Express®具有集成型
PHY 的 3.0 端口
– 1 个与第 2 代兼容的双通道端口
– 或 2 个与第 2 代兼容的单通道端口
• 双控制器局域网 (DCAN) 模块
– CAN 2.0B 协议
• MIPI®CSI-2 摄像头串行接口
• 多达 215 个通用 I/O (GPIO) 引脚
• 实时时钟子系统 (RTCSS)
• 器件安全 特性
• 显示子系统
– 具有 DMA 引擎和多达 3 条管线的显示控制器
– HDMI™编码器：兼容 HDMI 1.4a 和 DVI 1.0
• 单核 PowerVR®SGX544 3D GPU
• 2D 图形加速器 (BB2D) 子系统
– Vivante®GC320 内核
– 硬件加密加速器和 DMA
– 防火墙
• 视频处理引擎 (VPE)
– JTAG 锁定
– 安全密钥
– 安全 ROM 和引导
• 一个视频输入端口 (VIP) 模块
– 支持多达 4 个复用输入端口
• 通用存储器控制器 (GPMC)
• 电源、复位和时钟管理
• 片上调试，采用 CTool 技术
• 28nm CMOS 技术
• 增强型直接存储器存取 (EDMA) 控制器
• 2 端口千兆以太网 (GMAC)
– 最多 2 个外部端口，1 个内部端口
• 16 个 32 位通用计时器
• 23mm × 23mm、0.8mm 间距、760 引脚 BGA
(ABC)
• 32 位 MPU 看门狗计时器
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SPRS958
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
1.2 应用
•
单声道立体场或 Tri-Optic 前置摄像头
•
LVDS 或以太网环视
–
–
–
–
–
–
–
–
对象检测
–
–
–
–
–
–
–
2D 环视
行人检测
3D 环视
交通标志识别
车道检测和偏离警告
自动紧急刹车
自适应巡航控制
前部碰撞警告
远光灯辅助
车后物体检测
停车辅助
行人检测
车道跟踪
行车记录
•
传感器融合 – 视觉、雷达、超声波和激光雷达传感
器
–
–
物体数据融合
原始数据融合
1.3 说明
TI 的全新 TDA2Ex 片上系统 (SoC) 是经过高度优化的可扩展系列器件，专为满足领先的高级驾驶辅助系统
(ADAS) 的要求而设计。TDA2Ex 系列集最佳的性能、低功耗和 ADAS 视觉分析处理功能于一体，可广泛应
用于当今汽车领域中的 ADAS 应用 以推动实现更自主的无碰撞驾驶体验。
TDA2Ex SoC 通过广泛的 ADAS 支持复杂的嵌入视觉技术 应用 ，包括泊车辅助、环视以及传感器融合系
统。
TDA2Ex SoC 采用异类可扩展架构，包含 TI 的定点和浮点 TMS320C66x 数字信号处理器 (DSP) 生成内
核、Arm Cortex-A15 MPCore™ 和双 Cortex-M4 处理器的组合。它集成有视频加速器，可用于解码以太网
AVB 网络中的多个视频流，并与用于渲染虚拟视图的图形加速器相结合，可以实现 3D 观影体验。TDA2Ex
SoC 还集成了诸多外设，包括支持以太网或 LVDS 环视系统的多摄像头接口（并行和串行，包括 CSI-2）、
显示屏和千兆位以太网 AVB。
此外，TI 提供了一整套针对 Arm 和 DSP 的开发工具，其中包括 C 语言编译器、用于简化编程和调度的
DSP 汇编优化器、可查看源代码执行情况的调试界面等。
TDA2Ex ADAS 处理器符合 AEC-Q100 标准。
器件信息
封装
器件编号
封装尺寸
TDA2EG
FCBGA (760)
23.0mm x 23.0mm
2
器件概述
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
1.4 功能方框图
图 1-1 是器件的功能方框图。
TDA2Ex
CAL
CSI2 x2
MPU
IVA HD
(1x Arm
Cortex–A15)
1080p Video
Co-Processor
IPU 1
(Dual Cortex–M4)
Display Subsystem
GPU
1x GFX Pipeline
3x Video Pipeline
Blend / Scale
LCD1
(1x SGX544 3D)
IPU 2
(Dual Cortex–M4)
LCD2
LCD3
DSP
BB2D
HDMI 1.4a
(C66x Co-Processor)
(GC320 2D)
EDMA
JTAG
MMU x2
VIP x1
VPE
High-Speed Interconnect
System
Connectivity
RTC SS
Spinlock
Mailbox x13
GPIO x8
Timers x16
WDT
1x USB 3.0
Dual Mode FS/HS/SS
w/ PHY
PCIe SS x2
GMAC AVB
SDMA
PWM SS x3
2x USB 2.0
Dual Mode FS/HS
1x PHY, 1x ULPI
Program/Data Storage
SATA
Serial Interfaces
GPMC / ELM
(NAND/NOR/
Async)
EMIF
1x 32-bit
DDR3/3L W/ECC
QSPI
McASP x8
I2C x6
UART x10
McSPI x4
DCAN x2
512-KB
RAM
256-KB ROM
OCMC
MMC / SD x4
DMM
intro-001
Copyright © 2016, Texas Instruments Incorporated
图 1-1. TDA2Ex 框图
版权 © 2016–2018, Texas Instruments Incorporated
器件概述
3
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
内容
1
器件概述.................................................... 1
1.1 特性 ................................................... 1
1.2 应用 ................................................... 2
1.3 说明 ................................................... 2
1.4 功能方框图 ........................................... 3
修订历史记录............................................... 5
Device Comparison ..................................... 6
3.1 Device Comparison Table............................ 6
Terminal Configuration and Functions.............. 8
4.1 Terminal Assignment ................................. 8
4.2 Ball Characteristics ................................... 9
4.3 Multiplexing Characteristics ......................... 69
4.4 Signal Descriptions.................................. 85
Specifications ......................................... 121
5.1 Absolute Maximum Ratings........................ 121
5.2 ESD Ratings ....................................... 123
5.3 Power on Hour (POH) Limits ...................... 123
5.4 Recommended Operating Conditions ............. 123
5.5 Operating Performance Points..................... 127
5.6 Power Consumption Summary .................... 148
5.7 Electrical Characteristics........................... 148
5.8 Thermal Characteristics............................ 157
5.9 Power Supply Sequences ......................... 158
Clock Specifications ................................. 169
6.1 Input Clock Specifications ......................... 170
6.2 DPLLs, DLLs Specifications ....................... 178
7.10 External Memory Interface (EMIF)................. 217
7.11 General-Purpose Memory Controller (GPMC)..... 217
7.12 Timers.............................................. 241
7.13 Inter-Integrated Circuit Interface (I2C)............. 241
7.14 Universal Asynchronous Receiver Transmitter
(UART) ............................................. 244
7.15 Multichannel Serial Peripheral Interface (McSPI) . 246
7.16 Quad Serial Peripheral Interface (QSPI) .......... 252
7.17 Multichannel Audio Serial Port (McASP) .......... 256
7.18 Universal Serial Bus (USB) ........................ 276
2
3
4
7.19 Serial Advanced Technology Attachment (SATA). 277
7.20 Peripheral Component Interconnect Express
(PCIe) .............................................. 278
7.21 Controller Area Network Interface (DCAN) ........ 278
7.22 Ethernet Interface (GMAC_SW) ................... 279
7.23 eMMC/SD/SDIO ................................... 292
7.24 General-Purpose Interface (GPIO) ................ 315
7.25 System and Miscellaneous interfaces ............. 316
7.26 Test Interfaces ..................................... 316
Applications, Implementation, and Layout ...... 320
8.1 Introduction ........................................ 320
8.2 Power Optimizations ............................... 321
8.3 Core Power Domains .............................. 332
8.4 Single-Ended Interfaces ........................... 342
8.5 Differential Interfaces .............................. 344
5
8
9
6
7
8.6
DDR3 Board Design and Layout Guidelines....... 363
Device and Documentation Support.............. 386
9.1
Timing Requirements and Switching
Device Nomenclature and Orderable Information . 386
Characteristics ........................................ 182
9.2 Tools and Software ................................ 388
9.3 Documentation Support............................ 388
7.1 Timing Test Conditions ............................ 182
7.2 Interface Clock Specifications ..................... 182
7.3 Timing Parameters and Information ............... 182
9.4
Receiving Notification of Documentation Updates. 389
9.5 Community Resources............................. 389
9.6 商标 ................................................ 389
9.7 静电放电警告....................................... 389
9.8 出口管制提示....................................... 389
9.9 术语表.............................................. 389
7.4
Recommended Clock and Control Signal Transition
Behavior............................................ 184
7.5 Virtual and Manual I/O Timing Modes ............. 184
7.6 Video Input Ports (VIP) ............................ 186
7.7
Display Subsystem - Video Output Ports.......... 205
Display Subsystem - High-Definition Multimedia
7.8
10 Mechanical Packaging Information ............... 390
Interface (HDMI) ................................... 216
Camera Serial Interface 2 CAL bridge (CSI2) ..... 217
10.1 Mechanical Data ................................... 390
7.9
4
内容
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
2 修订历史记录
Changes from March 1, 2018 to June 7, 2018 (from E Revision (March 2018) to F Revision)
Page
•
•
•
•
•
•
•
•
在以下位置将引用的“ARM”更新为“Arm”：节 1.1特性 ............................................................................ 1
Updated "ARM" references to "Arm" in 表 3-1, Device Comparison........................................................... 6
Added missing balls in 表 4-1, Unused Balls Specific Connection Requirements ........................................... 9
Updated "ARM" references to "Arm" in 表 4-29, INTC Signal Descriptions................................................ 116
Added table note for maximum valid input voltage on an IO pin to 节 5.1, Absolute Maximum Ratings .............. 121
Removed voltage high level limits from CSI2 ULPS state in 表 5-14, LVCMOS CSI2 DC Electrical Characteristics 152
Added references to notes under 表 5-14, LVCMOS CSI2 DC Electrical Characteristics ............................... 152
Updated resetn timing in power and reset sequencing. Added clarification on the limits of resetn timing during
the power/clock/reset sequence diagrams (图 5-2, 图 5-5) and their footnotes ........................................... 159
Updated DPLL type A CLKOUT output frequency ............................................................................ 180
Removed duplicated IOSETs from 表 7-5, VIN2 IOSETs .................................................................... 189
Added new DPI VOUT Switching Characteristics tables as well as their associated MANUAL4 and MANUAL5 IO
delays ............................................................................................................................... 205
Updated phase polarity in all QSPI timing figures............................................................................. 253
Updated IOSET2 MUX in 表 7-63, USB3 IOSETs ............................................................................ 277
Added CAN delay time receive and transmit parameters in relation to the shift registers .............................. 279
Updated "ARM" references to "Arm" in 表 7-134, Switching Characteristics Over Recommended Operating
•
•
•
•
•
•
•
Conditions for IEEE 1149.1 JTAG With RTCK ................................................................................ 317
Added new parameter in 表 8-23, Length Mismatch Guidelines for CSI-2 (1.5 Gbps) ................................... 362
Updated "ARM" references to "Arm" in section Trademarks................................................................. 389
•
•
版权 © 2016–2018, Texas Instruments Incorporated
修订历史记录
5
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
3 Device Comparison
3.1 Device Comparison Table
表 3-1 shows a comparison between devices, highlighting the differences.
表 3-1. Device Comparison
Device
Features
TDA2EG
Features
CTRL_WKUP_STD_FUSE_DIE_ID_2[31:24] Base PN register bitfield value(1)
TDA2EGx: 20 (0x14)
Processors/Accelerators
Speed Grades
H, D
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Arm Single Cortex-A15 Microprocessor (MPU) Subsystem
C66x VLIW DSP
MPU core 0
DSP1
BB2D
VOUT1
VOUT2
VOUT3
HDMI
IPU1
BitBLT 2D Hardware Acceleration Engine (BB2D)
Display Subsystem
Dual Arm Cortex-M4 Image Processing Unit (IPU)
IPU2
Image Video Accelarator (IVA)
IVA
SGX544 Single-Core 3D Graphics Processing Unit (GPU)
GPU
vin1a
vin1b
Video Input Port (VIP)
VIP1
vin2a
vin2b
Video Processing Engine (VPE)
Program/Data Storage
VPE
On-Chip Shared Memory (RAM)
General-Purpose Memory Controller (GPMC)
OCMC_RAM1
GPMC
512KB
Yes
EMIF1
up to 2GB across single chip select
DDR3 Memory Controller
SECDED/ECC
DMM
Yes
Yes
Dynamic Memory Manager (DMM)
Peripherals
DCAN1
Yes
Dual Controller Area Network (DCAN) Interface
DCAN2
Yes
Enhanced DMA (EDMA)
EDMA
Yes
Yes
System DMA (DMA_SYSTEM)
DMA_SYSTEM
GMAC_SW[0]
GMAC_SW[1]
GPIO
MII, RMII, or RGMII
MII, RMII, or RGMII
up to 215
Ethernet Subsystem (Ethernet SS)
General-Purpose I/O (GPIO)
Inter-Integrated Circuit Interface (I2C)
System Mailbox Module
I2C
6
MAILBOX
CSI2_0
13
1 CLK + 4 Data Line
1 CLK + 2 Data Line
Camera Adaptation Layer (CAL) Camera Serial Interface 2 (CSI2)
CSI2_1
6
Device Comparison
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
Features
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 3-1. Device Comparison (continued)
Device
TDA2EG
16 serializers
16 serializers
4 serializers
4 serializers
4 serializers
4 serializers
4 serializers
4 serializers
1x UHSI 4b
1x eMMC™ 8b
1x SDIO 8b
1x SDIO 4b
Yes
McASP1
McASP2
McASP3
McASP4
McASP5
McASP6
McASP7
McASP8
MMC1
Multichannel Audio Serial Port (McASP)
MMC2
MultiMedia Card/Secure Digital/Secure Digital Input Output Interface
(MMC/SD/SDIO)
MMC3
MMC4
PCIe_SS1
PCIe_SS2
SATA
PCI Express 3.0 Port with Integrated PHY
Yes
Serial Advanced Technology Attachment (SATA)
Real-Time Clock Subsystem (RTCSS)
Multichannel Serial Peripheral Interface (McSPI)
Quad SPI (QSPI)
Yes
RTCSS
Yes
McSPI
4
QSPI
Yes
Spinlock Module
SPINLOCK
TIMERS GP
WD TIMER
PWMSS1
PWMSS2
PWMSS3
UART
Yes
Timers, General-Purpose
16
Timer, Watchdog
Yes
Yes
Pulse-Width Modulation Subsystem (PWMSS)
Yes
Yes
Universal Asynchronous Receiver/Transmitter (UART)
Universal Serial Bus (USB3.0)
10
USB1 (Super-Speed, Dual-
Role-Device [DRD])
Yes
USB2 (High-Speed, Dual-
Role-Device [DRD], with
embedded HS PHY)
Yes
Universal Serial Bus (USB2.0)
USB3 (High-Speed, OTG2.0,
with ULPI)
Yes
No
USB4 (High-Speed, OTG2.0,
with ULPI)
(1) For more details about the CTRL_WKUP_STD_FUSE_DIE_ID_2 register and Base PN bitfield, see the TDA2Ex Technical Reference
Manual.
版权 © 2016–2018, Texas Instruments Incorporated
Device Comparison
7
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
4 Terminal Configuration and Functions
4.1 Terminal Assignment
图 4-1 shows the ball locations for the 760 plastic ball grid array (PBGA) package and is used in
conjunction with 表 4-2 through 表 4-31 to locate signal names and ball grid numbers.
SPRS906_BALL_01
图 4-1. ABC S-PBGA-N760 Package (Bottom View)
注
The following bottom balls are not pinned out: AF7, AF10, AF13, AF16, AF19, AE4, AE25,
AB26, W3, W26, T3, T26, N3, N26, K3, K26, G3, D4, D25, C10, C13, C16, C19, C22.
These balls do not exist on the package.
注
The following bottom balls are not connected: AH11, AH12, AG2, AG8, AG11, AG12, AF4,
AF6, AF8, AF9, AE3, AE5, AE6, AE8, AE9, AD3, AD8, AD9, Y15, Y16, V18, V19, U18, U19,
U22, U23, U24, U25, U26, U27, U28, T22, T23, T27, T28, R20, R22, R23, R24, R25, R26,
R27, R28, P19, P22, P23, P24, P25, P26, P27, N20, N22, N23, N27, N28, M20, M21, M22,
M23, M24, M25, M26, M27, M28, L20, L21, L22, L23, L24, L25, L26, L27, L28, K20, K21,
K22, K23, K27, K28, J20, J21, J22, J23, J24, J25, J26, J27, H20, H21, H22, H23, H24, H25,
H26, H27, H28, G22, G23, G24, G25, G26, G27, G28, F24, F25, F26, F27, F28, E24, E26,
E27, E28
These balls can be connected as desired, including to VSS. For users designing TDA2x
compatible PCB, please refer to TDA2x Data Manual for appropriate requirements.
4.1.1 Unused Balls Connection Requirements
This section describes the connection requirements of the unused and reserved balls.
8
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
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ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
注
The following balls are reserved: A27, K14, Y5, Y10, B28, AC1, AC2, AA1, AA2, AB1, AB2,
AD14.
These balls must be left unconnected.
注
All unused power supply balls must be supplied with the voltages specified in the 节 5.4,
Recommended Operating Conditions, unless alternative tie-off options are included in 节 4.4,
Signal Descriptions.
表 4-1. Unused Balls Specific Connection Requirements
Balls
Connection Requirements
AE15, AC15, AE14, D20, AD17, AC16, V27, AH25, AE27, AD27,
Y28
These balls must be connected to GND through an external pull
resistor if unused.
E20, D21, E23, C20, C21, V28, F18, AG25, AE28, AD28, Y27, F17,
C25
These balls must be connected to the corresponding power supply
through an external pull resistor if unused.
This ball should be connected to the corresponding power supply
through an external pull resistor if unused; or can be connected to
F22 (porz) when RTC unused (level translation may be needed)
AF14 (rtc_iso)
This ball should be connected to VSS when RTC is unused; or can
be connected to F22 (porz) when RTC unused (level translation may
be needed)
AB17 (rtc_porz)
注
All other unused signal balls with a Pad Configuration register can be left unconnected with
their internal pullup or pulldown resistor enabled.
注
All other unused signal balls without a Pad Configuration register can be left unconnected.
4.2 Ball Characteristics
表 4-2 describes the terminal characteristics and the signals multiplexed on each ball. The following list
describes the table column headers:
1. BALL NUMBER:This column lists ball numbers on the bottom side associated with each signal on the
bottom.
2. BALL NAME: This column lists mechanical name from package device (name is taken from muxmode
0).
3. SIGNAL NAME:This column lists names of signals multiplexed on each ball (also notice that the name
of the ball is the signal name in muxmode 0).
注
表 4-2 does not take into account the subsystem multiplexing signals. Subsystem
multiplexing signals are described in 节 4.4, Signal Descriptions.
注
In driver off mode, the buffer is configured in high-impedance.
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
9
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
注
In some cases 表 4-2 may present more than one signal name per muxmode for the same
ball. First signal in the list is the dominant function as selected via CTRL_CORE_PAD_*
register.
All other signals are virtual functions that present alternate multiplexing options. This virtual
functions are controlled via CTRL_CORE_ALT_SELECT_MUX or
CTRL_CORE_VIP_MUX_SELECT register. For more information on how to use this options,
please refer to Device TRM, Chapter Control Module, Section Pad Configuration Registers.
4. MUXMODE: Multiplexing mode number:
a. MUXMODE 0 is the primary mode; this means that when MUXMODE=0 is set, the function
mapped on the pin corresponds to the name of the pin. The primary muxmode is not necessarily
the default muxmode.
注
The default mode is the mode at the release of the reset; also see the RESET REL.
MUXMODE column.
b. MUXMODE 1 through 15 are possible muxmodes for alternate functions. On each pin, some
muxmodes are effectively used for alternate functions, while some muxmodes are not used. Only
MUXMODE values which correspond to defined functions should be used.
c. An empty box means Not Applicable.
5. TYPE: Signal type and direction:
–
–
–
–
–
–
–
–
–
I = Input
O = Output
IO = Input or Output
D = Open drain
DS = Differential Signaling
A = Analog
PWR = Power
GND = Ground
CAP = LDO Capacitor
6. BALL RESET STATE: The state of the terminal at power-on reset:
–
–
–
–
–
–
drive 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated)
drive 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated)
OFF: High-impedance
PD: High-impedance with an active pulldown resistor
PU: High-impedance with an active pullup resistor
An empty box means Not Applicable
7. BALL RESET REL. STATE: The state of the terminal at the deactivation of the rstoutn signal (also
mapped to the PRCM SYS_WARM_OUT_RST signal)
–
–
–
–
–
–
–
drive 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated)
drive clk (OFF): The buffer drives a toggling clock (pulldown or pullup resistor not activated)
drive 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated)
OFF: High-impedance
PD: High-impedance with an active pulldown resistor
PU: High-impedance with an active pullup resistor
An empty box means Not Applicable
10
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
注
For more information on the CORE_PWRON_RET_RST reset signal and its reset sources,
see the Power, Reset, and Clock Management / PRCM Reset Management Functional
Description section of the Device TRM.
8. BALL RESET REL. MUXMODE: This muxmode is automatically configured at the release of the
rstoutn signal (also mapped to the PRCM SYS_WARM_OUT_RST signal).
An empty box means Not Applicable.
9. IO VOLTAGE VALUE: This column describes the IO voltage value (VDDS supply).
An empty box means Not Applicable.
10. POWER: The voltage supply that powers the terminal IO buffers.
An empty box means Not Applicable.
11. HYS: Indicates if the input buffer is with hysteresis:
–
–
–
Yes: With hysteresis
No: Without hysteresis
An empty box: Not Applicable
注
For more information, see the hysteresis values in 节 5.7, Electrical Characteristics.
12. BUFFER TYPE: Drive strength of the associated output buffer.
An empty box means Not Applicable.
注
For programmable buffer strength:
–
–
The default value is given in 表 4-2.
A note describes all possible values according to the selected muxmode.
13. PULLUP / PULLDOWN TYPE: Denotes the presence of an internal pullup or pulldown resistor.
Pullup and pulldown resistors can be enabled or disabled via software.
–
–
–
–
–
–
PU: Internal pullup
PD: Internal pulldown
PU/PD: Internal pullup and pulldown
PUx/PDy: Programmable internal pullup and pulldown
PDy: Programmable internal pulldown
An empty box means No pull
14. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0" or
logic "1") when the peripheral pin function is not selected by any of the PINCNTLx registers.
–
–
–
0: Logic 0 driven on the peripheral's input signal port.
1: Logic 1 driven on the peripheral's input signal port.
blank: Pin state driven on the peripheral's input signal port.
注
Configuring two pins to the same input signal is not supported as it can yield unexpected
results. This can be easily prevented with the proper software configuration (Hi-Z mode is not
an input signal).
注
When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that
pad’s behavior is undefined. This should be avoided.
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
11
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
注
Some of the EMIF1 signals have an additional state change at the release of porz. The state
that the signals change to at the release of porz is as follows:
drive 0 (OFF) for: ddr1_csn0, ddr1_ck, ddr1_nck, ddr1_casn, ddr1_rasn, ddr1_wen,
ddr1_ba[2:0], ddr1_a[15:0].
OFF for: ddr1_ecc_d[7:0], ddr1_dqm[3:0], ddr1_dqm_ecc, ddr1_dqs[3:0], ddr1_dqsn[3:0],
ddr1_dqs_ecc, ddr1_dqsn_ecc, ddr1_d[31:0].
注
Dual rank support is not available on this device, but signal names are retained for
consistency with the TDA2xx family of devices.
12
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-2. Ball Characteristics(1)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
K9
cap_vbbldo_dsp
cap_vbbldo_dsp
CAP
Y14
J10
J16
T20
L9
cap_vbbldo_gpu
cap_vbbldo_iva
cap_vbbldo_mpu
cap_vddram_core1
cap_vddram_core3
cap_vddram_core4
cap_vddram_dsp
cap_vddram_gpu
cap_vddram_iva
cap_vddram_mpu
csi2_0_dx0
cap_vbbldo_gpu
cap_vbbldo_iva
cap_vbbldo_mpu
cap_vddram_core1
cap_vddram_core3
cap_vddram_core4
cap_vddram_dsp
cap_vddram_gpu
cap_vddram_iva
cap_vddram_mpu
csi2_0_dx0
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
I
J19
J9
Y13
K16
K19
AE1
0
1.8
vdda_csi
vdda_csi
vdda_csi
vdda_csi
vdda_csi
vdda_csi
vdda_csi
vdda_csi
vdda_csi
vdda_csi
vdda_csi
vdda_csi
vdda_csi
vdda_csi
vdda_csi
vdda_csi
Yes
LVCMOS
CSI2
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
AF1
AF2
AH4
AH3
AD2
AE2
AF3
AG4
AG3
AG5
AG6
AH7
AH5
AH6
AG7
csi2_0_dx1
csi2_0_dx2
csi2_0_dx3
csi2_0_dx4
csi2_0_dy0
csi2_0_dy1
csi2_0_dy2
csi2_0_dy3
csi2_0_dy4
csi2_1_dx0
csi2_1_dx1
csi2_1_dx2
csi2_1_dy0
csi2_1_dy1
csi2_1_dy2
csi2_0_dx1
csi2_0_dx2
csi2_0_dx3
csi2_0_dx4
csi2_0_dy0
csi2_0_dy1
csi2_0_dy2
csi2_0_dy3
csi2_0_dy4
csi2_1_dx0
csi2_1_dx1
csi2_1_dx2
csi2_1_dy0
csi2_1_dy1
csi2_1_dy2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
LVCMOS
CSI2
LVCMOS
CSI2
LVCMOS
CSI2
LVCMOS
CSI2
LVCMOS
CSI2
LVCMOS
CSI2
LVCMOS
CSI2
LVCMOS
CSI2
LVCMOS
CSI2
LVCMOS
CSI2
LVCMOS
CSI2
LVCMOS
CSI2
LVCMOS
CSI2
LVCMOS
CSI2
LVCMOS
CSI2
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
13
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
BALL NAME [2]
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
G19
dcan1_rx
dcan1_rx
uart8_txd
0
IO
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
1
0
2
O
I
mmc2_sdwp
sata1_led
hdmi1_cec
gpio1_15
Driver off
dcan1_tx
uart8_rxd
mmc2_sdcd
hdmi1_hpd
gpio1_14
Driver off
ddr1_a0
3
4
O
IO
IO
I
6
14
15
0
G20
dcan1_tx
IO
I
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
1
1
1
2
3
I
6
IO
IO
I
14
15
0
AD20
AC19
AC20
AB19
AF21
AH22
AG23
AE21
AF22
AE22
AD21
AD22
AC21
AF18
AE17
ddr1_a0
ddr1_a1
ddr1_a2
ddr1_a3
ddr1_a4
ddr1_a5
ddr1_a6
ddr1_a7
ddr1_a8
ddr1_a9
ddr1_a10
ddr1_a11
ddr1_a12
ddr1_a13
ddr1_a14
O
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
LVCMOS
DDR
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
ddr1_a1
ddr1_a2
ddr1_a3
ddr1_a4
ddr1_a5
ddr1_a6
ddr1_a7
ddr1_a8
ddr1_a9
ddr1_a10
ddr1_a11
ddr1_a12
ddr1_a13
ddr1_a14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
O
O
O
O
O
O
O
O
O
O
O
O
O
O
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
14
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
AD18
AF17
AE18
AB18
AC18
AG24
AG22
AH23
AB16
AF25
AF26
AG26
AH26
AF24
AE24
AF23
AE23
AC23
AF27
AG27
AF28
AE26
AC25
ddr1_a15
ddr1_a15
ddr1_ba0
ddr1_ba1
ddr1_ba2
ddr1_casn
ddr1_ck
0
O
O
O
O
O
O
O
O
O
PD
drive 1 (OFF)
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
ddr1_ba0
ddr1_ba1
ddr1_ba2
ddr1_casn
ddr1_ck
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PU
PU
PU
PU
PD
PU
PU
PU
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
drive 1 (OFF)
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
LVCMOS
DDR
drive 1 (OFF)
LVCMOS
DDR
drive 1 (OFF)
LVCMOS
DDR
drive 1 (OFF)
LVCMOS
DDR
drive 0 (OFF)
LVCMOS
DDR
ddr1_cke
ddr1_csn0
ddr1_csn1
ddr1_d0
ddr1_d1
ddr1_d2
ddr1_d3
ddr1_d4
ddr1_d5
ddr1_d6
ddr1_d7
ddr1_d8
ddr1_d9
ddr1_d10
ddr1_d11
ddr1_d12
ddr1_d13
ddr1_cke
ddr1_csn0
ddr1_csn1
ddr1_d0
ddr1_d1
ddr1_d2
ddr1_d3
ddr1_d4
ddr1_d5
ddr1_d6
ddr1_d7
ddr1_d8
ddr1_d9
ddr1_d10
ddr1_d11
ddr1_d12
ddr1_d13
drive 1 (OFF)
LVCMOS
DDR
drive 1 (OFF)
LVCMOS
DDR
drive 1 (OFF)
LVCMOS
DDR
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
15
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
BALL NAME [2]
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
AC24
AD25
V20
ddr1_d14
ddr1_d15
ddr1_d16
ddr1_d17
ddr1_d18
ddr1_d19
ddr1_d20
ddr1_d21
ddr1_d22
ddr1_d23
ddr1_d24
ddr1_d25
ddr1_d26
ddr1_d27
ddr1_d28
ddr1_d29
ddr1_d30
ddr1_d31
ddr1_dqm0
ddr1_dqm1
ddr1_dqm2
ddr1_dqm3
ddr1_dqm_ecc
ddr1_d14
ddr1_d15
ddr1_d16
ddr1_d17
ddr1_d18
ddr1_d19
ddr1_d20
ddr1_d21
ddr1_d22
ddr1_d23
ddr1_d24
ddr1_d25
ddr1_d26
ddr1_d27
ddr1_d28
ddr1_d29
ddr1_d30
ddr1_d31
0
IO
PD
PD
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PU
PU
PU
PU
PU
PD
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
LVCMOS
DDR
PD
LVCMOS
DDR
W20
AB28
AC28
AC27
Y19
PD
LVCMOS
DDR
PD
LVCMOS
DDR
PD
LVCMOS
DDR
PD
LVCMOS
DDR
PD
LVCMOS
DDR
AB27
Y20
PD
LVCMOS
DDR
PD
LVCMOS
DDR
AA23
Y22
PD
LVCMOS
DDR
PD
LVCMOS
DDR
Y23
PD
LVCMOS
DDR
AA24
Y24
PD
LVCMOS
DDR
PD
LVCMOS
DDR
AA26
AA25
AA28
AD23
AB23
AC26
AA27
V26
PD
LVCMOS
DDR
PD
LVCMOS
DDR
PD
LVCMOS
DDR
ddr1_dqm0
ddr1_dqm1
ddr1_dqm2
ddr1_dqm3
ddr1_dqm_ecc
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
LVCMOS
DDR
O
LVCMOS
DDR
O
LVCMOS
DDR
O
LVCMOS
DDR
O
LVCMOS
DDR
16
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
AH25
AE27
AD27
Y28
ddr1_dqs0
ddr1_dqs0
ddr1_dqs1
ddr1_dqs2
ddr1_dqs3
0
IO
PD
PD
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
LVCMOS
DDR
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
ddr1_dqs1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
PD
PD
PD
PU
PU
PU
PU
PU
PD
PD
PD
PD
PD
PD
PD
PD
PD
PU
PD
PD
PU
PD
PD
LVCMOS
DDR
ddr1_dqs2
PD
LVCMOS
DDR
ddr1_dqs3
PD
LVCMOS
DDR
AG25
AE28
AD28
Y27
ddr1_dqsn0
ddr1_dqsn1
ddr1_dqsn2
ddr1_dqsn3
ddr1_dqsn_ecc
ddr1_dqs_ecc
ddr1_ecc_d0
ddr1_ecc_d1
ddr1_ecc_d2
ddr1_ecc_d3
ddr1_ecc_d4
ddr1_ecc_d5
ddr1_ecc_d6
ddr1_ecc_d7
ddr1_nck
ddr1_dqsn0
ddr1_dqsn1
ddr1_dqsn2
ddr1_dqsn3
ddr1_dqsn_ecc
ddr1_dqs_ecc
ddr1_ecc_d0
ddr1_ecc_d1
ddr1_ecc_d2
ddr1_ecc_d3
ddr1_ecc_d4
ddr1_ecc_d5
ddr1_ecc_d6
ddr1_ecc_d7
ddr1_nck
PU
LVCMOS
DDR
PU
LVCMOS
DDR
PU
LVCMOS
DDR
PU
LVCMOS
DDR
V28
PU
LVCMOS
DDR
V27
PD
LVCMOS
DDR
W22
V23
PD
No
LVCMOS
DDR
PD
No
No
No
No
No
No
No
No
No
No
No
No
LVCMOS
DDR
W19
W23
Y25
PD
LVCMOS
DDR
PD
LVCMOS
DDR
PD
LVCMOS
DDR
V24
PD
LVCMOS
DDR
V25
PD
LVCMOS
DDR
Y26
PD
LVCMOS
DDR
AH24
AE20
AC17
AF20
AG21
drive 1 (OFF)
drive 0 (OFF)
drive 0 (OFF)
drive 1 (OFF)
drive 0 (OFF)
LVCMOS
DDR
ddr1_odt0
ddr1_odt0
O
LVCMOS
DDR
ddr1_odt1
ddr1_odt1
O
LVCMOS
DDR
ddr1_rasn
ddr1_rasn
O
LVCMOS
DDR
ddr1_rst
ddr1_rst
O
LVCMOS
DDR
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
17
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
BALL NAME [2]
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
Y18
ddr1_vref0
ddr1_wen
emu0
ddr1_vref0
ddr1_wen
0
PWR
OFF
drive 1 (OFF)
drive 1 (OFF)
PU
1.35/1.5
1.35/1.5
1.8/3.3
vdds_ddr1
vdds_ddr1
vddshv3
No
LVCMOS
DDR
AH21
G21
0
O
PU
PU
No
LVCMOS
DDR
PUx/PDy
emu0
0
IO
IO
IO
IO
IO
O
IO
IO
I
0
Yes
Dual Voltage PU/PD
LVCMOS
gpio8_30
emu1
14
0
D24
AC5
emu1
PU
PU
PU
PU
0
1.8/3.3
1.8/3.3
vddshv3
vddshv7
Yes
Yes
Dual Voltage PU/PD
LVCMOS
gpio8_31
gpio6_10
mdio_mclk
i2c3_sda
14
0
gpio6_10
15
Dual Voltage PU/PD
LVCMOS
1
1
1
0
2
usb3_ulpi_d7
vin2b_hsync1
vin1a_clk0
ehrpwm2A
gpio6_10
3
4
9
I
0
10
14
15
0
O
IO
I
Driver off
AB4
gpio6_11
gpio6_11
IO
IO
IO
IO
I
PU
PU
15
1.8/3.3
vddshv7
Yes
Dual Voltage PU/PD
LVCMOS
mdio_d
1
1
1
0
i2c3_scl
2
usb3_ulpi_d6
vin2b_vsync1
vin1a_de0
ehrpwm2B
gpio6_11
3
4
9
I
0
10
14
15
0
O
IO
I
Driver off
E21
gpio6_14
gpio6_14
IO
IO
IO
I
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
mcasp1_axr8
dcan2_tx
1
0
1
1
2
uart10_rxd
vout2_hsync
3
6
O
I
vin2a_hsync0
vin1a_hsync0
8
i2c3_sda
timer1
9
IO
IO
IO
I
1
10
14
15
gpio6_14
Driver off
18
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
F20
gpio6_15
gpio6_15
0
IO
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
mcasp1_axr9
dcan2_rx
1
2
3
6
8
IO
IO
O
O
I
0
1
uart10_txd
vout2_vsync
vin2a_vsync0
vin1a_vsync0
i2c3_scl
9
IO
IO
IO
I
1
0
timer2
10
14
15
0
gpio6_15
Driver off
gpio6_16
mcasp1_axr10
vout2_fld
F21
gpio6_16
IO
IO
O
I
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
1
6
vin2a_fld0
vin1a_fld0
8
clkout1
9
O
IO
IO
I
timer3
10
14
15
0
gpio6_16
Driver off
gpmc_a0
vin1a_d16
vout3_d16
R6
gpmc_a0
O
I
PD
PD
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
2
0
3
O
I
vin2a_d0
vin1a_d0
4
vin1b_d0
i2c4_scl
uart5_rxd
6
I
0
1
1
7
IO
I
8
gpio7_3
14
IO
gpmc_a26
gpmc_a16
Driver off
15
I
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
19
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
BALL NAME [2]
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
T9
T6
T7
gpmc_a1
gpmc_a2
gpmc_a3
gpmc_a1
vin1a_d17
vout3_d17
0
O
I
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv10
vddshv10
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
2
3
4
0
O
I
vin2a_d1
vin1a_d1
vin1b_d1
i2c4_sda
uart5_txd
gpio7_4
6
I
0
1
7
IO
O
IO
I
8
14
15
0
Driver off
gpmc_a2
vin1a_d18
vout3_d18
O
I
PD
Yes
Dual Voltage PU/PD
LVCMOS
2
0
3
O
I
vin2a_d2
vin1a_d2
4
vin1b_d2
uart7_rxd
uart5_ctsn
gpio7_5
6
I
0
1
1
7
I
8
I
14
15
0
IO
I
Driver off
gpmc_a3
qspi1_cs2
vin1a_d19
vout3_d19
O
O
I
PD
Yes
Dual Voltage PU/PD
LVCMOS
1
1
0
2
3
O
I
vin2a_d3
vin1a_d3
4
vin1b_d3
uart7_txd
uart5_rtsn
gpio7_6
6
I
0
7
O
O
IO
I
8
14
15
Driver off
20
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
P6
gpmc_a4
gpmc_a4
qspi1_cs3
vin1a_d20
vout3_d20
0
O
O
I
PD
PD
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
1
2
3
4
1
0
O
I
vin2a_d4
vin1a_d4
vin1b_d4
i2c5_scl
6
I
0
1
1
7
IO
I
uart6_rxd
gpio1_26
Driver off
gpmc_a5
vin1a_d21
vout3_d21
8
14
15
0
IO
I
R9
gpmc_a5
O
I
PD
PD
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
2
0
3
O
I
vin2a_d5
vin1a_d5
4
vin1b_d5
i2c5_sda
uart6_txd
gpio1_27
Driver off
gpmc_a6
vin1a_d22
vout3_d22
6
I
0
1
7
IO
O
IO
I
8
14
15
0
R5
gpmc_a6
O
I
PD
PD
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
2
0
3
O
I
vin2a_d6
vin1a_d6
4
vin1b_d6
uart8_rxd
uart6_ctsn
gpio1_28
Driver off
6
I
0
1
1
7
I
8
I
14
15
IO
I
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
21
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
BALL NAME [2]
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
P5
gpmc_a7
gpmc_a7
vin1a_d23
vout3_d23
0
O
I
PD
PD
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
2
3
4
0
0
O
I
vin2a_d7
vin1a_d7
vin1b_d7
uart8_txd
uart6_rtsn
gpio1_29
Driver off
gpmc_a8
6
I
7
O
O
8
14
15
0
IO
I
N7
R4
N9
gpmc_a8
gpmc_a9
gpmc_a10
O
I
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv10
vddshv10
vddshv10
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
vin1a_hsync0
vout3_hsync
vin1b_hsync1
timer12
2
0
0
0
3
O
I
6
7
IO
IO
IO
I
spi4_sclk
gpio1_30
Driver off
gpmc_a9
vin1a_vsync0
vout3_vsync
vin1b_vsync1
timer11
8
14
15
0
O
I
Dual Voltage PU/PD
LVCMOS
2
0
0
0
3
O
I
6
7
IO
IO
IO
I
spi4_d1
8
gpio1_31
Driver off
gpmc_a10
vin1a_de0
vout3_de
vin1b_clk1
timer10
14
15
0
O
I
Dual Voltage PU/PD
LVCMOS
2
0
0
0
3
O
I
6
7
IO
IO
IO
I
spi4_d0
8
gpio2_0
14
15
Driver off
22
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
P9
gpmc_a11
gpmc_a11
vin1a_fld0
vout3_fld
0
O
I
PD
PD
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
2
3
4
0
O
I
vin2a_fld0
vin1a_fld0
vin1b_de1
timer9
6
I
0
1
7
IO
IO
IO
I
spi4_cs0
gpio2_1
8
14
15
0
Driver off
gpmc_a12
P4
gpmc_a12
O
I
PD
PD
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
vin2a_clk0
vin1a_clk0
4
gpmc_a0
vin1b_fld1
timer8
5
O
I
6
0
7
IO
IO
I
spi4_cs1
dma_evt1
gpio2_2
8
1
0
9
14
15
0
IO
I
Driver off
gpmc_a13
qspi1_rtclk
R3
gpmc_a13
O
I
PD
PD
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
1
0
vin2a_hsync0
vin1a_hsync0
4
I
timer7
7
IO
IO
I
spi4_cs2
dma_evt2
gpio2_3
8
1
0
9
14
15
0
IO
I
Driver off
gpmc_a14
qspi1_d3
T2
gpmc_a14
O
IO
I
PD
PD
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
1
0
1
vin2a_vsync0
vin1a_vsync0
4
timer6
7
IO
IO
IO
I
spi4_cs3
gpio2_4
Driver off
8
14
15
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
23
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
BALL NAME [2]
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
U2
gpmc_a15
gpmc_a15
qspi1_d2
0
O
PD
PD
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
1
4
IO
I
0
vin2a_d8
vin1a_d8
timer5
7
IO
IO
I
gpio2_5
Driver off
gpmc_a16
qspi1_d0
14
15
0
U1
P3
R2
gpmc_a16
gpmc_a17
gpmc_a18
gpmc_a19
O
IO
I
PD
PD
PD
PD
PD
PD
PD
PD
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv10
vddshv10
vddshv10
vddshv11
Yes
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
1
0
vin2a_d9
vin1a_d9
4
gpio2_6
14
15
0
IO
I
Driver off
gpmc_a17
qspi1_d1
O
IO
I
Dual Voltage PU/PD
LVCMOS
1
0
vin2a_d10
vin1a_d10
4
gpio2_7
14
15
0
IO
I
Driver off
gpmc_a18
qspi1_sclk
O
IO
I
Dual Voltage PU/PD
LVCMOS
1
vin2a_d11
vin1a_d11
4
gpio2_8
14
15
0
IO
I
Driver off
gpmc_a19
K7(9)
O
IO
O
I
Dual Voltage PU/PD
LVCMOS
mmc2_dat4
gpmc_a13
1
1
2
vin2a_d12
vin1a_d12
4
vin2b_d0
vin1b_d0
6
I
gpio2_9
14
15
IO
I
Driver off
24
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
M7(9)
gpmc_a20
gpmc_a20
0
O
PD
PD
PD
PD
PD
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv11
vddshv11
vddshv11
vddshv11
Yes
Dual Voltage PU/PD
LVCMOS
mmc2_dat5
gpmc_a14
1
2
4
IO
O
I
1
1
1
1
vin2a_d13
vin1a_d13
vin2b_d1
vin1b_d1
6
I
gpio2_10
14
15
0
IO
I
Driver off
J5(9)
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a21
mmc2_dat6
gpmc_a15
O
IO
O
I
PD
PD
PD
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
1
2
vin2a_d14
vin1a_d14
4
vin2b_d2
vin1b_d2
6
I
gpio2_11
14
15
0
IO
I
Driver off
K6(9)
gpmc_a22
mmc2_dat7
gpmc_a16
O
IO
O
I
Dual Voltage PU/PD
LVCMOS
1
2
vin2a_d15
vin1a_d15
4
vin2b_d3
vin1b_d3
6
I
gpio2_12
Driver off
gpmc_a23
mmc2_clk
gpmc_a17
14
15
0
IO
I
J7
O
IO
O
I
Dual Voltage PU/PD
LVCMOS
1
2
vin2a_fld0
vin1a_fld0
4
vin2b_d4
vin1b_d4
6
I
gpio2_13
Driver off
14
15
IO
I
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
25
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
BALL NAME [2]
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
(9)
gpmc_a24
gpmc_a25
gpmc_a26
gpmc_a27
gpmc_a24
mmc2_dat0
0
O
PD
PD
PD
PD
PD
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv11
vddshv11
vddshv11
vddshv11
Yes
Dual Voltage PU/PD
LVCMOS
J4
1
2
6
IO
O
I
1
1
1
1
gpmc_a18
vin2b_d5
vin1b_d5
gpio2_14
14
15
0
IO
I
Driver off
(9)
gpmc_a25
mmc2_dat1
gpmc_a19
O
IO
O
I
PD
PD
PD
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
J6
1
2
vin2b_d6
vin1b_d6
6
gpio2_15
14
15
0
IO
I
Driver off
(9)
gpmc_a26
mmc2_dat2
gpmc_a20
O
IO
O
I
Dual Voltage PU/PD
LVCMOS
H4
1
2
vin2b_d7
vin1b_d7
6
gpio2_16
14
15
0
IO
I
Driver off
(9)
gpmc_a27
mmc2_dat3
gpmc_a21
O
IO
O
I
Dual Voltage PU/PD
LVCMOS
H5
1
2
vin2b_hsync1
vin1b_hsync1
6
gpio2_17
Driver off
gpmc_ad0
vin1a_d0
vout3_d0
gpio1_6
14
15
0
IO
I
M6
M2
gpmc_ad0
gpmc_ad1
IO
I
OFF
OFF
OFF
OFF
15
15
1.8/3.3
1.8/3.3
vddshv10
vddshv10
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
0
2
3
O
IO
I
14
15
0
sysboot0
gpmc_ad1
vin1a_d1
vout3_d1
gpio1_7
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
2
3
O
IO
I
14
15
sysboot1
26
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
L5
M1
L6
L4
L3
L2
L1
gpmc_ad2
gpmc_ad2
vin1a_d2
vout3_d2
gpio1_8
0
IO
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
15
15
15
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv10
vddshv10
vddshv10
vddshv10
vddshv10
vddshv10
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
0
0
2
I
3
O
IO
I
14
15
0
sysboot2
gpmc_ad3
vin1a_d3
vout3_d3
gpio1_9
gpmc_ad3
gpmc_ad4
gpmc_ad5
gpmc_ad6
gpmc_ad7
gpmc_ad8
IO
I
OFF
OFF
OFF
OFF
OFF
OFF
Yes
Yes
Yes
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
0
2
3
O
IO
I
14
15
0
sysboot3
gpmc_ad4
vin1a_d4
vout3_d4
gpio1_10
sysboot4
gpmc_ad5
vin1a_d5
vout3_d5
gpio1_11
sysboot5
gpmc_ad6
vin1a_d6
vout3_d6
gpio1_12
sysboot6
gpmc_ad7
vin1a_d7
vout3_d7
gpio1_13
sysboot7
gpmc_ad8
vin1a_d8
vout3_d8
gpio7_18
sysboot8
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
2
3
O
IO
I
14
15
0
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
2
3
O
IO
I
14
15
0
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
2
3
O
IO
I
14
15
0
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
2
3
O
IO
I
14
15
0
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
2
3
O
IO
I
14
15
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
27
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
BALL NAME [2]
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
K2
gpmc_ad9
gpmc_ad9
vin1a_d9
vout3_d9
gpio7_19
sysboot9
0
IO
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
15
15
15
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv10
vddshv10
vddshv10
vddshv10
vddshv10
vddshv10
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
0
0
2
I
3
O
IO
I
14
15
0
J1
gpmc_ad10
gpmc_ad11
gpmc_ad12
gpmc_ad13
gpmc_ad14
gpmc_ad15
gpmc_ad10
vin1a_d10
vout3_d10
gpio7_28
IO
I
OFF
OFF
OFF
OFF
OFF
OFF
Yes
Yes
Yes
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
0
2
3
O
IO
I
14
15
0
sysboot10
gpmc_ad11
vin1a_d11
vout3_d11
gpio7_29
J2
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
2
3
O
IO
I
14
15
0
sysboot11
gpmc_ad12
vin1a_d12
vout3_d12
gpio1_18
H1
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
2
3
O
IO
I
14
15
0
sysboot12
gpmc_ad13
vin1a_d13
vout3_d13
gpio1_19
J3
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
2
3
O
IO
I
14
15
0
sysboot13
gpmc_ad14
vin1a_d14
vout3_d14
gpio1_20
H2
H3
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
2
3
O
IO
I
14
15
0
sysboot14
gpmc_ad15
vin1a_d15
vout3_d15
gpio1_21
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
2
3
O
IO
I
14
15
sysboot15
28
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
N1
gpmc_advn_ale
gpmc_advn_ale
0
O
O
O
I
PU
PU
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
gpmc_cs6
clkout2
1
2
3
4
gpmc_wait1
1
vin2a_vsync0
vin1a_vsync0
I
gpmc_a2
gpmc_a23
timer3
5
O
O
6
7
IO
IO
I
i2c3_sda
dma_evt2
8
1
0
9
gpio2_23
14
IO
gpmc_a19
Driver off
15
0
I
N6
gpmc_ben0
gpmc_ben0
gpmc_cs4
O
O
I
PU
PU
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
1
vin2b_de1
vin1b_de1
6
timer2
7
IO
I
dma_evt3
9
0
gpio2_26
14
IO
gpmc_a21
Driver off
15
0
I
M4
gpmc_ben1
gpmc_ben1
gpmc_cs5
O
O
I
PU
PU
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
1
vin2b_clk1
vin1b_clk1
4
gpmc_a3
5
6
O
I
vin2b_fld1
vin1b_fld1
timer1
7
IO
I
dma_evt4
9
0
gpio2_27
14
IO
gpmc_a22
Driver off
15
I
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
29
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
BALL NAME [2]
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
P7
gpmc_clk
gpmc_clk
gpmc_cs7
clkout1
0
IO
PU
PU
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
0
1
1
2
3
4
O
O
I
gpmc_wait1
vin2a_hsync0
vin1a_hsync0
I
vin2a_de0
vin1a_de0
5
6
I
I
vin2b_clk1
vin1b_clk1
timer4
7
IO
IO
I
i2c3_scl
dma_evt1
8
1
0
9
gpio2_22
14
IO
gpmc_a20
Driver off
gpmc_cs0
gpio2_19
Driver off
gpmc_cs1
mmc2_cmd
gpmc_a22
15
0
I
T1
H6
gpmc_cs0
gpmc_cs1
O
IO
I
PU
PU
PU
PU
15
15
1.8/3.3
1.8/3.3
vddshv10
vddshv11
Yes
Yes
Dual Voltage PU/PD
LVCMOS
14
15
0
O
IO
O
I
Dual Voltage PU/PD
LVCMOS
1
1
2
vin2a_de0
vin1a_de0
4
vin2b_vsync1
vin1b_vsync1
6
I
gpio2_18
Driver off
gpmc_cs2
qspi1_cs0
14
15
0
IO
I
P2
gpmc_cs2
O
IO
IO
PU
PU
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
1
1
gpio2_20
gpmc_a23
gpmc_a13
14
Driver off
15
I
30
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
P1
gpmc_cs3
gpmc_cs3
qspi1_cs1
vin1a_clk0
vout3_clk
gpmc_a1
0
O
O
I
PU
PU
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
1
1
0
2
3
O
O
5
gpio2_21
gpmc_a24
gpmc_a14
14
IO
Driver off
15
0
I
M5
N2
gpmc_oen_ren
gpmc_wait0
gpmc_oen_ren
gpio2_24
O
IO
I
PU
PU
PU
PU
15
15
1.8/3.3
1.8/3.3
vddshv10
vddshv10
Yes
Yes
Dual Voltage PU/PD
LVCMOS
14
15
0
Driver off
gpmc_wait0
I
Dual Voltage PU/PD
LVCMOS
1
gpio2_28
gpmc_a25
gpmc_a15
14
IO
Driver off
15
0
I
M3
gpmc_wen
gpmc_wen
gpio2_25
O
IO
I
PU
PU
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
14
15
0
Driver off
AG16
AH16
AG17
AH17
AG18
AH18
AG19
AH19
C20
hdmi1_clockx
hdmi1_clocky
hdmi1_data0x
hdmi1_data0y
hdmi1_data1x
hdmi1_data1y
hdmi1_data2x
hdmi1_data2y
i2c1_scl
hdmi1_clockx
hdmi1_clocky
hdmi1_data0x
hdmi1_data0y
hdmi1_data1x
hdmi1_data1y
hdmi1_data2x
hdmi1_data2y
i2c1_scl
O
O
O
O
O
O
O
O
IO
I
1.8
vdda_hdmi
vdda_hdmi
vdda_hdmi
vdda_hdmi
vdda_hdmi
vdda_hdmi
vdda_hdmi
vdda_hdmi
vddshv3
HDMIPHY
HDMIPHY
HDMIPHY
HDMIPHY
HDMIPHY
HDMIPHY
HDMIPHY
HDMIPHY
Pdy
Pdy
Pdy
Pdy
Pdy
Pdy
Pdy
Pdy
0
1.8
0
1.8
0
1.8
0
1.8
0
1.8
0
1.8
0
1.8
0
1.8/3.3
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS I2C
Driver off
15
0
C21
F17
i2c1_sda
i2c2_scl
i2c1_sda
IO
I
1.8/3.3
1.8/3.3
vddshv3
vddshv3
Dual Voltage PU/PD
LVCMOS I2C
Driver off
15
0
i2c2_scl
IO
IO
I
15
15
Dual Voltage PU/PD
LVCMOS I2C
1
1
hdmi1_ddc_sda
Driver off
1
15
0
C25
i2c2_sda
ljcb_clkn
i2c2_sda
IO
IO
I
1.8/3.3
1.8
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS I2C
hdmi1_ddc_scl
Driver off
1
15
0
AH15
ljcb_clkn
IO
vdda_pcie
LJCB
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
31
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
BALL NAME [2]
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
AG15
B14
ljcb_clkp
ljcb_clkp
0
IO
1.8
vdda_pcie
vddshv3
LJCB
mcasp1_aclkr
mcasp1_aclkr
mcasp7_axr2
vout2_d0
0
1
6
8
IO
IO
O
I
PD
PD
15
1.8/3.3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
vin2a_d0
vin1a_d0
i2c4_sda
10
14
15
0
IO
IO
I
1
gpio5_0
Driver off
C14
G12
mcasp1_aclkx
mcasp1_axr0
mcasp1_aclkx
vin1a_fld0
i2c3_sda
IO
I
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv3
vddshv3
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
7
10
14
15
0
IO
IO
I
gpio7_31
Driver off
mcasp1_axr0
uart6_rxd
vin1a_vsync0
i2c5_sda
IO
I
Dual Voltage PU/PD
LVCMOS
0
1
0
1
3
7
I
10
14
15
0
IO
IO
I
gpio5_2
Driver off
F12
mcasp1_axr1
mcasp1_axr1
uart6_txd
IO
O
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
3
vin1a_hsync0
i2c5_scl
7
0
1
10
14
15
0
IO
IO
I
gpio5_3
Driver off
G13
mcasp1_axr2
mcasp1_axr2
mcasp6_axr2
uart6_ctsn
vout2_d2
IO
IO
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
1
3
6
O
I
vin2a_d2
vin1a_d2
8
gpio5_4
14
15
IO
I
Driver off
32
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
J11
mcasp1_axr3
mcasp1_axr3
0
IO
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
mcasp6_axr3
uart6_rtsn
vout2_d3
1
3
6
8
IO
O
O
I
vin2a_d3
vin1a_d3
gpio5_5
14
15
0
IO
I
Driver off
E12
F13
C12
D12
mcasp1_axr4
mcasp1_axr5
mcasp1_axr6
mcasp1_axr7
mcasp1_axr4
mcasp4_axr2
vout2_d4
IO
IO
O
I
PD
PD
PD
PD
PD
PD
PD
PD
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv3
vddshv3
vddshv3
vddshv3
Yes
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
6
vin2a_d4
vin1a_d4
8
gpio5_6
14
15
0
IO
I
Driver off
mcasp1_axr5
mcasp4_axr3
vout2_d5
IO
IO
O
I
Dual Voltage PU/PD
LVCMOS
0
0
1
6
vin2a_d5
vin1a_d5
8
gpio5_7
14
15
0
IO
I
Driver off
mcasp1_axr6
mcasp5_axr2
vout2_d6
IO
IO
O
I
Dual Voltage PU/PD
LVCMOS
0
0
1
6
vin2a_d6
vin1a_d6
8
gpio5_8
14
15
0
IO
I
Driver off
mcasp1_axr7
mcasp5_axr3
vout2_d7
IO
IO
O
I
Dual Voltage PU/PD
LVCMOS
0
0
1
6
vin2a_d7
vin1a_d7
8
timer4
10
14
15
IO
IO
I
gpio5_9
Driver off
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
33
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
BALL NAME [2]
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
B12
A11
B13
mcasp1_axr8
mcasp1_axr9
mcasp1_axr10
mcasp1_axr8
0
IO
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv3
vddshv3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
0
mcasp6_axr0
spi3_sclk
1
IO
IO
I
3
vin1a_d15
timer5
7
10
14
15
0
IO
IO
I
gpio5_10
Driver off
mcasp1_axr9
mcasp6_axr1
spi3_d1
IO
IO
IO
I
PD
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
0
1
3
vin1a_d14
timer6
7
10
14
15
0
IO
IO
I
gpio5_11
Driver off
mcasp1_axr10
mcasp6_aclkx
mcasp6_aclkr
spi3_d0
IO
IO
IO
IO
I
PD
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
2
3
0
0
vin1a_d13
timer7
7
10
14
15
0
IO
IO
I
gpio5_12
Driver off
A12
mcasp1_axr11
mcasp1_axr11
mcasp6_fsx
mcasp6_fsr
spi3_cs0
IO
IO
IO
IO
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
2
3
1
0
vin1a_d12
timer8
7
10
14
15
0
IO
IO
I
gpio4_17
Driver off
E14
mcasp1_axr12
mcasp1_axr12
mcasp7_axr0
spi3_cs1
IO
IO
IO
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
0
1
3
vin1a_d11
timer9
7
10
14
15
IO
IO
I
gpio4_18
Driver off
34
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
A13
mcasp1_axr13
mcasp1_axr13
0
IO
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
mcasp7_axr1
vin1a_d10
timer10
1
IO
I
7
10
14
15
0
IO
IO
I
gpio6_4
Driver off
G14
mcasp1_axr14
mcasp1_axr15
mcasp1_fsr
mcasp1_axr14
mcasp7_aclkx
mcasp7_aclkr
vin1a_d9
IO
IO
IO
I
PD
PD
PD
PD
15
1.8/3.3
vddshv3
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
2
7
0
timer11
10
14
15
0
IO
IO
I
gpio6_5
Driver off
F14
mcasp1_axr15
mcasp7_fsx
mcasp7_fsr
vin1a_d8
IO
IO
IO
I
PD
15
1.8/3.3
vddshv3
Dual Voltage PU/PD
LVCMOS
0
0
1
2
7
0
timer12
10
14
15
0
IO
IO
I
gpio6_6
Driver off
J14
mcasp1_fsr
mcasp7_axr3
vout2_d1
IO
IO
O
I
PD
15
1.8/3.3
vddshv3
Dual Voltage PU/PD
LVCMOS
0
0
1
6
vin2a_d1
vin1a_d1
8
i2c4_scl
10
14
15
0
IO
IO
I
1
gpio5_1
Driver off
mcasp1_fsx
vin1a_de0
i2c3_scl
D14
mcasp1_fsx
IO
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
7
10
14
15
IO
IO
I
gpio7_30
Driver off
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
35
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
BALL NAME [2]
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
E15
mcasp2_aclkr
mcasp2_aclkr
0
IO
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
mcasp8_axr2
vout2_d8
1
6
8
IO
O
I
vin2a_d8
vin1a_d8
Driver off
15
0
I
A19
B15
mcasp2_aclkx
mcasp2_axr0
mcasp2_aclkx
vin1a_d7
IO
I
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv3
vddshv3
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
0
7
Driver off
15
0
I
mcasp2_axr0
vout2_d10
IO
O
I
Dual Voltage PU/PD
LVCMOS
0
6
vin2a_d10
vin1a_d10
8
Driver off
15
0
I
A15
C15
mcasp2_axr1
mcasp2_axr2
mcasp2_axr1
vout2_d11
IO
O
I
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv3
vddshv3
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
6
vin2a_d11
vin1a_d11
8
Driver off
15
0
I
mcasp2_axr2
mcasp3_axr2
vin1a_d5
IO
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
0
1
7
gpio6_8
14
15
0
IO
I
Driver off
A16
D15
mcasp2_axr3
mcasp2_axr4
mcasp2_axr3
mcasp3_axr3
vin1a_d4
IO
IO
I
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv3
vddshv3
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
1
7
gpio6_9
14
15
0
IO
I
Driver off
mcasp2_axr4
mcasp8_axr0
vout2_d12
IO
IO
O
I
Dual Voltage PU/PD
LVCMOS
0
0
1
6
vin2a_d12
vin1a_d12
8
gpio1_4
14
15
IO
I
Driver off
36
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
B16
mcasp2_axr5
mcasp2_axr5
0
IO
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
mcasp8_axr1
vout2_d13
1
6
8
IO
O
I
vin2a_d13
vin1a_d13
gpio6_7
14
15
0
IO
I
Driver off
B17
mcasp2_axr6
mcasp2_axr7
mcasp2_fsr
mcasp2_axr6
mcasp8_aclkx
mcasp8_aclkr
vout2_d14
IO
IO
IO
O
I
PD
PD
PD
PD
15
1.8/3.3
vddshv3
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
2
6
vin2a_d14
vin1a_d14
8
gpio2_29
14
15
0
IO
I
Driver off
A17
mcasp2_axr7
mcasp8_fsx
mcasp8_fsr
vout2_d15
IO
IO
IO
O
I
PD
15
1.8/3.3
vddshv3
Dual Voltage PU/PD
LVCMOS
0
0
1
2
6
vin2a_d15
vin1a_d15
8
gpio1_5
14
15
0
IO
I
Driver off
A20
mcasp2_fsr
mcasp8_axr3
vout2_d9
IO
IO
O
I
PD
15
1.8/3.3
vddshv3
Dual Voltage PU/PD
LVCMOS
0
0
1
6
vin2a_d9
vin1a_d9
8
Driver off
15
0
I
A18
B18
mcasp2_fsx
mcasp2_fsx
vin1a_d6
IO
I
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv3
vddshv3
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
0
7
Driver off
15
0
I
mcasp3_aclkx
mcasp3_aclkx
mcasp3_aclkr
mcasp2_axr12
uart7_rxd
IO
IO
IO
I
Dual Voltage PU/PD
LVCMOS
0
1
2
0
1
0
3
vin1a_d3
7
I
gpio5_13
14
15
IO
I
Driver off
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
37
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
BALL NAME [2]
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
B19
mcasp3_axr0
mcasp3_axr0
0
IO
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
1
0
mcasp2_axr14
uart7_ctsn
uart5_rxd
2
IO
I
3
4
I
vin1a_d1
7
I
Driver off
15
0
I
C17
mcasp3_axr1
mcasp3_axr1
mcasp2_axr15
uart7_rtsn
uart5_txd
IO
IO
O
O
I
PD
PD
PD
PD
15
1.8/3.3
vddshv3
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
0
2
3
4
vin1a_d0
7
0
0
vin1a_fld0
Driver off
9
I
15
0
I
F15
mcasp3_fsx
mcasp3_fsx
mcasp3_fsr
mcasp2_axr13
uart7_txd
IO
IO
IO
O
I
PD
15
1.8/3.3
vddshv3
Dual Voltage PU/PD
LVCMOS
0
0
0
1
2
3
vin1a_d2
7
gpio5_14
14
15
0
IO
I
Driver off
C18
mcasp4_aclkx
mcasp4_aclkx
mcasp4_aclkr
spi3_sclk
IO
IO
IO
I
PD
15
1.8/3.3
vddshv3
Dual Voltage PU/PD
LVCMOS
0
1
2
0
1
1
uart8_rxd
3
i2c4_sda
4
IO
O
I
vout2_d16
6
vin2a_d16
vin1a_d16
8
vin1a_d15
Driver off
9
I
I
0
15
38
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
G16
D17
A21
mcasp4_axr0
mcasp4_axr0
0
IO
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv3
vddshv3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
1
spi3_d0
2
3
4
6
8
IO
I
uart8_ctsn
uart4_rxd
vout2_d18
I
O
I
vin2a_d18
vin1a_d18
vin1a_d13
i2c6_scl
9
I
0
14
15
0
IO
I
Driver off
mcasp4_axr1
spi3_cs0
mcasp4_axr1
IO
IO
O
O
O
I
PD
Yes
Dual Voltage PU/PD
LVCMOS
0
1
2
uart8_rtsn
uart4_txd
vout2_d19
3
4
6
vin2a_d19
vin1a_d19
8
vin1a_d12
i2c6_sda
Driver off
mcasp4_fsx
mcasp4_fsr
spi3_d1
9
I
0
14
15
0
IO
I
mcasp4_fsx
IO
IO
IO
O
IO
O
I
PD
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
1
2
uart8_txd
i2c4_scl
3
4
vout2_d17
6
vin2a_d17
vin1a_d17
8
vin1a_d14
Driver off
9
I
I
0
15
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
39
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
BALL NAME [2]
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
AA3
mcasp5_aclkx
mcasp5_aclkx
0
IO
PD
PD
15
1.8/3.3
vddshv7
Yes
Dual Voltage PU/PD
LVCMOS
0
mcasp5_aclkr
spi4_sclk
1
2
3
4
6
8
IO
IO
I
0
1
1
uart9_rxd
i2c5_sda
IO
O
I
vout2_d20
vin2a_d20
vin1a_d20
vin1a_d11
Driver off
9
I
0
15
0
I
AB3
AA4
AB9
mcasp5_axr0
mcasp5_axr1
mcasp5_fsx
mcasp5_axr0
spi4_d0
IO
IO
I
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv7
vddshv7
vddshv7
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
1
2
uart9_ctsn
uart3_rxd
vout2_d22
3
4
I
6
O
I
vin2a_d22
vin1a_d22
8
vin1a_d9
9
I
0
Driver off
15
0
I
mcasp5_axr1
spi4_cs0
IO
IO
O
O
O
I
Dual Voltage PU/PD
LVCMOS
0
1
2
uart9_rtsn
uart3_txd
vout2_d23
3
4
6
vin2a_d23
vin1a_d23
8
vin1a_d8
Driver off
mcasp5_fsx
mcasp5_fsr
spi4_d1
9
I
0
0
0
1
15
0
I
IO
IO
IO
O
IO
O
I
Dual Voltage PU/PD
LVCMOS
1
2
uart9_txd
i2c5_scl
3
4
vout2_d21
6
vin2a_d21
vin1a_d21
8
vin1a_d10
Driver off
9
I
I
0
15
40
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
U4
mdio_d
mdio_d
0
IO
PU
PU
15
1.8/3.3
vddshv9
Yes
Dual Voltage PU/PD
LVCMOS
1
1
0
0
0
uart3_ctsn
mii0_txer
vin2a_d0
vin1b_d0
gpio5_16
Driver off
mdio_mclk
uart3_rtsn
mii0_col
1
I
3
O
I
4
5
I
14
15
0
IO
I
V1
mdio_mclk
O
O
I
PU
PU
15
1.8/3.3
vddshv9
Yes
Dual Voltage PU/PD
LVCMOS
1
0
0
1
3
vin2a_clk0
vin1b_clk1
gpio5_15
Driver off
mmc1_clk
gpio6_21
Driver off
4
I
5
I
14
15
0
IO
I
W6
Y6
mmc1_clk
IO
IO
I
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
15
15
15
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv8
vddshv8
vddshv8
vddshv8
vddshv8
vddshv8
vddshv8
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SDIO2KV183 Pux/PDy
3
1
1
1
1
1
1
14
15
0
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
mmc1_sdcd
mmc1_cmd
gpio6_22
Driver off
mmc1_dat0
gpio6_23
Driver off
mmc1_dat1
gpio6_24
Driver off
mmc1_dat2
gpio6_25
Driver off
mmc1_dat3
gpio6_26
Driver off
mmc1_sdcd
uart6_rxd
i2c4_sda
IO
IO
I
SDIO2KV183 Pux/PDy
3
14
15
0
AA6
Y4
IO
IO
I
SDIO2KV183 Pux/PDy
3
14
15
0
IO
IO
I
SDIO2KV183 Pux/PDy
3
14
15
0
AA5
Y3
IO
IO
I
SDIO2KV183 Pux/PDy
3
14
15
0
IO
IO
I
SDIO2KV183 Pux/PDy
3
14
15
0
W7
I
Dual Voltage PU/PD
LVCMOS
1
1
1
3
I
4
IO
IO
I
gpio6_27
Driver off
14
15
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
41
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
BALL NAME [2]
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
Y9
mmc1_sdwp
mmc1_sdwp
0
I
PD
PD
15
1.8/3.3
vddshv8
Yes
Dual Voltage PU/PD
LVCMOS
0
1
uart6_txd
3
O
i2c4_scl
4
IO
IO
I
gpio6_28
14
15
0
Driver off
AD4
mmc3_clk
mmc3_clk
usb3_ulpi_d5
vin2b_d7
IO
IO
I
PU
PU
15
1.8/3.3
vddshv7
Yes
Dual Voltage PU/PD
LVCMOS
1
0
0
0
0
3
4
vin1a_d7
9
I
ehrpwm2_tripzone_input
gpio6_29
10
14
15
0
IO
IO
I
Driver off
AC4
mmc3_cmd
mmc3_cmd
spi3_sclk
IO
IO
IO
I
PU
PU
15
1.8/3.3
vddshv7
Yes
Dual Voltage PU/PD
LVCMOS
1
0
0
0
0
0
1
usb3_ulpi_d4
vin2b_d6
3
4
vin1a_d6
9
I
eCAP2_in_PWM2_out
gpio6_30
10
14
15
0
IO
IO
I
Driver off
AC7
mmc3_dat0
mmc3_dat0
spi3_d1
IO
IO
I
PU
PU
15
1.8/3.3
vddshv7
Yes
Dual Voltage PU/PD
LVCMOS
1
0
1
0
0
0
0
1
uart5_rxd
2
usb3_ulpi_d3
vin2b_d5
3
IO
I
4
vin1a_d5
9
I
eQEP3A_in
gpio6_31
10
14
15
0
I
IO
I
Driver off
AC6
mmc3_dat1
mmc3_dat1
spi3_d0
IO
IO
O
IO
I
PU
PU
15
1.8/3.3
vddshv7
Yes
Dual Voltage PU/PD
LVCMOS
1
0
1
uart5_txd
2
usb3_ulpi_d2
vin2b_d4
3
0
0
0
0
4
vin1a_d4
9
I
eQEP3B_in
gpio7_0
10
14
15
I
IO
I
Driver off
42
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
AC9
AC3
AC8
AD6
mmc3_dat2
mmc3_dat2
0
IO
PU
PU
PU
PU
PU
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv7
vddshv7
vddshv7
vddshv7
Yes
Dual Voltage PU/PD
LVCMOS
1
1
1
0
0
0
0
spi3_cs0
1
IO
I
uart5_ctsn
usb3_ulpi_d1
vin2b_d3
2
3
IO
I
4
vin1a_d3
9
I
eQEP3_index
gpio7_1
10
14
15
0
IO
IO
I
Driver off
mmc3_dat3
mmc3_dat4
mmc3_dat5
mmc3_dat3
spi3_cs1
IO
IO
O
IO
I
PU
PU
PU
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
1
1
1
uart5_rtsn
usb3_ulpi_d0
vin2b_d2
2
3
0
0
0
0
4
vin1a_d2
9
I
eQEP3_strobe
gpio7_2
10
14
15
0
IO
IO
I
Driver off
mmc3_dat4
spi4_sclk
IO
IO
I
Dual Voltage PU/PD
LVCMOS
1
0
1
0
0
0
1
uart10_rxd
usb3_ulpi_nxt
vin2b_d1
2
3
I
4
I
vin1a_d1
9
I
ehrpwm3A
gpio1_22
10
14
15
0
O
IO
I
Driver off
mmc3_dat5
spi4_d1
IO
IO
O
I
Dual Voltage PU/PD
LVCMOS
1
0
1
uart10_txd
usb3_ulpi_dir
vin2b_d0
2
3
0
0
0
4
I
vin1a_d0
9
I
ehrpwm3B
gpio1_23
10
14
15
O
IO
I
Driver off
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
43
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
BALL NAME [2]
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
AB8
AB5
D21
mmc3_dat6
mmc3_dat7
nmin_dsp
mmc3_dat6
0
IO
PU
PU
PU
PD
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv7
vddshv7
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
1
0
1
spi4_d0
1
IO
I
uart10_ctsn
usb3_ulpi_stp
vin2b_de1
2
3
O
I
4
vin1a_hsync0
ehrpwm3_tripzone_input
gpio1_24
9
I
0
0
10
14
15
0
IO
IO
I
Driver off
mmc3_dat7
spi4_cs0
IO
IO
O
I
PU
15
Yes
Dual Voltage PU/PD
LVCMOS
1
1
1
uart10_rtsn
usb3_ulpi_clk
vin2b_clk1
2
3
0
4
I
vin1a_vsync0
eCAP3_in_PWM3_out
gpio1_25
9
I
0
0
10
14
15
0
IO
IO
I
Driver off
nmin_dsp
I
PD
Yes
Yes
Dual Voltage PU/PD
LVCMOS
Y11
on_off
on_off
0
0
0
0
0
0
0
O
I
PU
drive 1 (OFF)
OFF
1.8/3.3
1.8
vddshv5
BC1833IHHV PU/PD
SERDES
AG13
AH13
AG14
AH14
F22
pcie_rxn0
pcie_rxp0
pcie_txn0
pcie_txp0
porz
pcie_rxn0
pcie_rxp0
pcie_txn0
pcie_txp0
porz
OFF
OFF
vdda_pcie0
vdda_pcie0
vdda_pcie0
vdda_pcie0
vddshv3
I
OFF
1.8
SERDES
O
O
I
1.8
SERDES
1.8
SERDES
1.8/3.3
1.8/3.3
Yes
Yes
IHHV1833
PU/PD
E23
resetn
resetn
I
PU
PD
PU
PD
vddshv3
Dual Voltage PU/PD
LVCMOS
U5
rgmii0_rxc
rgmii0_rxc
rmii1_txen
mii0_txclk
vin2a_d5
0
I
15
1.8/3.3
vddshv9
Yes
Dual Voltage PU/PD
LVCMOS
0
2
O
I
3
0
0
0
0
4
I
vin1b_d5
5
I
usb3_ulpi_d2
gpio5_26
Driver off
6
IO
IO
I
14
15
44
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
V5
rgmii0_rxctl
rgmii0_rxctl
0
I
PD
PD
15
1.8/3.3
vddshv9
Yes
Dual Voltage PU/PD
LVCMOS
0
rmii1_txd1
mii0_txd3
vin2a_d6
2
O
O
I
3
4
0
0
0
vin1b_d6
5
I
usb3_ulpi_d3
gpio5_27
6
IO
IO
I
14
15
0
Driver off
W2
rgmii0_rxd0
rgmii0_rxd0
rmii0_txd0
mii0_txd0
vin2a_fld0
vin1b_fld1
usb3_ulpi_d7
gpio5_31
I
PD
PD
15
1.8/3.3
vddshv9
Yes
Dual Voltage PU/PD
LVCMOS
0
1
O
O
I
3
4
5
I
0
0
6
IO
IO
I
14
15
0
Driver off
Y2
V3
V4
rgmii0_rxd1
rgmii0_rxd2
rgmii0_rxd3
rgmii0_rxd1
rmii0_txd1
mii0_txd1
vin2a_d9
I
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv9
vddshv9
vddshv9
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
1
O
O
I
3
4
0
0
usb3_ulpi_d6
gpio5_30
6
IO
IO
I
14
15
0
Driver off
rgmii0_rxd2
rmii0_txen
mii0_txen
vin2a_d8
I
Dual Voltage PU/PD
LVCMOS
0
1
O
O
I
3
4
0
0
usb3_ulpi_d5
gpio5_29
6
IO
IO
I
14
15
0
Driver off
rgmii0_rxd3
rmii1_txd0
mii0_txd2
vin2a_d7
I
Dual Voltage PU/PD
LVCMOS
0
2
O
O
I
3
4
0
0
0
vin1b_d7
5
I
usb3_ulpi_d4
gpio5_28
6
IO
IO
I
14
15
Driver off
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
45
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
BALL NAME [2]
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
W9
V9
U6
rgmii0_txc
rgmii0_txctl
rgmii0_txd0
rgmii0_txc
uart3_ctsn
rmii1_rxd1
mii0_rxd3
vin2a_d3
vin1b_d3
0
O
I
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv9
vddshv9
vddshv9
Yes
Dual Voltage PU/PD
LVCMOS
1
1
0
0
0
0
0
0
1
2
I
3
I
4
I
5
I
usb3_ulpi_clk
spi3_d0
6
I
7
IO
IO
IO
I
spi4_cs2
8
gpio5_20
Driver off
rgmii0_txctl
uart3_rtsn
rmii1_rxd0
mii0_rxd2
vin2a_d4
14
15
0
O
O
I
PD
Yes
Dual Voltage PU/PD
LVCMOS
1
2
0
0
0
0
3
I
4
I
vin1b_d4
5
I
usb3_ulpi_stp
spi3_cs0
6
O
IO
IO
IO
I
7
1
1
spi4_cs3
8
gpio5_21
Driver off
rgmii0_txd0
rmii0_rxd0
mii0_rxd0
vin2a_d10
usb3_ulpi_d1
spi4_cs0
14
15
0
O
I
PD
Yes
Dual Voltage PU/PD
LVCMOS
1
0
0
0
0
1
3
I
4
I
6
IO
IO
O
IO
I
7
uart4_rtsn
gpio5_25
Driver off
8
14
15
46
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
V6
U7
V7
U3
rgmii0_txd1
rgmii0_txd1
0
O
I
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv9
vddshv9
vddshv9
vddshv9
Yes
Dual Voltage PU/PD
LVCMOS
rmii0_rxd1
mii0_rxd1
vin2a_vsync0
vin1b_vsync1
usb3_ulpi_d0
spi4_d0
1
0
0
3
I
4
I
5
I
0
0
0
1
6
IO
IO
IO
IO
I
7
uart4_ctsn
gpio5_24
8
14
15
0
Driver off
rgmii0_txd2
rgmii0_txd2
rmii0_rxer
mii0_rxer
O
I
PD
PD
PD
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
1
0
0
3
I
vin2a_hsync0
vin1b_hsync1
usb3_ulpi_nxt
spi4_d1
4
I
5
I
0
0
0
6
I
7
IO
O
IO
I
uart4_txd
8
gpio5_23
14
15
0
Driver off
rgmii0_txd3
rgmii0_txd3
rmii0_crs
O
I
Dual Voltage PU/PD
LVCMOS
1
0
0
mii0_crs
3
I
vin2a_de0
vin1b_de1
usb3_ulpi_dir
spi4_sclk
4
I
5
I
0
0
0
1
6
I
7
IO
I
uart4_rxd
8
gpio5_22
14
15
0
IO
I
Driver off
RMII_MHZ_50_CLK
RMII_MHZ_50_CLK
vin2a_d11
gpio5_17
IO
I
15
Dual Voltage PU/PD
LVCMOS
0
0
4
14
15
0
IO
I
Driver off
F23
E18
rstoutn
rtck
rstoutn
O
PD
PU
PD
1.8/3.3
1.8/3.3
vddshv3
vddshv3
Yes
Yes
Dual Voltage PU/PD
LVCMOS
rtck
0
O
OFF
0
Dual Voltage PU/PD
LVCMOS
gpio8_29
14
IO
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
47
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
BALL NAME [2]
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
AF14
AE14
rtc_iso
rtc_iso
0
I
I
1.8/3.3
1.8
vddshv5
vdda_rtc
Yes
IHHV1833
PU/PD
rtc_osc_xi_clkin32
rtc_osc_xi_clkin32
0
No
LVCMOS
OSC
AD14
rtc_osc_xo
rtc_osc_xo
0
O
1.8
vdda_rtc
No
LVCMOS
OSC
AB17
AH9
rtc_porz
rtc_porz
0
I
1.8/3.3
1.8
vddshv5
Yes
IHHV1833
SATAPHY
SATAPHY
SATAPHY
SATAPHY
PU/PD
sata1_rxn0
sata1_rxp0
sata1_txn0
sata1_txp0
spi1_cs0
sata1_rxn0
sata1_rxp0
sata1_txn0
sata1_txp0
spi1_cs0
gpio7_10
Driver off
spi1_cs1
sata1_led
spi2_cs1
gpio7_11
Driver off
spi1_cs2
uart4_rxd
mmc3_sdcd
spi2_cs2
dcan2_tx
mdio_mclk
hdmi1_hpd
gpio7_12
Driver off
spi1_cs3
uart4_txd
mmc3_sdwp
spi2_cs3
dcan2_rx
mdio_d
0
I
OFF
OFF
OFF
vdda_sata
vdda_sata
vdda_sata
vdda_sata
vddshv3
AG9
0
I
OFF
1.8
AG10
AH10
A24
0
O
O
1.8
0
1.8
0
IO
IO
I
PU
PU
PU
15
15
1.8/3.3
Yes
Yes
Dual Voltage PU/PD
LVCMOS
1
14
15
0
A22
B21
spi1_cs1
spi1_cs2
IO
O
IO
IO
I
PU
1.8/3.3
1.8/3.3
vddshv3
vddshv3
Dual Voltage PU/PD
LVCMOS
1
1
2
3
14
15
0
IO
I
PU
PU
15
Yes
Dual Voltage PU/PD
LVCMOS
1
1
1
1
1
1
1
2
I
3
IO
IO
O
IO
IO
I
4
5
6
14
15
0
B20
spi1_cs3
IO
O
I
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
1
1
2
0
1
1
1
3
IO
IO
IO
IO
IO
I
4
5
hdmi1_cec
gpio7_13
Driver off
6
14
15
48
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
B25
F16
A25
B24
spi1_d0
spi1_d1
spi1_d0
gpio7_9
Driver off
spi1_d1
gpio7_8
Driver off
spi1_sclk
gpio7_7
Driver off
spi2_cs0
uart3_rtsn
uart5_txd
gpio7_17
Driver off
spi2_d0
uart3_ctsn
uart5_rxd
gpio7_16
Driver off
spi2_d1
uart3_txd
gpio7_15
Driver off
spi2_sclk
uart3_rxd
gpio7_14
Driver off
tclk
0
IO
PD
PD
PD
PD
PU
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv3
vddshv3
vddshv3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
1
14
15
0
IO
I
IO
IO
I
PD
PD
PU
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
14
15
0
spi1_sclk
spi2_cs0
IO
IO
I
Dual Voltage PU/PD
LVCMOS
14
15
0
IO
O
O
IO
I
Dual Voltage PU/PD
LVCMOS
1
2
14
15
0
G17
spi2_d0
IO
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
1
1
1
2
I
14
15
0
IO
I
B22
A26
spi2_d1
IO
O
IO
I
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv3
vddshv3
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
1
14
15
0
spi2_sclk
IO
I
Dual Voltage PU/PD
LVCMOS
0
1
1
14
15
0
IO
I
E20
D23
tclk
tdi
I
PU
PU
PU
PU
0
0
1.8/3.3
1.8/3.3
vddshv3
vddshv3
Yes
Yes
IQ1833
PU/PD
tdi
0
I
Dual Voltage PU/PD
LVCMOS
gpio8_27
tdo
14
0
I
F19
tdo
O
IO
I
PU
PU
0
0
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
gpio8_28
tms
14
0
F18
D20
tms
PU
PD
PU
PD
1.8/3.3
1.8/3.3
vddshv3
vddshv3
Yes
Yes
Dual Voltage PU/PD
LVCMOS
trstn
trstn
0
I
Dual Voltage PU/PD
LVCMOS
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
49
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
BALL NAME [2]
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
E25
uart1_ctsn
uart1_ctsn
uart9_rxd
mmc4_clk
gpio7_24
Driver off
uart1_rtsn
uart9_txd
0
I
I
PU
PU
15
1.8/3.3
vddshv4
Yes
Dual Voltage PU/PD
LVCMOS
1
1
1
2
3
IO
IO
I
14
15
0
C27
uart1_rtsn
O
O
IO
IO
I
PU
PU
15
1.8/3.3
vddshv4
Yes
Dual Voltage PU/PD
LVCMOS
2
mmc4_cmd
gpio7_25
Driver off
uart1_rxd
mmc4_sdcd
gpio7_22
Driver off
uart1_txd
mmc4_sdwp
gpio7_23
Driver off
uart2_ctsn
uart3_rxd
mmc4_dat2
uart10_rxd
uart1_dtrn
gpio1_16
Driver off
uart2_rtsn
uart3_txd
uart3_irtx
mmc4_dat3
uart10_txd
uart1_rin
3
1
14
15
0
B27
C26
D27
uart1_rxd
uart1_txd
uart2_ctsn
I
PU
PU
PU
PU
PU
PU
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv4
vddshv4
vddshv4
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
1
1
3
I
14
15
0
IO
I
O
I
Dual Voltage PU/PD
LVCMOS
3
0
14
15
0
IO
I
I
Dual Voltage PU/PD
LVCMOS
1
1
1
1
2
I
3
IO
I
4
5
O
IO
I
14
15
0
C28
uart2_rtsn
O
O
O
IO
O
I
PU
PU
15
1.8/3.3
vddshv4
Yes
Dual Voltage PU/PD
LVCMOS
1
2
3
1
1
4
5
gpio1_17
Driver off
14
15
IO
I
50
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
D28
D26
V2
uart2_rxd
uart2_rxd
uart3_ctsn
uart3_rctx
0
I
PU
PU
PU
PD
PD
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv4
vddshv4
vddshv9
vddshv9
Yes
Dual Voltage PU/PD
LVCMOS
1
1
1
I
2
O
mmc4_dat0
uart2_rxd
uart1_dcdn
gpio7_26
Driver off
uart2_txd
uart3_rtsn
uart3_sd
mmc4_dat1
uart2_txd
uart1_dsrn
gpio7_27
Driver off
uart3_rxd
rmii1_crs
mii0_rxdv
vin2a_d1
vin1b_d1
spi3_sclk
gpio5_18
Driver off
uart3_txd
rmii1_rxer
mii0_rxclk
vin2a_d2
vin1b_d2
spi3_d1
3
IO
I
1
1
1
4
5
I
14
15
0
IO
I
uart2_txd
uart3_rxd
uart3_txd
O
O
O
IO
O
I
PU
PD
PD
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
1
2
3
1
0
4
5
14
15
0
IO
I
I
Dual Voltage PU/PD
LVCMOS
1
0
0
0
0
0
2
I
3
I
4
I
5
I
7
IO
IO
I
14
15
0
Y1
O
I
Dual Voltage PU/PD
LVCMOS
2
0
0
0
0
0
1
3
I
4
I
5
I
7
IO
IO
IO
I
spi4_cs1
gpio5_19
Driver off
usb1_dm
8
14
15
0
AC12
AD12
usb1_dm
usb1_dp
IO
OFF
OFF
OFF
OFF
3.3
3.3
vdda33v_usb
1
USBPHY
USBPHY
usb1_dp
0
IO
vdda33v_usb
1
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
51
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
BALL NAME [2]
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
AB10
usb1_drvvbus
usb1_drvvbus
0
O
PD
PD
15
1.8/3.3
vddshv6
Yes
Dual Voltage PU/PD
LVCMOS
timer16
7
IO
IO
I
gpio6_12
Driver off
usb2_dm
14
15
0
AF11
AE11
AC10
usb2_dm
IO
3.3
vdda33v_usb No
2
USBPHY
USBPHY
usb2_dp
usb2_dp
0
IO
3.3
vdda33v_usb No
2
usb2_drvvbus
usb2_drvvbus
timer15
0
O
PD
PD
15
1.8/3.3
vddshv6
Yes
Dual Voltage PU/PD
LVCMOS
7
IO
gpio6_13
Driver off
usb_rxn0
pcie_rxn1
usb_rxp0
pcie_rxp1
usb_txn0
pcie_txn1
usb_txp0
pcie_txp1
vdd
14
15
0
IO
I
AF12
AE12
AC11
AD11
usb_rxn0
usb_rxp0
usb_txn0
usb_txp0
vdd
I
OFF
OFF
OFF
OFF
1.8
1.8
1.8
1.8
vdda_usb1
vdda_usb1
vdda_usb1
vdda_usb1
SERDES
SERDES
SERDES
SERDES
1
I
0
I
1
I
0
O
1
O
0
O
1
O
H13, H14, J17,
J18, L7, L8, N10,
N13, P11, P12,
P13, R11, R16,
R19, T13, T16,
T19, U13, U16,
U8, U9, V16, V8
PWR
AA12
Y12
vdda33v_usb1
vdda33v_usb2
vdda_core_gmac
vdda_csi
vdda33v_usb1
vdda33v_usb2
vdda_core_gmac
vdda_csi
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
P14
W12
R17
vdda_ddr
vdda_ddr
N11
vdda_debug
vdda_dsp_iva
vdda_gpu
vdda_debug
vdda_dsp_iva
vdda_gpu
N12
R14
Y17
vdda_hdmi
vdda_mpu_abe
vdda_osc
vdda_hdmi
vdda_mpu_abe
vdda_osc
N16
AD16, AE16
AA17
AA16
M14
vdda_pcie
vdda_pcie
vdda_pcie0
vdda_per
vdda_pcie0
vdda_per
52
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
P15
vdda_pll_spare
vdda_pll_spare
PWR
AB13
V13
vdda_rtc
vdda_rtc
PWR
PWR
PWR
PWR
PWR
PWR
PWR
vdda_sata
vdda_usb1
vdda_usb2
vdda_usb3
vdda_video
vdds18v
vdda_sata
vdda_usb1
vdda_usb2
vdda_usb3
vdda_video
vdds18v
AA13
AB12
W14
P16
G18, H17, M8,
M9, N8, P8, R8,
T8, V21, V22,
W17, W18
AA18, AA19, N21, vdds18v_ddr1
vdds18v_ddr1
PWR
P20, P21, W21,
Y21
E3, E5, G4, G5,
H8, H9
vddshv1
vddshv2
vddshv3
vddshv1
vddshv2
vddshv3
PWR
PWR
PWR
B6, D10, E10,
H10, H11
B23, D16, D22,
E16, E22, G15,
H15, H16, H18,
H19
C24
V12
vddshv4
vddshv5
vddshv4
vddshv5
vddshv6
PWR
PWR
PWR
AD5, AD7, AE7, vddshv6
AF5
AB6, AB7
W8, Y8
vddshv7
vddshv8
vddshv9
vddshv7
vddshv8
vddshv9
vddshv10
PWR
PWR
PWR
PWR
U10, W4, W5
N4, N5, P10, R10, vddshv10
R7, T4, T5
J8, K8
vddshv11
vdds_ddr1
vddshv11
vdds_ddr1
PWR
PWR
AA21, AA22,
AB21, AB22,
AB24, AB25,
AC22, AD26,
AG20, AG28,
AH27, T24, T25,
W16, W27
AA7, Y7
vdds_mlbp
vdd_dsp
vdds_mlbp
vdd_dsp
PWR
PWR
K10, K11, L10,
L11, M10, M11
U11, U12, V10,
V11, V14, W10,
W11, W13
vdd_gpu
vdd_gpu
PWR
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
53
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
BALL NAME [2]
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
J13, K12, K13,
L12, M12, M13
vdd_iva
vdd_iva
PWR
K17, K18, L15,
L16, L17, L18,
L19, M15, M16,
M17, M18, N17,
N18, P17, P18,
R18
vdd_mpu
vdd_mpu
PWR
AB15
E1
vdd_rtc
vdd_rtc
PWR
vin2a_clk0
vin2a_clk0
vout2_fld
emu5
0
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
4
O
O
I
5
eQEP1A_in
10
14
0
0
gpio3_28
gpmc_a27
gpmc_a17
IO
Driver off
15
0
I
F2
F3
D1
vin2a_d0
vin2a_d1
vin2a_d2
vin2a_d0
I
PD
PD
PD
PD
15
1.8/3.3
vddshv1
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
vout2_d23
emu10
4
O
O
I
5
uart9_ctsn
spi4_d0
7
1
0
8
IO
O
IO
I
ehrpwm1B
gpio4_1
10
14
15
0
Driver off
vin2a_d1
I
PD
15
1.8/3.3
vddshv1
Dual Voltage PU/PD
LVCMOS
0
vout2_d22
emu11
4
O
O
O
IO
IO
IO
I
5
uart9_rtsn
spi4_cs0
7
8
1
0
ehrpwm1_tripzone_input
gpio4_2
10
14
15
0
Driver off
vin2a_d2
I
PD
15
1.8/3.3
vddshv1
Dual Voltage PU/PD
LVCMOS
0
vout2_d21
emu12
4
O
O
I
5
uart10_rxd
eCAP1_in_PWM1_out
gpio4_3
8
1
0
10
14
15
IO
IO
I
Driver off
54
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
E2
D2
F4
C1
E4
vin2a_d3
vin2a_d3
vout2_d20
emu13
0
I
PD
PD
PD
PD
PD
PD
15
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv1
vddshv1
vddshv1
vddshv1
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
0
4
O
O
O
I
5
uart10_txd
8
ehrpwm1_synci
gpio4_4
10
14
15
0
0
0
1
IO
I
Driver off
vin2a_d4
vout2_d19
emu14
vin2a_d4
vin2a_d5
vin2a_d6
vin2a_d7
I
PD
PD
PD
PD
Yes
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
4
O
O
I
5
uart10_ctsn
ehrpwm1_synco
gpio4_5
8
10
14
15
0
O
IO
I
Driver off
vin2a_d5
vout2_d18
emu15
I
Dual Voltage PU/PD
LVCMOS
0
4
O
O
O
I
5
uart10_rtsn
eQEP2A_in
gpio4_6
8
10
14
15
0
0
0
IO
I
Driver off
vin2a_d6
vout2_d17
emu16
I
Dual Voltage PU/PD
LVCMOS
4
O
O
I
5
mii1_rxd1
eQEP2B_in
gpio4_7
8
0
0
10
14
15
0
I
IO
I
Driver off
vin2a_d7
vout2_d16
emu17
I
Dual Voltage PU/PD
LVCMOS
0
4
O
O
I
5
mii1_rxd2
eQEP2_index
gpio4_8
8
0
0
10
14
15
IO
IO
I
Driver off
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
55
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
BALL NAME [2]
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
F5
vin2a_d8
vin2a_d8
vout2_d15
emu18
0
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
0
4
O
O
I
5
mii1_rxd3
8
0
0
eQEP2_strobe
10
14
IO
IO
gpio4_9
gpmc_a26
Driver off
vin2a_d9
vout2_d14
emu19
15
0
I
E6
vin2a_d9
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
0
0
4
O
O
I
5
mii1_rxd0
ehrpwm2A
8
10
14
O
IO
gpio4_10
gpmc_a25
Driver off
15
0
I
D3
F6
D5
vin2a_d10
vin2a_d11
vin2a_d12
vin2a_d10
mdio_mclk
vout2_d13
ehrpwm2B
I
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv1
vddshv1
vddshv1
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
1
3
O
O
O
IO
4
10
14
gpio4_11
gpmc_a24
Driver off
15
0
I
vin2a_d11
I
Dual Voltage PU/PD
LVCMOS
0
1
mdio_d
3
IO
O
IO
IO
vout2_d12
4
ehrpwm2_tripzone_input
10
14
0
gpio4_12
gpmc_a23
Driver off
15
0
I
vin2a_d12
rgmii1_txc
I
Dual Voltage PU/PD
LVCMOS
0
3
O
O
I
vout2_d11
mii1_rxclk
4
8
0
0
eCAP2_in_PWM2_out
gpio4_13
10
14
15
IO
IO
I
Driver off
56
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
C2
C3
C4
B2
vin2a_d13
vin2a_d13
0
I
PD
PD
PD
PD
PD
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv1
vddshv1
vddshv1
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
0
rgmii1_txctl
vout2_d10
mii1_rxdv
eQEP3A_in
gpio4_14
3
O
O
I
4
8
0
0
10
14
15
0
I
IO
I
Driver off
vin2a_d14
vin2a_d15
vin2a_d16
vin2a_d14
rgmii1_txd3
vout2_d9
I
PD
PD
PD
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
3
O
O
I
4
mii1_txclk
eQEP3B_in
gpio4_15
8
0
0
10
14
15
0
I
IO
I
Driver off
vin2a_d15
rgmii1_txd2
vout2_d8
I
Dual Voltage PU/PD
LVCMOS
0
0
3
O
O
O
IO
IO
I
4
mii1_txd0
eQEP3_index
gpio4_16
8
10
14
15
0
Driver off
vin2a_d16
vin2b_d7
I
Dual Voltage PU/PD
LVCMOS
0
0
2
I
rgmii1_txd1
vout2_d7
3
O
O
O
IO
IO
I
4
mii1_txd1
eQEP3_strobe
gpio4_24
8
10
14
15
0
0
Driver off
D6
vin2a_d17
vin2a_d17
vin2b_d6
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
0
0
2
I
rgmii1_txd0
vout2_d6
3
O
O
O
O
IO
I
4
mii1_txd2
ehrpwm3A
gpio4_25
8
10
14
15
Driver off
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
57
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
BALL NAME [2]
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
C5
A3
B3
vin2a_d18
vin2a_d19
vin2a_d20
vin2a_d18
vin2b_d5
rgmii1_rxc
vout2_d5
mii1_txd3
ehrpwm3B
gpio4_26
Driver off
vin2a_d19
vin2b_d4
0
I
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv1
vddshv1
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
2
I
3
I
4
O
O
O
8
10
14
15
0
IO
I
I
PD
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
2
I
rgmii1_rxctl
vout2_d4
3
I
4
O
O
IO
IO
I
mii1_txer
8
0
0
ehrpwm3_tripzone_input
gpio4_27
10
14
15
0
Driver off
vin2a_d20
vin2b_d3
I
PD
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
2
I
rgmii1_rxd3
vout2_d3
3
I
4
O
I
mii1_rxer
8
0
0
eCAP3_in_PWM3_out
gpio4_28
10
14
15
0
IO
IO
I
Driver off
B4
vin2a_d21
vin2a_d21
vin2b_d2
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
2
I
rgmii1_rxd2
vout2_d2
3
I
4
O
I
mii1_col
8
0
gpio4_29
14
15
0
IO
I
Driver off
B5
vin2a_d22
vin2a_d22
vin2b_d1
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
2
I
rgmii1_rxd1
vout2_d1
3
I
4
O
I
mii1_crs
8
0
gpio4_30
14
15
IO
I
Driver off
58
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
A4
vin2a_d23
vin2a_d23
vin2b_d0
0
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
2
I
rgmii1_rxd0
vout2_d0
mii1_txen
gpio4_31
Driver off
vin2a_de0
vin2a_fld0
vin2b_fld1
vin2b_de1
vout2_de
emu6
3
I
4
O
O
8
14
15
0
IO
I
G2
vin2a_de0
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
1
I
2
I
3
I
4
O
O
I
5
eQEP1B_in
gpio3_29
Driver off
vin2a_fld0
vin2b_clk1
vout2_clk
emu7
10
14
15
0
0
IO
I
H7
vin2a_fld0
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
2
I
4
O
O
IO
IO
5
eQEP1_index
10
14
0
gpio3_30
gpmc_a27
gpmc_a18
Driver off
15
0
I
G1
vin2a_hsync0
vin2a_hsync0
vin2b_hsync1
vout2_hsync
emu8
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
3
I
4
O
O
I
5
uart9_rxd
7
1
0
0
spi4_sclk
8
IO
IO
IO
eQEP1_strobe
10
14
gpio3_31
gpmc_a27
Driver off
15
I
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
59
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
BALL NAME [2]
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
G6
vin2a_vsync0
vin2a_vsync0
0
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
vin2b_vsync1
vout2_vsync
emu9
3
I
4
O
O
O
5
uart9_txd
spi4_d1
7
8
IO
O
IO
I
0
ehrpwm1A
gpio4_0
10
14
15
0
Driver off
vout1_clk
D11
vout1_clk
O
I
PD
PD
15
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
vin2a_fld0
vin1a_fld0
3
vin1a_fld0
spi3_cs0
gpio4_19
Driver off
vout1_d0
uart5_rxd
4
I
0
1
8
IO
IO
I
14
15
0
F11
vout1_d0
O
I
PD
PD
15
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
2
1
vin2a_d16
vin1a_d16
3
I
vin1a_d16
spi3_cs2
gpio8_0
4
I
0
1
8
IO
IO
I
14
15
0
Driver off
vout1_d1
uart5_txd
G10
vout1_d1
O
O
I
PD
PD
15
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
2
vin2a_d17
vin1a_d17
3
vin1a_d17
gpio8_1
4
I
0
14
15
IO
I
Driver off
60
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
F10
vout1_d2
vout1_d2
emu2
0
O
O
I
PD
PD
15
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
2
3
vin2a_d18
vin1a_d18
vin1a_d18
obs0
4
I
0
5
O
O
O
obs16
6
obs_irq1
gpio8_2
Driver off
vout1_d3
emu5
7
14
15
0
IO
I
G11
vout1_d3
O
O
I
PD
PD
15
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
2
vin2a_d19
vin1a_d19
3
vin1a_d19
obs1
4
I
0
5
O
O
O
IO
I
obs17
6
obs_dmarq1
gpio8_3
7
14
15
0
Driver off
vout1_d4
emu6
E9
vout1_d4
O
O
I
PD
PD
15
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
2
vin2a_d20
vin1a_d20
3
vin1a_d20
obs2
4
I
0
5
O
O
IO
I
obs18
6
gpio8_4
Driver off
vout1_d5
emu7
14
15
0
F9
vout1_d5
O
O
I
PD
PD
15
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
2
vin2a_d21
vin1a_d21
3
vin1a_d21
obs3
4
I
0
5
O
O
IO
I
obs19
6
gpio8_5
Driver off
14
15
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
61
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
BALL NAME [2]
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
F8
vout1_d6
vout1_d6
emu8
0
O
O
I
PD
PD
15
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
2
3
vin2a_d22
vin1a_d22
vin1a_d22
obs4
4
I
0
5
O
O
obs20
6
gpio8_6
Driver off
vout1_d7
emu9
14
15
0
IO
I
E7
E8
D9
D7
vout1_d7
vout1_d8
vout1_d9
vout1_d10
O
O
I
PD
PD
PD
PD
PD
PD
PD
PD
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv2
vddshv2
vddshv2
vddshv2
Yes
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
2
vin2a_d23
vin1a_d23
3
vin1a_d23
gpio8_7
4
I
0
14
15
0
IO
I
Driver off
vout1_d8
uart6_rxd
O
I
Dual Voltage PU/PD
LVCMOS
2
1
0
vin2a_d8
vin1a_d8
3
I
vin1a_d8
gpio8_8
4
I
14
15
0
IO
I
Driver off
vout1_d9
uart6_txd
O
O
I
Dual Voltage PU/PD
LVCMOS
2
vin2a_d9
vin1a_d9
3
vin1a_d9
gpio8_9
Driver off
vout1_d10
emu3
4
I
0
14
15
0
IO
I
O
O
I
Dual Voltage PU/PD
LVCMOS
2
vin2a_d10
vin1a_d10
3
vin1a_d10
obs5
4
I
0
5
O
O
O
IO
I
obs21
6
obs_irq2
gpio8_10
Driver off
7
14
15
62
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
D8
vout1_d11
vout1_d11
emu10
0
O
O
I
PD
PD
15
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
2
3
vin2a_d11
vin1a_d11
vin1a_d11
obs6
4
I
0
5
O
O
O
obs22
6
obs_dmarq2
gpio8_11
Driver off
vout1_d12
emu11
7
14
15
0
IO
I
A5
C6
C8
vout1_d12
vout1_d13
vout1_d14
O
O
I
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv2
vddshv2
vddshv2
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
2
vin2a_d12
vin1a_d12
3
vin1a_d12
obs7
4
I
0
0
0
5
O
O
IO
I
obs23
6
gpio8_12
Driver off
vout1_d13
emu12
14
15
0
O
O
I
Dual Voltage PU/PD
LVCMOS
2
vin2a_d13
vin1a_d13
3
vin1a_d13
obs8
4
I
5
O
O
IO
I
obs24
6
gpio8_13
Driver off
vout1_d14
emu13
14
15
0
O
O
I
Dual Voltage PU/PD
LVCMOS
2
vin2a_d14
vin1a_d14
3
vin1a_d14
obs9
4
I
5
O
O
IO
I
obs25
6
gpio8_14
Driver off
14
15
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
63
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
BALL NAME [2]
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
C7
vout1_d15
vout1_d15
emu14
0
O
O
I
PD
PD
15
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
2
3
vin2a_d15
vin1a_d15
vin1a_d15
obs10
4
I
0
5
O
O
obs26
6
gpio8_15
Driver off
vout1_d16
uart7_rxd
14
15
0
IO
I
B7
B8
A7
vout1_d16
vout1_d17
vout1_d18
O
I
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv2
vddshv2
vddshv2
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
2
1
0
vin2a_d0
vin1a_d0
3
I
vin1a_d0
gpio8_16
Driver off
vout1_d17
uart7_txd
4
I
14
15
0
IO
I
O
O
I
Dual Voltage PU/PD
LVCMOS
2
vin2a_d1
vin1a_d1
3
vin1a_d1
gpio8_17
Driver off
vout1_d18
emu4
4
I
0
14
15
0
IO
I
O
O
I
Dual Voltage PU/PD
LVCMOS
2
vin2a_d2
vin1a_d2
3
vin1a_d2
obs11
4
I
0
5
O
O
IO
I
obs27
6
gpio8_18
Driver off
14
15
64
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表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
A8
C9
A9
B9
vout1_d19
vout1_d19
emu15
0
O
O
I
PD
PD
PD
PD
PD
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv2
vddshv2
vddshv2
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
2
3
vin2a_d3
vin1a_d3
vin1a_d3
obs12
4
I
0
0
0
0
5
O
O
obs28
6
gpio8_19
Driver off
vout1_d20
emu16
14
15
0
IO
I
vout1_d20
vout1_d21
vout1_d22
O
O
I
PD
PD
PD
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
2
vin2a_d4
vin1a_d4
3
vin1a_d4
obs13
4
I
5
O
O
IO
I
obs29
6
gpio8_20
Driver off
vout1_d21
emu17
14
15
0
O
O
I
Dual Voltage PU/PD
LVCMOS
2
vin2a_d5
vin1a_d5
3
vin1a_d5
obs14
4
I
5
O
O
IO
I
obs30
6
gpio8_21
Driver off
vout1_d22
emu18
14
15
0
O
O
I
Dual Voltage PU/PD
LVCMOS
2
vin2a_d6
vin1a_d6
3
vin1a_d6
obs15
4
I
5
O
O
IO
I
obs31
6
gpio8_22
Driver off
14
15
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表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
BALL NAME [2]
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
A10
vout1_d23
vout1_d23
emu19
0
O
O
I
PD
PD
15
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
2
3
vin2a_d7
vin1a_d7
vin1a_d7
spi3_cs3
gpio8_23
Driver off
vout1_de
4
I
0
1
8
IO
IO
I
14
15
0
B10
B11
C11
E11
vout1_de
O
I
PD
PD
PD
PD
PD
PD
PD
PD
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv2
vddshv2
vddshv2
vddshv2
Yes
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
vin2a_de0
vin1a_de0
3
vin1a_de0
spi3_d1
4
I
0
0
8
IO
IO
I
gpio4_20
Driver off
vout1_fld
14
15
0
vout1_fld
O
I
Dual Voltage PU/PD
LVCMOS
vin2a_clk0
vin1a_clk0
3
vin1a_clk0
spi3_cs1
gpio4_21
Driver off
4
I
0
1
8
IO
IO
I
14
15
0
vout1_hsync
vout1_hsync
O
I
Dual Voltage PU/PD
LVCMOS
vin2a_hsync0
vin1a_hsync0
3
vin1a_hsync0
spi3_d0
4
I
0
0
8
IO
IO
I
gpio4_22
14
15
0
Driver off
vout1_vsync
vout1_vsync
O
I
Dual Voltage PU/PD
LVCMOS
vin2a_vsync0
vin1a_vsync0
3
vin1a_vsync0
spi3_sclk
4
I
0
0
8
IO
IO
I
gpio4_23
14
15
Driver off
66
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ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
A1, A14, A2, A23, vss
A28, A6, AA14,
AA15, AA20, AA8,
AA9, AB14, AB20,
AD1, AD24, AG1,
AH1, AH2, AH20,
AH28, B1, D13,
D19, E13, E19,
F1, F7, G7, G8,
G9, H12, J12,
vss
GND
J15, J28, K1, K15,
K24, K25, K4, K5,
L13, L14, M19,
N14, N15, N19,
N24, N25, P28,
R1, R12, R13,
R21, T10, T11,
T12, T14, T15,
T17, T18, T21,
U14, U15, U17,
U20, U21, V15,
V17, W1, W15,
W24, W25, W28
AA10, AH8
AD19, AE19
AF15
vssa_csi
vssa_hdmi
vssa_csi
GND
GND
GND
GND
GND
GND
GND
GND
GND
I
vssa_hdmi
vssa_osc0
vssa_osc1
vssa_pcie
vssa_sata
vssa_usb
vssa_usb3
vssa_osc0
vssa_osc1
vssa_pcie
vssa_sata
vssa_usb
vssa_usb3
vssa_video
Wakeup0
AC14
AD13, AE13
AE10
AA11, AB11
AD10
R15
vssa_video
Wakeup0
dcan1_rx
AD17
0
15
15
1.8/3.3
1.8/3.3
vddshv5
vddshv5
Yes
IHHV1833
IHHV1833
PU/PD
PU/PD
1
I
1
gpio1_0
sys_nirq2
14
I
Driver off
Wakeup3
sys_nirq1
15
0
I
I
I
I
AC16
Wakeup3
Yes
1
gpio1_3
14
dcan2_rx
Driver off
xi_osc0
15
0
I
I
AE15
AC15
AD15
xi_osc0
xi_osc1
xo_osc0
1.8
1.8
1.8
vdda_osc
vdda_osc
vdda_osc
No
No
No
LVCMOS
Analog
xi_osc1
xo_osc0
0
0
I
LVCMOS
Analog
O
LVCMOS
Analog
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表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
BALL NAME [2]
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
AC13
D18
xo_osc1
xref_clk0
xo_osc1
xref_clk0
0
A
I
1.8
vdda_osc
vddshv3
No
LVCMOS
Analog
0
PD
PD
15
1.8/3.3
Yes
Dual Voltage PU/PD
LVCMOS
mcasp2_axr8
mcasp1_axr4
mcasp1_ahclkx
mcasp5_ahclkx
vin1a_d0
1
IO
IO
O
O
I
0
0
2
3
4
7
0
clkout2
9
O
IO
IO
I
timer13
10
14
15
0
gpio6_17
Driver off
E17
xref_clk1
xref_clk1
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
mcasp2_axr9
mcasp1_axr5
mcasp2_ahclkx
mcasp6_ahclkx
vin1a_clk0
1
IO
IO
O
O
I
0
0
2
3
4
7
0
timer14
10
14
15
0
IO
IO
I
gpio6_18
Driver off
B26
xref_clk2
xref_clk2
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
mcasp2_axr10
mcasp1_axr6
mcasp3_ahclkx
mcasp7_ahclkx
vout2_clk
1
IO
IO
O
O
O
I
0
0
2
3
4
6
vin2a_clk0
vin1a_clk0
8
timer15
10
14
15
IO
IO
I
gpio6_19
Driver off
68
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ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-2. Ball Characteristics(1) (continued)
BALL
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
BALL NUMBER
[1]
MUXMODE
[4]
RESET REL.
MUXMODE
[8]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
C23
xref_clk3
xref_clk3
0
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
mcasp2_axr11
mcasp1_axr7
mcasp4_ahclkx
mcasp8_ahclkx
vout2_de
1
2
3
4
6
8
IO
IO
O
O
O
I
0
0
vin2a_de0
vin1a_de0
clkout3
9
O
IO
IO
I
timer16
10
14
15
gpio6_20
Driver off
(1) NA in this table stands for Not Applicable.
(2) For more information on recommended operating conditions, see 表 5-4, Recommended Operating Conditions.
(3) The pullup or pulldown block strength is equal to: minimum = 50 μA, typical = 100 μA, maximum = 250 μA.
(4) The output impedance settings of this IO cell are programmable; by default, the value is DS[1:0] = 10, this means 40 Ω. For more information on DS[1:0] register configuration, see the
Device TRM.
(5) IO drive strength for usb1_dp, usb1_dm, usb2_dp and usb2_dm: minimum 18.3 mA, maximum 89 mA (for a power supply vdda33v_usb1 and vdda33v_usb2 = 3.46 V).
(6) Minimum PU = 900 Ω, maximum PU = 3.090 kΩ and minimum PD = 14.25 kΩ, maximum PD = 24.8 kΩ.
For more information, see chapter 7 of the USB2.0 specification, in particular section Signaling / Device Speed Identification.
(7) This function will not be supported on some pin-compatible roadmap devices. Pin compatibility can be maintained in the future by not using these GPIO signals.
(8) In PUx / PDy, x and y = 60 to 200 μA.
The output impedance settings (or drive strengths) of this IO are programmable (34 Ω, 40 Ω, 48 Ω, 60 Ω, 80 Ω) depending on the values of the I[2:0] registers.
(9) The internal pull resistors for balls K7, M7, J5, K6, J4, J6, H4, H5 are permanently disabled when sysboot15 is set to 0 as described in the section Sysboot Configuration of the Device
TRM. If internal pull-up/down resistors are desired on these balls then sysboot15 should be set to 1. If gpmc boot mode is used with SYSBOOT15=0 (not recommended) then external
pull-downs should be implemented to keep the address bus at logic-1 value during boot since the gpmc ms-address bits are high-z during boot.
4.3 Multiplexing Characteristics
表 4-3 describes the device multiplexing (no characteristics are available in this table).
注
This table doesn't take into account subsystem multiplexing signals. Subsystem multiplexing signals are described in 节 4.4, Signal
Descriptions.
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注
For more information, see the Control Module / Control Module Functional Description / PAD Functional Multiplexing and Configuration
section of the Device TRM.
注
Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the
proper software configuration (Hi-Z mode is not an input signal).
注
When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad’s behavior is undefined. This should be
avoided.
注
In some cases 表 4-3 may present more than one signal per muxmode for the same ball. First signal in the list is the dominant function as
selected via CTRL_CORE_PAD_* register.
All other signals are virtual functions that present alternate multiplexing options. This virtual functions are controlled via
CTRL_CORE_ALT_SELECT_MUX or CTRL_CORE_VIP_MUX_SELECT register. For more information on how to use this options,
please refer to Device TRM, Chapter Control Module, Section Pad Configuration Registers.
CAUTION
The I/O timings provided in 节 7, Timing Requirements and Switching Characteristics are valid only if signals within a
single IOSET are used. The IOSETs are defined in the corresponding tables.
注
Dual rank support is not available on this device, but signal names are retained for consistency with the TDA2xx family of devices.
表 4-3. Multiplexing Characteristics
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
ADDRESS
REGISTER NAME
NUMBER
0
1
2
3*
4*
5*
6*
7
8*
9
10
14*
15
Y23
ddr1_d26
70
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ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-3. Multiplexing Characteristics (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS
REGISTER NAME
0
1
2
3*
4*
5* 6*
7
8*
9
10
14*
15
Y19
ddr1_d21
xi_osc0
AE15
AH24
AG15
AF24
V25
ddr1_nck
ljcb_clkp
ddr1_d4
ddr1_ecc_d6
ddr1_csn1
hdmi1_data2x
ddr1_a4
AB16
AG19
AF21
AG5
csi2_1_dx0
ddr1_ecc_d3
ddr1_dqsn3
ddr1_d14
ddr1_d11
ddr1_d24
ddr1_a15
hdmi1_clocky
csi2_1_dy0
ddr1_a2
W23
Y27
AC24
AF28
AA23
AD18
AH16
AH5
AC20
AA24
W19
ddr1_d27
ddr1_ecc_d2
ddr1_rst
AG21
AE28
AC11
AG25
AC17
AG4
ddr1_dqsn1
usb_txn0
pcie_txn1
ddr1_dqsn0
ddr1_odt1
csi2_0_dy3
ddr1_d17
rtc_iso
W20
AF14
AA27
AF25
AF2
ddr1_dqm3
ddr1_d0
csi2_0_dx2
ddr1_d6
AF23
AG18
AH6
hdmi1_data1x
csi2_1_dy1
sata1_txn0
ddr1_rasn
AG10
AF20
V26
ddr1_dqm_ec
c
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表 4-3. Multiplexing Characteristics (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS
REGISTER NAME
0
1
2
3*
4*
5* 6*
7
8*
9
10
14*
15
V20
ddr1_d16
pcie_rxp0
ddr1_casn
sata1_rxp0
ddr1_csn0
usb2_dp
AH13
AC18
AG9
AH23
AE11
Y24
ddr1_d28
ljcb_clkn
AH15
AD20
AA25
AD14
AC25
AB23
AE1
ddr1_a0
ddr1_d30
rtc_osc_xo
ddr1_d13
ddr1_dqm1
csi2_0_dx0
hdmi1_data2y
ddr1_d22
pcie_txn0
ddr1_dqs3
ddr1_a3
AH19
AB27
AG14
Y28
AB19
AH10
AG24
AE24
AC15
AC21
AF12
AH9
sata1_txp0
ddr1_ck
ddr1_d5
xi_osc1
ddr1_a12
usb_rxn0
sata1_rxn0
ddr1_dqm2
ddr1_d31
ddr1_dqm0
ddr1_dqs1
ddr1_d9
pcie_rxn1
AC26
AA28
AD23
AE27
AF27
V24
ddr1_ecc_d5
ddr1_d10
ddr1_a8
AG27
AF22
AH21
AE21
AC12
Y20
ddr1_wen
ddr1_a7
usb1_dm
ddr1_d23
ddr1_d20
AC27
72
Terminal Configuration and Functions
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ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-3. Multiplexing Characteristics (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS
REGISTER NAME
0
1
2
3*
4*
5* 6*
7
8*
9
10
14*
15
AE23
ddr1_d7
AG22
AD27
AH26
AH14
AD21
Y25
ddr1_cke
ddr1_dqs2
ddr1_d3
pcie_txp0
ddr1_a10
ddr1_ecc_d4
ddr1_a14
csi2_1_dy2
hdmi1_data1y
ddr1_a5
AE17
AG7
AH18
AH22
W22
ddr1_ecc_d0
ddr1_ecc_d1
usb_rxp0
V23
AE12
AE14
pcie_rxp1
rtc_osc_xi_clki
n32
AF3
csi2_0_dy2
ddr1_a6
AG23
AG6
csi2_1_dx1
ddr1_ba2
hdmi1_data0x
ddr1_d1
AB18
AG17
AF26
AD11
V27
usb_txp0
pcie_txp1
ddr1_dqs_ecc
ddr1_ba0
ddr1_d12
ddr1_a1
AF17
AE26
AC19
AG13
AB28
Y26
pcie_rxn0
ddr1_d18
ddr1_ecc_d7
csi2_0_dx4
ddr1_a11
ddr1_dqsn2
csi2_0_dy0
ddr1_ba1
ddr1_odt0
usb2_dm
AH3
AD22
AD28
AD2
AE18
AE20
AF11
AD15
AH7
xo_osc0
csi2_1_dx2
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表 4-3. Multiplexing Characteristics (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS
REGISTER NAME
0
1
2
3*
4*
5* 6*
7
8*
9
10
14*
15
AE22
ddr1_a9
Y18
ddr1_vref0
xo_osc1
AC13
AD12
Y22
usb1_dp
ddr1_d25
hdmi1_data0y
csi2_0_dx3
csi2_0_dy1
ddr1_d2
AH17
AH4
AE2
AG26
AH25
AF18
AC28
AG3
ddr1_dqs0
ddr1_a13
ddr1_d19
csi2_0_dy4
V28
ddr1_dqsn_ec
c
AC23
F22
ddr1_d8
porz
AG16
AF1
hdmi1_clockx
csi2_0_dx1
ddr1_d29
ddr1_d15
gpmc_ad0
AA26
AD25
0x1400
0x1404
0x1408
0x140C
0x1410
0x1414
0x1418
0x141C
0x1420
0x1424
0x1428
CTRL_CORE_PAD_ M6
GPMC_AD0
vin1a_d0
vin1a_d1
vin1a_d2
vin1a_d3
vin1a_d4
vin1a_d5
vin1a_d6
vin1a_d7
vin1a_d8
vin1a_d9
vin1a_d10
vout3_d0
vout3_d1
vout3_d2
vout3_d3
vout3_d4
vout3_d5
vout3_d6
vout3_d7
vout3_d8
vout3_d9
vout3_d10
gpio1_6
sysboot0
sysboot1
sysboot2
sysboot3
sysboot4
sysboot5
sysboot6
sysboot7
sysboot8
sysboot9
sysboot10
CTRL_CORE_PAD_ M2
GPMC_AD1
gpmc_ad1
gpmc_ad2
gpmc_ad3
gpmc_ad4
gpmc_ad5
gpmc_ad6
gpmc_ad7
gpmc_ad8
gpmc_ad9
gpmc_ad10
gpio1_7
CTRL_CORE_PAD_ L5
GPMC_AD2
gpio1_8
CTRL_CORE_PAD_ M1
GPMC_AD3
gpio1_9
CTRL_CORE_PAD_ L6
GPMC_AD4
gpio1_10
gpio1_11
gpio1_12
gpio1_13
gpio7_18
gpio7_19
gpio7_28
CTRL_CORE_PAD_ L4
GPMC_AD5
CTRL_CORE_PAD_ L3
GPMC_AD6
CTRL_CORE_PAD_ L2
GPMC_AD7
CTRL_CORE_PAD_ L1
GPMC_AD8
CTRL_CORE_PAD_ K2
GPMC_AD9
CTRL_CORE_PAD_ J1
GPMC_AD10
74
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-3. Multiplexing Characteristics (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS
REGISTER NAME
0
1
2
3*
4*
5*
6*
7
8*
9
10
14*
15
0x142C
CTRL_CORE_PAD_ J2
GPMC_AD11
gpmc_ad11
vin1a_d11
vout3_d11
gpio7_29
sysboot11
0x1430
0x1434
0x1438
0x143C
0x1440
CTRL_CORE_PAD_ H1
GPMC_AD12
gpmc_ad12
gpmc_ad13
gpmc_ad14
gpmc_ad15
gpmc_a0
vin1a_d12
vin1a_d13
vin1a_d14
vin1a_d15
vin1a_d16
vout3_d12
vout3_d13
vout3_d14
vout3_d15
vout3_d16
gpio1_18
gpio1_19
gpio1_20
gpio1_21
sysboot12
sysboot13
sysboot14
sysboot15
Driver off
CTRL_CORE_PAD_ J3
GPMC_AD13
CTRL_CORE_PAD_ H2
GPMC_AD14
CTRL_CORE_PAD_ H3
GPMC_AD15
CTRL_CORE_PAD_ R6
GPMC_A0
vin2a_d0
vin1a_d0
vin1b_d0
i2c4_scl
uart5_rxd
gpio7_3
gpmc_a26
gpmc_a16
0x1444
0x1448
0x144C
0x1450
0x1454
0x1458
0x145C
0x1460
0x1464
0x1468
0x146C
0x1470
0x1474
0x1478
0x147C
0x1480
0x1484
CTRL_CORE_PAD_ T9
GPMC_A1
gpmc_a1
gpmc_a2
gpmc_a3
gpmc_a4
gpmc_a5
gpmc_a6
gpmc_a7
gpmc_a8
gpmc_a9
gpmc_a10
gpmc_a11
gpmc_a12
gpmc_a13
gpmc_a14
gpmc_a15
gpmc_a16
gpmc_a17
vin1a_d17
vin1a_d18
vin1a_d19
vin1a_d20
vin1a_d21
vin1a_d22
vin1a_d23
vout3_d17
vout3_d18
vout3_d19
vout3_d20
vout3_d21
vout3_d22
vout3_d23
vin2a_d1
vin1a_d1
vin1b_d1
vin1b_d2
vin1b_d3
vin1b_d4
vin1b_d5
vin1b_d6
vin1b_d7
i2c4_sda
uart7_rxd
uart7_txd
i2c5_scl
uart5_txd
uart5_ctsn
uart5_rtsn
uart6_rxd
uart6_txd
uart6_ctsn
uart6_rtsn
spi4_sclk
spi4_d1
gpio7_4
gpio7_5
gpio7_6
gpio1_26
gpio1_27
gpio1_28
gpio1_29
gpio1_30
gpio1_31
gpio2_0
gpio2_1
gpio2_2
gpio2_3
gpio2_4
gpio2_5
gpio2_6
gpio2_7
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD_ T6
GPMC_A2
vin2a_d2
vin1a_d2
CTRL_CORE_PAD_ T7
GPMC_A3
qspi1_cs2
qspi1_cs3
vin2a_d3
vin1a_d3
CTRL_CORE_PAD_ P6
GPMC_A4
vin2a_d4
vin1a_d4
CTRL_CORE_PAD_ R9
GPMC_A5
vin2a_d5
vin1a_d5
i2c5_sda
uart8_rxd
uart8_txd
CTRL_CORE_PAD_ R5
GPMC_A6
vin2a_d6
vin1a_d6
CTRL_CORE_PAD_ P5
GPMC_A7
vin2a_d7
vin1a_d7
CTRL_CORE_PAD_ N7
GPMC_A8
vin1a_hsync0 vout3_hsync
vin1a_vsync0 vout3_vsync
vin1b_hsync1 timer12
vin1b_vsync1 timer11
CTRL_CORE_PAD_ R4
GPMC_A9
CTRL_CORE_PAD_ N9
GPMC_A10
vin1a_de0
vin1a_fld0
vout3_de
vout3_fld
vin1b_clk1
vin1b_de1
vin1b_fld1
timer10
timer9
timer8
timer7
timer6
timer5
spi4_d0
CTRL_CORE_PAD_ P9
GPMC_A11
vin2a_fld0
vin1a_fld0
spi4_cs0
spi4_cs1
spi4_cs2
spi4_cs3
CTRL_CORE_PAD_ P4
GPMC_A12
vin2a_clk0
vin1a_clk0
gpmc_a0
dma_evt1
dma_evt2
CTRL_CORE_PAD_ R3
GPMC_A13
qspi1_rtclk
qspi1_d3
qspi1_d2
qspi1_d0
qspi1_d1
vin2a_hsync0
vin1a_hsync0
CTRL_CORE_PAD_ T2
GPMC_A14
vin2a_vsync0
vin1a_vsync0
CTRL_CORE_PAD_ U2
GPMC_A15
vin2a_d8
vin1a_d8
CTRL_CORE_PAD_ U1
GPMC_A16
vin2a_d9
vin1a_d9
CTRL_CORE_PAD_ P3
GPMC_A17
vin2a_d10
vin1a_d10
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
75
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 4-3. Multiplexing Characteristics (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS
REGISTER NAME
0
1
2
3*
4*
5*
6*
7
8*
9
10
14*
gpio2_8
15
0x1488
CTRL_CORE_PAD_ R2
GPMC_A18
gpmc_a18
qspi1_sclk
vin2a_d11
vin1a_d11
Driver off
0x148C
0x1490
0x1494
0x1498
0x149C
0x14A0
0x14A4
0x14A8
0x14AC
0x14B0
0x14B4
0x14B8
CTRL_CORE_PAD_ K7
GPMC_A19
gpmc_a19
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
gpmc_a25
gpmc_a26
gpmc_a27
gpmc_cs1
gpmc_cs0
gpmc_cs2
mmc2_dat4
mmc2_dat5
mmc2_dat6
mmc2_dat7
mmc2_clk
gpmc_a13
gpmc_a14
gpmc_a15
gpmc_a16
gpmc_a17
gpmc_a18
gpmc_a19
gpmc_a20
gpmc_a21
gpmc_a22
vin2a_d12
vin1a_d12
vin2b_d0
vin1b_d0
gpio2_9
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD_ M7
GPMC_A20
vin2a_d13
vin1a_d13
vin2b_d1
vin1b_d1
gpio2_10
gpio2_11
gpio2_12
gpio2_13
gpio2_14
gpio2_15
gpio2_16
gpio2_17
gpio2_18
gpio2_19
CTRL_CORE_PAD_ J5
GPMC_A21
vin2a_d14
vin1a_d14
vin2b_d2
vin1b_d2
CTRL_CORE_PAD_ K6
GPMC_A22
vin2a_d15
vin1a_d15
vin2b_d3
vin1b_d3
CTRL_CORE_PAD_ J7
GPMC_A23
vin2a_fld0
vin1a_fld0
vin2b_d4
vin1b_d4
CTRL_CORE_PAD_ J4
GPMC_A24
mmc2_dat0
mmc2_dat1
mmc2_dat2
mmc2_dat3
mmc2_cmd
vin2b_d5
vin1b_d5
CTRL_CORE_PAD_ J6
GPMC_A25
vin2b_d6
vin1b_d6
CTRL_CORE_PAD_ H4
GPMC_A26
vin2b_d7
vin1b_d7
CTRL_CORE_PAD_ H5
GPMC_A27
vin2b_hsync1
vin1b_hsync1
CTRL_CORE_PAD_ H6
GPMC_CS1
vin2a_de0
vin1a_de0
vin2b_vsync1
vin1b_vsync1
CTRL_CORE_PAD_ T1
GPMC_CS0
CTRL_CORE_PAD_ P2
GPMC_CS2
qspi1_cs0
qspi1_cs1
gpmc_cs7
gpio2_20
gpmc_a23
gpmc_a13
0x14BC
CTRL_CORE_PAD_ P1
GPMC_CS3
gpmc_cs3
gpmc_clk
vin1a_clk0
vout3_clk
gpmc_a1
gpio2_21
gpmc_a24
gpmc_a14
Driver off
0x14C0
0x14C4
0x14C8
0x14CC
0x14D0
0x14D4
0x14D8
CTRL_CORE_PAD_ P7
GPMC_CLK
clkout1
clkout2
gpmc_wait1
gpmc_wait1
vin2a_hsync0 vin2a_de0
vin1a_hsync0 vin1a_de0
vin2b_clk1
vin1b_clk1
timer4
timer3
i2c3_scl
dma_evt1
dma_evt2
gpio2_22
gpmc_a20
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD_ N1
GPMC_ADVN_ALE
gpmc_advn_al gpmc_cs6
e
vin2a_vsync0 gpmc_a2
vin1a_vsync0
gpmc_a23
i2c3_sda
gpio2_23
gpmc_a19
CTRL_CORE_PAD_ M5
GPMC_OEN_REN
gpmc_oen_re
n
gpio2_24
gpio2_25
CTRL_CORE_PAD_ M3
GPMC_WEN
gpmc_wen
CTRL_CORE_PAD_ N6
GPMC_BEN0
gpmc_ben0
gpmc_ben1
gpmc_wait0
gpmc_cs4
gpmc_cs5
vin2b_de1
vin1b_de1
timer2
timer1
dma_evt3
dma_evt4
gpio2_26
gpmc_a21
CTRL_CORE_PAD_ M4
GPMC_BEN1
vin2b_clk1
vin1b_clk1
gpmc_a3
emu5
vin2b_fld1
vin1b_fld1
gpio2_27
gpmc_a22
CTRL_CORE_PAD_ N2
GPMC_WAIT0
gpio2_28
gpmc_a25
gpmc_a15
0x1554
CTRL_CORE_PAD_V E1
IN2A_CLK0
vin2a_clk0
vout2_fld
eQEP1A_in
gpio3_28
gpmc_a27
gpmc_a17
Driver off
76
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-3. Multiplexing Characteristics (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS
REGISTER NAME
0
1
2
3*
4*
5*
6*
7
8*
9
10
14*
15
0x1558
CTRL_CORE_PAD_V G2
IN2A_DE0
vin2a_de0
vin2a_fld0
vin2b_fld1
vin2b_de1
vout2_de
emu6
emu7
eQEP1B_in
gpio3_29
Driver off
0x155C
CTRL_CORE_PAD_V H7
IN2A_FLD0
vin2a_fld0
vin2b_clk1
vout2_clk
eQEP1_index gpio3_30
gpmc_a27
Driver off
gpmc_a18
0x1560
0x1564
0x1568
0x156C
0x1570
0x1574
0x1578
0x157C
0x1580
0x1584
0x1588
0x158C
0x1590
0x1594
0x1598
0x159C
0x15A0
0x15A4
0x15A8
0x15AC
0x15B0
CTRL_CORE_PAD_V G1
IN2A_HSYNC0
vin2a_hsync0
vin2a_vsync0
vin2a_d0
vin2b_hsync1 vout2_hsync emu8
vin2b_vsync1 vout2_vsync emu9
uart9_rxd
uart9_txd
uart9_ctsn
uart9_rtsn
spi4_sclk
spi4_d1
eQEP1_strob gpio3_31
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
e
gpmc_a27
CTRL_CORE_PAD_V G6
IN2A_VSYNC0
ehrpwm1A
gpio4_0
CTRL_CORE_PAD_V F2
IN2A_D0
vout2_d23
vout2_d22
vout2_d21
vout2_d20
vout2_d19
vout2_d18
vout2_d17
vout2_d16
vout2_d15
vout2_d14
vout2_d13
vout2_d12
vout2_d11
vout2_d10
vout2_d9
vout2_d8
vout2_d7
vout2_d6
vout2_d5
emu10
spi4_d0
ehrpwm1B
gpio4_1
CTRL_CORE_PAD_V F3
IN2A_D1
vin2a_d1
emu11
emu12
emu13
emu14
emu15
emu16
emu17
emu18
emu19
spi4_cs0
ehrpwm1_trip gpio4_2
zone_input
CTRL_CORE_PAD_V D1
IN2A_D2
vin2a_d2
uart10_rxd
uart10_txd
uart10_ctsn
uart10_rtsn
mii1_rxd1
mii1_rxd2
mii1_rxd3
mii1_rxd0
eCAP1_in_P gpio4_3
WM1_out
CTRL_CORE_PAD_V E2
IN2A_D3
vin2a_d3
ehrpwm1_syn gpio4_4
ci
CTRL_CORE_PAD_V D2
IN2A_D4
vin2a_d4
ehrpwm1_syn gpio4_5
co
CTRL_CORE_PAD_V F4
IN2A_D5
vin2a_d5
eQEP2A_in
gpio4_6
CTRL_CORE_PAD_V C1
IN2A_D6
vin2a_d6
eQEP2B_in
gpio4_7
CTRL_CORE_PAD_V E4
IN2A_D7
vin2a_d7
eQEP2_index gpio4_8
eQEP2_strob gpio4_9
CTRL_CORE_PAD_V F5
IN2A_D8
vin2a_d8
e
gpmc_a26
CTRL_CORE_PAD_V E6
IN2A_D9
vin2a_d9
ehrpwm2A
gpio4_10
gpmc_a25
CTRL_CORE_PAD_V D3
IN2A_D10
vin2a_d10
vin2a_d11
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
vin2a_d16
vin2a_d17
vin2a_d18
mdio_mclk
mdio_d
ehrpwm2B
gpio4_11
gpmc_a24
CTRL_CORE_PAD_V F6
IN2A_D11
ehrpwm2_trip gpio4_12
zone_input gpmc_a23
CTRL_CORE_PAD_V D5
IN2A_D12
rgmii1_txc
rgmii1_txctl
rgmii1_txd3
rgmii1_txd2
rgmii1_txd1
rgmii1_txd0
rgmii1_rxc
mii1_rxclk
mii1_rxdv
mii1_txclk
mii1_txd0
mii1_txd1
mii1_txd2
mii1_txd3
eCAP2_in_P gpio4_13
WM2_out
CTRL_CORE_PAD_V C2
IN2A_D13
eQEP3A_in
gpio4_14
CTRL_CORE_PAD_V C3
IN2A_D14
eQEP3B_in
gpio4_15
CTRL_CORE_PAD_V C4
IN2A_D15
eQEP3_index gpio4_16
CTRL_CORE_PAD_V B2
IN2A_D16
vin2b_d7
vin2b_d6
vin2b_d5
eQEP3_strob gpio4_24
e
CTRL_CORE_PAD_V D6
IN2A_D17
ehrpwm3A
gpio4_25
CTRL_CORE_PAD_V C5
IN2A_D18
ehrpwm3B
gpio4_26
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
77
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 4-3. Multiplexing Characteristics (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS
REGISTER NAME
0
1
2
3*
4*
5*
6*
7
8*
9
10
14*
15
0x15B4
CTRL_CORE_PAD_V A3
IN2A_D19
vin2a_d19
vin2b_d4
rgmii1_rxctl
vout2_d4
mii1_txer
ehrpwm3_trip gpio4_27
zone_input
Driver off
0x15B8
0x15BC
0x15C0
0x15C4
0x15C8
0x15CC
0x15D0
0x15D4
0x15D8
0x15DC
0x15E0
0x15E4
0x15E8
0x15EC
0x15F0
0x15F4
0x15F8
0x15FC
0x1600
0x1604
0x1608
0x160C
0x1610
CTRL_CORE_PAD_V B3
IN2A_D20
vin2a_d20
vin2a_d21
vin2a_d22
vin2a_d23
vout1_clk
vout1_de
vout1_fld
vout1_hsync
vout1_vsync
vout1_d0
vout1_d1
vout1_d2
vout1_d3
vout1_d4
vout1_d5
vout1_d6
vout1_d7
vout1_d8
vout1_d9
vout1_d10
vout1_d11
vout1_d12
vout1_d13
vin2b_d3
vin2b_d2
vin2b_d1
vin2b_d0
rgmii1_rxd3
rgmii1_rxd2
rgmii1_rxd1
rgmii1_rxd0
vout2_d3
vout2_d2
vout2_d1
vout2_d0
vin1a_fld0
vin1a_de0
vin1a_clk0
mii1_rxer
mii1_col
mii1_crs
mii1_txen
spi3_cs0
spi3_d1
eCAP3_in_P gpio4_28
WM3_out
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD_V B4
IN2A_D21
gpio4_29
gpio4_30
gpio4_31
gpio4_19
gpio4_20
gpio4_21
gpio4_22
gpio4_23
gpio8_0
gpio8_1
gpio8_2
gpio8_3
gpio8_4
gpio8_5
gpio8_6
gpio8_7
gpio8_8
gpio8_9
gpio8_10
gpio8_11
gpio8_12
gpio8_13
CTRL_CORE_PAD_V B5
IN2A_D22
CTRL_CORE_PAD_V A4
IN2A_D23
CTRL_CORE_PAD_V D11
OUT1_CLK
vin2a_fld0
vin1a_fld0
CTRL_CORE_PAD_V B10
OUT1_DE
vin2a_de0
vin1a_de0
CTRL_CORE_PAD_V B11
OUT1_FLD
vin2a_clk0
vin1a_clk0
spi3_cs1
spi3_d0
CTRL_CORE_PAD_V C11
OUT1_HSYNC
vin2a_hsync0 vin1a_hsync0
vin1a_hsync0
CTRL_CORE_PAD_V E11
OUT1_VSYNC
vin2a_vsync0 vin1a_vsync0
vin1a_vsync0
spi3_sclk
spi3_cs2
CTRL_CORE_PAD_V F11
OUT1_D0
uart5_rxd
uart5_txd
emu2
vin2a_d16
vin1a_d16
vin1a_d16
vin1a_d17
vin1a_d18
vin1a_d19
vin1a_d20
vin1a_d21
vin1a_d22
vin1a_d23
vin1a_d8
CTRL_CORE_PAD_V G10
OUT1_D1
vin2a_d17
vin1a_d17
CTRL_CORE_PAD_V F10
OUT1_D2
vin2a_d18
vin1a_d18
obs0
obs1
obs2
obs3
obs4
obs16
obs17
obs18
obs19
obs20
obs_irq1
CTRL_CORE_PAD_V G11
OUT1_D3
emu5
vin2a_d19
vin1a_d19
obs_dmarq1
CTRL_CORE_PAD_V E9
OUT1_D4
emu6
vin2a_d20
vin1a_d20
CTRL_CORE_PAD_V F9
OUT1_D5
emu7
vin2a_d21
vin1a_d21
CTRL_CORE_PAD_V F8
OUT1_D6
emu8
vin2a_d22
vin1a_d22
CTRL_CORE_PAD_V E7
OUT1_D7
emu9
vin2a_d23
vin1a_d23
CTRL_CORE_PAD_V E8
OUT1_D8
uart6_rxd
uart6_txd
emu3
vin2a_d8
vin1a_d8
CTRL_CORE_PAD_V D9
OUT1_D9
vin2a_d9
vin1a_d9
vin1a_d9
CTRL_CORE_PAD_V D7
OUT1_D10
vin2a_d10
vin1a_d10
vin1a_d10
vin1a_d11
vin1a_d12
vin1a_d13
obs5
obs6
obs7
obs8
obs21
obs22
obs23
obs24
obs_irq2
CTRL_CORE_PAD_V D8
OUT1_D11
emu10
emu11
emu12
vin2a_d11
vin1a_d11
obs_dmarq2
CTRL_CORE_PAD_V A5
OUT1_D12
vin2a_d12
vin1a_d12
CTRL_CORE_PAD_V C6
OUT1_D13
vin2a_d13
vin1a_d13
78
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-3. Multiplexing Characteristics (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS
REGISTER NAME
0
1
2
3*
4*
5*
6*
7
8*
9
10
14*
15
0x1614
CTRL_CORE_PAD_V C8
OUT1_D14
vout1_d14
emu13
vin2a_d14
vin1a_d14
vin1a_d14
obs9
obs25
obs26
gpio8_14
Driver off
0x1618
0x161C
0x1620
0x1624
0x1628
0x162C
0x1630
0x1634
0x1638
0x163C
0x1640
0x1644
0x1648
0x164C
0x1650
0x1654
0x1658
0x165C
0x1660
0x1664
0x1668
0x166C
0x1670
CTRL_CORE_PAD_V C7
OUT1_D15
vout1_d15
vout1_d16
vout1_d17
vout1_d18
vout1_d19
vout1_d20
vout1_d21
vout1_d22
vout1_d23
mdio_mclk
mdio_d
emu14
uart7_rxd
uart7_txd
emu4
vin2a_d15
vin1a_d15
vin1a_d15
vin1a_d0
vin1a_d1
vin1a_d2
vin1a_d3
vin1a_d4
vin1a_d5
vin1a_d6
vin1a_d7
vin2a_clk0
vin2a_d0
vin2a_d11
vin2a_d1
vin2a_d2
vin2a_d3
vin2a_d4
vin2a_de0
obs10
gpio8_15
gpio8_16
gpio8_17
gpio8_18
gpio8_19
gpio8_20
gpio8_21
gpio8_22
gpio8_23
gpio5_15
gpio5_16
gpio5_17
gpio5_18
gpio5_19
gpio5_20
gpio5_21
gpio5_22
gpio5_23
gpio5_24
gpio5_25
gpio5_26
gpio5_27
gpio5_28
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD_V B7
OUT1_D16
vin2a_d0
vin1a_d0
CTRL_CORE_PAD_V B8
OUT1_D17
vin2a_d1
vin1a_d1
CTRL_CORE_PAD_V A7
OUT1_D18
vin2a_d2
vin1a_d2
obs11
obs12
obs13
obs14
obs15
obs27
obs28
obs29
obs30
obs31
CTRL_CORE_PAD_V A8
OUT1_D19
emu15
emu16
emu17
emu18
emu19
vin2a_d3
vin1a_d3
CTRL_CORE_PAD_V C9
OUT1_D20
vin2a_d4
vin1a_d4
CTRL_CORE_PAD_V A9
OUT1_D21
vin2a_d5
vin1a_d5
CTRL_CORE_PAD_V B9
OUT1_D22
vin2a_d6
vin1a_d6
CTRL_CORE_PAD_V A10
OUT1_D23
vin2a_d7
vin1a_d7
spi3_cs3
CTRL_CORE_PAD_ V1
MDIO_MCLK
uart3_rtsn
uart3_ctsn
mii0_col
vin1b_clk1
vin1b_d0
CTRL_CORE_PAD_ U4
MDIO_D
mii0_txer
CTRL_CORE_PAD_R U3
MII_MHZ_50_CLK
RMII_MHZ_50
_CLK
CTRL_CORE_PAD_U V2
ART3_RXD
uart3_rxd
rmii1_crs
rmii1_rxer
rmii1_rxd1
rmii1_rxd0
mii0_rxdv
mii0_rxclk
mii0_rxd3
mii0_rxd2
mii0_crs
vin1b_d1
vin1b_d2
vin1b_d3
vin1b_d4
vin1b_de1
spi3_sclk
spi3_d1
CTRL_CORE_PAD_U Y1
ART3_TXD
uart3_txd
spi4_cs1
spi4_cs2
spi4_cs3
uart4_rxd
uart4_txd
uart4_ctsn
uart4_rtsn
CTRL_CORE_PAD_R W9
GMII0_TXC
rgmii0_txc
rgmii0_txctl
rgmii0_txd3
rgmii0_txd2
rgmii0_txd1
rgmii0_txd0
rgmii0_rxc
rgmii0_rxctl
rgmii0_rxd3
uart3_ctsn
uart3_rtsn
rmii0_crs
usb3_ulpi_clk spi3_d0
usb3_ulpi_stp spi3_cs0
usb3_ulpi_dir spi4_sclk
CTRL_CORE_PAD_R V9
GMII0_TXCTL
CTRL_CORE_PAD_R V7
GMII0_TXD3
CTRL_CORE_PAD_R U7
GMII0_TXD2
rmii0_rxer
rmii0_rxd1
rmii0_rxd0
mii0_rxer
mii0_rxd1
mii0_rxd0
mii0_txclk
mii0_txd3
mii0_txd2
vin2a_hsync0 vin1b_hsync1 usb3_ulpi_nxt spi4_d1
vin2a_vsync0 vin1b_vsync1 usb3_ulpi_d0 spi4_d0
CTRL_CORE_PAD_R V6
GMII0_TXD1
CTRL_CORE_PAD_R U6
GMII0_TXD0
vin2a_d10
vin2a_d5
vin2a_d6
vin2a_d7
usb3_ulpi_d1 spi4_cs0
usb3_ulpi_d2
CTRL_CORE_PAD_R U5
GMII0_RXC
rmii1_txen
rmii1_txd1
rmii1_txd0
vin1b_d5
vin1b_d6
vin1b_d7
CTRL_CORE_PAD_R V5
GMII0_RXCTL
usb3_ulpi_d3
CTRL_CORE_PAD_R V4
GMII0_RXD3
usb3_ulpi_d4
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
79
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 4-3. Multiplexing Characteristics (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS
REGISTER NAME
0
1
2
3*
4*
5*
6*
7
8*
9
10
14*
15
0x1674
CTRL_CORE_PAD_R V3
GMII0_RXD2
rgmii0_rxd2
rmii0_txen
mii0_txen
vin2a_d8
usb3_ulpi_d5
gpio5_29
Driver off
0x1678
0x167C
0x1680
0x1684
0x1688
0x168C
0x1690
0x1694
0x1698
0x169C
0x16A0
0x16A4
0x16A8
0x16AC
0x16B0
0x16B4
0x16B8
0x16BC
0x16C0
0x16C4
0x16C8
0x16CC
0x16D0
CTRL_CORE_PAD_R Y2
GMII0_RXD1
rgmii0_rxd1
rgmii0_rxd0
usb1_drvvbus
usb2_drvvbus
gpio6_14
rmii0_txd1
rmii0_txd0
mii0_txd1
mii0_txd0
vin2a_d9
usb3_ulpi_d6
usb3_ulpi_d7
gpio5_30
gpio5_31
gpio6_12
gpio6_13
gpio6_14
gpio6_15
gpio6_16
gpio6_17
gpio6_18
gpio6_19
gpio6_20
gpio7_31
gpio7_30
gpio5_0
gpio5_1
gpio5_2
gpio5_3
gpio5_4
gpio5_5
gpio5_6
gpio5_7
gpio5_8
gpio5_9
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD_R W2
GMII0_RXD0
vin2a_fld0
vin1b_fld1
CTRL_CORE_PAD_U AB10
SB1_DRVVBUS
timer16
CTRL_CORE_PAD_U AC10
SB2_DRVVBUS
timer15
CTRL_CORE_PAD_ E21
GPIO6_14
mcasp1_axr8 dcan2_tx
mcasp1_axr9 dcan2_rx
uart10_rxd
uart10_txd
vout2_hsync
vout2_vsync
vout2_fld
vin2a_hsync0 i2c3_sda
vin1a_hsync0
timer1
CTRL_CORE_PAD_ F20
GPIO6_15
gpio6_15
vin2a_vsync0 i2c3_scl
vin1a_vsync0
timer2
CTRL_CORE_PAD_ F21
GPIO6_16
gpio6_16
mcasp1_axr1
0
vin2a_fld0
vin1a_fld0
clkout1
timer3
CTRL_CORE_PAD_X D18
REF_CLK0
xref_clk0
mcasp2_axr8 mcasp1_axr4 mcasp1_ahclk mcasp5_ahclk
vin1a_d0
clkout2
timer13
timer14
timer15
timer16
i2c3_sda
i2c3_scl
i2c4_sda
i2c4_scl
i2c5_sda
i2c5_scl
x
x
CTRL_CORE_PAD_X E17
REF_CLK1
xref_clk1
mcasp2_axr9 mcasp1_axr5 mcasp2_ahclk mcasp6_ahclk
vin1a_clk0
x
x
CTRL_CORE_PAD_X B26
REF_CLK2
xref_clk2
mcasp2_axr1 mcasp1_axr6 mcasp3_ahclk mcasp7_ahclk
0
vout2_clk
vout2_de
vin2a_clk0
vin1a_clk0
x
x
CTRL_CORE_PAD_X C23
REF_CLK3
xref_clk3
mcasp2_axr1 mcasp1_axr7 mcasp4_ahclk mcasp8_ahclk
1
vin2a_de0
vin1a_de0
clkout3
x
x
CTRL_CORE_PAD_ C14
MCASP1_ACLKX
mcasp1_aclkx
mcasp1_fsx
vin1a_fld0
vin1a_de0
CTRL_CORE_PAD_ D14
MCASP1_FSX
CTRL_CORE_PAD_ B14
MCASP1_ACLKR
mcasp1_aclkr mcasp7_axr2
vout2_d0
vout2_d1
vin2a_d0
vin1a_d0
CTRL_CORE_PAD_ J14
MCASP1_FSR
mcasp1_fsr
mcasp7_axr3
vin2a_d1
vin1a_d1
CTRL_CORE_PAD_ G12
MCASP1_AXR0
mcasp1_axr0
mcasp1_axr1
uart6_rxd
uart6_txd
uart6_ctsn
uart6_rtsn
vin1a_vsync0
vin1a_hsync0
CTRL_CORE_PAD_ F12
MCASP1_AXR1
CTRL_CORE_PAD_ G13
MCASP1_AXR2
mcasp1_axr2 mcasp6_axr2
mcasp1_axr3 mcasp6_axr3
mcasp1_axr4 mcasp4_axr2
mcasp1_axr5 mcasp4_axr3
mcasp1_axr6 mcasp5_axr2
mcasp1_axr7 mcasp5_axr3
vout2_d2
vout2_d3
vout2_d4
vout2_d5
vout2_d6
vout2_d7
vin2a_d2
vin1a_d2
CTRL_CORE_PAD_ J11
MCASP1_AXR3
vin2a_d3
vin1a_d3
CTRL_CORE_PAD_ E12
MCASP1_AXR4
vin2a_d4
vin1a_d4
CTRL_CORE_PAD_ F13
MCASP1_AXR5
vin2a_d5
vin1a_d5
CTRL_CORE_PAD_ C12
MCASP1_AXR6
vin2a_d6
vin1a_d6
CTRL_CORE_PAD_ D12
MCASP1_AXR7
vin2a_d7
vin1a_d7
timer4
80
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-3. Multiplexing Characteristics (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS
REGISTER NAME
0
1
2
3*
4*
5*
6*
7
8*
9
10
timer5
14*
15
0x16D4
CTRL_CORE_PAD_ B12
mcasp1_axr8 mcasp6_axr0
spi3_sclk
vin1a_d15
gpio5_10
Driver off
MCASP1_AXR8
0x16D8
0x16DC
0x16E0
0x16E4
0x16E8
0x16EC
0x16F0
0x16F4
0x16F8
0x16FC
0x1700
0x1704
0x1708
0x170C
0x1710
0x1714
0x1718
0x171C
0x1720
0x1724
0x1728
0x172C
0x1730
CTRL_CORE_PAD_ A11
MCASP1_AXR9
mcasp1_axr9 mcasp6_axr1
spi3_d1
vin1a_d14
vin1a_d13
vin1a_d12
vin1a_d11
vin1a_d10
vin1a_d9
vin1a_d8
vin1a_d7
vin1a_d6
timer6
timer7
timer8
timer9
timer10
timer11
timer12
gpio5_11
gpio5_12
gpio4_17
gpio4_18
gpio6_4
gpio6_5
gpio6_6
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD_ B13
MCASP1_AXR10
mcasp1_axr1 mcasp6_aclkx mcasp6_aclkr spi3_d0
0
CTRL_CORE_PAD_ A12
MCASP1_AXR11
mcasp1_axr1 mcasp6_fsx
1
mcasp6_fsr
spi3_cs0
CTRL_CORE_PAD_ E14
MCASP1_AXR12
mcasp1_axr1 mcasp7_axr0
2
spi3_cs1
CTRL_CORE_PAD_ A13
MCASP1_AXR13
mcasp1_axr1 mcasp7_axr1
3
CTRL_CORE_PAD_ G14
MCASP1_AXR14
mcasp1_axr1 mcasp7_aclkx mcasp7_aclkr
4
CTRL_CORE_PAD_ F14
MCASP1_AXR15
mcasp1_axr1 mcasp7_fsx
5
mcasp7_fsr
CTRL_CORE_PAD_ A19
MCASP2_ACLKX
mcasp2_aclkx
CTRL_CORE_PAD_ A18
MCASP2_FSX
mcasp2_fsx
CTRL_CORE_PAD_ E15
MCASP2_ACLKR
mcasp2_aclkr mcasp8_axr2
vout2_d8
vout2_d9
vout2_d10
vout2_d11
vin2a_d8
vin1a_d8
CTRL_CORE_PAD_ A20
MCASP2_FSR
mcasp2_fsr
mcasp8_axr3
vin2a_d9
vin1a_d9
CTRL_CORE_PAD_ B15
MCASP2_AXR0
mcasp2_axr0
mcasp2_axr1
vin2a_d10
vin1a_d10
CTRL_CORE_PAD_ A15
MCASP2_AXR1
vin2a_d11
vin1a_d11
CTRL_CORE_PAD_ C15
MCASP2_AXR2
mcasp2_axr2 mcasp3_axr2
mcasp2_axr3 mcasp3_axr3
mcasp2_axr4 mcasp8_axr0
mcasp2_axr5 mcasp8_axr1
vin1a_d5
vin1a_d4
gpio6_8
gpio6_9
gpio1_4
gpio6_7
gpio2_29
gpio1_5
gpio5_13
gpio5_14
CTRL_CORE_PAD_ A16
MCASP2_AXR3
CTRL_CORE_PAD_ D15
MCASP2_AXR4
vout2_d12
vout2_d13
vout2_d14
vout2_d15
vin2a_d12
vin1a_d12
CTRL_CORE_PAD_ B16
MCASP2_AXR5
vin2a_d13
vin1a_d13
CTRL_CORE_PAD_ B17
MCASP2_AXR6
mcasp2_axr6 mcasp8_aclkx mcasp8_aclkr
mcasp2_axr7 mcasp8_fsx mcasp8_fsr
vin2a_d14
vin1a_d14
CTRL_CORE_PAD_ A17
MCASP2_AXR7
vin2a_d15
vin1a_d15
CTRL_CORE_PAD_ B18
MCASP3_ACLKX
mcasp3_aclkx mcasp3_aclkr mcasp2_axr1 uart7_rxd
2
vin1a_d3
vin1a_d2
vin1a_d1
vin1a_d0
CTRL_CORE_PAD_ F15
MCASP3_FSX
mcasp3_fsx
mcasp3_axr0
mcasp3_axr1
mcasp3_fsr
mcasp2_axr1 uart7_txd
3
CTRL_CORE_PAD_ B19
MCASP3_AXR0
mcasp2_axr1 uart7_ctsn
4
uart5_rxd
uart5_txd
CTRL_CORE_PAD_ C17
MCASP3_AXR1
mcasp2_axr1 uart7_rtsn
5
vin1a_fld0
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
81
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 4-3. Multiplexing Characteristics (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS
REGISTER NAME
0
1
2
3*
4*
5*
6*
7
8*
9
10
14*
15
0x1734
CTRL_CORE_PAD_ C18
MCASP4_ACLKX
mcasp4_aclkx mcasp4_aclkr spi3_sclk
uart8_rxd
i2c4_sda
vout2_d16
vin2a_d16
vin1a_d16
vin1a_d15
Driver off
0x1738
0x173C
0x1740
0x1744
0x1748
0x174C
0x1750
0x1754
0x1758
0x175C
0x1760
0x1764
0x1768
0x176C
0x1770
0x1774
0x1778
0x177C
0x1780
0x1784
0x1788
0x178C
0x1790
CTRL_CORE_PAD_ A21
MCASP4_FSX
mcasp4_fsx
mcasp4_axr0
mcasp4_axr1
mcasp4_fsr
spi3_d1
spi3_d0
spi3_cs0
uart8_txd
uart8_ctsn
uart8_rtsn
uart9_rxd
uart9_txd
uart9_ctsn
uart9_rtsn
i2c4_scl
vout2_d17
vout2_d18
vout2_d19
vout2_d20
vout2_d21
vout2_d22
vout2_d23
vin2a_d17
vin1a_d17
vin1a_d14
vin1a_d13
vin1a_d12
vin1a_d11
vin1a_d10
vin1a_d9
vin1a_d8
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD_ G16
MCASP4_AXR0
uart4_rxd
uart4_txd
i2c5_sda
i2c5_scl
vin2a_d18
vin1a_d18
i2c6_scl
CTRL_CORE_PAD_ D17
MCASP4_AXR1
vin2a_d19
vin1a_d19
i2c6_sda
CTRL_CORE_PAD_ AA3
MCASP5_ACLKX
mcasp5_aclkx mcasp5_aclkr spi4_sclk
vin2a_d20
vin1a_d20
CTRL_CORE_PAD_ AB9
MCASP5_FSX
mcasp5_fsx
mcasp5_axr0
mcasp5_axr1
mmc1_clk
mcasp5_fsr
spi4_d1
spi4_d0
spi4_cs0
vin2a_d21
vin1a_d21
CTRL_CORE_PAD_ AB3
MCASP5_AXR0
uart3_rxd
uart3_txd
vin2a_d22
vin1a_d22
CTRL_CORE_PAD_ AA4
MCASP5_AXR1
vin2a_d23
vin1a_d23
CTRL_CORE_PAD_ W6
MMC1_CLK
gpio6_21
gpio6_22
gpio6_23
gpio6_24
gpio6_25
gpio6_26
gpio6_27
gpio6_28
gpio6_10
gpio6_11
CTRL_CORE_PAD_ Y6
MMC1_CMD
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
mmc1_sdcd
mmc1_sdwp
gpio6_10
CTRL_CORE_PAD_ AA6
MMC1_DAT0
CTRL_CORE_PAD_ Y4
MMC1_DAT1
CTRL_CORE_PAD_ AA5
MMC1_DAT2
CTRL_CORE_PAD_ Y3
MMC1_DAT3
CTRL_CORE_PAD_ W7
MMC1_SDCD
uart6_rxd
uart6_txd
i2c4_sda
i2c4_scl
CTRL_CORE_PAD_ Y9
MMC1_SDWP
CTRL_CORE_PAD_ AC5
GPIO6_10
mdio_mclk
mdio_d
i2c3_sda
i2c3_scl
usb3_ulpi_d7 vin2b_hsync1
usb3_ulpi_d6 vin2b_vsync1
usb3_ulpi_d5 vin2b_d7
usb3_ulpi_d4 vin2b_d6
usb3_ulpi_d3 vin2b_d5
usb3_ulpi_d2 vin2b_d4
usb3_ulpi_d1 vin2b_d3
usb3_ulpi_d0 vin2b_d2
vin1a_clk0
vin1a_de0
vin1a_d7
vin1a_d6
vin1a_d5
vin1a_d4
vin1a_d3
vin1a_d2
ehrpwm2A
ehrpwm2B
CTRL_CORE_PAD_ AB4
GPIO6_11
gpio6_11
CTRL_CORE_PAD_ AD4
MMC3_CLK
mmc3_clk
ehrpwm2_trip gpio6_29
zone_input
CTRL_CORE_PAD_ AC4
MMC3_CMD
mmc3_cmd
mmc3_dat0
mmc3_dat1
mmc3_dat2
mmc3_dat3
spi3_sclk
spi3_d1
spi3_d0
spi3_cs0
spi3_cs1
eCAP2_in_P gpio6_30
WM2_out
CTRL_CORE_PAD_ AC7
MMC3_DAT0
uart5_rxd
uart5_txd
uart5_ctsn
uart5_rtsn
eQEP3A_in
gpio6_31
CTRL_CORE_PAD_ AC6
MMC3_DAT1
eQEP3B_in
gpio7_0
CTRL_CORE_PAD_ AC9
MMC3_DAT2
eQEP3_index gpio7_1
CTRL_CORE_PAD_ AC3
MMC3_DAT3
eQEP3_strob gpio7_2
e
82
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-3. Multiplexing Characteristics (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS
REGISTER NAME
0
1
2
3*
4*
5*
6*
7
8*
9
10
14*
15
0x1794
CTRL_CORE_PAD_ AC8
MMC3_DAT4
mmc3_dat4
spi4_sclk
uart10_rxd
usb3_ulpi_nxt vin2b_d1
usb3_ulpi_dir vin2b_d0
usb3_ulpi_stp vin2b_de1
usb3_ulpi_clk vin2b_clk1
vin1a_d1
ehrpwm3A
gpio1_22
Driver off
0x1798
0x179C
0x17A0
0x17A4
0x17A8
0x17AC
0x17B0
0x17B4
0x17B8
0x17BC
0x17C0
0x17C4
0x17C8
0x17CC
0x17D0
0x17D4
0x17E0
0x17E4
0x17E8
0x17EC
0x17F0
0x17F4
0x17F8
CTRL_CORE_PAD_ AD6
MMC3_DAT5
mmc3_dat5
mmc3_dat6
mmc3_dat7
spi1_sclk
spi1_d1
spi4_d1
spi4_d0
spi4_cs0
uart10_txd
uart10_ctsn
uart10_rtsn
vin1a_d0
ehrpwm3B
gpio1_23
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD_ AB8
MMC3_DAT6
vin1a_hsync0 ehrpwm3_trip gpio1_24
zone_input
CTRL_CORE_PAD_ AB5
MMC3_DAT7
vin1a_vsync0 eCAP3_in_P gpio1_25
WM3_out
CTRL_CORE_PAD_S A25
PI1_SCLK
gpio7_7
CTRL_CORE_PAD_S F16
PI1_D1
gpio7_8
CTRL_CORE_PAD_S B25
PI1_D0
spi1_d0
gpio7_9
CTRL_CORE_PAD_S A24
PI1_CS0
spi1_cs0
spi1_cs1
spi1_cs2
spi1_cs3
spi2_sclk
spi2_d1
gpio7_10
gpio7_11
gpio7_12
gpio7_13
gpio7_14
gpio7_15
gpio7_16
gpio7_17
gpio1_14
gpio1_15
gpio7_22
gpio7_23
gpio7_24
gpio7_25
gpio7_26
gpio7_27
gpio1_16
CTRL_CORE_PAD_S A22
PI1_CS1
sata1_led
spi2_cs1
CTRL_CORE_PAD_S B21
PI1_CS2
uart4_rxd
uart4_txd
uart3_rxd
uart3_txd
uart3_ctsn
uart3_rtsn
mmc3_sdcd
spi2_cs2
dcan2_tx
dcan2_rx
mdio_mclk
mdio_d
hdmi1_hpd
hdmi1_cec
CTRL_CORE_PAD_S B20
PI1_CS3
mmc3_sdwp spi2_cs3
CTRL_CORE_PAD_S A26
PI2_SCLK
CTRL_CORE_PAD_S B22
PI2_D1
CTRL_CORE_PAD_S G17
PI2_D0
spi2_d0
uart5_rxd
uart5_txd
CTRL_CORE_PAD_S B24
PI2_CS0
spi2_cs0
dcan1_tx
dcan1_rx
uart1_rxd
uart1_txd
uart1_ctsn
uart1_rtsn
uart2_rxd
uart2_txd
uart2_ctsn
CTRL_CORE_PAD_D G20
CAN1_TX
uart8_rxd
uart8_txd
mmc2_sdcd
hdmi1_hpd
hdmi1_cec
CTRL_CORE_PAD_D G19
CAN1_RX
mmc2_sdwp sata1_led
mmc4_sdcd
CTRL_CORE_PAD_U B27
ART1_RXD
CTRL_CORE_PAD_U C26
ART1_TXD
mmc4_sdwp
CTRL_CORE_PAD_U E25
ART1_CTSN
uart9_rxd
uart9_txd
uart3_rctx
uart3_sd
uart3_rxd
mmc4_clk
CTRL_CORE_PAD_U C27
ART1_RTSN
mmc4_cmd
CTRL_CORE_PAD_U D28
ART2_RXD
uart3_ctsn
uart3_rtsn
mmc4_dat0
mmc4_dat1
mmc4_dat2
uart2_rxd
uart2_txd
uart10_rxd
uart1_dcdn
uart1_dsrn
uart1_dtrn
CTRL_CORE_PAD_U D26
ART2_TXD
CTRL_CORE_PAD_U D27
ART2_CTSN
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表 4-3. Multiplexing Characteristics (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS
REGISTER NAME
0
1
2
3*
4*
5*
6*
7
8*
9
10
14*
15
0x17FC
CTRL_CORE_PAD_U C28
ART2_RTSN
uart2_rtsn
uart3_txd
uart3_irtx
mmc4_dat3
uart10_txd
uart1_rin
gpio1_17
Driver off
0x1800
0x1804
0x1808
0x180C
0x1818
0x1824
0x1828
0x182C
0x1830
0x1834
0x1838
0x183C
0x1840
0x1844
0x1848
0x184C
0x185C
0x1860
0x1864
CTRL_CORE_PAD_I C21
2C1_SDA
i2c1_sda
i2c1_scl
i2c2_sda
i2c2_scl
Wakeup0
Wakeup3
on_off
rtc_porz
tms
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD_I C20
2C1_SCL
CTRL_CORE_PAD_I C25
2C2_SDA
hdmi1_ddc_sc
l
CTRL_CORE_PAD_I F17
2C2_SCL
hdmi1_ddc_sd
a
CTRL_CORE_PAD_ AD17
WAKEUP0
dcan1_rx
gpio1_0
sys_nirq2
CTRL_CORE_PAD_ AC16
WAKEUP3
sys_nirq1
gpio1_3
dcan2_rx
CTRL_CORE_PAD_ Y11
ON_OFF
CTRL_CORE_PAD_R AB17
TC_PORZ
CTRL_CORE_PAD_T F18
MS
CTRL_CORE_PAD_T D23
DI
tdi
gpio8_27
gpio8_28
CTRL_CORE_PAD_T F19
DO
tdo
CTRL_CORE_PAD_T E20
CLK
tclk
CTRL_CORE_PAD_T D20
RSTN
trstn
CTRL_CORE_PAD_R E18
TCK
rtck
gpio8_29
gpio8_30
gpio8_31
CTRL_CORE_PAD_E G21
MU0
emu0
CTRL_CORE_PAD_E D24
MU1
emu1
CTRL_CORE_PAD_R E23
ESETN
resetn
nmin_dsp
rstoutn
CTRL_CORE_PAD_N D21
MIN_DSP
CTRL_CORE_PAD_R F23
STOUTN
1. NA in table stands for Not Applicable.
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4.4 Signal Descriptions
Many signals are available on multiple pins, according to the software configuration of the pin multiplexing
options.
1. SIGNAL NAME: The name of the signal passing through the pin.
注
The subsystem multiplexing signals are not described in 表 4-2 and 表 4-3.
2. DESCRIPTION: Description of the signal
3. TYPE: Signal direction and type:
–
–
–
–
–
–
–
–
I = Input
O = Output
IO = Input or output
D = Open Drain
DS = Differential
A = Analog
PWR = Power
GND = Ground
4. BALL: Associated ball(s) bottom
注
For more information, see the Control Module / Control Module Register Manual section of
the device TRM.
4.4.1 Video Input Ports (VIP)
注
For more information, see the Video Input Port (VIP) section of the device TRM.
CAUTION
The I/O timings provided in 节 7, Timing Requirements and Switching
Characteristics are valid only for VIN1 and VIN2 if signals within a single IOSET
are used. The IOSETs are defined in 表 7-4 and 表 7-5.
表 4-4. VIP Signal Descriptions
SIGNAL NAME
Video Input 1
vin1a_clk0
DESCRIPTION
TYPE
BALL
Video Input 1 Port A Clock input.Input clock for 8-bit 16-bit or 24-bit Port A video
capture. Input data is sampled on the CLK0 edge.
I
I
I
I
I
I
AC5 / B11 / E17 /
P1 / P4 / B26
vin1a_d0
vin1a_d1
vin1a_d2
vin1a_d3
vin1a_d4
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
AD6 / B7 / C17 /
D18 / M6 / R6 / B14
AC8 / B19 / B8 / M2
/ T9 / J14
A7 / AC3 / F15 / L5 /
T6 / G13
A8 / AC9 / B18 / M1
/ T7 / J11
A16 / AC6 / C9 / L6 /
P6 / E12
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BALL
表 4-4. VIP Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
vin1a_d5
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
I
A9 / AC7 / C15 / L4 /
R9 / F13
vin1a_d6
vin1a_d7
vin1a_d8
vin1a_d9
vin1a_d10
vin1a_d11
vin1a_d12
vin1a_d13
vin1a_d14
vin1a_d15
I
I
I
I
I
I
I
I
I
I
A18 / AC4 / B9 / L3 /
R5 / C12
A10 / A19 / AD4 / L2
/ P5 / D12
AA4 / E8 / F14 / L1 /
U2 / E15
AB3 / D9 / G14 / K2
/ U1 / A20
A13 / AB9 / D7 / J1 /
P3 / B15
AA3 / D8 / E14 / J2 /
R2 / A15
A12 / A5 / D17 / H1 /
K7 / D15
B13 / C6 / G16 / J3 /
M7 / B16
A11 / A21 / C8 / H2 /
J5 / B17
B12 / C18 / C7 / H3
/ K6 / A17
vin1a_d16
vin1a_d17
vin1a_d18
vin1a_d19
vin1a_d20
vin1a_d21
vin1a_d22
vin1a_d23
vin1a_de0
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Field ID input
I
I
I
I
I
I
I
I
I
F11 / R6 / C18
G10 / T9 / A21
F10 / T6 / G16
G11 / T7 / D17
E9 / P6 / AA3
F9 / R9 / AB9
F8 / R5 / AB3
E7 / P5 / AA4
AB4 / B10 / D14 /
N9 / H6 / C23 / P7
vin1a_fld0
vin1a_hsync0
vin1a_vsync0
Video Input 1 Port A Field ID input
I
I
I
C14 / C17 / D11 /
P9 / J7 / F21
Video Input 1 Port A Horizontal Sync input
Video Input 1 Port A Vertical Sync input
AB8 / C11 / F12 /
N7 / R3 / P7 / E21
AB5 / E11 / G12 /
R4 / T2 / N1 / F20
vin1b_clk1
vin1b_d0
Video Input 1 Port B Clock input
Video Input 1 Port B Data input
Video Input 1 Port B Data input
Video Input 1 Port B Data input
Video Input 1 Port B Data input
Video Input 1 Port B Data input
Video Input 1 Port B Data input
Video Input 1 Port B Data input
Video Input 1 Port B Data input
Video Input 1 Port B Field ID input
Video Input 1 Port B Field ID input
Video Input 1 Port B Horizontal Sync input
Video Input 1 Port B Vertical Sync input
I
I
I
I
I
I
I
I
I
I
I
I
I
N9 / V1 / M4 / P7
R6 / U4 / K7
T9 / V2 / M7
T6 / Y1 / J5
T7 / W9 / K6
P6 / V9 / J7
R9 / U5 / J4
R5 / V5 / J6
P5 / V4 / H4
P9 / V7 / N6
P4 / W2 / M4
N7 / U7 / H5
R4 / V6 / H6
vin1b_d1
vin1b_d2
vin1b_d3
vin1b_d4
vin1b_d5
vin1b_d6
vin1b_d7
vin1b_de1
vin1b_fld1
vin1b_hsync1
vin1b_vsync1
Video Input 2
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表 4-4. VIP Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
vin2a_clk0
Video Input 2 Port A Clock input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
I
B11 / B26 / E1 / P4 /
V1
vin2a_d0
vin2a_d1
vin2a_d2
vin2a_d3
vin2a_d4
vin2a_d5
vin2a_d6
vin2a_d7
vin2a_d8
vin2a_d9
vin2a_d10
vin2a_d11
I
I
I
I
I
I
I
I
I
I
I
I
B14 / B7 / F2 / R6 /
U4
B8 / F3 / J14 / T9 /
V2
A7 / D1 / G13 / T6 /
Y1
A8 / E2 / J11 / T7 /
W9
C9 / D2 / E12 / P6 /
V9
A9 / F13 / F4 / R9 /
U5
B9 / C1 / C12 / R5 /
V5
A10 / D12 / E4 / P5 /
V4
E15 / E8 / F5 / U2 /
V3
A20 / D9 / E6 / U1 /
Y2
B15 / D3 / D7 / P3 /
U6
A15 / D8 / F6 / R2 /
U3
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
vin2a_d16
vin2a_d17
vin2a_d18
vin2a_d19
vin2a_d20
vin2a_d21
vin2a_d22
vin2a_d23
vin2a_de0
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Field ID input
I
I
I
I
I
I
I
I
I
I
I
I
I
A5 / D15 / D5 / K7
B16 / C2 / C6 / M7
B17 / C3 / C8 / J5
A17 / C4 / C7 / K6
B2 / C18 / F11
A21 / D6 / G10
C5 / F10 / G16
A3 / D17 / G11
AA3 / B3 / E9
AB9 / B4 / F9
AB3 / B5 / F8
A4 / AA4 / E7
B10 / C23 / G2 / H6
/ P7 / V7
vin2a_fld0
vin2a_hsync0
vin2a_vsync0
Video Input 2 Port A Field ID input
I
I
I
D11 / F21 / G2 / H7
/ J7 / P9 / W2
Video Input 2 Port A Horizontal Sync input
Video Input 2 Port A Vertical Sync input
C11 / E21 / G1 / P7
/ R3 / U7
E11 / F20 / G6 / N1 /
T2 / V6
vin2b_clk1
vin2b_d0
vin2b_d1
vin2b_d2
vin2b_d3
vin2b_d4
vin2b_d5
Video Input 2 Port B Clock input
Video Input 2 Port B Data input
Video Input 2 Port B Data input
Video Input 2 Port B Data input
Video Input 2 Port B Data input
Video Input 2 Port B Data input
Video Input 2 Port B Data input
I
I
I
I
I
I
I
AB5 / H7 / M4 / P7
A4 / AD6 / K7
AC8 / B5 / M7
AC3 / B4 / J5
AC9 / B3 / K6
A3 / AC6 / J7
AC7 / C5 / J4
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表 4-4. VIP Signal Descriptions (continued)
SIGNAL NAME
vin2b_d6
DESCRIPTION
TYPE
BALL
Video Input 2 Port B Data input
I
I
I
I
I
I
AC4 / D6 / J6
AD4 / B2 / H4
AB8 / G2 / N6
G2 / M4
vin2b_d7
Video Input 2 Port B Data input
vin2b_de1
Video Input 2 Port B Field ID input
Video Input 2 Port B Field ID input
Video Input 2 Port B Horizontal Sync input
Video Input 2 Port B Vertical Sync input
vin2b_fld1
vin2b_hsync1
vin2b_vsync1
AC5 / G1 / H5
AB4 / G6 / H6
4.4.2 Display Subsystem – Video Output Ports
CAUTION
The I/O timings provided in 节 7, Timing Requirements and Switching
Characteristics are valid only if signals within a single IOSET are used. The
IOSETs are defined in表 7-18.
表 4-5. DSS Signal Descriptions
SIGNAL NAME
DPI Video Output 1
vout1_clk
DESCRIPTION
TYPE
BALL
Video Output 1 Clock output
O
O
O
O
D11
B10
B11
C11
vout1_de
Video Output 1 Data Enable output
vout1_fld
Video Output 1 Field ID output.This signal is not used for embedded sync modes.
vout1_hsync
Video Output 1 Horizontal Sync output.This signal is not used for embedded sync
modes.
vout1_vsync
vout1_d0
vout1_d1
vout1_d2
vout1_d3
vout1_d4
vout1_d5
vout1_d6
vout1_d7
vout1_d8
vout1_d9
vout1_d10
vout1_d11
vout1_d12
vout1_d13
vout1_d14
vout1_d15
vout1_d16
vout1_d17
vout1_d18
vout1_d19
vout1_d20
vout1_d21
vout1_d22
Video Output 1 Vertical Sync output.This signal is not used for embedded sync modes.
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
Video Output 1 Data output
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
E11
F11
G10
F10
G11
E9
F9
F8
E7
E8
D9
D7
D8
A5
C6
C8
C7
B7
B8
A7
A8
C9
A9
B9
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表 4-5. DSS Signal Descriptions (continued)
SIGNAL NAME
vout1_d23
DESCRIPTION
TYPE
BALL
Video Output 1 Data output
O
A10
DPI Video Output 2
vout2_clk
Video Output 2 Clock output
O
O
O
O
H7 / B26
G2 / C23
E1 / F21
G1 / E21
vout2_de
Video Output 2 Data Enable output
vout2_fld
Video Output 2 Field ID output.This signal is not used for embedded sync modes.
vout2_hsync
Video Output 2 Horizontal Sync output.This signal is not used for embedded sync
modes.
vout2_vsync
vout2_d0
Video Output 2 Vertical Sync output.This signal is not used for embedded sync modes.
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
G6 / F20
A4 / B14
B5 / J14
B4 / G13
B3 / J11
A3 / E12
C5 / F13
D6 / C12
B2 / D12
C4 / E15
C3 / A20
C2 / B15
D5 / A15
F6 / D15
D3 / B16
E6 / B17
F5 / A17
E4 / C18
C1 / A21
F4 / G16
D2 / D17
E2 / AA3
D1 / AB9
F3 / AB3
F2 / AA4
vout2_d1
vout2_d2
vout2_d3
vout2_d4
vout2_d5
vout2_d6
vout2_d7
vout2_d8
vout2_d9
vout2_d10
vout2_d11
vout2_d12
vout2_d13
vout2_d14
vout2_d15
vout2_d16
vout2_d17
vout2_d18
vout2_d19
vout2_d20
vout2_d21
vout2_d22
vout2_d23
DPI Video Output 3
vout3_clk
vout3_d0
Video Output 3 Clock output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
P1
M6
M2
L5
M1
L6
L4
L3
L2
L1
K2
J1
vout3_d1
vout3_d2
vout3_d3
vout3_d4
vout3_d5
vout3_d6
vout3_d7
vout3_d8
vout3_d9
vout3_d10
vout3_d11
vout3_d12
vout3_d13
J2
H1
J3
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表 4-5. DSS Signal Descriptions (continued)
SIGNAL NAME
vout3_d14
vout3_d15
vout3_d16
vout3_d17
vout3_d18
vout3_d19
vout3_d20
vout3_d21
vout3_d22
vout3_d23
vout3_de
DESCRIPTION
TYPE
O
BALL
H2
H3
R6
T9
Video Output 3 Data output
Video Output 3 Data output
O
Video Output 3 Data output
O
Video Output 3 Data output
O
Video Output 3 Data output
O
T6
Video Output 3 Data output
O
T7
Video Output 3 Data output
O
P6
R9
R5
P5
N9
P9
N7
Video Output 3 Data output
O
Video Output 3 Data output
O
Video Output 3 Data output
O
Video Output 3 Data Enable output
Video Output 3 Field ID output.This signal is not used for embedded sync modes.
O
vout3_fld
O
vout3_hsync
Video Output 3 Horizontal Sync output.This signal is not used for embedded sync
modes.
O
vout3_vsync
Video Output 3 Vertical Sync output.This signal is not used for embedded sync modes.
O
R4
4.4.3 Display Subsystem – High-Definition Multimedia Interface (HDMI)
注
For more information, see the Display Subsystem / Display Subsystem Overview of the
device TRM.
表 4-6. HDMI Signal Descriptions
SIGNAL NAME
hdmi1_cec
DESCRIPTION
TYPE
IOD
BALL
B20/ G19
B21/ G20
C25
HDMI consumer electronic control
hdmi1_hpd
HDMI display hot plug detect
IOD
hdmi1_ddc_scl
hdmi1_ddc_sda
hdmi1_clockx
hdmi1_clocky
hdmi1_data2x
hdmi1_data2y
hdmi1_data1x
hdmi1_data1y
hdmi1_data0x
hdmi1_data0y
HDMI display data channel clock
IOD
HDMI display data channel data
IOD
F17
HDMI clock differential positive or negative
HDMI clock differential positive or negative
HDMI data 2 differential positive or negative
HDMI data 2 differential positive or negative
HDMI data 1 differential positive or negative
HDMI data 1 differential positive or negative
HDMI data 0 differential positive or negative
HDMI data 0 differential positive or negative
ODS
ODS
ODS
ODS
ODS
ODS
ODS
ODS
AG16
AH16
AG19
AH19
AG18
AH18
AG17
AH17
4.4.4 Camera Serial Interface 2 CAL bridge (CSI2)
注
For more information, see the CAL Subsystem / CAL Subsystem Overview of the device
TRM.
表 4-7. CSI 2 Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
csi2_0_dx0
Serial data/clock input - line 0 (position 1)
I
AE1
90
Terminal Configuration and Functions
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表 4-7. CSI 2 Signal Descriptions (continued)
SIGNAL NAME
csi2_0_dy0
csi2_0_dx1
csi2_0_dy1
csi2_0_dx2
csi2_0_dy2
csi2_0_dx3
csi2_0_dy3
csi2_0_dx4
csi2_0_dy4
csi2_1_dx0
csi2_1_dy0
csi2_1_dx1
csi2_1_dy1
csi2_1_dx2
csi2_1_dy2
DESCRIPTION
TYPE
BALL
AD2
AF1
AE2
AF2
AF3
AH4
AG4
AH3
AG3
AG5
AH5
AG6
AH6
AH7
AG7
Serial data/clock input - line 0 (position 1)
Serial data/clock input - line 1 (position 2)
Serial data/clock input - line 1 (position 2)
Serial data/clock input - line 2 (position 3)
Serial data/clock input - line 2 (position 3)
Serial data/clock input - line 3 (position 4)
Serial data/clock input - line 3 (position 4)
Serial data input only - line 4 (position 5) (1)
Serial data input only - line 4 (position 5) (1)
Serial data/clock input - line 0 (position 1)
Serial data/clock input - line 0 (position 1)
Serial data/clock input - line 1 (position 2)
Serial data/clock input - line 1 (position 2)
Serial data/clock input - line 2 (position 3)
Serial data/clock input - line 2 (position 3)
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
(1) Line 4 (position 5) supports only data. For more information see CAL Subsystem of the device TRM.
4.4.5 External Memory Interface (EMIF SDRAM)
注
For more information, see the Memory Subsystem / EMIF Controller section of the device
TRM.
注
Dual rank support is not available on this device, but signal names are retained for
consistency with the TDA2xx family of devices.
注
The index number 1 which is part of the EMIF1 signal prefixes (ddr1_*) listed in 表 4-8, EMIF
SDRAM Signal Descriptions, column "SIGNAL NAME" not to be confused with DDR1 type of
SDRAM memories.
表 4-8. EMIF SDRAM Signal Descriptions
SIGNAL NAME DESCRIPTION
EMIF SDRAM Channel 1
TYPE
BALL
ddr1_csn0
ddr1_csn1
ddr1_cke
ddr1_ck
EMIF1 Chip Select 0
O
O
O
O
O
O
O
O
O
O
O
AH23
AB16
AG22
AG24
AH24
AE20
AC17
AC18
AF20
AH21
AG21
EMIF1 Chip Select 1
EMIF1 Clock Enable
EMIF1 Clock
ddr1_nck
ddr1_odt0
ddr1_odt1
ddr1_casn
ddr1_rasn
ddr1_wen
ddr1_rst
EMIF1 Negative Clock
EMIF1 On-Die Termination for Chip Select 0
EMIF1 On-Die Termination for Chip Select 1
EMIF1 Column Address Strobe
EMIF1 Row Address Strobe
EMIF1 Write Enable
EMIF1 Reset output (DDR3-SDRAM only)
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表 4-8. EMIF SDRAM Signal Descriptions (continued)
SIGNAL NAME DESCRIPTION
EMIF1 Bank Address
TYPE
O
BALL
AF17
AE18
AB18
AD20
AC19
AC20
AB19
AF21
AH22
AG23
AE21
AF22
AE22
AD21
AD22
AC21
AF18
AE17
AD18
AF25
AF26
AG26
AH26
AF24
AE24
AF23
AE23
AC23
AF27
AG27
AF28
AE26
AC25
AC24
AD25
V20
ddr1_ba0
ddr1_ba1
ddr1_ba2
ddr1_a0
ddr1_a1
ddr1_a2
ddr1_a3
ddr1_a4
ddr1_a5
ddr1_a6
ddr1_a7
ddr1_a8
ddr1_a9
ddr1_a10
ddr1_a11
ddr1_a12
ddr1_a13
ddr1_a14
ddr1_a15
ddr1_d0
ddr1_d1
ddr1_d2
ddr1_d3
ddr1_d4
ddr1_d5
ddr1_d6
ddr1_d7
ddr1_d8
ddr1_d9
ddr1_d10
ddr1_d11
ddr1_d12
ddr1_d13
ddr1_d14
ddr1_d15
ddr1_d16
ddr1_d17
ddr1_d18
ddr1_d19
ddr1_d20
ddr1_d21
ddr1_d22
ddr1_d23
ddr1_d24
ddr1_d25
ddr1_d26
ddr1_d27
EMIF1 Bank Address
EMIF1 Bank Address
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
W20
AB28
AC28
AC27
Y19
AB27
Y20
AA23
Y22
Y23
AA24
92
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表 4-8. EMIF SDRAM Signal Descriptions (continued)
SIGNAL NAME DESCRIPTION
TYPE
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
BALL
Y24
ddr1_d28
ddr1_d29
EMIF1 Data Bus
EMIF1 Data Bus
AA26
AA25
AA28
W22
V23
ddr1_d30
EMIF1 Data Bus
ddr1_d31
EMIF1 Data Bus
ddr1_ecc_d0
ddr1_ecc_d1
ddr1_ecc_d2
ddr1_ecc_d3
ddr1_ecc_d4
ddr1_ecc_d5
ddr1_ecc_d6
ddr1_ecc_d7
ddr1_dqm0
ddr1_dqm1
ddr1_dqm2
ddr1_dqm3
ddr1_dqm_ecc
ddr1_dqs0
EMIF1 ECC Data Bus
EMIF1 ECC Data Bus
EMIF1 ECC Data Bus
EMIF1 ECC Data Bus
EMIF1 ECC Data Bus
EMIF1 ECC Data Bus
EMIF1 ECC Data Bus
EMIF1 ECC Data Bus
EMIF1 Data Mask
W19
W23
Y25
V24
V25
Y26
AD23
AB23
AC26
AA27
V26
EMIF1 Data Mask
O
EMIF1 Data Mask
O
EMIF1 Data Mask
O
EMIF1 ECC Data Mask
O
Data strobe 0 input/output for byte 0 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
IO
AH25
ddr1_dqsn0
ddr1_dqs1
Data strobe 0 invert
IO
IO
AG25
AE27
Data strobe 1 input/output for byte 1 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
ddr1_dqsn1
ddr1_dqs2
Data strobe 1 invert
IO
IO
AE28
AD27
Data strobe 2 input/output for byte 2 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
ddr1_dqsn2
ddr1_dqs3
Data strobe 2 invert
IO
IO
AD28
Y28
Data strobe 3 input/output for byte 3 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
ddr1_dqsn3
Data strobe 3 invert
IO
IO
Y27
V27
ddr1_dqs_ecc
EMIF1 ECC Data strobe input/output. This signal is output to the EMIF1 memory when
writing and input when reading.
ddr1_dqsn_ecc EMIF1 ECC Complementary Data strobe
ddr1_vref0 Reference Power Supply EMIF1
IO
A
V28
Y18
4.4.6 General-Purpose Memory Controller (GPMC)
注
For more information, see the Memory Subsystem / General-Purpose Memory Controller
section of the device TRM.
表 4-9. GPMC Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
gpmc_ad0
GPMC Data 0 in A/D nonmultiplexed mode and additionally Address 1
in A/D multiplexed mode
IO
M6
M2
L5
gpmc_ad1
gpmc_ad2
gpmc_ad3
GPMC Data 1 in A/D nonmultiplexed mode and additionally Address 2
in A/D multiplexed mode
IO
IO
IO
GPMC Data 2 in A/D nonmultiplexed mode and additionally Address 3
in A/D multiplexed mode
GPMC Data 3 in A/D nonmultiplexed mode and additionally Address 4
in A/D multiplexed mode
M1
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表 4-9. GPMC Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
gpmc_ad4
GPMC Data 4 in A/D nonmultiplexed mode and additionally Address 5
in A/D multiplexed mode
IO
L6
gpmc_ad5
gpmc_ad6
gpmc_ad7
gpmc_ad8
gpmc_ad9
gpmc_ad10
gpmc_ad11
gpmc_ad12
gpmc_ad13
gpmc_ad14
gpmc_ad15
gpmc_a0
GPMC Data 5 in A/D nonmultiplexed mode and additionally Address 6
in A/D multiplexed mode
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
L4
GPMC Data 6 in A/D nonmultiplexed mode and additionally Address 7
in A/D multiplexed mode
L3
GPMC Data 7 in A/D nonmultiplexed mode and additionally Address 8
in A/D multiplexed mode
L2
GPMC Data 8 in A/D nonmultiplexed mode and additionally Address 9
in A/D multiplexed mode
L1
GPMC Data 9 in A/D nonmultiplexed mode and additionally Address 10
in A/D multiplexed mode
K2
GPMC Data 10 in A/D nonmultiplexed mode and additionally Address
11 in A/D multiplexed mode
J1
GPMC Data 11 in A/D nonmultiplexed mode and additionally Address
12 in A/D multiplexed mode
J2
GPMC Data 12 in A/D nonmultiplexed mode and additionally Address
13 in A/D multiplexed mode
H1
J3
GPMC Data 13 in A/D nonmultiplexed mode and additionally Address
14 in A/D multiplexed mode
GPMC Data 14 in A/D nonmultiplexed mode and additionally Address
15 in A/D multiplexed mode
H2
GPMC Data 15 in A/D nonmultiplexed mode and additionally Address
16 in A/D multiplexed mode
H3
GPMC Address 0. Only used to effectively address 8-bit data
nonmultiplexed memories
R6 / P4
T9 / P1
T6 / N1
T7 / M4
P6
gpmc_a1
GPMC address 1 in A/D nonmultiplexed mode and Address 17 in A/D
multiplexed mode
O
gpmc_a2
GPMC address 2 in A/D nonmultiplexed mode and Address 18 in A/D
multiplexed mode
O
gpmc_a3
GPMC address 3 in A/D nonmultiplexed mode and Address 19 in A/D
multiplexed mode
O
gpmc_a4
GPMC address 4 in A/D nonmultiplexed mode and Address 20 in A/D
multiplexed mode
O
gpmc_a5
GPMC address 5 in A/D nonmultiplexed mode and Address 21 in A/D
multiplexed mode
O
R9
gpmc_a6
GPMC address 6 in A/D nonmultiplexed mode and Address 22 in A/D
multiplexed mode
O
R5
gpmc_a7
GPMC address 7 in A/D nonmultiplexed mode and Address 23 in A/D
multiplexed mode
O
P5
gpmc_a8
GPMC address 8 in A/D nonmultiplexed mode and Address 24 in A/D
multiplexed mode
O
N7
gpmc_a9
GPMC address 9 in A/D nonmultiplexed mode and Address 25 in A/D
multiplexed mode
O
R4
gpmc_a10
gpmc_a11
gpmc_a12
gpmc_a13
gpmc_a14
gpmc_a15
GPMC address 10 in A/D nonmultiplexed mode and Address 26 in A/D
multiplexed mode
O
N9
GPMC address 11 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
P9
GPMC address 12 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
P4
GPMC address 13 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
R3 / K7 / P2
T2 / M7 / P1
U2 / J5 / N2
GPMC address 14 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
GPMC address 15 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
94
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表 4-9. GPMC Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
gpmc_a16
gpmc_a17
gpmc_a18
gpmc_a19
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
gpmc_a25
gpmc_a26
gpmc_a27
GPMC address 16 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
U1 / K6 / R6
GPMC address 17 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
O
O
O
O
O
O
O
O
O
O
P3 / J7 / E1
R2 / J4 / H7
K7(3) / J6
GPMC address 18 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 19 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 20 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
M7(3) / H4
GPMC address 21 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
J5(3) / H5
GPMC address 22 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
K6(3) / H6
GPMC address 23 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
F6 / J7 / N1 / P2
D3 / J4(3) / P1
E6 / J6(3) / N2
F5 / H4(3) / R6
G1 / H5(3) / E1 / H7
GPMC address 24 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 25 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 26 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 27 in A/D nonmultiplexed mode and Address 27 in A/D
multiplexed mode
gpmc_cs0
gpmc_cs1
GPMC Chip Select 0 (active low)
GPMC Chip Select 1 (active low)
GPMC Chip Select 2 (active low)
GPMC Chip Select 3 (active low)
GPMC Chip Select 4 (active low)
GPMC Chip Select 5 (active low)
GPMC Chip Select 6 (active low)
GPMC Chip Select 7 (active low)
GPMC Clock output
O
O
O
O
O
O
O
O
IO
O
O
O
O
O
I
T1
H6
gpmc_cs2
P2
gpmc_cs3
P1
gpmc_cs4
N6
gpmc_cs5
M4
N1
gpmc_cs6
gpmc_cs7
P7
gpmc_clk(1)(2)
gpmc_advn_ale
gpmc_oen_ren
gpmc_wen
gpmc_ben0
gpmc_ben1
gpmc_wait0
gpmc_wait1
P7
GPMC address valid active low or address latch enable
GPMC output enable active low or read enable
GPMC write enable active low
N1
M5
M3
N6
GPMC lower-byte enable active low
GPMC upper-byte enable active low
GPMC external indication of wait 0
GPMC external indication of wait 1
M4
N2
I
P7 / N1
(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the
clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS
.
(2) The gpio6_16.clkout1 signal can be used as an “always-on” alternative to gpmc_clk provided that the external device can support the
associated timing. See 表 7-25 GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Default and 表 7-27
GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Alternate for timing information.
(3) The internal pull resistors for balls K7, M7, J5, K6, J4, J6, H4, H5 are permanently disabled when sysboot15 is set to 0 as described in
the section Sysboot Configuration of the Device TRM. If internal pull-up/down resistors are desired on these balls then sysboot15 should
be set to 1. If gpmc boot mode is used with SYSBOOT15=0 (not recommended) then external pull-downs should be implemented to
keep the address bus at logic-1 value during boot since the gpmc ms-address bits are high-z during boot.
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4.4.7 Timers
注
For more information, see the Timers section of the device TRM.
表 4-10. Timers Signal Descriptions
SIGNAL NAME
timer1
DESCRIPTION
TYPE
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
BALL
M4 / E21
N6 / F20
N1 / F21
P7 / D12
U2 / B12
T2 / A11
R3 / B13
P4 / A12
P9 / E14
N9 / A13
R4 / G14
N7 / F14
D18
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
timer2
timer3
timer4
timer5
timer6
timer7
timer8
timer9
timer10
timer11
timer12
timer13
timer14
timer15
timer16
E17
AC10 / B26
AB10 / C23
4.4.8 Inter-Integrated Circuit Interface (I2C)
注
For more information, see the Serial Communication Interface / Multimaster High-Speed I2C
Controller / HS I2C Environment / HS I2C in I2C Mode section of the device TRM.
注
I2C1 and I2C2 do NOT support HS-mode.
表 4-11. I2C Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
Inter-Integrated Circuit Interface 1 (I2C1)
i2c1_scl
I2C1 Clock
I2C1 Data
IOD
IOD
C20
C21
i2c1_sda
Inter-Integrated Circuit Interface 2 (I2C2)
i2c2_scl
I2C2 Clock
I2C2 Data
IOD
IOD
F17
C25
i2c2_sda
Inter-Integrated Circuit Interface 3 (I2C3)
i2c3_scl
I2C3 Clock
I2C3 Data
IOD
IOD
P7/ D14/ AB4/ F20
N1/ C14/ AC5/ E21
i2c3_sda
Inter-Integrated Circuit Interface 4 (I2C4)
i2c4_scl
I2C4 Clock
I2C4 Data
IOD
IOD
R6/ J14/ A21/ Y9
T9/ B14/ C18/ W7
i2c4_sda
96
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表 4-11. I2C Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
Inter-Integrated Circuit Interface 5 (I2C5)
i2c5_scl
I2C5 Clock
I2C5 Data
IOD
IOD
AB9/ P6/ F12
AA3/ R9/ G12
i2c5_sda
Inter-Integrated Circuit Interface 6 (I2C6)
i2c6_scl
I2C6 Clock
I2C6 Data
IOD
IOD
G16
D17
i2c6_sda
4.4.9 Universal Asynchronous Receiver Transmitter (UART)
注
For more information about UART booting, see the Initialization / Device Initialization by
ROM Code / Perypheral Booting / Initialization Phase for UART Boot section of the device
TRM.
表 4-12. UART Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
Universal Asynchronous Receiver/Transmitter 1 (UART1)
uart1_dcdn
uart1_dsrn
uart1_dtrn
uart1_rin
UART1 Data Carrier Detect active low
UART1 Data Set Ready Active Low
UART1 Data Terminal Ready Active Low
UART1 Ring Indicator
I
I
D28
D26
D27
C28
B27
C26
E25
C27
O
I
uart1_rxd
uart1_txd
uart1_ctsn
uart1_rtsn
UART1 Receive Data
I
UART1 Transmit Data
O
I
UART1 clear to send active low
UART1 request to send active low
O
Universal Asynchronous Receiver/Transmitter 2 (UART2)
uart2_rxd
uart2_txd
uart2_ctsn
uart2_rtsn
UART2 Receive Data
I
D28
D26
D27
C28
UART2 Transmit Data
O
I
UART2 clear to send active low
UART2 request to send active low
O
Universal Asynchronous Receiver/Transmitter 3 (UART3)/IrDA
uart3_rxd
uart3_txd
uart3_ctsn
uart3_rtsn
uart3_rctx
uart3_sd
UART3 Receive Data
I
V2/ AB3/ A26 / D27
Y1/ AA4/ B22/ C28
U4/ W9/ G17/ D28
V1/ V9/ D26/ B24
D28
UART3 Transmit Data
O
I
UART3 clear to send active low
UART3 request to send active low
Remote control data
O
O
O
I
Infrared transceiver configure/shutdown
D26
uart3_irrx
Infrared data input. Also functions as uart3_rxd Receive Data Input when IrDA
mode is not used.
D27
uart3_irtx
Infrared data output
O
C28
Universal Asynchronous Receiver/Transmitter 4 (UART4)
uart4_rxd
uart4_txd
uart4_ctsn
uart4_rtsn
UART4 Receive Data
I
V7/ G16/ B21
UART4 Transmit Data
O
I
U7/ D17/ B20
UART4 clear to send active low
UART4 request to send active low
V6
U6
O
Universal Asynchronous Receiver/Transmitter 5 (UART5)
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BALL
表 4-12. UART Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
uart5_rxd
UART5 Receive Data
I
R6/ F11/ B19/ AC7/
G17
uart5_txd
UART5 Transmit Data
O
T9/ G10/ C17/ AC6/
B24
uart5_ctsn
uart5_rtsn
UART5 clear to send active low
UART5 request to send active low
I
T6 / AC9
T7 / AC3
O
Universal Asynchronous Receiver/Transmitter 6 (UART6)
uart6_rxd
uart6_txd
uart6_ctsn
uart6_rtsn
UART6 Receive Data
I
P6/ E8/ G12/ W7
R9/ D9/ F12/ Y9
R5 / G13
UART6 Transmit Data
O
I
UART6 clear to send active low
UART6 request to send active low
O
P5 / J11
Universal Asynchronous Receiver/Transmitter 7 (UART7)
uart7_rxd
uart7_txd
uart7_ctsn
uart7_rtsn
UART7 Receive Data
I
B18 / B7 / T6
B8 / F15 / T7
B19
UART7 Transmit Data
O
I
UART7 clear to send active low
UART7 request to send active low
O
C17
Universal Asynchronous Receiver/Transmitter 8 (UART8)
uart8_rxd
uart8_txd
uart8_ctsn
uart8_rtsn
UART8 Receive Data
I
C18 / G20 / R5
A21 / G19 / P5
G16
UART8 Transmit Data
O
I
UART8 clear to send active low
UART8 request to send active low
O
D17
Universal Asynchronous Receiver/Transmitter 9 (UART9)
uart9_rxd
uart9_txd
uart9_ctsn
uart9_rtsn
UART9 Receive Data
I
G1/ AA3/ E25
G6/ AB9/ C27
F2 / AB3
UART9 Transmit Data
O
I
UART9 clear to send active low
UART9 request to send active low
O
F3/ AA4
Universal Asynchronous Receiver/Transmitter 10 (UART10)
uart10_rxd
uart10_txd
uart10_ctsn
uart10_rtsn
UART10 Receive Data
I
D1/ E21/ AC8/ D27
E2/ F20/ AD6/ C28
D2 / AB8
UART10 Transmit Data
O
I
UART10 clear to send active low
UART10 request to send active low
O
F4 / AB5
4.4.10 Multichannel Serial Peripheral Interface (McSPI)
CAUTION
The I/O timings provided in 节 7, Timing Requirements and Switching
Characteristics are applicable for all combinations of signals for SPI1 and SPI2.
However, the timings are valid only for SPI3 and SPI4 if signals within a single
IOSET are used. The IOSETS are defined in 表 7-40.
注
For more information, see the Serial Communication Interface / Multichannel Serial
Peripheral Interface (McSPI) section of the device TRM.
98
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表 4-13. SPI Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
Serial Peripheral Interface 1
spi1_sclk(1)
spi1_d1
SPI1 Clock
SPI1 Data. Can be configured as either MISO or MOSI.
IO
IO
IO
IO
IO
IO
IO
A25
F16
B25
A24
A22
B21
B20
spi1_d0
SPI1 Data. Can be configured as either MISO or MOSI.
SPI1 Chip Select
spi1_cs0
spi1_cs1
spi1_cs2
spi1_cs3
SPI1 Chip Select
SPI1 Chip Select
SPI1 Chip Select
Serial Peripheral Interface 2
spi2_sclk(1)
SPI2 Clock
IO
IO
IO
IO
IO
IO
IO
A26
B22
G17
B24
A22
B21
B20
spi2_d1
SPI2 Data. Can be configured as either MISO or MOSI.
SPI2 Data. Can be configured as either MISO or MOSI.
SPI2 Chip Select
spi2_d0
spi2_cs0
spi2_cs1
spi2_cs2
spi2_cs3
SPI2 Chip Select
SPI2 Chip Select
SPI2 Chip Select
Serial Peripheral Interface 3
spi3_sclk(1)
SPI3 Clock
IO
IO
IO
IO
AC4 / B12 / C18 /
E11 / V2
spi3_d1
SPI3 Data. Can be configured as either MISO or MOSI.
SPI3 Data. Can be configured as either MISO or MOSI.
SPI3 Chip Select
A11 / A21 / AC7 /
B10 / Y1
spi3_d0
AC6 / B13 / C11 /
G16 / W9
spi3_cs0
A12 / AC9 / D11 /
D17 / V9
spi3_cs1
spi3_cs2
spi3_cs3
SPI3 Chip Select
SPI3 Chip Select
SPI3 Chip Select
IO
IO
IO
AC3 / B11 / E14
F11
A10
Serial Peripheral Interface 4
spi4_sclk(1)
SPI4 Clock
IO
IO
IO
IO
N7/ G1/ AA3/ V7/
AC8
spi4_d1
SPI4 Data. Can be configured as either MISO or MOSI.
SPI4 Data. Can be configured as either MISO or MOSI.
SPI4 Chip Select
R4/ G6/ AB9/ U7/
AD6
spi4_d0
N9/ F2/ AB3/ V6/
AB8
spi4_cs0
P9/ F3/ AA4/ U6/
AB5
spi4_cs1
spi4_cs2
spi4_cs3
SPI4 Chip Select
SPI4 Chip Select
SPI4 Chip Select
IO
IO
IO
P4 / Y1
R3 / W9
T2 / V9
(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the
clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS
.
4.4.11 Quad Serial Peripheral Interface (QSPI)
注
For more information about UART booting, see the Initialization / Device Initialization by
ROM Code / Memory Booting / SPI/QSPI Flash Devices section of the device TRM.
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表 4-14. QSPI Signal Descriptions
SIGNAL NAME
qspi1_sclk
DESCRIPTION
TYPE
BALL
R2
QSPI1 Serial Clock
IO
I
qspi1_rtclk
QSPI1 Return Clock Input. Must be connected from QSPI1_SCLK on PCB. Refer
to PCB Guidelines for QSPI1
R3
qspi1_d0
QSPI1 Data[0]. This pin is output data for all commands/writes and for dual read
and quad read modes it becomes input data pin during read phase.
IO
U1
qspi1_d1
qspi1_d2
QSPI1 Data[1]. Input read data in all modes.
IO
IO
P3
U2
QSPI1 Data[2]. This pin is used only in quad read mode as input data pin during
read phase
qspi1_d3
QSPI1 Data[3]. This pin is used only in quad read mode as input data pin during
read phase
IO
T2
qspi1_cs0
qspi1_cs1
qspi1_cs2
qspi1_cs3
QSPI1 Chip Select[0]. This pin is Used for QSPI1 boot modes.
QSPI1 Chip Select[1]
IO
O
O
O
P2
P1
T7
P6
QSPI1 Chip Select[2]
QSPI1 Chip Select[3]
4.4.12 Multichannel Audio Serial Port (McASP)
注
For more information, see the Serial Communication Interface / Multichannel Audio Serial
Port (McASP) section of the device TRM.
表 4-15. McASP Signal Descriptions
SIGNAL NAME
Multichannel Audio Serial Port 1
McASP1 Transmit/Receive Data
DESCRIPTION
TYPE
BALL
mcasp1_axr0
mcasp1_axr1
mcasp1_axr2
mcasp1_axr3
mcasp1_axr4
mcasp1_axr5
mcasp1_axr6
mcasp1_axr7
mcasp1_axr8
mcasp1_axr9
mcasp1_axr10
mcasp1_axr11
mcasp1_axr12
mcasp1_axr13
mcasp1_axr14
mcasp1_axr15
mcasp1_fsx
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
G12
F12
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit Frame Sync
McASP1 Receive Bit Clock
G13
J11
D18/ E12
E17 / F13
B26 / C12
C23 / D12
E21 / B12
F20/ A11
F21 / B13
A12
E14
A13
G14
F14
D14
mcasp1_aclkr(1)
B14
mcasp1_fsr
McASP1 Receive Frame Sync
McASP1 Transmit High-Frequency Master Clock
McASP1 Transmit Bit Clock
J14
mcasp1_ahclkx
mcasp1_aclkx(1)
D18
IO
C14
Multichannel Audio Serial Port 2
mcasp2_axr0
McASP2 Transmit/Receive Data
IO
B15
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表 4-15. McASP Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
BALL
A15
C15
A16
D15
B16
B17
A17
D18
E17
B26
C23
B18
F15
B19
C17
A18
E15
A20
E17
A19
mcasp2_axr1
mcasp2_axr2
mcasp2_axr3
mcasp2_axr4
mcasp2_axr5
mcasp2_axr6
mcasp2_axr7
mcasp2_axr8
mcasp2_axr9
mcasp2_axr10
mcasp2_axr11
mcasp2_axr12
mcasp2_axr13
mcasp2_axr14
mcasp2_axr15
mcasp2_fsx
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit Frame Sync
McASP2 Receive Bit Clock
mcasp2_aclkr(1)
mcasp2_fsr
McASP2 Receive Frame Sync
McASP2 Transmit High-Frequency Master Clock
McASP2 Transmit Bit Clock
mcasp2_ahclkx
mcasp2_aclkx(1)
IO
Multichannel Audio Serial Port 3
mcasp3_axr0
mcasp3_axr1
mcasp3_axr2
mcasp3_axr3
mcasp3_fsx
McASP3 Transmit/Receive Data
IO
IO
IO
IO
IO
O
B19
C17
C15
A16
F15
B26
B18
B18
F15
McASP3 Transmit/Receive Data
McASP3 Transmit/Receive Data
McASP3 Transmit/Receive Data
McASP3 Transmit Frame Sync
McASP3 Transmit High-Frequency Master Clock
McASP3 Transmit Bit Clock
mcasp3_ahclkx
mcasp3_aclkx(1)
mcasp3_aclkr(1)
mcasp3_fsr
IO
IO
IO
McASP3 Receive Bit Clock
McASP3 Receive Frame Sync
Multichannel Audio Serial Port 4
mcasp4_axr0
mcasp4_axr1
mcasp4_axr2
mcasp4_axr3
mcasp4_fsx
McASP4 Transmit/Receive Data
IO
IO
IO
IO
IO
O
G16
D17
E12
F13
A21
C23
C18
C18
A21
McASP4 Transmit/Receive Data
McASP4 Transmit/Receive Data
McASP4 Transmit/Receive Data
McASP4 Transmit Frame Sync
McASP4 Transmit High-Frequency Master Clock
McASP4 Transmit Bit Clock
mcasp4_ahclkx
mcasp4_aclkx(1)
mcasp4_aclkr(1)
mcasp4_fsr
IO
IO
IO
McASP4 Receive Bit Clock
McASP4 Receive Frame Sync
Multichannel Audio Serial Port 5
mcasp5_axr0
mcasp5_axr1
mcasp5_axr2
mcasp5_axr3
mcasp5_fsx
McASP5 Transmit/Receive Data
IO
IO
IO
IO
IO
O
AB3
AA4
C12
D12
AB9
D18
McASP5 Transmit/Receive Data
McASP5 Transmit/Receive Data
McASP5 Transmit/Receive Data
McASP5 Transmit Frame Sync
mcasp5_ahclkx
McASP5 Transmit High-Frequency Master Clock
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表 4-15. McASP Signal Descriptions (continued)
SIGNAL NAME
mcasp5_aclkx(1)
mcasp5_aclkr(1)
mcasp5_fsr
DESCRIPTION
TYPE
IO
BALL
AA3
McASP5 Transmit Bit Clock
McASP5 Receive Bit Clock
McASP5 Receive Frame Sync
IO
AA3
IO
AB9
Multichannel Audio Serial Port 6
mcasp6_axr0
mcasp6_axr1
mcasp6_axr2
mcasp6_axr3
mcasp6_ahclkx
mcasp6_aclkx(1)
mcasp6_fsx
McASP6 Transmit/Receive Data
IO
IO
IO
IO
O
B12
A11
G13
J11
McASP6 Transmit/Receive Data
McASP6 Transmit/Receive Data
McASP6 Transmit/Receive Data
McASP6 Transmit High-Frequency Master Clock
McASP6 Transmit Bit Clock
E17
B13
A12
B13
A12
IO
IO
IO
IO
McASP6 Transmit Frame Sync
McASP6 Receive Bit Clock
mcasp6_aclkr(1)
mcasp6_fsr
McASP6 Receive Frame Sync
Multichannel Audio Serial Port 7
mcasp7_axr0
mcasp7_axr1
mcasp7_axr2
mcasp7_axr3
mcasp7_ahclkx
mcasp7_aclkx(1)
mcasp7_fsx
McASP7 Transmit/Receive Data
IO
IO
IO
IO
O
E14
A13
B14
J14
McASP7 Transmit/Receive Data
McASP7 Transmit/Receive Data
McASP7 Transmit/Receive Data
McASP7 Transmit High-Frequency Master Clock
McASP7 Transmit Bit Clock
B26
G14
F14
G14
F14
IO
IO
IO
IO
McASP7 Transmit Frame Sync
McASP7 Receive Bit Clock
mcasp7_aclkr(1)
mcasp7_fsr
McASP7 Receive Frame Sync
Multichannel Audio Serial Port 8
mcasp8_axr0
mcasp8_axr1
mcasp8_axr2
mcasp8_axr3
mcasp8_ahclkx
mcasp8_aclkx(1)
mcasp8_fsx
McASP8 Transmit/Receive Data
IO
IO
IO
IO
O
D15
B16
E15
A20
C23
B17
A17
B17
A17
McASP8 Transmit/Receive Data
McASP8 Transmit/Receive Data
McASP8 Transmit/Receive Data
McASP8 Transmit High-Frequency Master Clock
McASP8 Transmit Bit Clock
IO
IO
IO
IO
McASP8 Transmit Frame Sync
McASP8 Receive Bit Clock
mcasp8_aclkr(1)
mcasp8_fsr
McASP8 Receive Frame Sync
(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the
clock input. Any non monotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS
.
4.4.13 Universal Serial Bus (USB)
注
For more information, see: Serial Communication Interface / SuperSpeed USB DRD
Subsystem section of the device TRM.
表 4-16. Universal Serial Bus Signal Descriptions
SIGNAL NAME
Universal Serial Bus 1
usb1_dp
DESCRIPTION
TYPE
BALL
USB1 USB2.0 differential signal pair (positive)
USB1 USB2.0 differential signal pair (negative)
IODS
IODS
AD12
AC12
usb1_dm
102
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表 4-16. Universal Serial Bus Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
AB10
AF12
AE12
AC11
AD11
usb1_drvvbus
usb_rxn0(1)
usb_rxp0(1)
usb_txn0(1)
usb_txp0(1)
USB1 Drive VBUS signal
O
USB1 USB3.0 receiver negative lane
USB1 USB3.0 receiver positive lane
USB1 USB3.0 transmitter negative lane
USB1 USB3.0 transmitter positive lane
IDS
IDS
ODS
ODS
Universal Serial Bus 2
usb2_dp
USB2 USB2.0 differential signal pair (positive)
USB2 USB2.0 differential signal pair (negative)
USB2 Drive VBUS signal
IODS
IODS
O
AE11
AF11
AC10
usb2_dm
usb2_drvvbus
Universal Serial Bus 3
usb3_ulpi_d0
usb3_ulpi_d1
usb3_ulpi_d2
usb3_ulpi_d3
usb3_ulpi_d4
usb3_ulpi_d5
usb3_ulpi_d6
usb3_ulpi_d7
usb3_ulpi_nxt
usb3_ulpi_dir
usb3_ulpi_stp
usb3_ulpi_clk
USB3 - ULPI 8-bit data bus
USB3 - ULPI 8-bit data bus
USB3 - ULPI 8-bit data bus
USB3 - ULPI 8-bit data bus
USB3 - ULPI 8-bit data bus
USB3 - ULPI 8-bit data bus
USB3 - ULPI 8-bit data bus
USB3 - ULPI 8-bit data bus
USB3 - ULPI next
IO
IO
IO
IO
IO
IO
IO
IO
I
AC3 / V6
AC9 / U6
AC6 / U5
AC7 / V5
AC4 / V4
AD4 / V3
AB4 / Y2
AC5 / W2
AC8 / U7
AD6 / V7
AB8 / V9
AB5 / W9
USB3 - ULPI bus direction
USB3 - ULPI stop
I
O
I
USB3 - ULPI functional clock
(1) Signals are enabled by selecting the correct field in the PCIE_B1C0_MODE_SEL register. There are no CTRL_CORE_PAD* register
involved.
4.4.14 SATA
注
For more information, see the Serial Communication Interfaces / SATA section of the device
TRM.
表 4-17. SATA Signal Descriptions
SIGNAL NAME
sata1_rxn0
sata1_rxp0
sata1_txn0
sata1_txp0
sata1_led
DESCRIPTION
TYPE
IDS
BALL
AH9
SATA differential negative receiver lane 0
SATA differential positive receiver lane 0
SATA differential negative transmitter lane 0
SATA differential positive transmitter lane 0
SATA channel activity indicator
IDS
AG9
ODS
ODS
O
AG10
AH10
A22 / G19
4.4.15 Peripheral Component Interconnect Express (PCIe)
注
For more information, see the Serial Communication Interfaces / PCIe Controllers and the
Shared PHY Component Subsystems / PCIe Shared PHY Susbsytem sections of the device
TRM.
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表 4-18. PCIe Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
pcie_rxn0
PCIe1_PHY_RX Receive Data Lane 0 (negative) - mapped to PCIe_SS1
only.
IDS
AG13
pcie_rxp0
pcie_txn0
pcie_txp0
pcie_rxn1
pcie_rxp1
pcie_txn1
pcie_txp1
ljcb_clkp
ljcb_clkn
PCIe1_PHY_RX Receive Data Lane 0 (positive) - mapped to PCIe_SS1
only.
IDS
ODS
ODS
IDS
AH13
AG14
AH14
AF12
AE12
AC11
AD11
AG15
AH15
PCIe1_PHY_TX Transmit Data Lane 0 (negative) - mapped to PCIe_SS1
only.
PCIe1_PHY_TX Transmit Data Lane 0 (positive) - mapped to PCIe_SS1
only.
PCIe2_PHY_RX Receive Data Lane 1 (negative) - mapped to either
PCIe_SS1 (dual lane- mode) or PCIe_SS2 (single lane- mode)
PCIe2_PHY_RX Receive Data Lane 1 (positive) - mapped to either
PCIe_SS1 (dual lane- mode) or PCIe_SS2 (single lane- mode)
IDS
PCIe2_PHY_TX Transmit Data Lane 1 (negative) - mapped to either
PCIe_SS1 (dual lane- mode) or PCIe_SS2 (single lane- mode)
ODS
ODS
IODS
IODS
PCIe2_PHY_TX Transmit Data Lane 1 (positive) - mapped to either
PCIe_SS1 (dual lane- mode) or PCIe_SS2 (single lane- mode)
PCIe1_PHY shared Reference Clock Input / Output Differential Pair
(positive)
PCIe1_PHY shared Reference Clock Input / Output Differential Pair
(negative)
4.4.16 Controller Area Network Interface (DCAN)
注
For more information, see the Serial Communication Interface / DCAN section of the device
TRM.
表 4-19. DCAN Signal Descriptions
SIGNAL NAME
DCAN 1
DESCRIPTION
TYPE
BALL
dcan1_tx
dcan1_rx
DCAN1 transmit data pin
DCAN1 receive data pin
IO
IO
G20
G19 / AD17
DCAN 2
dcan2_tx
dcan2_rx
DCAN2 transmit data pin
DCAN2 receive data pin
IO
IO
E21/ B21
F20/ B20/ AC16
4.4.17 Ethernet Interface (GMAC_SW)
CAUTION
The I/O timings provided in 节 7, Timing Requirements and Switching
Characteristics are valid only if signals within a single IOSET are used. The
IOSETs are defined in 表 7-73, 表 7-78 and 表 7-85.
注
For more information, see the Serial Communication Interfaces / Ethernet Controller section
of the device TRM.
104
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ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-20. GMAC Signal Descriptions
SIGNAL NAME
rgmii0_txc
rgmii0_txctl
rgmii0_txd3
rgmii0_txd2
rgmii0_txd1
rgmii0_txd0
rgmii0_rxc
rgmii0_rxctl
rgmii0_rxd3
rgmii0_rxd2
rgmii0_rxd1
rgmii0_rxd0
rgmii1_txc
rgmii1_txctl
rgmii1_txd3
rgmii1_txd2
rgmii1_txd1
rgmii1_txd0
rgmii1_rxc
rgmii1_rxctl
rgmii1_rxd3
rgmii1_rxd2
rgmii1_rxd1
rgmii1_rxd0
mii1_rxd1
mii1_rxd2
mii1_rxd3
mii1_rxd0
mii1_rxclk
mii1_rxdv
DESCRIPTION
TYPE
BALL
W9
V9
V7
U7
V6
U6
U5
V5
V4
V3
Y2
W2
D5
C2
C3
C4
B2
D6
C5
A3
B3
B4
B5
A4
C1
E4
F5
RGMII0 Transmit Clock
RGMII0 Transmit Enable
RGMII0 Transmit Data
RGMII0 Transmit Data
RGMII0 Transmit Data
RGMII0 Transmit Data
RGMII0 Receive Clock
RGMII0 Receive Control
RGMII0 Receive Data
RGMII0 Receive Data
RGMII0 Receive Data
RGMII0 Receive Data
RGMII1 Transmit Clock
RGMII1 Transmit Enable
RGMII1 Transmit Data
RGMII1 Transmit Data
RGMII1 Transmit Data
RGMII1 Transmit Data
RGMII1 Receive Clock
RGMII1 Receive Control
RGMII1 Receive Data
RGMII1 Receive Data
RGMII1 Receive Data
RGMII1 Receive Data
MII1 Receive Data
O
O
O
O
O
O
I
I
I
I
I
I
O
O
O
O
O
O
I
I
I
I
I
I
I
MII1 Receive Data
I
MII1 Receive Data
I
MII1 Receive Data
I
E6
D5
C2
C3
C4
B2
D6
C5
A3
B3
B4
B5
A4
V6
V9
W9
U6
Y1
V2
U5
MII1 Receive Clock
I
MII1 Receive Data Valid
MII1 Transmit Clock
MII1 Transmit Data
I
mii1_txclk
mii1_txd0
I
O
O
O
O
I
mii1_txd1
MII1 Transmit Data
mii1_txd2
MII1 Transmit Data
mii1_txd3
MII1 Transmit Data
mii1_txer
MII1 Transmit Error
mii1_rxer
MII1 Receive Data Error
I
mii1_col
MII1 Collision Detect (Sense)
MII1 Carrier Sense
I
mii1_crs
I
mii1_txen
MII1 Transmit Data Enable
MII0 Receive Data
O
I
mii0_rxd1
mii0_rxd2
mii0_rxd3
mii0_rxd0
mii0_rxclk
mii0_rxdv
MII0 Receive Data
I
MII0 Receive Data
I
MII0 Receive Data
I
MII0 Receive Clock
MII0 Receive Data Valid
MII0 Transmit Clock
I
I
mii0_txclk
I
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表 4-20. GMAC Signal Descriptions (continued)
SIGNAL NAME
mii0_txd0
mii0_txd1
mii0_txd2
mii0_txd3
mii0_txer
mii0_rxer
mii0_col
DESCRIPTION
TYPE
BALL
MII0 Transmit Data
O
O
O
O
I
W2
MII0 Transmit Data
Y2
MII0 Transmit Data
V4
MII0 Transmit Data
V5
MII0 Transmit Error
U4
MII0 Receive Data Error
MII0 Collision Detect (Sense)
MII0 Carrier Sense
I
U7
I
V1
mii0_crs
I
V7
mii0_txen
rmii1_crs
rmii1_rxer
rmii1_rxd1
rmii1_rxd0
rmii1_txen
rmii1_txd1
rmii1_txd0
rmii0_crs
rmii0_rxer
rmii0_rxd1
rmii0_rxd0
rmii0_txen
rmii0_txd1
rmii0_txd0
mdio_mclk
mdio_d
MII0 Transmit Data Enable
RMII1 Carrier Sense
RMII1 Receive Data Error
RMII1 Receive Data
O
I
V3
V2
I
Y1
I
W9
RMII1 Receive Data
I
V9
RMII1 Transmit Data Enable
RMII1 Transmit Data
RMII1 Transmit Data
RMII0 Carrier Sense
RMII0 Receive Data Error
RMII0 Receive Data
O
O
O
I
U5
V5
V4
V7
I
U7
I
V6
RMII0 Receive Data
I
U6
RMII0 Transmit Data Enable
RMII0 Transmit Data
RMII0 Transmit Data
Management Data Serial Clock
Management Data
O
O
O
O
IO
V3
Y2
W2
AC5 / V1 / B21 / D3
AB4 / U4 / B20 / F6
4.4.18 eMMC/SD/SDIO
注
For more information, see the HS MMC/SDIO section of the device TRM.
表 4-21. eMMC/SD/SDIO Signal Descriptions
SIGNAL NAME
Multi Media Card 1
mmc1_clk(1)
DESCRIPTION
TYPE
BALL
MMC1 clock
IO
IO
I
W6
Y6
mmc1_cmd
MMC1 command
MMC1 Card Detect
MMC1 Write Protect
MMC1 data bit 0
MMC1 data bit 1
MMC1 data bit 2
MMC1 data bit 3
mmc1_sdcd
W7
Y9
mmc1_sdwp
mmc1_dat0
I
IO
IO
IO
IO
AA6
Y4
mmc1_dat1
mmc1_dat2
AA5
Y3
mmc1_dat3
Multi Media Card 2
mmc2_clk(1)
MMC2 clock
IO
IO
I
J7
H6
mmc2_cmd
MMC2 command
MMC2 Card Detect
mmc2_sdcd
G20
106
Terminal Configuration and Functions
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TDA2E
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ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-21. eMMC/SD/SDIO Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
I
BALL
G19
J4
mmc2_sdwp
mmc2_dat0
mmc2_dat1
mmc2_dat2
mmc2_dat3
mmc2_dat4
mmc2_dat5
mmc2_dat6
mmc2_dat7
Multi Media Card 3
mmc3_clk(1)
mmc3_cmd
mmc3_sdcd
mmc3_sdwp
mmc3_dat0
mmc3_dat1
mmc3_dat2
mmc3_dat3
mmc3_dat4
mmc3_dat5
mmc3_dat6
mmc3_dat7
Multi Media Card 4
mmc4_clk(1)
mmc4_cmd
mmc4_sdcd
mmc4_sdwp
mmc4_dat0
mmc4_dat1
mmc4_dat2
mmc4_dat3
MMC2 Write Protect
MMC2 data bit 0
MMC2 data bit 1
MMC2 data bit 2
MMC2 data bit 3
MMC2 data bit 4
MMC2 data bit 5
MMC2 data bit 6
MMC2 data bit 7
IO
IO
IO
IO
IO
IO
IO
IO
J6
H4
H5
K7
M7
J5
K6
MMC3 clock
IO
IO
I
AD4
AC4
B21
B20
AC7
AC6
AC9
AC3
AC8
AD6
AB8
AB5
MMC3 command
MMC3 Card Detect
MMC3 Write Protect
MMC3 data bit 0
MMC3 data bit 1
MMC3 data bit 2
MMC3 data bit 3
MMC3 data bit 4
MMC3 data bit 5
MMC3 data bit 6
MMC3 data bit 7
I
IO
IO
IO
IO
IO
IO
IO
IO
MMC4 clock
IO
IO
I
E25
C27
B27
C26
D28
D26
D27
C28
MMC4 command
MMC4 Card Detect
MMC4 Write Protect
MMC4 data bit 0
MMC4 data bit 1
MMC4 data bit 2
MMC4 data bit 3
I
IO
IO
IO
IO
(1) By default, this clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer
to serve as the internal reference signal. mmc1_clk and mmc2_clk have an optional software programmable setting to use an 'internal
loopback clock' instead of the default 'pad loopback clock'. If the 'pad loopback clock' is used, series termination is recommended (as
close to device pin as possible) to improve signal integrity of the clock input. Any nonmonotonicity in voltage that occurs at the pad
loopback clock pin between VIH and VIL must be less than VHYS
.
4.4.19 General-Purpose Interface (GPIO)
注
For more information, see the General-Purpose Interface section of the device TRM.
表 4-22. GPIOs Signal Descriptions
SIGNAL NAME
GPIO 1
DESCRIPTION
TYPE
BALL
gpio1_0
gpio1_3
gpio1_4
General-Purpose Input
I
I
AD17
AC16
D15
General-Purpose Input
General-Purpose Input/Output
IO
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表 4-22. GPIOs Signal Descriptions (continued)
SIGNAL NAME
gpio1_5
DESCRIPTION
TYPE
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
BALL
A17
M6
M2
L5
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
gpio1_6
gpio1_7
gpio1_8
gpio1_9
M1
L6
gpio1_10
gpio1_11
gpio1_12
gpio1_13
gpio1_14
gpio1_15
gpio1_16
gpio1_17
gpio1_18
gpio1_19
gpio1_20
gpio1_21
gpio1_22
gpio1_23
gpio1_24
gpio1_25
gpio1_26
gpio1_27
gpio1_28
gpio1_29
gpio1_30
gpio1_31
L4
L3
L2
G20
G19
D27
C28
H1
J3
H2
H3
AC8
AD6
AB8
AB5
P6
R9
R5
P5
N7
R4
GPIO 2
gpio2_0
gpio2_1
gpio2_2
gpio2_3
gpio2_4
gpio2_5
gpio2_6
gpio2_7
gpio2_8
gpio2_9
gpio2_10
gpio2_11
gpio2_12
gpio2_13
gpio2_14
gpio2_15
gpio2_16
gpio2_17
gpio2_18
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
N9
P9
P4
R3
T2
U2
U1
P3
R2
K7
M7
J5
K6
J7
J4
J6
H4
H5
H6
108
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
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ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-22. GPIOs Signal Descriptions (continued)
SIGNAL NAME
gpio2_19
gpio2_20
gpio2_21
gpio2_22
gpio2_23
gpio2_24
gpio2_25
gpio2_26
gpio2_27
gpio2_28
gpio2_29
GPIO 3
DESCRIPTION
TYPE
IO
BALL
T1
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
IO
P2
IO
P1
IO
P7
IO
N1
IO
M5
M3
N6
IO
IO
IO
M4
N2
IO
IO
B17
gpio3_28
gpio3_29
gpio3_30
gpio3_31
GPIO 4
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
IO
IO
IO
IO
E1
G2
H7
G1
gpio4_0
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
G6
F2
gpio4_1
gpio4_2
F3
gpio4_3
D1
E2
gpio4_4
gpio4_5
D2
F4
gpio4_6
gpio4_7
C1
E4
gpio4_8
gpio4_9
F5
gpio4_10
gpio4_11
gpio4_12
gpio4_13
gpio4_14
gpio4_15
gpio4_16
gpio4_17
gpio4_18
gpio4_19
gpio4_20
gpio4_21
gpio4_22
gpio4_23
gpio4_24
gpio4_25
gpio4_26
gpio4_27
gpio4_28
gpio4_29
E6
D3
F6
D5
C2
C3
C4
A12
E14
D11
B10
B11
C11
E11
B2
D6
C5
A3
B3
B4
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表 4-22. GPIOs Signal Descriptions (continued)
SIGNAL NAME
gpio4_30
DESCRIPTION
TYPE
IO
BALL
B5
General-Purpose Input/Output
General-Purpose Input/Output
gpio4_31
IO
A4
GPIO 5
gpio5_0
gpio5_1
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
B14
J14
G12
F12
G13
J11
E12
F13
C12
D12
B12
A11
B13
B18
F15
V1
gpio5_2
gpio5_3
gpio5_4
gpio5_5
gpio5_6
gpio5_7
gpio5_8
gpio5_9
gpio5_10
gpio5_11
gpio5_12
gpio5_13
gpio5_14
gpio5_15
gpio5_16
gpio5_17
gpio5_18
gpio5_19
gpio5_20
gpio5_21
gpio5_22
gpio5_23
gpio5_24
gpio5_25
gpio5_26
gpio5_27
gpio5_28
gpio5_29
gpio5_30
gpio5_31
U4
U3
V2
Y1
W9
V9
V7
U7
V6
U6
U5
V5
V4
V3
Y2
W2
GPIO 6
gpio6_4
gpio6_5
gpio6_6
gpio6_7
gpio6_8
gpio6_9
gpio6_10
gpio6_11
gpio6_12
gpio6_13
gpio6_14
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
A13
G14
F14
B16
C15
A16
AC5
AB4
AB10
AC10
E21
110
Terminal Configuration and Functions
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TDA2E
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ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 4-22. GPIOs Signal Descriptions (continued)
SIGNAL NAME
gpio6_15
gpio6_16
gpio6_17
gpio6_18
gpio6_19
gpio6_20
gpio6_21
gpio6_22
gpio6_23
gpio6_24
gpio6_25
gpio6_26
gpio6_27
gpio6_28
gpio6_29
gpio6_30
gpio6_31
GPIO 7
DESCRIPTION
TYPE
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
BALL
F20
F21
D18
E17
B26
C23
W6
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
Y6
AA6
Y4
AA5
Y3
W7
Y9
AD4
AC4
AC7
gpio7_0
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
AC6
AC9
AC3
R6
gpio7_1
gpio7_2
gpio7_3
gpio7_4
T9
gpio7_5
T6
gpio7_6
T7
gpio7_7
A25
F16
B25
A24
A22
B21
B20
A26
B22
G17
B24
L1
gpio7_8
gpio7_9
gpio7_10
gpio7_11
gpio7_12
gpio7_13
gpio7_14
gpio7_15
gpio7_16
gpio7_17
gpio7_18
gpio7_19
gpio7_22
gpio7_23
gpio7_24
gpio7_25
gpio7_26
gpio7_27
gpio7_28
gpio7_29
gpio7_30
K2
B27
C26
E25
C27
D28
D26
J1
J2
D14
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www.ti.com.cn
表 4-22. GPIOs Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
gpio7_31
General-Purpose Input/Output
IO
C14
GPIO 8
gpio8_0
gpio8_1
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
F11
G10
F10
G11
E9
gpio8_2
gpio8_3
gpio8_4
gpio8_5
F9
gpio8_6
F8
gpio8_7
E7
gpio8_8
E8
gpio8_9
D9
gpio8_10
gpio8_11
gpio8_12
gpio8_13
gpio8_14
gpio8_15
gpio8_16
gpio8_17
gpio8_18
gpio8_19
gpio8_20
gpio8_21
gpio8_22
gpio8_23
gpio8_27
gpio8_28
gpio8_29
gpio8_30
gpio8_31
D7
D8
A5
C6
C8
C7
B7
B8
A7
A8
C9
A9
B9
A10
D23
F19
E18
G21
D24
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
IO
IO
IO
IO
4.4.20 Pulse Width Modulation (PWM) Interface
注
For more information, see the Pulse-Width Modulation (PWM) SS section of the device TRM.
表 4-23. PWM Signal Descriptions
SIGNAL NAME
PWMSS1
DESCRIPTION
TYPE
BALL
eQEP1A_in
eQEP1B_in
eQEP1_index
eQEP1_strobe
ehrpwm1A
EQEP1 Quadrature Input A
EQEP1 Quadrature Input B
EQEP1 Index Input
I
E1
G2
H7
G1
G6
F2
I
IO
IO
O
O
EQEP1 Strobe Input
EHRPWM1 Output A
EHRPWM1 Output B
ehrpwm1B
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表 4-23. PWM Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
ehrpwm1_tripzone_in EHRPWM1 Trip Zone Input
put
IO
AG7 / F3
eCAP1_in_PWM1_out ECAP1 Capture Input / PWM Output
IO
I
AH6 / D1
AH3 / E2
AH5 / D2
ehrpwm1_synci
ehrpwm1_synco
EHRPWM1 Sync Input
EHRPWM1 Sync Output
O
PWMSS2
eQEP2A_in
eQEP2B_in
eQEP2_index
eQEP2_strobe
ehrpwm2A
EQEP2 Quadrature Input A
EQEP2 Quadrature Input B
EQEP2 Index Input
I
AG6 / F4
AH4 / C1
AG4 / E4
F5
I
IO
IO
O
O
IO
EQEP2 Strobe Input
EHRPWM2 Output A
EHRPWM2 Output B
AC5 / E6
AB4 / D3
AD4 / F6
ehrpwm2B
ehrpwm2_tripzone_in EHRPWM2 Trip Zone Input
put
eCAP2_in_PWM2_out ECAP2 Capture Input / PWM Output
IO
AC4 / D5
PWMSS3
eQEP3A_in
eQEP3B_in
eQEP3_index
eQEP3_strobe
ehrpwm3A
EQEP3 Quadrature Input A
EQEP3 Quadrature Input B
EQEP3 Index Input
I
AC7 / C2
AC6 / C3
AC9 / C4
AC3 / B2
AC8 / D6
AD6 / C5
AB8 / A3
I
IO
IO
O
O
IO
EQEP3 Strobe Input
EHRPWM3 Output A
EHRPWM3 Output B
ehrpwm3B
ehrpwm3_tripzone_in EHRPWM3 Trip Zone Input
put
eCAP3_in_PWM3_out ECAP3 Capture Input / PWM Output
IO
AB5 / B3
4.4.21 Test Interfaces
CAUTION
The I/O timings provided in 节 7, Timing Requirements and Switching
Characteristics are valid only if signals within a single IOSET are used. The
IOSETs are defined in 表 7-136.
注
For more information, see the On-Chip Debug Support / Debug Ports section of the device
TRM.
表 4-24. Debug Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
tms
JTAG test port mode select. An external pullup resistor should be used on this
ball.
IO
F18
tdi
tdo
JTAG test data
I
O
I
D23
F19
E20
D20
E18
JTAG test port data
JTAG test clock
JTAG test reset
JTAG return clock
tclk
trstn
rtck
I
O
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表 4-24. Debug Signal Descriptions (continued)
SIGNAL NAME
emu0
DESCRIPTION
Emulator pin 0
Emulator pin 1
Emulator pin 2
Emulator pin 3
Emulator pin 4
Emulator pin 5
Emulator pin 6
Emulator pin 7
Emulator pin 8
Emulator pin 9
Emulator pin 10
Emulator pin 11
Emulator pin 12
Emulator pin 13
Emulator pin 14
Emulator pin 15
Emulator pin 16
Emulator pin 17
Emulator pin 18
Emulator pin 19
TYPE
IO
IO
O
BALL
G21
emu1
D24
emu2
F10
emu3
O
D7
emu4
O
A7
emu5
O
E1 / G11
G2 / E9
H7 / F9
G1 / F8
G6 / E7
F2 / D8
F3 / A5
D1 / C6
E2 / C8
D2 / C7
F4 / A8
C1 / C9
E4 / A9
F5 / B9
E6 / A10
emu6
O
emu7
O
emu8
O
emu9
O
emu10
emu11
emu12
emu13
emu14
emu15
emu16
emu17
emu18
emu19
O
O
O
O
O
O
O
O
O
O
4.4.22 System and Miscellaneous
4.4.22.1 Sysboot
注
For more information, see the Initialization (ROM Code) section of the device TRM.
表 4-25. Sysboot Signal Descriptions
SIGNAL NAME DESCRIPTION
TYPE
BALL
sysboot0
sysboot1
sysboot2
sysboot3
sysboot4
sysboot5
sysboot6
sysboot7
sysboot8
sysboot9
Boot Mode Configuration 0. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
M6
Boot Mode Configuration 1. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
I
I
I
I
I
I
I
I
M2
L5
M1
L6
L4
L3
L2
L1
K2
Boot Mode Configuration 2. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 3. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 4. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 5. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 6. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 7. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 8. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 9. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
114
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表 4-25. Sysboot Signal Descriptions (continued)
SIGNAL NAME DESCRIPTION
TYPE
BALL
sysboot10
sysboot11
sysboot12
sysboot13
sysboot14
sysboot15
Boot Mode Configuration 10. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
J1
Boot Mode Configuration 11. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
I
I
I
I
J2
H1
J3
Boot Mode Configuration 12. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 13. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 14. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
H2
H3
Boot Mode Configuration 15. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
4.4.22.2 Power, Reset, and Clock Management (PRCM)
注
For more information, see PRCM section of the device TRM.
表 4-26. PRCM Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
clkout1
Device Clock output 1. Can be used externally for devices with non-
critical timing requirements, or for debug, or as a reference clock on
GPMC as described in 表 7-25 GPMC/NOR Flash Interface Switching
Characteristics - Synchronous Mode - Default and 表 7-27
GPMC/NOR Flash Interface Switching Characteristics - Synchronous
Mode - Alternate.
O
F21 / P7
clkout2
clkout3
rstoutn
Device Clock output 2. Can be used externally for devices with non-
critical timing requirements, or for debug.
O
O
O
D18 / N1
C23
Device Clock output 3. Can be used xternally for devices with non-
critical timing requirements, or for debug.
Reset out (Active low). This pin asserts low in response to any global
reset condition on the device.(2)
F23
resetn
porz
Device Reset Input
I
I
E23
F22
Power on Reset (active low). This pin must be asserted low until all
device supplies are valid (see reset sequence/requirements).
xref_clk0
xref_clk1
xref_clk2
xref_clk3
xi_osc0
External Reference Clock 0. For Audio and other Peripherals.
External Reference Clock 1. For Audio and other Peripherals.
External Reference Clock 2. For Audio and other Peripherals.
External Reference Clock 3. For Audio and other Peripherals.
I
I
I
I
I
D18
E17
B26
C23
AE15
System Oscillator OSC0 Crystal input / LVCMOS clock input.
Functions as the input connection to a crystal when the internal
oscillator OSC0 is used. Functions as an LVCMOS-compatible input
clock when an external oscillator is used.
xo_osc0
xi_osc1
System Oscillator OSC0 Crystal output
O
I
AD15
AC15
Auxiliary Oscillator OSC1 Crystal input / LVCMOS clock input.
Functions as the input connection to a crystal when the internal
oscillator OSC1 is used. Functions as an LVCMOS-compatible input
clock when an external oscillator is used.
xo_osc1
RMII_MHZ_50_CLK(1)
Auxiliary Oscillator OSC1 Crystal output
A
AC13
U3
RMII Reference Clock (50MHz). This pin is an input when external
reference is used or output when internal reference is used.
IO
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(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the
clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS
.
(2) Note that rstoutn is only valid after vddshv3 is valid. If the rstoutn signal will be used as a reset into other devices attached to the SOC, it
must be AND'ed with porz. This will prevent glitches occurring during supply ramping being propagated.
4.4.22.3 Real-Time Clock (RTC) Interface
注
For more information, see the Real-Time Clock (RTC) chapter of the device TRM.
表 4-27. RTC Signal Descriptions
SIGNAL NAME DESCRIPTION
TYPE
BALL
AD17
AC17
AB16
AC16
AB17
AE14
Wakeup0
Wakeup1
Wakeup2
Wakeup3
rtc_porz
RTC External Wakeup Input 0
I
I
I
I
I
I
RTC External Wakeup Input 1
RTC External Wakeup Input 2
RTC External Wakeup Input 3
RTC Power Domain Power-On Reset Input
rtc_osc_xi_clkin3 RTC Oscillator Input. Crystal connection to internal RTC oscillator. Functions as an
2
RTC clock input when an external oscillator is used.
rtc_osc_xo
rtc_iso(1)
on_off
RTC Oscillator Output
O
I
AD14
AF14
Y11
RTC Domain Isolation Signal
RTC Power Enable output pin
O
(1) This signal must be kept 0 if device power supplies are not valid during RTC mode and 1 during normal operation. This can typically be
achieved by connecting rtc_iso to the same signal driving porz (not rtc_porz) with appropriate voltage level translation if necessary.
4.4.22.4 System Direct Memory Access (SDMA)
注
For more information, see the DMA Controllers / System DMA section of the device TRM.
表 4-28. System DMA Signal Descriptions
SIGNAL NAME DESCRIPTION
TYPE
BALL
P7 / P4
N1 / R3
N6
dma_evt1
dma_evt2
dma_evt3
dma_evt4
System DMA Event Input 1
I
I
I
I
System DMA Event Input 2
System DMA Event Input 3
System DMA Event Input 4
M4
4.4.22.5 Interrupt Controllers (INTC)
注
For more information, see the Interrupt Controllers section of the device TRM.
表 4-29. INTC Signal Descriptions
SIGNAL NAME DESCRIPTION
TYPE
BALL
nmin_dsp
Non maskable interrupt input, active-low. This pin can be optionally routed to the
DSP NMI input or as generic input to the Arm cores. Note that by default this pin
has an internal pulldown resistor enabled. This internal pulldown should be disabled
or countered by a stronger external pullup resistor before routing to the DSP or Arm
processors.
I
D21
sys_nirq2
External interrupt event to any device INTC
I
AD17
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表 4-29. INTC Signal Descriptions (continued)
SIGNAL NAME DESCRIPTION
TYPE
BALL
sys_nirq1
External interrupt event to any device INTC
I
AC16
4.4.22.6 Observability
注
For more information, see the Control Module section of the device TRM.
表 4-30. Observability Signal Descriptions
SIGNAL NAME DESCRIPTION
TYPE
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
BALL
F10
G11
E9
obs0
obs1
Observation Output 0
Observation Output 1
obs2
Observation Output 2
obs3
Observation Output 3
F9
obs4
Observation Output 4
F8
obs5
Observation Output 5
D7
D8
A5
obs6
Observation Output 6
obs7
Observation Output 7
obs8
Observation Output 8
C6
C8
C7
A7
obs9
Observation Output 9
obs10
obs11
obs12
obs13
obs14
obs15
obs16
obs17
obs18
obs19
obs20
obs21
obs22
obs23
obs24
obs25
obs26
obs27
obs28
obs29
obs30
obs31
obs_dmarq1
obs_dmarq2
obs_irq1
obs_irq2
Observation Output 10
Observation Output 11
Observation Output 12
Observation Output 13
Observation Output 14
Observation Output 15
Observation Output 16
Observation Output 17
Observation Output 18
Observation Output 19
Observation Output 20
Observation Output 21
Observation Output 22
Observation Output 23
Observation Output 24
Observation Output 25
Observation Output 26
Observation Output 27
Observation Output 28
Observation Output 29
Observation Output 30
Observation Output 31
DMA Request External Observation Output 1
DMA Request External Observation Output 2
IRQ External Observation Output 1
IRQ External Observation Output 2
A8
C9
A9
B9
F10
G11
E9
F9
F8
D7
D8
A5
C6
C8
C7
A7
A8
C9
A9
B9
G11
D8
F10
D7
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4.4.23 Power Supplies
注
For more information, see Power, Reset, and Clock Management / PRCM Subsystem
Environment / External Voltage Inputs section of the device TRM.
表 4-31. Power Supply Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
PWR
H13 / H14 / J17 / J18
/ L7 / L8 / N10 / N13 /
P11 / P12 / P13 / R11
/ R16 / R19 / T13 /
vdd
Core voltage domain supply
T16 / T19 / U13 / U16
/ U8 / U9 / V16 / V8
GND
A1 / A14 / A2 / A23 /
A28 / A6 / AA14 /
AA15 / AA20 / AA8 /
AA9 / AB14 / AB20 /
AD1 / AD24 / AG1 /
AH1 / AH2 / AH20 /
AH28 / B1 / D13 /
D19 / E13 / E19 / F1 /
F7 / G7 / G8 / G9 /
H12 / J12 / J15 / J28 /
K1 / K15 / K24 / K25 /
K4 / K5 / L13 / L14 /
M19 / N14 / N15 /
vss
Ground
N19 / N24 / N25 / P28
/ R1 / R12 / R13 /
R21 / T10 / T11 / T12
/ T14 / T15 / T17 /
T18 / T21 / U14 / U15
/ U17 / U20 / U21 /
V15 / V17 / W1 / W15
/ W24 / W25 / W28
cap_vbbldo_gpu(1)
cap_vbbldo_iva(1)
cap_vbbldo_mpu(1)
cap_vbbldo_dsp(1)
cap_vddram_core1(1)
cap_vddram_core3(1)
cap_vddram_core4(1)
cap_vddram_mpu(1)
cap_vddram_gpu(1)
cap_vddram_iva(1)
cap_vddram_dsp(1)
vdda_dsp_iva
External capacitor connection for the GPU vbb ldo output
External capacitor connection for the IVA vbb ldo output
External capacitor connection for the MPU vbb ldo output
External capacitor connection for the DSP vbb ldo output
External capacitor connection for the Core SRAM array ldo1 output
External capacitor connection for the Core SRAM array ldo3 output
External capacitor connection for the Core SRAM array ldo4 output
External capacitor connection for the MPU SRAM array ldo output
External capacitor connection for the GPU SRAM array ldo output
External capacitor connection for the IVA SRAM array ldo output
External capacitor connection for the DSP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
PWR
PWR
PWR
PWR
PWR
PWR
Y14
J10
J16
K9
T20
L9
J19
K19
Y13
K16
J9
DSP PLL and IVA PLL analog power supply
N12
P14
P15
M14
N16
AA12
vdda_core_gmac
vdda_pll_spare
DPLL_CORE and CORE HSDIVIDER analog power supply
DPLL_SPARE analog power supply
vdda_per
DPLL_ABE, DPLL_PER, and PER HSDIVIDER analog power supply
MPU_ABE PLL analog power supply
vdda_mpu_abe
vdda33v_usb1
HS USB1 3.3V analog power supply. If USB1 is not used, this pin can
alternatively be connected to VSS if the following requirements are met:
- The usb1_dm/usb1_dp pins are left unconnected
- The USB1 PHY is kept powered down
vdda33v_usb2
HS USB2 3.3V analog power supply. If USB2 is not used, this pin can
alternatively be connected to VSS if the following requirements are met:
- The usb2_dm/usb2_dp pins are left unconnected
PWR
Y12
- The USB2 PHY is kept powered down
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表 4-31. Power Supply Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
BALL
R17
vdda_ddr
vdda_debug
vdda_gpu
vdda_hdmi
vdda_osc
vdda_pcie
vdda_pcie0
vdda_rtc
DPLL_DDR and DDR HSDIVIDER analog power supply
DPLL_DEBUG analog power supply
N11
DPLL_GPU analog power supply
R14
PLL_HDMI and HDMI analog power supply
HFOSC analog power supply
Y17
AD16 / AE16
AA17
AA16
AB13
V13
DPLL_PCIe_REF and PCIe analog power supply
PCIe ch0 RX/TX analog power supply
RTC bias and RTC LFOSC analog power supply
DPLL_SATA and SATA RX/TX analog power supply
DPLL_USB and HS USB1 1.8V analog power supply
HS USB2 1.8V analog power supply
vdda_sata
vdda_usb1
vdda_usb2
vdda_usb3
vdda_csi
AA13
AB12
W14
DPLL_USB_OTG_SS and USB3.0 RX/TX analog power supply
CSI Interface 1.8v Supply
W12
vdda_video
vdds18v
VIDEO1 and VIDEO2 PLL analog power supply
1.8V power supply
P16
G18 / H17 / M8 / M9 /
N8 / P8 / R8 / T8 /
V21 / V22 / W17 /
W18
vdds18v_ddr1
EMIF1 bias power supply
PWR
AA18 / AA19 / N21 /
P20 / P21 / W21 /
Y21
vddshv1
vddshv2
vddshv3
Dual Voltage (1.8V or 3.3V) power supply for the VIN2 Power Group
pins
PWR
PWR
PWR
E3 / E5 / G4 / G5 / H8
/ H9
Dual Voltage (1.8V or 3.3V) power supply for the VOUT Power Group
pins
B6 / D10 / E10 / H10 /
H11
Dual Voltage (1.8V or 3.3V) power supply for the GENERAL Power
Group pins
B23 / D16 / D22 / E16
/ E22 / G15 / H15 /
H16 / H18 / H19
vddshv4
vddshv5
vddshv6
vddshv7
vddshv8
vddshv9
vddshv10
vddshv11
vdds_ddr1
Dual Voltage (1.8V or 3.3V) power supply for the MMC4 Power Group
pins
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
C24
Dual Voltage (1.8V or 3.3V) power supply for the RTC Power Group
pins
V12
Dual Voltage (1.8V or 3.3V) power supply for the VIN1 Power Group
pins
AD5 / AD7 / AE7 /
AF5
Dual Voltage (1.8V or 3.3V) power supply for the WIFI Power Group
pins
AB6 / AB7
Dual Voltage (1.8V or 3.3V) power supply for the MMC1 Power Group
pins
W8 / Y8
Dual Voltage (1.8V or 3.3V) power supply for the RGMII Power Group
pins
U10 / W4 / W5
Dual Voltage (1.8V or 3.3V) power supply for the GPMC Power Group
pins
N4 / N5 / P10 / R10 /
R7 / T4 / T5
Dual Voltage (1.8V or 3.3V) power supply for the MMC2 Power Group
pins
J8 / K8
EMIF1 power supply (1.5V for DDR3 mode / 1.35V DDR3L mode)
AA21 / AA22 / AB21 /
AB22 / AB24 / AB25 /
AC22 / AD26 / AG20 /
AG28 / AH27 / T24 /
T25 / W16 / W27
vdds_mlbp
vdd_dsp
MLBP IO power supply
PWR
PWR
AA7 / Y7
DSP voltage domain supply
K10 / K11 / L10 / L11
/ M10 / M11
vdd_gpu
GPU voltage domain supply
PWR
U11 / U12 / V10 / V11
/ V14 / W10 / W11 /
W13
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BALL
表 4-31. Power Supply Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
vdd_iva
IVA voltage domain supply
PWR
J13 / K12 / K13 / L12
/ M12 / M13
vdd_mpu
MPU voltage domain supply
PWR
K17 / K18 / L15 / L16
/ L17 / L18 / L19 /
M15 / M16 / M17 /
M18 / N17 / N18 /
P17 / P18 / R18
vdd_rtc
vssa_hdmi
vssa_osc0
vssa_osc1
vssa_pcie
vssa_sata
vssa_usb
vssa_usb3
vssa_csi
RTC voltage domain supply
DPLL_HDMI and HDMI PHY analog ground
OSC0 analog ground
PWR
GND
GND
GND
GND
GND
GND
GND
GND
GND
AB15
AD19 / AE19
AF15
OSC1 analog ground
AC14
PCIe analog ground
AD13 / AE13
AE10
SATA analog ground
HS USB1 and HS USB2 analog ground
DPLL_USB and USB3.0 RX/TX analog ground
CSI Interface 0v Supply
AA11 / AB11
AD10
AA10 / AH8
R15
vssa_video
DPLL_VIDEO1 analog ground
(1) This pin must always be connected via a 1-µF capacitor to vss.
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5 Specifications
注
For more information, see Power, Reset, and Clock Management / PRCM Subsystem
Environment / External Voltage Inputs or Initialization / Preinitialization / Power Requirements
section of the Device TRM.
注
The index numbers 1 which is part of the EMIF1 signal prefixes (ddr1_*) listed in 表 4-8,
EMIF SDRAM Signal Descriptions, column "SIGNAL NAME" not to be confused with DDR1
type of SDRAM memories.
注
Audio Back End (ABE) module is not supported for this family of devices, but “ABE” name is
still present in some clock or DPLL names.
CAUTION
All IO Cells are NOT Fail-safe compliant and should not be externally driven in
absence of their IO supply.
5.1 Absolute Maximum Ratings
Stresses beyond those listed as absolute maximum ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions
beyond those listed under 节 5.4, Recommended Operating Conditions, is not implied. Exposure to
absolute maximum rated conditions for extended periods may affect device reliability.
表 5-1. Absolute Maximum Rating Over Junction Temperature Range
PARAMETER(1)
MIN
MAX
UNIT
VSUPPLY (Steady-State)
Supply Voltage Ranges (Steady-
State)
Core (vdd, vdd_mpu, vdd_gpu,
vdd_dsp, vdd_iva, vdd_rtc)
-0.3
1.5
V
Analog (vdda_usb1, vdda_usb2,
vdda_per, vdda_ddr, vdda_debug,
vdda_mpu_abe, vdda_usb3,
vdda_csi, vdda_core_gmac,
vdda_pll_spare, vdda_dsp_iva,
vdda_gpu, dda_hdmi, vdda_pcie,
vdda_pcie0, vdda_sata,
-0.3
-0.3
2.0
3.8
V
V
vdda_video, vdda_osc, vdda_rtc)
Analog 3.3V (vdda33v_usb1,
vdda33v_usb2)
vdds18v, vdds18v_ddr1,
vdds_mlbp, vdds_ddr1
-0.3
-0.3
-0.3
-0.3
2.1
2.1
3.8
3.6
V
V
V
V
vddshv1-11 (1.8V mode)
vddshv1-7 (3.3V mode), vddshv9-11
(3.3V mode)
vddshv8 (3.3V mode)
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表 5-1. Absolute Maximum Rating Over Junction Temperature Range (continued)
PARAMETER(1)
MIN
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
MAX
UNIT
V
VIO (Steady-State)
Input and Output Voltage Ranges
(Steady-State)
Core I/Os
1.5
2.0
Analog I/Os (except HDMI)
HDMI I/Os
V
3.5
V
I/O 1.35V
1.65
1.8
V
I/O 1.5V
V
1.8V I/Os
2.1
V
3.3V I/Os (except those powered by
vddshv8)
-0.3
-0.3
3.8
V
3.3V I/Os (powered by vddshv8)
3.6
105
V
SR
Maximum slew rate, all supplies
V/s
VIO (Transient Overshoot /
Undershoot)
Input and Output Voltage Ranges (Transient Overshoot/Undershoot)
Note: valid for up to 20% of the signal period. See 图 5-1.
0.2*VDD
V
(2)
TJ
Operating junction temperature
range
Automotive
-40
+125
°C
TSTG
Storage temperature range after soldered onto PC Board
I-test(3), All I/Os (if different levels then one line per level)
Over-voltage Test(4), All supplies (if different levels then one line per level)
-55
+150
100
°C
Latch-up I-Test
Latch-up OV-Test
-100
mA
1.5*Vsup
ply max
N/A
V
(1) See I/Os supplied by this power pin in 表 4-2 Ball Characteristics
(2) VDD is the voltage on the corresponding power-supply pin(s) for the IO.
(3) Per JEDEC JESD78 at 125°C with specified I/O pin injection current and clamp voltage of 1.5 times maximum recommended I/O
voltage and negative 0.5 times maximum recommended I/O voltage.
(4) Per JEDEC JESD78 at 125°C.
(5) The maximum valid input voltage on an IO pin cannot exceed 0.3 volts when the supply powering the IO is turned off. This requirement
applies to all the IO pins which are not fail-safe and for all values of IO supply voltage. Special attention should be applied anytime
peripheral devices are not powered from the same power sources used to power the respective IO supply. It is important the attached
peripheral never sources a voltage outside the valid input voltage range, including power supply ramp-up and ramp-down sequences.
Overshoot = 20% of nominal
IO supply voltage
Tovershoot
Nominal IO
supply voltage
Tperiod
Tundershoot
VSS
Undershoot = 20% of nominal
IO supply voltage
osus_sprs851
图 5-1. Tovershoot + Tundershoot < 20% of Tperiod
5.2 ESD Ratings
122
Specifications
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表 5-2. ESD Ratings
VALUE
UNIT
Human-Body model (HBM), per AEC Q100-002(1)
±1000
HDMIPHY Pins
(AG16, AH16, AG19,
AH19, AG18, AH18,
AG17, AH17)
±200
VESD Electrostatic discharge
V
Charged-device model (CDM), per AEC
Q100-011
All Pins (other than
HDMIPHY)
±250
±750
Corner pins (A1,
AH1, A28, AH28)
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
5.3 Power on Hour (POH) Limits
The information in the section below is provided solely for your convenience and does not extend or
modify the warranty provided under TI’s standard terms and conditions for TI semiconductor products.
注
POH is a functional of voltage, temperature and time. Usage at higher voltages and
temperatures will result in a reduction in POH to achieve the same reliability performance.
For assessment of alternate use cases, contact your local TI representative.
表 5-3. Power on Hour (POH) Limits
IP
Duty Cycle
Voltage Domain
Voltage (V)
(max)
Frequency
(MHz) (max)
Tj(°C)
POH
All
100%
All
All Supported OPPs
Automotive Profile(1)
20000
(1) Automotive profile is defined as 20000 power on hours with junction temperature as follows: 5%@-40°C, 65%@70°C, 20%@110°C,
10%@125°C.
5.4 Recommended Operating Conditions
The device is used under the recommended operating conditions described in 表 5-4.
注
Logic functions and parameter values are not assured out of the range specified in the
recommended operating conditions.
表 5-4. Recommended Operating Conditions
PARAMETER
DESCRIPTION
MIN (2)
NOM MAX DC (3)
MAX (2)
UNIT
Input Power Supply Voltage Range
vdd
Core voltage domain supply
Supply voltage range for MPU domain
GPU voltage domain supply
DSP voltage domain supply
IVA voltage domain supply
RTC voltage domain supply
See 节 5.5
See 节 5.5
See 节 5.5
See 节 5.5
See 节 5.5
See 节 5.5
V
V
V
V
V
V
vdd_mpu
vdd_gpu
vdd_dsp
vdd_iva
vdd_rtc
vdda_usb1
DPLL_USB and HS USB1 1.8V
analog power supply
1.71
1.80
50
1.836
1.89
V
Maximum noise (peak-peak)
mVPPmax
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表 5-4. Recommended Operating Conditions (continued)
PARAMETER
vdda_usb2
DESCRIPTION
MIN (2)
NOM MAX DC (3)
MAX (2)
UNIT
V
HS USB2 1.8V analog power supply
Maximum noise (peak-peak)
1.71
1.80
50
1.836
1.89
mVPPmax
vdda33v_usb1
HS USB1 3.3V analog power supply.If
USB1 is not used, this pin can
alternatively be connected to VSS if
the following requirements are met:
- The usb1_dm/usb1_dp pins are left
unconnected
3.135
3.3
50
3.366
3.465
V
mVPPmax
V
- The USB1 PHY is kept powered
down
Maximum noise (peak-peak)
vdda33v_usb2
HS USB2 3.3V analog power supply. If
USB2 is not used, this pin can
alternatively be connected to VSS if
the following requirements are met:
- The usb2_dm/usb2_dp pins are left
unconnected
3.135
1.71
3.3
3.366
1.836
3.465
1.89
- The USB2 PHY is kept powered
down
Maximum noise (peak-peak)
50
1.80
50
mVPPmax
vdda_per
vdda_ddr
PER PLL and PER HSDIVIDER
analog power supply
V
mVPPmax
V
Maximum noise (peak-peak)
DPLL_DDR and DDR HSDIVIDER
analog power supply
1.71
1.71
1.71
1.80
1.836
1.836
1.836
1.89
1.89
1.89
Maximum noise (peak-peak)
DPLL_DEBUG analog power supply
Maximum noise (peak-peak)
50
1.80
50
mVPPmax
V
vdda_debug
mVPPmax
vdda_dsp_iva
DPLL_DSP and DPLL_IVA analog
power supply
1.80
50
V
mVPPmax
V
Maximum noise (peak-peak)
vdda_core_gmac
DPLL_CORE and CORE HSDIVIDER
analog power supply
1.71
1.80
1.836
1.89
Maximum noise (peak-peak)
DPLL_SPARE analog power supply
Maximum noise (peak-peak)
DPLL_GPU analog power supply
Maximum noise (peak-peak)
50
1.80
50
mVPPmax
V
vdda_pll_spare
vdda_gpu
1.71
1.71
1.836
1.836
1.89
1.89
mVPPmax
V
1.80
50
mVPPmax
vdda_hdmi
PLL_HDMI and HDMI analog power
supply
1.71
1.71
1.80
1.836
1.836
1.89
1.89
V
mVPPmax
V
Maximum noise (peak-peak)
50
vdda_pcie
DPLL_PCIe_REF and PCIe analog
power supply
1.80
Maximum noise (peak-peak)
50
1.80
50
mVPPmax
V
vdda_pcie0
vdda_sata
PCIe ch0 RX/TX analog power supply
Maximum noise (peak-peak)
1.71
1.71
1.89
1.89
mVPPmax
DPLL_SATA and SATA RX/TX analog
power supply
1.80
1.836
1.836
1.836
V
mVPPmax
V
Maximum noise (peak-peak)
50
vdda_usb3
vdda_video
DPLL_USB_OTG_SS and USB3.0
RX/TX analog power supply
1.71
1.71
1.80
1.89
1.89
Maximum noise (peak-peak)
DPLL_VIDEO1 analog power supply
Maximum noise (peak-peak)
50
1.80
50
mVPPmax
V
mVPPmax
124
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表 5-4. Recommended Operating Conditions (continued)
PARAMETER
DESCRIPTION
MLBP IO power supply
MIN (2)
NOM MAX DC (3)
MAX (2)
UNIT
V
vdds_mlbp
vdda_mpu_abe
vdda_osc
1.71
1.80
50
1.89
Maximum noise (peak-peak)
DPLL_MPU analog power supply
Maximum noise (peak-peak)
HFOSC analog power supply
Maximum noise (peak-peak)
mVPPmax
V
1.71
1.71
1.71
1.80
50
1.836
1.89
1.89
1.89
mVPPmax
V
1.80
50
mVPPmax
vdda_rtc
RTC bias and RTC LFOSC analog
power supply
1.80
V
Maximum noise (peak-peak)
CSI Interface 1.8v Supply
Maximum noise (peak-peak)
1.8V power supply
50
1.80
50
mVPPmax
V
vdda_csi
1.71
1.71
1.71
1.836
1.836
1.836
1.89
1.89
1.89
mVPPmax
V
vdds18v
1.80
50
Maximum noise (peak-peak)
EMIF1 bias power supply
Maximum noise (peak-peak)
mVPPmax
V
vdds18v_ddr1
vdds_ddr1
1.80
50
mVPPmax
EMIF1 power supply
(1.5V for DDR3 mode /
1.35V DDR3L mode)
1.35-V
Mode
1.28
1.43
1.35
1.377
1.53
1.42
1.57
V
1.5-V Mode
1.50
50
Maximum noise (peak-
peak)
1.35-V
Mode
mVPPmax
1.5-V Mode
1.8-V Mode
3.3-V Mode
vddshv5
vddshv1
vddshv10
vddshv11
vddshv2
Dual Voltage (1.8V or
3.3V) power supply for
the RTC Power Group
pins
1.71
1.80
3.30
1.836
3.366
1.89
3.135
3.465
V
mVPPmax
V
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
1.8-V Mode
3.3-V Mode
50
Dual Voltage (1.8V or
3.3V) power supply for
the VIN2 Power Group
pins
1.71
1.80
3.30
1.836
3.366
1.89
3.135
3.465
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
1.8-V Mode
3.3-V Mode
50
mVPPmax
Dual Voltage (1.8V or
3.3V) power supply for
the GPMC Power Group
pins
1.71
1.80
3.30
1.836
3.366
1.89
3.135
3.465
V
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
1.8-V Mode
3.3-V Mode
50
mVPPmax
Dual Voltage (1.8V or
3.3V) power supply for
the MMC2 Power Group
pins
1.71
1.80
3.30
1.836
3.366
1.89
3.135
3.465
V
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
1.8-V Mode
3.3-V Mode
50
mVPPmax
Dual Voltage (1.8V or
3.3V) power supply for
the VOUT Power Group
pins
1.71
1.80
3.30
1.836
3.366
1.89
3.135
3.465
V
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
50
mVPPmax
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表 5-4. Recommended Operating Conditions (continued)
PARAMETER
vddshv3
DESCRIPTION
MIN (2)
NOM MAX DC (3)
MAX (2)
1.89
UNIT
Dual Voltage (1.8V or
1.8-V Mode
3.3-V Mode
1.71
1.80
3.30
1.836
3.366
3.3V) power supply for
the GENERAL Power
Group pins
3.135
3.465
V
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
1.8-V Mode
3.3-V Mode
50
mVPPmax
vddshv4
vddshv6
vddshv7
vddshv8
vddshv9
Dual Voltage (1.8V or
3.3V) power supply for
the MMC4 Power Group
pins
1.71
1.80
3.30
1.836
3.366
1.89
3.135
3.465
V
mVPPmax
V
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
1.8-V Mode
3.3-V Mode
50
Dual Voltage (1.8V or
3.3V) power supply for
the VIN1 Power Group
pins
1.71
1.80
3.30
1.836
3.366
1.89
3.135
3.465
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
1.8-V Mode
3.3-V Mode
50
mVPPmax
Dual Voltage (1.8V or
3.3V) power supply for
the WIFI Power Group
pins
1.71
1.80
3.30
1.836
3.366
1.89
3.135
3.465
V
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
1.8-V Mode
3.3-V Mode
50
mVPPmax
Dual Voltage (1.8V or
3.3V) power supply for
the MMC1 Power Group
pins
1.71
1.80
3.30
1.836
3.366
1.89
3.135
3.465
V
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
1.8-V Mode
3.3-V Mode
50
mVPPmax
Dual Voltage (1.8V or
3.3V) power supply for
the RGMII Power Group
pins
1.71
1.80
3.30
1.836
3.366
1.89
3.135
3.465
V
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
50
mVPPmax
vss
Ground supply
0
0
V
V
V
V
vssa_hdmi
DPLL_HDMI and HDMI PHY analog
ground
vssa_pcie
vssa_usb
PCIe analog ground
0
0
HS USB1 and HS USB2 analog
ground
vssa_usb3
DPLL_USB and USB3.0 RX/TX
analog ground
0
V
vssa_csi
CSI Interface 0v Supply
SATA TX ground
0
0
0
0
0
V
V
V
V
V
vssa_sata
vssa_video
vssa_osc0
vssa_osc1
DPLL_VIDEO1 analog ground
OSC0 analog ground
OSC1 analog ground
(1)
TJ
Operating junction
temperature range
Automotive
-40
125
°C
V
ddr1_vref0
Reference Power Supply EMIF1
0.5*vdds_ddr1
126
Specifications
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(1) Refer to Power on Hours table 表 5-3 for limitations.
(2) The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This
requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc.
(3) The DC voltage at the device ball should never be above the MAX DC voltage to avoid impact on device reliability and lifetime POH
(Power-On-Hours). The MAX DC voltage is defined as the highest allowed DC regulated voltage, without transients, seen at the ball.
5.5 Operating Performance Points
This section describes the operating conditions of the device. This section also contains the description of
each OPP (operating performance point) for processor clocks and device core clocks.
表 5-5 describes the maximum supported frequency per speed grade for TDA2Ex devices.
表 5-5. Speed Grade Maximum Frequency
Device Speed
Maximum frequency (MHz)
MPU
800
DSP
750
500
IVA
532
430
GPU
532
500
IPU
L3
DDR3/DDR3L
667 (DDR3-1333)
667 (DDR3-1333)
TDA2ExxH
TDA2ExxD
212.8
212.8
266
266
500
(1) N/A in this table stands for Not Applicable.
5.5.1 AVS and ABB Requirements
Adaptive Voltage Scaling (AVS) and Adaptive Body Biasing (ABB) are required on most of the vdd_*
supplies as defined in 表 5-6.
表 5-6. AVS and ABB Requirements per vdd_* Supply
Supply
AVS Required?
Yes, for all OPPs
Yes, for all OPPs
Yes, for all OPPs
Yes, for all OPPs
Yes, for all OPPs
ABB Required?
No
vdd_core
vdd_mpu
vdd_iva
vdd_dsp
vdd_gpu
Yes, for all OPPs
Yes, for all OPPs
Yes, for all OPPs
Yes, for all OPPs
5.5.2 Voltage And Core Clock Specifications
表 5-7 shows the recommended OPP per voltage domain.
表 5-7. Voltage Domains Operating Performance Points (1)
DOMAIN
CONDITION
OPP_NOM
OPP_OD
OPP_HIGH
MIN (3) NOM MAX (3) MIN (3) NOM (2) MAX (3) MIN (3) NOM (2) MAX DC MAX (3)
(2)
(4)
VD_CORE (V) BOOT (Before AVS is
1.11
AVS
1.15
1.2
1.2
Not Applicable
Not Applicable
Not Applicable
(5)
enabled)
After AVS is enabled
AVS
Not Applicable
(5)
Voltage Voltag
(6)
(6)
–
e
3.5%
VD_MPU (V)
BOOT (Before AVS is
1.11
1.15
1.2
1.2
Not Applicable
AVS
Not Applicable
(5)
enabled)
After AVS is enabled
AVS
AVS
AVS
AVS
AVS
AVS
AVS
AVS
(5)
Voltage( Voltag
Voltage( Voltage Voltage( Voltage( Voltage Voltage Voltage(
6)
(6)
6)
(6)
6)
(6)
–
e
–
6) + 5%
–
(6) +2% 6) + 5%
3.5%
3.5%
3.5%
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表 5-7. Voltage Domains Operating Performance Points (1) (continued)
DOMAIN
CONDITION
OPP_NOM
OPP_OD
OPP_HIGH
MIN (3) NOM MAX (3) MIN (3) NOM (2) MAX (3) MIN (3) NOM (2) MAX DC MAX (3)
(2)
(4)
(7)
VD_RTC (V)
Others (V)
-
0.84
0.88
to
1.06
1.2
Not Applicable
Not Applicable
BOOT (Before AVS is
1.02
AVS
1.06
1.2
1.2
Not Applicable
AVS
Not Applicable
(5)
enabled)
After AVS is enabled
AVS
AVS
AVS
AVS
AVS
AVS
AVS
(5)
Voltage Voltag
Voltage Voltage Voltage Voltage Voltage Voltage Voltage
(6)
(6)
(6)
(6)
(6)
(6)
–
e
–
(6) + 5%
–
(6) +2% (6) + 5%
3.5%
3.5%
3.5%
(1) The voltage ranges in this table are preliminary, and final voltage ranges may be different than shown. Systems should be designed with
the ability to modify the voltage to comply with future recommendations.
(2) In a typical implementation, the power supply should target the NOM voltage.
(3) The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This
requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc.
(4) The DC voltage at the device ball should never be above the MAX DC voltage to avoid impact on device reliability and lifetime POH
(Power-On-Hours). The MAX DC voltage is defined as the highest allowed DC regulated voltage, without transients, seen at the ball.
(5) For all OPPs, AVS must be enabled to avoid impact on device reliability, lifetime POH (Power-On-Hours), and device power.
(6) The AVS voltages are device-dependent, voltage domain-dependent, and OPP-dependent. They must be read from the
STD_FUSE_OPP Registers. For information about STD_FUSE_OPP Registers address, please refer to Control Module Section of the
TRM. The power supply should be adjustable over the following ranges for each required OPP:
–
–
–
–
OPP_NOM for MPU: 0.85 V – 1.15 V
OPP_NOM for CORE and Others: 0.85 V - 1.15 V
OPP_OD: 0.94 V - 1.15 V
OPP_HIGH: 1.05 V - 1.25 V
The AVS voltages will be within the above specified ranges.
(7) VD_RTC can optionally be tied to VD_CORE and operate at the VD_CORE AVS voltages.
(8) The power supply must be programmed with the AVS voltages for the MPU and the CORE voltage domain, either just after the ROM
boot or at the earliest possible time in the secondary boot loader before there is significant activity seen on these domains.
表 5-8 describes the standard processor clocks speed characteristics vs OPP of the device.
表 5-8. Supported OPP vs Max Frequency (2)
DESCRIPTION
OPP_NOM
OPP_OD
OPP_HIGH
Max Freq. (MHz)
Max Freq. (MHz)
Max Freq. (MHz)
VD_MPU
VD_DSP
VD_IVA
MPU_CLK
DSP_CLK
IVA_GCLK
GPU_CLK
800
600
800
700
430
500
800
750
532
532
388.3
425.6
VD_GPU
VD_CORE
CORE_IPU1_CLK
212.8
266
N/A
N/A
N/A
N/A
N/A
N/A
L3_CLK
DDR3 / DDR3L
667 (DDR3-1333)
128
Specifications
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
(1) N/A in this table stands for Not Applicable.
(2) Maximum supported frequency is limited according to the Device Speed Grade (see 表 5-5).
5.5.3 Maximum Supported Frequency
Device modules either receive their clock directly from an external clock input, directly from a PLL, or from
a PRCM. 表 5-9 lists the clock source options for each module on this device, along with the maximum
frequency that module can accept. To ensure proper module functionality, the device PLLs and dividers
must be programmed not to exceed the maximum frequencies listed in this table.
表 5-9. Maximum Supported Frequency
Module
Clock Sources
PLL / OSC /
Source Clock
Name
Clock
Type
Max. Clock
Allowed (MHz)
PLL / OSC /
Source Name
Instance Name
Input Clock Name
PRCM Clock Name
AES1
AES2
ATL
AES1_L3_CLK
AES2_L3_CLK
ATL_ICLK_L3
ATLPCLK
Int
Int
266
266
266
266
L4SEC_L3_GICLK
L4SEC_L3_GICLK
ATL_L3_GICLK
ATL_GFCLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_ABE
Int
Func
PER_ABE_X1_GF
CLK
FUNC_32K_CLK
OSC0
RTC Oscillator
DPLL_HDMI
DPLL_VIDEO1
DPLL_CORE
DPLL_CORE
OSC0
HDMI_CLK
VIDEO1_CLK
BB2D_GFCLK
CORE_X2_CLK
SYS_CLK1/610
BB2D
BB2D_FCLK
BB2D_ICLK
Func
Int
354.6
266
BB2D_GFCLK
DSS_L3_GICLK
FUNC_32K_CLK
COUNTER_32K
COUNTER_32K_F
CLK
Func
0.032
COUNTER_32K_IC
LK
Int
Int
38.4
4.8
WKUPAON_GICLK
L3INSTR_TS_GCLK
SYS_CLK1
OSC0
DPLL_ABE_X2_CL
K
DPLL_ABE
CTRL_MODULE_B L3INSTR_TS_GCL
ANDGAP
SYS_CLK1
OSC0
K
DPLL_ABE_X2_CL
K
DPLL_ABE
CTRL_MODULE_C L4CFG_L4_GICLK
ORE
Int
Int
133
L4CFG_L4_GICLK
WKUPAON_GICLK
CORE_X2_CLK
DPLL_CORE
CTRL_MODULE_ WKUPAON_GICLK
WKUP
38.4
SYS_CLK1
OSC0
DPLL_ABE_X2_CL
K
DPLL_ABE
DCAN1
DCAN1_FCLK
DCAN1_ICLK
Func
Int
38.4
266
DCAN1_SYS_CLK
WKUPAON_GICLK
SYS_CLK1
SYS_CLK2
SYS_CLK1
OSC0
OSC1
OSC0
DPLL_ABE_X2_CL
K
DPLL_ABE
DCAN2
DCAN2_FCLK
DCAN2_ICLK
Func
Int
38.4
266
266
DCAN2_SYS_CLK
L4PER2_L3_GICLK
L4SEC_L3_GICLK
EMIF_DLL_GCLK
SYS_CLK1
OSC0
CORE_X2_CLK
CORE_X2_CLK
EMIF_DLL_GCLK
DPLL_CORE
DPLL_CORE
DPLL_DDR
DES3DES
DLL
DES_CLK_L3
Int
EMIF_DLL_FCLK
Func
EMIF_DLL_FC
LK
DLL_AGING
FCLK
Int
38.4
L3INSTR_DLL_AGING
_GCLK
SYS_CLK1
OSC0
DPLL_ABE_X2_CL
K
DPLL_ABE
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Specifications
129
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ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
PLL / OSC /
Source Clock
Name
Clock
Type
Max. Clock
Allowed (MHz)
PLL / OSC /
Source Name
Instance Name
Input Clock Name
PRCM Clock Name
L4SEC_L3_GICLK
L4SEC_L4_GICLK
DMA_CRYPTO
DMA_CRYPTO_FC
LK
Int &
Func
266
133
CORE_X2_CLK
DPLL_CORE
DPLL_CORE
DMA_CRYPTO_IC
LK
Int
CORE_X2_CLK
DMM
DPLL_DEBUG
DSP1
DMM_CLK
SYSCLK
Int
Int
266
38.4
EMIF_L3_GICLK
EMU_SYS_CLK
DSP1_GFCLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
DSP1_FICLK
Int &
Func
DSP_CLK
DSP_GFCLK
DPLL_DSP
DSS
DSS_HDMI_CEC_
CLK
Func
0.032
48
HDMI_CEC_GFCLK
HDMI_PHY_GFCLK
SYS_CLK1/610
OSC0
DSS_HDMI_PHY_
CLK
Func
FUNC_192M_CLK
DPLL_PER
DSS_CLK
Func
Func
192
DSS_GFCLK
DSS_CLK
SYS_CLK1
DPLL_PER
OSC0
HDMI_CLKINP
38.4
HDMI_DPLL_CLK
SYS_CLK2
OSC1
DSS_L3_ICLK
Int
266
DSS_L3_GICLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
VIDEO1_CLKINP
Func
38.4
VIDEO1_DPLL_CLK
SYS_CLK2
OSC1
VIDEO2_CLKINP
Func
Func
Func
38.4
209.3
209.3
VIDEO2_DPLL_CLK
SYS_CLK1
OSC0
SYS_CLK2
OSC1
DPLL_DSI1_A_CL
K1
N/A
N/A
HDMI_CLK
DPLL_HDMI
DPLL_VIDEO1
DPLL_VIDEO1
DPLL_HDMI
DPLL_ABE
VIDEO1_CLKOUT1
VIDEO1_CLKOUT3
HDMI_CLK
DPLL_DSI1_B_CL
K1
DPLL_ABE_X2_CL
K
DPLL_DSI1_C_CL
K1
Func
209.3
N/A
HDMI_CLK
VIDEO1_CLKOUT3
HDMI_CLK
DPLL_HDMI
DPLL_VIDEO1
DPLL_HDMI
DPLL_HDMI_CLK1
LCD1_CLK
Func
Func
185.6
209.3
N/A
N/A
DSS DISPC
DPLL_DSI1_A_CL
K1
See DSS data in
the rows above
DSS_CLK
LCD2_CLK
LCD3_CLK
F_CLK
Func
Func
Func
209.3
209.3
209.3
N/A
N/A
N/A
DPLL_DSI1_B_CL
K1
DSS_CLK
DPLL_DSI1_C_CL
K1
DSS_CLK
DPLL_DSI1_A_CL
K1
DPLL_DSI1_B_CL
K1
DPLL_DSI1_C_CL
K1
DSS_CLK
DPLL_HDMI_CLK1
130
Specifications
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 5-9. Maximum Supported Frequency (continued)
Module
Input Clock Name
ocp_clk
Clock Sources
PLL / OSC /
Source Clock
Name
Clock
Type
Max. Clock
Allowed (MHz)
PLL / OSC /
Source Name
Instance Name
PRCM Clock Name
EFUSE_CTRL_CU
ST
Int
133
CUSTEFUSE_L4_GICL
K
CORE_X2_CLK
DPLL_CORE
OSC0
sys_clk
Func
38.4
CUSTEFUSE_SYS_GF
CLK
SYS_CLK1
ELM
EMIF_OCP_FW
EMIF_PHY1
EMIF1
ELM_ICLK
L3_CLK
Int
Int
266
266
DDR
266
266
L4PER_L3_GICLK
EMIF_L3_GICLK
EMIF_PHY_GCLK
EMIF_L3_GICLK
L4SEC_L3_GICLK
CORE_X2_CLK
CORE_X2_CLK
EMIF_PHY_GCLK
CORE_X2_CLK
CORE_X2_CLK
DPLL_CORE
DPLL_CORE
DPLL_DDR
EMIF_PHY1_FCLK
EMIF1_ICLK
PKA_CLK
Func
Int
DPLL_CORE
DPLL_CORE
FPKA
Int &
Func
GMAC_SW
CPTS_RFT_CLK
Func
266
GMAC_RFT_CLK
PER_ABE_X1_GF
CLK
DPLL_ABE
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
DPLL_GMAC
DPLL_GMAC
CORE_X2_CLK
GMAC_250M_CLK
MAIN_CLK
Int
125
250
GMAC_MAIN_CLK
GMII_250MHZ_CLK
MHZ_250_CLK
Func
GMII_250MHZ_CL
K
MHZ_5_CLK
MHZ_50_CLK
Func
Func
Func
Func
Int
5
50
RGMII_5MHZ_CLK
RMII_50MHZ_CLK
RMII_50MHZ_CLK
RMII_50MHZ_CLK
WKUPAON_GICLK
GMAC_RMII_HS_C
LK
DPLL_GMAC
DPLL_GMAC
DPLL_GMAC
DPLL_GMAC
GMAC_RMII_HS_C
LK
RMII1_MHZ_50_CL
K
50
GMAC_RMII_HS_C
LK
RMII2_MHZ_50_CL
K
50
GMAC_RMII_HS_C
LK
GPIO1
GPIO1_ICLK
38.4
SYS_CLK1
OSC0
DPLL_ABE_X2_CL
K
DPLL_ABE
GPIO1_DBCLK
Func
0.032
WKUPAON_SYS_GFC WKUPAON_32K_G
OSC0
LK
FCLK
RTC Oscillator
DPLL_CORE
OSC0
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO2_ICLK
Int
266
L4PER_L3_GICLK
GPIO_GFCLK
CORE_X2_CLK
FUNC_32K_CLK
GPIO2_DBCLK
Func
0.032
RTC Oscillator
DPLL_CORE
OSC0
GPIO3_ICLK
Int
266
L4PER_L3_GICLK
GPIO_GFCLK
CORE_X2_CLK
FUNC_32K_CLK
GPIO3_DBCLK
Func
0.032
RTC Oscillator
DPLL_CORE
OSC0
GPIO4_ICLK
GPIO4_DBCLK
PIDBCLK
Int
266
0.032
0.032
266
L4PER_L3_GICLK
GPIO_GFCLK
CORE_X2_CLK
FUNC_32K_CLK
Func
Func
Int
GPIO_GFCLK
RTC Oscillator
DPLL_CORE
OSC0
GPIO5_ICLK
GPIO5_DBCLK
PIDBCLK
L4PER_L3_GICLK
GPIO_GFCLK
CORE_X2_CLK
FUNC_32K_CLK
Func
Func
Int
0.032
0.032
266
GPIO_GFCLK
RTC Oscillator
DPLL_CORE
OSC0
GPIO6_ICLK
GPIO6_DBCLK
PIDBCLK
L4PER_L3_GICLK
GPIO_GFCLK
CORE_X2_CLK
FUNC_32K_CLK
Func
Func
0.032
0.032
GPIO_GFCLK
RTC Oscillator
版权 © 2016–2018, Texas Instruments Incorporated
Specifications
131
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
PLL / OSC /
Source Clock
Name
Clock
Type
Max. Clock
Allowed (MHz)
PLL / OSC /
Source Name
Instance Name
Input Clock Name
PRCM Clock Name
GPIO7
GPIO7_ICLK
GPIO7_DBCLK
PIDBCLK
Int
266
0.032
0.032
266
L4PER_L3_GICLK
GPIO_GFCLK
CORE_X2_CLK
FUNC_32K_CLK
DPLL_CORE
OSC0
Func
Func
Int
GPIO_GFCLK
RTC Oscillator
DPLL_CORE
OSC0
GPIO8
GPIO8_ICLK
GPIO8_DBCLK
PIDBCLK
L4PER_L3_GICLK
GPIO_GFCLK
CORE_X2_CLK
FUNC_32K_CLK
Func
Func
Int
0.032
0.032
266
GPIO_GFCLK
RTC Oscillator
DPLL_CORE
DPLL_CORE
DPLL_PER
DPLL_GPU
DPLL_CORE
DPLL_PER
DPLL_GPU
DPLL_CORE
DPLL_PER
GPMC
GPU
GPMC_FCLK
GPU_FCLK1
L3MAIN1_L3_GICLK
GPU_CORE_GCLK
CORE_X2_CLK
CORE_GPU_CLK
PER_GPU_CLK
GPU_GCLK
Func
GPU_CLK
GPU_FCLK2
GPU_ICLK
Func
GPU_CLK
GPU_HYD_GCLK
CORE_GPU_CLK
PER_GPU_CLK
GPU_GCLK
Int
266
GPU_L3_GICLK
CORE_X2_CLK
FUNC_192M_CLK
HDMI PHY
HDQ1W
DSS_HDMI_PHY_
CLK
Func
38.4
HDMI_PHY_GFCLK
HDQ1W_ICLK
Int &
Func
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
HDQ1W_FCLK
I2C1_ICLK
I2C1_FCLK
I2C2_ICLK
I2C2_FCLK
I2C3_ICLK
I2C3_FCLK
I2C4_ICLK
I2C4_FCLK
I2C5_ICLK
I2C5_FCLK
I2C6_ICLK
I2C6_FCLK
PI_L3CLK
Func
Int
12
266
96
PER_12M_GFCLK
L4PER_L3_GICLK
PER_96M_GFCLK
L4PER_L3_GICLK
PER_96M_GFCLK
L4PER_L3_GICLK
PER_96M_GFCLK
L4PER_L3_GICLK
PER_96M_GFCLK
IPU_L3_GICLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
I2C1
I2C2
I2C3
I2C4
I2C5
I2C6
Func
Int
266
96
Func
Int
266
96
Func
Int
266
96
Func
Int
266
96
Func
Int
IPU_96M_GFCLK
L4PER2_L3_GICLK
IPU_96M_GFCLK
L3INIT_L3_GICLK
266
96
Func
IEEE1500_2_OCP
IPU1
Int &
Func
266
IPU1_GFCLK
Int &
Func
425.6
IPU1_GFCLK
DPLL_ABE_X2_CL
K
DPLL_ABE
DPLL_CORE
DPLL_CORE
CORE_IPU_ISS_B
OOST_CLK
IPU2
IPU2_GFCLK
Int &
Func
425.6
IPU2_GFCLK
IVA_GCLK
CORE_IPU_ISS_B
OOST_CLK
IVA
IVA_GCLK
KBD_FCLK
Int
IVA_GCLK
0.032
IVA_GFCLK
DPLL_IVA
OSC0
KBD
Func
WKUPAON_SYS_GFC WKUPAON_32K_G
LK
FCLK
PICLKKBD
Func
0.032
WKUPAON_SYS_GFC
LK
RTC Oscillator
KBD_ICLK
PICLKOCP
Int
Int
38.4
38.4
WKUPAON_GICLK
WKUPAON_GICLK
SYS_CLK1
OSC0
DPLL_ABE_X2_CL
K
DPLL_ABE
L3_INSTR
L3_CLK
Int
L3_CLK
L3INSTR_L3_GICLK
CORE_X2_CLK
DPLL_CORE
132
Specifications
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
PLL / OSC /
Source Clock
Name
Clock
Type
Max. Clock
Allowed (MHz)
PLL / OSC /
Source Name
Instance Name
Input Clock Name
PRCM Clock Name
L3_MAIN
L3_CLK1
L3_CLK2
Int
Int
Int
Int
Int
Int
Int
L3_CLK
L3_CLK
133
L3MAIN1_L3_GICLK
L3INSTR_L3_GICLK
L4CFG_L3_GICLK
L4PER_L3_GICLK
L4PER2_L3_GICLK
L4PER3_L3_GICLK
WKUPAON_GICLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
OSC0
L4_CFG
L4_PER1
L4_PER2
L4_PER3
L4_WKUP
L4_CFG_CLK
L4_PER1_CLK
L4_PER2_CLK
L4_PER3_CLK
L4_WKUP_CLK
133
133
133
38.4
DPLL_ABE_X2_CL
K
DPLL_ABE
MAILBOX1
MAILBOX2
MAILBOX3
MAILBOX4
MAILBOX5
MAILBOX6
MAILBOX7
MAILBOX8
MAILBOX9
MAILBOX10
MAILBOX11
MAILBOX12
MAILBOX13
MAILBOX1_FLCK
MAILBOX2_FLCK
MAILBOX3_FLCK
MAILBOX4_FLCK
MAILBOX5_FLCK
MAILBOX6_FLCK
MAILBOX7_FLCK
MAILBOX8_FLCK
MAILBOX9_FLCK
MAILBOX10_FLCK
MAILBOX11_FLCK
MAILBOX12_FLCK
MAILBOX13_FLCK
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
266
266
266
266
266
266
266
266
266
266
266
266
266
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
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Specifications
133
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 5-9. Maximum Supported Frequency (continued)
Module
Input Clock Name
MCASP1_AHCLKR
Clock Sources
PLL / OSC /
Source Clock
Name
Clock
Type
Max. Clock
Allowed (MHz)
PLL / OSC /
Source Name
Instance Name
PRCM Clock Name
MCASP1
Func
100
MCASP1_AHCLKR
ABE_24M_GFCLK
ABE_SYS_CLK
DPLL_ABE
OSC0
FUNC_24M_GFCL
K
DPLL_PER
ATL_CLK0
ATL_CLK1
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
ATL_CLK2
ATL_CLK3
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
OSC0
MLBP_CLK
ABE_24M_GFCLK
ABE_SYS_CLK
MCASP1_AHCLKX
Func
100
MCASP1_AHCLKX
FUNC_24M_GFCL
K
DPLL_PER
ATL_CLK0
ATL_CLK1
ATL_CLK2
ATL_CLK3
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
MLBP_CLK
MCASP1_FCLK
MCASP1_ICLK
Func
Int
192
266
MCASP1_AUX_GFCLK PER_ABE_X1_GF
CLK
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
IPU_L3_GICLK
CORE_X2_CLK
134
Specifications
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 5-9. Maximum Supported Frequency (continued)
Module
Input Clock Name
MCASP2_AHCLKR
Clock Sources
PLL / OSC /
Source Clock
Name
Clock
Type
Max. Clock
Allowed (MHz)
PLL / OSC /
Source Name
Instance Name
PRCM Clock Name
MCASP2
Func
100
MCASP2_AHCLKR
ABE_24M_GFCLK
ABE_SYS_CLK
DPLL_ABE
OSC0
FUNC_24M_GFCL
K
DPLL_PER
ATL_CLK3
ATL_CLK2
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
ATL_CLK1
ATL_CLK0
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
OSC0
MLBP_CLK
ABE_24M_GFCLK
ABE_SYS_CLK
MCASP2_AHCLKX
Func
100
MCASP2_AHCLKX
FUNC_24M_GFCL
K
DPLL_PER
ATL_CLK3
ATL_CLK2
ATL_CLK1
ATL_CLK0
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
MLBP_CLK
MCASP2_FCLK
MCASP2_ICLK
Func
Int
192
266
MCASP2_AUX_GFCLK PER_ABE_X1_GF
CLK
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
L4PER2_L3_GICLK
CORE_X2_CLK
版权 © 2016–2018, Texas Instruments Incorporated
Specifications
135
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 5-9. Maximum Supported Frequency (continued)
Module
Input Clock Name
MCASP3_AHCLKX
Clock Sources
PLL / OSC /
Source Clock
Name
Clock
Type
Max. Clock
Allowed (MHz)
PLL / OSC /
Source Name
Instance Name
PRCM Clock Name
MCASP3
Func
100
MCASP3_AHCLKX
ABE_24M_GFCLK
ABE_SYS_CLK
DPLL_ABE
OSC0
FUNC_24M_GFCL
K
DPLL_PER
ATL_CLK3
ATL_CLK2
ATL_CLK1
ATL_CLK0
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
MLBP_CLK
MCASP3_FCLK
Func
192
MCASP3_AUX_GFCLK PER_ABE_X1_GF
CLK
VIDEO1_CLK
HDMI_CLK
DPLL_ABE
DPLL_HDMI
DPLL_CORE
DPLL_ABE
OSC0
MCASP3_ICLK
Int
266
100
L4PER2_L3_GICLK
MCASP4_AHCLKX
CORE_X2_CLK
ABE_24M_GFCLK
ABE_SYS_CLK
MCASP4
MCASP4_AHCLKX
Func
FUNC_24M_GFCL
K
DPLL_PER
ATL_CLK3
ATL_CLK2
ATL_CLK1
ATL_CLK0
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
MLBP_CLK
MCASP4_FCLK
MCASP4_ICLK
Func
Int
192
266
MCASP4_AUX_GFCLK PER_ABE_X1_GF
CLK
VIDEO1_CLK
HDMI_CLK
DPLL_ABE
DPLL_HDMI
DPLL_CORE
L4PER2_L3_GICLK
CORE_X2_CLK
136
Specifications
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 5-9. Maximum Supported Frequency (continued)
Module
Input Clock Name
MCASP5_AHCLKX
Clock Sources
PLL / OSC /
Source Clock
Name
Clock
Type
Max. Clock
Allowed (MHz)
PLL / OSC /
Source Name
Instance Name
PRCM Clock Name
MCASP5
Func
100
MCASP5_AHCLKX
ABE_24M_GFCLK
ABE_SYS_CLK
DPLL_ABE
OSC0
FUNC_24M_GFCL
K
DPLL_PER
ATL_CLK3
ATL_CLK2
ATL_CLK1
ATL_CLK0
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
MLBP_CLK
MCASP5_FCLK
Func
192
MCASP5_AUX_GFCLK PER_ABE_X1_GF
CLK
VIDEO1_CLK
HDMI_CLK
DPLL_ABE
DPLL_HDMI
DPLL_CORE
DPLL_ABE
DPLL_PER
MCASP5_ICLK
Int
266
100
L4PER2_L3_GICLK
MCASP6_AHCLKX
CORE_X2_CLK
MCASP6
MCASP6_AHCLKX
Func
ABE_24M_GFCLK
FUNC_24M_GFCL
K
ATL_CLK3
ATL_CLK2
Module ATL
Module ATL
Module ATL
Module ATL
Module MLB
Module MLB
OSC0
ATL_CLK1
ATL_CLK0
MLB_CLK
MLBP_CLK
ABE_SYS_CLK
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
MCASP6_FCLK
MCASP6_ICLK
Func
Int
192
266
MCASP6_AUX_GFCLK PER_ABE_X1_GF
CLK
VIDEO1_CLK
HDMI_CLK
DPLL_ABE
DPLL_HDMI
DPLL_CORE
L4PER2_L3_GICLK
CORE_X2_CLK
版权 © 2016–2018, Texas Instruments Incorporated
Specifications
137
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 5-9. Maximum Supported Frequency (continued)
Module
Input Clock Name
MCASP7_AHCLKX
Clock Sources
PLL / OSC /
Source Clock
Name
Clock
Type
Max. Clock
Allowed (MHz)
PLL / OSC /
Source Name
Instance Name
PRCM Clock Name
MCASP7
Func
100
MCASP7_AHCLKX
ABE_24M_GFCLK
ABE_SYS_CLK
DPLL_ABE
OSC0
FUNC_24M_GFCL
K
DPLL_PER
ATL_CLK3
ATL_CLK2
ATL_CLK1
ATL_CLK0
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
MLBP_CLK
MCASP7_FCLK
Func
192
MCASP7_AUX_GFCLK PER_ABE_X1_GF
CLK
VIDEO1_CLK
HDMI_CLK
DPLL_ABE
DPLL_HDMI
DPLL_CORE
DPLL_ABE
OSC0
MCASP7_ICLK
Int
266
100
L4PER2_L3_GICLK
MCASP8_AHCLKX
CORE_X2_CLK
ABE_24M_GFCLK
ABE_SYS_CLK
MCASP8
MCASP8_AHCLKX
Func
FUNC_24M_GFCL
K
DPLL_PER
ATL_CLK3
ATL_CLK2
ATL_CLK1
ATL_CLK0
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
MLBP_CLK
MCASP8_FCLK
Func
192
MCASP8_AUX_GFCLK PER_ABE_X1_GF
CLK
VIDEO1_CLK
HDMI_CLK
DPLL_ABE
DPLL_HDMI
DPLL_CORE
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
MCASP8_ICLK
SPI1_ICLK
SPI1_FCLK
SPI2_ICLK
SPI2_FCLK
SPI3_ICLK
SPI3_FCLK
Int
Int
266
266
48
L4PER2_L3_GICLK
L4PER_L3_GICLK
PER_48M_GFCLK
L4PER_L3_GICLK
PER_48M_GFCLK
L4PER_L3_GICLK
PER_48M_GFCLK
CORE_X2_CLK
CORE_X2_CLK
PER_48M_GFCLK
CORE_X2_CLK
PER_48M_GFCLK
CORE_X2_CLK
PER_48M_GFCLK
MCSPI1
MCSPI2
MCSPI3
Func
Int
266
48
Func
Int
266
48
Func
138
Specifications
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
PLL / OSC /
Source Clock
Name
Clock
Type
Max. Clock
Allowed (MHz)
PLL / OSC /
Source Name
Instance Name
Input Clock Name
PRCM Clock Name
MCSPI4
SPI4_ICLK
SPI4_FCLK
MLB_L3_ICLK
MLB_L4_ICLK
MLB_FCLK
CTRLCLK
Int
Func
Int
266
48
L4PER_L3_GICLK
PER_48M_GFCLK
CORE_X2_CLK
PER_48M_GFCLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
DPLL_CORE
DPLL_PER
MLB_SS
CSI2_0
266
133
266
96
MLB_SHB_L3_GICLK
MLB_SPB_L4_GICLK
MLB_SYS_L3_GFCLK
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_PER
Int
Func
Int &
Func
LVDSRX_96M_GFCLK FUNC_192M_CLK
CAL_FCLK
Int &
Func
266
CAL_GICLK
CORE_ISS_MAIN_
CLK
DPLL_CORE
L3_ICLK
CM_CORE_AON
DPLL_PER
CSI2_1
MMC1
CTRLCLK
Int &
Func
96
LVDSRX_96M_GFCLK FUNC_192M_CLK
CAL_FCLK
Int &
Func
266
CAL_GICLK
CORE_ISS_MAIN_
CLK
DPLL_CORE
L3_ICLK
CM_CORE_AON
OSC0
MMC1_CLK_32K
MMC1_FCLK
Func
Func
0.032
192
L3INIT_32K_GFCLK
MMC1_GFCLK
FUNC_32K_CLK
FUNC_192M_CLK
FUNC_256M_CLK
CORE_X2_CLK
CORE_X2_CLK
FUNC_32K_CLK
FUNC_192M_CLK
FUNC_256M_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
FUNC_32K_CLK
FUNC_192M_CLK
DPLL_PER
DPLL_PER
DPLL_CORE
DPLL_CORE
OSC0
128
MMC1_ICLK1
MMC1_ICLK2
MMC2_CLK_32K
MMC2_FCLK
Int
Int
266
L3INIT_L3_GICLK
L3INIT_L4_GICLK
L3INIT_32K_GFCLK
MMC2_GFCLK
133
MMC2
Func
Func
0.032
192
DPLL_PER
DPLL_PER
DPLL_CORE
DPLL_CORE
DPLL_CORE
OSC0
128
MMC2_ICLK1
MMC2_ICLK2
MMC3_ICLK
Int
Int
266
L3INIT_L3_GICLK
L3INIT_L4_GICLK
L4PER_L3_GICLK
L4PER_32K_GFCLK
MMC3_GFCLK
133
MMC3
MMC4
Int
266
MMC3_CLK_32K
MMC3_FCLK
Func
Func
0.032
48
DPLL_PER
192
MMC4_ICLK
MMC4_CLK_32K
MMC4_FCLK
Int
266
L4PER_L3_GICLK
L4PER_32K_GFCLK
MMC4_GFCLK
CORE_X2_CLK
FUNC_32K_CLK
FUNC_192M_CLK
DPLL_CORE
OSC0
Func
Func
0.032
48
DPLL_PER
192
MMU_EDMA
MMU_PCIESS
MPU
MMU1_CLK
MMU2_CLK
MPU_CLK
Int
Int
266
L3MAIN1_L3_GICLK
L3MAIN1_L3_GICLK
MPU_GCLK
CORE_X2_CLK
CORE_X2_CLK
MPU_GCLK
DPLL_CORE
DPLL_CORE
DPLL_MPU
266
Int &
Func
MPU_CLK
MPU_EMU_DBG
FCLK
Int
38.4
EMU_SYS_CLK
SYS_CLK1
MPU_GCLK
OSC0
DPLL_MPU
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
OCMC_RAM1
OCMC_ROM
OCP_WP_NOC
OCP2SCP1
OCMC1_L3_CLK
OCMC_L3_CLK
PICLKOCPL3
Int
Int
Int
Int
266
266
266
133
L3MAIN1_L3_GICLK
L3MAIN1_L3_GICLK
L3INSTR_L3_GICLK
L3INIT_L4_GICLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
L4CFG1_ADAPTE
R_CLKIN
OCP2SCP2
L4CFG2_ADAPTE
R_CLKIN
Int
133
L4CFG_L4_GICLK
CORE_X2_CLK
DPLL_CORE
版权 © 2016–2018, Texas Instruments Incorporated
Specifications
139
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
PLL / OSC /
Source Clock
Name
Clock
Type
Max. Clock
Allowed (MHz)
PLL / OSC /
Source Name
Instance Name
OCP2SCP3
PCIESS1
Input Clock Name
PRCM Clock Name
L3INIT_L4_GICLK
PCIE_32K_GFCLK
L4CFG3_ADAPTE
R_CLKIN
Int
133
CORE_X2_CLK
DPLL_CORE
RTC Oscillator
PCIE1_PHY_WKU
P_CLK
Func
0.032
FUNC_32K_CLK
PCIe_SS1_FICLK
PCIEPHY_CLK
Int
266
2500
1250
PCIE_L3_GICLK
PCIE_PHY_GCLK
CORE_X2_CLK
DPLL_CORE
APLL_PCIE
APLL_PCIE
Func
Func
PCIE_PHY_GCLK
PCIEPHY_CLK_DI
V
PCIE_PHY_DIV_GCLK PCIE_PHY_DIV_G
CLK
PCIE1_REF_CLKI
N
Func
34.3
PCIE_REF_GFCLK
CORE_USB_OTG_
SS_LFPS_TX_CLK
DPLL_CORE
PCIE1_PWR_CLK
Func
Func
38.4
PCIE_SYS_GFCLK
PCIE_32K_GFCLK
SYS_CLK1
OSC0
PCIESS2
PCIE2_PHY_WKU
P_CLK
0.032
FUNC_32K_CLK
RTC Oscillator
PCIe_SS2_FICLK
PCIEPHY_CLK
Func
Func
Func
266
2500
1250
PCIE_L3_GICLK
PCIE_PHY_GCLK
CORE_X2_CLK
DPLL_CORE
APLL_PCIE
APLL_PCIE
PCIE_PHY_GCLK
PCIEPHY_CLK_DI
V
PCIE_PHY_DIV_GCLK PCIE_PHY_DIV_G
CLK
PCIE2_REF_CLKI
N
Func
34.3
PCIE_REF_GFCLK
CORE_USB_OTG_
SS_LFPS_TX_CLK
DPLL_CORE
PCIE2_PWR_CLK
32K_CLK
Func
Func
Func
38.4
0.032
38.4
PCIE_SYS_GFCLK
FUNC_32K_CLK
WKUPAON_ICLK
SYS_CLK1
SYS_CLK1/610
SYS_CLK1
OSC0
OSC0
PRCM_MPU
SYS_CLK
OSC0
DPLL_ABE_X2_CL
K
DPLL_ABE
PWMSS1
PWMSS2
PWMSS3
QSPI
PWMSS1_GICLK
PWMSS2_GICLK
PWMSS3_GICLK
Int &
Func
266
266
266
L4PER2_L3_GICLK
L4PER2_L3_GICLK
L4PER2_L3_GICLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
DPLL_CORE
DPLL_CORE
DPLL_CORE
Int &
Func
Int &
Func
QSPI_ICLK
QSPI_FCLK
Int
266
128
L4PER2_L3_GICLK
QSPI_GFCLK
CORE_X2_CLK
FUNC_256M_CLK
PER_QSPI_CLK
CORE_X2_CLK
CORE_X2_CLK
SYS_32K
DPLL_CORE
DPLL_PER
DPLL_PER
DPLL_CORE
DPLL_CORE
RTC Oscillator
OSC0
Func
RNG
RNG_ICLK
RTC_ICLK
RTC_FCLK
Int
Int
266
133
L4SEC_L3_GICLK
RTC_L4_GICLK
RTC_AUX_CLK
FUNC_32K_CLK
L4CFG_L3_GICLK
RTC_SS
Func
RTC_FCLK
SYS_CLK1/610
CORE_X2_CLK
SAR_ROM
SATA
PRCM_ROM_CLO
CK
Int
266
DPLL_CORE
SATA_FICLK
Int
266
48
L3INIT_L3_GICLK
CORE_X2_CLK
DPLL_CORE
DPLL_PER
SATA_PMALIVE_F
CLK
Func
L3INIT_48M_GFCLK
FUNC_192M_CLK
REF_CLK
Func
38
SATA_REF_GFCLK
DMA_L3_GICLK
SYS_CLK1
OSC0
SDMA
SDMA_FCLK
Int &
Func
266
CORE_X2_CLK
DPLL_CORE
SHA2MD51
SHA2MD52
SL2
SHAM_1_CLK
SHAM_2_CLK
IVA_GCLK
Int
Int
Int
266
266
L4SEC_L3_GICLK
L4SEC_L3_GICLK
IVA_GCLK
CORE_X2_CLK
CORE_X2_CLK
IVA_GFCLK
DPLL_CORE
DPLL_CORE
DPLL_IVA
IVA_GCLK
140
Specifications
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
PLL / OSC /
Source Clock
Name
Clock
Type
Max. Clock
Allowed (MHz)
PLL / OSC /
Source Name
Instance Name
Input Clock Name
PRCM Clock Name
SMARTREFLEX_C
ORE
MCLK
Int
133
COREAON_L4_GICLK
WKUPAON_ICLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
SYSCLK
Func
38.4
DPLL_ABE_X2_CL
K
DPLL_ABE
SMARTREFLEX_D
SP
MCLK
Int
133
COREAON_L4_GICLK
WKUPAON_ICLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
SYSCLK
Func
38.4
DPLL_ABE_X2_CL
K
DPLL_ABE
SMARTREFLEX_G
PU
MCLK
Int
133
COREAON_L4_GICLK
WKUPAON_ICLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
SYSCLK
Func
38.4
DPLL_ABE_X2_CL
K
DPLL_ABE
SMARTREFLEX_IV
AHD
MCLK
Int
133
COREAON_L4_GICLK
WKUPAON_ICLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
SYSCLK
Func
38.4
DPLL_ABE_X2_CL
K
DPLL_ABE
SMARTREFLEX_M
PU
MCLK
Int
133
COREAON_L4_GICLK
WKUPAON_ICLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
SYSCLK
Func
38.4
DPLL_ABE_X2_CL
K
DPLL_ABE
SPINLOCK
TIMER1
SPINLOCK_ICLK
TIMER1_ICLK
Int
Int
266
L4CFG_L3_GICLK
WKUPAON_GICLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
38.4
DPLL_ABE_X2_CL
K
DPLL_ABE
TIMER1_FCLK
Func
100
TIMER1_GFCLK
SYS_CLK1
OSC0
OSC0
FUNC_32K_CLK
RTC Oscillator
OSC1
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
版权 © 2016–2018, Texas Instruments Incorporated
Specifications
141
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
PLL / OSC /
Source Clock
Name
Clock
Type
Max. Clock
Allowed (MHz)
PLL / OSC /
Source Name
Instance Name
Input Clock Name
PRCM Clock Name
TIMER2
TIMER2_ICLK
TIMER2_FCLK
Int
266
100
L4PER_L3_GICLK
TIMER2_GFCLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
Func
FUNC_32K_CLK
OSC0
RTC Oscillator
OSC1
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
OSC0
TIMER3
TIMER3_ICLK
TIMER3_FCLK
Int
266
100
L4PER_L3_GICLK
TIMER3_GFCLK
CORE_X2_CLK
SYS_CLK1
Func
FUNC_32K_CLK
OSC0
RTC Oscillator
OSC1
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
OSC0
TIMER4
TIMER4_ICLK
TIMER4_FCLK
Int
266
100
L4PER_L3_GICLK
TIMER4_GFCLK
CORE_X2_CLK
SYS_CLK1
Func
FUNC_32K_CLK
OSC0
RTC Oscillator
OSC1
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
142
Specifications
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
PLL / OSC /
Source Clock
Name
Clock
Type
Max. Clock
Allowed (MHz)
PLL / OSC /
Source Name
Instance Name
Input Clock Name
PRCM Clock Name
TIMER5
TIMER5_ICLK
TIMER5_FCLK
Int
266
100
IPU_L3_GICLK
TIMER5_GFCLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
Func
FUNC_32K_CLK
OSC0
RTC Oscillator
OSC1
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
CLKOUTMUX[0]
DPLL_CORE
OSC0
CLKOUTMUX[0]
CORE_X2_CLK
SYS_CLK1
TIMER6
TIMER6_ICLK
TIMER6_FCLK
Int
266
100
IPU_L3_GICLK
TIMER6_GFCLK
Func
FUNC_32K_CLK
OSC0
RTC Oscillator
OSC1
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
CLKOUTMUX[0]
DPLL_CORE
OSC0
CLKOUTMUX[0]
CORE_X2_CLK
SYS_CLK1
TIMER7
TIMER7_ICLK
TIMER7_FCLK
Int
266
100
IPU_L3_GICLK
TIMER7_GFCLK
Func
FUNC_32K_CLK
OSC0
RTC Oscillator
OSC1
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
CLKOUTMUX[0]
CLKOUTMUX[0]
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Specifications
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表 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
PLL / OSC /
Source Clock
Name
Clock
Type
Max. Clock
Allowed (MHz)
PLL / OSC /
Source Name
Instance Name
Input Clock Name
PRCM Clock Name
TIMER8
TIMER8_ICLK
TIMER8_FCLK
Int
266
100
IPU_L3_GICLK
TIMER8_GFCLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
Func
FUNC_32K_CLK
OSC0
RTC Oscillator
OSC1
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
CLKOUTMUX[0]
DPLL_CORE
OSC0
CLKOUTMUX[0]
CORE_X2_CLK
SYS_CLK1
TIMER9
TIMER9_ICLK
TIMER9_FCLK
Int
266
100
L4PER_L3_GICLK
TIMER9_GFCLK
Func
FUNC_32K_CLK
OSC0
RTC Oscillator
OSC1
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
OSC0
TIMER10
TIMER10_ICLK
TIMER10_FCLK
Int
266
100
L4PER_L3_GICLK
TIMER10_GFCLK
CORE_X2_CLK
SYS_CLK1
Func
FUNC_32K_CLK
OSC0
RTC Oscillator
OSC1
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
144
Specifications
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
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ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
PLL / OSC /
Source Clock
Name
Clock
Type
Max. Clock
Allowed (MHz)
PLL / OSC /
Source Name
Instance Name
Input Clock Name
PRCM Clock Name
TIMER11
TIMER11_ICLK
TIMER11_FCLK
Int
266
100
L4PER_L3_GICLK
TIMER11_GFCLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
Func
FUNC_32K_CLK
OSC0
RTC Oscillator
OSC1
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
SYS_CLK1
DPLL_VIDEO1
DPLL_HDMI
OSC0
TIMER12
TIMER13
TIMER12_ICLK
Int
38.4
WKUPAON_GICLK
DPLL_ABE_X2_CL
K
DPLL_ABE
TIMER12_FCLK
TIMER13_ICLK
TIMER13_FCLK
Func
Int
0.032
266
OSC_32K_CLK
L4PER3_L3_GICLK
TIMER13_GFCLK
RC_CLK
RC oscillator
DPLL_CORE
OSC0
CORE_X2_CLK
SYS_CLK1
Func
100
FUNC_32K_CLK
OSC0
RTC Oscillator
OSC1
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
OSC0
TIMER14
TIMER14_ICLK
TIMER14_FCLK
Int
266
100
L4PER3_L3_GICLK
TIMER14_GFCLK
CORE_X2_CLK
SYS_CLK1
Func
FUNC_32K_CLK
OSC0
RTC Oscillator
OSC1
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
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Specifications
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www.ti.com.cn
表 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
PLL / OSC /
Source Clock
Name
Clock
Type
Max. Clock
Allowed (MHz)
PLL / OSC /
Source Name
Instance Name
Input Clock Name
PRCM Clock Name
TIMER15
TIMER15_ICLK
TIMER15_FCLK
Int
266
100
L4PER3_L3_GICLK
TIMER15_GFCLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
Func
FUNC_32K_CLK
OSC0
RTC Oscillator
OSC1
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
OSC0
TIMER16
TIMER16_ICLK
TIMER16_FCLK
Int
266
100
L4PER3_L3_GICLK
TIMER16_GFCLK
CORE_X2_CLK
SYS_CLK1
Func
FUNC_32K_CLK
OSC0
RTC Oscillator
OSC1
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_PER
TPCC
TPTC1
TPTC2
UART1
TPCC_GCLK
TPTC0_GCLK
TPTC1_GCLK
UART1_FCLK
UART1_ICLK
UART2_FCLK
UART2_ICLK
UART3_FCLK
UART3_ICLK
UART4_FCLK
UART4_ICLK
UART5_FCLK
UART5_ICLK
UART6_FCLK
UART6_ICLK
UART7_FCLK
UART7_ICLK
UART8_FCLK
UART8_ICLK
Int
Int
266
266
266
48
L3MAIN1_L3_GICLK
L3MAIN1_L3_GICLK
L3MAIN1_L3_GICLK
UART1_GFCLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
Int
Func
Int
266
48
L4PER_L3_GICLK
UART2_GFCLK
DPLL_CORE
DPLL_PER
UART2
UART3
UART4
UART5
UART6
UART7
UART8
Func
Int
266
48
L4PER_L3_GICLK
UART3_GFCLK
DPLL_CORE
DPLL_PER
Func
Int
266
48
L4PER_L3_GICLK
UART4_GFCLK
DPLL_CORE
DPLL_PER
Func
Int
266
48
L4PER_L3_GICLK
UART5_GFCLK
DPLL_CORE
DPLL_PER
Func
Int
266
48
L4PER_L3_GICLK
UART6_GFCLK
DPLL_CORE
DPLL_PER
Func
Int
266
48
IPU_L3_GICLK
DPLL_CORE
DPLL_PER
Func
Int
UART7_GFCLK
266
48
L4PER2_L3_GICLK
UART8_GFCLK
DPLL_CORE
DPLL_PER
Func
Int
266
L4PER2_L3_GICLK
DPLL_CORE
146
Specifications
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
PLL / OSC /
Source Clock
Name
Clock
Type
Max. Clock
Allowed (MHz)
PLL / OSC /
Source Name
Instance Name
Input Clock Name
PRCM Clock Name
UART9
UART9_FCLK
UART9_ICLK
UART10_FCLK
UART10_ICLK
Func
Int
48
266
48
UART9_GFCLK
L4PER2_L3_GICLK
UART10_GFCLK
WKUPAON_GICLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
SYS_CLK1
DPLL_PER
DPLL_CORE
DPLL_PER
OSC0
UART10
USB1
Func
Int
38.4
DPLL_ABE_X2_CL
K
DPLL_ABE
USB1_MICLK
Int
266
L3INIT_L3_GICLK
CORE_X2_CLK
DPLL_CORE
DPLL_CORE
USB3PHY_REF_C
LK
Func
34.3
USB_LFPS_TX_GFCL CORE_USB_OTG_
K
SS_LFPS_TX_CLK
USB2PHY1_TREF
_CLK
Func
Func
38.4
960
USB_OTG_SS_REF_C
LK
SYS_CLK1
OSC0
USB2PHY1_REF_
CLK
L3INIT_960M_GFCLK L3INIT_960_GFCL
K
DPLL_USB
USB2
USB3
USB2_MICLK
Int
266
L3INIT_L3_GICLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
USB2PHY2_TREF
_CLK
Func
38.4
USB_OTG_SS_REF_C
LK
USB2PHY2_REF_
CLK
Func
960
L3INIT_960M_GFCLK L3INIT_960_GFCL
K
DPLL_USB
USB3_MICLK
Int
266
L3INIT_L3_GICLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
USB3PHY_PWRS_
CLK
Func
38.4
USB_OTG_SS_REF_C
LK
USB_PHY1_CORE USB2PHY1_WKUP
_CLK
Func
Func
Func
0.032
0.032
0.032
COREAON_32K_GFCL
K
SYS_CLK1/610
SYS_CLK1/610
SYS_CLK1/610
OSC0
OSC0
OSC0
USB_PHY2_CORE USB2PHY2_WKUP
_CLK
COREAON_32K_GFCL
K
USB_PHY3_CORE USB3PHY_WKUP_
CLK
COREAON_32K_GFCL
K
VCP1
VCP2
VIP1
VCP1_CLK
VCP2_CLK
Int
Int
266
266
266
L3MAIN1_L3_GICLK
L3MAIN1_L3_GICLK
VIP1_GCLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
L3_CLK_PROC_CL
K
Int &
Func
CORE_ISS_MAIN_
CLK
VPE
L3_CLK_PROC_CL
K
Int &
Func
300
VPE_GCLK
CORE_ISS_MAIN_
CLK
DPLL_CORE
VIDEO1_CLKOUT4
SYS_CLK1
DPLL_VIDEO1
OSC0
WD_TIMER1
PIOCPCLK
Int
38.4
WKUPAON_GICLK
DPLL_ABE_X2_CL
K
DPLL_ABE
PITIMERCLK
Func
Int
0.032
38.4
OSC_32K_CLK
RC_CLK
RC oscillator
OSC0
WD_TIMER2
WD_TIMER2_ICLK
WKUPAON_GICLK
SYS_CLK1
DPLL_ABE_X2_CL
K
DPLL_ABE
WD_TIMER2_FCL
K
Func
0.032
WKUPAON_SYS_GFC WKUPAON_32K_G
LK FCLK
RTC Oscillator
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Specifications
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5.6 Power Consumption Summary
注
Maximum power consumption for this SoC depends on the specific use conditions for the
end system. Contact your TI representative for assistance in estimating maximum power
consumption for the end system use case.
5.7 Electrical Characteristics
注
The data specified in 节 5.7.1 through 节 5.7.12 are subject to change.
注
The interfaces or signals described in 节 5.7.1 through 节 5.7.12 correspond to the interfaces
or signals available in multiplexing mode 0 (Function 1).
All interfaces or signals multiplexed on the balls described in these tables have the same DC
electrical characteristics, unless multiplexing involves a PHY/GPIO combination in which
case different DC electrical characteristics are specified for the different multiplexing modes
(Functions).
5.7.1 LVCMOS DDR DC Electrical Characteristics
表 5-10 summarizes the DC electrical characteristics for LVCMOS DDR Buffers.
注
For more information on the I/O cell configurations (i[2:0], sr[1:0]), see the Chapter Control
Module of the Device TRM.
表 5-10. LVCMOS DDR DC Electrical Characteristics
PARAMETER
MIN
NOM
MAX
UNIT
Signal Names in MUXMODE 0 (Single-Ended Signals): ddr1_d[31:0], ddr1_a[15:0], ddr1_dqm[3:0], ddr1_ba[2:0], ddr1_csn[1:0],
ddr1_cke, ddr1_odt[1:0], ddr1_casn, ddr1_rasn, ddr1_wen, ddr1_rst, ddr1_ecc_d[7:0], ddr1_dqm_ecc;
Balls: AH23 / AB16 / AG22 / AE20 / AC17 / AC18 / AF20 /AH21 / AG21 / AF17 / AE18 / AB18 / AD20 / AC19 / AC20 / AB19 / AF21 / AH22
/ AG23 / AE21 / AF22 / AE22 / AD21 / AD22 / AC21 / AF18 / AE17 / AD18 / AF25 / AF26 / AG26 / AH26 / AF24 / AE24 / AF23 / AE23 /
AC23 / AF27 / AG27 / AF28 / AE26 / AC25 / AC24 / AD25 / V20 / W20 / AB28 / AC28 / AC27 / Y19 / AB27 / Y20 / AA23 / Y22 / Y23 / AA24
/ Y24 / AA26 / AA25 / AA28 / W22 / V23 / W19 / W23 / Y25 / V24 / V25 / Y26 / AD23 / AB23 / AC26 / AA27 / V26;
Driver Mode
VOH
VOL
CPAD
ZO
High-level output threshold (IOH = 0.1 mA)
Low-level output threshold (IOL = 0.1 mA)
Pad capacitance (including package capacitance)
0.9*VDDS
V
V
0.1*VDDS
3
pF
Output impedance (drive
strength)
l[2:0] = 000
(Imp80)
80
60
48
40
34
l[2:0] = 001
(Imp60)
l[2:0] = 010
(Imp48)
Ω
l[2:0] = 011
(Imp40)
l[2:0] = 100
(Imp34)
Single-Ended Receiver Mode
148
Specifications
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
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ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 5-10. LVCMOS DDR DC Electrical Characteristics (continued)
PARAMETER
High-level input threshold
Low-level input threshold
Input common-mode voltage
MIN
VREF+0.1
-0.2
NOM
MAX
VDDS+0.2
VREF-0.1
UNIT
V
VIH
VIL
DDR3/DDR3L
DDR3/DDR3L
V
VCM
VREF
-10%vdds
VREF+
10%vdds
V
CPAD
Pad capacitance (including package capacitance)
3
pF
Signal Names in MUXMODE 0 (Differential Signals): ddr1_dqs[3:0], ddr1_dqsn[3:0], ddr1_ck, ddr1_nck, ddr1_dqs_ecc, ddr1_dqsn_ecc
Bottom Balls: AH25 / AG25 / AE27 / AE28 / AD27 / AD28 / Y28 / Y27 / V27 / V28 / AG24 / AH24
Driver Mode
VOH
VOL
CPAD
ZO
High-level output threshold (IOH = 0.1 mA)
Low-level output threshold (IOL = 0.1 mA)
Pad capacitance (including package capacitance)
0.9*VDDS
V
V
0.1*VDDS
3
pF
Output impedance (drive
strength)
l[2:0] = 000
(Imp80)
80
60
48
40
34
l[2:0] = 001
(Imp60)
l[2:0] = 010
(Imp48)
Ω
l[2:0] = 011
(Imp40)
l[2:0] = 100
(Imp34)
Single-Ended Receiver Mode
VIH
VIL
High-level input threshold
DDR3/DDR3L
DDR3/DDR3L
VREF+0.1
-0.2
VDDS+0.2
VREF-0.1
V
V
Low-level input threshold
VCM
Input common-mode voltage
VREF
-10%vdds
VREF+
10%vdds
V
CPAD
Pad capacitance (including package capacitance)
3
pF
Differential Receiver Mode
VSWING Input voltage swing
VCM Input common-mode voltage
DDR3/DDR3L
0.2
vdds+0.4
V
V
VREF
-10%vdds
VREF+
10%vdds
CPAD
Pad capacitance (including package capacitance)
3
pF
(1) VDDS in this table stands for corresponding power supply (i.e. vdds_ddr1). For more information on the power supply name and the
corresponding ball, see 表 4-2, POWER [10] column.
(2) VREF in this table stands for corresponding Reference Power Supply (i.e. ddr1_vref0). For more information on the power supply name
and the corresponding ball, see 表 4-2, POWER [10] column.
5.7.2 HDMIPHY DC Electrical Characteristics
The HDMIPHY DC Electrical Characteristics are compliant with the HDMI 1.4a specification and are not
reproduced here.
5.7.3 Dual Voltage LVCMOS I2C DC Electrical Characteristics
表 5-11 summarizes the DC electrical characteristics for Dual Voltage LVCMOS I2C Buffers.
注
For more information on the I/O cell configurations, see the Control Module section of the
Device TRM.
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Specifications
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表 5-11. Dual Voltage LVCMOS I2C DC Electrical Characteristics
PARAMETER
Signal Names in MUXMODE 0: i2c2_scl; i2c1_scl; i2c1_sda; i2c2_sda;
Balls: F17 / C20 / C21 / C25
MIN
NOM
MAX
UNIT
I2C Standard Mode – 1.8 V
VIH
VIL
Input high-level threshold
Input low-level threshold
Hysteresis
0.7*VDDS
0.1*VDDS
V
V
V
0.3*VDDS
12
Vhys
IIN
Input current at each I/O pin with an input voltage
between 0.1*VDDS to 0.9*VDDS
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
12
µA
PAD is swept from 0 to VDDS and the Max(I(PAD)
)
is measured and is reported as IOZ
CIN
Input capacitance
10
pF
V
VOL3
Output low-level threshold open-drain at 3-mA
sink current
0.2*VDDS
IOLmin
tOF
Low-level output current @VOL=0.2*VDDS
3
mA
ns
Output fall time from VIHmin to VILmax with a bus
capacitance CB from 5 pF to 400 pF
250
I2C Fast Mode – 1.8 V
VIH
VIL
Input high-level threshold
0.7*VDDS
0.1*VDDS
V
V
V
Input low-level threshold
Hysteresis
0.3*VDDS
12
Vhys
IIN
Input current at each I/O pin with an input voltage
between 0.1*VDDS to 0.9*VDDS
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
12
µA
PAD is swept from 0 to VDDS and the Max(I(PAD)
)
is measured and is reported as IOZ
CIN
Input capacitance
10
pF
V
VOL3
Output low-level threshold open-drain at 3-mA
sink current
0.2*VDDS
IOLmin
tOF
Low-level output current @VOL=0.2*VDDS
3
mA
ns
Output fall time from VIHmin to VILmax with a bus
capacitance CB from 10 pF to 400 pF
20+0.1*Cb
250
I2C Standard Mode – 3.3 V
VIH
VIL
Input high-level threshold
0.7*VDDS
V
V
V
Input low-level threshold
Hysteresis
0.3*VDDS
80
Vhys
IIN
0.05*VDDS
31
Input current at each I/O pin with an input voltage
between 0.1*VDDS to 0.9*VDDS
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
31
80
µA
PAD is swept from 0 to VDDS and the Max(I(PAD)
)
is measured and is reported as IOZ
CIN
Input capacitance
10
pF
V
VOL3
Output low-level threshold open-drain at 3-mA
sink current
0.4
IOLmin
IOLmin
Low-level output current @VOL=0.4V
3
6
mA
mA
Low-level output current @VOL=0.6V for full drive
load (400pF/400KHz)
150
Specifications
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
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ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 5-11. Dual Voltage LVCMOS I2C DC Electrical Characteristics (continued)
PARAMETER
MIN
NOM
MAX
UNIT
tOF
Output fall time from VIHmin to VILmax with a bus
capacitance CB from 5 pF to 400 pF
250
ns
I2C Fast Mode – 3.3 V
VIH
VIL
Input high-level threshold
0.7*VDDS
V
V
V
Input low-level threshold
Hysteresis
0.3*VDDS
80
Vhys
IIN
0.05*VDDS
31
Input current at each I/O pin with an input voltage
between 0.1*VDDS to 0.9*VDDSS
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
31
80
µA
PAD is swept from 0 to VDDS and the Max(I(PAD)
)
is measured and is reported as IOZ
CIN
Input capacitance
10
pF
V
VOL3
Output low-level threshold open-drain at 3-mA
sink current
0.4
IOLmin
IOLmin
Low-level output current @VOL=0.4V
3
6
mA
mA
Low-level output current @VOL=0.6V for full drive
load (400pF/400KHz)
tOF
Output fall time from VIHmin to VILmax with a bus
capacitance CB from 10 pF to 200 pF (Proper
External Resistor Value should be used as per
I2C spec)
20+0.1*Cb
40
250
290
ns
Output fall time from VIHmin to VILmax with a bus
capacitance CB from 300 pF to 400 pF (Proper
External Resistor Value should be used as per
I2C spec)
(1) VDDS in this table stands for corresponding power supply (i.e. vddshv3). For more information on the power supply name and the
corresponding ball, see 表 4-2, POWER [10] column.
5.7.4 IQ1833 Buffers DC Electrical Characteristics
表 5-12 summarizes the DC electrical characteristics for IQ1833 Buffers.
表 5-12. IQ1833 Buffers DC Electrical Characteristics
PARAMETER
MIN
NOM
MAX
UNIT
Signal Names in MUXMODE 0: tclk;
Balls: E20;
1.8-V Mode
VIH
Input high-level threshold (Does not meet JEDEC VIH
)
0.75 *
VDDS
V
V
VIL
Input low-level threshold (Does not meet JEDEC VIL)
0.25 *
VDDS
VHYS
IIN
Input hysteresis voltage
100
2
mV
µA
pF
Input current at each I/O pin
11
1
CPAD
3.3-V Mode
VIH
Pad capacitance (including package capacitance)
Input high-level threshold (Does not meet JEDEC VIH
Input low-level threshold (Does not meet JEDEC VIL)
Input hysteresis voltage
)
2.0
V
V
VIL
0.6
VHYS
IIN
400
5
mV
µA
pF
Input current at each I/O pin
11
1
CPAD
Pad capacitance (including package capacitance)
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(1) VDDS in this table stands for corresponding power supply (i.e. vddshv3). For more information on the power supply name and the
corresponding ball, see 表 4-2, POWER [10] column.
5.7.5 IHHV1833 Buffers DC Electrical Characteristics
表 5-13 summarizes the DC electrical characteristics for IHHV1833 Buffers.
表 5-13. IHHV1833 Buffers DC Electrical Characteristics
PARAMETER
Signal Names in MUXMODE 0: porz / rtc_porz / wakeup3 / wakeup0;
Balls: F22 / AB17 / AD17 / AC16;
MIN
NOM
MAX
UNIT
1.8-V Mode
VIH
Input high-level threshold
1.2
V
V
VIL
Input low-level threshold
0.4
VHYS
IIN
Input hysteresis voltage
40
mV
µA
pF
Input current at each I/O pin
Pad capacitance (including package capacitance)
0.02
1
1
CPAD
3.3-V Mode
VIH
Input high-level threshold
1.2
V
V
VIL
Input low-level threshold
0.4
VHYS
IIN
Input hysteresis voltage
40
5
mV
µA
pF
Input current at each I/O pin
Pad capacitance (including package capacitance)
8
1
CPAD
5.7.6 LVCMOS CSI2 DC Electrical Characteristics
表 5-14 summarizes the DC electrical characteristics for LVCMOS CSI2 Buffers.
表 5-14. LVCMOS CSI2 DC Electrical Characteristics
PARAMETER
MIN
NOM
MAX
UNIT
Signals MUXMODE0 : csi2_0_dx[4:0]; csi2_0_dy[4:0]; csi2_1_dx[2:0]; csi2_1_dy[2:0];
Bottom Balls: AE1 / AD2 / AF1 / AE2 / AF2 / AF3 / AH4 / AG4 / AH3 / AG3 / AG5 / AH5 / AG6 / AH6 / AH7 / AG7
MIPI D-PHY Mode Low-Power Receiver (LP-RX)
VIH
VIL
Input high-level voltage
Input low-level voltage
Input high-level threshold
880
1350
550
mV
mV
mV
mV
mV
(1)
(2)
VITH
VITL
VHYS
880
Input low-level threshold
Input hysteresis (3)
550
25
MIPI D-PHY Mode Ultralow Power Receiver (ULP-RX)
VIL
VITL
VHYS
Input low-level voltage
Input low-level threshold
Input hysteresis (3)
300
mV
mV
mV
(4)
300
25
MIPI D-PHY Mode High-Speed Receiver (HS-RX)
VIDTH
VIDTL
Differential input high-level threshold
Differential input low-level threshold
Maximum differential input voltage (7)
Single-ended input high voltage (5)
Single-ended input low voltage (5)
70
mV
mV
mV
mV
mV
mV
–70
270
460
VIDMAX
VIHHS
VILHS
–40
70
VCMRXDC
Differential input common-mode voltage (5) (6)
330
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表 5-14. LVCMOS CSI2 DC Electrical Characteristics (continued)
PARAMETER
MIN
NOM
MAX
UNIT
ZID
Differential input impedance
80
100
125
Ω
(1) VITH is the voltage at which the receiver is required to detect a high state in the input signal.
(2) VITL is the voltage at which the receiver is required to detect a low state in the input signal. VITL is larger than the maximum single-ended
line high voltage during HS transmission. Therefore, both low-power (LP) receivers will detect low during HS signaling.
(3) To reduce noise sensitivity on the received signal, the LP receiver is required to incorporate a hysteresis, VHYST. VHYST is the difference
between the VITH threshold and the VITL threshold.
(4) VITL is the voltage at which the receiver is required to detect a low state in the input signal. Specification is relaxed for detecting 0 during
ultralow power (ULP) state. The LP receiver is not required to detect HS single-ended voltage as 0 in this state.
(5) Excluding possible additional RF interference of 200 mVPP beyond 450 MHz.
(6) This value includes a ground difference of 50 mV between the transmitter and the receiver, the static common-mode level tolerance and
variations below 450 MHz.
(7) This number corresponds to the VODMAX transmitter.
(8) Common mode is defined as the average voltage level of X and Y: VCMRX = (VX + VY) / 2.
(9) Common mode ripple may be due to tR or tF and transmission line impairments in the PCB.
(10) For more information regarding the pin name (or ball name) and corresponding signal name, see 表 4-7 ,CSI 2 Signal Descriptions.
5.7.7 BC1833IHHV Buffers DC Electrical Characteristics
表 5-15 summarizes the DC electrical characteristics for BC1833IHHV Buffers.
表 5-15. BC1833IHHV Buffers DC Electrical Characteristics
PARAMETER
Signal Names in MUXMODE 0: on_off;
MIN
NOM
MAX
UNIT
Balls: Y11;
1.8-V Mode
VOH
Output high-level threshold (IOH = 2 mA)
VDDS-
0.45
V
VOL
IDRIVE
IIN
Output low-level threshold (IOL = 2 mA)
Pin Drive strength at PAD Voltage = 0.45V or VDDS-0.45V
Input current at each I/O pin
0.45
12
6
V
6
6
mA
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is contributed by
the tristated driver leakage + input current of the Rx + weak
pullup/pulldown leakage. PAD is swept from 0 to VDDS and
the Max(I(PAD)) is measured and is reported as IOZ
µA
pF
CPAD
3.3-V Mode
VOH
Pad capacitance (including package capacitance)
4
Output high-level threshold (IOH = 100 µA)
Output low-level threshold (IOL = 100 µA)
Pin Drive strength at PAD Voltage = 0.45V or VDDS-0.45V
Input current at each I/O pin
VDDS-0.2
6
V
V
VOL
0.2
60
60
4
IDRIVE
IIN
mA
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is contributed by
the tristated driver leakage + input current of the Rx + weak
pullup/pulldown leakage. PAD is swept from 0 to VDDS and
the Max(I(PAD)) is measured and is reported as IOZ
µA
pF
CPAD
Pad capacitance (including package capacitance)
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(1) VDDS in this table stands for corresponding power supply (i.e. vddshv5). For more information on the power supply name and the
corresponding ball, see 表 4-2, POWER [10] column.
5.7.8 USBPHY DC Electrical Characteristics
注
USB1 instance is compliant with the USB3.0 SuperSpeed Transmitter and Receiver
Normative Electrical Parameters as defined in the USB3.0 Specification Rev 1.0 dated Jun 6,
2011.
注
USB1 and USB2 Electrical Characteristics are compliant with USB2.0 Specification Rev 2.0
dated April 27, 2000 including ECNs and Errata as applicable.
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5.7.9 Dual Voltage SDIO1833 DC Electrical Characteristics
表 5-16 summarizes the DC electrical characteristics for Dual Voltage SDIO1833 Buffers.
表 5-16. Dual Voltage SDIO1833 DC Electrical Characteristics
PARAMETER
Signal Names in Mode 0: mmc1_clk, mmc1_cmd, mmc1_data[3:0]
Bottom Balls: W6 / Y6 / AA6 / Y4 / AA5 / Y3
1.8-V Mode
MIN
NOM
MAX
UNIT
VIH
VIL
Input high-level threshold
Input low-level threshold
Input hysteresis voltage
Input current at each I/O pin
1.27
V
V
0.58
30
(2)
VHYS
IIN
50
mV
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is contributed by the
tristated driver leakage + input current of the Rx + weak
pullup/pulldown leakage. PAD is swept from 0 to VDDS and the
Max(I(PAD)) is measured and is reported as IOZ
30
µA
IIN with
pulldown
enabled
Input current at each I/O pin with weak pulldown enabled
measured when PAD = VDDS
50
60
120
120
210
µA
µA
IIN with
pullup
Input current at each I/O pin with weak pullup enabled measured
when PAD = 0
200
5
enabled
CPAD
VOH
VOL
Pad capacitance (including package capacitance)
Output high-level threshold (IOH = 2 mA)
Output low-level threshold (IOL = 2 mA)
pF
V
1.4
0.45
V
3.3-V Mode
VIH
Input high-level threshold
0.625 ×
VDDS
V
VIL
Input low-level threshold
Input hysteresis voltage
Input current at each I/O pin
0.25 × VDDS
110
V
(2)
VHYS
IIN
40
mV
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is contributed by the
tristated driver leakage + input current of the Rx + weak
pullup/pulldown leakage. PAD is swept from 0 to VDDS and the
Max(I(PAD)) is measured and is reported as IOZ
110
µA
IIN with
pulldown
enabled
Input current at each I/O pin with weak pulldown enabled
measured when PAD = VDDS
40
10
100
100
290
µA
µA
IIN with
pullup
Input current at each I/O pin with weak pullup enabled measured
when PAD = 0
290
5
enabled
CPAD
VOH
VOL
Pad capacitance (including package capacitance)
Output high-level threshold (IOH = 2 mA)
Output low-level threshold (IOL = 2 mA)
pF
V
0.75 × VDDS
0.125 ×
VDDS
V
(1) VDDS in this table stands for corresponding power supply (i.e. vddshv8). For more information on the power supply name and the
corresponding ball, see 表 4-2, POWER [10] column.
(2) Hysteresis is enabled/disabled with CTRL_CORE_CONTROL_HYST_1.SDCARD_HYST register.
5.7.10 Dual Voltage LVCMOS DC Electrical Characteristics
表 5-17 summarizes the DC electrical characteristics for Dual Voltage LVCMOS Buffers.
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表 5-17. Dual Voltage LVCMOS DC Electrical Characteristics
PARAMETER
1.8-V Mode
VIH
MIN
NOM
MAX
0.35*VDDS
0.45
UNIT
Input high-level threshold
0.65*VDDS
V
V
VIL
Input low-level threshold
VHYS
Input hysteresis voltage
100
mV
V
VOH
Output high-level threshold (IOH = 2 mA)
Output low-level threshold (IOL = 2 mA)
VDDS-0.45
VOL
V
IDRIVE
Pin Drive strength at PAD Voltage = 0.45V or
VDDS-0.45V
6
mA
µA
IIN
Input current at each I/O pin
16
16
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
µA
PAD is swept from 0 to VDDS and the Max(I(PAD)
)
is measured and is reported as IOZ
IIN with pulldown
enabled
Input current at each I/O pin with weak pulldown
enabled measured when PAD = VDDS
50
60
120
120
210
µA
µA
IIN with pullup
enabled
Input current at each I/O pin with weak pullup
enabled measured when PAD = 0
200
4
CPAD
Pad capacitance (including package capacitance)
Output impedance (drive strength)
pF
ZO
40
Ω
3.3-V Mode
VIH
Input high-level threshold
2
V
V
VIL
Input low-level threshold
0.8
0.2
VHYS
VOH
Input hysteresis voltage
200
mV
V
Output high-level threshold (IOH = 100 µA)
Output low-level threshold (IOL = 100 µA)
VDDS-0.2
VOL
V
IDRIVE
Pin Drive strength at PAD Voltage = 0.45V or
VDDS-0.45V
6
mA
µA
IIN
Input current at each I/O pin
65
65
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
µA
PAD is swept from 0 to VDDS and the Max(I(PAD)
)
is measured and is reported as IOZ
IIN with pulldown
enabled
Input current at each I/O pin with weak pulldown
enabled measured when PAD = VDDS
40
10
100
100
200
290
4
µA
µA
IIN with pullup
enabled
Input current at each I/O pin with weak pullup
enabled measured when PAD = 0
CPAD
Pad capacitance (including package capacitance)
Output impedance (drive strength)
pF
ZO
40
Ω
(1) VDDS in this table stands for corresponding power supply. For more information on the power supply name and the corresponding ball,
see 表 4-2, POWER [10] column.
5.7.11 SATAPHY DC Electrical Characteristics
注
The SATA module is compliant with the electrical parameters specified in the SATA-IO SATA
Specification, Revision 3.2, August 7, 2013.
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5.7.12 PCIEPHY DC Electrical Characteristics
注
The PCIe interfaces are compliant with the electrical parameters specified in PCI Express®
Base Specification Revision 3.0.
5.8 Thermal Characteristics
For reliability and operability concerns, the maximum junction temperature of the Device has to be at or
below the TJ value identified in 表 5-4, Recommended Operating Conditions.
A BCI compact thermal model for this Device is available and recommended for use when modeling
thermal performance in a system.
Therefore, it is recommended to perform thermal simulations at the system level with the worst case
device power consumption.
5.8.1 Package Thermal Characteristics
表 5-18 provides the thermal resistance characteristics for the package used on this device.
注
Power dissipation of 1.9 W and an ambient temperature of 85ºC is assumed for ABC
package.
表 5-18. Thermal Resistance Characteristics
NO.
T1
PARAMETER
RΘJC
DESCRIPTION
°C/W(1)
0.41
4.74
11.9
8.9
AIR FLOW (m/s)(2)
Junction-to-case
Junction-to-board
Junction-to-free air
N/A
N/A
0
T2
RΘJB
T3
T4
1
RΘJA
T5
Junction-to-moving air
8.0
2
T6
7.4
3
T7
0.22
0.22
0.22
0.23
4.12
3.73
3.59
3.48
0
T8
1
ΨJT
Junction-to-package top
T9
2
T10
T11
T12
T13
T14
3
0
1
ΨJB
Junction-to-board
2
3
(1) These measurements were conducted in a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] measurement,
which was conducted in a JEDEC defined 1S0P system) and will change based on environment as well as application. For more
information, see these EIA/JEDEC standards:
–
–
–
–
JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Packages
(2) m/s = meters per second
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5.9 Power Supply Sequences
This section describes the power-up and power-down sequence required to ensure proper device
operation. The power supply names described in this section comprise a superset of a family of
compatible devices. Some members of this family will not include a subset of these power supplies and
their associated device modules. Refer to the 节 4.2, Ball Characteristics of the 节 4, Terminal
Configuration and Functions to determine which power supplies are applicable.
图 5-2 and 图 5-3 describe the device Power Sequencing when RTC-mode is used.
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Note 4 Note 5
vdda_rtc(3)
vdds18v, vdds_mlbp, vdds18v_ddr1
vdda_per, vdda_ddr, vdda_debug,
vdda_core_gmac, vdda_gpu,
vdda_dsp_iva, vdda_video,
vdda_mpu_abe, vdda_osc
vdd_rtc(3)
vdds_ddr1, ddr1_vref0
VD_CORE BOOT voltage
vdd
vdd_mpu
vdd_iva
VD_MPU BOOT voltage
VD_IVA BOOT voltage
VD_GPU BOOT voltage
VD_DSPEVE BOOT voltage
vdd_gpu
vdd_dsp
vdda_usb1, vdda_usb2, vdda_hdmi,
vdda_pcie, vdda_pcie1, vdda_sata,
vdda_usb3, vdda_csi
vddshv5(3)
Note 6
vddshv1, vddshv2, vddshv3, vddshv4,
vddshv6, vddshv7, vddshv9,
vddshv10, vddshv11
vdda33v_usb1, vdda33v_usb2
Note 7
vddshv8
xi_osc0
rtc_porz
Note 9
Note 11
porz
Note 12
Note 13
sysboot[15:0]
Valid Config
Note 14
rstoutn
SPRS906_ELCH_01
图 5-2. Power-Up Sequencing
(1) Grey shaded areas are windows where it is valid to ramp the voltage rail.
(2) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
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(3) If RTC-mode is used then vdda_rtc, vdd_rtc and vddshv5 must be individually powered with separate power supplies and cannot be
combined with other rails.
(4) vdd must ramp before or at the same time as vdd_mpu, vdd_gpu, vdd_dsp and vdd_iva.
(5) vdd_mpu, vdd_gpu, vdd_dsp, vdd_iva can be ramped at the same time or can be staggered.
(6) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
(7) vddshv8 is separated out to show support for dual voltage. If single voltage is used then vddshv8 can be combined with other vddshvn
rails but vddshv8 must ramp after vdd.
(8) vdds and vdda rails must not be combined together.
(9) Pulse duration: rtc_porz must remain low 1ms after vdda_rtc, vddshv5, and vdd_rtc are ramped and stable.
(10) The SYS_32K source must be stable and at a valid frequency 1ms prior to de-asserting rtc_porz high.
(11) Pulse duration: porz must remain low a minimum of 12P(15) after xi_osc0 is stable and at a valid frequency. porz must also remain low
until all supply rails are valid and stable. resetn must be high prior to, or simultaneous with, porz rising. During initial power-up, resetn
can rise any time after, or concurrently with, its supply voltage, vddshv3 rising.
(12) Setup time: sysboot[15:0] pins must be valid 2P(15) before porz is de-asserted high.
(13) Hold time: sysboot[15:0] pins must be valid 15P(15) after porz is de-asserted high.
(14) porz to rstoutn delay is 2ms.
(15) P = 1/(SYS_CLK1/610) frequency in ns.
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Note 5 Note 6
porz
Note 8
vddshv8
vdda33v_usb1, vdda33v_usb2
Note 7
vddshv1, vddshv2, vddshv3, vddshv4,
vddshv6, vddshv7, vddshv9, vddshv10,
vddshv11
vdda_usb1, vdda_usb2, vdda_hdmi,
vdda_pcie, vdda_pcie0, vdda_sata,
vdda_usb3, vdda_csi
vddshv5(4)
vdd_dsp
vdd_gpu
vdd_iva
vdd_mpu
vdd
vdds_ddr1, ddr1_vref0
vdda_per, vdda_ddr, vdda_debug, vdda_dsp_iva,
vdda_core_gmac, vdda_gpu, vdda_video,
vdda_mpu_abe, vdda_osc
vdd_rtc(4)
vdds18v, vdds_mlbp, vdds18v_ddr1
vdda_rtc(4)
xi_osc0
SPRS906_ELCH_02
图 5-3. Power-Down Sequencing
(1) xi_osc0 can be turned off anytime after porz assertion and must be turned off before vdda_osc voltage rail is shutdown.
(2) Grey shaded areas are windows where it is valid to ramp the voltage rail.
(3) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
(4) If RTC-mode is supported then vdda_rtc, vdd_rtc and vddshv5 must be individually powered with separate power supplies and cannot
be combined with other rails.
(5) vdd_mpu, vdd_gpu, vdd_dsp, vdd_iva can be ramped at the same time or can be staggered.
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(6) vdd must ramp after or at the same time as vdd_mpu, vdd_gpu, vdd_dsp and vdd_iva.
(7) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
vddshv[1-7,9-11] is allowed to ramp down at either of the two points shown in the timing diagram in either 1.8V mode or in 3.3V mode. If
vddshv[1-7,9-11] ramps down at the later time in the diagram then the board design must guarantee that the vddshv[1-7,9-11] rail is
never higher than 2.0 V above the vdds18v rail.
(8) vddshv8 is separated out to show support for dual voltage. If a dedicated LDO/supply source is used for vddshv8, then vddshv8 ramp
down should occur at one of the two earliest points in the timing diagram. If vddshv8 is powered by the same supply source as the other
vddshvn rails, then it is allowed to ramp down at either of the last two points in the timing diagram.
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图 5-4 describes the RTC-mode Power Sequencing.
Note 4 Note 3
Note 5 Note 4
vdds18v, vdds_mlbp, vdds18v_ddr1
vdda_rtc
vdda_per, vdda_ddr, vdda_debug,
vdda_dsp_iva, vdda_core_gmac,
vdda_gpu, vdda_video, vdda_mpu,
vdda_osc
vdd_rtc
vdds_ddr1, ddr1_vref0
vdd
R
T
C
vdd_mpu
vdd_iva
M
O
D
E
vdd_gpu
vdd_dsp
vdda_usb1, vdda_usb2, vdda_hdmi,
vdda_pcie, vdda_pcie0, vdda_sata,
vdda_usb3, vdda_csi
vddshv5
Note 6
Note 8
vddshv1, vddshv2, vddshv3, vddshv4,
vddshv6, vddshv7, vddshv9, vddshv10,
vddshv11
vdda33v_usb1, vdda33v_usb2
Note 9
Note 7
vddshv8
rtc_porz
resetn/porz
SPRS906_ELCH_03
图 5-4. RTC Mode Sequencing
(1) Grey shaded areas are windows where it is valid to ramp the voltage rail.
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(2) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
(3) vdd must ramp down after or at the same time as vdd_mpu, vdd_gpu, vdd_dsp and vdd_iva.
(4) vdd_mpu, vdd_gpu, vdd_dsp, vdd_iva can be ramped at the same time or can be staggered.
(5) vdd must ramp up before or at the same time as vdd_mpu, vdd_gpu, vdd_dsp and vdd_iva.
(6) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
(7) vddshv8 is separated out to show support for dual voltage. If single voltage is used then vddshv8 can be combined with other vddshvn
rails but vddshv8 must ramp down before vdd and must ramp up after vdd.
(8) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
vddshv[1-7,9-11] is allowed to ramp down at either of the two points shown in the timing diagram in either 1.8V mode or in 3.3V mode. If
vddshv[1-7,9-11] ramps down at the later time in the diagram then the board design must guarantee that the vddshvn rail is never higher
than 2.0 V above the vdds18v rail.
(9) vddshv8 is separated out to show support for dual voltage. If a dedicated LDO/supply source is used for vddshv8, then vddshv8 ramp
down should occur at one of the two earliest points in the timing diagram. If vddshv8 is powered by the same supply source as the other
vddshvn rails, then it is allowed to ramp down at either of the last two points in the timing diagram.
图 5-5 and 图 5-6 describe the device Power Sequencing when RTC-mode is NOT used.
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Note 4
Note 5
vdds18v, vdds_mlbp, vdds18v_ddr1, vdda_rtc(3)
vdda_per, vdda_ddr, vdda_debug,
vdda_dsp_iva, vdda_core_gmac, vdda_gpu,
vdda_video, vdda_mpu, vdda_osc
vdds_ddr1, ddr1_vref0
VD_CORE BOOT voltage
vdd, vdd_rtc(3)
vdd_mpu
vdd_iva
VD_MPU BOOT voltage
VD_IVA BOOT voltage
VD_GPU BOOT voltage
VD_DSP BOOT voltage
vdd_gpu
vdd_dsp
vdda_usb1, vdda_usb2, vdda_hdmi,
vdda_pcie, vdda_pcie0, vdda_sata,
vdda_usb3, vdda_csi
vddshv1, vddshv2, vddshv3, vddshv4,
vddshv5(3), vddshv6, vddshv7, vddshv9,
vddshv10, vddshv11
Note 6
vdda33v_usb1, vdda33v_usb2
Note 7
vddshv8
xi_osc0
Note 9
rtc_porz
Note 11
porz
Note 12
Note 13
sysboot[15:0]
Valid Config
Note 14
rstoutn
SPRS906_ELCH_04
图 5-5. Power-Up Sequencing
(1) Grey shaded areas are windows where it is valid to ramp the voltage rail.
(2) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
(3) If RTC-mode is not supported then the following combinations are approved:
- vdda_rtc can be combined with vdds18v
- vdd_rtc can be combined with vdd
- vddshv5 can be combined with other 1.8V or 3.3V vddshvn rails.
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If combinations listed above are not followed then sequencing for these 3 voltage rails should follow the RTC mode timing requirements.
(4) vdd must ramp before or at the same time as vdd_mpu, vdd_gpu, vdd_dsp and vdd_iva.
(5) vdd_mpu, vdd_gpu, vdd_dsp, vdd_iva can be ramped at the same time or can be staggered.
(6) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
(7) vddshv8 is separated out to show support for dual voltage. If single voltage is used then vddshv8 can be combined with other vddshvn
rails but vddshv8 must ramp after vdd.
(8) vdds and vdda rails must not be combined together, with the one exception of vdda_rtc when RTC-mode is not supported.
(9) Pulse duration: rtc_porz must remain low 1ms after vdda_rtc, vddshv5, and vdd_rtc are ramped and stable.
(10) The SYS_32K source must be stable and at a valid frequency 1ms prior to de-asserting rtc_porz high.
(11) Pulse duration: porz must remain low a minimum of 12P(15) after xi_osc0 is stable and at a valid frequency. porz must also remain low
until all supply rails are valid and stable. resetn must be high prior to, or simultaneous with, porz rising. During initial power-up, resetn
can rise any time after, or concurrently with, its supply voltage, vddshv3 rising.
(12) Setup time: sysboot[15:0] pins must be valid 2P(15) before porz is de-asserted high.
(13) Hold time: sysboot[15:0] pins must be valid 15P(15) after porz is de-asserted high.
(14) porz to rstoutn delay is 2ms.
(15) P = 1/(SYS_CLK1/610) frequency in ns.
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Note 5 Note 6
porz
Note 8
vddshv8
vdda33v_usb1, vdda33v_usb2
Note 7
vdda_usb1, vdda_usb2, vdda_hdmi,
vdda_pcie, vdda_pcie0, vdda_sata,
vdda_usb3, vdda_csi
vdd_dsp
vdd_gpu
vdd_iva
vdd_mpu
vdd, vdd_rtc(4)
vdds_ddr1, ddr1_vref0
vdda_per, vdda_ddr, vdda_debug,
vdda_dsp_iva, vdda_core_gmac,
vdda_gpu, vdda_video, vdda_mpu,
vdda_osc
vdds18v, vdds_mlbp, vdds18v_ddr1,
vdda_rtc(4)
xi_osc0
SPRS906_ELCH_05
图 5-6. Power-Down Sequencing
(1) Grey shaded areas are windows where it is valid to ramp the voltage rail.
(2) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
(3) xi_osc0 can be turned off anytime after porz assertion and must be turned off before vdda_osc voltage rail is shutdown.
(4) If RTC-mode is not used then the following combinations are approved:
- vdda_rtc can be combined with vdds18v
- vdd_rtc can be combined with vdd
- vddshv5 can be combined with other 1.8V or 3.3V vddshvn rails
If combinations listed above are not followed then sequencing for these 3 voltage rails should follow the RTC mode timing requirements.
(5) vdd_mpu, vdd_gpu, vdd_dsp, vdd_iva can be ramped at the same time or can be staggered.
(6) vdd must ramp after or at the same time as vdd_mpu, vdd_gpu, vdd_dsp and vdd_iva.
(7) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
vddshv[1-7,9-11] is allowed to ramp down at either of the two points shown in the timing diagram in either 1.8V mode or in 3.3V mode. If
vddshv[1-7,9-11] ramps down at the later time in the diagram then the board design must guarantee that the vddshv[1-7,9-11] rail is
never higher than 2.0 V above the vdds18v rail.
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(8) vddshv8 is separated out to show support for dual voltage. If a dedicated LDO/supply source is used for vddshv8, then vddshv8 ramp
down should occur at one of the two earliest points in the timing diagram. If vddshv8 is powered by the same supply source as the other
vddshvn rails, then it is allowed to ramp down at either of the last two points in the timing diagram.
图 5-7 describes vddshv[1-7,9-11] Supplies Falling Before vdds18v Supplies Delta.
图 5-7. vddshv* Supplies Falling After vdds18v Supplies Delta
(1) Vdelta MAX = 2V
(2) If vddshv8 is powered by the same supply source as the other vddshv[1-7,9-11] rails.
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6 Clock Specifications
注
For more information, see Power Reset and Clock Management / PRCM Environment /
External Clock Signal and Power Reset / PRCM Functional Description / PRCM Clock
Manager Functional Description section of the Device TRM.
注
Audio Back End (ABE) module is not supported for this family of devices, but “ABE” name is
still present in some clock or DPLL names.
The device operation requires the following clocks:
•
The system clocks, SYS_CLKIN1(Mandatory) and SYS_CLKIN2(Optional) are the main clock sources
of the device. They supply the reference clock to the DPLLs as well as functional clock to several
modules.
图 6-1 shows the external input clock sources and the output clocks to peripherals.
DEVICE
rstoutn
Warm reset output.
Device reset input.
Power ON Reset.
resetn
porz
From quartz (19.2, 20 or 27 MHz)
or from CMOS square clock source (19.2, 20 or 27MHz).
xi_osc0
xo_osc0
To quartz (from oscillator output).
From quartz (range from 19.2 to 32 MHz)
or from CMOS square clock source(range from 12 to 38.4 MHz).
xi_osc1
xo_osc1
clkout1
clkout2
clkout3
To quartz (from oscillator output).
Output clkout[3:1] clocks come from:
• Either the input system clock and alternate clock (xi_osc0 or xi_osc1)
• Or a CORE clock (from CORE output)
• Or a 192-MHz clock (from PER DPLL output).
xref_clk0
xref_clk1
xref_clk2
External Reference Clock [3:0].
For Audio and other Peripherals
xref_clk3
Boot Mode Configuration
sysboot[15:0]
图 6-1. Clock Interface
6.1 Input Clock Specifications
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6.1.1 Input Clock Requirements
•
The source of the internal system clock (SYS_CLK1) could be either:
–
A CMOS clock that enters on the xi_osc0 ball (with xo_osc0 left unconnected on the CMOS clock
case).
–
A crystal oscillator clock managed by xi_osc0 and xo_osc0.
•
The source of the internal system clock (SYS_CLK2) could be either:
–
A CMOS clock that enters on the xi_osc1 ball (with xo_osc1 left unconnected on the CMOS clock
case).
–
A crystal oscillator clock managed by xi_osc1 and xo_osc1.
6.1.2 System Oscillator OSC0 Input Clock
SYS_CLKIN1 is received directly from oscillator OSC0. For more information about SYS_CLKIN1 see
Device TRM, Chapter: Power, Reset, and Clock Management.
6.1.2.1 OSC0 External Crystal
An external crystal is connected to the device pins. 图 6-2 describes the crystal implementation.
Device
xo_osc0
vssa_osc0
xi_osc0
Rd
(Optional)
Crystal
Cf2
Cf1
SPRS906_CLK_03
图 6-2. OSC0 Crystal Implementation
注
The load capacitors, Cf1 and Cf2 in 图 6-2, should be chosen such that the below equation is
satisfied. CL in the equation is the load specified by the crystal manufacturer. All discrete
components used to implement the oscillator circuit should be placed as close as possible to
the associated oscillator xi_osc0, xo_osc0, and vssa_osc0 pins.
Cf1Cf2
C
= (Cf1+Cf2)
L
图 6-3. Load Capacitance Equation
The crystal must be in the fundamental mode of operation and parallel resonant. 表 6-1 summarizes the
required electrical constraints.
表 6-1. OSC0 Crystal Electrical Characteristics
NAME
fp
DESCRIPTION
Parallel resonance crystal frequency
Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2
MIN
TYP
MAX UNIT
19.2, 20, 27
MHz
Cf1
12
24
pF
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表 6-1. OSC0 Crystal Electrical Characteristics (continued)
NAME
DESCRIPTION
MIN
TYP
MAX UNIT
Cf2
Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2
12
24
pF
ESR(Cf1,Cf2)
Crystal ESR
100
Ω
(1)
ESR = 30 Ω
ESR = 40 Ω
19.2 MHz, 20 MHz, 27 MHz
7
pF
19.2 MHz, 20 MHz
27 MHz
7
5
7
pF
pF
pF
-
ESR = 50 Ω
19.2 MHz, 20 MHz
27 MHz
ESR = 60 Ω
ESR = 80 Ω
ESR = 100 Ω
CO
Crystal shunt capacitance
Not Supported
Not Supported
19.2 MHz, 20 MHz
27 MHz
5
3
pF
-
19.2 MHz, 20 MHz
27 MHz
pF
-
Not Supported
10.16
LM
Crystal motional inductance for fp = 20 MHz
Crystal motional capacitance
mH
fF
CM
3.42
Ethernet and MLB not used
±200
±50
Ethernet RGMII and RMII
using derived clock
tj(xiosc0)
Frequency accuracy(1), xi_osc0
ppm
Ethernet MII using derived
clock
±100
±50
MLB using derived clock
(1) Crystal characteristics should account for tolerance+stability+aging.
When selecting a crystal, the system design must take into account the temperature and aging
characteristics of a crystal versus the user environment and expected lifetime of the system.
表 6-2 details the switching characteristics of the oscillator and the requirements of the input clock.
表 6-2. Oscillator Switching Characteristics—Crystal Mode
NAME
fp
DESCRIPTION
MIN
TYP
MAX
UNIT
Oscillation frequency
Start-up time
19.2, 20, 27 MHz
MHz
ms
tsX
4
6.1.2.2 OSC0 Input Clock
A 1.8-V LVCMOS-Compatible Clock Input can be used instead of the internal oscillator to provide the
SYS_CLKIN1 clock input to the system. The external connections to support this are shown in 图 6-4. The
xi_osc0 pin is connected to the 1.8-V LVCMOS-Compatible clock source. The xi_osc0 pin is left
unconnected. The vssa_osc0 pin is connected to board ground (VSS).
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Device
xo_osc0
vssa_osc0
xi_osc0
NC
SPRS906_CLK_04
图 6-4. 1.8-V LVCMOS-Compatible Clock Input
表 6-3 summarizes the OSC0 input clock electrical characteristics.
表 6-3. OSC0 Input Clock Electrical Characteristics—Bypass Mode
NAME
DESCRIPTION
MIN
TYP
19.2, 20, 27
2.384
MAX
UNIT
MHz
pF
f
Frequency
CIN
IIN
Input capacitance
2.184
4
2.584
10
Input current (3.3V mode)
6
µA
表 6-4 details the OSC0 input clock timing requirements.
表 6-4. OSC0 Input Clock Timing Requirements
NAME
DESCRIPTION
MIN
TYP
19.2, 20, 27
MAX
UNIT
1 /
tc(xiosc0)
CK0
Frequency, xi_osc0
MHz
0.55 *
tc(xiosc0)
0.45 *
tc(xiosc0)
CK1
tw(xiosc0) Pulse duration, xi_osc0 low or high
tj(xiosc0) Period jitter(1), xi_osc0
ns
ns
0.01 ×
tc(xiosc0)
tR(xiosc0) Rise time, xi_osc0
tF(xiosc0) Fall time, xi_osc0
5
5
ns
ns
Ethernet and MLB not used
±200
Ethernet RGMII and RMII
using derived clock
±50
tj(xiosc0) Frequency accuracy(2), xi_osc0
ppm
Ethernet MII using derived
clock
±100
±50
MLB using derived clock
(1) Period jitter is meant here as follows:
– The maximum value is the difference between the longest measured clock period and the expected clock period
– The minimum value is the difference between the shortest measured clock period and the expected clock period
(2) Crystal characteristics should account for tolerance+stability+aging.
CK0
CK1
CK1
xi_osc0
SPRS906_CLK_05
图 6-5. xi_osc0 Input Clock
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6.1.3 Auxiliary Oscillator OSC1 Input Clock
SYS_CLKIN2 is received directly from oscillator OSC1. For more information about SYS_CLKIN2 see
Device TRM, Chapter: Power, Reset, and Clock Management.
6.1.3.1 OSC1 External Crystal
An external crystal is connected to the device pins. 图 6-6 describes the crystal implementation.
Device
xo_osc1
xi_osc1
vssa_osc1
Rd
(Optional)
Crystal
Cf2
Cf1
SPRS906_CLK_06
图 6-6. Crystal Implementation
注
The load capacitors, Cf1 and Cf2 in 图 6-6, should be chosen such that the below equation is
satisfied. CL in the equation is the load specified by the crystal manufacturer. All discrete
components used to implement the oscillator circuit should be placed as close as possible to
the associated oscillator xi_osc1, xo_osc1, and vssa_osc1 pins.
Cf1Cf2
C
= (Cf1+Cf2)
L
图 6-7. Load Capacitance Equation
The crystal must be in the fundamental mode of operation and parallel resonant. 表 6-5 summarizes the
required electrical constraints.
表 6-5. OSC1 Crystal Electrical Characteristics
NAME
fp
DESCRIPTION
Parallel resonance crystal frequency
MIN
TYP
MAX
UNIT
MHz
pF
Range from 19.2 to 32
Cf1
Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2
Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2
12
12
24
24
Cf2
pF
ESR(Cf1,Cf2) Crystal ESR
100
Ω
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表 6-5. OSC1 Crystal Electrical Characteristics (continued)
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
pF
pF
pF
pF
-
ESR = 30 Ω 19.2 MHz ≤ fp ≤ 32 MHz
ESR = 40 Ω 19.2 MHz ≤ fp ≤ 32 MHz
19.2 MHz ≤ fp ≤ 25 MHz
7
5
7
5
ESR = 50 Ω 25 MHz < fp ≤ 27 MHz
27 MHz < fp ≤ 32 MHz
Not Supported
Not Supported
Not Supported
19.2 MHz ≤ fp ≤ 23 MHz
7
5
pF
pF
-
CO
Crystal shunt capacitance
ESR = 60 Ω 23 MHz < fp ≤ 25 MHz
25 MHz < fp ≤ 32 MHz
19.2 MHz ≤ fp ≤ 23 MHz
5
3
pF
pF
-
ESR = 80 Ω 23 MHz ≤ fp ≤ 25 MHz
25 MHz < fp ≤ 32 MHz
19.2 MHz ≤ fp ≤ 20 MHz
ESR = 100 Ω
3
pF
-
20 MHz < fp ≤ 32 MHz
Not Supported
10.16
LM
Crystal motional inductance for fp = 20 MHz
Crystal motional capacitance
mH
fF
CM
3.42
Ethernet and MLB not used
±200
±50
Ethernet RGMII and RMII
using derived clock
tj(xiosc1)
Frequency accuracy(1), xi_osc1
ppm
Ethernet MII using derived
clock
±100
±50
MLB using derived clock
(1) Crystal characteristics should account for tolerance+stability+aging.
When selecting a crystal, the system design must take into account the temperature and aging
characteristics of a crystal versus the user environment and expected lifetime of the system.
表 6-6 details the switching characteristics of the oscillator and the requirements of the input clock.
表 6-6. Oscillator Switching Characteristics—Crystal Mode
NAME
fp
DESCRIPTION
MIN
TYP
MAX
UNIT
Oscillation frequency
Start-up time
Range from 19.2 to 32
MHz
ms
tsX
4
6.1.3.2 OSC1 Input Clock
A 1.8-V LVCMOS-Compatible Clock Input can be used instead of the internal oscillator to provide the
SYS_CLKIN2 clock input to the system. The external connections to support this are shown in, 图 6-8.
The xi_osc1 pin is connected to the 1.8-V LVCMOS-Compatible clock sources. The xo_osc1 pin is left
unconnected. The vssa_osc1 pin is connected to board ground (vss).
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Device
xo_osc1
vssa_osc1
xi_osc1
NC
SPRS906_CLK_07
图 6-8. 1.8-V LVCMOS-Compatible Clock Input
表 6-7 summarizes the OSC1 input clock electrical characteristics.
表 6-7. OSC1 Input Clock Electrical Characteristics—Bypass Mode
NAME
f
DESCRIPTION
MIN
TYP
MAX
UNIT
MHz
pF
Frequency
Range from 12 to 38.4
CIN
IIN
Input capacitance
2.819
3.019
6
See(2)
3.219
10
Input current (3.3V mode)
Start-up time(1)
4
µA
tsX
ms
(1) To switch from bypass mode to crystal or from crystal mode to bypass mode, there is a waiting time about 100 μs; however, if the chip
comes from bypass mode to crystal mode the crystal will start-up after time mentioned in 表 6-6, tsX parameter.
(2) Before the processor boots up and the oscillator is set to bypass mode, there is a waiting time when the internal oscillator is in
application mode and receives a wave. The switching time in this case is about 100 μs.
表 6-8 details the OSC1 input clock timing requirements.
表 6-8. OSC1 Input Clock Timing Requirements
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
1 /
tc(xiosc1)
CK0
Frequency, xi_osc1
Range from 12 to 38.4
MHz
0.45 *
tc(xiosc1)
0.55 *
tc(xiosc1)
CK1
tw(xiosc1) Pulse duration, xi_osc1 low or high
tj(xiosc1) Period jitter(1), xi_osc1
ns
ns
0.01 ×
tc(xiosc1)
(3)
tR(xiosc1) Rise time, xi_osc1
tF(xiosc1) Fall time, xi_osc1
5
5
ns
ns
Ethernet and MLB not used
±200
Ethernet RGMII and RMII
using derived clock
±50
tj(xiosc1) Frequency accuracy(2), xi_osc1
ppm
Ethernet MII using derived
clock
±100
±50
MLB using derived clock
(1) Period jitter is meant here as follows:
–
–
The maximum value is the difference between the longest measured clock period and the expected clock period
The minimum value is the difference between the shortest measured clock period and the expected clock period
(2) Crystal characteristics should account for tolerance+stability+aging.
(3) The Period jitter requirement for osc1 can be relaxed to 0.02*tc(xiosc1) under the following constraints:
a.The osc1/SYS_CLK2 clock bypasses all device PLLs
b.The osc1/SYS_CLK2 clock is only used to source the DSS pixel clock outputs
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CK0
CK1
CK1
xi_osc1
SPRS906_CLK_08
图 6-9. xi_osc1 Input Clock
6.1.4 RTC Oscillator Input Clock
SYS_32K is received directly from RTC Oscillator. For more information about SYS_32K see the Device
TRM, Power, Reset, and Clock Management chapter.
6.1.4.1 RTC Oscillator External Crystal
An external crystal is connected to the device pins. 图 6-10 describes the crystal implementation.
Device
rtc_osc_xo
Rd
rtc_osc_xi_clkin32
Crystal
(Optional)
Cf2
Cf1
SPRS906_CLK_01
图 6-10. Crystal Implementation
注
The load capacitors, Cf1 and Cf2 in 图 6-10, should be chosen such that the below equation is
satisfied. CL in the equation is the load specified by the crystal manufacturer. All discrete
components used to implement the oscillator circuit should be placed as close as possible to
the associated oscillator rtc_osc_xi_clkin32 and rtc_osc_xo pins.
Cf1Cf2
C
= (Cf1+Cf2)
L
图 6-11. Load Capacitance Equation
The crystal must be in the fundamental mode of operation and parallel resonant. 表 6-9 summarizes the
required electrical constraints.
表 6-9. RTC Crystal Electrical Characteristics
NAME
fp
DESCRIPTION
Parallel resonance crystal frequency
MIN
TYP
32.768
MAX
UNIT
kHz
pF
Cf1
Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2
Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2
12
12
24
24
Cf2
pF
176
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表 6-9. RTC Crystal Electrical Characteristics (continued)
NAME
DESCRIPTION
MIN
TYP
MAX
80
UNIT
kΩ
ESR(Cf1,Cf2)
Crystal ESR
CO
LM
CM
Crystal shunt capacitance
5
pF
Crystal motional inductance for fp = 32,768 kHz
Crystal motional capacitance
10.7
2.2
mH
fF
tj(rtc_osc_xi_clkin32) Frequency accuracy, rtc_osc_xi_clkin32
±200
ppm
When selecting a crystal, the system design must take into account the temperature and aging
characteristics of a crystal versus the user environment and expected lifetime of the system.
表 6-10 details the switching characteristics of the oscillator and the requirements of the input clock.
表 6-10. Oscillator Switching Characteristics—Crystal Mode
NAME
fp
DESCRIPTION
MIN
TYP
32.768
MAX
UNIT
Oscillation frequency
Start-up time
kHz
ms
tsX
4
6.1.4.2 RTC Oscillator Input Clock
A 1.8-V LVCMOS-Compatible Clock Input can be used instead of the internal oscillator to provide the
SYS_32K clock input to the system. The external connections to support this are shown in 图 6-12. The
rtc_osc_xi_clkin32 pin is connected to the 1.8-V LVCMOS-Compatible clock sources. The rtc_osc_xo pin
is left unconnected.
Device
rtc_osc_xo
rtc_osc_xi_clkin32
NC
SPRS906_CLK_10
图 6-12. LVCMOS-Compatible Clock Input
表 6-11 summarizes the RTC Oscillator input clock electrical characteristics.
表 6-11. RTC Oscillator Input Clock Electrical Characteristics—Bypass Mode
NAME
DESCRIPTION
MIN
TYP
32.768
MAX
UNIT
CK0
CK1
1/tc(rtc_osc_xi_clkin32) Frequency, rtc_osc_xi_clkin32
kHz
Pulse duration, rtc_osc_xi_clkin32 low or
high
0.45 *
tc(rtc_osc_xi_clkin32)
0.55 *
tc(rtc_osc_xi_clkin32)
tw(rtc_osc_xi_clkin32)
ns
CIN
IIN
Input capacitance
Input current (3.3V mode)
Start-up time
2.178
4
2.378
6
See (1)
2.578
10
pF
µA
ms
tsX
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(1) Before the processor boots up and the oscillator is set to bypass mode, there is a waiting time when the internal oscillator is
inapplication mode and receives a wave. The switching time in this case is about 100 μs.
CK0
CK1
CK1
rtc_osc_xi_clkin32
SPRS906_CLK_11
图 6-13. rtc_osc_xi_clkin32 Input Clock
6.1.4.3 RC On-die Oscillator Clock
注
The OSC_32K_CLK clock, provided by the On-die 32K RC oscillator, inside of the SoC, is
not accurate 32kHz clock.
The frequency may significantly vary with temperature and silicon characteristics.
For more information about OSC_32K_CLK see the Device TRM, Chapter: Power, Reset, and Clock
Management.
6.2 DPLLs, DLLs Specifications
注
For more information, see:
•
Power, Reset, and Clock Management / Clock Management Functional / Internal Clock
Sources / Generators / Generic DPLL Overview Section
and
•
Display Subsystem / Display Subsystem Overview section of the Device TRM.
To generate high-frequency clocks, the device supports multiple on-chip DPLLs controlled directly by the
PRCM module. They are of two types: type A and type B DPLLs.
•
They have their own independent power domain (each one embeds its own switch and can be
controlled as an independent functional power domain)
•
They are fed with ALWAYS ON system clock, with independent control per DPLL.
The different DPLLs managed by the PRCM are listed below:
•
•
•
•
DPLL_MPU: It supplies the MPU subsystem clocking internally.
DPLL_IVA: It feeds the IVA subsystem clocking.
DPLL_CORE: It supplies all interface clocks and also few module functional clocks.
DPLL_PER: It supplies several clock sources: a 192-MHz clock for the display functional clock, a
96-MHz functional clock to subsystems and peripherals.
•
•
•
•
•
•
DPLL_ABE: It provides clocks to various modules within the device.
DPLL_USB: It provides 960M clock for USB modules (USB1/2/3/4).
DPLL_GMAC: It supplies several clocks for the Gigabit Ethernet Switch (GMAC_SW).
DPLL_DSP: It feeds the DSP Subsystem clocking.
DPLL_GPU: It supplies clock for the GPU Subsystem.
DPLL_DDR: It generates clocks for the two External Memory Interface (EMIF) controllers and their
associated EMIF PHYs.
•
•
DPLL_PCIE_REF: It provides reference clock for the APLL_PCIE in PCIE Subsystem.
APLL_PCIE: It feeds clocks for the device Peripheral Component Interconnect Express (PCIe)
controllers.
178
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注
The following DPLLs are controlled by the clock manager located in the always-on Core
power domain (CM_CORE_AON):
•
DPLL_MPU, DPLL_IVA, DPLL_CORE, DPLL_ABE, DPLL_DDR, DPLL_GMAC,
DPLL_PCIE_REF, DPLL_PER, DPLL_USB, DPLL_DSP, DPLL_GPU, APLL_PCIE_REF.
For more information on CM_CORE_AON and CM_CORE or PRCM DPLLs, see the Power, Reset, and
Clock Management (PRCM) chapter of the Device TRM.
The following DPLLs are not managed by the PRCM:
•
•
•
•
•
DPLL_VIDEO1; (It is controlled from DSS)
DPLL_HDMI; (It is controlled from DSS)
DPLL_SATA; (It is controlled from SATA)
DPLL_DEBUG; (It is controlled from DEBUGSS)
DPLL_USB_OTG_SS; (It is controlled from OCP2SCP1)
注
For more information for not controlled from PRCM DPLL’s see the related chapters in TRM.
6.2.1 DPLL Characteristics
The DPLL has three relevant input clocks. One of them is the reference clock (CLKINP) used to generated
the synthesized clock but can also be used as the bypass clock whenever the DPLL enters a bypass
mode. It is therefore mandatory. The second one is a fast bypass clock (CLKINPULOW) used when
selected as the bypass clock and is optional. The third clock (CLKINPHIF) is explained in the next
paragraph.
The DPLL has three output clocks (namely CLKOUT, CLKOUTX2, and CLKOUTHIF). CLKOUT and
CLKOUTX2 run at the bypass frequency whenever the DPLL enters a bypass mode. Both of them are
generated from the lock frequency divided by a post-divider (namely M2 post-divider). The third clock,
CLKOUTHIF, has no automatic bypass capability. It is an output of a post-divider (M3 post-divider) with
the input clock selectable between the internal lock clock (Fdpll) and CLKINPHIF input of the PLL through
an asynchronous multplexing.
For more information, see the Power Reset Controller Management chapter of the Device TRM.
表 6-12 summarizes DPLL type described in 节 6.2, DPLLs, DLLs Specifications introduction.
表 6-12. DPLL Control Type
DPLL NAME
DPLL_ABE
TYPE
CONTROLLED BY PRCM
(1)
表 6-13 (Type A)
表 6-13 (Type A)
表 6-13 (Type A)
表 6-13 (Type A)
表 6-13 (Type A)
表 6-14 (Type B)
表 6-13 (Type A)
表 6-13 (Type A)
表 6-13 (Type A)
表 6-13 (Type A)
表 6-14 (Type B)
表 6-14 (Type B)
Yes
(1)
DPLL_CORE
DPLL_DEBUGSS
DPLL_DSP
Yes
(2)
No
(1)
Yes
(1)
DPLL_GMAC
DPLL_HDMI
DPLL_IVA
Yes
(2)
No
(1)
Yes
(1)
DPLL_MPU
Yes
(1)
DPLL_PER
Yes
(1)
APLL_PCIE
Yes
(1)
DPLL_PCIE_REF
DPLL_SATA
Yes
(2)
No
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表 6-12. DPLL Control Type (continued)
DPLL NAME
DPLL_USB
TYPE
CONTROLLED BY PRCM
(1)
表 6-14 (Type B)
表 6-14 (Type B)
表 6-13 (Type A)
表 6-13 (Type A)
表 6-13 (Type A)
Yes
(2)
DPLL_USB_OTG_SS
DPLL_VIDEO1
No
No
(2)
(1)
(1)
DPLL_DDR
Yes
Yes
DPLL_GPU
(1) DPLL is in the always-on domain.
(2) DPLL is not controlled by the PRCM.
表 6-13 and 表 6-14 summarize the DPLL characteristics and assume testing over recommended
operating conditions.
表 6-13. DPLL Type A Characteristics
NAME
finput
DESCRIPTION
MIN
0.032
0.15
10
TYP
MAX
52
UNIT
MHz
MHz
MHz
COMMENTS
CLKINP input frequency
Internal reference frequency
CLKINPHIF input frequency
FINP
finternal
52
REFCLK
FINPHIF
fCLKINPHIF
1400
Bypass mode: fCLKOUT
=
fCLKINPULOW
CLKINPULOW input frequency
0.001
600
MHz
MHz
fCLKINPULOW / (M1 + 1) if
ulowclken = 1
(6)
[M / (N + 1)] × FINP × [1 / M2]
(in locked condition)
(1)
(2)
fCLKOUT
CLKOUT output frequency
CLKOUTx2 output frequency
20
1800
2 × [M / (N + 1)] × FINP × [1 /
M2] (in locked condition)
(1)
(2)
(4)
(4)
fCLKOUTx2
40
2200
1400
2200
MHz
MHz
MHz
(3)
20
FINPHIF / M3 if clkinphifsel = 1
fCLKOUTHIF
CLKOUTHIF output frequency
2 × [M / (N + 1)] × FINP × [1 /
M3] if clkinphifsel = 0
(3)
40
DCOCLKLDO output
frequency
2 × [M / (N + 1)] × FINP (in
locked condition)
fCLKDCOLDO
tlock
40
2800
MHz
µs
6 + 350 ×
REFCLK
Frequency lock time
Phase lock time
6 + 500 ×
REFCLK
plock
µs
Relock time—Frequency
lock(5) (LP relock time from
bypass)
Relock time—Phase lock(5)
(LP relock time from bypass)
6 + 70 ×
REFCLK
DPLL in LP relock time:
lowcurrstdby = 1
trelock-L
prelock-L
trelock-F
prelock-F
µs
µs
µs
µs
6 + 120 ×
REFCLK
DPLL in LP relock time:
lowcurrstdby = 1
Relock time—Frequency
lock(5) (fast relock time from
bypass)
Relock time—Phase lock(5)
(fast relock time from bypass)
3.55 + 70 ×
REFCLK
DPLL in fast relock time:
lowcurrstdby = 0
3.55 + 120 ×
REFCLK
DPLL in fast relock time:
lowcurrstdby = 0
(1) The minimum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1.
For M2 > 1, the minimum frequency on these clocks will further scale down by factor of M2.
(2) The maximum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1.
(3) The minimum frequency on CLKOUTHIF is assuming M3 = 1. For M3 > 1, the minimum frequency on this clock will further scale down
by factor of M3.
(4) The maximum frequency on CLKOUTHIF is assuming M3 = 1.
(5) Relock time assumes typical operating conditions, 10°C maximum temperature drift.
(6) Bypass mode: fCLKOUT = FINP if ulowclken = 0. For more information, see the Device TRM.
180
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表 6-14. DPLL Type B Characteristics
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
COMMENTS
finput
CLKINP input clock frequency
0.62
60
MHz
FINP
REFCLK internal reference
clock frequency
finternal
0.62
2.5
MHz
[1 / (N + 1)] × FINP
Bypass mode: fCLKOUT
=
CLKINPULOW bypass input
clock frequency
fCLKINPULOW
0.001
600
MHz
fCLKINPULOW / (M1 + 1) If
(4)
ulowclken = 1
CLKOUTLDO output clock
frequency
M / (N + 1)] × FINP × [1 / M2]
(in locked condition)
(1)(5)
(2)(5)
fCLKLDOOUT
fCLKOUT
fCLKDCOLDO
20
2500
MHz
MHz
CLKOUT output clock
frequency
[M / (N + 1)] × FINP × [1 / M2]
(in locked condition)
(1)(5)
(2)(5)
20
1450
(5)
(5)
750
1500
MHz
MHz
Internal oscillator (DCO) output
clock frequency
[M / (N + 1)] × FINP (in locked
condition)
(5)
(5)
1250
2500
CLKOUTLDO period jitter
CLKOUT period jitter
The period jitter at the output
clocks is ± 2.5% peak to peak
tJ
–2.5%
2.5%
CLKDCOLDO period jitter
350 ×
REFCLKs
tlock
plock
trelock-L
prelock-L
Frequency lock time
µs
µs
µs
µs
500 ×
REFCLKs
Phase lock time
Relock time—Frequency lock(3)
(LP relock time from bypass)
Relock time—Phase lock(3) (LP
relock time from bypass)
9 + 30 ×
REFCLKs
9 + 125 ×
REFCLKs
(1) The minimum frequency on CLKOUT is assuming M2 = 1.
For M2 > 1, the minimum frequency on this clock will further scale down by factor of M2.
(2) The maximum frequency on CLKOUT is assuming M2 = 1.
(3) Relock time assumes typical operating conditions, 10°C maximum temperature drift.
(4) Bypass mode: fCLKOUT = FINP if ULOWCLKEN = 0. For more information, see the Device TRM.
(5) For output clocks, there are two frequency ranges according to the SELFREQDCO setting. For more information, see the Device TRM.
6.2.2 DLL Characteristics
表 6-15 summarizes the DLL characteristics and assumes testing over recommended operating
conditions.
表 6-15. DLL Characteristics
NAME
finput
DESCRIPTION
Input clock frequency (EMIF_DLL_FCLK)
MIN
TYP
MAX
266
50k
UNIT
MHz
tlock
Lock time
cycles
cycles
trelock
Relock time (a change of the DLL frequency implies that DLL must relock)
50k
6.2.3 DPLL and DLL Noise Isolation
注
For more information on DPLL and DLL decoupling capacitor requirements, see the External
Capacitors / Voltage Decoupling Capacitors / I/O and Analog Voltage Decoupling / VDDA
Power Domain section.
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7 Timing Requirements and Switching Characteristics
7.1 Timing Test Conditions
All timing requirements and switching characteristics are valid over the recommended operating conditions
unless otherwise specified.
7.2 Interface Clock Specifications
7.2.1 Interface Clock Terminology
The interface clock is used at the system level to sequence the data and/or to control transfers accordingly
with the interface protocol.
7.2.2 Interface Clock Frequency
The two interface clock characteristics are:
•
•
The maximum clock frequency
The maximum operating frequency
The interface clock frequency documented in this document is the maximum clock frequency, which
corresponds to the maximum frequency programmable on this output clock. This frequency defines the
maximum limit supported by the Device IC and does not take into account any system consideration
(PCB, peripherals).
The system designer will have to consider these system considerations and the Device IC timing
characteristics as well to define properly the maximum operating frequency that corresponds to the
maximum frequency supported to transfer the data on this interface.
7.3 Timing Parameters and Information
The timing parameter symbols used in the timing requirement and switching characteristic tables are
created in accordance with JEDEC Standard 100. To shorten the symbols, some of pin names and other
related terminologies have been abbreviated as follows:
表 7-1. Timing Parameters
SUBSCRIPTS
SYMBOL
PARAMETER
c
Cycle time (period)
d
Delay time
dis
Disable time
en
Enable time
h
Hold time
su
Setup time
START
Start bit
t
v
Transition time
Valid time
w
X
F
Pulse duration (width)
Unknown, changing, or don't care level
Fall time
High
H
L
Low
R
V
IV
Rise time
Valid
Invalid
182
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表 7-1. Timing Parameters (continued)
SUBSCRIPTS
SYMBOL
PARAMETER
AE
FE
LE
Z
Active Edge
First Edge
Last Edge
High impedance
7.3.1 Parameter Information
Tester Pin Electronics
Transmission Line
Data Sheet Timing Reference Point
42 Ω
3.5 nH
Output
Under
Test
Z0 = 50 Ω
(see Note)
Device Pin
(see Note)
4.0 pF
1.85 pF
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be
taken into account.Atransmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission line is
intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
pm_tstcirc_prs403
图 7-1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals.
This load capacitance value does not indicate the maximum load the device is capable of driving.
7.3.1.1 1.8V and 3.3V Signal Transition Levels
All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. Vref = (VDD
I/O)/2.
Vref
pm_io_volt_prs403
图 7-2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL
MAX and VOH MIN for output clocks.
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Vref = VIH MIN (or VOH MIN)
Vref = VIL MAX (or VOL MAX)
pm_transvolt_prs403
图 7-3. Rise and Fall Transition Time Voltage Reference Levels
7.3.1.2 1.8V and 3.3V Signal Transition Rates
The default SLEWCONTROL settings in each pad configuration register must be used to guaranteed
timings, unless specific instructions otherwise are given in the individual timing sub-sections of the
datasheet.
All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).
7.3.1.3 Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data manual do not include delays by board routes. As a
good board design practice, such delays must always be taken into account. Timing values may be
adjusted by increasing/decreasing such delays. TI recommends using the available I/O buffer information
specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to
attain accurate timing analysis for a given system, see the Using IBIS Models for timing Analysis
application report (literature number SPRA839). If needed, external logic hardware such as buffers may be
used to compensate any timing differences.
7.4 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner. Monotonic transitions are more easily guaranteed with faster switching signals. Slower input
transitions are more susceptible to glitches due to noise and special care should be taken for slow input
clocks.
7.5 Virtual and Manual I/O Timing Modes
Some of the timings described in the following sections require the use of Virtual or Manual I/O Timing
Modes. 表 7-2 provides a summary of the Virtual and Manual I/O Timing Modes across all device
interfaces. The individual interface timing sections found later in this document provide the full description
of each applicable Virtual and Manual I/O Timing Mode. Refer to the "Pad Configuration" section of the
TRM for the procedure on implementing the Virtual and Manual Timing Modes in a system.
表 7-2. Modes Summary
Virtual or Manual IO Mode Name
DPI Video Output
Data Manual Timing Mode
No Virtual or Manual IO Timing Mode Required
DSS_VIRTUAL1
DPI1/3 Video Output Default Timings - Rising-edge Clock Reference
DPI1/3 Video Output Default Timings - Falling-edge Clock Reference
DPI1 Video Output Alternate Timings
VOUT1_MANUAL1
VOUT1_MANUAL4
DPI1 Video Output MANUAL4 Timings
VOUT1_MANUAL5
DPI1 Video Output MANUAL5 Timings
VOUT2_IOSET1_MANUAL1
VOUT2_IOSET1_MANUAL2
VOUT2_IOSET1_MANUAL3
VOUT2_IOSET1_MANUAL4
VOUT2_IOSET1_MANUAL5
VOUT2_IOSET2_MANUAL1
VOUT2_IOSET2_MANUAL2
DPI2 Video Output IOSET1 Alternate Timings
DPI2 Video Output IOSET1 Default Timings - Rising-edge Clock Reference
DPI2 Video Output IOSET1 Default Timings - Falling-edge Clock Reference
DPI2 Video Output IOSET1 MANUAL4 Timings
DPI2 Video Output IOSET1 MANUAL5 Timings
DPI2 Video Output IOSET2 Alternate Timings
DPI2 Video Output IOSET2 Default Timings - Rising-edge Clock Reference
184
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表 7-2. Modes Summary (continued)
Virtual or Manual IO Mode Name
VOUT2_IOSET2_MANUAL3
Data Manual Timing Mode
DPI2 Video Output IOSET2 Default Timings - Falling-edge Clock Reference
DPI2 Video Output IOSET2 MANUAL4 Timings
DPI2 Video Output IOSET2 MANUAL5 Timings
DPI3 Video Output Alternate Timings
VOUT2_IOSET2_MANUAL4
VOUT2_IOSET2_MANUAL5
VOUT3_MANUAL1
VOUT3_MANUAL4
DPI3 Video Output MANUAL4 Timings
VOUT3_MANUAL5
DPI3 Video Output MANUAL5 Timings
GPMC
No Virtual or Manual IO Timing Mode Required
GPMC_VIRTUAL1
GPMC Asynchronous Mode Timings and Synchronous Mode - Default Timings
GPMC Synchronous Mode - Alternate Timings
McASP
No Virtual or Manual IO Timing Mode Required
MCASP1_VIRTUAL1_SYNC_RX
MCASP1_VIRTUAL2_ASYNC_RX
No Virtual or Manual IO Timing Mode Required
MCASP2_VIRTUAL1_SYNC_RX_80M
MCASP2_VIRTUAL2_ASYNC_RX
MCASP2_VIRTUAL3_SYNC_RX
MCASP2_VIRTUAL4_ASYNC_RX_80M
No Virtual or Manual IO Timing Mode Required
MCASP3_VIRTUAL2_SYNC_RX
No Virtual or Manual IO Timing Mode Required
MCASP4_VIRTUAL1_SYNC_RX
No Virtual or Manual IO Timing Mode Required
MCASP5_VIRTUAL1_SYNC_RX
No Virtual or Manual IO Timing Mode Required
MCASP6_VIRTUAL1_SYNC_RX
No Virtual or Manual IO Timing Mode Required
MCASP7_VIRTUAL2_SYNC_RX
No Virtual or Manual IO Timing Mode Required
MCASP8_VIRTUAL1_SYNC_RX
eMMC/SD/SDIO
McASP1 Asynchronous and Synchronous Transmit Timings
See 表 7-50
See 表 7-50
McASP2 Asynchronous and Synchronous Transmit Timings
See 表 7-51
See 表 7-51
See 表 7-51
See 表 7-51
McASP3 Synchronous Transmit Timings
See 表 7-52
McASP4 Synchronous Transmit Timings
See 表 7-53
McASP5 Synchronous Transmit Timings
See 表 7-54
McASP6 Synchronous Transmit Timings
See 表 7-55
McASP7 Synchronous Transmit Timings
See 表 7-56
McASP8 Synchronous Transmit Timings
See 表 7-57
No Virtual or Manual IO Timing Mode Required
MMC1 DS (Pad Loopback), HS (Internal Loopback and Pad Loopback), SDR12
(Internal Loopback and Pad Loopback), and SDR25 Timings (Internal Loopback and
Pad Loopback) Timings
MMC1_VIRTUAL1
MMC1 SDR50 (Pad Loopback) Timings
MMC1 DS (Internal Loopback) Timings
MMC1 SDR50 (Internal Loopback) Timings
MMC1 DDR50 (Internal Loopback) Timings
MMC1 DDR50 (Pad Loopback) Timings
MMC1 SDR104 Timings
MMC1_VIRTUAL4
MMC1_VIRTUAL5
MMC1_VIRTUAL6
MMC1_MANUAL1
MMC1_MANUAL2
No Virtual or Manual IO Timing Mode Required
MMC2_VIRTUAL2
MMC2 Standard (Pad Loopback), High Speed (Pad Loopback) Timings
MMC2 Standard (Internal Loopback), High Speed (Internal Loopback) Timings
MMC2 DDR (Pad Loopback) Timings
MMC2_MANUAL1
MMC2_MANUAL2
MMC2 DDR (Internal Loopback Manual) Timings
MMC2 HS200 Timings
MMC2_MANUAL3
No Virtual or Manual IO Timing Mode Required
MMC3_MANUAL1
MMC3 DS, SDR12, HS, SDR25 Timings
MMC3 SDR50 Timings
No Virtual or Manual IO Timing Mode Required
MMC4 DS, SDR12, HS, SDR25 Timings
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表 7-2. Modes Summary (continued)
Virtual or Manual IO Mode Name
QSPI
Data Manual Timing Mode
No Virtual or Manual IO Timing Mode Required
QSPI1_MANUAL1
QSPI Mode 3 Timings
QSPI Mode 0 Timings
GMAC
No Virtual or Manual IO Timing Mode Required
GMAC_RGMII0_MANUAL1
GMAC_RGMII1_MANUAL1
GMAC_RMII0_MANUAL1
GMAC_RMII1_MANUAL1
VIP
GMAC MII0/1 Timings
GMAC RGMII0 with Transmit Clock Internal Delay Enabled
GMAC RGMII1 with Transmit Clock Internal Delay Enabled
GMAC RMII0 Timings
GMAC RMII1 Timings
VIP_MANUAL1
VIN1A (IOSET7) and VIN2A (IOSET10) Rise-Edge Capture Mode Timings
VIN1A (IOSET7) and VIN2A (IOSET10) Fall-Edge Capture Mode Timings
VIN2A (IOSET4/5/6) Rise-Edge Capture Mode Timings
VIP_MANUAL2
VIP_MANUAL3
VIP_MANUAL4
VIN2B (IOSET7/8/9) Rise-Edge Capture Mode Timings
VIP_MANUAL5
VIN2A (IOSET4/5/6) Fall-Edge Capture Mode Timings
VIP_MANUAL6
VIN2B (IOSET7/8/9) Fall-Edge Capture Mode Timings
VIP_MANUAL7
VIN1A (IOSET2/3/4) and VIN1B (IOSET4/7) and VIN2B (IOSET1/10) Rise-Edge
Capture Mode Timings
VIP_MANUAL8
VIP_MANUAL9
VIP_MANUAL10
VIP_MANUAL11
VIP_MANUAL12
VIN1A (IOSET5/6) and VIN2A (IOSET7/8/9) Rise-Edge Capture Mode Timings
VIN1B (IOSET6/7) Rise-Edge Capture Mode Timings
VIN1B (IOSET5) and VIN2B (IOSET2/11) Rise-Edge Capture Mode Timings
VIN1B (IOSET5) and VIN2B (IOSET2/11) Fall-Edge Capture Mode Timings
VIN1A (IOSET2/3/4) and VIN1B (IOSET4/7) and VIN2B (IOSET1/10) Fall-Edge
Capture Mode Timings
VIP_MANUAL13
VIP_MANUAL14
VIP_MANUAL15
VIP_MANUAL16
VIN1A (IOSET5/6) and VIN2A (IOSET7/8/9) Fall-Edge Capture Mode Timings
VIN1B (IOSET6/7) Fall-Edge Capture Mode Timings
VIN1A (IOSET8/9/10) Rise-Edge Capture Mode Timings
VIN1A (IOSET8/9/10) Fall-Edge Capture Mode Timings
HDMI, EMIF, Timers, I2C, HDQ/1-Wire, UART, McSPI, USB, SATA, PCIe, DCAN, GPIO, KBD, PWM, ATL, JTAG, TPIU, RTC, SDMA,
INTC, MLB
No Virtual or Manual IO Timing Mode Required
All Modes
7.6 Video Input Ports (VIP)
The Device includes 1 Video Input Ports (VIP).
表 7-3, 图 7-4 and 图 7-5 present timings and switching characteristics of the VIPs.
CAUTION
The I/O timings provided in this section are valid only for VIN1 and VIN2 if
signals within a single IOSET are used. The IOSETs are defined in 表 7-4 and
表 7-5.
表 7-3. Timing Requirements for VIP (3)(4)(5)
NO.
V1
PARAMETER
tc(CLK)
DESCRIPTION
MIN
6.06 (2)
0.45*P (2)
0.45*P (2)
MAX
UNIT
ns
Cycle time, vinx_clki (3) (5)
Pulse duration, vinx_clki high (3) (5)
Pulse duration, vinx_clki low (3) (5)
V2
tw(CLKH)
ns
V3
tw(CLKL)
ns
186
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表 7-3. Timing Requirements for VIP (3)(4)(5) (continued)
NO.
PARAMETER
tsu(CTL/DATA-CLK)
DESCRIPTION
MIN
3.11 (2)
MAX
UNIT
V4
Input setup time, Control (vinx_dei, vinx_vsynci, vinx_fldi,
ns
vinx_hsynci) and Data (vinx_dn) valid to vinx_clki transition (3) (4) (5)
V6
th(CLK-CTL/DATA)
Input hold time, Control (vinx_dei, vinx_vsynci, vinx_fldi, vinx_hsynci)
and Data (vinx_dn) valid from vinx_clki transition (3) (4) (5)
-0.05 (2)
ns
(1) For maximum frequency of 165 MHz.
(2) P = vinx_clki period.
(3) x in vinx = 1a, 1b, 2a, 2b.
(4) n in dn = 0 to 7 when x = 1b, 2b.
n = 0 to 23 when x = 1a, 2a.
(5) i in clki, dei, vsynci, hsynci and fldi = 0 or 1.
V3
V2
V1
vinx_clki
SPRS906_TIMING_VIP_01
图 7-4. Video Input Ports clock signal
vinx_clki
(positive-edge clocking)
vinx_clki
(negative-edge clocking)
V5
V4
vinx_d[23:0]/sig
SPRS8xx_VIP_02
图 7-5. Video Input Ports timings
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In 表 7-4 and 表 7-5 are presented the specific groupings of signals (IOSET) for use with vin1 and vin2.
表 7-4. VIN1 IOSETs
SIGNALS
IOSET2
IOSET3
IOSET4 (1)
BALL MUX
IOSET5 (1)
BALL MUX
IOSET6 (1)
BALL MUX
vin1a
P4
IOSET7 (1)
BALL MUX
IOSET8
IOSET9
IOSET10
BALL
MUX
BALL
MUX
BALL
MUX
BALL
MUX
BALL
MUX
vin1a_clk0
vin1a_hsync0
vin1a_vsync0
vin1a_fld0
vin1a_de0
vin1a_d0
P1
N7
R4
P9
N9
M6
M2
L5
M1
L6
L4
L3
L2
L1
K2
J1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
B11
C11
E11
D11
B10
B7
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
B11
C11
E11
D11
B10
B7
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
P4
R3
T2
P9
P7
R6
T9
T6
T7
P6
R9
R5
P5
U2
U1
P3
R2
K7
M7
J5
4
4
4
4
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
B26
E21
F20
F21
C23
B14
J14
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
AC5
AB8
AB5
C17
AB4
AD6
AC8
AC3
AC9
AC6
AC7
AC4
AD4
AA4
AB3
AB9
AA3
D17
G16
A21
C18
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
E17
F12
G12
C14
D14
D18
B19
F15
B18
A16
C15
A18
A19
F14
G14
A13
E14
A12
B13
A11
B12
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
E17
F12
G12
C14
D14
C17
B19
F15
B18
A16
C15
A18
A19
F14
G14
A13
E14
A12
B13
A11
B12
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
P7
N1
J7
H6
R6
T9
T6
T7
P6
R9
R5
P5
U2
U1
P3
R2
K7
M7
J5
vin1a_d1
B8
B8
vin1a_d2
A7
A7
G13
J11
vin1a_d3
A8
A8
vin1a_d4
C9
C9
E12
F13
C12
D12
E15
A20
B15
A15
D15
B16
B17
A17
C18
A21
G16
D17
AA3
AB9
AB3
AA4
vin1a_d5
A9
A9
vin1a_d6
B9
B9
vin1a_d7
A10
E8
A10
E8
vin1a_d8
vin1a_d9
D9
D9
vin1a_d10
vin1a_d11
vin1a_d12
vin1a_d13
vin1a_d14
vin1a_d15
vin1a_d16
vin1a_d17
vin1a_d18
vin1a_d19
vin1a_d20
vin1a_d21
vin1a_d22
vin1a_d23
D7
D7
J2
D8
D8
H1
J3
A5
A5
C6
C6
H2
H3
R6
T9
T6
T7
P6
R9
R5
P5
C8
C8
C7
C7
K6
K6
F11
G10
F10
G11
E9
F11
G10
F10
G11
E9
F9
F9
F8
F8
E7
E7
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SIGNALS
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 7-4. VIN1 IOSETs (continued)
IOSET2
BALL MUX
IOSET3
BALL MUX
IOSET4 (1)
BALL MUX
IOSET5 (1)
IOSET6 (1)
BALL MUX
vin1b
V1
IOSET7 (1)
IOSET8
BALL MUX
IOSET9
BALL MUX
IOSET10
BALL MUX
BALL MUX
BALL MUX
vin1b_clk1
vin1b_hsync1
vin1b_vsync1
vin1b_fld1
vin1b_de1
vin1b_d0
P7
H5
H6
M4
N6
K7
M7
J5
6
6
6
6
6
6
6
6
6
6
6
6
6
M4
H5
H6
4
6
6
5
5
5
5
5
5
5
5
5
5
5
5
5
N9
N7
R4
P4
P9
R6
T9
T6
T7
P6
R9
R5
P5
6
6
6
6
6
6
6
6
6
6
6
6
6
U7
V6
W2
V7
U4
V2
Y1
W9
V9
U5
V5
V4
N6
K7
M7
J5
6
6
6
6
6
6
6
6
6
vin1b_d1
vin1b_d2
vin1b_d3
K6
J7
K6
J7
vin1b_d4
vin1b_d5
J4
J4
vin1b_d6
J6
J6
vin1b_d7
H4
H4
(1) The IOSET under this column is only applicable for pins with alternate functionality which allows either VIN1 or VIN2 signals to be mapped to the pins. These alternate functions are
controlled via CTRL_CORE_VIP_MUX_SELECT register. For more information on how to use these options, please refer to Device TRM, chapter Control Module, section Pad
Configuration Registers.
表 7-5. VIN2 IOSETs
SIGNALS
IOSET1
BALL MUX
IOSET2
BALL MUX
IOSET4
IOSET5
IOSET6
IOSET7 (1)
BALL MUX
IOSET8 (1)
BALL MUX
IOSET9 (1)
BALL MUX
IOSET10 (1)
BALL
MUX
BALL
MUX
BALL
vin2a
MUX
BALL
MUX
vin2a_clk0
vin2a_hsync0
vin2a_vsync0
vin2a_fld0
vin2a_de0
vin2a_d0
E1
G1
G6
H7
G2
F2
F3
D1
E2
D2
0
0
0
0
0
0
0
0
0
0
E1
G1
G6
G2
0
0
0
1
V1
U7
V6
W2
V7
U4
V2
Y1
W9
V9
4
4
4
4
4
4
4
4
4
4
B11
C11
E11
D11
B10
B7
3
3
3
3
3
3
3
3
3
3
P4
R3
T2
P9
P7
R6
T9
T6
T7
P6
4
4
4
4
5
4
4
4
4
4
P4
P7
N1
J7
4
4
4
4
4
4
4
4
4
4
B26
E21
F20
F21
C23
B14
J14
G13
J11
E12
8
8
8
8
8
8
8
8
8
8
H6
R6
T9
T6
T7
P6
F2
F3
D1
E2
D2
0
0
0
0
0
vin2a_d1
B8
vin2a_d2
A7
vin2a_d3
A8
vin2a_d4
C9
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IOSET10 (1)
表 7-5. VIN2 IOSETs (continued)
SIGNALS
IOSET1
IOSET2
IOSET4
IOSET5
IOSET6
IOSET7 (1)
IOSET8 (1)
BALL MUX
IOSET9 (1)
BALL MUX
BALL
MUX
BALL
MUX
BALL
MUX
0
BALL
MUX
0
BALL
MUX
BALL MUX
BALL
MUX
8
vin2a_d5
vin2a_d6
F4
C1
E4
F5
E6
D3
F6
D5
C2
C3
C4
B2
D6
C5
A3
B3
B4
B5
A4
F4
C1
E4
F5
E6
D3
F6
D5
C2
C3
C4
B2
D6
C5
A3
B3
B4
B5
A4
U5
V5
V4
V3
Y2
U6
U3
4
4
4
4
4
4
4
A9
B9
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
R9
R5
P5
U2
U1
P3
R2
K7
M7
J5
4
4
4
4
4
4
4
4
4
4
4
R9
R5
P5
U2
U1
P3
R2
K7
M7
J5
4
4
4
4
4
4
4
4
4
4
4
F13
C12
D12
E15
A20
B15
A15
D15
B16
B17
A17
C18
A21
G16
D17
AA3
AB9
AB3
AA4
0
0
8
vin2a_d7
0
0
A10
E8
8
vin2a_d8
0
0
8
vin2a_d9
0
0
D9
D7
D8
A5
8
vin2a_d10
vin2a_d11
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
vin2a_d16
vin2a_d17
vin2a_d18
vin2a_d19
vin2a_d20
vin2a_d21
vin2a_d22
vin2a_d23
0
0
8
0
0
8
0
0
8
0
0
C6
C8
C7
F11
G10
F10
G11
E9
8
0
0
8
0
0
K6
K6
8
0
0
8
0
0
8
0
0
8
0
0
8
0
0
8
0
0
F9
8
0
0
F8
8
0
0
E7
8
vin2b
vin2b_clk1
vin2b_hsync1
vin2b_vsync1
vin2b_fld1
vin2b_de1
vin2b_d0
P7
H5
H6
M4
N6
K7
M7
J5
6
6
6
6
6
6
6
6
6
6
6
6
M4
H5
H6
4
6
6
H7
G1
G6
2
3
3
H7
G1
G6
G2
2
3
3
2
AB5
AC5
AB4
4
4
4
N6
K7
M7
J5
6
6
6
6
6
6
6
6
G2
A4
B5
B4
B3
A3
C5
D6
3
2
2
2
2
2
2
2
AB8
AD6
AC8
AC3
AC9
AC6
AC7
AC4
4
4
4
4
4
4
4
4
A4
B5
B4
B3
A3
C5
D6
2
2
2
2
2
2
2
vin2b_d1
vin2b_d2
vin2b_d3
K6
J7
K6
J7
vin2b_d4
vin2b_d5
J4
J4
vin2b_d6
J6
J6
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表 7-5. VIN2 IOSETs (continued)
SIGNALS
IOSET1
IOSET2
IOSET4
BALL MUX
IOSET5
BALL MUX
IOSET6
BALL MUX
IOSET7 (1)
BALL MUX
B2
IOSET8 (1)
BALL MUX
B2
IOSET9 (1)
BALL MUX
AD4
IOSET10 (1)
BALL MUX
BALL
H4
MUX
BALL
H4
MUX
vin2b_d7
6
6
2
2
4
(1) The IOSET under this column is only applicable for pins with alternate functionality which allows either VIN1 or VIN2 signals to be mapped to the pins. These alternate functions are
controlled via CTRL_CORE_VIP_MUX_SELECT register. For more information on how to use these options, please refer to Device TRM, chapter Control Module, section Pad
Configuration Registers.
注
To configure the desired Manual IO Timing Mode the user must follow the steps described in section "Manual IO Timing Modes" of the
Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more information please see the Control Module
chapter in the Device TRM.
Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See 表 7-2 Modes Summary for a list of IO timings requiring the
use of Manual IO Timings Modes. See Manual Functions Mapping for VIP1 1A IOSET7 and 2A IOSET10 for a definition of the Manual modes.
表 7-6 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
表 7-6. Manual Functions Mapping for VIP1 1A IOSET7 and 2A IOSET10
BALL
BALL NAME
VIP_MANUAL1
VIP_MANUAL2
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
8
8(1)
E21
F20
F21
B14
G13
J11
E12
F13
C12
D12
J14
E15
B15
A15
gpio6_14
gpio6_15
1400
1170
1470
2145
2740
2933
2901
2600
2718
2983
2203
2143
2543
2664
240
240
0
1767
1522
1600
2509
2680
2700
2660
2640
3081
2540
2566
2492
2905
2730
0
0
CFG_GPIO6_14_IN
CFG_GPIO6_15_IN
vin2a_hsync0
vin2a_vsync0
vin2a_fld0
vin2a_d0
vin2a_d2
vin2a_d3
vin2a_d4
vin2a_d5
vin2a_d6
vin2a_d7
vin2a_d1
vin2a_d8
vin2a_d10
vin2a_d11
vin1a_hsync0
vin1a_vsync0
vin1a_fld0
vin1a_d0
vin1a_d2
vin1a_d3
vin1a_d4
vin1a_d5
vin1a_d6
vin1a_d7
vin1a_d1
vin1a_d8
vin1a_d10
vin1a_d11
gpio6_16
0
CFG_GPIO6_16_IN
mcasp1_aclkr
mcasp1_axr2
mcasp1_axr3
mcasp1_axr4
mcasp1_axr5
mcasp1_axr6
mcasp1_axr7
mcasp1_fsr
mcasp2_aclkr
mcasp2_axr0
mcasp2_axr1
200
900
200
240
840
240
240
240
240
240
240
0
CFG_MCASP1_ACLKR_IN
CFG_MCASP1_AXR2_IN
CFG_MCASP1_AXR3_IN
CFG_MCASP1_AXR4_IN
CFG_MCASP1_AXR5_IN
CFG_MCASP1_AXR6_IN
CFG_MCASP1_AXR7_IN
CFG_MCASP1_FSR_IN
CFG_MCASP2_ACLKR_IN
CFG_MCASP2_AXR0_IN
CFG_MCASP2_AXR1_IN
1180
600
700
920
0
800
0
0
0
400
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Timing Requirements and Switching Characteristics
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表 7-6. Manual Functions Mapping for VIP1 1A IOSET7 and 2A IOSET10 (continued)
BALL
BALL NAME
VIP_MANUAL1
VIP_MANUAL2
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
8
8(1)
D15
B16
B17
A17
A20
C18
G16
D17
A21
AA3
AB3
AA4
AB9
B26
C23
mcasp2_axr4
mcasp2_axr5
mcasp2_axr6
mcasp2_axr7
mcasp2_fsr
mcasp4_aclkx
mcasp4_axr0
mcasp4_axr1
mcasp4_fsx
mcasp5_aclkx
mcasp5_axr0
mcasp5_axr1
mcasp5_fsx
xref_clk2
2792
2621
1903
2928
2291
1433
2500
2379
1500
3740
3800
4099
3740
0
240
300
100
200
200
0
2750
2983
2086
2670
2654
1540
2560
2599
1900
3900
3800
3900
3860
0
400
0
CFG_MCASP2_AXR4_IN
CFG_MCASP2_AXR5_IN
CFG_MCASP2_AXR6_IN
CFG_MCASP2_AXR7_IN
CFG_MCASP2_FSR_IN
CFG_MCASP4_ACLKX_IN
CFG_MCASP4_AXR0_IN
CFG_MCASP4_AXR1_IN
CFG_MCASP4_FSX_IN
CFG_MCASP5_ACLKX_IN
CFG_MCASP5_AXR0_IN
CFG_MCASP5_AXR1_IN
CFG_MCASP5_FSX_IN
CFG_XREF_CLK2_IN
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
vin2a_d9
vin2a_d16
vin2a_d18
vin2a_d19
vin2a_d17
vin2a_d20
vin2a_d22
vin2a_d23
vin2a_d21
vin2a_clk0
vin2a_de0
vin1a_d12
vin1a_d13
vin1a_d14
vin1a_d15
vin1a_d9
0
700
0
0
vin1a_d16
vin1a_d18
vin1a_d19
vin1a_d17
vin1a_d20
vin1a_d22
vin1a_d23
vin1a_d21
vin1a_clk0
vin1a_de0
0
0
100
1400
1850
2760
2500
2100
0
0
1040
1700
2800
2870
2060
0
xref_clk3
1440
0
1623
0
CFG_XREF_CLK3_IN
(1) Some signals listed are manual functions that present alternate multiplexing options. These manual functions are controlled via CTRL_CORE_ALT_SELECT_MUX or
CTRL_CORE_VIP_MUX_SELECT registers. For more information on how to use these options, please refer to Device TRM, Chapter Control Module, Section Pad Configuration
Registers.
Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See 表 7-2 Modes Summary for a list of IO timings requiring the
use of Manual IO Timings Modes. See 表 7-7 Manual Functions Mapping for VIN2A (IOSET4/5/6) for a definition of the Manual modes.
表 7-7 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
表 7-7. Manual Functions Mapping for VIN2A (IOSET4/5/6)
BAL
L
BALL NAME
VIP_MANUAL3
VIP_MANUAL5
CFG REGISTER
MUXMODE
2
A_DELAY
G_DELAY
(ps)
A_DELAY
G_DELAY
(ps)
0
1
3
4
(ps)
(ps)
U3
RMII_MHZ_50
_CLK
2616
1379
2798
1294
CFG_RMII_MHZ_50_CLK_I
N
-
-
-
-
vin2a_d11
U4
V1
U5
V5
W2
mdio_d
2558
998
1105
463
2790
1029
2896
2844
2856
954
431
CFG_MDIO_D_IN
CFG_MDIO_MCLK_IN
CFG_RGMII0_RXC_IN
CFG_RGMII0_RXCTL_IN
CFG_RGMII0_RXD0_IN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
vin2a_d0
vin2a_clk0
vin2a_d5
vin2a_d6
vin2a_fld0
mdio_mclk
rgmii0_rxc
rgmii0_rxctl
rgmii0_rxd0
2658
2658
2638
862
651
1628
1123
1518
888
192
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表 7-7. Manual Functions Mapping for VIN2A (IOSET4/5/6) (continued)
BAL
L
BALL NAME
VIP_MANUAL3
VIP_MANUAL5
CFG REGISTER
MUXMODE
A_DELAY
G_DELAY
(ps)
A_DELAY
G_DELAY
(ps)
0
1
2
3
4
(ps)
2641
2641
2644
2638
2672
2604
2683
(ps)
2804
2801
2807
2835
2831
2764
2843
Y2
V3
V4
W9
V9
U6
V6
rgmii0_rxd1
rgmii0_rxd2
rgmii0_rxd3
rgmii0_txc
1737
1676
1828
1454
1663
1442
1598
1702
1652
1790
1396
1640
1417
1600
CFG_RGMII0_RXD1_IN
CFG_RGMII0_RXD2_IN
CFG_RGMII0_RXD3_IN
CFG_RGMII0_TXC_IN
CFG_RGMII0_TXCTL_IN
CFG_RGMII0_TXD0_IN
CFG_RGMII0_TXD1_IN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
vin2a_d9
vin2a_d8
vin2a_d7
vin2a_d3
vin2a_d4
vin2a_d10
rgmii0_txctl
rgmii0_txd0
rgmii0_txd1
vin2a_vsync
0
U7
rgmii0_txd2
2563
1483
2816
1344
CFG_RGMII0_TXD2_IN
-
-
-
-
vin2a_hsync
0
V7
V2
Y1
E1
F2
F3
D3
F6
D5
C2
C3
C4
B2
D6
C5
A3
D1
B3
B4
B5
A4
E2
rgmii0_txd3
uart3_rxd
uart3_txd
vin2a_clk0
vin2a_d0
2717
2445
2650
0
1461
1145
1197
0
2913
2743
2842
0
1310
923
1080
0
CFG_RGMII0_TXD3_IN
CFG_UART3_RXD_IN
CFG_UART3_TXD_IN
CFG_VIN2A_CLK0_IN
CFG_VIN2A_D0_IN
CFG_VIN2A_D1_IN
CFG_VIN2A_D10_IN
CFG_VIN2A_D11_IN
CFG_VIN2A_D12_IN
CFG_VIN2A_D13_IN
CFG_VIN2A_D14_IN
CFG_VIN2A_D15_IN
CFG_VIN2A_D16_IN
CFG_VIN2A_D17_IN
CFG_VIN2A_D18_IN
CFG_VIN2A_D19_IN
CFG_VIN2A_D2_IN
CFG_VIN2A_D20_IN
CFG_VIN2A_D21_IN
CFG_VIN2A_D22_IN
CFG_VIN2A_D23_IN
CFG_VIN2A_D3_IN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
vin2a_de0
-
-
vin2a_d1
-
-
vin2a_d2
vin2a_clk0
vin2a_d0
vin2a_d1
vin2a_d10
vin2a_d11
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
vin2a_d16
vin2a_d17
vin2a_d18
vin2a_d19
vin2a_d2
vin2a_d20
vin2a_d21
vin2a_d22
vin2a_d23
vin2a_d3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1812
1701
1720
1622
1350
1613
1149
1530
1512
1293
2140
2041
1675
1972
1957
2011
1962
1457
102
439
215
0
1936
2229
2031
1702
1819
1476
1701
2021
2044
1839
2494
1699
1736
2412
2391
2446
2395
1943
0
-
vin2a_d1
10
0
-
vin2a_d10
vin2a_d11
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
vin2a_d16
vin2a_d17
vin2a_d18
vin2a_d19
vin2a_d2
-
0
-
412
147
516
450
449
488
371
275
35
0
-
260
0
-
-
0
-
11
5
vin2b_d7
vin2b_d6
vin2b_d5
vin2b_d4
-
0
611
0
vin2a_d20
vin2a_d21
vin2a_d22
vin2a_d23
vin2a_d3
441
556
433
523
361
88
161
102
145
0
vin2b_d3
vin2b_d2
vin2b_d1
vin2b_d0
-
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表 7-7. Manual Functions Mapping for VIN2A (IOSET4/5/6) (continued)
BAL
L
BALL NAME
VIP_MANUAL3
VIP_MANUAL5
CFG REGISTER
MUXMODE
2
A_DELAY
G_DELAY
(ps)
A_DELAY
G_DELAY
(ps)
0
1
3
4
(ps)
1535
1676
1513
1616
1286
1544
1732
1461
1877
(ps)
1601
2052
1571
1855
1224
1373
1949
1983
1943
D2
F4
C1
E4
F5
E6
G2
H7
G1
vin2a_d4
vin2a_d5
0
0
0
CFG_VIN2A_D4_IN
CFG_VIN2A_D5_IN
CFG_VIN2A_D6_IN
CFG_VIN2A_D7_IN
CFG_VIN2A_D8_IN
CFG_VIN2A_D9_IN
CFG_VIN2A_DE0_IN
CFG_VIN2A_FLD0_IN
CFG_VIN2A_HSYNC0_IN
vin2a_d4
vin2a_d5
vin2a_d6
vin2a_d7
vin2a_d8
vin2a_d9
vin2a_de0
vin2a_fld0
-
-
-
-
-
-
-
-
-
-
-
-
271
0
-
-
-
vin2a_d6
0
-
-
-
vin2a_d7
141
437
265
208
562
0
0
-
-
-
vin2a_d8
618
509
0
-
-
-
vin2a_d9
-
-
-
vin2a_de0
vin2a_fld0
vin2a_hsync0
vin2a_fld0
vin2b_fld1
vin2b_clk1
-
vin2b_de1
-
151
0
-
-
vin2a_hsync
0
vin2b_hsync
1
G6
vin2a_vsync0
1566
0
1612
0
CFG_VIN2A_VSYNC0_IN
vin2a_vsync
0
-
-
vin2b_vsync
1
-
Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See 表 7-2 Modes Summary for a list of IO timings requiring the
use of Manual IO Timings Modes. See 表 7-8 Manual Functions Mapping for VIN2B (IOSET7/8/9) for a definition of the Manual modes.
表 7-8 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
表 7-8. Manual Functions Mapping for VIN2B (IOSET7/8/9)
BALL
BALL NAME
VIP_MANUAL4
VIP_MANUAL6
CFG REGISTER
MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps)
2
-
-
-
-
-
-
-
-
-
-
-
-
3
-
-
-
-
-
-
-
-
-
-
-
-
4
AC5
AB4
AD4
AC4
AC7
AC6
AC9
AC3
AC8
AD6
AB8
AB5
gpio6_10
gpio6_11
2829
2648
2794
2789
2689
2605
2616
2760
2757
2688
2638
995
884
1033
1074
1162
1180
1219
703
3009
2890
2997
2959
2897
2891
2947
2931
2979
2894
2894
1202
892
1096
1089
1210
1269
1219
590
CFG_GPIO6_10_IN
CFG_GPIO6_11_IN
vin2b_hsync1
vin2b_vsync1
vin2b_d7
vin2b_d6
vin2b_d5
vin2b_d4
vin2b_d3
vin2b_d2
vin2b_d1
vin2b_d0
vin2b_de1
vin2b_clk1
mmc3_clk
CFG_MMC3_CLK_IN
CFG_MMC3_CMD_IN
CFG_MMC3_DAT0_IN
CFG_MMC3_DAT1_IN
CFG_MMC3_DAT2_IN
CFG_MMC3_DAT3_IN
CFG_MMC3_DAT4_IN
CFG_MMC3_DAT5_IN
CFG_MMC3_DAT6_IN
CFG_MMC3_DAT7_IN
mmc3_cmd
mmc3_dat0
mmc3_dat1
mmc3_dat2
mmc3_dat3
mmc3_dat4
mmc3_dat5
mmc3_dat6
mmc3_dat7
1235
880
1342
891
1177
1165
182
1262
1187
107
194
Timing Requirements and Switching Characteristics
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表 7-8. Manual Functions Mapping for VIN2B (IOSET7/8/9) (continued)
BALL
BALL NAME
VIP_MANUAL4
VIP_MANUAL6
CFG REGISTER
MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps)
2
3
4
-
-
-
-
-
-
-
-
-
-
-
-
B2
D6
C5
A3
B3
B4
B5
A4
G2
H7
G1
G6
vin2a_d16
vin2a_d17
vin2a_d18
vin2a_d19
vin2a_d20
vin2a_d21
vin2a_d22
vin2a_d23
vin2a_de0
vin2a_fld0
vin2a_hsync0
vin2a_vsync0
1423
1253
2080
1849
1881
1917
1955
1899
1568
0
0
0
1739
1568
2217
2029
2202
2313
2334
2288
2048
0
0
0
0
0
0
0
0
0
0
0
0
0
CFG_VIN2A_D16_IN
CFG_VIN2A_D17_IN
CFG_VIN2A_D18_IN
CFG_VIN2A_D19_IN
CFG_VIN2A_D20_IN
CFG_VIN2A_D21_IN
CFG_VIN2A_D22_IN
CFG_VIN2A_D23_IN
CFG_VIN2A_DE0_IN
CFG_VIN2A_FLD0_IN
CFG_VIN2A_HSYNC0_IN
CFG_VIN2A_VSYNC0_IN
vin2b_d7
vin2b_d6
vin2b_d5
vin2b_d4
vin2b_d3
vin2b_d2
vin2b_d1
vin2b_d0
vin2b_fld1
vin2b_clk1
-
-
-
0
-
0
-
50
167
79
145
261
0
-
-
-
-
vin2b_de1
-
1793
1382
0
2011
1632
vin2b_hsync1
vin2b_vsync1
0
-
Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See 表 7-2 Modes Summary for a list of IO timings requiring the
use of Manual IO Timings Modes. See 表 7-9 Manual Functions Mapping for VIN1A (IOSET2/3/4) and VIN1B (IOSET4/7) and VIN2B (IOSET1/10)
for a definition of the Manual modes.
表 7-9 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
表 7-9. Manual Functions Mapping for VIN1A (IOSET2/3/4) and VIN1B (IOSET4/7) and VIN2B (IOSET1/10)
BA BALL NAME
LL
VIP_MANUAL7
VIP_MANUAL12
CFG REGISTER
MUXMODE
A_DELA G_DELA A_DELA G_DELA
2
3(1)
3(1)
4(1)
4(1)
5
-
-
-
-
-
-
6(1)
6(1)
Y (ps)
Y (ps)
Y (ps)
Y (ps)
R6
T9
N9
P9
K7
T6
gpmc_a0
gpmc_a1
gpmc_a10
gpmc_a11
gpmc_a19
gpmc_a2
3080
1792
3376
1632
CFG_GPMC_A0_IN
CFG_GPMC_A1_IN
CFG_GPMC_A10_IN
CFG_GPMC_A11_IN
CFG_GPMC_A19_IN
CFG_GPMC_A2_IN
vin1a_d1
6
-
-
-
-
-
-
-
-
-
-
-
-
vin2a_d0
vin2a_d1
-
-
-
-
vin1b_d0
vin1b_d1
-
2958
3073
3014
1385
3041
1890
1653
1784
0
3249
3388
3290
1246
3322
1749
1433
1693
0
vin1a_d1
7
-
vin1a_de
0
vin1b_clk
1
-
vin1a_fld
0
vin2a_fld vin1a_fld
vin1b_de
1
-
0
0
-
vin2a_d1
2
-
vin2b_d0
vin1b_d0
-
1960
1850
vin1a_d1
8
vin2a_d2
-
vin1b_d2
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表 7-9. Manual Functions Mapping for VIN1A (IOSET2/3/4) and VIN1B (IOSET4/7) and VIN2B (IOSET1/10) (continued)
BA BALL NAME
LL
VIP_MANUAL7
VIP_MANUAL12
CFG REGISTER
MUXMODE
A_DELA G_DELA A_DELA G_DELA
2
-
3(1)
3(1)
4(1)
4(1)
5
-
6(1)
6(1)
Y (ps)
Y (ps)
Y (ps)
Y (ps)
M7
J5
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a23
859
0
720
0
CFG_GPMC_A20_IN
CFG_GPMC_A21_IN
CFG_GPMC_A22_IN
CFG_GPMC_A23_IN
-
-
-
-
-
-
-
-
vin2a_d1
3
-
-
-
-
vin2b_d1
vin2b_d2
vin2b_d3
vin2b_d4
vin1b_d1
vin1b_d2
vin1b_d3
vin1b_d4
1465
1210
1111
0
0
0
1334
1064
954
0
0
0
-
vin2a_d1
4
-
K6
J7
-
vin2a_d1
5
-
-
vin2a_fld
0
-
J4
J6
gpmc_a24
gpmc_a25
gpmc_a26
gpmc_a27
1137
1402
1298
934
0
0
0
0
1051
1283
1153
870
0
0
0
0
CFG_GPMC_A24_IN
CFG_GPMC_A25_IN
CFG_GPMC_A26_IN
CFG_GPMC_A27_IN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
vin2b_d5
vin2b_d6
vin2b_d7
vin1b_d5
vin1b_d6
vin1b_d7
H4
H5
vin2b_hsy vin1b_hsyn
nc1
c1
T7
P6
R9
R5
P5
N7
R4
gpmc_a3
gpmc_a4
gpmc_a5
gpmc_a6
gpmc_a7
gpmc_a8
gpmc_a9
3019
3063
3021
3062
3260
3033
2991
2145
1981
1954
1716
1889
1702
1905
3296
3357
3304
3348
3583
3328
3281
2050
1829
1840
1592
1631
1547
1766
CFG_GPMC_A3_IN
CFG_GPMC_A4_IN
CFG_GPMC_A5_IN
CFG_GPMC_A6_IN
CFG_GPMC_A7_IN
CFG_GPMC_A8_IN
CFG_GPMC_A9_IN
vin1a_d1
9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
vin2a_d3
vin2a_d4
vin2a_d5
vin2a_d6
vin2a_d7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
vin1b_d3
-
vin1a_d2
0
vin1b_d4
vin1b_d5
vin1b_d6
vin1b_d7
-
-
-
-
-
-
vin1a_d2
1
vin1a_d2
2
vin1a_d2
3
vin1a_hsy
nc0
vin1b_hsy
nc1
vin1a_vsy
nc0
-
vin1b_vsy
nc1
M6
M2
J1
gpmc_ad0
gpmc_ad1
gpmc_ad10
2907
2858
2920
1342
1321
1384
3181
3132
3223
1255
1234
1204
CFG_GPMC_AD0_IN vin1a_d0
CFG_GPMC_AD1_IN vin1a_d1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CFG_GPMC_AD10_IN vin1a_d1
0
J2
H1
J3
gpmc_ad11
gpmc_ad12
gpmc_ad13
2719
2845
2765
1310
1135
1225
3019
3160
3045
1198
917
CFG_GPMC_AD11_IN vin1a_d1
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CFG_GPMC_AD12_IN vin1a_d1
2
1119
CFG_GPMC_AD13_IN vin1a_d1
3
196
Timing Requirements and Switching Characteristics
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
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ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
表 7-9. Manual Functions Mapping for VIN1A (IOSET2/3/4) and VIN1B (IOSET4/7) and VIN2B (IOSET1/10) (continued)
BA BALL NAME
LL
VIP_MANUAL7
VIP_MANUAL12
CFG REGISTER
MUXMODE
4(1) 4(1)
A_DELA G_DELA A_DELA G_DELA
2
3(1)
3(1)
5
-
6(1)
6(1)
Y (ps)
Y (ps)
Y (ps)
Y (ps)
H2
H3
gpmc_ad14
gpmc_ad15
2845
1150
3153
952
CFG_GPMC_AD14_IN vin1a_d1
4
-
-
-
-
-
-
-
-
-
-
-
-
2766
1453
3044
1355
CFG_GPMC_AD15_IN vin1a_d1
5
-
L5
M1
L6
L4
L3
L2
L1
K2
N6
gpmc_ad2
gpmc_ad3
gpmc_ad4
gpmc_ad5
gpmc_ad6
gpmc_ad7
gpmc_ad8
gpmc_ad9
gpmc_ben0
2951
2825
2927
2923
2958
2900
2845
2779
1555
1296
1154
1245
1251
1342
1244
1585
1343
0
3226
3121
3246
3217
3238
3174
3125
3086
1425
1209
997
CFG_GPMC_AD2_IN vin1a_d2
CFG_GPMC_AD3_IN vin1a_d3
CFG_GPMC_AD4_IN vin1a_d4
CFG_GPMC_AD5_IN vin1a_d5
CFG_GPMC_AD6_IN vin1a_d6
CFG_GPMC_AD7_IN vin1a_d7
CFG_GPMC_AD8_IN vin1a_d8
CFG_GPMC_AD9_IN vin1a_d9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1014
1098
1239
1157
1482
1223
0
CFG_GPMC_BEN0_IN
CFG_GPMC_BEN1_IN
CFG_GPMC_CLK_IN
CFG_GPMC_CS1_IN
-
-
-
-
vin2b_de vin1b_de1
1
M4
P7
gpmc_ben1
gpmc_clk
gpmc_cs1
gpmc_cs3
vout1_clk
vout1_d0
vout1_d1
vout1_d10
vout1_d11
vout1_d12
vout1_d13
1501
0
0
0
1397
0
0
-
-
-
-
-
-
-
-
vin2b_clk
1
-
-
-
-
-
-
-
-
-
-
-
-
vin2b_fld vin1b_fld1
1
0
vin2a_hsy
nc0
vin2a_de vin2b_clk vin1b_clk1
0
1
H6
1192
1324
1648
2197
2221
1800
1656
1719
1757
0
1102
1466
1762
2734
2750
1910
1780
1866
1851
0
vin2a_de
0
-
vin2b_vsy vin1b_vsyn
nc1
c1
P1
374
885
565
576
863
931
1086
928
353
928
215
230
916
945
1041
1022
CFG_GPMC_CS3_IN vin1a_clk
0
-
-
-
-
-
-
-
-
-
-
-
D11
F11
G10
D7
CFG_VOUT1_CLK_IN
CFG_VOUT1_D0_IN
CFG_VOUT1_D1_IN
CFG_VOUT1_D10_IN
CFG_VOUT1_D11_IN
CFG_VOUT1_D12_IN
CFG_VOUT1_D13_IN
-
-
-
-
-
-
-
vin2a_fld vin1a_fld vin1a_fld
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
vin2a_d1 vin1a_d1 vin1a_d1
6
6
6
vin2a_d1 vin1a_d1 vin1a_d1
7
7
7
vin2a_d1 vin1a_d1 vin1a_d1
0
0
0
D8
vin2a_d1 vin1a_d1 vin1a_d1
1
1
1
A5
vin2a_d1 vin1a_d1 vin1a_d1
2
2
2
C6
vin2a_d1 vin1a_d1 vin1a_d1
3
3
3
版权 © 2016–2018, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics
197
TDA2E
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www.ti.com.cn
表 7-9. Manual Functions Mapping for VIN1A (IOSET2/3/4) and VIN1B (IOSET4/7) and VIN2B (IOSET1/10) (continued)
BA BALL NAME
LL
VIP_MANUAL7
VIP_MANUAL12
CFG REGISTER
MUXMODE
A_DELA G_DELA A_DELA G_DELA
2
-
3(1)
3(1)
4(1)
4(1)
5
-
6(1)
6(1)
Y (ps)
Y (ps)
Y (ps)
Y (ps)
C8
C7
vout1_d14
vout1_d15
2279
345
2788
0
CFG_VOUT1_D14_IN
CFG_VOUT1_D15_IN
vin2a_d1 vin1a_d1 vin1a_d1
-
-
-
-
-
-
4
4
4
1810
874
2786
69
-
vin2a_d1 vin1a_d1 vin1a_d1
-
5
5
5
B7
B8
vout1_d16
vout1_d17
vout1_d18
vout1_d19
vout1_d2
1763
1695
1777
2047
1809
774
788
590
22
1880
1805
1871
2196
2759
807
838
684
0
CFG_VOUT1_D16_IN
CFG_VOUT1_D17_IN
CFG_VOUT1_D18_IN
CFG_VOUT1_D19_IN
CFG_VOUT1_D2_IN
-
-
-
-
-
vin2a_d0 vin1a_d0 vin1a_d0
vin2a_d1 vin1a_d1 vin1a_d1
vin2a_d2 vin1a_d2 vin1a_d2
vin2a_d3 vin1a_d3 vin1a_d3
vin2a_d1 vin1a_d1 vin1a_d1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A7
A8
F10
941
178
8
8
8
C9
A9
vout1_d20
vout1_d21
vout1_d22
vout1_d23
vout1_d3
1676
1712
1698
1627
2427
944
688
557
1035
429
1795
1848
2443
1726
2853
973
670
0
CFG_VOUT1_D20_IN
CFG_VOUT1_D21_IN
CFG_VOUT1_D22_IN
CFG_VOUT1_D23_IN
CFG_VOUT1_D3_IN
-
-
-
-
-
vin2a_d4 vin1a_d4 vin1a_d4
vin2a_d5 vin1a_d5 vin1a_d5
vin2a_d6 vin1a_d6 vin1a_d6
vin2a_d7 vin1a_d7 vin1a_d7
vin2a_d1 vin1a_d1 vin1a_d1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B9
A10
G11
1116
167
9
9
9
E9
F9
F8
E7
vout1_d4
vout1_d5
vout1_d6
vout1_d7
2351
1634
1776
2272
412
983
880
351
2845
1729
2736
2757
85
1076
107
53
CFG_VOUT1_D4_IN
CFG_VOUT1_D5_IN
CFG_VOUT1_D6_IN
CFG_VOUT1_D7_IN
-
-
-
-
vin2a_d2 vin1a_d2 vin1a_d2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
vin2a_d2 vin1a_d2 vin1a_d2
1
1
1
vin2a_d2 vin1a_d2 vin1a_d2
2
2
2
vin2a_d2 vin1a_d2 vin1a_d2
3
3
3
E8
D9
vout1_d8
vout1_d9
vout1_de
1724
2281
1734
898
566
749
1819
2804
1828
990
195
842
CFG_VOUT1_D8_IN
CFG_VOUT1_D9_IN
CFG_VOUT1_DE_IN
-
-
-
vin2a_d8 vin1a_d8 vin1a_d8
vin2a_d9 vin1a_d9 vin1a_d9
vin2a_de vin1a_de vin1a_de
-
-
-
-
-
-
-
-
-
-
-
-
B10
0
0
0
B11
vout1_fld
0
0
606
0
0
0
0
0
CFG_VOUT1_FLD_IN
-
-
-
vin2a_clk vin1a_clk vin1a_clk
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
C11 vout1_hsync
E11 vout1_vsync
1634
1887
2399
2068
CFG_VOUT1_HSYNC_
IN
vin2a_hsy vin1a_hsy vin1a_hsy
nc0 nc0 nc0
CFG_VOUT1_VSYNC_
IN
vin2a_vsy vin1a_vsy vin1a_vsy
nc0 nc0 nc0
198
Timing Requirements and Switching Characteristics
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E
www.ti.com.cn
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
(1) Some signals listed are manual functions that present alternate multiplexing options. These manual functions are controlled via CTRL_CORE_ALT_SELECT_MUX or
CTRL_CORE_VIP_MUX_SELECT registers. For more information on how to use these options, please refer to Device TRM, Chapter Control Module, Section Pad Configuration
Registers.
Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See 表 7-2 Modes Summary for a list of IO timings requiring the
use of Manual IO Timings Modes. See 表 7-10 Manual Functions Mapping for VIN1A (IOSET5/6) and VIN2A (IOSET7/8/9) for a definition of the
Manual modes.
表 7-10 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
表 7-10. Manual Functions Mapping for VIN1A (IOSET5/6) and VIN2A (IOSET7/8/9)
BAL
L
BALL NAME
VIP_MANUAL8
VIP_MANUAL13
CFG REGISTER
MUXMODE
4(1)
A_DELAY
G_DELAY
(ps)
A_DELAY
G_DELAY
(ps)
3
4(1)
5(1)
5(1)
(ps)
1891
1713
1797
0
(ps)
2176
2109
2036
0
R6
T9
P9
P4
R3
gpmc_a0
gpmc_a1
gpmc_a11
gpmc_a12
gpmc_a13
427
513
317
0
0
0
0
0
0
CFG_GPMC_A0_IN
CFG_GPMC_A1_IN
CFG_GPMC_A11_IN
CFG_GPMC_A12_IN
CFG_GPMC_A13_IN
-
-
-
-
-
vin2a_d0
vin2a_d1
vin2a_fld0
vin2a_clk0
vin1a_d0
vin1a_d1
vin1a_fld0
vin1a_clk0
-
-
-
-
-
-
-
-
-
-
1876
391
2144
vin2a_hsync vin1a_hsync
0
0
T2
gpmc_a14
1720
756
2384
38
CFG_GPMC_A14_IN
-
vin2a_vsync vin1a_vsync
-
-
0
0
U2
U1
P3
R2
K7
T6
M7
J5
gpmc_a15
gpmc_a16
gpmc_a17
gpmc_a18
gpmc_a19
gpmc_a2
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a3
gpmc_a4
gpmc_a5
gpmc_a6
gpmc_a7
1502
1651
1642
1612
1463
1789
1124
1491
1218
1216
1789
1842
1778
1783
2207
1755
368
355
338
0
1804
1902
1862
1406
1418
2310
933
0
0
0
0
0
0
0
0
0
0
8
0
0
0
0
0
CFG_GPMC_A15_IN
CFG_GPMC_A16_IN
CFG_GPMC_A17_IN
CFG_GPMC_A18_IN
CFG_GPMC_A19_IN
CFG_GPMC_A2_IN
CFG_GPMC_A20_IN
CFG_GPMC_A21_IN
CFG_GPMC_A22_IN
CFG_GPMC_A23_IN
CFG_GPMC_A3_IN
CFG_GPMC_A4_IN
CFG_GPMC_A5_IN
CFG_GPMC_A6_IN
CFG_GPMC_A7_IN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
vin2a_d8
vin2a_d9
vin2a_d10
vin2a_d11
vin2a_d12
vin2a_d2
vin2a_d13
vin2a_d14
vin2a_d15
vin2a_fld0
vin2a_d3
vin2a_d4
vin2a_d5
vin2a_d6
vin2a_d7
vin1a_d8
vin1a_d9
vin1a_d10
vin1a_d11
vin1a_d12
vin1a_d2
vin1a_d13
vin1a_d14
vin1a_d15
vin1a_fld0
vin1a_d3
vin1a_d4
vin1a_d5
vin1a_d6
vin1a_d7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
152
646
0
206
245
0
1483
1254
1021
2451
2329
2215
2088
2393
1745
K6
J7
T7
P6
R9
R5
P5
N1
766
646
556
443
370
116
gpmc_advn_al
e
CFG_GPMC_ADVN_ALE_I
N
vin2a_vsync vin1a_vsync
0
0
版权 © 2016–2018, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics
199
TDA2E
ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
www.ti.com.cn
表 7-10. Manual Functions Mapping for VIN1A (IOSET5/6) and VIN2A (IOSET7/8/9) (continued)
BAL
L
BALL NAME
VIP_MANUAL8
VIP_MANUAL13
CFG REGISTER
MUXMODE
4(1)
A_DELAY
G_DELAY
(ps)
A_DELAY
G_DELAY
(ps)
3
4(1)
5(1)
5(1)
(ps)
(ps)
P7
gpmc_clk
1896
351
2152
0
CFG_GPMC_CLK_IN
-
vin2a_hsync vin1a_hsync
vin2a_de0
vin1a_de0
0
0
H6
D11
F11
G10
D7
gpmc_cs1
vout1_clk
vout1_d0
vout1_d1
vout1_d10
vout1_d11
vout1_d12
vout1_d13
vout1_d14
vout1_d15
vout1_d16
vout1_d17
vout1_d18
vout1_d19
vout1_d2
vout1_d20
vout1_d21
vout1_d22
vout1_d23
vout1_d3
vout1_d4
vout1_d5
vout1_d6
vout1_d7
vout1_d8
vout1_d9
vout1_de
vout1_fld
1337
1939
2140
2104
2139
1944
1966
2048
2222
2072
2044
1971
2104
1888
2170
1942
1997
1949
1871
2319
2300
1923
2148
2212
1962
2312
1973
0
74
1288
2486
2617
2620
2675
2569
2646
2624
2700
2664
2634
2433
2440
2105
2624
2579
2324
2165
2522
2740
2739
2527
2622
2653
2573
2725
2551
0
0
0
CFG_GPMC_CS1_IN
CFG_VOUT1_CLK_IN
CFG_VOUT1_D0_IN
CFG_VOUT1_D1_IN
CFG_VOUT1_D10_IN
CFG_VOUT1_D11_IN
CFG_VOUT1_D12_IN
CFG_VOUT1_D13_IN
CFG_VOUT1_D14_IN
CFG_VOUT1_D15_IN
CFG_VOUT1_D16_IN
CFG_VOUT1_D17_IN
CFG_VOUT1_D18_IN
CFG_VOUT1_D19_IN
CFG_VOUT1_D2_IN
CFG_VOUT1_D20_IN
CFG_VOUT1_D21_IN
CFG_VOUT1_D22_IN
CFG_VOUT1_D23_IN
CFG_VOUT1_D3_IN
CFG_VOUT1_D4_IN
CFG_VOUT1_D5_IN
CFG_VOUT1_D6_IN
CFG_VOUT1_D7_IN
CFG_VOUT1_D8_IN
CFG_VOUT1_D9_IN
CFG_VOUT1_DE_IN
CFG_VOUT1_FLD_IN
CFG_VOUT1_HSYNC_IN
-
vin2a_de0
vin1a_de0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
332
647
615
406
534
659
447
548
443
455
246
120
0
vin2a_fld0
vin2a_d16
vin2a_d17
vin2a_d10
vin2a_d11
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
vin2a_d0
vin2a_d1
vin2a_d2
vin2a_d3
vin2a_d18
vin2a_d4
vin2a_d5
vin2a_d6
vin2a_d7
vin2a_d19
vin2a_d20
vin2a_d21
vin2a_d22
vin2a_d23
vin2a_d8
vin2a_d9
vin2a_de0
vin2a_clk0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
386
314
85
125
154
87
286
67
82
0
D8
A5
C6
C8
C7
B7
B8
A7
0
A8
0
F10
C9
237
512
141
0
0
91
0
A9
B9
0
A10
G11
E9
704
417
369
579
396
335
573
335
414
0
269
191
137
191
138
110
178
138
52
0
F9
F8
E7
E8
D9
B10
B11
C11
vout1_hsync
1813
261
2277
0
vin2a_hsync
0
200
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表 7-10. Manual Functions Mapping for VIN1A (IOSET5/6) and VIN2A (IOSET7/8/9) (continued)
BAL
L
BALL NAME
VIP_MANUAL8
VIP_MANUAL13
CFG REGISTER
MUXMODE
4(1)
A_DELAY
G_DELAY
(ps)
A_DELAY
G_DELAY
(ps)
3
4(1)
5(1)
5(1)
(ps)
(ps)
E11
vout1_vsync
1665
0
1881
0
CFG_VOUT1_VSYNC_IN
vin2a_vsync
0
-
-
-
-
(1) Some signals listed are manual functions that present alternate multiplexing options. These manual functions are controlled via CTRL_CORE_ALT_SELECT_MUX or
CTRL_CORE_VIP_MUX_SELECT registers. For more information on how to use these options, please refer to Device TRM, Chapter Control Module, Section Pad Configuration
Registers.
Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See 表 7-2 Modes Summary for a list of IO timings requiring the
use of Manual IO Timings Modes. See 表 7-11 Manual Functions Mapping for VIN1B (IOSET6/7) for a definition of the Manual modes.
表 7-11 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
表 7-11. Manual Functions Mapping for VIN1B (IOSET6/7)
BALL
BALL NAME
VIP_MANUAL9
VIP_MANUAL14
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
702
A_DELAY (ps)
G_DELAY (ps)
441
5
6
R6
T9
N9
P9
P4
T6
T7
P6
R9
R5
P5
N7
R4
U4
V1
U5
V5
W2
V4
W9
gpmc_a0
gpmc_a1
gpmc_a10
gpmc_a11
gpmc_a12
gpmc_a2
gpmc_a3
gpmc_a4
gpmc_a5
gpmc_a6
gpmc_a7
gpmc_a8
gpmc_a9
mdio_d
1873
1629
0
2202
2057
0
CFG_GPMC_A0_IN
CFG_GPMC_A1_IN
CFG_GPMC_A10_IN
CFG_GPMC_A11_IN
CFG_GPMC_A12_IN
CFG_GPMC_A2_IN
CFG_GPMC_A3_IN
CFG_GPMC_A4_IN
CFG_GPMC_A5_IN
CFG_GPMC_A6_IN
CFG_GPMC_A7_IN
CFG_GPMC_A8_IN
CFG_GPMC_A9_IN
CFG_MDIO_D_IN
-
vin1b_d0
772
413
-
vin1b_d1
0
0
-
vin1b_clk1
1851
2009
1734
1757
1794
1726
1792
2117
1758
1705
1945
255
1011
601
2126
2289
2131
2106
2164
2120
2153
2389
2140
2067
2265
337
856
-
vin1b_de1
327
-
vin1b_fld1
898
573
-
vin1b_d2
1076
893
812
-
vin1b_d3
559
-
vin1b_d4
853
523
-
vin1b_d5
612
338
-
vin1b_d6
610
304
-
vin1b_d7
653
308
-
vin1b_hsync1
899
646
-
vin1b_vsync1
671
414
vin1b_d0
vin1b_clk1
vin1b_d5
vin1b_d6
vin1b_fld1
vin1b_d7
vin1b_d3
-
-
-
-
-
-
-
mdio_mclk
rgmii0_rxc
rgmii0_rxctl
rgmii0_rxd0
rgmii0_rxd3
rgmii0_txc
119
0
CFG_MDIO_MCLK_IN
CFG_RGMII0_RXC_IN
CFG_RGMII0_RXCTL_IN
CFG_RGMII0_RXD0_IN
CFG_RGMII0_RXD3_IN
CFG_RGMII0_TXC_IN
2057
2121
2070
2092
2088
909
2341
2323
2336
2306
2328
646
1139
655
988
340
1357
1205
1216
1079
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表 7-11. Manual Functions Mapping for VIN1B (IOSET6/7) (continued)
BALL
BALL NAME
VIP_MANUAL9
VIP_MANUAL14
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
5
6
-
-
-
-
-
-
V9
V6
U7
V7
V2
Y1
rgmii0_txctl
rgmii0_txd1
rgmii0_txd2
rgmii0_txd3
uart3_rxd
2143
2078
1928
2255
1829
2030
1383
1189
1125
971
2312
2324
2306
2401
2220
2324
1311
1065
763
CFG_RGMII0_TXCTL_IN
CFG_RGMII0_TXD1_IN
CFG_RGMII0_TXD2_IN
CFG_RGMII0_TXD3_IN
CFG_UART3_RXD_IN
CFG_UART3_TXD_IN
vin1b_d4
vin1b_vsync1
vin1b_hsync1
vin1b_de1
vin1b_d1
846
747
400
uart3_txd
837
568
vin1b_d2
Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See 表 7-2 Modes Summary for a list of IO timings requiring the
use of Manual IO Timings Modes. See 表 7-12 Manual Functions Mapping for VIN1B (IOSET5) and VIN2B (IOSET2/11) for a definition of the
Manual modes.
表 7-12 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
表 7-12. Manual Functions Mapping for VIN1B (IOSET5) and VIN2B (IOSET2/11)
BALL
BALL NAME
VIP_MANUAL10
VIP_MANUAL11
CFG REGISTER
MUXMODE
4(1)
A_DELAY
G_DELAY
(ps)
A_DELAY
G_DELAY
(ps)
4(1)
6(1)
6(1)
(ps)
1600
1440
1602
1395
1571
1463
1426
1362
1283
1978
0
(ps)
2023
1875
2021
1822
2045
1893
1842
1797
1760
2327
0
K7
M7
J5
gpmc_a19
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
gpmc_a25
gpmc_a26
gpmc_a27
gpmc_ben0
gpmc_ben1
gpmc_cs1
943
621
1066
983
716
832
1166
1094
809
780
0
477
136
604
519
200
396
732
584
338
389
0
CFG_GPMC_A19_IN
CFG_GPMC_A20_IN
CFG_GPMC_A21_IN
CFG_GPMC_A22_IN
CFG_GPMC_A23_IN
CFG_GPMC_A24_IN
CFG_GPMC_A25_IN
CFG_GPMC_A26_IN
CFG_GPMC_A27_IN
CFG_GPMC_BEN0_IN
CFG_GPMC_BEN1_IN
CFG_GPMC_CS1_IN
-
-
vin2b_d0
vin2b_d1
vin2b_d2
vin2b_d3
vin2b_d4
vin2b_d5
vin2b_d6
vin2b_d7
vin1b_d0
vin1b_d1
vin1b_d2
vin1b_d3
vin1b_d4
vin1b_d5
vin1b_d6
vin1b_d7
-
-
-
-
K6
J7
-
-
-
-
J4
-
-
J6
-
-
H4
H5
N6
M4
H6
-
-
-
-
vin2b_hsync1 vin1b_hsync1
-
-
vin2b_de1
vin2b_fld1
vin1b_de1
vin1b_fld1
vin2b_clk1
-
vin1b_clk1
-
1411
982
1857
536
vin2b_vsync1 vin1b_vsync1
(1) Some signals listed are manual functions that present alternate multiplexing options. These manual functions are controlled via CTRL_CORE_ALT_SELECT_MUX or
CTRL_CORE_VIP_MUX_SELECT registers. For more information on how to use these options, please refer to Device TRM, Chapter Control Module, Section Pad Configuration
Registers.
Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See 表 7-2 Modes Summary for a list of IO timings requiring the
use of Manual IO Timings Modes. See 表 7-13 Manual Functions Mapping for VIN1A (IOSET8/9/10) for a definition of the Manual modes.
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表 7-13 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
表 7-13. Manual Functions Mapping for VIN1A (IOSET8/9/10)
BALL
BALL NAME
VIP_MANUAL15
VIP_MANUAL16
CFG REGISTER
MUXMODE
A_DELAY (ps)
2131
3720
2447
3061
3113
2803
3292
2854
2813
2471
2815
2965
3082
2898
2413
2478
2806
2861
1583
2873
1625
2792
1547
2362
2326
924
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
2180
2448
0
7
-
9
AC5
AB4
C14
G12
F12
B13
A12
E14
A13
G14
F14
B12
A11
D14
A19
C15
A16
A18
B18
B19
C17
F15
C18
G16
D17
A21
AA3
AB3
AA4
AB9
gpio6_10
2198
2170
4106
3042
3380
3396
3362
3357
3145
3229
3053
3225
3427
3253
3368
2972
3062
3175
2936
1878
3109
2072
3146
1776
2815
2769
1338
4130
4159
4179
4074
CFG_GPIO6_10_IN
CFG_GPIO6_11_IN
vin1a_clk0
gpio6_11
2732
-
vin1a_de0
mcasp1_aclkx
mcasp1_axr0
mcasp1_axr1
mcasp1_axr10
mcasp1_axr11
mcasp1_axr12
mcasp1_axr13
mcasp1_axr14
mcasp1_axr15
mcasp1_axr8
mcasp1_axr9
mcasp1_fsx
0
0
CFG_MCASP1_ACLKX_IN
CFG_MCASP1_AXR0_IN
CFG_MCASP1_AXR1_IN
CFG_MCASP1_AXR10_IN
CFG_MCASP1_AXR11_IN
CFG_MCASP1_AXR12_IN
CFG_MCASP1_AXR13_IN
CFG_MCASP1_AXR14_IN
CFG_MCASP1_AXR15_IN
CFG_MCASP1_AXR8_IN
CFG_MCASP1_AXR9_IN
CFG_MCASP1_FSX_IN
CFG_MCASP2_ACLKX_IN
CFG_MCASP2_AXR2_IN
CFG_MCASP2_AXR3_IN
CFG_MCASP2_FSX_IN
CFG_MCASP3_ACLKX_IN
CFG_MCASP3_AXR0_IN
CFG_MCASP3_AXR1_IN
CFG_MCASP3_FSX_IN
CFG_MCASP4_ACLKX_IN
CFG_MCASP4_AXR0_IN
CFG_MCASP4_AXR1_IN
CFG_MCASP4_FSX_IN
CFG_MCASP5_ACLKX_IN
CFG_MCASP5_AXR0_IN
CFG_MCASP5_AXR1_IN
CFG_MCASP5_FSX_IN
vin1a_fld0
vin1a_vsync0
vin1a_hsync0
vin1a_d13
vin1a_d12
vin1a_d11
vin1a_d10
vin1a_d9
vin1a_d8
vin1a_d15
vin1a_d14
vin1a_de0
vin1a_d7
vin1a_d5
vin1a_d4
vin1a_d6
vin1a_d3
vin1a_d1
vin1a_d0
vin1a_d2
-
-
292
304
0
-
0
-
0
-
0
546
320
196
0
-
0
-
0
-
0
-
0
201
83
-
0
-
0
440
139
0
-
0
-
mcasp2_aclkx
mcasp2_axr2
mcasp2_axr3
mcasp2_fsx
0
-
0
0
-
0
242
599
0
-
78
0
-
mcasp3_aclkx
mcasp3_axr0
mcasp3_axr1
mcasp3_fsx
-
0
375
1023
257
0
-
1400
0
vin1a_fld0
-
mcasp4_aclkx
mcasp4_axr0
mcasp4_axr1
mcasp4_fsx
268
587
667
2573
2106
3013
2951
2447
vin1a_d15
vin1a_d13
vin1a_d12
vin1a_d14
vin1a_d11
vin1a_d9
vin1a_d8
vin1a_d10
193
304
2219
1708
2776
2733
2142
-
-
-
mcasp5_aclkx
mcasp5_axr0
mcasp5_axr1
mcasp5_fsx
3731
3800
3828
3675
-
-
-
-
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表 7-13. Manual Functions Mapping for VIN1A (IOSET8/9/10) (continued)
BALL
BALL NAME
VIP_MANUAL15
A_DELAY (ps)
VIP_MANUAL16
A_DELAY (ps)
CFG REGISTER
MUXMODE
G_DELAY (ps)
2744
2768
2765
2961
2447
2903
2622
2824
2818
2481
0
G_DELAY (ps)
2450
2470
2522
2667
2096
2672
2342
2595
2491
2161
0
7
9
AD4
AC4
AC7
AC6
AC9
AC3
AC8
AD6
AB8
AB5
D18
E17
mmc3_clk
mmc3_cmd
mmc3_dat0
mmc3_dat1
mmc3_dat2
mmc3_dat3
mmc3_dat4
mmc3_dat5
mmc3_dat6
mmc3_dat7
xref_clk0
3907
3892
3786
3673
3818
3902
3905
3807
3724
3775
1971
0
4260
4242
4156
4053
4209
4259
4259
4167
4123
4159
2472
0
CFG_MMC3_CLK_IN
CFG_MMC3_CMD_IN
CFG_MMC3_DAT0_IN
CFG_MMC3_DAT1_IN
CFG_MMC3_DAT2_IN
CFG_MMC3_DAT3_IN
CFG_MMC3_DAT4_IN
CFG_MMC3_DAT5_IN
CFG_MMC3_DAT6_IN
CFG_MMC3_DAT7_IN
CFG_XREF_CLK0_IN
CFG_XREF_CLK1_IN
-
vin1a_d7
vin1a_d6
vin1a_d5
vin1a_d4
vin1a_d3
vin1a_d2
vin1a_d1
vin1a_d0
vin1a_hsync0
vin1a_vsync0
-
-
-
-
-
-
-
-
-
-
vin1a_d0
vin1a_clk0
xref_clk1
192
603
-
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7.7 Display Subsystem - Video Output Ports
Three Display Parallel Interfaces (DPI) channels are available in DSS named DPI Video Output 1, DPI
Video Output 2 and DPI Video Output 3.
注
The DPI Video Output i (i = 1 to 3) interface is also referred to as VOUTi.
Every VOUT interface consists of:
•
•
•
•
•
•
24-bit data bus (data[23:0])
Horizontal synchronization signal (HSYNC)
Vertical synchronization signal (VSYNC)
Data enable (DE)
Field ID (FID)
Pixel clock (CLK)
注
For more information, see the Display Subsystem chapter of the Device TRM.
CAUTION
The I/O Timings provided in this section are valid only if signals within a single
IOSET are used. The IOSETs are defined in 表 7-18 .
CAUTION
The I/O Timings provided in this section are valid only for some DSS usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
CAUTION
All pads/balls configured as vouti_* signals must be programmed to use slow
slew rate by setting the corresponding CTRL_CORE_PAD_*[SLEWCONTROL]
register field to SLOW (0b1).
表 7-14 through 表 7-17, and 图 7-6 assume testing over the recommended operating conditions and
electrical characteristic conditions.
表 7-14. DPI Video Output i (i = 1..3) Default Switching Characteristics
PARAMETE
NO.
DESCRIPTION
MODE
MIN
MAX
UNIT
R
D1
tc(clk)
Cycle time, output pixel clock vouti_clk
DPI1/2/3 in 1.8V mode 11.76(3)
DPI2 in 3.3V mode
ns
DPI1/3 in 3.3V mode
13.33(3)
ns
ns
D2
D3
tw(clkL)
tw(clkH)
Pulse duration, output pixel clock vouti_clk low
Pulse duration, output pixel clock vouti_clk high
P*0.5-1
(1)
P*0.5-1
(1)
ns
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表 7-14. DPI Video Output i (i = 1..3) Default Switching Characteristics (continued)
PARAMETE
R
NO.
DESCRIPTION
MODE
MIN
MAX
UNIT
D5
td(clk-ctlV)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI1
DPI1
-2.5
2.5
2.5
ns
D6
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
-2.5
ns
D5
D6
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI2 (vin2a_fld0 clock
reference)
-2.5
-2.5
2.5
2.5
ns
ns
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
DPI2 (vin2a_fld0 clock
reference)
D5
D6
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI2 (xref_clk2 clock
reference)
-2.5
-2.5
2.5
2.5
ns
ns
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
DPI2 (xref_clk2 clock
reference)
D5
D6
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI3
DPI3
-2.5
-2.5
2.5
2.5
ns
ns
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
(1) P = output vouti_clk period in ns.
(2) All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding
CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
(3) SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note SPRAC62 for additional guidance.
表 7-15. DPI Video Output i (i = 1..3) Alternate Switching Characteristics(2)
PARAMETE
NO.
DESCRIPTION
MODE
MIN
MAX
UNIT
R
D1
tc(clk)
Cycle time, output pixel clock vouti_clk
DPI1/2/3 in 1.8V mode
DPI2 in 3.3V mode
6.06(3)
ns
DPI1/3 in 3.3V mode
13.33(3)
ns
ns
D2
D3
D5
D6
tw(clkL)
tw(clkH)
td(clk-ctlV)
td(clk-dV)
Pulse duration, output pixel clock vouti_clk low
Pulse duration, output pixel clock vouti_clk high
P*0.5-1
(1)
P*0.5-1
ns
ns
ns
(1)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI1
DPI1
1.51
1.51
4.55
4.55
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
D5
D6
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI2 (vin2a_fld0 clock
reference)
1.51
1.51
4.55
4.55
ns
ns
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
DPI2 (vin2a_fld0 clock
reference)
D5
D6
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI2 (xref_clk2 clock
reference)
1.51
1.51
4.55
4.55
ns
ns
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
DPI2 (xref_clk2 clock
reference)
D5
D6
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI3
DPI3
1.51
1.51
4.55
4.55
ns
ns
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
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(1) P = output vouti_clk period in ns.
(2) All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding
CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
(3) SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note SPRAC62 for additional guidance.
表 7-16. DPI Video Output i (i = 1..3) MANUAL4 Switching Characteristics (2)
NO. PARAMETER DESCRIPTION
MODE
MIN
MAX
UNIT
D1
tc(clk)
Cycle time, output pixel clock vouti_clk
DPI1/2/3 in 1.8V mode
DPI2 in 3.3V mode
6.06
(3)
ns
DPI1/3 in 3.3V mode
13.33
(3)
ns
ns
ns
ns
ns
D2
D3
D5
D6
tw(clkL)
Pulse duration, output pixel clock vouti_clk low
Pulse duration, output pixel clock vouti_clk high
P*0.5-
1 (1)
tw(clkH)
P*0.5-
1 (1)
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI1
DPI1
2.85
5.56
5.56
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
2.85
D5
D6
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI2 (vin2a_fld0 clock
reference)
2.85
2.85
5.56
5.56
ns
ns
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
DPI2 (vin2a_fld0 clock
reference)
D5
D6
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI2 (xref_clk2 clock
reference)
2.85
2.85
5.56
5.56
ns
ns
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
DPI2 (xref_clk2 clock
reference)
D5
D6
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI3
DPI3
2.85
2.85
5.56
5.56
ns
ns
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
(1) P = output vouti_clk period in ns.
(2) All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding
CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
(3) SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note SPRAC62 for additional guidance.
表 7-17. DPI Video Output i (i = 1..3) MANUAL5 Switching Characteristics (2)
NO. PARAMETER DESCRIPTION
MODE
MIN
MAX
UNIT
D1
tc(clk)
Cycle time, output pixel clock vouti_clk
DPI1/2/3 in 1.8V mode
DPI2 in 3.3V mode
6.06
(3)
ns
DPI1/3 in 3.3V mode
13.33
(3)
ns
ns
ns
ns
ns
D2
D3
D5
D6
tw(clkL)
Pulse duration, output pixel clock vouti_clk low
Pulse duration, output pixel clock vouti_clk high
P*0.5-
1 (1)
tw(clkH)
P*0.5-
1 (1)
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI1
DPI1
3.55
6.61
6.61
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
3.55
D5
td(clk-ctlV)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI2 (vin2a_fld0 clock
reference)
3.55
6.61
ns
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表 7-17. DPI Video Output i (i = 1..3) MANUAL5 Switching Characteristics (2) (continued)
NO. PARAMETER DESCRIPTION
MODE
MIN
MAX
UNIT
D6
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
DPI2 (vin2a_fld0 clock
reference)
3.55
6.61
ns
D5
D6
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI2 (xref_clk2 clock
reference)
3.55
3.55
6.61
6.61
ns
ns
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
DPI2 (xref_clk2 clock
reference)
D5
D6
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI3
DPI3
3.55
3.55
6.61
6.61
ns
ns
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
(1) P = output vouti_clk period in ns.
(2) All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding
CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
(3) SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note SPRAC62 for additional guidance.
D2
D3
D1
D6
D4
Falling-edge Clock Reference
Rising-edge Clock Reference
vouti_clk
vouti_clk
vouti_vsync
D6
vouti_hsync
vouti_d[23:0]
vouti_de
D5
data_1 data_2
D6
data_n
D6
even
vouti_fld
odd
SWPS049-018
图 7-6. DPI Video Output(1)(2)(3)
(1) The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock.
(2) The polarity and the pulse width of vouti_hsync and vouti_vsync are programmable, refer to the DSS section of the device TRM.
(3) The vouti_clk frequency can be configured, refer to the DSS section of the device TRM.
In 表 7-18 are presented the specific groupings of signals (IOSET) for use with VOUT2.
表 7-18. VOUT2 IOSETs
SIGNALS
IOSET1
IOSET2
BALL
MUX
BALL
MUX
vout2_d23
F2
4
AA4
6
208
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表 7-18. VOUT2 IOSETs (continued)
SIGNALS
IOSET1
IOSET2
BALL
F3
MUX
4
BALL
AB3
AB9
AA3
D17
G16
A21
C18
A17
B17
B16
D15
A15
B15
A20
E15
D12
C12
F13
E12
J11
MUX
6
vout2_d22
vout2_d21
vout2_d20
vout2_d19
vout2_d18
vout2_d17
vout2_d16
vout2_d15
vout2_d14
vout2_d13
vout2_d12
vout2_d11
vout2_d10
vout2_d9
vout2_d8
vout2_d7
vout2_d6
vout2_d5
vout2_d4
vout2_d3
vout2_d2
vout2_d1
vout2_d0
vout2_vsync
vout2_hsync
vout2_clk
vout2_fld
D1
E2
D2
F4
4
6
4
6
4
6
4
6
C1
E4
F5
4
6
4
6
4
6
E6
D3
F6
4
6
4
6
4
6
D5
C2
C3
C4
B2
D6
C5
A3
B3
B4
B5
A4
G6
G1
H7
E1
G2
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
G13
J14
6
4
6
4
B14
F20
E21
B26
F21
C23
6
4
6
4
6
4
6
4
6
vout2_de
4
6
注
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in 表 4-3 and described in Device TRM, Control
Module Chapter.
Virtual IO Timings Modes must be used to guaranteed some IO timings for VOUT1. See 表 7-2 Modes
Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See 表 7-19 Virtual
Functions Mapping for VOUT1 for a definition of the Virtual modes.
表 7-19 presents the values for DELAYMODE bitfield.
表 7-19. Virtual Functions Mapping for DSS VOUT1
BALL
BALL NAME
Delay Mode Value
MUXMODE
DSS_VIRTUAL1
0
3
H3
D9
N7
gpmc_ad15
vout1_d9
gpmc_a8
14
15
15
vout3_d15
vout1_d9
vout3_hsync
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表 7-19. Virtual Functions Mapping for DSS VOUT1 (continued)
BALL
BALL NAME
Delay Mode Value
MUXMODE
DSS_VIRTUAL1
0
3
vout3_d4
L6
E8
M6
F9
gpmc_ad4
vout1_d8
14
15
14
15
14
15
14
15
15
15
15
15
14
15
15
15
15
15
15
15
15
15
14
14
15
14
15
14
15
15
15
15
14
14
15
15
15
15
14
15
14
15
15
15
15
15
vout1_d8
vout1_d5
gpmc_ad0
vout1_d5
vout3_d0
J3
gpmc_ad13
gpmc_a2
vout3_d13
vout3_d18
vout3_d1
T6
M2
P6
B10
B7
R5
A9
H2
T9
gpmc_ad1
gpmc_a4
vout3_d20
vout1_de
vout1_de
vout1_d16
gpmc_a6
vout1_d16
vout3_d22
vout1_d21
gpmc_ad14
gpmc_a1
vout1_d21
vout3_d14
vout3_d17
E7
C11
D11
P1
B9
G11
R4
D8
J2
vout1_d7
vout1_d7
vout1_hsync
vout1_clk
vout1_hsync
vout1_clk
gpmc_cs3
vout1_d22
vout1_d3
vout3_clk
vout1_d22
vout1_d3
gpmc_a9
vout3_vsync
vout1_d11
gpmc_ad11
gpmc_ad6
vout1_d10
gpmc_ad2
vout1_d2
vout1_d11
vout3_d11
vout3_d6
L3
D7
L5
vout1_d10
vout1_d2
vout3_d2
F10
M1
P5
T7
gpmc_ad3
gpmc_a7
vout3_d3
vout3_d23
vout3_d19
gpmc_a3
A7
C7
J1
vout1_d18
vout1_d15
gpmc_ad10
gpmc_ad7
gpmc_a10
vout1_d0
vout1_d18
vout1_d15
vout3_d10
vout3_d7
vout3_de
L2
N9
F11
G10
R9
L1
vout1_d0
vout1_d1
vout1_d1
gpmc_a5
vout3_d21
vout3_d8
gpmc_ad8
vout1_d6
F8
vout1_d6
L4
gpmc_ad5
vout1_d23
vout1_vsync
vout1_d20
gpmc_a0
vout3_d5
A10
E11
C9
R6
A8
vout1_d23
vout1_vsync
vout1_d20
vout3_d16
vout1_d19
vout1_d19
210
Timing Requirements and Switching Characteristics
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表 7-19. Virtual Functions Mapping for DSS VOUT1 (continued)
BALL
BALL NAME
Delay Mode Value
MUXMODE
DSS_VIRTUAL1
0
3
E9
H1
B11
P9
K2
C6
B8
A5
C8
vout1_d4
gpmc_ad12
vout1_fld
15
14
15
15
14
15
15
15
15
vout1_d4
vout3_d12
vout1_fld
gpmc_a11
gpmc_ad9
vout1_d13
vout1_d17
vout1_d12
vout1_d14
vout3_fld
vout3_d9
vout1_d13
vout1_d17
vout1_d12
vout1_d14
注
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section "Manual IO Timing Modes" of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information please see the Control Module Chapter in the Device TRM.
Manual IO Timings Modes must be used to guaranteed some IO timings for VOUT1. See 表 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See 表 7-20 Manual
Functions Mapping for DSS VOUT1 for a definition of the Manual modes.
表 7-20 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
表 7-20. Manual Functions Mapping for DSS VOUT1
BALL BALL NAME
VOUT1_MANUAL1
VOUT1_MANUAL4
VOUT1_MANUAL5
CFG REGISTER
MUXMODE
0
A_DELAY G_DELAY A_DELAY G_DELAY A_DELAY G_DELAY
(ps)
0
(ps)
212
0
(ps)
0
(ps)
249
0
(ps)
0
(ps)
249
0
D11
F11
G10
D7
D8
A5
vout1_clk
vout1_d0
vout1_d1
vout1_d10
vout1_d11
vout1_d12
vout1_d13
vout1_d14
vout1_d15
vout1_d16
vout1_d17
vout1_d18
vout1_d19
vout1_d2
vout1_d20
vout1_d21
vout1_d22
vout1_d23
vout1_d3
vout1_d4
vout1_d5
CFG_VOUT1_CLK_OUT
CFG_VOUT1_D0_OUT
CFG_VOUT1_D1_OUT
CFG_VOUT1_D10_OUT
CFG_VOUT1_D11_OUT
CFG_VOUT1_D12_OUT
CFG_VOUT1_D13_OUT
CFG_VOUT1_D14_OUT
CFG_VOUT1_D15_OUT
CFG_VOUT1_D16_OUT
CFG_VOUT1_D17_OUT
CFG_VOUT1_D18_OUT
CFG_VOUT1_D19_OUT
CFG_VOUT1_D2_OUT
CFG_VOUT1_D20_OUT
CFG_VOUT1_D21_OUT
CFG_VOUT1_D22_OUT
CFG_VOUT1_D23_OUT
CFG_VOUT1_D3_OUT
CFG_VOUT1_D4_OUT
CFG_VOUT1_D5_OUT
vout1_clk
vout1_d0
vout1_d1
vout1_d10
vout1_d11
vout1_d12
vout1_d13
vout1_d14
vout1_d15
vout1_d16
vout1_d17
vout1_d18
vout1_d19
vout1_d2
vout1_d20
vout1_d21
vout1_d22
vout1_d23
vout1_d3
vout1_d4
vout1_d5
2502
2402
2147
2249
2410
2129
2279
2266
1798
2243
2127
2096
2375
2105
2120
2013
1887
2429
2639
2319
3778
3650
3353
3588
3733
3427
3485
3573
3069
3492
3319
3455
3788
3402
3477
3395
3213
3753
3728
3643
4648
4520
4223
4458
4603
4297
4355
4443
3939
4362
4189
4225
4658
4272
4347
4265
3983
4623
4598
4363
0
0
0
0
0
0
0
0
0
0
0
0
C6
C8
C7
B7
0
0
0
0
0
0
23
0
0
0
0
0
B8
0
0
0
A7
0
0
0
A8
0
0
0
F10
C9
A9
0
0
0
0
0
0
0
0
0
B9
65
0
0
0
A10
G11
E9
0
0
0
0
0
0
0
0
F9
0
0
0
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表 7-20. Manual Functions Mapping for DSS VOUT1 (continued)
BALL BALL NAME
VOUT1_MANUAL1
VOUT1_MANUAL4
VOUT1_MANUAL5
CFG REGISTER
MUXMODE
0
A_DELAY G_DELAY A_DELAY G_DELAY A_DELAY G_DELAY
(ps)
2227
2309
1999
2276
1933
1825
1741
(ps)
0
(ps)
3544
3707
3315
3539
3507
3382
3408
(ps)
0
(ps)
4264
4427
4185
4409
4177
4052
4278
(ps)
0
F8
E7
vout1_d6
vout1_d7
vout1_d8
vout1_d9
vout1_de
vout1_fld
CFG_VOUT1_D6_OUT
CFG_VOUT1_D7_OUT
CFG_VOUT1_D8_OUT
CFG_VOUT1_D9_OUT
CFG_VOUT1_DE_OUT
CFG_VOUT1_FLD_OUT
vout1_d6
vout1_d7
vout1_d8
vout1_d9
vout1_de
vout1_fld
0
0
0
E8
0
0
0
D9
0
0
0
B10
B11
0
0
0
0
0
0
C11 vout1_hsync
13
0
0
CFG_VOUT1_HSYNC_O vout1_hsync
UT
E11 vout1_vsync
2338
0
3718
0
4588
0
CFG_VOUT1_VSYNC_OU vout1_vsync
T
Manual IO Timings Modes must be used to guaranteed some IO timings for VOUT2. See 表 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See 表 7-21 Manual
Functions Mapping for DSS VOUT2 IOSET1 for a definition of the Manual modes.
表 7-21 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
212
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表 7-21. Manual Functions Mapping for DSS VOUT2 IOSET1
BALL
BALL
NAME
VOUT2_IOSET1_
MANUAL1
VOUT2_IOSET1_
MANUAL2
VOUT2_IOSET1_
MANUAL3
VOUT2_IOSET1_
MANUAL4
VOUT2_IOSET1_
MANUAL5
CFG REGISTER
MUXMODE
4
A_DELAY G_DELAY A_DELAY G_DELAY A_DELAY G_DELAY A_DELAY G_DELAY A_DELAY G_DELAY
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
E1
vin2a_clk0
2571
0
1059
0
1025
0
4110
0
4980
0
CFG_VIN2A_CLK0_O
UT
vout2_fld
F2
F3
D3
F6
D5
C2
C3
C4
B2
D6
C5
A3
D1
B3
B4
B5
A4
E2
D2
F4
C1
E4
F5
E6
G2
vin2a_d0
vin2a_d1
vin2a_d10
vin2a_d11
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
vin2a_d16
vin2a_d17
vin2a_d18
vin2a_d19
vin2a_d2
vin2a_d20
vin2a_d21
vin2a_d22
vin2a_d23
vin2a_d3
vin2a_d4
vin2a_d5
vin2a_d6
vin2a_d7
vin2a_d8
vin2a_d9
vin2a_de0
2124
2103
2091
2142
2920
2776
2904
2670
2814
3002
1893
1698
2193
1736
1636
1628
1538
1997
2528
2038
1746
2213
2268
2170
2102
0
0
589
568
557
608
1816
1872
1769
1665
1908
1897
358
163
658
202
101
93
0
0
577
557
545
596
1783
1838
1757
1632
1878
1865
347
151
646
190
89
0
0
3613
3442
3430
3481
3943
3799
3869
3792
3837
4024
3432
3237
3531
3075
3074
3266
2968
3335
3867
3577
3285
3552
3607
3509
3841
0
0
4483
4312
4200
4251
4713
4669
4739
4662
4707
4894
4302
4007
4401
3945
3944
4036
3838
4205
4537
4347
4055
4272
4277
4379
4611
0
0
CFG_VIN2A_D0_OUT
CFG_VIN2A_D1_OUT
vout2_d23
vout2_d22
0
0
0
0
0
CFG_VIN2A_D10_OUT vout2_d13
CFG_VIN2A_D11_OUT vout2_d12
CFG_VIN2A_D12_OUT vout2_d11
CFG_VIN2A_D13_OUT vout2_d10
0
0
0
0
0
385
322
0
255
192
0
276
213
0
601
538
174
473
371
415
0
601
538
174
473
371
415
0
CFG_VIN2A_D14_OUT
CFG_VIN2A_D15_OUT
CFG_VIN2A_D16_OUT
CFG_VIN2A_D17_OUT
CFG_VIN2A_D18_OUT
CFG_VIN2A_D19_OUT
CFG_VIN2A_D2_OUT
CFG_VIN2A_D20_OUT
CFG_VIN2A_D21_OUT
CFG_VIN2A_D22_OUT
CFG_VIN2A_D23_OUT
CFG_VIN2A_D3_OUT
CFG_VIN2A_D4_OUT
CFG_VIN2A_D5_OUT
CFG_VIN2A_D6_OUT
CFG_VIN2A_D7_OUT
CFG_VIN2A_D8_OUT
CFG_VIN2A_D9_OUT
vout2_d9
vout2_d8
vout2_d7
vout2_d6
vout2_d5
vout2_d4
vout2_d21
vout2_d3
vout2_d2
vout2_d1
vout2_d0
vout2_d20
vout2_d19
vout2_d18
vout2_d17
vout2_d16
vout2_d15
vout2_d14
vout2_de
257
155
199
0
127
31
69
0
148
43
89
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
81
0
0
0
0
0
0
0
0
0
0
0
462
993
503
211
678
733
635
568
0
450
982
492
200
666
721
623
556
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CFG_VIN2A_DE0_OU
T
H7
G1
vin2a_fld0
0
983
0
1398
974
1185
0
1385
936
1202
0
0
994
0
0
994
0
CFG_VIN2A_FLD0_OU
T
vout2_clk
vin2a_hsync
0
2482
4021
4891
CFG_VIN2A_HSYNC0 vout2_hsync
_OUT
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表 7-21. Manual Functions Mapping for DSS VOUT2 IOSET1 (continued)
BALL
BALL
NAME
VOUT2_IOSET1_
MANUAL1
VOUT2_IOSET1_
MANUAL2
VOUT2_IOSET1_
MANUAL3
VOUT2_IOSET1_
MANUAL4
VOUT2_IOSET1_
MANUAL5
CFG REGISTER
MUXMODE
4
A_DELAY G_DELAY A_DELAY G_DELAY A_DELAY G_DELAY A_DELAY G_DELAY A_DELAY G_DELAY
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
G6
vin2a_vsync
0
2296
0
784
0
750
0
3935
0
4805
0
CFG_VIN2A_VSYNC0 vout2_vsync
_OUT
Manual IO Timings Modes must be used to guaranteed some IO timings for VOUT2. See 表 7-2 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See 表 7-22 Manual Functions Mapping for DSS VOUT2 IOSET2 for a definition of the Manual modes.
表 7-22 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
表 7-22. Manual Functions Mapping for DSS VOUT2 IOSET2
BALL
BALL
NAME
VOUT2_IOSET2_
MANUAL1
VOUT2_IOSET2_
MANUAL2
VOUT2_IOSET2_
MANUAL3
VOUT2_IOSET2_
MANUAL4
VOUT2_IOSET2_
MANUAL5
CFG REGISTER
MUXMODE
6
A_DELAY G_DELAY A_DELAY G_DELAY A_DELAY G_DELAY A_DELAY G_DELAY A_DELAY G_DELAY
(ps)
1983
2159
1864
2614
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
3513
3689
3394
4353
(ps)
(ps)
4383
4559
4264
5223
(ps)
E21
F20
F21
B14
gpio6_14
gpio6_15
gpio6_16
0
79
0
68
0
0
0
CFG_GPIO6_14_OUT vout2_hsync
CFG_GPIO6_15_OUT vout2_vsync
0
158
0
0
148
0
0
0
0
0
0
0
0
0
CFG_GPIO6_16_OUT
vout2_fld
vout2_d0
mcasp1_acl
kr
0
1255
0
1270
0
0
0
CFG_MCASP1_ACLK
R_OUT
G13
J11
E12
F13
C12
D12
J14
E15
B15
mcasp1_axr
2
2705
2865
2759
2980
2634
2658
2818
2728
2513
0
0
0
0
0
0
0
0
0
1350
1210
1404
1325
1275
1302
1163
1373
319
0
0
1360
1219
1413
1335
1289
1311
1172
1382
308
0
0
4444
4504
4498
4419
4373
4396
4456
4367
4151
0
0
0
0
0
0
0
0
0
5314
5374
5368
5289
5243
5266
5326
5237
5021
0
0
0
0
0
0
0
0
0
CFG_MCASP1_AXR2_
OUT
vout2_d2
vout2_d3
vout2_d4
vout2_d5
vout2_d6
vout2_d7
vout2_d1
vout2_d8
mcasp1_axr
3
CFG_MCASP1_AXR3_
OUT
mcasp1_axr
4
0
0
CFG_MCASP1_AXR4_
OUT
mcasp1_axr
5
0
0
CFG_MCASP1_AXR5_
OUT
mcasp1_axr
6
0
0
CFG_MCASP1_AXR6_
OUT
mcasp1_axr
7
0
0
CFG_MCASP1_AXR7_
OUT
mcasp1_fsr
0
0
CFG_MCASP1_FSR_
OUT
mcasp2_acl
kr
0
0
CFG_MCASP2_ACLK
R_OUT
mcasp2_axr
0
534
560
CFG_MCASP2_AXR0_ vout2_d10
OUT
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表 7-22. Manual Functions Mapping for DSS VOUT2 IOSET2 (continued)
BALL
BALL
NAME
VOUT2_IOSET2_
MANUAL1
VOUT2_IOSET2_
MANUAL2
VOUT2_IOSET2_
MANUAL3
VOUT2_IOSET2_
MANUAL4
VOUT2_IOSET2_
MANUAL5
CFG REGISTER
MUXMODE
6
A_DELAY G_DELAY A_DELAY G_DELAY A_DELAY G_DELAY A_DELAY G_DELAY A_DELAY G_DELAY
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
A15
D15
B16
B17
A17
A20
C18
G16
D17
A21
AA3
AB3
AA4
AB9
B26
C23
mcasp2_axr
1
2712
0
1357
0
1366
0
4351
0
5221
0
CFG_MCASP2_AXR1_ vout2_d11
OUT
mcasp2_axr
4
2529
2376
2620
2492
2358
2524
2578
2253
2478
4672
4642
4625
4565
0
0
0
1169
543
0
478
0
1184
1029
1274
845
0
0
4267
4114
4359
4130
3797
3863
4208
3983
4117
5900
5870
6153
6093
0
0
0
5137
4984
5229
5000
4667
4733
5078
4853
4987
6770
6740
7023
6963
0
0
0
CFG_MCASP2_AXR4_ vout2_d12
OUT
mcasp2_axr
5
CFG_MCASP2_AXR5_ vout2_d13
OUT
mcasp2_axr
6
0
1265
354
0
0
0
CFG_MCASP2_AXR6_ vout2_d14
OUT
mcasp2_axr
7
0
483
487
0
0
0
0
CFG_MCASP2_AXR7_ vout2_d15
OUT
mcasp2_fsr
0
12
513
0
0
0
CFG_MCASP2_FSR_
OUT
vout2_d9
mcasp4_acl
kx
0
1165
797
1179
806
0
0
0
CFG_MCASP4_ACLKX vout2_d16
_OUT
mcasp4_axr
0
0
0
0
0
0
CFG_MCASP4_AXR0_ vout2_d18
OUT
mcasp4_axr
1
0
750
0
759
0
0
0
CFG_MCASP4_AXR1_ vout2_d19
OUT
mcasp4_fsx
0
823
0
832
0
0
0
CFG_MCASP4_FSX_O vout2_d17
UT
mcasp5_acl
kx
1737
1286
725
1062
49
0
3256
3226
3209
3149
1359
36
1798
1347
786
1123
466
0
3226
3196
3179
3119
1341
45
1837
1386
825
1162
512
0
1949
1497
935
1273
60
0
1949
1497
935
1273
60
0
CFG_MCASP5_ACLKX vout2_d20
_OUT
mcasp5_axr
0
CFG_MCASP5_AXR0_ vout2_d22
OUT
mcasp5_axr
1
CFG_MCASP5_AXR1_ vout2_d23
OUT
mcasp5_fsx
CFG_MCASP5_FSX_O vout2_d21
UT
xref_clk2
CFG_XREF_CLK2_OU
T
vout2_clk
xref_clk3
1947
3378
4248
CFG_XREF_CLK3_OU
T
vout2_de
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Manual IO Timings Modes must be used to guaranteed some IO timings for VOUT3. See 表 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See 表 7-23 Manual
Functions Mapping for DSS VOUT3 for a definition of the Manual modes.
表 7-23 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
表 7-23. Manual Functions Mapping for DSS VOUT3
BALL
BALL
NAME
VOUT3_MANUAL1
VOUT3_MANUAL4
VOUT3_MANUAL5
CFG REGISTER
MUXMODE
3
A_DELAY G_DELAY A_DELAY G_DELAY A_DELAY G_DELAY
(ps)
2395
2412
2473
2906
2360
2391
2626
2338
2374
2432
3155
(ps)
0
(ps)
3909
3957
3980
4253
3873
4112
4336
3840
3913
3947
4309
(ps)
0
(ps)
4779
4827
4850
5123
4743
4982
5206
4710
4783
4817
5179
(ps)
0
R6
T9
N9
P9
T6
T7
P6
R9
R5
P5
N7
gpmc_a0
gpmc_a1
gpmc_a10
gpmc_a11
gpmc_a2
gpmc_a3
gpmc_a4
gpmc_a5
gpmc_a6
gpmc_a7
gpmc_a8
CFG_GPMC_A0_OUT
CFG_GPMC_A1_OUT
CFG_GPMC_A10_OUT
CFG_GPMC_A11_OUT
CFG_GPMC_A2_OUT
CFG_GPMC_A3_OUT
CFG_GPMC_A4_OUT
CFG_GPMC_A5_OUT
CFG_GPMC_A6_OUT
CFG_GPMC_A7_OUT
CFG_GPMC_A8_OUT
vout3_d16
vout3_d17
vout3_de
0
0
0
0
0
0
0
0
0
vout3_fld
0
0
0
vout3_d18
vout3_d19
vout3_d20
vout3_d21
vout3_d22
vout3_d23
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
105
105
vout3_hsyn
c
R4
gpmc_a9
2309
0
3842
0
4712
0
CFG_GPMC_A9_OUT
vout3_vsyn
c
M6
M2
J1
gpmc_ad0
gpmc_ad1
gpmc_ad10
gpmc_ad11
gpmc_ad12
gpmc_ad13
gpmc_ad14
gpmc_ad15
gpmc_ad2
gpmc_ad3
gpmc_ad4
gpmc_ad5
gpmc_ad6
gpmc_ad7
gpmc_ad8
gpmc_ad9
gpmc_cs3
2360
2420
2235
2253
1949
2318
2123
2195
2617
2350
2324
2371
2231
2440
2479
2355
0
0
0
3652
3762
3456
3584
3589
3547
3302
3532
3859
3590
3534
3609
3416
3661
3714
3593
0
0
0
4522
4632
4326
4454
4459
4417
4172
4402
4729
4460
4404
4479
4286
4531
4584
4463
0
0
0
CFG_GPMC_AD0_OUT
CFG_GPMC_AD1_OUT
vout3_d0
vout3_d1
0
0
0
CFG_GPMC_AD10_OUT vout3_d10
CFG_GPMC_AD11_OUT vout3_d11
CFG_GPMC_AD12_OUT vout3_d12
CFG_GPMC_AD13_OUT vout3_d13
CFG_GPMC_AD14_OUT vout3_d14
CFG_GPMC_AD15_OUT vout3_d15
J2
0
0
0
H1
J3
427
0
0
0
0
0
H2
H3
L5
M1
L6
L4
L3
L2
L1
K2
P1
0
0
0
29
0
0
0
0
0
CFG_GPMC_AD2_OUT
CFG_GPMC_AD3_OUT
CFG_GPMC_AD4_OUT
CFG_GPMC_AD5_OUT
CFG_GPMC_AD6_OUT
CFG_GPMC_AD7_OUT
CFG_GPMC_AD8_OUT
CFG_GPMC_AD9_OUT
CFG_GPMC_CS3_OUT
vout3_d2
vout3_d3
vout3_d4
vout3_d5
vout3_d6
vout3_d7
vout3_d8
vout3_d9
vout3_clk
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
641
905
905
7.8 Display Subsystem - High-Definition Multimedia Interface (HDMI)
The High-Definition Multimedia Interface is provided for transmitting digital television audiovisual signals
from DVD players, set-top boxes and other audiovisual sources to television sets, projectors and other
video displays. The HDMI interface is aligned with the HDMI TMDS single stream standard v1.4a (720p
@60Hz to 1080p @24Hz) and the HDMI v1.3 (1080p @60Hz): 3 data channels, plus 1 clock channel is
supported (differential).
216
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注
For more information, see the High-Definition Multimedia Interface chapter of the device
TRM
7.9 Camera Serial Interface 2 CAL bridge (CSI2)
注
For more information, see the Camera Serial Interface 2 CAL Bridge chapter of the device
TRM
The camera adaptation layer (CAL) deals with the processing of the pixel data coming from an external
image sensor, data from memory. The CAL is a key component for the following multimedia applications:
camera viewfinder, video record, and still image capture. The CAL has two serial camera interfaces
(primary and secondary):
•
•
The primary serial interface (CSI2 Port A) is compliant with MIPI CSI-2 protocol with four data lanes.
The secondary serial interface (CSI2 Port B) is compliant with MIPI CSI-2 protocol with two data lanes.
7.9.1 CSI-2 MIPI D-PHY
The CSI-2 port A is compliant with the MIPI D-PHY RX specification v1.00.00 and the MIPI CSI-2
specification v1.00, with 4 data differential lanes plus 1 clock differential lane in synchronous mode,
double data rate:
•
1.5 Gbps (750 MHz) @OPP_NOM for each lane.
The CSI-2 port B is compliant with the MIPI D-PHY RX specification v1.00.00 and the MIPI CSI-2
specification v1.00, with 2 data lanes plus 1 clock lane (differential) in synchronous mode, double data
rate:
•
1.5 Gbps (750 MHz) @OPP_NOM for each lane, in synchronous mode.
7.10 External Memory Interface (EMIF)
The device has a dedicated interface to DDR3 and DDR3L SDRAM. It supports JEDEC standard
compliant DDR3 and DDR3L SDRAM devices with the following features:
•
•
•
16-bit or 32-bit data path to external SDRAM memory
Memory device capacity: 128Mb, 256Mb, 512Mb, 1Gb, 2Gb, 4Gb and 8Gb devices
One interface with associated DDR3/DDR3L PHYs
注
For more information, see the EMIF Controller section of the Device TRM.
7.11 General-Purpose Memory Controller (GPMC)
The GPMC is the unified memory controller that interfaces external memory devices such as:
•
•
•
Asynchronous SRAM-like memories and ASIC devices
Asynchronous page mode and synchronous burst NOR flash
NAND flash
注
For more information, see the General-Purpose Memory Controller section of the Device
TRM.
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7.11.1 GPMC/NOR Flash Interface Synchronous Timing
CAUTION
The I/O Timings provided in this section are valid only for some GPMC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
表 7-24 and 表 7-25 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see 图 7-7, 图 7-8, 图 7-9, 图 7-10, 图 7-11 and 图 7-12).
表 7-24. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - Default
NO.
PARAMETER
DESCRIPTION
MIN
3
MAX
UNIT
ns
F12 tsu(dV-clkH)
F13 th(clkH-dV)
F21 tsu(waitV-clkH)
F22 th(clkH-waitV)
Setup time, read gpmc_ad[15:0] valid before gpmc_clk high
Hold time, read gpmc_ad[15:0] valid after gpmc_clk high
Setup time, gpmc_wait[1:0] valid before gpmc_clk high
Hold Time, gpmc_wait[1:0] valid after gpmc_clk high
1.1
2.5
1.3
ns
ns
ns
注
Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of
wait monitoring feature, see the Device TRM.
表 7-25. GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Default
NO.
F0
PARAMETER
tc(clk)
DESCRIPTION
Cycle time, output clock gpmc_clk period
MIN
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11.3
(7)
(7)
F2
td(clkH-nCSV)
td(clkH-nCSIV)
td(ADDV-clk)
td(clkH-ADDIV)
td(nBEV-clk)
td(clkH-nBEIV)
td(clkH-nADV)
td(clkH-nADVIV)
td(clkH-nOE)
td(clkH-nOEIV)
td(clkH-nWE)
td(clkH-Data)
td(clkH-nBE)
tw(nCSV)
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] invalid
Delay time, gpmc_a[27:0] address bus valid to gpmc_clk first edge
Delay time, gpmc_clk rising edge to gpmc_a[27:0] gpmc address bus invalid
Delay time, gpmc_ben[1:0] valid to gpmc_clk rising edge
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] invalid
Delay time, gpmc_clk rising edge to gpmc_advn_ale transition
Delay time, gpmc_clk rising edge to gpmc_advn_ale invalid
Delay time, gpmc_clk rising edge to gpmc_oen_ren transition
Delay time, gpmc_clk rising edge to gpmc_oen_ren invalid
Delay time, gpmc_clk rising edge to gpmc_wen transition
Delay time, gpmc_clk rising edge to gpmc_ad[15:0] data bus transition
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] transition
Pulse duration, gpmc_cs[7:0] low
F-1.7
F+4.3
F3
E-1.7 (6) E+4.2 (6)
B-1.8 (3) B+4.3 (3)
-1.8
B-4.3(3)
D-1.5(5)
G-1.3 (8) G+4.2 (8)
D-1.3 (5) G+4.2 (5)
H-1.0 (9) H+3.2 (9)
E-1.0 (6) E+3.2 (6)
I-0.9 (10) I+4.2 (10)
F4
F5
F6
B+1.5(3)
D+4.3(5)
F7
F8
F9
F10
F11
F14
F15
F17
F18
F19
F20
F23
(11)
(11)
J-2.1
J-1.5
J+4.6
J+4.3
(11)
(11)
A (2)
(4)
tw(nBEV)
Pulse duration, gpmc_ben[1:0] low
C
tw(nADVV)
Pulse duration, gpmc_advn_ale low
K (12)
td(CLK-GPIO)
Delay time, gpmc_clk transition to gpio6_16 transition
0.5
7.5
表 7-26. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - Alternate
NO.
PARAMETER
DESCRIPTION
MIN
2.5
MAX
UNIT
ns
F12 tsu(dV-clkH)
F13 th(clkH-dV)
Setup time, read gpmc_ad[15:0] valid before gpmc_clk high
Hold time, read gpmc_ad[15:0] valid after gpmc_clk high
1.9
ns
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表 7-26. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - Alternate (continued)
NO.
F21 tsu(waitV-clkH)
F22 th(clkH-waitV)
PARAMETER
DESCRIPTION
MIN
2.5
MAX
UNIT
ns
Setup time, gpmc_wait[1:0] valid before gpmc_clk high
Hold Time, gpmc_wait[1:0] valid after gpmc_clk high
1.9
ns
表 7-27. GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Alternate
NO.
F0
F2
F3
F4
F5
F6
F7
F8
F9
PARAMETER
tc(clk)
DESCRIPTION
Cycle time, output clock gpmc_clk period (13)
MIN
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15.04
(7)
(7)
td(clkH-nCSV)
td(clkH-nCSIV)
td(ADDV-clk)
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] invalid
Delay time, gpmc_a[27:0] address bus valid to gpmc_clk first edge
Delay time, gpmc_clk rising edge to gpmc_a[27:0] gpmc address bus invalid
Delay time, gpmc_ben[1:0] valid to gpmc_clk rising edge
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] invalid
Delay time, gpmc_clk rising edge to gpmc_advn_ale transition
Delay time, gpmc_clk rising edge to gpmc_advn_ale invalid
Delay time, gpmc_clk rising edge to gpmc_oen_ren transition
Delay time, gpmc_clk rising edge to gpmc_oen_ren invalid
Delay time, gpmc_clk rising edge to gpmc_wen transition
Delay time, gpmc_clk rising edge to gpmc_ad[15:0] data bus transition
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] transition
Pulse duration, gpmc_cs[7:0] low
F+0.6
F+7.0
E+0.6 (6)
B-0.7 (3)
-0.7
E+7.0 (6)
B+7.0 (3)
td(clkH-ADDIV)
td(nBEV-clk)
B-7.0
B+0.4
td(clkH-nBEIV)
td(clkH-nADV)
td(clkH-nADVIV)
D-0.4
D+7.0
G+0.7 (8)
D+0.7 (5)
H+0.7 (9)
E+0.7 (6)
I+0.7 (10)
G+6.1 (8)
D+6.1 (5)
H+5.1 (9)
E+5.1 (6)
I+6.1 (10)
F10 td(clkH-nOE)
F11 td(clkH-nOEIV)
F14 td(clkH-nWE)
F15 td(clkH-Data)
F17 td(clkH-nBE)
F18 tw(nCSV)
(11)
(11)
J-0.4
J+4.9
(11)
(11)
J-0.4
J+4.9
A (2)
(4)
F19 tw(nBEV)
Pulse duration, gpmc_ben[1:0] low
C
F20 tw(nADVV)
F23 td(CLK-GPIO)
Pulse duration, gpmc_advn_ale low
Delay time, gpmc_clk transition to gpio6_16.clkout1 transition (14)
K (12)
0.5
7.5
(1) Total GPMC load on any signal at 3.3V must not exceed 10pF.
(2) For single read: A = (CSRdOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK period
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period
with n the page burst access number.
(3) B = ClkActivationTime * GPMC_FCLK
(4) For single read: C = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: C = (RdCycleTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For Burst write: C = (WrCycleTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK with n the page burst
access number.
(5) For single read: D = (RdCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: D = (RdCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: D = (WrCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(6) For single read: E = (CSRdOffTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: E = (CSRdOffTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: E = (CSWrOffTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(7) For nCS falling edge (CS activated):
Case GpmcFCLKDivider = 0 :
F = 0.5 * CSExtraDelay * GPMC_FCLK Case GpmcFCLKDivider = 1:
F = 0.5 * CSExtraDelay * GPMC_FCLK if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are even)
F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
F = 0.5 * CSExtraDelay * GPMC_FCLK if ((CSOnTime - ClkActivationTime) is a multiple of 3)
F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)
F = (2 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
F = 0.5 * CSExtraDelay * GPMC_FCLK if ((CSOnTime - ClkActivationTime) is a multiple of 4)
F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime - ClkActivationTime - 1) is a multiple of 4)
F = (2 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime - ClkActivationTime - 2) is a multiple of 4)
F = (3 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime - ClkActivationTime - 3) is a multiple of 4)
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(8) For ADV falling edge (ADV activated):
Case GpmcFCLKDivider = 0 :
G = 0.5 * ADVExtraDelay * GPMC_FCLK
Case GpmcFCLKDivider = 1:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are
even)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVOnTime - ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3)
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3)
For ADV rising edge (ADV desactivated) in Reading mode:
Case GpmcFCLKDivider = 0:
G = 0.5 * ADVExtraDelay * GPMC_FCLK
Case GpmcFCLKDivider = 1:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and ADVRdOffTime
are even)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3)
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime) is a multiple of 4)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 4)
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 4)
G = (3 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime - 3) is a multiple of 4)
For ADV rising edge (ADV desactivated) in Writing mode:
Case GpmcFCLKDivider = 0:
G = 0.5 * ADVExtraDelay * GPMC_FCLK
Case GpmcFCLKDivider = 1:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and ADVWrOffTime
are even)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3)
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime) is a multiple of 4)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 4)
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 4)
G = (3 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 3) is a multiple of 4)
(9) For OE falling edge (OE activated):
Case GpmcFCLKDivider = 0:
- H = 0.5 * OEExtraDelay * GPMC_FCLK
Case GpmcFCLKDivider = 1:
- H = 0.5 * OEExtraDelay * GPMC_FCLK if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are even)
- H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
- H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOnTime - ClkActivationTime) is a multiple of 3)
- H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)
- H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
- H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOnTime - ClkActivationTime) is a multiple of 4)
- H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime - ClkActivationTime - 1) is a multiple of 4)
- H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime - ClkActivationTime - 2) is a multiple of 4)
- H = (3 + 0.5 * OEExtraDelay)) * GPMC_FCLK if ((OEOnTime - ClkActivationTime - 3) is a multiple of 4)
For OE rising edge (OE desactivated):
Case GpmcFCLKDivider = 0:
- H = 0.5 * OEExtraDelay * GPMC_FCLK
Case GpmcFCLKDivider = 1:
- H = 0.5 * OEExtraDelay * GPMC_FCLK if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are even)
- H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
- H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOffTime - ClkActivationTime) is a multiple of 3)
- H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)
- H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
- H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOffTime - ClkActivationTime) is a multiple of 4)
- H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime - ClkActivationTime - 1) is a multiple of 4)
- H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime - ClkActivationTime - 2) is a multiple of 4)
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- H = (3 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime - ClkActivationTime - 3) is a multiple of 4)
(10) For WE falling edge (WE activated):
Case GpmcFCLKDivider = 0:
- I = 0.5 * WEExtraDelay * GPMC_FCLK
Case GpmcFCLKDivider = 1:
- I = 0.5 * WEExtraDelay * GPMC_FCLK if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are
even)
- I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
- I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOnTime - ClkActivationTime) is a multiple of 3)
- I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)
- I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
- I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOnTime - ClkActivationTime) is a multiple of 4)
- I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime - ClkActivationTime - 1) is a multiple of 4)
- I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime - ClkActivationTime - 2) is a multiple of 4)
- I = (3 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime - ClkActivationTime - 3) is a multiple of 4)
For WE rising edge (WE desactivated):
Case GpmcFCLKDivider = 0:
- I = 0.5 * WEExtraDelay * GPMC_FCLK
Case GpmcFCLKDivider = 1:
- I = 0.5 * WEExtraDelay * GPMC_FCLK if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are
even)
- I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
- I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOffTime - ClkActivationTime) is a multiple of 3)
- I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)
- I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
- I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOffTime - ClkActivationTime) is a multiple of 4)
- I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime - ClkActivationTime - 1) is a multiple of 4)
- I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime - ClkActivationTime - 2) is a multiple of 4)
- I = (3 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime - ClkActivationTime - 3) is a multiple of 4)
(11) J = GPMC_FCLK period, where GPMC_FCLK is the General Purpose Memory Controller internal functional clock
(12) For read:
K = (ADVRdOffTime - ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For write: K = (ADVWrOffTime - ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(13) The gpmc_clk output clock maximum and minimum frequency is programmable in the I/F module by setting the GPMC_CONFIG1_CSx
configuration register bit fields GpmcFCLKDivider
(14) gpio6_16 programmed to MUXMODE=9 (clkout1), CM_CLKSEL_CLKOUTMUX1 programmed to 7 (CORE_DPLL_OUT_DCLK),
CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX programmed to 1.
(15) CSEXTRADELAY = 0, ADVEXTRADELAY = 0, WEEXTRADELAY = 0, OEEXTRADELAY = 0. Extra half-GPMC_FCLK cycle delay
mode is not timed.
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F1
F0
F1
gpmc_clk
F2
F3
F18
gpmc_csi
F4
gpmc_a[10:1]
gpmc_a[27]
Address (MSB)
F19
F6
F7
F7
gpmc_ben1
F6
F19
gpmc_ben0
gpmc_advn_ale
gpmc_oen_ren
F8
F8
F20
F9
F10
F11
F13
F4
F5
F12
D 0
gpmc_ad[15:0]
Address (LSB)
F22
F21
gpmc_waitj
F23
F23
gpio6_16.clkout1
GPMC_01
图 7-7. GPMC / Multiplexed 16bits NOR Flash - Synchronous Single Read -
(GpmcFCLKDivider = 0)(1)(2)
(1) In gpmc_csi, i = 0 to 7.
(2) In gpmc_waitj, j = 0 to 1.
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Timing Requirements and Switching Characteristics
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F1
F0
F1
gpmc_clk
F2
F3
F18
gpmc_csi
F4
F6
gpmc_a[27:1]
Address
F7
F7
F19
gpmc_ben1
gpmc_ben0
F6
F19
F8
F8
F9
F20
gpmc_advn_ale
gpmc_oen_ren
F10
F11
F13
F12
D 0
gpmc_ad[15:0]
F22
F21
gpmc_waitj
F23
F23
gpio6_16.clkout1
GPMC_02
图 7-8. GPMC / Nonmultiplexed 16bits NOR Flash - Synchronous Single Read -
(GpmcFCLKDivider = 0)(1)(2)
(1) In gpmc_csi, i = 0 to 7.
(2) In gpmc_waitj, j = 0 to 1.
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F1
F1
F0
gpmc_clk
F2
F3
F18
gpmc_csi
F4
gpmc_a[10:1]
gpmc_a[27]
Address (MSB)
F7
F7
F6
F19
gpmc_ben1
Valid
F6
F19
Valid
gpmc_ben0
F8
F8
F9
F20
gpmc_advn_ale
gpmc_oen_ren
F10
F5
F11
F12
F4
F13
D1
F12
gpmc_ad[15:0]
D0
D2
D3
Address (LSB)
F22
F21
gpmc_waitj
F23
F23
gpio6_16.clkout1
GPMC_03
图 7-9. GPMC / Multiplexed 16bits NOR Flash - Synchronous Burst Read 4x16 bits -
(GpmcFCLKDivider = 0)(1)(2)
(1) In gpmc_csi, i= 0 to 7.
(2) In gpmc_waitj, j = 0 to 1.
224
Timing Requirements and Switching Characteristics
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F1
F1
F0
gpmc_clk
F2
F3
F18
gpmc_csi
gpmc_a[27:1]
gpmc_ben1
gpmc_ben0
F4
F6
Address
F7
F19
Valid
F7
F6
F19
Valid
F8
F8
F20
F9
gpmc_advn_ale
gpmc_oen_ren
F10
F11
F12
F13
D1
F12
gpmc_ad[15:0]
D0
D3
D2
F21
F22
gpmc_waitj
F23
F23
gpio6_16.clkout1
GPMC_04
图 7-10. GPMC / Nonmultiplexed 16bits NOR Flash - Synchronous Burst Read 4x16 bits -
(GpmcFCLKDivider = 0)(1)(2)
(1) In gpmc_csi, i = 0 to 7.
(2) In gpmc_waitj, j = 0 to 1.
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F1
F1
F0
gpmc_clk
F2
F3
F18
gpmc_csi
F4
gpmc_a[10:1]
gpmc_a[27]
Address (MSB)
F17
F17
F6
F6
F17
F17
F17
F17
gpmc_ben1
gpmc_ben0
F8
F20
F8
F9
gpmc_advn_ale
F14
F14
gpmc_wen
gpmc_ad[15:0]
gpmc_waitj
F15
D 1
F15
D 2
F15
Address (LSB)
D 0
D 3
F22
F21
F23
F23
gpio6_16.clkout1
GPMC_05
图 7-11. GPMC / Multiplexed 16bits NOR Flash - Synchronous Burst Write 4x16bits -
(GpmcFCLKDivider = 0)(1)(2)
(1) In “gpmc_csi”, i = 0 to 7.
(2) In “gpmc_waitj”, j = 0 to 1.
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ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
F1
F1
F0
gpmc_clk
F2
F3
F18
gpmc_csi
F4
F6
F6
gpmc_a[27:1]
Address
F17
F17
F17
F17
gpmc_ben1
gpmc_ben0
F17
F17
F8
F20
F8
F9
gpmc_advn_ale
F14
F14
gpmc_wen
gpmc_ad[15:0]
gpmc_waitj
F15
D 1
F15
D 2
F15
D 0
D 3
F21
F22
F23
F23
gpio6_16.clkout1
GPMC_06
图 7-12. GPMC / Nonmultiplexed 16bits NOR Flash - Synchronous Burst Write 4x16bits -
(GpmcFCLKDivider = 0)(1)(2)
(1) In “gpmc_csi”, i = 1 to 7.
(2) In “gpmc_waitj”, j = 0 to 1.
7.11.2 GPMC/NOR Flash Interface Asynchronous Timing
CAUTION
The I/O Timings provided in this section are valid only for some GPMC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
表 7-28 and 表 7-29 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see 图 7-13, 图 7-14, 图 7-15, 图 7-16, 图 7-17 and 图 7-18).
表 7-28. GPMC/NOR Flash Interface Timing Requirements - Asynchronous Mode
NO.
PARAMETER
tacc(DAT)
DESCRIPTION
MIN
MAX
UNIT
(1)
FA5
Data Maximum Access Time (GPMC_FCLK cycles)
H
cycles
cycles
FA20 tacc1-pgmode(DAT)
Page Mode Successive Data Maximum Access Time (GPMC_FCLK
cycles)
P (2)
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表 7-28. GPMC/NOR Flash Interface Timing Requirements - Asynchronous Mode (continued)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
cycles
ns
(1)
FA21 tacc2-pgmode(DAT)
Page Mode First Data Maximum Access Time (GPMC_FCLK cycles)
Setup time, read gpmc_ad[15:0] valid before gpmc_oen_ren high
Hold time, read gpmc_ad[15:0] valid after gpmc_oen_ren high
H
-
-
tsu(DV-OEH)
th(OEH-DV)
1.9
1
ns
(1) H = Access Time * (TimeParaGranularity + 1)
(2) P = PageBurstAccessTime * (TimeParaGranularity + 1)
表 7-29. GPMC/NOR Flash Interface Switching Characteristics - Asynchronous Mode
NO.
PARAMETER
tr(DO)
tf(DO)
DESCRIPTION
Rising time, gpmc_ad[15:0] output data
MIN
0.447
0.43
MAX
4.067
4.463
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
Fallling time, gpmc_ad[15:0] output data
(1)
FA0 tw(nBEV)
Pulse duration, gpmc_ben[1:0] valid time
N
(2)
FA1 tw(nCSV)
Pulse duration, gpmc_cs[7:0] low
A
(3)
(3)
FA3 td(nCSV-nADVIV)
FA4 td(nCSV-nOEIV)
FA9 td(AV-nCSV)
FA10 td(nBEV-nCSV)
FA12 td(nCSV-nADVV)
FA13 td(nCSV-nOEV)
FA16 tw(AIV)
Delay time, gpmc_cs[7:0] valid to gpmc_advn_ale invalid
Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren invalid (Single read)
Delay time, address bus valid to gpmc_cs[7:0] valid
Delay time, gpmc_ben[1:0] valid to gpmc_cs[7:0] valid
Delay time, gpmc_cs[7:0] valid to gpmc_advn_ale valid
Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren valid
Pulse duration, address invalid between 2 successive R/W accesses
Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren invalid (Burst read)
Pulse duration, address valid : 2nd, 3rd and 4th accesses
Delay time, gpmc_cs[7:0] valid to gpmc_wen valid
Delay time, gpmc_cs[7:0] valid to gpmc_wen invalid
Delay time, gpmc_ wen valid to data bus valid
B - 2
C - 2
J - 2
J - 2
K - 2
L - 2
B + 4
C + 4
J + 4
J + 4
K + 4
L + 4
(4)
(5)
(5)
(6)
(7)
(4)
(5)
(5)
(6)
(7)
(8)
G
(9)
(9)
FA18 td(nCSV-nOEIV)
FA20 tw(AV)
I - 2
I + 4
(10)
D
(11)
(12)
(11)
(12)
FA25 td(nCSV-nWEV)
FA27 td(nCSV-nWEIV)
FA28 td(nWEV-DV)
FA29 td(DV-nCSV)
FA37 td(nOEV-AIV)
E - 2
F - 2
E + 4
F + 4
2
(5)
(5)
Delay time, data bus valid to gpmc_cs[7:0] valid
J - 2
J + 4
2
Delay time, gpmc_oen_ren valid to gpmc_ad[15:0] multiplexed address bus
phase end
(1) For single read: N = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK
For single write: N = WrCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: N = (RdCycleTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: N = (WrCycleTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(2) For single read: A = (CSRdOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For single write: A = (CSWrOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(3) For reading: B = ((ADVRdOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - CSExtraDelay)) * GPMC_FCLK
For writing: B = ((ADVWrOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - CSExtraDelay)) * GPMC_FCLK
(4) C = ((OEOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) * GPMC_FCLK
(5) J = (CSOnTime * (TimeParaGranularity + 1) + 0.5 * CSExtraDelay) * GPMC_FCLK
(6) K = ((ADVOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - CSExtraDelay)) * GPMC_FCLK
(7) L = ((OEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) * GPMC_FCLK
(8) G = Cycle2CycleDelay * GPMC_FCLK * (TimeParaGranularity +1)
(9) I = ((OEOffTime + (n - 1) * PageBurstAccessTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) *
GPMC_FCLK
(10) D = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK
(11) E = ((WEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - CSExtraDelay)) * GPMC_FCLK
(12) F = ((WEOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - CSExtraDelay)) * GPMC_FCLK
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GPMC_FCLK
gpmc_clk
FA5
FA1
gpmc_csi
FA9
gpmc_a[27:1]
Valid Address
FA0
FA10
gpmc_ben0
gpmc_ben1
Valid
FA0
Valid
FA10
FA3
FA12
gpmc_advn_ale
FA4
FA13
gpmc_oen_ren
gpmc_ad[15:0]
Data IN 0
Data IN 0
gpmc_waitj
FA15
FA14
OUT
IN
OUT
DIR
GPMC_07
图 7-13. GPMC / NOR Flash - Asynchronous Read - Single Word Timing(1)(2)(3)
(1) In gpmc_csi, i = 0 to 7. In gpmc_waitj, j = 0 to 1.
(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock
edge. FA5 value must be stored inside AccessTime register bits field.
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
(4) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
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GPMC_FCLK
gpmc_clk
FA5
FA5
FA1
FA1
gpmc_csi
FA16
FA9
FA9
gpmc_a[27:1]
Address 0
FA0
Address 1
FA0
FA10
FA10
gpmc_ben0
Valid
FA0
Valid
FA0
gpmc_ben1
FA10
Valid
Valid
FA10
FA3
FA12
FA3
FA12
gpmc_advn_ale
FA4
FA4
FA13
FA13
gpmc_oen_ren
gpmc_ad[15:0]
Data Upper
gpmc_waitj
FA15
FA15
FA14
OUT
FA14
OUT
DIR
IN
IN
GPMC_08
图 7-14. GPMC / NOR Flash - Asynchronous Read - 32-bit Timing(1)(2)(3)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.
(2) FA5 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock
edge. FA5 value should be stored inside AccessTime register bits field
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally
(4) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
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Timing Requirements and Switching Characteristics
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GPMC_FCLK
gpmc_clk
FA21
FA20
Add1
FA20 FA20
FA1
gpmc_csi
FA9
gpmc_a[27:1]
Add0
Add2
Add3
Add4
FA0
FA10
FA10
gpmc_ben0
FA0
gpmc_ben1
FA12
gpmc_advn_ale
FA18
FA13
gpmc_oen_ren
gpmc_ad[15:0]
D3
D2
D3
D0
D1
gpmc_waitj
FA15
FA14
OUT
OUT
DIR
IN
SPRS91v_GPMC_09
图 7-15. GPMC / NOR Flash - Asynchronous Read - Page Mode 4x16-bit Timing(1)(2)(3)(4)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1
(2) FA21 parameter illustrates amount of time required to internally sample first input Page Data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, First input Page Data will be internally sampled
by active functional clock edge. FA21 calculation is detailled in a separated application note and should be stored inside AccessTime
register bits field.
(3) FA20 parameter illustrates amount of time required to internally sample successive input Page Data. It is expressed in number of GPMC
functional clock cycles. After each access to input Page Data, next input Page Data will be internally sampled by active functional clock
edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input Page Data (excluding first
input Page Data). FA20 value should be stored in PageBurstAccessTime register bits field.
(4) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally
(5) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
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gpmc_fclk
gpmc_clk
FA1
gpmc_csi
FA9
gpmc_a[27:1]
Valid Address
FA0
FA10
gpmc_ben0
FA0
FA10
gpmc_ben1
FA3
FA12
gpmc_advn_ale
FA27
FA25
gpmc_wen
FA29
gpmc_ad[15:0]
gpmc_waitj
DIR
Data OUT
OUT
GPMC_10
图 7-16. GPMC / NOR Flash - Asynchronous Write - Single Word Timing(1)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.
(2) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
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Timing Requirements and Switching Characteristics
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GPMC_FCLK
gpmc_clk
FA1
FA5
gpmc_csi
FA9
gpmc_a27
gpmc_a[10:1]
Address (MSB)
FA0
FA10
FA10
gpmc_ben0
gpmc_ben1
Valid
FA0
Valid
FA3
FA12
gpmc_advn_ale
FA4
FA13
gpmc_oen_ren
gpmc_ad[15:0]
FA29
FA37
Data IN
Data IN
Address (LSB)
FA15
FA14
OUT
DIR
OUT
IN
gpmc_waitj
GPMC_11
图 7-17. GPMC / Multiplexed NOR Flash - Asynchronous Read - Single Word Timing(1)(2)(3)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1
(2) FA5 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock
edge. FA5 value should be stored inside AccessTime register bits field.
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally
(4) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
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gpmc_fclk
gpmc_clk
gpmc_csi
FA1
FA9
gpmc_a27
gpmc_a[10:1]
Address (MSB)
FA0
FA10
gpmc_ben0
FA0
FA10
gpmc_ben1
FA3
FA12
gpmc_advn_ale
FA27
FA25
gpmc_wen
gpmc_ad[15:0]
gpmc_waitj
DIR
FA29
Valid Address (LSB)
FA28
Data OUT
OUT
GPMC_12
图 7-18. GPMC / Multiplexed NOR Flash - Asynchronous Write - Single Word Timing(1)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.
(2) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
7.11.3 GPMC/NAND Flash Interface Asynchronous Timing
CAUTION
The I/O Timings provided in this section are valid only for some GPMC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
表 7-30 and 表 7-31 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see 图 7-19, 图 7-20, 图 7-21 and 图 7-22).
表 7-30. GPMC/NAND Flash Interface Timing Requirements
NO.
GNF12
-
PARAMETER
tacc(DAT)
tsu(DV-OEH)
DESCRIPTION
MIN
MAX
J (1)
UNIT
cycles
ns
Data maximum access time (GPMC_FCLK Cycles)
Setup time, read gpmc_ad[15:0] valid before
gpmc_oen_ren high
1.9
1
-
th(OEH-DV)
Hold time, read gpmc_ad[15:0] valid after
gpmc_oen_ren high
ns
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(1) J = AccessTime * (TimeParaGranularity + 1)
表 7-31. GPMC/NAND Flash Interface Switching Characteristics
NO.
PARAMETER
tr(DO)
tf(DO)
DESCRIPTION
Rising time, gpmc_ad[15:0] output data
MIN
0.447
0.43
MAX
4.067
4.463
A (1)
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
Fallling time, gpmc_ad[15:0] output data
GNF0 tw(nWEV)
Pulse duration, gpmc_wen valid time
(2)
(2)
GNF1 td(nCSV-nWEV)
GNF2 td(CLEH-nWEV)
GNF3 td(nWEV-DV)
GNF4 td(nWEIV-DIV)
GNF5 td(nWEIV-CLEIV)
GNF6 td(nWEIV-nCSIV)
GNF7 td(ALEH-nWEV)
GNF8 td(nWEIV-ALEIV)
GNF9 tc(nWE)
Delay time, gpmc_cs[7:0] valid to gpmc_wen valid
Delay time, gpmc_ben[1:0] high to gpmc_wen valid
Delay time, gpmc_ad[15:0] valid to gpmc_wen valid
Delay time, gpmc_wen invalid to gpmc_ad[15:0] invalid
Delay time, gpmc_wen invalid to gpmc_ben[1:0] invalid
Delay time, gpmc_wen invalid to gpmc_cs[7:0] invalid
Delay time, gpmc_advn_ale high to gpmc_wen valid
Delay time, gpmc_wen invalid to gpmc_advn_ale invalid
Cycle time, write cycle time
B - 2
C - 2
D - 2
E - 2
F - 2
G - 2
C - 2
F - 2
B + 4
C + 4
D + 4
E + 4
F + 4
G + 4
C + 4
F + 4
(3)
(4)
(5)
(6)
(7)
(3)
(6)
(3)
(4)
(5)
(6)
(7)
(3)
(6)
(8)
H
(9)
(9)
GNF10 td(nCSV-nOEV)
GNF13 tw(nOEV)
Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren valid
Pulse duration, gpmc_oen_ren valid time
I - 2
I + 4
K (10)
(11)
GNF14 tc(nOE)
Cycle time, read cycle time
L
(12)
(12)
GNF15 td(nOEIV-nCSIV)
Delay time, gpmc_oen_ren invalid to gpmc_cs[7:0] invalid
M - 2
M + 4
(1) A = (WEOffTime - WEOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(2) B = ((WEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - CSExtraDelay)) * GPMC_FCLK
(3) C = ((WEOnTime - ADVOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - ADVExtraDelay)) * GPMC_FCLK
(4) D = (WEOnTime * (TimeParaGranularity + 1) + 0.5 * WEExtraDelay ) * GPMC_FCLK
(5) E = (WrCycleTime - WEOffTime * (TimeParaGranularity + 1) - 0.5 * WEExtraDelay ) * GPMC_FCLK
(6) F = (ADVWrOffTime - WEOffTime * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - WEExtraDelay ) * GPMC_FCLK
(7) G = (CSWrOffTime - WEOffTime * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay - WEExtraDelay ) * GPMC_FCLK
(8) H = WrCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK
(9) I = ((OEOffTime + (n - 1) * PageBurstAccessTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) *
GPMC_FCLK
(10) K = (OEOffTime - OEOnTime) * (1 + TimeParaGranularity) * GPMC_FCLK
(11) L = RdCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK
(12) M = (CSRdOffTime - OEOffTime * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay - OEExtraDelay ) * GPMC_FCLK
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GPMC_FCLK
gpmc_csi
GNF1
GNF2
GNF6
GNF5
gpmc_ben0
gpmc_advn_ale
gpmc_oen_ren
gpmc_wen
GNF0
GNF3
GNF4
Command
gpmc_ad[15:0]
GPMC_13
图 7-19. GPMC / NAND Flash - Command Latch Cycle Timing(1)
(1) In gpmc_csi, i = 0 to 7.
GPMC_FCLK
GNF1
GNF7
GNF6
GNF8
gpmc_csi
gpmc_ben0
gpmc_advn_ale
gpmc_oen_ren
GNF9
GNF0
gpmc_wen
GNF3
GNF4
gpmc_ad[15:0]
Address
GPMC_14
图 7-20. GPMC / NAND Flash - Address Latch Cycle Timing(1)
(1) In gpmc_csi, i = 0 to 7.
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GPMC_FCLK
GNF12
GNF10
GNF15
gpmc_csi
gpmc_ben0
gpmc_advn_ale
GNF14
GNF13
gpmc_oen_ren
gpmc_ad[15:0]
DATA
gpmc_waitj
GPMC_15
图 7-21. GPMC / NAND Flash - Data Read Cycle Timing(1)(2)(3)
(1) GNF12 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional
clock edge. GNF12 value must be stored inside AccessTime register bits field.
(2) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
(3) In gpmc_csi, i = 0 to 7. In gpmc_waitj, j = 0 to 1.
GPMC_FCLK
GNF1
GNF6
gpmc_csi
gpmc_ben0
gpmc_advn_ale
gpmc_oen_ren
GNF9
GNF0
gpmc_wen
GNF3
GNF4
gpmc_ad[15:0]
DATA
GPMC_16
图 7-22. GPMC / NAND Flash - Data Write Cycle Timing(1)
(1) In gpmc_csi, i = 0 to 7.
注
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in 表 4-3 and described in Device TRM, Control
Module Chapter.
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Virtual IO Timings Modes must be used to guaranteed some IO timings for GPMC. See 表 7-2 Modes Summary for a list of IO timings requiring
the use of Virtual IO Timings Modes. See 表 7-32 Virtual Functions Mapping for GPMC for a definition of the Virtual modes.
表 7-32 presents the values for DELAYMODE bitfield.
表 7-32. Virtual Functions Mapping for GPMC
BALL
BALL NAME
Delay Mode Value
GPMC_VIRTUAL1
15
MUXMODE
0
1
2
3
5
6
14(1)
14(1)
N1
gpmc_advn_al
e
gpmc_advn_al
e
gpmc_cs6
gpmc_wait1
gpmc_a2
gpmc_a23
H3
L3
gpmc_ad15
gpmc_ad6
gpmc_ad2
vin2a_d9
13
13
13
9
gpmc_ad15
gpmc_ad6
gpmc_ad2
L5
E6
M3
H2
R3
N7
T2
L6
gpmc_a25
gpmc_wen
gpmc_ad14
gpmc_a13
gpmc_a8
15
13
15
14
15
13
15
13
15
9
gpmc_wen
gpmc_ad14
gpmc_a13
gpmc_a8
gpmc_a14
gpmc_ad4
gpmc_a26
gpmc_ad0
gpmc_wait0
vin2a_d11
gpmc_ad1
gpmc_ad13
gpmc_a2
gpmc_a14
gpmc_ad4
gpmc_a26
gpmc_ad0
gpmc_wait0
H4
M6
N2
F6
M2
J3
gpmc_a20
gpmc_a23
13
13
14
13
9
gpmc_ad1
gpmc_ad13
gpmc_a2
T6
L4
gpmc_ad5
vin2a_d8
gpmc_ad5
F5
T1
G1
P6
N6
R5
U2
J2
gpmc_a26
gpmc_a27
gpmc_cs0
vin2a_hsync0
gpmc_a4
15
9
gpmc_cs0
14
15
14
15
13
gpmc_a4
gpmc_ben0
gpmc_a6
gpmc_ben0
gpmc_a6
gpmc_cs4
gpmc_a15
gpmc_ad11
gpmc_a15
gpmc_ad11
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表 7-32. Virtual Functions Mapping for GPMC (continued)
BALL
BALL NAME
Delay Mode Value
MUXMODE
GPMC_VIRTUAL1
0
1
2
3
5
6
14(1)
14(1)
U1
T9
J4
gpmc_a16
gpmc_a1
15
14
15
15
13
13
13
15
9
gpmc_a16
gpmc_a1
gpmc_a24
gpmc_a23
gpmc_ad8
gpmc_ad10
gpmc_ad12
gpmc_a20
vin2a_d10
gpmc_cs3
gpmc_oen_ren
gpmc_a9
gpmc_a24
gpmc_a23
gpmc_ad8
gpmc_ad10
gpmc_ad12
gpmc_a20
gpmc_a18
gpmc_a17
J7
L1
J1
H1
M7
D3
P1
M5
R4
H6
M1
L2
gpmc_a14
gpmc_a22
gpmc_a24
14
15
14
15
13
13
14
14
15
15
15
15
11
14
15
15
14
15
15
13
15
15
14
gpmc_cs3
gpmc_oen_ren
gpmc_a9
gpmc_a1
gpmc_cs1
gpmc_ad3
gpmc_ad7
gpmc_a7
gpmc_cs1
gpmc_ad3
gpmc_ad7
gpmc_a7
P5
T7
M4
P7
K6
P2
H7
N9
P4
P3
R9
J5
gpmc_a3
gpmc_a3
gpmc_ben1
gpmc_clk
gpmc_ben1
gpmc_clk
gpmc_cs5
gpmc_cs7
gpmc_a3
gpmc_a0
gpmc_wait1
gpmc_a22
gpmc_cs2
vin2a_fld0
gpmc_a10
gpmc_a12
gpmc_a17
gpmc_a5
gpmc_a22
gpmc_cs2
gpmc_a16
gpmc_a27
gpmc_a18
gpmc_a10
gpmc_a12
gpmc_a17
gpmc_a5
gpmc_a21
gpmc_a27
gpmc_ad9
gpmc_a19
gpmc_a25
gpmc_a0
gpmc_a21
gpmc_a27
gpmc_ad9
gpmc_a19
gpmc_a25
gpmc_a0
gpmc_a15
gpmc_a21
H5
K2
K7
J6
gpmc_a13
gpmc_a19
R6
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表 7-32. Virtual Functions Mapping for GPMC (continued)
BALL
BALL NAME
Delay Mode Value
MUXMODE
GPMC_VIRTUAL1
0
1
2
3
5
6
14(1)
14(1)
E1
R2
P9
vin2a_clk0
gpmc_a18
gpmc_a11
11
15
14
gpmc_a27
gpmc_a17
gpmc_a18
gpmc_a11
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(1) Some signals listed are virtual functions that present alternate multiplexing options. These virtual functions are controlled via
CTRL_CORE_ALT_SELECT_MUX or CTRL_CORE_VIP_MUX_SELECT registers. For more information on how to use these options,
please refer to Device TRM, Chapter Control Module, Section Pad Configuration Registers.
7.12 Timers
The device has 16 general-purpose (GP) timers (TIMER1 - TIMER16), two watchdog timers, and a 32-kHz
synchronized timer (COUNTER_32K) that have the following features:
•
Dedicated input trigger for capture mode and dedicated output trigger/pulse width modulation (PWM)
signal
•
•
•
Interrupts generated on overflow, compare, and capture
Free-running 32-bit upward counter
Supported modes:
–
–
–
Compare and capture modes
Auto-reload mode
Start-stop mode
•
On-the-fly read/write register (while counting)
The device has two system watchdog timer (WD_TIMER1 and WD_TIMER2) that have the following
features:
•
•
•
Free-running 32-bit upward counter
On-the-fly read/write register (while counting)
Reset upon occurrence of a timer overflow condition
The device includes one instance of the 32-bit watchdog timer: WD_TIMER2, also called the MPU
watchdog timer.
The watchdog timer is used to provide a recovery mechanism for the device in the event of a fault
condition, such as a non-exiting code loop.
注
For additional information on the Timer Module, see the Device TRM.
7.13 Inter-Integrated Circuit Interface (I2C)
The device includes 6 inter-integrated circuit (I2C) modules which provide an interface to other devices
compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External
components attached to this 2-wire serial bus can transmit/receive 8-bit data to/from the device through
the I2C module.
注
Note that, on I2C1 and I2C2, due to characteristics of the open drain IO cells, HS mode is
not supported.
注
Inter-integrated circuit i (i=1 to 6) module is also referred to as I2Ci.
注
For more information, see the Multimaster High-Speed I2C Controller section of the Device
TRM.
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表 7-33, 表 7-34 and 图 7-23 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
表 7-33. Timing Requirements for I2C Input Timings(1)
STANDARD MODE
FAST MODE
NO.
PARAMETER
DESCRIPTION
UNIT
MIN
MAX
MIN
MAX
1
2
tc(SCL)
Cycle time, SCL
10
2.5
µs
µs
Setup time, SCL high before SDA low (for a
repeated START condition)
tsu(SCLH-SDAL)
4.7
4
0.6
Hold time, SCL low after SDA low (for a START
and a repeated START condition)
3
th(SDAL-SCLL)
0.6
µs
4
5
6
7
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100(2)
0(3)
µs
µs
ns
µs
tw(SCLH)
Pulse duration, SCL high
tsu(SDAV-SCLH)
th(SCLL-SDAV)
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low
250
0(3)
3.45(4)
0.9(4)
Pulse duration, SDA high between STOP and
START conditions
8
tw(SDAH)
tr(SDA)
tr(SCL)
tf(SDA)
tf(SCL)
4.7
1.3
µs
ns
ns
ns
ns
µs
20 + 0.1Cb
9
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
1000
1000
300
300(3)
300(3)
300(3)
300(3)
(5)
20 + 0.1Cb
10
11
12
13
(5)
20 + 0.1Cb
(5)
20 + 0.1Cb
300
(5)
Setup time, SCL high before SDA high (for
STOP condition)
tsu(SCLH-SDAH)
tw(SP)
4
0.6
0
14
15
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
50
ns
(5)
Cb
400
400
pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be
met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns
(according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
(5) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
表 7-34. Timing Requirements for I2C HS-Mode (I2C3/4/5/6 Only)(1)
NO.
PARAMETER
DESCRIPTION
Cb = 100 pF MAX
MIN MAX
Cb = 400 pF (2)
UNIT
MIN MAX
1
2
tc(SCL)
Cycle time, SCL
0.294
160
0.588
160
µs
ns
tsu(SCLH-SDAL)
Set-up time, SCL high before
SDA low (for a repeated START
condition)
3
th(SDAL-SCLL)
Hold time, SCL low after SDA
low (for a repeated START
condition)
160
160
ns
4
5
6
tw(SCLL)
LOW period of the SCLH clock
HIGH period of the SCLH clock
160
60
320
120
10
ns
ns
ns
tw(SCLH)
tsu(SDAV-SCLH)
Setup time, SDA valid vefore
SCL high
10
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表 7-34. Timing Requirements for I2C HS-Mode (I2C3/4/5/6 Only)(1) (continued)
NO.
PARAMETER
DESCRIPTION
Cb = 100 pF MAX
Cb = 400 pF (2)
UNIT
MIN MAX
MIN
MAX
(3)
(3)
7
th(SCLL-SDAV)
tsu(SCLH-SDAH)
tw(SP)
Hold time, SDA valid after SCL
low
0
70
0
150
ns
ns
ns
pF
pF
13
14
15
16
Setup time, SCL high before
SDA high (for a STOP condition)
160
0
160
0
Pulse duration, spike (must be
suppressed)
10
10
(2)
Cb
Capacitive load for SDAH and
SCLH lines
100
400
400
400
Cb
Capacitive load for SDAH + SDA
line and SCLH + SCL line
(1) I2C HS-Mode is only supported on I2C3/4/5/6. I2C HS-Mode is not supported on I2C1/2.
(2) For bus line loads Cb between 100 and 400 pF the timing parameters must be linearly interpolated.
(3) A device must internally provide a Data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH
signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.
9
11
I2Ci_SDA
I2Ci_SCL
6
8
14
4
13
5
10
1
12
3
7
2
3
Stop
Start
Repeated
Start
Stop
SPRS906_TIMING_I2C_01
图 7-23. I2C Receive Timing
表 7-35 and 图 7-24 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
表 7-35. Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings(2)
STANDARD MODE
FAST MODE
NO.
PARAMETER
DESCRIPTION
UNIT
MIN
MAX
MIN
MAX
16
17
tc(SCL)
Cycle time, SCL
10
2.5
µs
µs
Setup time, SCL high before SDA low (for a
repeated START condition)
tsu(SCLH-SDAL)
4.7
4
0.6
Hold time, SCL low after SDA low (for a
START and a repeated START condition)
18
th(SDAL-SCLL)
0.6
µs
19
20
21
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100
µs
µs
ns
tw(SCLH)
Pulse duration, SCL high
tsu(SDAV-SCLH)
Setup time, SDA valid before SCL high
250
Hold time, SDA valid after SCL low (for I2C
bus devices)
22
23
th(SCLL-SDAV)
tw(SDAH)
0
3.45
0
0.9
µs
µs
Pulse duration, SDA high between STOP and
START conditions
4.7
1.3
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表 7-35. Switching Characteristics Over Recommended Operating Conditions for I2C Output
Timings(2) (continued)
STANDARD MODE
FAST MODE
NO.
PARAMETER
DESCRIPTION
UNIT
MIN
MAX
MIN
MAX
20 + 0.1Cb
24
25
26
27
tr(SDA)
tr(SCL)
tf(SDA)
tf(SCL)
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
1000
300(3)
ns
ns
ns
ns
(1) (3)
20 + 0.1Cb
1000
300
300(3)
300(3)
300(3)
(1) (3)
20 + 0.1Cb
(1) (3)
20 + 0.1Cb
300
(1) (3)
Setup time, SCL high before SDA high (for
STOP condition)
28
29
tsu(SCLH-SDAH)
Cp
4
0.6
µs
pF
Capacitance for each I2C pin
10
10
(1) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
(2) Software must properly configure the I2C module registers to achieve the timings shown in this table. See the Device TRM for details.
(3) These timings apply only to I2C1 and I2C2. I2C3, I2C4, I2C5 and I2C6 use standard LVCMOS buffers to emulate open-drain buffers
and their rise/fall times should be referenced in the device IBIS model.
注
I2C emulation is achieved by configuring the LVCMOS buffers to output Hi-Z instead of
driving high when transmitting logic-1.
26
24
I2Ci_SDA
I2Ci_SCL
21
23
19
28
20
25
27
16
18
22
17
18
Stop
Start
Repeated
Start
Stop
SPRS906_TIMING_I2C_02
图 7-24. I2C Transmit Timing
7.14 Universal Asynchronous Receiver Transmitter (UART)
The UART performs serial-to-parallel conversions on data received from a peripheral device and parallel-
to-serial conversion on data received from the CPU. There are 10 UART modules in the device. Only one
UART supports IrDA features. Each UART can be used for configuration and data exchange with a
number of external peripheral devices or interprocessor communication between devices
The UARTi (where i = 1 to 10) include the following features:
•
•
•
16C750 compatibility
64-byte FIFO buffer for receiver and 64-byte FIFO for transmitter
Baud generation based on programmable divisors N (where N = 1…16 384) operating from a fixed
functional clock of 48 MHz or 192 MHz
•
Break character detection and generation
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•
Configurable data format:
–
–
–
Data bit: 5, 6, 7, or 8 bits
Parity bit: Even, odd, none
Stop-bit: 1, 1.5, 2 bit(s)
•
•
•
Flow control: Hardware (RTS/CTS) or software (XON/XOFF)
Only UART1 module has extended modem control signals (CD, RI, DTR, DSR)
Only UART3 supports IrDA
注
For more information, see the UART section of the Device TRM.
表 7-36, 表 7-37 and 图 7-25 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
表 7-36. Timing Requirements for UART
NO.
4
PARAMETER
DESCRIPTION
MIN
0.96U(1)
0.96U(1)
P(2)
MAX
UNIT
ns
tw(RX)
Pulse width, receive data bit, 15/30/100pF high or low
Pulse width, receive start bit, 15/30/100pF high or low
Delay time, transmit start bit to transmit data
Delay time, receive start bit to transmit data
1.05U(1)
1.05U(1)
5
tw(CTS)
ns
td(RTS-TX)
td(CTS-TX)
ns
P(2)
ns
(1) U = UART baud time = 1/programmed baud rate
(2) P = Clock period of the reference clock (FCLK, usually 48 MHz or 192MHz).
表 7-37. Switching Characteristics Over Recommended Operating Conditions for UART
NO.
PARAMETER
DESCRIPTION
MIN
MAX
12
UNIT
15 pF
30 pF
100 pF
f(baud)
Maximum programmable baud rate
0.23
MHz
0.115
U + 2(1)
U + 2(1)
2
3
tw(TX)
Pulse width, transmit data bit, 15/30/100 pF high or low
Pulse width, transmit start bit, 15/30/100 pF high or low
U - 2(1)
U - 2(1)
ns
ns
tw(RTS)
(1) U = UART baud time = 1/programmed baud rate
3
2
Start
Bit
UARTi_TXD
Data Bits
5
4
Start
Bit
UARTi_RXD
Data Bits
SPRS906_TIMING_UART_01
图 7-25. UART Timing
7.15 Multichannel Serial Peripheral Interface (McSPI)
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The McSPI is a master/slave synchronous serial bus. There are four separate McSPI modules (SPI1,
SPI2, SPI3, and SPI4) in the device. All these four modules support up to four external devices (four chip
selects) and are able to work as both master and slave.
The McSPI modules include the following main features:
•
•
•
•
Serial clock with programmable frequency, polarity, and phase for each channel
Wide selection of SPI word lengths, ranging from 4 to 32 bits
Up to four master channels, or single channel in slave mode
Master multichannel mode:
–
–
–
–
–
Full duplex/half duplex
Transmit-only/receive-only/transmit-and-receive modes
Flexible input/output (I/O) port controls per channel
Programmable clock granularity
SPI configuration per channel. This means, clock definition, polarity enabling and word width
•
•
•
•
Power management through wake-up capabilities
Programmable timing control between chip select and external clock generation
Built-in FIFO available for a single channel.
Each SPI module supports multiple chip select pins spim_cs[i], where i = 1 to 4.
注
For more information, see the Serial Communication Interface section of the device TRM.
注
The McSPIm module (m = 1 to 4) is also referred to as SPIm.
CAUTION
The I/O timings provided in this section are applicable for all combinations of
signals for SPI1 and SPI2. However, the timings are valid only for SPI3 and
SPI4 if signals within a single IOSET are used. The IOSETS are defined in 表
7-40.
表 7-38, 图 7-26 and 图 7-27 present Timing Requirements for McSPI - Master Mode.
表 7-38. Timing Requirements for SPI - Master Mode (1)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
SM1
tc(SPICLK)
Cycle time, spi_sclk (1) (2)
SPI1/2/3/ 20.8 (3)
4
ns
SM2
SM3
tw(SPICLKL)
tw(SPICLKH)
Typical Pulse duration, spi_sclk low (1)
Typical Pulse duration, spi_sclk high (1)
0.5*P-1
ns
ns
(4)
0.5*P-1
(4)
SM4
SM5
SM6
tsu(MISO-SPICLK)
th(SPICLK-MISO)
td(SPICLK-SIMO)
Setup time, spi_d[x] valid before spi_sclk active edge (1)
Hold time, spi_d[x] valid after spi_sclk active edge (1)
Delay time, spi_sclk active edge to spi_d[x] transition (1)
3.5
3.7
ns
ns
ns
ns
ns
ns
SPI1
SPI2
SPI3
SPI4
-3.57
-3.9
-4.9
-4.3
4.1
3.6
4.7
4.5
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表 7-38. Timing Requirements for SPI - Master Mode (1) (continued)
NO.
SM7
SM8
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
ns
td(CS-SIMO)
Delay time, spi_cs[x] active edge to spi_d[x] transition
Delay time, spi_cs[x] active to spi_sclk first edge (1)
5
td(CS-SPICLK)
MASTER B-4.2 (6)
ns
_PHA0
(5)
MASTER A-4.2 (7)
ns
ns
ns
_PHA1
(5)
SM9
td(SPICLK-CS)
Delay time, spi_sclk last edge to spi_cs[x] inactive (1)
MASTER A-4.2 (7)
_PHA0
(5)
MASTER B-4.2 (6)
_PHA1
(5)
(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture
input data.
(2) Related to the SPI_CLK maximum frequency.
(3) 20.8ns cycle time = 48MHz
(4) P = SPICLK period.
(5) SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
(6) B = (TCS + 0.5) * TSPICLKREF * Fratio, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even ≥2.
(7) When P = 20.8 ns, A = (TCS + 1) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8 ns, A = (TCS
+ 0.5) * Fratio * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.
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PHA=0
EPOL=1
spim_cs(OUT)
SM1
SM3
SM8
SM2
SM9
POL=0
spim_sclk(OUT)
SM1
SM3
SM2
POL=1
spim_sclk(OUT)
SM7
Bit n-1
SM6
Bit n-2
SM6
Bit n-3
Bit n-4
Bit 0
spim_d(OUT)
PHA=1
EPOL=1
spim_cs(OUT)
SM1
SM2
SM8
SM3
SM2
SM9
POL=0
spim_sclk(OUT)
SM1
SM3
POL=1
spim_sclk(OUT)
SM6
Bit n-1
SM6
Bit n-2
SM6
Bit n-3
SM6
Bit 1
Bit0
spim_d(OUT)
SPRS906_TIMING_McSPI_01
图 7-26. McSPI - Master Mode Transmit
248
Timing Requirements and Switching Characteristics
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PHA=0
EPOL=1
spim_cs(OUT)
SM1
SM3
SM8
SM2
SM9
POL=0
POL=1
spim_sclk(OUT)
SM1
SM3
SM2
spim_sclk(OUT)
SM5
SM5
SM4
SM4
Bit n-1
Bit n-2
Bit n-3
Bit n-4
Bit 0
spim_d(IN)
PHA=1
EPOL=1
spim_cs(OUT)
SM2
SM1
SM8
SM3
SM2
SM9
POL=0
POL=1
spim_sclk(OUT)
SM1
SM3
spim_sclk(OUT)
SM5
SM4
SM5
SM4
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
spim_d(IN)
SPRS906_TIMING_McSPI_02
图 7-27. McSPI - Master Mode Receive
表 7-39, 图 7-28 and 图 7-29 present Timing Requirements for McSPI - Slave Mode.
表 7-39. Timing Requirements for SPI - Slave Mode
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
SS1 (1) tc(SPICLK)
Cycle time, spi_sclk
62.5 (2)
ns
(3)
SS2 (1) tw(SPICLKL)
SS3 (1) tw(SPICLKH)
SS4 (1) tsu(SIMO-SPICLK)
SS5 (1) th(SPICLK-SIMO)
SS6 (1) td(SPICLK-SOMI)
Typical Pulse duration, spi_sclk low
0.45*P (4)
0.45*P (4)
ns
ns
ns
ns
ns
ns
ns
Typical Pulse duration, spi_sclk high
Setup time, spi_d[x] valid before spi_sclk active edge
Hold time, spi_d[x] valid after spi_sclk active edge
Delay time, spi_sclk active edge to mcspi_somi transition
5
5
2
2
SPI1/2/3
SPI4
26.6
20.1
SS7 (5) td(CS-SOMI)
Delay time, spi_cs[x] active edge to mcspi_somi transition
20.95
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表 7-39. Timing Requirements for SPI - Slave Mode (continued)
NO.
SS8 (1) tsu(CS-SPICLK)
SS9 (1) th(SPICLK-CS)
PARAMETER
DESCRIPTION
MODE
MIN
5
MAX
UNIT
ns
Setup time, spi_cs[x] valid before spi_sclk first edge
Hold time, spi_cs[x] valid after spi_sclk last edge
SPI1/2
SPI3
5
ns
7.5
6
ns
SPI4
ns
(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture
input data.
(2) When operating the SPI interface in RX-only mode, the minimum Cycle time is 26ns (38.4MHz)
(3) 62.5ns Cycle time = 16 MHz
(4) P = SPICLK period.
(5) PHA = 0; SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
PHA=0
EPOL=1
spim_cs(IN)
SS1
SS2
SS8
SS3
SS3
SS9
POL=0
POL=1
spim_sclk(IN)
SS1
SS2
spim_sclk(IN)
spim_d(OUT)
SS7
Bit n-1
SS6
Bit n-2
SS6
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
spim_cs(IN)
spim_sclk(IN)
SS1
SS2
SS8
SS3
SS2
SS9
POL=0
POL=1
SS1
SS3
spim_sclk(IN)
spim_d(OUT)
SS6
Bit n-1
SS6
Bit n-2
SS6
Bit n-3
SS6
Bit 1
Bit 0
SPRS906_TIMING_McSPI_03
图 7-28. McSPI - Slave Mode Transmit
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PHA=0
EPOL=1
spim_cs(IN)
SS1
SS2
SS8
SS3
SS3
SS9
POL=0
POL=1
spim_sclk(IN)
SS1
SS2
spim_sclk(IN)
SS5
SS4
SS5
Bit n-2
SS4
Bit n-1
Bit n-3
Bit n-4
Bit 0
spim_d(IN)
PHA=1
EPOL=1
spim_cs(IN)
SS1
SS2
SS8
SS3
SS2
SS9
POL=0
POL=1
spim_sclk(IN)
spim_sclk(IN)
SS1
SS3
SS4
SS5
SS4
SS5
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
spim_d(IN)
SPRS906_TIMING_McSPI_04
图 7-29. McSPI - Slave Mode Receive
In 表 7-40 are presented the specific groupings of signals (IOSET) for use with SPI3 and SPI4.
表 7-40. McSPI3/4 IOSETs
SIGNALS
IOSET1
BALL
IOSET2
BALL
IOSET3
BALL
IOSET4
BALL
IOSET5
MUX
MUX
MUX
MUX
BALL
MUX
McSPI3
A12
spi3_cs0
spi3_cs1
spi3_cs2
spi3_cs3
spi3_d0
D11
B11
F11
A10
C11
B10
E11
8
8
8
8
8
8
8
V9
7
1
3
3
8
8
3
3
3
D17
B11
F11
A10
G16
A21
C18
2
8
8
8
2
2
2
AC9
AC3
1
1
AC3
E14
F11
A10
W9
Y1
V2
7
7
7
B13
AC6
AC7
AC4
1
1
1
spi3_d1
A11
spi3_sclk
B12
McSPI4
U6
spi4_cs0
P9
8
F3
8
7
AA4
2
AB5
1
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表 7-40. McSPI3/4 IOSETs (continued)
SIGNALS
IOSET1
BALL
IOSET2
BALL
IOSET3
BALL
IOSET4
BALL
IOSET5
BALL
MUX
MUX
MUX
MUX
MUX
spi4_cs1
spi4_cs2
spi4_cs3
spi4_d0
spi4_d1
spi4_sclk
P4
R3
T2
N9
R4
N7
8
8
8
8
8
8
P4
R3
T2
F2
G6
G1
8
8
8
8
8
8
Y1
W9
V9
V6
U7
V7
8
8
8
7
7
7
Y1
W9
8
8
8
2
2
2
Y1
W9
8
8
8
1
1
1
V9
V9
AB3
AB9
AA3
AB8
AD6
AC8
7.16 Quad Serial Peripheral Interface (QSPI)
The Quad SPI (QSPI) module is a type of SPI module that allows single, dual or quad read access to
external SPI devices. This module has a memory mapped register interface, which provides a direct
interface for accessing data from external SPI devices and thus simplifying software requirements. It
works as a master only. There is one QSPI module in the device and it is primary intended for fast
booting from quad-SPI flash memories.
General SPI features:
•
•
•
•
•
•
•
•
Programmable clock divider
Six pin interface (DCLK, CS_N, DOUT, DIN, QDIN1, QDIN2)
4 external chip select signals
Support for 3-, 4- or 6-pin SPI interface
Programmable CS_N to DOUT delay from 0 to 3 DCLKs
Programmable signal polarities
Programmable active clock edge
Software controllable interface allowing for any type of SPI transfer
注
For more information, see the Quad Serial Peripheral Interface section of the Device TRM.
CAUTION
The I/O Timings provided in this section are only valid when all QSPI Chip
Selects used in a system are configured to use the same Clock Mode (either
Clock Mode 0 or Clock Mode 3).
CAUTION
The I/O Timings provided in this section are valid only for some QSPI usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
表 7-41 and 表 7-42 Present Timing and Switching Characteristics for Quad SPI Interface.
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表 7-41. Switching Characteristics for QSPI
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
Q1
tc(SCLK)
Cycle time, sclk
Default Timing Mode,
Clock Mode 0
11.71
ns
Default Timing Mode,
Clock Mode 3
20.8
ns
ns
ns
ns
Q2
Q3
Q4
tw(SCLKL)
tw(SCLKH)
td(CS-SCLK)
Pulse duration, sclk low
Y*P-1
(1)
Pulse duration, sclk high
Y*P-1
(1)
Delay time, sclk falling edge to cs active edge, CS3:0
Default Timing Mode
-M*P-
-
1.6 (2) M*P+2.
(3)
6 (2) (3)
Q5
td(SCLK-CS)
Delay time, sclk falling edge to cs inactive edge,
CS3:0
Default Timing Mode
Default Timing Mode
N*P-1.6 N*P+2.
ns
(2) (3)
6 (2) (3)
Q6
Q7
Q8
Q9
td(SCLK-D0)
tena(CS-D0LZ)
tdis(CS-D0Z)
td(SCLK-D0)
Delay time, sclk falling edge to d[0] transition
Enable time, cs active edge to d[0] driven (lo-z)
Disable time, cs active edge to d[0] tri-stated (hi-z)
Delay time, sclk first falling edge to first d[0] transition
-1.6
2.6
ns
ns
ns
ns
-P-3.5
-P-2.5
-P+2.5
-P+2.0
PHA=0 Only, Default
Timing Mode
-1.6 -
P(2)
2.6 -
P(2)
(1) The Y parameter is defined as follows:
If DCLK_DIV is 0 or ODD then, Y equals 0.5.
If DCLK_DIV is EVEN then, Y equals (DCLK_DIV/2) / (DCLK_DIV+1).
For best performance, it is recommended to use a DCLK_DIV of 0 or ODD to minimize the duty cycle distortion. The HSDIVIDER on
CLKOUTX2_H13 output of DPLL_PER can be used to achieve the desired clock divider ratio. All required details about clock division
factor DCLK_DIV can be found in the device-specific Technical Reference Manual.
(2) P = SCLK period.
(3) M=QSPI_SPI_DC_REG.DDx + 1 when Clock Mode 0.
M=QSPI_SPI_DC_REG.DDx when Clock Mode 3.
N = 2 when Clock Mode 0.
N = 3 when Clock Mode 3.
cs
Q5
Q1
PHA=1
POL=1
Q4
Q3
Q2
sclk
Q15
Q14
Q12
Q6
Q13
Read Data
Bit 1
Q6
Q7
Command
Bit n-1
Command
Bit n-2
Read Data
Bit 0
d[0]
Q15
Q14
Q12 Q13
Read Data
Bit 1
Read Data
Bit 0
d[3:1]
SPRS85v_TIMING_OSPI1_01
图 7-30. QSPI Read (Clock Mode 3)
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cs
Q5
Q4
Q1
PHA=0
POL=0
Q2
Q3
sclk
POL=0
rtclk
Q12
Q13
Q12 Q13
Read Data
Bit 0
Q6
Q7
Q9
Command
Bit n-1
Command
Bit n-2
Read Data
Bit 1
d[0]
Q12 Q13
Read Data
Bit 1
Q12 Q13
Read Data
Bit 0
d[3:1]
SPRS85v_TIMING_OSPI1_02
图 7-31. QSPI Read (Clock Mode 0)
CAUTION
The I/O Timings provided in this section are valid only for some QSPI usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
表 7-42. Timing Requirements for QSPI(3)(2)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
Q2
tsu(D-RTCLK)
Setup time, d[3:0] valid before falling rtclk edge
Default Timing Mode,
Clock Mode 0
4.6
ns
tsu(D-SCLK)
th(RTCLK-D)
th(SCLK-D)
tsu(D-SCLK)
th(SCLK-D)
Setup time, d[3:0] valid before falling sclk edge
Hold time, d[3:0] valid after falling rtclk edge
Hold time, d[3:0] valid after falling sclk edge
Default Timing Mode,
Clock Mode 3
12.3
-0.1
0.1
ns
ns
ns
ns
ns
Q13
Default Timing Mode,
Clock Mode 0
Default Timing Mode,
Clock Mode 3
Q14
Q15
Setup time, final d[3:0] bit valid before final falling sclk
edge
Default Timing Mode,
Clock Mode 3
12.3-P
(1)
Hold time, final d[3:0] bit valid after final falling sclk
edge
Default Timing Mode,
Clock Mode 3
0.1+P
(1)
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(1) P = SCLK period.
(2) Clock Modes 1 and 2 are not supported.
(3) The Device captures data on the falling clock edge in Clock Mode 0 and 3, as opposed to the traditional rising clock edge. Although
non-standard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI devices that
launch data on the falling edge in Clock Modes 0 and 3.
cs
Q5
Q1
PHA=1
POL=1
Q4
Q3
Q2
sclk
Q8
Q6
Q6
Q6
Q6
Q7
Command
Bit n-1
Command
Bit n-2
Write Data
Bit 1
Write Data
Bit 0
d[0]
d[3:1]
SPRS85v_TIMING_OSPI1_03
图 7-32. QSPI Write (Clock Mode 3)
cs
Q5
Q4
Q1
PHA=0
POL=0
Q2
Q3
sclk
Q8
Q6
Q6
Q7
Q9
Q6
Command
Bit n-1
Command
Bit n-2
Write Data
Bit 1
Write Data
Bit 0
d[0]
d[3:1]
SPRS85v_TIMING_OSPI1_04
图 7-33. QSPI Write (Clock Mode 0)
CAUTION
The I/O Timings provided in this section are valid only for some QSPI usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
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注
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section Manual IO Timing Modes of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information see the Control Module chapter in the Device TRM.
Manual IO Timings Modes must be used to guaranteed some IO timings for QSPI. See 表 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See 表 7-43 Manual
Functions Mapping for QSPI for a definition of the Manual modes.
表 7-43 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
表 7-43. Manual Functions Mapping for QSPI
BALL
BALL NAME
QSPI1_MANUAL1
CFG REGISTER
MUXMODE
1
A_DELAY (ps)
G_DELAY (ps)
T7
P6
R3
T2
U2
U1
U1
P3
R2
P2
P1
gpmc_a3
gpmc_a4
0
0
0
0
CFG_GPMC_A3_OUT
CFG_GPMC_A4_OUT
CFG_GPMC_A13_IN
CFG_GPMC_A14_IN
CFG_GPMC_A15_IN
CFG_GPMC_A16_IN
CFG_GPMC_A16_OUT
CFG_GPMC_A17_IN
CFG_GPMC_A18_OUT
CFG_GPMC_CS2_OUT
CFG_GPMC_CS3_OUT
qspi1_cs2
qspi1_cs3
qspi1_rtclk
qspi1_d3
qspi1_d2
qspi1_d0
qspi1_d0
qspi1_d1
qspi1_sclk
qspi1_cs0
qspi1_cs1
gpmc_a13
gpmc_a14
gpmc_a15
gpmc_a16
gpmc_a16
gpmc_a17
gpmc_a18
gpmc_cs2
gpmc_cs3
0
0
2247
2176
2229
0
1186
1197
1268
0
2251
0
1217
0
0
0
0
0
7.17 Multichannel Audio Serial Port (McASP)
The multichannel audio serial port (McASP) functions as a general-purpose audio serial port optimized for
the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM)
stream, Inter-Integrated Sound (I2S) protocols, and intercomponent digital audio interface transmission
(DIT).
The device have integrated 8 McASP modules (McASP1-McASP8) with:
•
•
McASP1 and McASP2 modules supporting 16 channels with independent TX/RX clock/sync domain
McASP3 through McASP8 modules supporting 4 channels with independent TX/RX clock/sync domain
注
For more information, see the Serial Communication Interface section of the Device TRM.
CAUTION
The I/O Timings provided in this section are valid only for some McASP usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
表 7-44, 表 7-45, 表 7-46 and 图 7-34 present Timing Requirements for McASP1 to 8
.
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表 7-44. Timing Requirements for McASP1(1)
NO.
1
PARAMETER
DESCRIPTION
MODE
MIN
20
0.35P (2)
MAX
UNIT
ns
tc(AHCLKX)
tw(AHCLKX)
tc(ACLKRX)
tw(ACLKRX)
Cycle time, AHCLKX
2
Pulse duration, AHCLKX high or low
Cycle time, ACLKR/X
ns
3
20
ns
4
Pulse duration, ACLKR/X high or low
0.5R - 3
ns
(3)
5
6
7
8
tsu(AFSRX-ACLK)
th(ACLK-AFSRX)
tsu(AXR-ACLK)
th(ACLK-AXR)
Setup time, AFSR/X input valid before ACLKR/X
Hold time, AFSR/X input valid after ACLKR/X
Setup time, AXR input valid before ACLKR/X
Hold time, AXR input valid after ACLKR/X
ACLKR/X int
20.5
4
ns
ns
ACLKR/X ext
in
ACLKR/X ext
out
ACLKR/X int
-1
ns
ns
ACLKR/X ext
1.7
in
ACLKR/X ext
out
ACLKR/X int
21.6
11.5
ns
ns
ACLKR/X ext
in
ACLKR/X ext
out
ACLKR/X int
-1
ns
ns
ACLKR/X ext
1.8
in
ACLKR/X ext
out
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKX period in ns.
(3) R = ACLKR/X period in ns.
表 7-45. Timing Requirements for McASP2(1)
NO.
1
PARAMETER
tc(AHCLKX)
DESCRIPTION
MODE
MIN
MAX
UNIT
ns
Cycle time, AHCLKX
20
2
tw(AHCLKX)
Pulse duration, AHCLKX high or low
0.35P
ns
(2)
3
tc(ACLKRX)
Cycle time, ACLKR/X
Any Other Conditions
20
ns
ns
ACLKX/AFSX (In Sync Mode),
ACLKR/AFSR (In Async Mode),
and AXR are all inputs "80M"
Virtual IO Timing Modes
12.5
4
tw(ACLKRX)
Pulse duration, ACLKR/X high or low
Any Other Conditions
0.5R - 3
ns
ns
(3)
ACLKX/AFSX (In Sync Mode),
ACLKR/AFSR (In Async Mode),
and AXR are all inputs "80M"
Virtual IO Timing Modes
0.38R
(3)
5
tsu(AFSRX-ACLK)
Setup time, AFSR/X input valid before
ACLKR/X
ACLKR/X int
20.3
4.5
ns
ns
ACLKR/X ext in
ACLKR/X ext out
ACLKR/X ext in
ACLKR/X ext out "80M" Virtual
IO Timing Modes
3
ns
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表 7-45. Timing Requirements for McASP2(1) (continued)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
-1
MAX
UNIT
ns
6
th(ACLK-AFSRX)
Hold time, AFSR/X input valid after ACLKR/X
ACLKR/X int
ACLKR/X ext in
ACLKR/X ext out
1.8
ns
ACLKR/X ext in
ACLKR/X ext out "80M" Virtual
IO Timing Modes
3
ns
7
8
tsu(AXR-ACLK)
Setup time, AXR input valid before ACLKR/X
Hold time, AXR input valid after ACLKR/X
ACLKR/X int
21.1
4.5
ns
ns
ACLKR/X ext in
ACLKR/X ext out
ACLKR/X ext in
ACLKR/X ext out "80M" Virtual
IO Timing Modes
3
ns
th(ACLK-AXR)
ACLKR/X int
-1
ns
ns
ACLKR/X ext in
ACLKR/X ext out
1.8
ACLKR/X ext in
ACLKR/X ext out "80M" Virtual
IO Timing Modes
3
ns
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKX period in ns.
(3) R = ACLKR/X period in ns.
表 7-46. Timing Requirements for McASP3/4/5/6/7/8(1)
NO.
1
PARAMETER
tc(AHCLKX)
DESCRIPTION
MODE
MIN
MAX
UNIT
ns
Cycle time, AHCLKX
20
2
tw(AHCLKX)
Pulse duration, AHCLKX high or low
0.35P
ns
(2)
3
4
tc(ACLKRX)
tw(ACLKRX)
Cycle time, ACLKR/X
20
ns
ns
Pulse duration, ACLKR/X high or low
0.5R - 3
(3)
5
6
tsu(AFSRX-ACLK)
th(ACLK-AFSRX)
tsu(AXR-ACLK)
Setup time, AFSR/X input valid before ACLKR/X
Hold time, AFSR/X input valid after ACLKR/X
Setup time, AXR input valid before ACLKX
ACLKR/X int
19.7
5.6
ns
ns
ACLKR/X ext in
ACLKR/X ext out
ACLKR/X int
-1.1
2.5
ns
ns
ACLKR/X ext in
ACLKR/X ext out
ACLKX int
(ASYNC=0)
20.3
5.1
ns
ns
ns
ns
ACLKR/X ext in
ACLKR/X ext out
8
th(ACLK-AXR)
Hold time, AXR input valid after ACLKX
ACLKX int
(ASYNC=0)
-0.8
2.5
ACLKR/X ext in
ACLKR/X ext out
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1 (NOT SUPPORTED)
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKX period in ns.
258
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(3) R = ACLKR/X period in ns.
2
1
2
AHCLKX (Falling Edge Polarity)
AHCLKX (Rising Edge Polarity)
4
3
4
(A)
(B)
ACLKR/X (CLKRP = CLKXP = 0)
ACLKR/X (CLKRP = CLKXP = 1)
6
5
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
8
7
AXR[n] (Data In/Receive)
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
SPRS906_TIMING_McASP_01
A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
图 7-34. McASP Input Timing
表 7-47, 表 7-48, 表 7-49 and 图 7-35 present Switching Characteristics Over Recommended Operating
Conditions for McASP1 to 8.
表 7-47. Switching Characteristics Over Recommended Operating Conditions for McASP1(1)
NO.
9
PARAMETER
tc(AHCLKX)
DESCRIPTION
MODE
MIN
MAX
UNIT
ns
Cycle time, AHCLKX
20
10
tw(AHCLKX)
Pulse duration, AHCLKX high or low
0.5P -
2.5 (2)
ns
11
tc(ACLKRX)
Cycle time, ACLKR/X
20
ns
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表 7-47. Switching Characteristics Over Recommended Operating Conditions for McASP1(1) (continued)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
12
tw(ACLKRX)
Pulse duration, ACLKR/X high or low
0.5P -
2.5 (3)
ns
13
14
td(ACLK-AFSXR)
Delay time, ACLKR/X transmit edge to AFSX/R output valid
Delay time, ACLKR/X transmit edge to AXR output valid
ACLKR/X int
-0.9
2
6
ns
ns
ACLKR/X ext in
ACLKR/X ext out
23.1
td(ACLK-AXR)
ACLKR/X int
-1.4
2
6
ns
ns
ACLKR/X ext in
ACLKR/X ext out
24.2
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKX period in ns.
(3) R = ACLKR/X period in ns.
表 7-48. Switching Characteristics Over Recommended Operating Conditions for McASP2 (1)
NO.
9
PARAMETER
tc(AHCLKX)
DESCRIPTION
MODE
MIN
MAX
UNIT
ns
Cycle time, AHCLKX
20
10
tw(AHCLKX)
Pulse duration, AHCLKX high or low
0.5P -
2.5 (2)
ns
11
12
tc(ACLKRX)
tw(ACLKRX)
Cycle time, ACLKR/X
20
ns
ns
Pulse duration, ACLKR/X high or low
0.5P -
2.5 (3)
13
14
td(ACLK-AFSXR)
Delay time, ACLKR/X transmit edge to AFSX/R output valid
Delay time, ACLKR/X transmit edge to AXR output valid
ACLKR/X int
-1
2
6
ns
ns
ACLKR/X ext in
ACLKR/X ext out
23.2
td(ACLK-AXR)
ACLKR/X int
-1.3
2
6
ns
ns
ACLKR/X ext in
ACLKR/X ext out
23.7
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKX period in ns.
(3) R = ACLKR/X period in ns.
表 7-49. Switching Characteristics Over Recommended Operating Conditions for
McASP3/4/5/6/7/8(1)
NO.
9
PARAMETER
tc(AHCLKX)
DESCRIPTION
MODE
MIN
MAX
UNIT
ns
Cycle time, AHCLKX
20
10
tw(AHCLKX)
Pulse duration, AHCLKX high or low
0.5P -
2.5 (2)
ns
11
12
tc(ACLKRX)
tw(ACLKRX)
Cycle time, ACLKR/X
20
ns
ns
Pulse duration, ACLKR/X high or low
0.5P -
2.5 (3)
13
td(ACLK-AFSXR)
Delay time, ACLKR/X transmit edge to AFSX/R output valid
ACLKR/X int
-0.5
1.9
6
ns
ns
ACLKR/X ext in
ACLKR/X ext out
24.5
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Timing Requirements and Switching Characteristics
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表 7-49. Switching Characteristics Over Recommended Operating Conditions for
McASP3/4/5/6/7/8(1) (continued)
NO.
PARAMETER
td(ACLK-AXR)
DESCRIPTION
Delay time, ACLKR/X transmit edge to AXR output valid
MODE
MIN
-1.4
1.1
MAX
7.1
UNIT
ns
14
ACLKR/X int
ACLKR/X ext in
ACLKR/X ext out
24.2
ns
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKX period in ns.
(3) R = ACLKR/X period in ns.
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10
10
9
AHCLKX (Falling Edge Polarity)
AHCLKX (Rising Edge Polarity)
12
11
12
(A)
ACLKR/X (CLKRP = CLKXP = 1)
(B)
ACLKR/X (CLKRP = CLKXP = 0)
13
13
13
13
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
AXR[n] (Data Out/T ransmit)
13
13
13
14
15
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
SPRS906_TIMING_McASP_02
A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
图 7-35. McASP Output Timing
表 7-50 through 表 7-57 explain all cases with Virtual Mode Details for McASP1/2/3/4/5/6/7/8 (see 图 7-36
through 图 7-43).
表 7-50. Virtual Mode Case Details for McASP1
No.
CASE
CASE Description
Virtual Mode Settings
Notes
Signals
IP Mode : ASYNC
Virtual Mode Value
1
COIFOI
CLKX / FSX: Output
CLKR / FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
See 图 7-36
MCASP1_VIRTUAL2_ASYNC_RX
262
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表 7-50. Virtual Mode Case Details for McASP1 (continued)
No.
2
CASE
COIFIO
CIOFIO
CIOFOI
CASE Description
Virtual Mode Settings
Notes
Signals
Virtual Mode Value
Default (No Virtual Mode)
CLKX / FSR: Output
CLKR / FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
See 图 7-37
See 图 7-38
See 图 7-39
MCASP1_VIRTUAL2_ASYNC_RX
MCASP1_VIRTUAL2_ASYNC_RX
Default (No Virtual Mode)
3
CLKR / FSR: Output
CLKX / FSX: Input
4
CLKR / FSX: Output
CLKX / FSR: Input
MCASP1_VIRTUAL2_ASYNC_RX
Default (No Virtual Mode)
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
6
7
8
CO-FO-
CI-FO-
CI-FI-
CLKX / FSX: Output
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
Default (No Virtual Mode)
See 图 7-40
See 图 7-41
See 图 7-42
See 图 7-43
FSX: Output CLKX:
Input
MCASP1_VIRTUAL1_SYNC_RX
MCASP1_VIRTUAL1_SYNC_RX
MCASP1_VIRTUAL1_SYNC_RX
MCASP1_VIRTUAL1_SYNC_RX
Default (No Virtual Mode)
CLKX / FSX: Input
CO-FI-
CLKX: Output FSX:
Input
Default (No Virtual Mode)
表 7-51. Virtual Mode Case Details for McASP2
No.
CASE
CASE
Virtual Mode Settings
Notes
Description
Signals
IP Mode : ASYNC
Virtual Mode Value
1
COIFOI
CLKX / FSX:
Output CLKR /
FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
AXR(Inputs)/CLKR/FSR
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)(1)
Default (No Virtual Mode)(1)
MCASP2_VIRTUAL4_ASYNC_RX_80M (2)
See 图 7-36
2
3
4
COIFIO
CIOFIO
CIOFOI
CLKX / FSR:
Output CLKR /
FSX: Input
Default (No Virtual Mode)
See 图 7-37
See 图 7-38
See 图 7-39
MCASP2_VIRTUAL2_ASYNC_RX
CLKR / FSR:
Output CLKX /
FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP2_VIRTUAL2_ASYNC_RX
Default (No Virtual Mode)
CLKR / FSX:
Output CLKX /
FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP2_VIRTUAL2_ASYNC_RX
Default (No Virtual Mode)
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
6
7
CO-FO-
CI-FO-
CI-FI-
CLKX / FSX:
Output
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
Default (No Virtual Mode)
See 图 7-40
See 图 7-41
See 图 7-42
FSX: Output
CLKX: Input
MCASP2_VIRTUAL3_SYNC_RX
MCASP2_VIRTUAL3_SYNC_RX
MCASP2_VIRTUAL3_SYNC_RX(1)
MCASP2_VIRTUAL3_SYNC_RX(1)
MCASP2_VIRTUAL1_SYNC_RX_80M(2)
Default (No Virtual Mode)
CLKX / FSX:
Input
8
CO-FI-
CLKX: Output
FSX: Input
See 图 7-43
Default (No Virtual Mode)
(1) Used up to 50MHz. Should also be used in a CI-FI- mixed case where AXR operate as both inputs and outputs (that is, AXR are
bidirectional).
(2) Used in 80MHz input only mode when AXR, CLKX and FSX are all inputs.
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表 7-52. Virtual Mode Case Details for McASP3
No.
1
CASE
COIFOI
COIFIO
CIOFIO
CIOFOI
CASE
Description
Virtual Mode Settings
Notes
Signals
Virtual Mode Value
IP Mode : ASYNC
CLKX /
FSX: Output
CLKR /
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
See 图 7-36
See 图 7-37
See 图 7-38
See 图 7-39
MCASP3_VIRTUAL2_SYNC_RX
FSR: Input
2
CLKX /
FSR: Output
CLKR /
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
MCASP3_VIRTUAL2_SYNC_RX
FSX: Input
3
CLKR /
FSR: Output
CLKX /
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP3_VIRTUAL2_SYNC_RX
MCASP3_VIRTUAL2_SYNC_RX
FSX: Input
4
CLKR /
FSX: Output
CLKX /
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP3_VIRTUAL2_SYNC_RX
MCASP3_VIRTUAL2_SYNC_RX
FSR: Input
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
6
7
8
CO-FO-
CI-FO-
CI-FI-
CLKX /
FSX: Output
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
Default (No Virtual Mode)
See 图 7-40
See 图 7-41
See 图 7-42
See 图 7-43
FSX: Output
CLKX: Input
MCASP3_VIRTUAL2_SYNC_RX
MCASP3_VIRTUAL2_SYNC_RX
MCASP3_VIRTUAL2_SYNC_RX
MCASP3_VIRTUAL2_SYNC_RX
Default (No Virtual Mode)
CLKX /
FSX: Input
CO-FI-
CLKX:
Output FSX:
Input
Default (No Virtual Mode)
表 7-53. Virtual Mode Case Details for McASP4
No.
CASE
CASE
Virtual Mode Settings
Notes
Description
Signals
Virtual Mode Value
IP Mode : ASYNC
1
2
3
4
COIFOI
COIFIO
CIOFIO
CIOFOI
CLKX / FSX:
Output CLKR /
FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
See 图 7-36
See 图 7-37
See 图 7-38
See 图 7-39
MCASP4_VIRTUAL1_SYNC_RX
CLKX / FSR:
Output CLKR /
FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
MCASP4_VIRTUAL1_SYNC_RX
CLKR / FSR:
Output CLKX /
FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP4_VIRTUAL1_SYNC_RX
MCASP4_VIRTUAL1_SYNC_RX
CLKR / FSX:
Output CLKX /
FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP4_VIRTUAL1_SYNC_RX
MCASP4_VIRTUAL1_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
6
7
CO-FO-
CI-FO-
CI-FI-
CLKX / FSX:
Output
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
Default (No Virtual Mode)
See 图 7-40
See 图 7-41
See 图 7-42
FSX: Output
CLKX: Input
MCASP4_VIRTUAL1_SYNC_RX
MCASP4_VIRTUAL1_SYNC_RX
MCASP4_VIRTUAL1_SYNC_RX
MCASP4_VIRTUAL1_SYNC_RX
CLKX / FSX:
Input
264
Timing Requirements and Switching Characteristics
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表 7-53. Virtual Mode Case Details for McASP4 (continued)
No.
CASE
CASE
Virtual Mode Settings
Notes
Description
Signals
Virtual Mode Value
Default (No Virtual Mode)
Default (No Virtual Mode)
8
CO-FI-
CLKX: Output
FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
See 图 7-43
表 7-54. Virtual Mode Case Details for McASP5
No.
CASE
CASE
Virtual Mode Settings
Notes
Description
Signals
IP Mode : ASYNC
Virtual Mode Value
1
2
3
4
COIFOI
COIFIO
CIOFIO
CIOFOI
CLKX / FSX:
Output CLKR /
FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
See 图 7-36
See 图 7-37
See 图 7-38
See 图 7-39
MCASP5_VIRTUAL1_SYNC_RX
CLKX / FSR:
Output CLKR /
FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
MCASP5_VIRTUAL1_SYNC_RX
CLKR / FSR:
Output CLKX /
FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP5_VIRTUAL1_SYNC_RX
MCASP5_VIRTUAL1_SYNC_RX
CLKR / FSX:
Output CLKX /
FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP5_VIRTUAL1_SYNC_RX
MCASP5_VIRTUAL1_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
6
7
8
CO-FO-
CI-FO-
CI-FI-
CLKX / FSX:
Output
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
Default (No Virtual Mode)
See 图 7-40
See 图 7-41
See 图 7-42
See 图 7-43
FSX: Output
CLKX: Input
MCASP5_VIRTUAL1_SYNC_RX
MCASP5_VIRTUAL1_SYNC_RX
MCASP5_VIRTUAL1_SYNC_RX
MCASP5_VIRTUAL1_SYNC_RX
Default (No Virtual Mode)
CLKX / FSX:
Input
CO-FI-
CLKX: Output
FSX: Input
Default (No Virtual Mode)
表 7-55. Virtual Mode Case Details for McASP6
No.
CASE
CASE
Virtual Mode Settings
Notes
Description
Signals
IP Mode : ASYNC
Virtual Mode Value
1
2
3
4
COIFOI
COIFIO
CIOFIO
CIOFOI
CLKX / FSX:
Output CLKR
/ FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
See 图 7-36
See 图 7-37
See 图 7-38
See 图 7-39
MCASP6_VIRTUAL1_SYNC_RX
CLKX / FSR:
Output CLKR
/ FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
MCASP6_VIRTUAL1_SYNC_RX
CLKR / FSR:
Output CLKX
/ FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP6_VIRTUAL1_SYNC_RX
MCASP6_VIRTUAL1_SYNC_RX
CLKR / FSX:
Output CLKX
/ FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP6_VIRTUAL1_SYNC_RX
MCASP6_VIRTUAL1_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
CO-FO-
CLKX / FSX:
Output
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
Default (No Virtual Mode)
See 图 7-40
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表 7-55. Virtual Mode Case Details for McASP6 (continued)
No.
6
CASE
CI-FO-
CI-FI-
CASE
Description
Virtual Mode Settings
Notes
Signals
Virtual Mode Value
FSX: Output
CLKX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
MCASP6_VIRTUAL1_SYNC_RX
MCASP6_VIRTUAL1_SYNC_RX
MCASP6_VIRTUAL1_SYNC_RX
MCASP6_VIRTUAL1_SYNC_RX
Default (No Virtual Mode)
See 图 7-41
See 图 7-42
See 图 7-43
7
CLKX / FSX:
Input
8
CO-FI-
CLKX:
Output FSX:
Input
Default (No Virtual Mode)
表 7-56. Virtual Mode Case Details for McASP7
No.
CASE
CASE
Virtual Mode Settings
Notes
Description
Signals
IP Mode : ASYNC
Virtual Mode Value
1
2
3
4
COIFOI
COIFIO
CIOFIO
CIOFOI
CLKX / FSX:
Output CLKR
/ FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
See 图 7-36
See 图 7-37
See 图 7-38
See 图 7-39
MCASP7_VIRTUAL2_SYNC_RX
CLKX / FSR:
Output CLKR
/ FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
MCASP7_VIRTUAL2_SYNC_RX
CLKR / FSR:
Output CLKX
/ FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP7_VIRTUAL2_SYNC_RX
MCASP7_VIRTUAL2_SYNC_RX
CLKR / FSX:
Output CLKX
/ FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP7_VIRTUAL2_SYNC_RX
MCASP7_VIRTUAL2_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
6
7
8
CO-FO-
CI-FO-
CI-FI-
CLKX / FSX:
Output
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
Default (No Virtual Mode)
See 图 7-40
See 图 7-41
See 图 7-42
See 图 7-43
FSX: Output
CLKX: Input
MCASP7_VIRTUAL2_SYNC_RX
MCASP7_VIRTUAL2_SYNC_RX
MCASP7_VIRTUAL2_SYNC_RX
MCASP7_VIRTUAL2_SYNC_RX
Default (No Virtual Mode)
CLKX / FSX:
Input
CO-FI-
CLKX:
Output FSX:
Input
Default (No Virtual Mode)
表 7-57. Virtual Mode Case Details for McASP8
No.
CASE
CASE
Virtual Mode Settings
Notes
Description
Signals
IP Mode : ASYNC
Virtual Mode Value
1
2
3
COIFOI
COIFIO
CIOFIO
CLKX / FSX:
Output CLKR
/ FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
See 图 7-36
See 图 7-37
See 图 7-38
MCASP8_VIRTUAL1_SYNC_RX
CLKX / FSR:
Output CLKR
/ FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
MCASP8_VIRTUAL1_SYNC_RX
CLKR / FSR:
Output CLKX
/ FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP8_VIRTUAL1_SYNC_RX
MCASP8_VIRTUAL1_SYNC_RX
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表 7-57. Virtual Mode Case Details for McASP8 (continued)
No.
CASE
CASE
Virtual Mode Settings
Notes
Description
Signals
Virtual Mode Value
4
CIOFOI
CLKR / FSX:
Output CLKX
/ FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP8_VIRTUAL1_SYNC_RX
MCASP8_VIRTUAL1_SYNC_RX
See 图 7-39
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
6
7
8
CO-FO-
CI-FO-
CI-FI-
CLKX / FSX:
Output
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
Default (No Virtual Mode)
See 图 7-40
See 图 7-41
See 图 7-42
See 图 7-43
FSX: Output
CLKX: Input
MCASP8_VIRTUAL1_SYNC_RX
MCASP8_VIRTUAL1_SYNC_RX
MCASP8_VIRTUAL1_SYNC_RX
MCASP8_VIRTUAL1_SYNC_RX
Default (No Virtual Mode)
CLKX / FSX:
Input
CO-FI-
CLKX:
Output FSX:
Input
Default (No Virtual Mode)
SoC IOs
McASP
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_01
图 7-36. McASP1-8 COIFOI - ASYNC Mode
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SoC IOs
McASP
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_02
图 7-37. McASP1-8 COIFIO - ASYNC Mode
SoC IOs
McASP
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_03
图 7-38. McASP1-8 CIOFIO - ASYNC Mode
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SoC IOs
McASP
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_04
图 7-39. McASP1-8 CIOFOI - ASYNC Mode
SoC IOs
McASP
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_05
图 7-40. McASP1-8 CO-FO- - SYNC Mode
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SoC IOs
McASP
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_06
图 7-41. McASP1-8 CI-FO- - SYNC Mode
SoC IOs
McASP
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_07
图 7-42. McASP1-8 CI-FI- - SYNC Mode
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SoC IOs
McASP
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_08
图 7-43. McASP1-8 CO-FI- - SYNC Mode
注
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in 表 4-3 and described in Device TRM, Control
Module Chapter.
CAUTION
The I/O Timings provided in this section are valid only for some McASP usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
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Virtual IO Timings Modes must be used to guaranteed some IO timings for McASP1. See 表 7-2 Modes Summary for a list of IO timings requiring
the use of Virtual IO Timings Modes. See 表 7-58 Virtual Functions Mapping for McASP1 for a definition of the Virtual modes.
表 7-58 presents the values for DELAYMODE bitfield.
表 7-58. Virtual Functions Mapping for McASP1
BALL
BALL NAME
Delay Mode Value
MUXMODE
1
MCASP1_VIRTUAL1_SYNC_RX
MCASP1_VIRTUAL2_ASYNC_RX
0
2
C14
E21
A13
E12
B26
A11
D12
E14
F21
F20
C23
C12
B13
J14
mcasp1_aclkx
gpio6_14
15
14
15
14
14
15
14
15
14
14
14
14
15
N/A
15
15
14
15
15
15
15
N/A
14
15
15
14
15
14
13
14
13
13
14
13
14
13
13
13
13
14
14
14
14
13
14
14
14
14
14
13
14
14
13
14
mcasp1_aclkx
mcasp1_axr8
mcasp1_axr13
mcasp1_axr4
xref_clk2
mcasp1_axr13
mcasp1_axr4
mcasp1_axr6
mcasp1_axr9
mcasp1_axr7
mcasp1_axr12
gpio6_16
mcasp1_axr9
mcasp1_axr7
mcasp1_axr12
mcasp1_axr10
mcasp1_axr9
gpio6_15
xref_clk3
mcasp1_axr7
mcasp1_axr6
mcasp1_axr10
mcasp1_fsr
mcasp1_axr8
mcasp1_axr11
mcasp1_axr2
mcasp1_fsx
mcasp1_axr14
mcasp1_axr15
mcasp1_axr1
mcasp1_aclkr
mcasp1_axr5
xref_clk1
mcasp1_axr6
mcasp1_axr10
mcasp1_fsr
B12
A12
G13
D14
G14
F14
F12
B14
F13
E17
G12
J11
mcasp1_axr8
mcasp1_axr11
mcasp1_axr2
mcasp1_fsx
mcasp1_axr14
mcasp1_axr15
mcasp1_axr1
mcasp1_aclkr
mcasp1_axr5
mcasp1_axr5
mcasp1_axr4
mcasp1_axr0
mcasp1_axr3
xref_clk0
mcasp1_axr0
mcasp1_axr3
D18
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Timing Requirements and Switching Characteristics
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Virtual IO Timings Modes must be used to guaranteed some IO timings for McASP2. See 表 7-2 Modes Summary for a list of IO timings requiring
the use of Virtual IO Timings Modes. See 表 7-59 Virtual Functions Mapping for McASP2 for a definition of the Virtual modes.
表 7-59 presents the values for DELAYMODE bitfield.
表 7-59. Virtual Functions Mapping for McASP2
BALL
BALL NAME
Delay Mode Value
MUXMODE
1
MCASP2_VIRTUAL1
_SYNC_RX_80M
MCASP2_VIRTUAL2
MCASP2_VIRTUAL3
_SYNC_RX
MCASP2_VIRTUAL4
_ASYNC_RX_80M
0
2
_ASYNC_RX
B19
B17
B16
A18
B26
A16
E15
B18
A19
A17
C23
C17
F15
C15
D15
A20
E17
A15
B15
D18
mcasp3_axr0
mcasp2_axr6
mcasp2_axr5
mcasp2_fsx
xref_clk2
15
14
14
15
12
15
N/A
15
15
14
12
15
15
15
14
N/A
10
14
14
10
14
13
13
14
11
14
14
14
14
13
11
14
14
14
13
14
9
10
12
12
10
10
10
N/A
10
10
12
10
10
10
10
12
N/A
8
9
11
11
9
mcasp2_axr14
mcasp2_axr6
mcasp2_axr5
mcasp2_fsx
9
mcasp2_axr10
mcasp2_axr11
mcasp2_axr3
mcasp2_aclkr
mcasp3_aclkx
mcasp2_aclkx
mcasp2_axr7
xref_clk3
9
mcasp2_axr3
mcasp2_aclkr
13
9
mcasp2_axr12
9
mcasp2_aclkx
mcasp2_axr7
11
9
mcasp3_axr1
mcasp3_fsx
mcasp2_axr2
mcasp2_axr4
mcasp2_fsr
xref_clk1
8
mcasp2_axr15
mcasp2_axr13
9
9
mcasp2_axr2
mcasp2_axr4
mcasp2_fsr
11
13
6
mcasp2_axr9
mcasp2_axr8
mcasp2_axr1
mcasp2_axr0
xref_clk0
13
13
9
12
12
8
11
11
6
mcasp2_axr1
mcasp2_axr0
Virtual IO Timings Modes must be used to guaranteed some IO timings for McASP3/4/5/6/7/8. See 表 7-2 Modes Summary for a list of IO timings
requiring the use of Virtual IO Timings Modes. See 表 7-60 Virtual Functions Mapping for McASP3/4/5/6/7/8 for a definition of the Virtual modes.
表 7-60 presents the values for DELAYMODE bitfield.
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表 7-60. Virtual Functions Mapping for McASP3/4/5/6/7/8
BALL
BALL NAME
Delay Mode Value
MUXMODE
1
0
2
MCASP3_VIRTUAL2_SYNC_RX
A16
B18
B19
C17
F15
C15
mcasp2_axr3
mcasp3_aclkx
mcasp3_axr0
mcasp3_axr1
mcasp3_fsx
8
mcasp3_axr3
mcasp3_aclkr
8
8
6
8
8
mcasp3_aclkx
mcasp3_axr0
mcasp3_axr1
mcasp3_fsx
mcasp3_fsr
mcasp2_axr2
mcasp3_axr2
MCASP4_VIRTUAL1_SYNC_RX
A21
C18
G16
D17
F13
E12
mcasp4_fsx
mcasp4_aclkx
mcasp4_axr0
mcasp4_axr1
mcasp1_axr5
mcasp1_axr4
14
14
14
14
12
12
mcasp4_fsx
mcasp4_fsr
mcasp4_aclkx
mcasp4_axr0
mcasp4_axr1
mcasp4_aclkr
mcasp4_axr3
mcasp4_axr2
MCASP5_VIRTUAL1_SYNC_RX
AA3
AB9
AA4
C12
AB3
D12
mcasp5_aclkx
mcasp5_fsx
14
14
14
12
14
12
mcasp5_aclkx
mcasp5_aclkr
mcasp5_fsr
mcasp5_fsx
mcasp5_axr1
mcasp1_axr6
mcasp5_axr0
mcasp1_axr7
mcasp5_axr1
mcasp5_axr2
mcasp5_axr3
mcasp5_axr0
MCASP6_VIRTUAL1_SYNC_RX
G13
J11
B13
A11
B12
A12
mcasp1_axr2
mcasp1_axr3
mcasp1_axr10
mcasp1_axr9
mcasp1_axr8
mcasp1_axr11
12
mcasp6_axr2
mcasp6_axr3
mcasp6_aclkx
mcasp6_axr1
mcasp6_axr0
mcasp6_fsx
12
10
mcasp6_aclkr
mcasp6_fsr
10
10
10
MCASP7_VIRTUAL2_SYNC_RX
E14
F14
G14
mcasp1_axr12
mcasp1_axr15
mcasp1_axr14
10
10
10
mcasp7_axr0
mcasp7_fsx
mcasp7_fsr
mcasp7_aclkx
mcasp7_aclkr
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表 7-60. Virtual Functions Mapping for McASP3/4/5/6/7/8 (continued)
BALL
BALL NAME
Delay Mode Value
MUXMODE
0
1
2
A13
B14
J14
mcasp1_axr13
mcasp1_aclkr
mcasp1_fsr
10
13
13
mcasp7_axr1
mcasp7_axr2
mcasp7_axr3
MCASP8_VIRTUAL1_SYNC_RX
D15
A17
B17
A20
B16
E15
mcasp2_axr4
mcasp2_axr7
mcasp2_axr6
mcasp2_fsr
10
10
10
12
10
12
mcasp8_axr0
mcasp8_fsx
mcasp8_fsr
mcasp8_aclkx
mcasp8_axr3
mcasp8_axr1
mcasp8_axr2
mcasp8_aclkr
mcasp2_axr5
mcasp2_aclkr
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7.18 Universal Serial Bus (USB)
SuperSpeed USB DRD Subsystem has four instances in the device providing the following functions:
•
USB1: SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with integrated SS (USB3.0)
PHY and HS/FS (USB2.0) PHY.
•
•
USB2: High-Speed (HS) USB 2.0 Dual-Role-Device (DRD) subsystem with integrated HS/FS PHY.
USB3: HS USB 2.0 Dual-Role-Device (DRD) subsystem with ULPI (SDR) interface to external HS/FS
PHYs.
注
For more information, see the SuperSpeed USB DRD section of the Device TRM.
7.18.1 USB1 DRD PHY
The USB1 DRD interface supports the following applications:
•
USB2.0 High-Speed PHY port (1.8 V and 3.3 V): this asynchronous high-speed interface is compliant
with the USB2.0 PHY standard with an internal transceiver (USB2.0 standard v2.0), for a maximum
data rate of 480 Mbps.
•
USB3.0 Super-Speed PHY port (1.8 V): this asynchronous differential super-speed interface is
compliant with the USB3.0 RX/TX PHY standard (USB3.0 standard v1.0) for a maximum data bit rate
of 5Gbps.
7.18.2 USB2 PHY
The USB2 interface supports the following applications:
•
USB2.0 High-Speed PHY port (1.8 V and 3.3 V): this asynchronous high-speed interface is compliant
with the USB2.0 PHY standard with an internal transceiver (USB2.0 standard v2.0), for a maximum
data rate of 480 Mbps.
7.18.3 USB3 DRD ULPI-SDR-Slave Mode-12-pin Mode
TheUSB3 DRD interfaces support the following application:
•
USB ULPI port: this synchronous interface is compliant with the USB2.0 ULPI SDR standard (UTMI+
v1.22), for alternative off-chip USB2.0 PHY interface; that is, with external transceiver with a maximum
frequency of 60 MHz (synchronous slave mode, SDR, 12-pin, 8-data-bit).
注
The Universal Serial Bus k ULPI modules are also refered as USBk where k = 3, 4.
表 7-61, 表 7-62 and 图 7-44 assume testing over the recommended operating conditions and electrical
characteristic conditions.
表 7-61. Timing Requirements for ULPI SDR Slave Mode
NO.
US1
US5
PARAMETER
tc(clk)
tsu(ctrlV-clkH)
DESCRIPTION
Cycle time, usb_ulpi_clk period
MIN
16.66
6.73
MAX
UNIT
ns
Setup time, usb_ulpi_dir/usb_ulpi_nxt valid before usb_ulpi_clk
rising edge
ns
US6
th(clkH-ctrlV)
Hold time, usb_ulpi_dir/usb_ulpi_nxt valid after usb_ulpi_clk
rising edge
-0.41
ns
US7
US8
tsu(dV-clkH)
th(clkH-dV)
Setup time, usb_ulpi_d[7:0] valid before usb_ulpi_clk rising edge
Hold time, usb_ulpi_d[7:0] valid after usb_ulpi_clk rising edge
6.73
ns
ns
-0.41
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Timing Requirements and Switching Characteristics
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表 7-62. Switching Characteristics for ULPI SDR Slave Mode
NO.
PARAMETER
td(clkH-stpV)
DESCRIPTION
MIN
MAX
UNIT
US4
Delay time, usb_ulpi_clk rising edge high to output
usb_ulpi_stp valid
0.44
8.35
ns
US9
td(clkL-doV)
Delay time, usb_ulpi_clk rising edge high to output
usb_ulpi_d[7:0] valid
0.44
8.35
ns
US1
US2
US3
usbk_ulpi_clk
US4
US4
usbk_ulpi_stp
usbk_ulpi_dir_&_nxt
usbk_ulpi_d[7:0]
US6
US5
US7
US9
US8
US9
Data_IN
Data_OUT
SPRS906_TIMING_USB_01
图 7-44. HS USB3 ULPI -SDR-Slave Mode-12-pin Mode
In 表 7-63 are presented the specific groupings of signals (IOSET) for use with USB3 signals.
表 7-63. USB3 IOSETs
SIGNALS
IOSET2
IOSET3
BALL
AC5
AB4
AD4
AC4
AC7
AC6
AC9
AC3
AC8
AD6
AB8
AB5
MUX
3
BALL
W2
Y2
MUX
6
usb3_ulpi_d7
usb3_ulpi_d6
usb3_ulpi_d5
usb3_ulpi_d4
usb3_ulpi_d3
usb3_ulpi_d2
usb3_ulpi_d1
usb3_ulpi_d0
usb3_ulpi_nxt
usb3_ulpi_dir
usb3_ulpi_stp
usb3_ulpi_clk
3
6
3
V3
6
3
V4
6
3
V5
6
3
U5
U6
V6
6
3
6
3
6
3
U7
V7
6
3
6
3
V9
6
3
W9
6
7.19 Serial Advanced Technology Attachment (SATA)
The SATA RX/TX PHY interface is compliant with the SATA standard v2.6 for a maximum data rate:
•
•
Gen2i, Gen2m, Gen2x: 3Gbps.
Gen1i, Gen1m, Gen1x: 1.5Gbps.
注
For more information, see the SATA Controller section of the Device TRM.
7.20 Peripheral Component Interconnect Express (PCIe)
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The device supports connections to PCIe-compliant devices via the integrated PCIe master/slave bus
interface. The PCIe module is comprised of a dual-mode PCIe core and a SerDes PHY. Each PCIe
subsystem controller has support for PCIe Gen-II mode (5.0 Gbps /lane) and Gen-I mode (2.5 Gbps/lane)
(Single Lane and Flexible dual lane configuration).
The device PCIe supports the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
16-bit operation @250 MHz on PIPE interface (per 16-bit lane)
Supports 2 ports x 1 lane or 1 port x 2 lanes configuration
Single virtual channel (VC0), single traffic class (TC0)
Single function in end-point mode
Automatic width and speed negotiation
Max payload: 128 byte outbound, 256 byte inbound
Automatic credit management
ECRC generation and checking
Configurable BAR filtering
Legacy interrupt reception (RC) and generation (EP)
MSI generation and reception
PCI Express Active State Power Management (ASPM) state L0s and L1 (with exceptions)
All PCI Device Power Management D-states with the exception of D3cold / L2 state
The PCIe controller on this device conforms to the PCI Express Base 3.0 Specification, revision 1.0 and
the PCI Local Bus Specification, revision 3.0
注
For more information, see the PCIe Controller section of the Device TRM.
7.21 Controller Area Network Interface (DCAN)
The device provides two DCAN interfaces for supporting distributed realtime control with a high level of
security. The DCAN interfaces implement the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Supports CAN protocol version 2.0 part A, B
Bit rates up to 1 MBit/s
64 message objects
Individual identifier mask for each message object
Programmable FIFO mode for message objects
Programmable loop-back modes for self-test operation
Suspend mode for debug support
Software module reset
Automatic bus on after Bus-Off state by a programmable 32-bit timer
Direct access to Message RAM during test mode
CAN Rx/Tx pins are configurable as general-purpose IO pins
Two interrupt lines (plus additional parity-error interrupts line)
RAM initialization
DMA support
注
For more information, see the DCAN section of the Device TRM.
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注
The Controller Area Network Interface x (x = 1 to 2) is also referred to as DCANx.
注
Refer to the CAN Specification for calculations necessary to validate timing compliance. Jitter
tolerance calculations must be performed to validate the implementation.
表 7-64 and 表 7-65 present timing and switching characteristics for DCANx Interface.
表 7-64. Timing Requirements for DCANx Receive
NO.
PARAMETER
f(baud)
td(DCANRX)
DESCRIPTION
Maximum programmable baud rate
MIN
NOM
MAX
1
UNIT
Mbps
ns
-
-
Delay time, DCANx_RX pin to receive shift register
15
表 7-65. Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
NO.
PARAMETER
f(baud)
td(DCANTX)
DESCRIPTION
Maximum programmable baud rate
Delay time, Transmit shift register to DCANx_TX pin(1)
MIN
MAX
1
UNIT
Mbps
ns
-
-
23
(1) These values do not include rise/fall times of the output buffer.
7.22 Ethernet Interface (GMAC_SW)
The three-port gigabit ethernet switch subsystem (GMAC_SW) provides ethernet packet communication
and can be configured as an ethernet switch. It provides the Gigabit Media Independent Interface (G/MII)
in MII mode, Reduced Gigabit Media Independent Interface (RGMII), Reduced Media Independent
Interface (RMII), and the Management Data Input/Output (MDIO) for physical layer device (PHY)
management.
注
For more information, see the Ethernet Subsystem section of the Device TRM.
注
The Gigabit, Reduced and Media Independent Interface n (n = 0 to 1) are also referred to as
MIIn, RMIIn and RGMIIn.
CAUTION
The I/O timings provided in this section are valid only if signals within a single
IOSET are used. The IOSETs are defined in 表 7-70, 表 7-73, 表 7-78 and 表
7-85.
CAUTION
The I/O Timings provided in this section are valid only for some GMAC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
表 7-66 and 图 7-45 present timing requirements for MIIn in receive operation.
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7.22.1 GMAC MII Timings
表 7-66. Timing Requirements for miin_rxclk - MII Operation
NO.
PARAMETER
DESCRIPTION
SPEED
10 Mbps
100 Mbps
10 Mbps
100 Mbps
10 Mbps
100 Mbps
10 Mbps
100 Mbps
MIN
400
40
MAX
UNIT
ns
1
tc(RX_CLK)
Cycle time, miin_rxclk
ns
2
3
4
tw(RX_CLKH)
tw(RX_CLKL)
tt(RX_CLK)
Pulse duration, miin_rxclk high
Pulse duration, miin_rxclk low
Transition time, miin_rxclk
140
14
260
26
260
26
3
ns
ns
140
14
ns
ns
ns
3
ns
1
4
2
3
miin_rxclk
4
SPRS906_TIMING_GMAC_MIIRXCLK_01
图 7-45. Clock Timing (GMAC Receive) - MIIn operation
表 7-67 and 图 7-46 present timing requirements for MIIn in transmit operation.
表 7-67. Timing Requirements for miin_txclk - MII Operation
NO.
PARAMETER
DESCRIPTION
SPEED
10 Mbps
100 Mbps
10 Mbps
100 Mbps
10 Mbps
100 Mbps
10 Mbps
100 Mbps
MIN
MAX
UNIT
1
tc(TX_CLK)
Cycle time, miin_txclk
400
40
ns
ns
ns
ns
ns
ns
ns
ns
2
3
4
tw(TX_CLKH)
tw(TX_CLKL)
tt(TX_CLK)
Pulse duration, miin_txclk high
Pulse duration, miin_txclk low
Transition time, miin_txclk
140
14
260
26
260
26
3
140
14
3
1
4
2
3
miin_txclk
4
SPRS906_TIMING_GMAC_MIITXCLK_02
图 7-46. Clock Timing (GMAC Transmit) - MIIn operation
表 7-68 and 图 7-47 present timing requirements for GMAC MIIn Receive 10/100Mbit/s.
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表 7-68. Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
tsu(RXD-RX_CLK)
1
2
tsu(RX_DV-RX_CLK)
tsu(RX_ER-RX_CLK)
th(RX_CLK-RXD)
Setup time, receive selected signals valid before miin_rxclk
8
ns
th(RX_CLK-RX_DV)
th(RX_CLK-RX_ER)
Hold time, receive selected signals valid after miin_rxclk
8
ns
1
2
miin_rxclk (Input)
miin_rxd3−miin_rxd0,
miin_rxdv, miin_rxer (Inputs)
SPRS906_TIMING_GMAC_MIIRCV_03
图 7-47. GMAC Receive Interface Timing MIIn operation
表 7-69 and 图 7-48 present timing requirements for GMAC MIIn Transmit 10/100Mbit/s.
表 7-69. Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit
10/100 Mbits/s
NO.
PARAMETER
td(TX_CLK-TXD)
DESCRIPTION
MIN
MAX
UNIT
1
Delay time, miin_txclk to transmit selected signals valid
0
25
ns
td(TX_CLK-TX_EN)
1
miin_txclk (input)
miin_txd3 − miin_txd0,
miin_txen (outputs)
SPRS906_TIMING_GMAC_MIITX_04
图 7-48. GMAC Transmit Interface Timing MIIn operation
In 表 7-70 are presented the specific groupings of signals (IOSET) for use with GMAC MII signals.
表 7-70. GMAC MII IOSETs
SIGNALS
IOSET5
IOSET6
BALL
MUX
GMAC MII1
BALL
MUX
mii1_txd3
mii1_txd2
mii1_txd1
mii1_txd0
mii1_rxd3
mii1_rxd2
mii1_rxd1
mii1_rxd0
C5
D6
B2
C4
F5
E4
C1
E6
8
8
8
8
8
8
8
8
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表 7-70. GMAC MII IOSETs (continued)
SIGNALS
IOSET5
IOSET6
BALL
B4
MUX
BALL
MUX
mii1_col
mii1_rxer
mii1_txer
mii1_txen
mii1_crs
8
8
8
8
8
8
8
8
B3
A3
A4
B5
mii1_rxclk
mii1_txclk
mii1_rxdv
D5
C3
C2
GMAC MII0
mii0_txd3
mii0_txd2
mii0_txd1
mii0_txd0
mii0_rxd3
mii0_rxd2
mii0_rxd1
mii0_rxd0
mii0_txclk
mii0_txer
mii0_rxer
mii0_rxdv
mii0_crs
V5
V4
Y2
W2
W9
V9
V6
U6
U5
U4
U7
V2
V7
V1
Y1
V3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
mii0_col
mii0_rxclk
mii0_txen
7.22.2 GMAC MDIO Interface Timings
CAUTION
The I/O Timings provided in this section are valid only for some GMAC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
表 7-71, 表 7-71 and 图 7-49 present timing requirements for MDIO.
表 7-71. Timing Requirements for MDIO Input
No
PARAMETER
tc(MDC)
DESCRIPTION
MIN
400
160
160
90
MAX
UNIT
ns
MDIO1
MDIO2
MDIO3
MDIO4
MDIO5
Cycle time, MDC
tw(MDCH)
Pulse Duration, MDC High
ns
tw(MDCL)
Pulse Duration, MDC Low
ns
tsu(MDIO-MDC)
th(MDIO_MDC)
Setup time, MDIO valid before MDC High
Hold time, MDIO valid from MDC High
ns
0
ns
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表 7-72. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
NO
PARAMETER
tt(MDC)
DESCRIPTION
Transition time, MDC
MIN
MAX
5
UNIT
ns
MDIO6
MDIO7
td(MDC-MDIO)
Delay time, MDC High to MDIO valid
10
390
ns
1
MDIO2
MDIO3
MDCLK
MDIO6
MDIO6
MDIO4
MDIO5
MDIO
(input)
MDIO7
MDIO
(output)
SPRS906_TIMING_GMAC_MDIO_05
图 7-49. GMAC MDIO diagrams
In 表 7-73 are presented the specific groupings of signals (IOSET) for use with GMAC MDIO signals.
表 7-73. GMAC MDIO IOSETs
SIGNALS
IOSET7
IOSET8
IOSET9
IOSET10
BALL
F6
MUX
BALL
U4
MUX
BALL
AB4
MUX
BALL
B20
MUX
mdio_d
3
3
0
0
1
1
5
5
mdio_mclk
D3
V1
AC5
B21
7.22.3 GMAC RMII Timings
The main reference clock REF_CLK (RMII_50MHZ_CLK) of RMII interface is internally supplied from
PRCM. The source of this clock could be either externally sourced from the RMII_MHZ_50_CLK pin of the
device or internally generated from DPLL_GMAC output clock GMAC_RMII_HS_CLK. Please see the
PRCM chapter of the device TRM for full details about RMII reference clock.
CAUTION
The I/O Timings provided in this section are valid only for some GMAC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
表 7-74, 表 7-75 and 图 7-50 present timing requirements for GMAC RMIIn Receive.
表 7-74. Timing Requirements for GMAC REF_CLK - RMII Operation
NO.
PARAMETER
DESCRIPTION
MIN
20
7
MAX
UNIT
ns
RMII1 tc(REF_CLK)
RMII2 tw(REF_CLKH)
RMII3 tw(REF_CLKL)
Cycle time, REF_CLK
Pulse duration, REF_CLK high
Pulse duration, REF_CLK low
13
13
ns
7
ns
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表 7-74. Timing Requirements for GMAC REF_CLK - RMII Operation (continued)
NO.
PARAMETER
DESCRIPTION
Transistion time, REF_CLK
MIN
MAX
UNIT
RMII4 ttt(REF_CLK)
3
ns
表 7-75. Timing Requirements for GMAC RMIIn Receive
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
RMII5
tsu(RXD-REF_CLK)
tsu(CRS_DV-REF_CLK)
tsu(RX_ER-REF_CLK)
th(REF_CLK-RXD)
Setup time, receive selected signals valid before REF_CLK
4
ns
RMII6
Hold time, receive selected signals valid after REF_CLK
2
ns
th(REF_CLK-CRS_DV)
th(REF_CLK-RX_ER)
RMII1
RMII3
RMII2
RMII4
RMII6
RMII5
REF_CLK (PRCM)
rmiin_rxd1−rmiin_rxd0,
rmiin_crs, rmin_rxer (inputs)
SPRS906_TIMING_GMAC_RGMIITX_09
图 7-50. GMAC Receive Interface Timing RMIIn operation
表 7-76, 表 7-76 and 图 7-51 present switching characteristics for GMAC RMIIn Transmit 10/100Mbit/s.
表 7-76. Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII
Operation
NO.
PARAMETER
tc(REF_CLK)
DESCRIPTION
MIN
20
7
MAX
UNIT
ns
RMII7
RMII8
RMII9
Cycle time, REF_CLK
tw(REF_CLKH)
tw(REF_CLKL)
Pulse duration, REF_CLK high
Pulse duration, REF_CLK low
Transistion time, REF_CLK
13
13
3
ns
7
ns
RMII10 tt(REF_CLK)
ns
表 7-77. Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit
10/100 Mbits/s
NO.
PARAMETER
td(REF_CLK-TXD)
tdd(REF_CLK-TXEN)
td(REF_CLK-TXD)
tdd(REF_CLK-TXEN)
DESCRIPTION
RMIIn
MIN
MAX
UNIT
RMII0
2
13.5
ns
Delay time, REF_CLK high to selected transmit signals
valid
RMII11
RMII1
2
13.8
ns
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RMII7
RMII8
RMII11
RMII9
RMII10
REF_CLK (PRCM)
rmiin_txd1−rmiin_txd0,
rmiin_txen (Outputs)
SPRS906_TIMING_GMAC_RMIITX_07
图 7-51. GMAC Transmit Interface Timing RMIIn Operation
In 表 7-78 are presented the specific groupings of signals (IOSET) for use with GMAC RMII signals.
表 7-78. GMAC RMII IOSETs
SIGNALS
IOSET1
IOSET2
BALL
MUX
GMAC RMII1
BALL
MUX
RMII_MHZ_50_CLK
rmii1_txd1
U3
V5
V4
W9
V9
Y1
U5
V2
0
2
2
2
2
2
2
2
rmii1_txd0
rmii1_rxd1
rmii1_rxd0
rmii1_rxer
rmii1_txen
rmii1_crs
GMAC RMII0
RMII_MHZ_50_CLK
rmii0_txd1
U3
Y2
W2
V6
U6
V3
U7
V7
0
1
1
1
1
1
1
1
rmii0_txd0
rmii0_rxd1
rmii0_rxd0
rmii0_txen
rmii0_rxer
rmii0_crs
Manual IO Timings Modes must be used to guaranteed some IO timings for GMAC. See 表 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See 表 7-79 Manual
Functions Mapping for GMAC RMII0 for a definition of the Manual modes.
表 7-79 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
表 7-79. Manual Functions Mapping for GMAC RMII0
BALL
BALL NAME
GMAC_RMII0_MANUAL1
CFG REGISTER
MUXMODE
A_DELAY
(ps)
G_DELAY
(ps)
0
1
U3
U6
V6
U7
V7
RMII_MHZ_50_CLK
rgmii0_txd0
0
0
CFG_RMII_MHZ_50_CLK_IN
CFG_RGMII0_TXD0_IN
CFG_RGMII0_TXD1_IN
CFG_RGMII0_TXD2_IN
CFG_RGMII0_TXD3_IN
RMII_MHZ_50_CLK
2444
2453
2356
2415
804
981
847
993
rmii0_rxd0
rmii0_rxd1
rmii0_rxer
rmii0_crs
rgmii0_txd1
rgmii0_txd2
rgmii0_txd3
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Manual IO Timings Modes must be used to guaranteed some IO timings for GMAC. See 表 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See 表 7-80 Manual
Functions Mapping for GMAC RMII1 for a definition of the Manual modes.
表 7-80 list the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
表 7-80. Manual Functions Mapping for GMAC RMII1
BALL
BALL NAME
GMAC_RMII1_MANUAL1
CFG REGISTER
MUXMODE
A_DELAY
(ps)
G_DELAY
(ps)
0
2
U3
V9
W9
Y1
V2
RMII_MHZ_50_CLK
rgmii0_txctl
rgmii0_txc
0
0
CFG_RMII_MHZ_50_CLK_IN
CFG_RGMII0_TXCTL_IN
CFG_RGMII0_TXC_IN
CFG_UART3_TXD_IN
CFG_UART3_RXD_IN
RMII_MHZ_50_CLK
2450
2327
2553
1943
909
926
443
1110
rmii1_rxd0
rmii1_rxd1
rmii1_rxer
rmii1_crs
uart3_txd
uart3_rxd
7.22.4 GMAC RGMII Timings
CAUTION
The I/O Timings provided in this section are valid only for some GMAC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
表 7-81, 表 7-82 and 图 7-52 present timing requirements for receive RGMIIn operation.
表 7-81. Timing Requirements for rgmiin_rxc - RGMIIn Operation
NO.
PARAMETER
DESCRIPTION
SPEED
10 Mbps
MIN
360
36
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
tc(TXC)
Cycle time, rgmiin_txc
440
44
100 Mbps
1000 Mbps
10 Mbps
7.2
160
16
8.8
2
3
4
tw(TXCH)
tw(TXCL)
tt(TXC)
Pulse duration, rgmiin_txc high
Pulse duration, rgmiin_txc low
Transition time, rgmiin_txc
240
24
100 Mbps
1000 Mbps
10 Mbps
3.6
160
16
4.4
240
24
100 Mbps
1000 Mbps
10 Mbps
3.6
4.4
0.75
0.75
0.75
100 Mbps
1000 Mbps
表 7-82. Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps (1)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
5
tsu(RXD-RXCH)
Setup time, receive selected signals valid before
rgmiin_rxc high/low
RGMII0/1
1
ns
6
th(RXCH-RXD)
Hold time, receive selected signals valid after
rgmiin_rxc high/low
RGMII0/1
1
ns
286
Timing Requirements and Switching Characteristics
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(1) For RGMII, receive selected signals include: rgmiin_rxd[3:0] and rgmiin_rxctl.
1
4
2
4
3
rgmiin_rxc(A)
5
1st Half-byte
2nd Half-byte
6
rgmiin_rxd[3:0](B)
rgmiin_rxctl(B)
RGRXD[3:0]
RXDV
RGRXD[7:4]
RXERR
SPRS906_TIMING_GMAC_RGMIIRX_08
A. rgmiin_rxc must be externally delayed relative to the data and control pins.
B. Data and control information is received using both edges of the clocks. rgmiin_rxd[3:0] carries data bits 3-0 on the
rising edge of rgmiin_rxc and data bits 7-4 on the falling edge ofrgmiin_rxc. Similarly, rgmiin_rxctl carries RXDV on
rising edge of rgmiin_rxc and RXERR on falling edge of rgmiin_rxc.
图 7-52. GMAC Receive Interface Timing, RGMIIn operation
表 7-83, 表 7-84 and 图 7-53 present switching characteristics for transmit - RGMIIn for
10/100/1000Mbit/s.
表 7-83. Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn
Operation for 10/100/1000 Mbit/s
NO.
PARAMETER
DESCRIPTION
SPEED
10 Mbps
MIN
360
36
MAX
440
44
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
tc(TXC)
Cycle time, rgmiin_txc
100 Mbps
1000 Mbps
10 Mbps
7.2
160
16
8.8
2
3
4
tw(TXCH)
tw(TXCL)
tt(TXC)
Pulse duration, rgmiin_txc high
Pulse duration, rgmiin_txc low
Transition time, rgmiin_txc
240
24
100 Mbps
1000 Mbps
10 Mbps
3.6
160
16
4.4
240
24
100 Mbps
1000 Mbps
10 Mbps
3.6
4.4
0.75
0.75
0.75
100 Mbps
1000 Mbps
表 7-84. Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps (1)
NO. PARAMETER
tosu(TXD-TXC)
DESCRIPTION
MODE
MIN
MAX
UNIT
5
Output Setup time, transmit selected signals valid to
rgmiin_txc high/low
RGMII0, Internal Delay
Enabled, 1000 Mbps
1.05
ns
(2)
RGMII0, Internal Delay
Enabled, 10/100 Mbps
1.2
ns
ns
ns
RGMII1, Internal Delay
Enabled, 1000 Mbps
1.05
(3)
RGMII1, Internal Delay
Enabled, 10/100 Mbps
1.2
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表 7-84. Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps (1) (continued)
NO. PARAMETER
toh(TXC-TXD)
DESCRIPTION
MODE
MIN
MAX
UNIT
6
Output Hold time, transmit selected signals valid after
rgmiin_txc high/low
RGMII0, Internal Delay
Enabled, 1000 Mbps
1.05
ns
(2)
RGMII0, Internal Delay
Enabled, 10/100 Mbps
1.2
ns
ns
ns
RGMII1, Internal Delay
Enabled, 1000 Mbps
1.05
(3)
RGMII1, Internal Delay
Enabled, 10/100 Mbps
1.2
(1) For RGMII, transmit selected signals include: rgmiin_txd[3:0] and rgmiin_txctl.
(2) RGMII0 requires that the 4 data pins rgmii0_txd[3:0] and rgmii0_txctl have their board propagation delays matched within 50pS of
rgmii0_txc.
(3) RGMII1 requires that the 4 data pins rgmii1_txd[3:0] and rgmii1_txctl have their board propagation delays matched within 50pS of
rgmii1_txc.
1
4
2
4
3
rgmiin_txc(A)
[internal delay enabled]
5
rgmiin_txd[3:0](B)
rgmiin_txctl(B)
1st Half-byte
TXEN
2nd Half-byte
TXERR
6
SPRS906_TIMING_GMAC_RGMIITX_09
A. TXC is delayed internally before being driven to the rgmiin_txc pin. This internal delay is always enabled.
B. Data and control information is transmitted using both edges of the clocks. rgmiin_txd[3:0] carries data bits 3-0 on the
rising edge of rgmiin_txc and data bits 7-4 on the falling edge of rgmiin_txc. Similarly, rgmiin_txctl carries TXEN on
rising edge of rgmiin_txc and TXERR of falling edge of rgmiin_txc.
图 7-53. GMAC Transmit Interface Timing RGMIIn operation
In 表 7-85 are presented the specific groupings of signals (IOSET) for use with GMAC RGMII signals.
表 7-85. GMAC RGMII IOSETs
SIGNALS
IOSET3
IOSET4
BALL
MUX
GMAC RGMII1
BALL
MUX
rgmii1_txd3
rgmii1_txd2
rgmii1_txd1
rgmii1_txd0
rgmii1_rxd3
rgmii1_rxd2
rgmii1_rxd1
rgmii1_rxd0
rgmii1_rxctl
rgmii1_txc
C3
C4
B2
D6
B3
B4
B5
A4
A3
D5
C2
C5
3
3
3
3
3
3
3
3
3
3
3
3
rgmii1_txctl
rgmii1_rxc
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表 7-85. GMAC RGMII IOSETs (continued)
SIGNALS
IOSET3
IOSET4
BALL
MUX
GMAC RGMII0
BALL
MUX
rgmii0_txd3
rgmii0_txd2
rgmii0_txd1
rgmii0_txd0
rgmii0_rxd3
rgmii0_rxd2
rgmii0_rxd1
rgmii0_rxd0
rgmii0_txc
V7
U7
V6
U6
V4
V3
Y2
W2
W9
V5
U5
V9
0
0
0
0
0
0
0
0
0
0
0
0
rgmii0_rxctl
rgmii0_rxc
rgmii0_txctl
注
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section "Manual IO Timing Modes" of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information please see the Control Module Chapter in the Device TRM.
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Manual IO Timings Modes must be used to guaranteed some IO timings for GMAC. See 表 7-2 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See 表 7-86 Manual Functions Mapping for GMAC RGMII0 for a definition of the Manual modes.
表 7-86 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
表 7-86. Manual Functions Mapping for GMAC RGMII0
BALL
BALL NAME
GMAC_RGMII0_MANUAL1
CFG REGISTER
MUXMODE
0
A_DELAY (ps)
G_DELAY (ps)
U5
V5
W2
Y2
V3
V4
rgmii0_rxc
rgmii0_rxctl
rgmii0_rxd0
rgmii0_rxd1
rgmii0_rxd2
rgmii0_rxd3
413
27
3
0
CFG_RGMII0_RXC_IN
CFG_RGMII0_RXCTL_IN
CFG_RGMII0_RXD0_IN
CFG_RGMII0_RXD1_IN
CFG_RGMII0_RXD2_IN
CFG_RGMII0_RXD3_IN
rgmii0_rxc
rgmii0_rxctl
rgmii0_rxd0
rgmii0_rxd1
rgmii0_rxd2
rgmii0_rxd3
2296
1721
1786
1966
2057
134
40
0
W9
V9
U6
V6
U7
V7
rgmii0_txc
rgmii0_txctl
rgmii0_txd0
rgmii0_txd1
rgmii0_txd2
rgmii0_txd3
0
0
0
0
0
0
60
60
60
0
CFG_RGMII0_TXC_OUT
CFG_RGMII0_TXCTL_OUT
CFG_RGMII0_TXD0_OUT
CFG_RGMII0_TXD1_OUT
CFG_RGMII0_TXD2_OUT
CFG_RGMII0_TXD3_OUT
rgmii0_txc
rgmii0_txctl
rgmii0_txd0
rgmii0_txd1
rgmii0_txd2
rgmii0_txd3
60
120
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Manual IO Timings Modes must be used to guaranteed some IO timings for GMAC. See 表 7-2 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See 表 7-87 Manual Functions Mapping for GMAC RGMII1 for a definition of the Manual modes.
表 7-87 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
表 7-87. Manual Functions Mapping for GMAC RGMII1
BALL
BALL NAME
GMAC_RGMII1_MANUAL1
CFG REGISTER
MUXMODE
3
A_DELAY (ps)
G_DELAY (ps)
C5
A3
B3
B4
B5
A4
vin2a_d18
vin2a_d19
vin2a_d20
vin2a_d21
vin2a_d22
vin2a_d23
530
71
0
CFG_VIN2A_D18_IN
CFG_VIN2A_D19_IN
CFG_VIN2A_D20_IN
CFG_VIN2A_D21_IN
CFG_VIN2A_D22_IN
CFG_VIN2A_D23_IN
rgmii1_rxc
rgmii1_rxctl
rgmii1_rxd3
rgmii1_rxd2
rgmii1_rxd1
rgmii1_rxd0
1099
1337
1517
1331
1328
142
114
171
0
D5
C2
C3
C4
B2
D6
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
vin2a_d16
vin2a_d17
0
170
150
0
0
0
0
0
0
0
CFG_VIN2A_D12_OUT
CFG_VIN2A_D13_OUT
CFG_VIN2A_D14_OUT
CFG_VIN2A_D15_OUT
CFG_VIN2A_D16_OUT
CFG_VIN2A_D17_OUT
rgmii1_txc
rgmii1_txctl
rgmii1_txd3
rgmii1_txd2
rgmii1_txd1
rgmii1_txd0
60
60
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7.23 eMMC/SD/SDIO
The Device includes the following external memory interfaces 4 MultiMedia Card/Secure Digital/Secure
Digital Input Output Interface (MMC/SD/SDIO).
注
The eMMC/SD/SDIOi (i = 1 to 4) controller is also referred to as MMCi.
7.23.1 MMC1-SD Card Interface
MMC1 interface is compliant with the SD Standard v3.01 and it supports the following SD Card
applications:
•
•
•
•
•
•
•
Default speed, 4-bit data, SDR, half-cycle
High speed, 4-bit data, SDR, half-cycle
SDR12, 4-bit data, half-cycle
SDR25, 4-bit data, half-cycle
UHS-I SDR50, 4-bit data, half-cycle
UHS-I SDR104, 4-bit data, half-cycle
UHS-I DDR50, 4-bit data
注
For more information, see the eMMC/SD/SDIO chapter of the Device TRM.
7.23.1.1 Default speed, 4-bit data, SDR, half-cycle
表 7-88 and 表 7-89 present Timing requirements and Switching characteristics for MMC1 - Default Speed
in receiver and transmitter mode (see 图 7-54 and 图 7-55).
表 7-88. Timing Requirements for MMC1 - SD Card Default Speed Mode
NO.
PARAMETER
DESCRIPTION
MIN
5.11
MAX
UNIT
ns
DSSD5 tsu(cmdV-clkH)
DSSD6 th(clkH-cmdV)
DSSD7 tsu(dV-clkH)
DSSD8 th(clkH-dV)
Setup time, mmc1_cmd valid before mmc1_clk rising clock edge
Hold time, mmc1_cmd valid after mmc1_clk rising clock edge
Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge
20.46
5.11
ns
ns
20.46
ns
表 7-89. Switching Characteristics for MMC1 - SD Card Default Speed Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
DSSD0 fop(clk)
DSSD1 tw(clkH)
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
24
0.5*P-
0.185
(1)
DSSD2 tw(clkL)
Pulse duration, mmc1_clk low
0.5*P-
ns
(1)
0.185
-14.93
-14.93
DSSD3 td(clkL-cmdV)
DSSD4 td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
14.93
14.93
ns
ns
292
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(1) P = output mmc1_clk period in ns
DSSD2
DSSD1
DSSD0
mmc1_clk
mmc1_cmd
DSSD6
DSSD5
DSSD8
DSSD7
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_01
图 7-54. MMC/SD/SDIO in - Default Speed - Receiver Mode
DSSD2
DSSD1
DSSD0
mmc1_clk
DSSD3
DSSD4
mmc1_cmd
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_02
图 7-55. MMC/SD/SDIO in - Default Speed - Transmitter Mode
7.23.1.2 High speed, 4-bit data, SDR, half-cycle
表 7-90 and 表 7-91 present Timing requirements and Switching characteristics for MMC1 - High Speed in
receiver and transmitter mode (see 图 7-56 and 图 7-57).
表 7-90. Timing Requirements for MMC1 - SD Card High Speed
NO.
PARAMETER
DESCRIPTION
MIN
5.3
2.6
5.3
2.6
MAX
UNIT
ns
HSSD3 tsu(cmdV-clkH)
HSSD4 th(clkH-cmdV)
HSSD7 tsu(dV-clkH)
HSSD8 th(clkH-dV)
Setup time, mmc1_cmd valid before mmc1_clk rising clock edge
Hold time, mmc1_cmd valid after mmc1_clk rising clock edge
Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge
ns
ns
ns
表 7-91. Switching Characteristics for MMC1 - SD Card High Speed
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
HSSD1 fop(clk)
HSSD2H tw(clkH)
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
48
0.5*P-
0.185
(1)
HSSD2L tw(clkL)
Pulse duration, mmc1_clk low
0.5*P-
0.185
ns
(1)
HSSD5 td(clkL-cmdV)
HSSD6 td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
-7.6
3.6
3.6
ns
ns
-7.6
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(1) P = output mmc1_clk period in ns
HSSD1
HSSD2H
HSSD4
HSSD2L
mmc1_clk
mmc1_cmd
HSSD3
HSSD7
HSSD8
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_03
图 7-56. MMC/SD/SDIO in - High Speed - Receiver Mode
HSSD1
HSSD2H
HSSD2L
HSSD5
mmc1_clk
mmc1_cmd
HSSD5
HSSD6
HSSD6
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_04
图 7-57. MMC/SD/SDIO in - High Speed - Transmitter Mode
7.23.1.3 SDR12, 4-bit data, half-cycle
表 7-92 and 表 7-93 present Timing requirements and Switching characteristics for MMC1 - SDR12 in
receiver and transmitter mode (see 图 7-58 and 图 7-59).
表 7-92. Timing Requirements for MMC1 - SD Card SDR12 Mode
NO.
PARAMETER
DESCRIPTION
MODE
MIN
25.99
MAX UNIT
SDR12 tsu(cmdV-clkH)
5
Setup time, mmc1_cmd valid before mmc1_clk rising
clock edge
ns
SDR12 th(clkH-cmdV)
6
Hold time, mmc1_cmd valid after mmc1_clk rising
clock edge
Pad Loopback Clock
1.6
1.6
ns
ns
ns
Internal Loopback Clock
SDR12 tsu(dV-clkH)
7
Setup time, mmc1_dat[3:0] valid before mmc1_clk
rising clock edge
25.99
SDR12 th(clkH-dV)
8
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising
clock edge
Pad Loopback Clock
1.6
1.6
ns
ns
Internal Loopback Clock
表 7-93. Switching Characteristics for MMC1 - SD Card SDR12 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
SDR120 fop(clk)
SDR121 tw(clkH)
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
24
0.5*P-
0.185
(1)
SDR122 tw(clkL)
Pulse duration, mmc1_clk low
0.5*P-
ns
0.185(1)
SDR123 td(clkL-cmdV)
SDR124 td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
-19.13
-19.13
16.93
16.93
ns
ns
294
Timing Requirements and Switching Characteristics
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(1) P = output mmc1_clk period in ns
SDR122
SDR121
SDR120
mmc1_clk
mmc1_cmd
SDR126
SDR125
SDR128
SDR127
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_05
图 7-58. MMC/SD/SDIO in - High Speed SDR12 - Receiver Mode
SDR122
SDR121
SDR120
SDR123
SDR124
mmc1_clk
mmc1_cmd
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_06
图 7-59. MMC/SD/SDIO in - High Speed SDR12 - Transmitter Mode
7.23.1.4 SDR25, 4-bit data, half-cycle
表 7-94 and 表 7-95 present Timing requirements and Switching characteristics for MMC1 - SDR25 in
receiver and transmitter mode (see 图 7-60 and 图 7-61).
表 7-94. Timing Requirements for MMC1 - SD Card SDR25 Mode
NO.
PARAMETER
DESCRIPTION
MODE
MIN
5.3
MAX UNIT
SDR25 tsu(cmdV-clkH)
3
Setup time, mmc1_cmd valid before mmc1_clk rising
clock edge
ns
SDR25 th(clkH-cmdV)
4
Hold time, mmc1_cmd valid after mmc1_clk rising
clock edge
1.6
5.3
ns
ns
SDR25 tsu(dV-clkH)
7
Setup time, mmc1_dat[3:0] valid before mmc1_clk
rising clock edge
SDR25 th(clkH-dV)
8
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising
clock edge
Pad Loopback Clock
1.6
1.6
ns
ns
Internal Loopback Clock
表 7-95. Switching Characteristics for MMC1 - SD Card SDR25 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
SDR251 fop(clk)
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
48
SDR252 tw(clkH)
H
0.5*P-
0.185
(1)
SDR252L tw(clkL)
Pulse duration, mmc1_clk low
0.5*P-
0.185
ns
ns
(1)
SDR255 td(clkL-cmdV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
-8.8
6.6
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表 7-95. Switching Characteristics for MMC1 - SD Card SDR25 Mode (continued)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
SDR256 td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
-8.8
6.6
ns
(1) P = output mmc1_clk period in ns
SDR251
SDR252L
SDR253
SDR252H
SDR254
mmc1_clk
mmc1_cmd
SDR257
SDR258
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_07
图 7-60. MMC/SD/SDIO in - High Speed SDR25 - Receiver Mode
SDR251
SDR252H
SDR252L
HSSDR255
SDR256
mmc1_clk
mmc1_cmd
SDR255
SDR256
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_08
图 7-61. MMC/SD/SDIO in - High Speed SDR25 - Transmitter Mode
7.23.1.5 UHS-I SDR50, 4-bit data, half-cycle
表 7-96 and 表 7-97 present Timing requirements and Switching characteristics for MMC1 - SDR50 in
receiver and transmitter mode (see 图 7-62 and 图 7-63).
表 7-96. Timing Requirements for MMC1 - SD Card SDR50 Mode
NO.
PARAMETER
DESCRIPTION
MODE
MIN
1.48
MAX UNIT
SDR50 tsu(cmdV-clkH)
3
Setup time, mmc1_cmd valid before mmc1_clk rising
clock edge
ns
SDR50 th(clkH-cmdV)
4
Hold time, mmc1_cmd valid after mmc1_clk rising
clock edge
1.7
ns
ns
SDR50 tsu(dV-clkH)
7
Setup time, mmc1_dat[3:0] valid before mmc1_clk
rising clock edge
1.48
SDR50 th(clkH-dV)
8
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising
clock edge
Pad Loopback Clock
1.7
1.6
ns
ns
Internal Loopback Clock
表 7-97. Switching Characteristics for MMC1 - SD Card SDR50 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
SDR501 fop(clk)
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
96
SDR502 tw(clkH)
H
0.5*P-
(1)
0.185
SDR502L tw(clkL)
Pulse duration, mmc1_clk low
0.5*P-
0.185
ns
(1)
SDR505 td(clkL-cmdV)
SDR506 td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
-8.8
6.6
ns
ns
-3.66
1.46
296
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(1) P = output mmc1_clk period in ns
SDR501
SDR502L
SDR502H
SDR504
mmc1_clk
mmc1_cmd
SDR503
SDR507
SDR508
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_09
图 7-62. MMC/SD/SDIO in - High Speed SDR50 - Receiver Mode
SDR501
SDR502H
SDR502L
SDR505
mmc1_clk
mmc1_cmd
SDR505
SDR506
SDR506
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_10
图 7-63. MMC/SD/SDIO in - High Speed SDR50 - Transmitter Mode
7.23.1.6 UHS-I SDR104, 4-bit data, half-cycle
表 7-98 presents Timing requirements and Switching characteristics for MMC1 - SDR104 in receiver and
transmitter mode (see 图 7-64 and 图 7-65).
表 7-98. Switching Characteristics for MMC1 - SD Card SDR104 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
192
UNIT
MHz
ns
SDR1041 fop(clk)
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
SDR1042 tw(clkH)
H
0.5*P-
(1)
0.185
SDR1042 tw(clkL)
L
Pulse duration, mmc1_clk low
0.5*P-
ns
(1)
0.185
-1.09
-1.09
SDR1045 td(clkL-cmdV)
SDR1046 td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
0.49
0.49
ns
ns
(1) P = output mmc1_clk period in ns
SDR1041
SDR1042L
SDR1042H
SDR1044
mmc1_clk
mmc1_cmd
SDR1043
SDR1047
SDR1048
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_11
图 7-64. MMC/SD/SDIO in - High Speed SDR104 - Receiver Mode
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SDR1041
SDR1042H
SDR1042L
SDR1045
mmc1_clk
mmc1_cmd
SDR1045
SDR1046
SDR1046
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_12
图 7-65. MMC/SD/SDIO in - High Speed SDR104 - Transmitter Mode
7.23.1.7 UHS-I DDR50, 4-bit data
表 7-99 and 表 7-100 present Timing requirements and Switching characteristics for MMC1 - DDR50 in
receiver and transmitter mode (see 图 7-66 and 图 7-67).
表 7-99. Timing Requirements for MMC1 - SD Card DDR50 Mode
PARAME
NO.
DESCRIPTION
MODE
MIN
1.79
MAX UNIT
TER
DDR50 tsu(cmdV-clk) Setup time, mmc1_cmd valid before mmc1_clk
transition
ns
5
DDR50 th(clk-cmdV) Hold time, mmc1_cmd valid after mmc1_clk transition
6
2
ns
DDR50 tsu(dV-clk)
7
Setup time, mmc1_dat[3:0] valid before mmc1_clk
transition
Pad Loopback
1.79
1.79
2
ns
ns
ns
ns
Internal Loopback
Pad Loopback
DDR50 th(clk-dV)
8
Hold time, mmc1_dat[3:0] valid after mmc1_clk
transition
Internal Loopback
1.6
表 7-100. Switching Characteristics for MMC1 - SD Card DDR50 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
DDR500 fop(clk)
DDR501 tw(clkH)
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
48
0.5*P-
(1)
0.185
DDR502 tw(clkL)
Pulse duration, mmc1_clk low
0.5*P-
ns
(1)
0.185
1.225
1.225
DDR503 td(clk-cmdV)
DDR504 td(clk-dV)
Delay time, mmc1_clk transition to mmc1_cmd transition
Delay time, mmc1_clk transition to mmc1_dat[3:0] transition
6.6
6.6
ns
ns
(1) P = output mmc1_clk period in ns
DDR500
DDR501
DDR502
mmc1_clk
DDR505
DDR506
mmc1_cmd
DDR507
DDR508
DDR507
DDR508
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_13
图 7-66. SDMMC - High Speed SD - DDR - Data/Command Receive
298
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DDR500
DDR501
DDR502
mmc1_clk
DDR503(max)
DDR503(min)
mmc1_cmd
DDR504(max)
DDR504(min)
DDR504(max)
DDR504(min)
mmc1_dat[3:0]
MMC1_14
图 7-67. SDMMC - High Speed SD - DDR - Data/Command Transmit
注
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in 表 4-3 and described in Device TRM, Control
Module Chapter.
Virtual IO Timings Modes must be used to guaranteed some IO timings for MMC1. See 表 7-2 Modes
Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See 表 7-101 Virtual
Functions Mapping for MMC1 for a definition of the Virtual modes.
表 7-101 presents the values for DELAYMODE bitfield.
表 7-101. Virtual Functions Mapping for MMC1
BALL
BALL NAME
Delay Mode Value
MUXMODE
0
MMC1_
MMC1_
MMC1_
MMC1_
VIRTUAL1
VIRTUAL4
VIRTUAL5
VIRTUAL6
W6
Y6
mmc1_clk
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
15
15
15
15
15
15
12
12
12
12
12
12
11
11
11
11
11
11
10
10
10
10
10
10
mmc1_clk
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
AA6
Y4
AA5
Y3
注
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section Manual IO Timing Modes of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information see the Control Module chapter in the Device TRM.
Manual IO Timings Modes must be used to guaranteed some IO timings for MMC1. See 表 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See 表 7-102 Manual
Functions Mapping for MMC1 for a definition of the Manual modes.
表 7-102 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
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表 7-102. Manual Functions Mapping for MMC1
BALL
BALL NAME
MMC1_MANUAL1
MMC1_MANUAL2
CFG REGISTER
MUXMODE
0
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
W6
Y6
mmc1_clk
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
588
0
0
0
0
0
0
-
-
-
-
-
-
-
-
-
-
-
-
CFG_MMC1_CLK_IN
CFG_MMC1_CMD_IN
CFG_MMC1_DAT0_IN
CFG_MMC1_DAT1_IN
CFG_MMC1_DAT2_IN
CFG_MMC1_DAT3_IN
mmc1_clk
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
1000
1375
1000
1000
1000
AA6
Y4
AA5
Y3
W6
Y6
mmc1_clk
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
1230
0
0
0
0
0
0
0
520
0
320
0
CFG_MMC1_CLK_OUT
CFG_MMC1_CMD_OUT
CFG_MMC1_DAT0_OUT
CFG_MMC1_DAT1_OUT
CFG_MMC1_DAT2_OUT
CFG_MMC1_DAT3_OUT
mmc1_clk
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
AA6
Y4
56
76
91
99
40
83
98
106
0
0
AA5
Y3
0
0
Y6
AA6
Y4
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
0
0
0
0
0
0
0
0
0
0
51
0
0
0
0
0
0
CFG_MMC1_CMD_OEN
CFG_MMC1_DAT0_OEN
CFG_MMC1_DAT1_OEN
CFG_MMC1_DAT2_OEN
CFG_MMC1_DAT3_OEN
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
363
199
273
AA5
Y3
7.23.2 MMC2 - eMMC
MMC2 interface is compliant with the JC64 eMMC Standard v4.5 and it supports the following eMMC applications:
•
•
•
•
Standard JC64 SDR, 8-bit data, half cycle
High-speed JC64 SDR, 8-bit data, half cycle
High-speed HS200 JEDS84, 8-bit data, half cycle
High-speed JC64 DDR, 8-bit data
注
For more information, see the eMMC/SD/SDIO chapter of the Device TRM.
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7.23.2.1 Standard JC64 SDR, 8-bit data, half cycle
表 7-103 and 表 7-104 present Timing requirements and Switching characteristics for MMC2 - Standart SDR in receiver and transmitter mode (see
图 7-68 and 图 7-69).
表 7-103. Timing Requirements for MMC2 - JC64 Standard SDR Mode
NO.
PARAMETER
tsu(cmdV-clkH)
th(clkH-cmdV)
tsu(dV-clkH)
DESCRIPTION
MIN
13.19
8.4
MAX
UNIT
ns
SSDR5
SSDR6
SSDR7
SSDR8
Setup time, mmc2_cmd valid before mmc2_clk rising clock edge
Hold time, mmc2_cmd valid after mmc2_clk rising clock edge
Setup time, mmc2_dat[7:0] valid before mmc2_clk rising clock edge
Hold time, mmc2_dat[7:0] valid after mmc2_clk rising clock edge
ns
13.19
8.4
ns
th(clkH-dV)
ns
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表 7-104. Switching Characteristics for MMC2 - JC64 Standard SDR Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
SSDR1 fop(clk)
SSDR2H tw(clkH)
Operating frequency, mmc2_clk
Pulse duration, mmc2_clk high
24
0.5*P-
0.172 (1)
SSDR2L tw(clkL)
Pulse duration, mmc2_clk low
0.5*P-
ns
0.172 (1)
SSDR3 td(clkL-cmdV)
SSDR4 td(clkL-dV)
Delay time, mmc2_clk falling clock edge to mmc2_cmd transition
Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition
-16.96
-16.96
16.96
16.96
ns
ns
(1) P = output mmc2_clk period in ns
SSDR2
SSDR1
SSDR2
mmc2_clk
SSDR6
SSDR8
SSDR5
mmc2_cmd
SSDR7
mmc2_dat[7:0]
SPRS906_TIMING_MMC2_01
图 7-68. MMC/SD/SDIO in - Standard JC64 - Receiver Mode
SSDR2
SSDR2
SSDR1
SSDR3
SSDR4
mmc2_clk
mmc2_cmd
mmc2_dat[7:0]
SPRS906_TIMING_MMC2_02
图 7-69. MMC/SD/SDIO in - Standard JC64 - Transmitter Mode
7.23.2.2 High-speed JC64 SDR, 8-bit data, half cycle
表 7-105 and 表 7-106 present Timing requirements and Switching characteristics for MMC2 - High speed
SDR in receiver and transmitter mode (see 图 7-70 and 图 7-71).
表 7-105. Timing Requirements for MMC2 - JC64 High Speed SDR Mode
NO.
PARAMETER
DESCRIPTION
MIN
5.6
2.6
5.6
2.6
MAX
UNIT
ns
JC643 tsu(cmdV-clkH)
JC644 th(clkH-cmdV)
JC647 tsu(dV-clkH)
JC648 th(clkH-dV)
Setup time, mmc2_cmd valid before mmc2_clk rising clock edge
Hold time, mmc2_cmd valid after mmc2_clk rising clock edge
Setup time, mmc2_dat[7:0] valid before mmc2_clk rising clock edge
Hold time, mmc2_dat[7:0] valid after mmc2_clk rising clock edge
ns
ns
ns
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表 7-106. Switching Characteristics for MMC2 - JC64 High Speed SDR Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
JC641 fop(clk)
JC642H tw(clkH)
Operating frequency, mmc2_clk
Pulse duration, mmc2_clk high
48
0.5*P-
0.172 (1)
JC642L tw(clkL)
Pulse duration, mmc2_clk low
0.5*P-
ns
0.172 (1)
JC645 td(clkL-cmdV)
JC646 td(clkL-dV)
Delay time, mmc2_clk falling clock edge to mmc2_cmd transition
Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition
-6.64
-6.64
6.64
6.64
ns
ns
(1) P = output mmc2_clk period in ns
JC641
JC642L
JC642H
mmc2_clk
mmc2_cmd
mmc2_dat[7:0]
JC643
JC644
JC647
JC648
SPRS906_TIMING_MMC2_03
图 7-70. MMC/SD/SDIO in - High Speed JC64 - Receiver Mode
JC641
JC642L
JC642H
mmc2_clk
mmc2_cmd
mmc2_dat[7:0]
JC645
JC645
JC646
JC646
MMC2_04
图 7-71. MMC/SD/SDIO in - High Speed JC64 - Transmitter Mode
7.23.2.3 High-speed HS200 JEDS84, 8-bit data, half cycle
表 7-107 presents Switching characteristics for MMC2 - HS200 in transmitter mode (see 图 7-72).
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表 7-107. Switching Characteristics for MMC2 - JEDS84 HS200 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
HS2001 fop(clk)
HS2002H tw(clkH)
Operating frequency, mmc2_clk
Pulse duration, mmc2_clk high
192
0.5*P-
0.172 (1)
HS2002L tw(clkL)
Pulse duration, mmc2_clk low
0.5*P-
ns
0.172 (1)
HS2005 td(clkL-cmdV)
HS2006 td(clkL-dV)
Delay time, mmc2_clk falling clock edge to mmc2_cmd transition
Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition
-1.136
-1.136
0.536
0.536
ns
ns
(1) P = output mmc2_clk period in ns
HS2001
HS2002H
HS2002L
mmc2_clk
mmc2_cmd
mmc2_dat[7:0]
HS2005
HS2006
HS2005
HS2006
MMC2_05
图 7-72. eMMC in - HS200 SDR - Transmitter Mode
7.23.2.4 High-speed JC64 DDR, 8-bit data
表 7-108 and 表 7-109 present Timing requirements and Switching characteristics for MMC2 - High speed
DDR in receiver and transmitter mode (see 图 7-73 and 图 7-74).
表 7-108. Timing Requirements for MMC2 - JC64 High Speed DDR Mode
NO.
PARAMETER
DESCRIPTION
MODE
MIN
1.8
MAX UNIT
DDR3 tsu(cmdV-clk)
Setup time, mmc2_cmd valid before mmc2_clk
transition
ns
DDR4 th(clk-cmdV)
DDR7 tsu(dV-clk)
Hold time, mmc2_cmd valid after mmc2_clk transition
1.6
1.8
ns
ns
Setup time, mmc2_dat[7:0] valid before mmc2_clk
transition
DDR8 th(clk-dV)
Hold time, mmc2_dat[7:0] valid after mmc2_clk
transition
Pad Loopback (1.8V and
3.3V), Boot
1.6
ns
ns
ns
ns
ns
Internal Loopback (1.8V
with MMC2_VIRTUAL2)
1.86
1.95
Internal Loopback (3.3V
with MMC2_VIRTUAL2)
Internal Loopback (1.8V
with MMC2_MANUAL2)
Internal Loopback (3.3V
with MMC2_MANUAL2)
1.6
表 7-109. Switching Characteristics for MMC2 - JC64 High Speed DDR Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
DDR1
fop(clk)
Operating frequency, mmc2_clk
Pulse duration, mmc2_clk high
48
(1)
DDR2H tw(clkH)
0.5*P-
0.172
(1)
DDR2L tw(clkL)
Pulse duration, mmc2_clk low
0.5*P-
0.172
ns
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Timing Requirements and Switching Characteristics
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表 7-109. Switching Characteristics for MMC2 - JC64 High Speed DDR Mode (continued)
NO.
PARAMETER
td(clk-cmdV)
td(clk-dV)
DESCRIPTION
MIN
2.9
MAX
7.14
7.14
UNIT
ns
DDR5
DDR6
Delay time, mmc2_clk transition to mmc2_cmd transition
Delay time, mmc2_clk transition to mmc2_dat[7:0] transition
2.9
ns
(1) P = output mmc2_clk period in ns
DDR1
DDR2H
DDR2L
DDR3
mmc2_clk
DDR4
mmc2_cmd
DDR8
DDR8
DDR8
DDR7
DDR7
DDR7
DDR7
mmc2_dat[7:0]
SPRS906_TIMING_MMC2_07
图 7-73. MMC/SD/SDIO in - High Speed DDR JC64 - Receiver Mode
DDR1
DDR2
DDR2
DDR5
mmc2_clk
DDR5
DDR5
DDR5
mmc2_cmd
DDR6
DDReMMC6
DDReMMC6
DDR6
DDR6
DDR6
mmc2_dat[7:0]
SPRS906_TIMING_MMC2_08
图 7-74. MMC/SD/SDIO in - High Speed DDR JC64 - Transmitter Mode
注
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in 表 4-3 and described in Device TRM, Control
Module Chapter.
Virtual IO Timings Modes must be used to guaranteed some IO timings for MMC2. See 表 7-2 Modes
Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See 表 7-110 Virtual
Functions Mapping for MMC2 for a definition of the Virtual modes.
表 7-110 presents the values for DELAYMODE bitfield.
表 7-110. Virtual Functions Mapping for MMC2
BALL
BALL NAME
Delay Mode Value
MUXMODE
1
MMC2_VIRTUAL2
H6
K7
gpmc_cs1
gpmc_a19
13
13
mmc2_cmd
mmc2_dat4
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表 7-110. Virtual Functions Mapping for MMC2 (continued)
BALL
BALL NAME
Delay Mode Value
MUXMODE
MMC2_VIRTUAL2
1
M7
J5
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
gpmc_a25
gpmc_a26
gpmc_a27
13
13
13
13
13
13
13
13
mmc2_dat5
mmc2_dat6
mmc2_dat7
mmc2_clk
mmc2_dat0
mmc2_dat1
mmc2_dat2
mmc2_dat3
K6
J7
J4
J6
H4
H5
注
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section Manual IO Timing Modes of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information see the Control Module chapter in the Device TRM.
Manual IO Timings Modes must be used to guaranteed some IO timings for MMC2. See 表 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See 表 7-111 Manual
Functions Mapping for MMC2 for a definition of the Manual modes.
表 7-111 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
表 7-111. Manual Functions Mapping for MMC2
BAL BALL NAME
L
MMC2_MANUAL1
MMC2_MANUAL2
MMC2_MANUAL3
CFG REGISTER
MUXMODE
1
A_DELAY G_DELAY A_DELAY G_DELAY A_DELAY G_DELAY
(ps)
0
(ps)
0
(ps)
0
(ps)
(ps)
(ps)
K7
M7
J5
gpmc_a19
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
gpmc_a25
gpmc_a26
gpmc_a27
gpmc_cs1
14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CFG_GPMC_A19_IN mmc2_dat4
CFG_GPMC_A20_IN mmc2_dat5
CFG_GPMC_A21_IN mmc2_dat6
CFG_GPMC_A22_IN mmc2_dat7
119
0
0
127
22
72
410
82
0
0
0
0
K6
J7
18
894
30
0
0
0
0
4000
CFG_GPMC_A23_IN
mmc2_clk
J4
0
0
0
0
0
0
CFG_GPMC_A24_IN mmc2_dat0
CFG_GPMC_A25_IN mmc2_dat1
CFG_GPMC_A26_IN mmc2_dat2
CFG_GPMC_A27_IN mmc2_dat3
CFG_GPMC_CS1_IN mmc2_cmd
J6
0
H4
H5
H6
23
0
0
77
0
0
0
0
0
K7
M7
J5
gpmc_a19
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
gpmc_a25
gpmc_a26
gpmc_a27
gpmc_cs1
152
206
78
2
0
0
0
0
0
0
0
0
0
0
152
206
78
2
0
0
0
0
0
0
0
0
0
0
285
189
0
0
0
CFG_GPMC_A19_OUT mmc2_dat4
CFG_GPMC_A20_OUT mmc2_dat5
CFG_GPMC_A21_OUT mmc2_dat6
CFG_GPMC_A22_OUT mmc2_dat7
CFG_GPMC_A23_OUT mmc2_clk
CFG_GPMC_A24_OUT mmc2_dat0
CFG_GPMC_A25_OUT mmc2_dat1
CFG_GPMC_A26_OUT mmc2_dat2
CFG_GPMC_A27_OUT mmc2_dat3
CFG_GPMC_CS1_OUT mmc2_cmd
120
70
360
0
K6
J7
0
266
0
266
0
730
0
J4
J6
0
0
0
0
H4
H5
H6
43
0
43
0
70
0
0
0
0
0
0
120
K7
gpmc_a19
0
0
0
0
0
0
CFG_GPMC_A19_OEN mmc2_dat4
306
Timing Requirements and Switching Characteristics
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表 7-111. Manual Functions Mapping for MMC2 (continued)
BAL BALL NAME
L
MMC2_MANUAL1
MMC2_MANUAL2
MMC2_MANUAL3
CFG REGISTER
MUXMODE
1
A_DELAY G_DELAY A_DELAY G_DELAY A_DELAY G_DELAY
(ps)
0
(ps)
0
(ps)
0
(ps)
0
(ps)
231
39
(ps)
0
M7
J5
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a24
gpmc_a25
gpmc_a26
gpmc_a27
gpmc_cs1
CFG_GPMC_A20_OEN mmc2_dat5
CFG_GPMC_A21_OEN mmc2_dat6
CFG_GPMC_A22_OEN mmc2_dat7
CFG_GPMC_A24_OEN mmc2_dat0
CFG_GPMC_A25_OEN mmc2_dat1
CFG_GPMC_A26_OEN mmc2_dat2
CFG_GPMC_A27_OEN mmc2_dat3
0
0
0
0
0
K6
J4
0
0
0
0
91
0
0
0
0
0
176
0
0
J6
0
0
0
0
0
H4
H5
H6
0
0
0
0
101
0
0
0
0
0
0
0
0
0
0
0
360
0
CFG_GPMC_CS1_OE mmc2_cmd
N
7.23.3 MMC3 and MMC4-SDIO/SD
MMC3 and MMC4 interfaces are compliant with the SDIO3.0 standard v1.0, SD Part E1 and for generic
SDIO devices, it supports the following applications:
•
•
•
MMC3 8-bit data and MMC4 4-bit data, SD Default speed, SDR
MMC3 8-bit data and MMC4 4-bit data, SD High speed, SDR
MMC3 8-bit data and MMC4 4-bit data, UHS-1 SDR12 (SD Standard v3.01), 4-bit data, SDR, half
cycle
•
•
MMC3 8-bit data and MMC4 4-bit data, UHS-I SDR25 (SD Standard v3.01), 4-bit data, SDR, half cycle
MMC3 8-bit data, UHS-I SDR50
注
The eMMC/SD/SDIOj (j = 3 to 4) controller is also referred to as MMCj.
注
For more information, see the MMC/SDIO chapter of the Device TRM.
7.23.3.1 MMC3 and MMC4, SD Default Speed
图 7-75, 图 7-76, and 表 7-112 through 表 7-115 present Timing requirements and Switching
characteristics for MMC3 and MMC4 - SD Default speed in receiver and transmitter mode.
(1)
表 7-112. Timing Requirements for MMC3 - Default Speed Mode
NO.
DS5
DS6
DS7
DS8
PARAMETER
tsu(cmdV-clkH)
th(clkH-cmdV)
tsu(dV-clkH)
DESCRIPTION
MIN
5.11
MAX
UNIT
ns
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
20.46
5.11
ns
ns
th(clkH-dV)
20.46
ns
(1) i in [i:0] = 7
(2)
表 7-113. Switching Characteristics for MMC3 - SD/SDIO Default Speed Mode
NO.
DS0
DS1
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
fop(clk)
tw(clkH)
Operating frequency, mmc3_clk
Pulse duration, mmc3_clk high
24
0.5*P-
0.270
(1)
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表 7-113. Switching Characteristics for MMC3 - SD/SDIO Default Speed Mode (continued)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
DS2
tw(clkL)
Pulse duration, mmc3_clk low
0.5*P-
ns
(1)
0.270
-14.93
-14.93
DS3
DS4
td(clkL-cmdV)
td(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition
14.93
14.93
ns
ns
(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
(1)
表 7-114. Timing Requirements for MMC4 - Default Speed Mode
NO.
DS5
DS6
DS7
DS8
PARAMETER
tsu(cmdV-clkH)
th(clkH-cmdV)
tsu(dV-clkH)
DESCRIPTION
MIN
5.11
MAX
UNIT
ns
Setup time, mmc4_cmd valid before mmc4_clk rising clock edge
Hold time, mmc4_cmd valid after mmc4_clk rising clock edge
Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge
Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge
20.46
5.11
ns
ns
th(clkH-dV)
20.46
ns
(1) i in [i:0] = 3
(2)
表 7-115. Switching Characteristics for MMC4 - Default Speed Mode
NO.
DS0
DS1
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
fop(clk)
tw(clkH)
Operating frequency, mmc4_clk
Pulse duration, mmc4_clk high
24
0.5*P-
0.270
(1)
DS2
tw(clkL)
Pulse duration, mmc4_clk low
0.5*P-
ns
(1)
0.270
-14.93
-14.93
DS3
DS4
td(clkL-cmdV)
td(clkL-dV)
Delay time, mmc4_clk falling clock edge to mmc4_cmd transition
Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition
14.93
14.93
ns
ns
(1) P = output mmc4_clk period in ns
(2) i in [i:0] = 3
DS2
DS1
DS0
mmcj_clk
mmcj_cmd
DS6
DS5
DS8
DS7
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_07
图 7-75. MMC/SD/SDIOj in - Default Speed - Receiver Mode
308
Timing Requirements and Switching Characteristics
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DS2
DS1
DS0
mmcj_clk
DS3
mmcj_cmd
DS4
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_08
图 7-76. MMC/SD/SDIOj in - Default Speed - Transmitter Mode
7.23.3.2 MMC3 and MMC4, SD High Speed
图 7-77, 图 7-78, and 表 7-116 through 表 7-119 present Timing requirements and Switching
characteristics for MMC3 and MMC4 - SD and SDIO High speed in receiver and transmitter mode.
(1)
表 7-116. Timing Requirements for MMC3 - SD/SDIO High Speed Mode
NO.
HS3
HS4
HS7
HS8
PARAMETER
tsu(cmdV-clkH)
th(clkH-cmdV)
tsu(dV-clkH)
DESCRIPTION
MIN
5.3
MAX
UNIT
ns
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
2.6
5.3
2.6
ns
ns
th(clkH-dV)
ns
(1) i in [i:0] = 7
(2)
表 7-117. Switching Characteristics for MMC3 - SD/SDIO High Speed Mode
NO.
HS1
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
fop(clk)
tw(clkH)
Operating frequency, mmc3_clk
Pulse duration, mmc3_clk high
48
HS2H
0.5*P-
0.270
(1)
HS2L
tw(clkL)
Pulse duration, mmc3_clk low
0.5*P-
0.270
ns
(1)
HS5
HS6
td(clkL-cmdV)
td(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition
-7.6
3.6
3.6
ns
ns
-7.6
(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
(1)
表 7-118. Timing Requirements for MMC4 - High Speed Mode
NO.
HS3
HS4
HS7
HS8
PARAMETER
tsu(cmdV-clkH)
th(clkH-cmdV)
tsu(dV-clkH)
DESCRIPTION
MIN
5.3
1.6
5.3
1.6
MAX
UNIT
ns
Setup time, mmc4_cmd valid before mmc4_clk rising clock edge
Hold time, mmc4_cmd valid after mmc4_clk rising clock edge
Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge
Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge
ns
ns
th(clkH-dV)
ns
(1) i in [i:0] = 3
(2)
表 7-119. Switching Characteristics for MMC4 - High Speed Mode
NO.
HS1
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
fop(clk)
tw(clkH)
Operating frequency, mmc4_clk
Pulse duration, mmc4_clk high
48
HS2H
0.5*P-
0.270
(1)
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表 7-119. Switching Characteristics for MMC4 - High Speed Mode (continued)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
HS2L
tw(clkL)
Pulse duration, mmc4_clk low
0.5*P-
0.270
ns
(1)
HS5
HS6
td(clkL-cmdV)
td(clkL-dV)
Delay time, mmc4_clk falling clock edge to mmc4_cmd transition
Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition
-8.8
6.6
6.6
ns
ns
-8.8
(1) P = output mmc4_clk period in ns
(2) i in [i:0] = 3
HS1
HS2H
HS2L
mmcj_clk
mmcj_cmd
HS4
HS3
HS7
HS8
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_09
图 7-77. MMC/SD/SDIOj in - High Speed - Receiver Mode
HS1
HS2H
HS2L
mmcj_clk
mmcj_cmd
HS5
HS5
HS6
HS6
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_10
图 7-78. MMC/SD/SDIOj in - High Speed - Transmitter Mode
7.23.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
图 7-79, 图 7-80, and 表 7-120, through 表 7-123 present Timing requirements and Switching
characteristics for MMC3 and MMC4 - SD and SDIO SDR12 in receiver and transmitter mode.
(1)
表 7-120. Timing Requirements for MMC3 - SDR12 Mode
NO.
PARAMETER
DESCRIPTION
MIN
25.99
1.6
MAX
UNIT
ns
SDR125 tsu(cmdV-clkH)
SDR126 th(clkH-cmdV)
SDR127 tsu(dV-clkH)
SDR128 th(clkH-dV)
(1) i in [i:0] = 7
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
ns
25.99
1.6
ns
ns
(2)
表 7-121. Switching Characteristics for MMC3 - SDR12 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
SDR120 fop(clk)
SDR121 tw(clkH)
Operating frequency, mmc3_clk
Pulse duration, mmc3_clk high
24
0.5*P-
0.270
(1)
310
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表 7-121. Switching Characteristics for MMC3 - SDR12 Mode (continued)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
SDR122 tw(clkL)
Pulse duration, mmc3_clk low
0.5*P-
ns
(1)
0.270
-19.13
-19.13
SDR123 td(clkL-cmdV)
SDR124 td(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition
16.93
16.93
ns
ns
(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
(1)
表 7-122. Timing Requirements for MMC4 - SDR12 Mode
NO.
PARAMETER
DESCRIPTION
MIN
25.99
1.6
MAX
UNIT
ns
SDR125 tsu(cmdV-clkH)
SDR126 th(clkH-cmdV)
SDR127 tsu(dV-clkH)
SDR128 th(clkH-dV)
(1) j in [i:0] = 3
Setup time, mmc4_cmd valid before mmc4_clk rising clock edge
Hold time, mmc4_cmd valid after mmc4_clk rising clock edge
Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge
Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge
ns
25.99
1.6
ns
ns
(2)
表 7-123. Switching Characteristics for MMC4 - SDR12 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
SDR120 fop(clk)
SDR121 tw(clkH)
Operating frequency, mmc4_clk
Pulse duration, mmc4_clk high
24
0.5*P-
0.270
(1)
SDR122 tw(clkL)
Pulse duration, mmc4_clk low
0.5*P-
ns
(1)
0.270
-19.13
-19.13
SDR125 td(clkL-cmdV)
SDR126 td(clkL-dV)
Delay time, mmc4_clk falling clock edge to mmc4_cmd transition
Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition
16.93
16.93
ns
ns
(1) P = output mmc4_clk period in ns
(2) j in [i:0] = 3
SDR122
SDR121
SDR120
mmcj_clk
mmcj_cmd
SDR126
SDR125
SDR128
SDR127
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_11
图 7-79. MMC/SD/SDIOj in - SDR12 - Receiver Mode
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SDR122
SDR121
SDR120
mmcj_clk
SDR123
SDR124
mmcj_cmd
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_12
图 7-80. MMC/SD/SDIOj in - SDR12 - Transmitter Mode
7.23.3.4 MMC3 and MMC4, SD SDR25 Mode
图 7-81, 图 7-82, and 表 7-124, through 表 7-127 present Timing requirements and Switching
characteristics for MMC3 and MMC4 - SD and SDIO SDR25 in receiver and transmitter mode.
(1)
表 7-124. Timing Requirements for MMC3 - SDR25 Mode
NO.
PARAMETER
DESCRIPTION
MIN
5.3
1.6
5.3
1.6
MAX
UNIT
ns
SDR253 tsu(cmdV-clkH)
SDR254 th(clkH-cmdV)
SDR257 tsu(dV-clkH)
SDR258 th(clkH-dV)
(1) i in [i:0] = 7
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
ns
ns
ns
(2)
表 7-125. Switching Characteristics for MMC3 - SDR25 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
SDR251 fop(clk)
Operating frequency, mmc3_clk
Pulse duration, mmc3_clk high
48
SDR252 tw(clkH)
H
0.5*P-
0.270
(1)
SDR252L tw(clkL)
Pulse duration, mmc3_clk low
0.5*P-
0.270
ns
(1)
SDR255 td(clkL-cmdV)
SDR256 td(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition
-8.8
6.6
6.6
ns
ns
-8.8
(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
(1)
表 7-126. Timing Requirements for MMC4 - SDR25 Mode
NO.
PARAMETER
DESCRIPTION
MIN
5.3
1.6
5.3
1.6
MAX
UNIT
ns
SDR255 tsu(cmdV-clkH)
SDR256 th(clkH-cmdV)
SDR257 tsu(dV-clkH)
SDR258 th(clkH-dV)
(1) i in [i:0] = 3
Setup time, mmc4_cmd valid before mmc4_clk rising clock edge
Hold time, mmc4_cmd valid after mmc4_clk rising clock edge
Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge
Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge
ns
ns
ns
(2)
表 7-127. Switching Characteristics for MMC4 - SDR25 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
SDR251 fop(clk)
Operating frequency, mmc4_clk
Pulse duration, mmc4_clk high
48
SDR252 tw(clkH)
H
0.5*P-
0.270
(1)
312
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表 7-127. Switching Characteristics for MMC4 - SDR25 Mode (continued)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
SDR252L tw(clkL)
Pulse duration, mmc4_clk low
0.5*P-
0.270
ns
(1)
SDR255 td(clkL-cmdV)
SDR256 td(clkL-dV)
Delay time, mmc4_clk falling clock edge to mmc4_cmd transition
Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition
-8.8
6.6
6.6
ns
ns
-8.8
(1) P = output mmc4_clk period in ns
(2) i in [i:0] = 3
SDR251
SDR252L
SDR253
SDR252H
SDR254
mmcj_clk
mmcj_cmd
SDR257
SDR258
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_13
图 7-81. MMC/SD/SDIOj in - SDR25 - Receiver Mode
SDR251
SDR252H
SDR252L
SDR255
mmcj_clk
mmcj_cmd
SDR255
SDR256
SDR256
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_14
图 7-82. MMC/SD/SDIOj in - SDR25 - Transmitter Mode
7.23.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
图 7-83, 图 7-84, 表 7-128, and 表 7-129 present Timing requirements and Switching characteristics for
MMC3 - SDIO High speed SDR50 in receiver and transmitter mode.
(1)
表 7-128. Timing Requirements for MMC3 - SDR50 Mode
NO.
PARAMETER
DESCRIPTION
MIN
1.48
MAX
UNIT
ns
SDR503 tsu(cmdV-clkH)
SDR504 th(clkH-cmdV)
SDR507 tsu(dV-clkH)
SDR508 th(clkH-dV)
(1) i in [i:0] = 7
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
1.6
1.48
1.6
ns
ns
ns
(2)
表 7-129. Switching Characteristics for MMC3 - SDR50 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
64
UNIT
MHz
ns
SDR501 fop(clk)
Operating frequency, mmc3_clk
Pulse duration, mmc3_clk high
SDR502 tw(clkH)
H
0.5*P-
0.270
(1)
SDR502L tw(clkL)
Pulse duration, mmc3_clk low
0.5*P-
0.270
ns
(1)
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表 7-129. Switching Characteristics for MMC3 - SDR50 Mode (continued)
NO.
PARAMETER
DESCRIPTION
MIN
-3.66
-3.66
MAX
UNIT
ns
SDR505 td(clkL-cmdV)
SDR506 td(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition
1.46
1.46
ns
(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
SDR501
SDR502L
SDR502H
SDR504
mmcj_clk
mmcj_cmd
SDR503
SDR507
SDR508
mmcj_dat[7:0]
SPRS906_TIMING_MMC3_05
图 7-83. MMC/SD/SDIOj in - High Speed SDR50 - Receiver Mode
SDR501
SDR502H
SDR502L
SDR505
mmcj_clk
mmcj_cmd
SDR505
SDR506
SDR506
mmcj_dat[7:0]
SPRS906_TIMING_MMC3_06
图 7-84. MMC/SD/SDIOj in - High Speed SDR50 - Transmitter Mode
注
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section Manual IO Timing Modes of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information see the Control Module chapter in the Device TRM.
Manual IO Timings Modes must be used to guaranteed some IO timings for MMC3. See 表 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See 表 7-130 Manual
Functions Mapping for MMC3 for a definition of the Manual modes.
表 7-130 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
表 7-130. Manual Functions Mapping for MMC3
BALL
BALL NAME
MMC3_MANUAL1
CFG REGISTER
MUXMODE
0
A_DELAY (ps)
G_DELAY (ps)
AD4
AD4
AC4
AC4
AC4
AC7
mmc3_clk
mmc3_clk
1085
1269
0
21
0
CFG_MMC3_CLK_IN
CFG_MMC3_CLK_OUT
CFG_MMC3_CMD_IN
CFG_MMC3_CMD_OEN
CFG_MMC3_CMD_OUT
CFG_MMC3_DAT0_IN
mmc3_clk
mmc3_clk
mmc3_cmd
mmc3_cmd
mmc3_cmd
mmc3_dat0
mmc3_cmd
mmc3_cmd
mmc3_cmd
mmc3_dat0
0
128
98
0
0
0
0
314
Timing Requirements and Switching Characteristics
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表 7-130. Manual Functions Mapping for MMC3 (continued)
BALL NAME
MMC3_MANUAL1
CFG REGISTER
MUXMODE
0
A_DELAY (ps)
G_DELAY (ps)
AC7
AC7
AC6
AC6
AC6
AC9
AC9
AC9
AC3
AC3
AC3
AC8
AC8
AC8
AD6
AD6
AD6
AB8
AB8
AB8
AB5
AB5
AB5
mmc3_dat0
mmc3_dat0
mmc3_dat1
mmc3_dat1
mmc3_dat1
mmc3_dat2
mmc3_dat2
mmc3_dat2
mmc3_dat3
mmc3_dat3
mmc3_dat3
mmc3_dat4
mmc3_dat4
mmc3_dat4
mmc3_dat5
mmc3_dat5
mmc3_dat5
mmc3_dat6
mmc3_dat6
mmc3_dat6
mmc3_dat7
mmc3_dat7
mmc3_dat7
362
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CFG_MMC3_DAT0_OEN
CFG_MMC3_DAT0_OUT
CFG_MMC3_DAT1_IN
CFG_MMC3_DAT1_OEN
CFG_MMC3_DAT1_OUT
CFG_MMC3_DAT2_IN
CFG_MMC3_DAT2_OEN
CFG_MMC3_DAT2_OUT
CFG_MMC3_DAT3_IN
CFG_MMC3_DAT3_OEN
CFG_MMC3_DAT3_OUT
CFG_MMC3_DAT4_IN
CFG_MMC3_DAT4_OEN
CFG_MMC3_DAT4_OUT
CFG_MMC3_DAT5_IN
CFG_MMC3_DAT5_OEN
CFG_MMC3_DAT5_OUT
CFG_MMC3_DAT6_IN
CFG_MMC3_DAT6_OEN
CFG_MMC3_DAT6_OUT
CFG_MMC3_DAT7_IN
CFG_MMC3_DAT7_OEN
CFG_MMC3_DAT7_OUT
mmc3_dat0
mmc3_dat0
mmc3_dat1
mmc3_dat1
mmc3_dat1
mmc3_dat2
mmc3_dat2
mmc3_dat2
mmc3_dat3
mmc3_dat3
mmc3_dat3
mmc3_dat4
mmc3_dat4
mmc3_dat4
mmc3_dat5
mmc3_dat5
mmc3_dat5
mmc3_dat6
mmc3_dat6
mmc3_dat6
mmc3_dat7
mmc3_dat7
mmc3_dat7
7
333
0
0
402
0
203
549
1
121
440
206
336
283
174
320
443
0
2
344
0
注
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in 表 4-3 and described in Device TRM, Control
Module Chapter.
7.24 General-Purpose Interface (GPIO)
The general-purpose interface combines eight general-purpose input/output (GPIO) banks. Each GPIO
module provides up to 32 dedicated general-purpose pins with input and output capabilities; thus, the
general-purpose interface supports up to 215 pins.
These pins can be configured for the following applications:
•
•
•
Data input (capture)/output (drive)
Keyboard interface with a debounce cell
Interrupt generation in active mode upon the detection of external events. Detected events are
processed by two parallel independent interrupt-generation submodules to support biprocessor
operations
•
Wake-up request generation in idle mode upon the detection of external events
注
For more information, see the General-Purpose Interface chapter of the Device TRM.
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注
The general-purpose input/output i (i = 1 to 8) bank is also referred to as GPIOi.
7.25 System and Miscellaneous interfaces
The Device includes the following System and Miscellaneous interfaces:
•
•
•
•
Sysboot Interface
System DMA Interface
Interrupt Controllers (INTC) Interface
Observability Signal (OBS) Interface
7.26 Test Interfaces
The Device includes the following Test interfaces:
•
•
•
IEEE 1149.1 Standard-Test-Access Port (JTAG)
Trace Port Interface Unit (TPIU)
Advanced Event Triggering Interface (AET)
7.26.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
The JTAG (IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture)
interface is used for BSDL testing and emulation of the device. The trstn pin only needs to be released
when it is necessary to use a JTAG controller to debug the device or exercise the device's boundary scan
functionality. For maximum reliability, the device includes an internal Pulldown (IPD) on the trstn pin to
ensure that trstn is always asserted upon power up and the device's internal emulation logic is always
properly initialized. JTAG controllers from Texas Instruments actively drive trstn high. However, some
third-party JTAG controllers may not drive trstn high but expect the use of a Pullup resistor on trstn. When
using this type of JTAG controller, assert trstn to initialize the device after powerup and externally drive
trstn high before attempting any emulation or boundary-scan operations.
The main JTAG features include:
•
•
•
•
•
32KB embedded trace buffer (ETB)
5-pin system trace interface for debug
Supports Advanced Event Triggering (AET)
All processors can be emulated via JTAG ports
All functions on EMU pins of the device:
–
–
EMU[1:0] - cross-triggering, boot mode (WIR), STM trace
EMU[4:2] - STM trace only (single direction)
7.26.1.1 JTAG Electrical Data/Timing
表 7-131, 表 7-132 and 图 7-85 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
表 7-131. Timing Requirements for IEEE 1149.1 JTAG
NO.
1
PARAMETER
tc(TCK)
DESCRIPTION
MIN
62.29
24.92
24.92
6.23
MAX
UNIT
ns
Cycle time, TCK
1a
1b
tw(TCKH)
Pulse duration, TCK high (40% of tc)
Pulse duration, TCK low (40% of tc)
Input setup time, TDI valid to TCK high
Input setup time, TMS valid to TCK high
ns
tw(TCKL)
ns
tsu(TDI-TCK)
tsu(TMS-TCK)
ns
3
6.23
ns
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表 7-131. Timing Requirements for IEEE 1149.1 JTAG (continued)
NO.
PARAMETER
th(TCK-TDI)
th(TCK-TMS)
DESCRIPTION
Input hold time, TDI valid from TCK high
Input hold time, TMS valid from TCK high
MIN
MAX
UNIT
ns
31.15
31.15
4
ns
表 7-132. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
NO.
PARAMETER
td(TCKL-TDOV)
DESCRIPTION
Delay time, TCK low to TDO valid
MIN
MAX
UNIT
2
0
30.5
ns
1
1a
1b
TCK
TDO
2
3
4
TDI/TMS
SPRS906_TIMING_JTAG_01
图 7-85. JTAG Timing
表 7-133, 表 7-134 and 图 7-86 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
表 7-133. Timing Requirements for IEEE 1149.1 JTAG With RTCK
NO.
1
PARAMETER
tc(TCK)
DESCRIPTION
MIN
62.29
24.92
24.92
6.23
MAX
UNIT
ns
Cycle time, TCK
1a
1b
tw(TCKH)
Pulse duration, TCK high (40% of tc)
Pulse duration, TCK low (40% of tc)
Input setup time, TDI valid to TCK high
Input setup time, TMS valid to TCK high
Input hold time, TDI valid from TCK high
Input hold time, TMS valid from TCK high
ns
tw(TCKL)
ns
tsu(TDI-TCK)
tsu(TMS-TCK)
th(TCK-TDI)
th(TCK-TMS)
ns
3
4
6.23
ns
31.15
31.15
ns
ns
表 7-134. Switching Characteristics Over Recommended Operating Conditions for
IEEE 1149.1 JTAG With RTCK
NO.
PARAMETER
td(TCK-RTCK)
DESCRIPTION
MIN
MAX
UNIT
Delay time, TCK to RTCK with no selected subpaths (i.e. ICEPick is
the only tap selected - when the Arm is in the scan chain, the delay
time is a function of the Arm functional clock).
5
0
27
ns
6
7
8
tc(RTCK)
Cycle time, RTCK
62.29
24.92
24.92
ns
ns
ns
tw(RTCKH)
tw(RTCKL)
Pulse duration, RTCK high (40% of tc)
Pulse duration, RTCK low (40% of tc)
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5
TCK
6
7
8
RTCK
SPRS906_TIMING_JTAG_02
图 7-86. JTAG With RTCK Timing
7.26.2 Trace Port Interface Unit (TPIU)
CAUTION
The I/O timings provided in this section are valid only if signals within a single
IOSET are used. The IOSETs are defined in 表 7-136.
7.26.2.1 TPIU PLL DDR Mode
表 7-135 and 图 7-87 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
表 7-135. Switching Characteristics for TPIU
NO.
PARAMETER
tc(clk)
DESCRIPTION
Cycle time, TRACECLK period
MIN
5.56
-1.61
MAX
UNIT
ns
TPIU1
TPIU4
td(clk-ctlV)
Skew time, TRACECLK transition to TRACECTL
transition
1.98
1.98
ns
TPIU5
td(clk-dataV)
Skew time, TRACECLK transition to TRACEDATA[17:0]
-1.61
ns
TPIU1
TPIU2
TPIU3
TRACECLK
TPIU4
TPIU4
TRACECTL
TPIU5
TPIU5
TRACEDATA[X:0]
SPRS906_TIMING_TIMER_01
图 7-87. TPIU-PLL DDR Transmit Mode(1)
(1) In d[X:0], X is equal to 15 or 17.
In 表 7-136 are presented the specific groupings of signals (IOSET) for use with TPIU signals.
表 7-136. TPIU IOSETs
SIGNALS
IOSET1
IOSET2
BALL
E6
MUX
BALL
A10
B9
MUX
emu19
emu18
5
5
2
2
F5
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表 7-136. TPIU IOSETs (continued)
SIGNALS
IOSET1
IOSET2
BALL
E4
MUX
5
BALL
A9
MUX
2
emu17
emu16
emu15
emu14
emu13
emu12
emu11
emu10
emu9
emu8
emu7
emu6
emu5
emu4
emu3
emu2
emu1
emu0
C1
5
C9
2
F4
5
A8
2
D2
5
C7
2
E2
5
C8
2
D1
5
C6
2
F3
5
A5
2
F2
5
D8
2
G6
G1
H7
5
E7
2
5
F8
2
5
F9
2
G2
E1
5
E9
2
5
G11
A7
2
A7
2
2
D7
2
D7
2
F10
D24
G21
2
F10
D24
G21
2
0
0
0
0
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8 Applications, Implementation, and Layout
注
Information in the following Applications section is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI's customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
8.1 Introduction
This chapter is intended to communicate, guide and illustrate a PCB design strategy resulting in a PCB
that can support TI’s latest Application Processor. This Processor is a high-performance processor
designed for automotive Infotainment based on enhanced OMAP™ architecture integrated on a 28-nm
CMOS process technology.
These guidelines first focus on designing a robust Power Delivery Network (PDN) which is essential to
achieve the desirable high performance processing available on Device. The general principles and step-
by-step approach for implementing good power integrity (PI) with specific requirements will be described
for the key Device power domains.
TI strongly believes that simulating a PCB’s proposed PDN is required for first pass PCB design success.
Key Device processor high-current power domains need to be evaluated for Power Rail IR Drop,
Decoupling Capacitor Loop-Inductance and Power Rail Target Impedance. Only then can a PCB’s PDN
performance be truly accessed by comparing these model PI parameters vs. TI’s recommended values.
Ultimately for any high-volume product, TI recommends conducting a “Processor PDN Validation” test on
prototype PCBs across processor “split lots” to verify PDN robustness meets desired performance goals
for each customer’s worst-case scenario. Please contact your TI representative to receive guidance on
PDN PI modeling and validation testing.
Likewise, the methodology and requirements needed to route Device high-speed, differential interfaces
(i.e. USB2.0, USB3.0, HDMI, PCIe), single-ended interfaces (i.e. DDR3, QSPI) and general purpose
interfaces using LVCMOS drivers that meet timing requirements while minimizing signal integrity (SI)
distortions on the PCB’s signaling traces. Signal trace lengths and flight times are aligned with FR-4
standard specification for PCBs.
Several different PCB layout stack-up examples have been presented to illustrate a typical number of
layers, signal assignments and controlled impedance requirements. Different Device interface signals
demand more or less complexity for routing and controlled impedance stack-ups. Optimizing the PCB’s
PDN stack-up needs with all of these different types of signal interfaces will ultimately determine the final
layer count and layer assignments in each customer’s PCB design.
This guideline must be used as a supplement in complement to TI’s Application Processor, Power
Management IC (PMIC) and Audio Companion components along with other TI component technical
documentation (i.e. Technical Reference Manual, Data Manual, Data Sheets, Silicon Errata, Pin-Out
Spreadsheet, Application Notes, etc.).
注
Notwithstanding any provision to the contrary, TI makes no warranty expressed, implied, or
statutory, including any implied warranty of merchantability of fitness for a specific purpose,
for customer boards. The data described in this appendix are intended as guidelines only.
注
These PCB guidelines are in a draft maturity and consequently, are subject to change
depending on design verification testing conducted during IC development and validation.
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8.1.1 Initial Requirements and Guidelines
Unless otherwise specified, the characteristic impedance for single-ended interfaces is recommended to
be between 35 Ω and 65 Ω to minimize the overshoot or undershoot on far-end loads.
Characteristic impedance for differential interfaces must be routed as differential traces on the same layer.
The trace width and spacing must be chosen to yield the recommended differential impedance. For more
information see 节 8.5.1.
The PDN must be optimized for low trace resistance and low trace inductance for all high-current power
nets from PMIC to the device.
An external interface using a connector must be protected following the IEC61000-4-2 level 4 system
ESD.
8.2 Power Optimizations
This section describes the necessary steps for designing a robust Power Distribution Network (PDN):
•
•
•
•
节 8.2.1, Step 1: PCB Stack-up
节 8.2.2, Step 2: Physical Placement
节 8.2.3, Step 3: Static Analysis
节 8.2.4, Step 4: Frequency Analysis
8.2.1 Step 1: PCB Stack-up
The PCB stack-up (layer assignment) is an important factor in determining the optimal performance of the
power distribution system. An optimized PCB stack-up for higher power integrity performance can be
achieved by following these recommendations:
•
•
•
Power and ground plane pairs must be closely coupled together. The capacitance formed between the
planes can decouple the power supply at high frequencies. Whenever possible, the power and ground
planes must be solid to provide continuous return path for return current.
Use a thin dielectric between the power and ground plane pair. Capacitance is inversely proportional to
the separation of the plane pair. Minimizing the separation distance (the dielectric thickness)
maximizes the capacitance.
Optimize the power and ground plane pair carrying high current supplies to key component power
domains as close as possible to the same surface where these components are placed (see 图 8-1).
This will help to minimize “loop inductance” encountered between supply decoupling capacitors and
component supply inputs and between power and ground plane pairs.
注
1-2oz Cu weight for power / ground plane is preferred to enable better PCB heat spreading,
helping to reduce Processor junction temperatures. In addition, it is preferable to have the
power / ground planes be adjacent to the PCB surface on which the Processor is mounted.
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Capacitor
Trace
DIE
Package
Via
3
1
Power/Ground
Ground/Power
2
Loop inductance
Note: 1. BGA via pair loop inductance
2. Power/Ground net spreading inductance
3. Capacitor trace inductance
SPRS906_PCB_STACKUP_01
图 8-1. Minimize Loop Inductance With Proper Layer Assignment
The placement of power and ground planes in the PCB stackup (determined by layer assignment) has a
significant impact on the parasitic inductances of power current path as shown in 图 8-1. For this reason, it
is recommended to consider layer order in the early stages of the PCB PDN design cycle, putting high-
priority supplies in the top half of the stackup (assuming high load and priority components are mounted
on the top-side of PCB) and low-priority supplies in the bottom half of the stackup as shown in the
examples below (vias have parasitic inductances which impact the bottom layers more, so it is advised to
put the sensitive and high-priority power supplies on the top/same layers).
8.2.2 Step 2: Physical Placement
A critical step in designing an optimized PDN is that proper care must be taken to making sure that the
initial floor planning of the PCB layout is done with good power integrity design guidelines in mind. The
following points are important for optimizing a PCB’s PDN:
•
Minimizing the physical distance between power sources and key high load components is the first
step toward optimization. Placing source and load components on the same side of the PCB is
desirable. This will minimize via inductance impact for high current loads and steps
•
•
External trace routing between components must be as wide as possible. The wider the traces, the
lower the DC resistance and consequently the lower the static IR drop.
Whenever possible for the internal layers (routing and plane), wide traces and copper area fills are
preferred for PDN layout. The routing of power nets in plane provide for more interplane capacitance
and improved high frequency performance of the PDN.
•
Whenever possible, use a via to component pin/pad ratio of 1:1 or better (i.e. especially decoupling
capacitors, power inductors and current sensing resistors). Do not share vias among multiple
capacitors for connecting power supply and ground planes.
•
•
Placement of vias must be as close as possible or even within a component’s solder pad if the PCB
technology you are using provides this capability.
To avoid any “ampacity” issue – maximum current-carrying capacity of each transitional via should be
evaluated to determine the appropriate number of vias required to connect components.
Adding vias to bring the “via-to-pad” ratio to 1:1 will improve PDN performance.
•
For noise sensitive power supplies (i.e. Phase Lock-Loops, analog signals like audio and video), a Gnd
shield can be used to isolate coplanar supplies that may have high step currents or high frequency
switching transitions from coupling into low-noise supplies.
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vdd_mpu
vss
vdd
PCB_PO_8
图 8-2. Coplanar Shielding of Power Net Using Ground Guard-band
8.2.3 Step 3: Static Analysis
Delivering reliable power to circuits is always of critical importance because voltage drops (also known as
IR drops) can happen at every level within an electronic system, on-chip, within a package, and across the
board. Robust system performance can only be ensured by understanding how the system elements will
perform under typical stressful Use Cases. Therefore, it is a good practice to perform a Static or DC
Analysis.
Static or DC analysis and design methodology results in a PDN design that minimizes voltage or IR drops
across power and ground planes, traces and vias. This ensures the application processor’s internal
transistors will be operating within their specified voltage ranges for proper functionality. The amount of IR
drop that will be encounter is based upon amount power drawn for a desired Use Case and PCB trace
(widths, geometry and number of parallel traces) and via (size, type and number) characteristics.
Components that are distant from their power source are particularly susceptible to IR drop. Designs that
rely on battery power must minimize voltage drops to avoid unacceptable power loss that can negatively
impact system performance. Early assessments a PDN’s static (DC) performance helps to determine
basic power distribution parameters such as best system input power point, optimal PCB layer stackup,
and copper area needed for load currents.
The resistance Rs of a plane conductor
for a unit length and unit width is called
the surface resistivity (ohms per square).
r
1
L
Rs =
=
t
σ ×t
l
t
R = Rs ×
W
w
SPRS906_PCB_STATIC_01
图 8-3. Depiction of Sheet Resistivity and Resistance
Ohm’s Law (V = I × R) relates conduction current to voltage drop. At DC, the relation coefficient is a
constant and represents the resistance of the conductor. Even current carrying conductors will dissipate
power at high currents even though their resistance may be very small. Both voltage drop and power
dissipation are proportional to the resistance of the conductor.
图 8-4 shows a PCB-level static IR drop budget defined between the power management device (PMIC)
pins and the application processor’s balls when the PMIC is supplying power.
•
It is highly recommended to physically place the PMIC as close as possible to the processor and on
the same side. The orientation of the PMIC vs. processor should be aligned to minimize distance for
the highest current rail.
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The resistance Rs of a plane conductor
for a unit length and unit width is called
the surface resistivity (ohms per square).
r
1
L
Rs =
=
t
σ ×t
l
t
R = Rs ×
W
w
SPRS906_PCB_STATIC_01
图 8-4. Static IR Drop Budget for PCB Only
The system-level IR drop budget is made up of three portions: on-chip, package, and PCB board. Static IR
or DC analysis/design methodology consists of designing the PDN such that the voltage drop (under DC
operating conditions) across power and ground pads of the transistors of the application processor device
is within a specified value of the nominal voltage for proper functionality of the device.
A PCB system-level voltage drop budget for proper device functionality is typically 1.5% of nominal
voltage. For a 1.35-V supply, this would be ≤20 mV.
To accurately analyze PCB static IR drop, the actual geometry of the PDN must be modeled properly and
simulated to accurately characterize long distribution paths, copper weight impacts, electro-migration
violations of current-carrying vias, and “Swiss-cheese” effects via placement has on power rails. It is
recommended to perform the following analyses:
•
•
Lumped resistance/IR drop analysis
Distributed resistance/IR drop analysis
注
The PMIC companion device supporting this processor has been designed with voltage
sensing feedback loop capabilities that enable a remote sense of the SMPS output voltage at
the point of use.
The NOTE above means the SMPS feedback signals and returns must be routed across PCB and
connected to the Device input power ball for which a particular SMPS is supplying power. This feedback
loop provides compensation for some of the voltage drop encountered across the PDN within limits. As
such, the effective resistance of the PDN within this loop should be determined in order to optimize
voltage compensation loop performance. The resistance of two PDN segments are of interest: one from
the power inductor/bulk power filtering capacitor node to the Processor’s input power and second is the
entire PDN route from SMPS output pin/ball to the Processor input power.
In the following sections each methodology is described in detail and an example has been provided of
analysis flow that can be used by the PCB designer to validate compliance to the requirements on their
PCB PDN design.
8.2.3.1 PDN Resistance and IR Drop
Lumped methodology consists of grouping all of the power pins on both the PMIC (voltage source) and
processor (current sink) devices. Then the PMIC source is set to an expected Use Case voltage level and
the processor load has its Use Case current sink value set as well. Now the lumped/effective resistance
for the power rail trace/plane routes can be determine based upon the actual layout’s power rail etch wide,
shape, length, via count and placement 图 8-5 illustrates the pin-grouping/lumped concept.
The lumped methodology consists of importing the PCB layout database (from Cadence Allegro tool or
any other layout design tool) into the static IR drop modeling and simulation tool of preference for the PCB
designer. This is followed by applying the correct PCB stack-up information (thickness, material
properties) of the PCB dielectric and metallization layers. The material properties of dielectric consist of
permittivity (Dk) and loss tangent (Df).
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For the conductor layers, the correct conductivity needs to be programmed into the simulation tool. This is
followed by pin-grouping of the power and ground nets, and applying appropriate voltage/current sources.
The current and voltage information can be obtained from the power and voltage specifications of the
device under different operating conditions / Use Cases.
Sources
Sources
Multiport net
Branch
Grouped Power/Ground
pins to create 1 equivalent
resistive branch
Port/Pin
Sinks
Sinks
SPRS906_PCB_PDN_01
图 8-5. Pin-grouping concept: Lumped and Distributed Methodologies
8.2.4 Step 4: Frequency Analysis
Delivering low noise voltage sources are very important to allowing a system to operate at the lowest
possible Operational Performance Point (OPP) for any one Use Case. An OPP is a combination of the
supply voltage level and clocking rate for key internal processor domains. A SCH and PCB designed to
provide low noise voltage supplies will then enable the processor to enter optimal OPPs for each Use
Case that in turn will minimize power dissipation and junction temperatures on-die. Therefore, it is a good
engineering practice to perform a Frequency Analysis over the key power domains.
Frequency analysis and design methodology results in a PDN design that minimizes transient noise
voltages at the processor’s input power balls. This allows the processor’s internal transistors to operate
near the minimum specified operating supply voltage levels. To accomplish this one must evaluate how a
voltage supply will change due to impedance variations over frequency. This analysis will focus on the
decoupling capacitor network (VDD_xxx and VSS/Gnd rails) at the load. Sufficient capacitance with a
distribution of self-resonant points will provide for an overall lower impedance vs frequency response for
each power domain.
Decoupling components that are distant from their load’s input power are susceptible to encountering
spreading loop inductance from the PCB design. Early analysis of each key power domain’s frequency
response helps to determine basic decoupling capacitor placement, optimal footprint, layer assignment,
and types needed for minimizing supply voltage noise/fluctuations due to switching and load current
transients.
注
Evaluation of loop inductance values for decoupling capacitors placed ~300mils closer to the
load’s input power balls has shown an 18% reduction in loop inductance due to reduced
distance.
•
Decoupling capacitors must be carefully placed in order to minimize loop inductance impact on supply
voltage transients. A real capacitor has characteristics not only of capacitance but also inductance and
resistance.
图 8-6 shows the parasitic model of a real capacitor. A real capacitor must be treated as an RLC circuit
with effective series resistance (ESR) and effective series inductance (ESL).
C
ESL
ESR
SPRS906_PCB_FREQ_01
图 8-6. Characteristics of a Real Capacitor With ESL and ESR
The magnitude of the impedance of this series model is given as:
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1
æ
ö2
2
Z = ESR +
ωESL -
ç
÷
ωC
è
ø
where : w = 2π¦
SPRS906_PCB_FREQ_02
图 8-7. Series Model Impedance Equation
图 8-8 shows the resonant frequency response of a typical capacitor with a self-resonant frequency of 55
MHz. The impedance of the capacitor is a combination of its series resistance and reactive capacitance
and inductance as shown in the equation above.
S-Parameter Magnitude
Job: GCM155R71E153KA55_15NF;
1.0e+01
1.0e+00
1.0e–01
1.0e–02
XC=1/ωC
XL=ωL
1.0e–03
Resonant frequency
(55 MHz) (minimum)
1.0e–04
1.00e–002
1.00e+000
1.00e+002
1.00e+004
1.00e+006
1.00e+008
Frequency (MHz)
SPRS906_PCB_FREQ_03
图 8-8. Typical Impedance Profile of a Capacitor
Because a capacitor has series inductance and resistance that impacts its effectiveness, it is important
that the following recommendations are adopted in placing capacitors on the PDN.
Wherever possible, mount the capacitor with the geometry that minimizes the mounting inductance and
resistance. This was shown earlier in 图 8-1. The capacitor mounting inductance and resistance values
include the inductance and resistance of the pads, trace, and vias. Whenever possible, use footprints that
have the lowest inductance configuration as shown in 图 8-9
The length of a trace used to connect a capacitor has a big impact on parasitic inductance and resistance
of the mounting. This trace must be as short and as wide as possible. wherever possible, minimize
distance to supply and Gnd vias by locating vias nearby or within the capacitor’s solder pad landing.
Further improvements can be made to the mounting by placing vias to the side of capacitor lands or
doubling the number of vias as shown in 图 8-9. If the PCB manufacturing processes allow it and if cost-
effective, via-in-pad (VIP) geometries are strongly recommended.
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In addition to mounting inductance and resistance associated with placing a capacitor on the PCB, the
effectiveness of a decoupling capacitor also depends on the spreading inductance and resistance that the
capacitor sees with respect to the load. The spreading inductance and resistance is strongly dependent on
the layer assignment in the PCB stack-up. Therefore, try to minimize X, Y and Z dimensions where the Z
is due to PCB thickness (as shown in 图 8-9).
From left (highest inductance) to right (lowest inductance) the capacitor footprint types shown in 图 8-9 are
known as:
•
•
•
•
•
2-via, Skinny End Exit (2vSEE)
2-via, Wide End Exit (2vWEE)
2-via, Wide Side Exit (2vWSE)
4-via, Wide Side Exit (4vWSE)
2-via, In-Pad (2vIP)
Via
Via-in-pad
Pad
Trace
Mounting geometry for reduced inductance
SPRS906_PCB_FREQ_04
图 8-9. Capacitor Placement Geometry for Improved Mounting Inductance
注
Evaluation of loop inductance values for decoupling capacitor footprints 2vSEE (worst case)
vs 4vWSE (2nd best) has shown a 30% reduction in inductance when 4vWSE footprint was
used in place of 2vSEE.
Decoupling Capacitor (Dcap) Strategy:
1. Use lowest inductance footprint and trace connection scheme possible for given PCB technology and
layout area in order to minimize Dcap loop inductance to power pin as much as possible (see 图 8-9).
2. Place Dcaps on “same-side” as component within their power plane outline to minimize “decoupling
loop inductance”. Target distance to power pin should be less than ~500mils depending upon PCB
layout characteristics (plane's layer assignment and solid nature). Use PI modeling CAD tool to verify
minimum inductance for top vs bottom-side placement.
3. Place Dcaps on “opposite-side” as component within their power plane outline if “same-side” is not
feasible or if distance to power pin is greater than ~500mils for top-side location. Use PI modeling CAD
tool to verify minimum inductance for top vs bottom-side placement.
4. Use minimum 10mil trace width for all voltage and gnd planes connections (i.e. Dcap pads, component
power pins, etc.).
5. Place all voltage and gnd plane vias “as close as possible” to point of use (i.e. Dcap pads, component
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power pins, etc.).
6. Use a “Power/Gnd pad/pin to via” ratio of 1:1 whenever possible. Do not exceed 2:1 ratio for small
number of vias within restricted PCB areas (i.e. underneath BGA components).
Frequency analysis for the CORE power domain has yielded the vdd Impedance vs Frequency response
shown in 节 8.3.7.2, vdd Example Analysis. As the example shows the overall CORE PDN Reff meets the
maximum recommended PDN resistance of 10mΩ.
8.2.5 System ESD Generic Guidelines
8.2.5.1 System ESD Generic PCB Guideline
Protection devices must be placed close to the ESD source which means close to the connector. This
allows the device to subtract the energy associated with an ESD strike before it reaches the internal
circuitry of the application board.
To help minimize the residual voltage pulse that will be built-up at the protection device due to its nonzero
turn-on impedance, it is mandatory to route the ESD device with minimum stub length so that the low-
resistive, low-inductive path from the signal to the ground is granted and not increasing the impedance
between signal and ground.
For ESD protection array being railed to a power supply when no decoupling capacitor is available in close
vicinity, consider using a decoupling capacitor (≥ 0.1 µF) tight to the VCC pin of the ESD protection. A
positive strike will be partially diverted to this capacitance resulting in a lower residual voltage pulse.
Ensure that there is sufficient metallization for the supply of signals at the interconnect side (VCC and
GND in 图 8-10) from connector to external protection because the interconnect may see between 15-A to
30-A current in a short period of time during the ESD event.
Bypass
capacitor
0.1 mf
(minimum)
Stub
inductance
Stub
Interconnection
inductance
inductance
vcc
Signal
VCC
VCC
Protected
circuit
Signal
Stub
inductance
ESD
strike
Minimize such
inductance by
optimizing layout
External
protection
Ground
inductance
Keep distance
between protected
circuit and external
protection
Keep external
protection closed by
connector
SPRS906_PCB_ESD_01
图 8-10. Placement Recommendation for an ESD External Protection
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注
To ensure normal behavior of the ESD protection (unwanted leakage), it is better to ground
the ESD protection to the board ground rather than any local ground (example isolated shield
or audio ground).
8.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
•
Avoid running critical signal traces (clocks, resets, interrupts, control signals, and so forth) near PCB
edges.
•
Add high frequency filtering: Decoupling capacitors close to the receivers rather than close to the
drivers to minimize ESD coupling.
•
•
Put a ground (guard) ring around the entire periphery of the PCB to act as a lightning rod.
Connect the guard ring to the PCB ground plane to provide a low impedance path for ESD-coupled
current on the ring.
•
•
Fill unused portions of the PCB with ground plane.
Minimize circuit loops between power and ground by using multilayer PCB with dedicated power and
ground planes.
•
•
Shield long line length (strip lines) to minimize radiated ESD.
Avoid running traces over split ground planes. It is better to use a bridge connecting the two planes in
one area.
BAD
BETTER
SPRS906_PCB_EMC_01
图 8-11. Trace Examples
•
Always route signal traces and their associated ground returns as close to one another as possible to
minimize the loop area enclosed by current flow:
–
–
At high frequencies current follows the path of least inductance.
At low frequencies current flows through the path of least resistance.
8.2.5.3 ESD Protection System Design Consideration
ESD protection system design consideration is covered in 节 8.5.2.2 of this document. The following are
additional considerations for ESD protection in a system.
•
•
•
•
•
•
Metallic shielding for both ESD and EMI
Chassis GND isolation from the board GND
Air gap designed on board to absorb ESD energy
Clamping diodes to absorb ESD energy
Capacitors to divert ESD energy
The use of external ESD components on the DP/DM lines may affect signal quality and are not
recommended.
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8.2.6 EMI / EMC Issues Prevention
All high-speed digital integrated circuits can be sources of unwanted radiation, which can affect nearby
sensitive circuitry and cause the final product to have radiated emissions levels above the limits allowed
by the EMC regulations if some preventative steps are not taken.
Likewise, analog and digital circuits can be susceptible to interference from the outside world and picked
up by the circuitry interconnections.
To minimize the potential for EMI/EMC issues, the following guidelines are recommended to be followed.
8.2.6.1 Signal Bandwidth
To evaluate the frequency of a digital signal, an estimated rule of thumb is to consider its bandwidth fBW
with respect to its rise time, tR:
fBW ≈ 0.35 / tR
This frequency actually corresponds to the break point in the signal spectrum, where the harmonics start
to decay at 40 dB per decade instead of 20 dB per decade.
8.2.6.2 Signal Routing
8.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
Keep radio frequency (RF) sensitive circuitry (like GPS receivers, GSM/WCDMA, Bluetooth/WLAN
transceivers, frequency modulation (FM) radio) away from high-speed ICs (the device, power and audio
manager, chargers, memories, and so forth) and ideally on the opposite side of the PCB. For improved
protection it is recommended to place these emission sources in a shield can. If the shield can have a
removable lid (two-piece shield), ensure there is low contact impedance between the fence and the lid.
Leave some space between the lid and the components under it to limit the high-frequency currents
induced in the lid. Limit the shield size to put any potential shield resonances above the frequencies of
interest; see 图 8-8, Typical Impedance Profile of a Capacitor.
8.2.6.2.2 Signal Routing—Outer Layer Routing
In case there is a need to use the outer layers for routing outside of shielded areas, it is recommended to
route only static signals and ensure that these static signals do not carry any high-frequency components
(due to parasitic coupling with other signals). In case of long traces, make provision for a bypass capacitor
near the signal source.
Routing of high-frequency clock signals on outer layers, even for a short distance, is discouraged,
because their emissions energy is concentrated at the discrete harmonics and can become significant
even with poor radiators.
Coplanar shielding of traces on outer layers (placing ground near the sides of a track along its length) is
effective only if the distance between the trace sides and the ground is smaller that the trace height above
the ground reference plane. For modern multilayer PCBs this is often not possible, so coplanar shielding
will not be effective. Do not route high-frequency traces near the periphery of the PCB, as the lack of a
ground reference near the trace edges can increase EMI: see 节 8.2.6.3, Ground Guidelines.
8.2.6.3 Ground Guidelines
8.2.6.3.1 PCB Outer Layers
Ideally the areas on the top and bottom layers of the PCB that are not enclosed by a shield should be
filled with ground after the routing is completed and connected with an adequate number of vias to the
ground on the inner ground planes.
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8.2.6.3.2 Metallic Frames
Ensure that all metallic parts are well connected to the PCB ground (like LCD screens metallic frames,
antennas reference planes, connector cages, flex cables grounds, and so forth). If using flex PCB ribbon
cables to bring high-frequency signals off the PCB, ensure they are adequately shielded (coaxial cables or
flex ribbons with a solid reference ground).
8.2.6.3.3 Connectors
For high-frequency signals going to connectors choose a fully shielded connector, if possible (for example,
SD card connectors). For signals going to external connectors or which are routed over long distances, it
is recommended to reduce their bandwidth by using low-pass filters (resistor, capacitor (RC) combinations
or lossy ferrite inductors). These filters will help to prevent emissions from the board and can also improve
the immunity from external disturbances.
8.2.6.3.4 Guard Ring on PCB Edges
The major advantage of a multilayer PCB with ground-plane is the ground return path below each and
every signal or power trace.
As shown in 图 8-12 the field lines of the signal return to PCB ground as long as an infinite ground is
available.
Traces near the PCB-edges do not have this infinite ground and therefore may radiate more than the
others. Thus, signals (clocks) or power traces (core power) identified to be critical must not be routed in
the vicinity of PCB edges, or, if not avoidable, must be accompanied by a guard ring on the PCB edge.
SPRS906_PCB_EMC_02
图 8-12. Field Lines of a Signal Above Ground
Signal
Power
Ground
Signal
SPRS906_PCB_EMC_03
图 8-13. Guard Ring Routing
The intention of the guard ring is that HF-energy, that otherwise would have been emitted from the PCB
edge, is reflected back into the board where it partially will be absorbed. For this purpose ground traces on
the borders of all layers (including power layer) must be applied as shown in 图 8-13.
As these traces must have the same (HF–) potential as the ground plane they must be connected to the
ground plane at least every 10 mm.
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8.2.6.3.5 Analog and Digital Ground
For the optimum solution, the AGND and the DGND planes must be connected together at the power
supply source in a same point. This ensures that both planes are at the same potential, while the transfer
of noise from the digital to the analog domain is minimized.
8.3 Core Power Domains
This section provides boundary conditions and theoretical background to be applied as a guide for
optimizing a PCB design. The decoupling capacitor and PDN characteristics tables shown below give
recommended capacitors and PCB parameters to be followed for schematic and PCB designs. Board
designs that meet the static and dynamic PDN characteristics shown in tables below will be aligned to the
expected PDN performance needed to optimize SoC performance.
8.3.1 General Constraints and Theory
•
•
•
Max PCB static/DC voltage drop (IRd) budget of 1.5% of supply voltage when using PMICs without
remote sensing as measured from PMIC’s power inductor and filter capacitor node to Processor input
including any ground return losses.
Max PCB static/DC voltage drop (IRd) budget can be relaxed to 5% of supply voltage when using
PMICs with remote sensing at the load as measured from PMIC’s power inductor and filter capacitor
node to Device’s supply input including any ground return losses.
PMIC component DM and guidelines should be referenced for the following:
–
–
Routing remote feedback sensing to optimize per each SMPS’s implementation
Selecting power filtering capacitor values and PCB placement.
•
•
•
•
Max Effective Resistance (Reff) budget can range from 4 – 50mΩ for key Device power rails not
including ground returns depending upon maximum load currents and maximum DC voltage drop
budget (as discussed above).
Max Device supply input voltage difference budget of 5mV under max current loading shall be
maintained across all balls connected to a common power rail. This represents any voltage difference
that may exist between a remote sense point to any power input.
Max PCB Loop Inductance (LL) budget between Device’s power inputs and local bulk and high
frequency decoupling capacitors including ground returns should range from 0.4 – 2.5nH depending
upon maximum transient load currents.
Max PCB dynamic/AC peak-to-peak transient noise voltage budgets between PMIC and Device
including ground returns are as follows:
–
+/-3% of nominal supply voltage for frequencies below the PMIC bandwidth (typ Fpmic ~
200kHz)
–
+/-5% of nominal supply voltage for frequencies between Fpmic to Fpcb (typ 20 – 100MHz)
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•
Max PCB Impedance (Z) vs Frequency (F) budget between Device’s power inputs and PMIC’s output
power filter node including ground return is determined by applying the Frequency Domain Target
Impedance Method to determine the PCB’s maximum frequency of interest (Fpcb). Ideally a properly
designed and decoupled PDN will exhibit smoothly increasing Z vs. F curve. There are 2 general
regions of interest as can be seen in 图 8-14.
–
1st area is from DC (0Hz) up to Fpmic (typ a few 100 kHz) where a PMIC’s transient response
characteristic (i.e. Switching Freq, Compensation Loop BW) dominate. A PDN’s Z is typically very
low due to power filtering & bulk capacitor values when PDN has very low trace resistance (i.e.
good Reff performance). The goal is to maintain a smoothly increasing Z that is less than Zt1 over
this low frequency range. This will ensure that a max transient current event will not cause a
voltage drop more than the PMIC’s current step response can support (typ 3%).
–
2nd area is from Fpmic up to Fpcb (typ 20-100MHz) where a PCB’s inherent characteristics (i.e.
parasitic capacitance, planar spreading inductances) dominate. A PDN’s Z will naturally increase
with frequency. At frequencies between Fpmic up to Fpcb, the goal is to maintain a smoothly
increasing Z to be less than Zt2. This will ensue that the high frequency content of a max transient
current event will not cause a voltage drop to be more than 5% of the min supply voltage.
图 8-14. PDN’s Target impedance
1.Voltage Rail Drop includes regulation accuracy, voltage distribution drops, and all dynamic events
such as transient noise, AC ripple, voltage dips etc.
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2.Typical max transient current is defined as 50% of max current draw possible.
8.3.2 Voltage Decoupling
Recommended power supply decoupling capacitors main characteristics for commercial products whose
ambient temperature is not to exceed +85C are shown in table below:
表 8-1. Commercial Applications Recommended Decoupling Capacitors Characteristics(1)(2)(3)
Value
Voltage [V] Package
Stability
Dielectric Capacitanc
Temp
Temp
REFERENCE
e
Range [°C] Sensitivity
[%]
Tolerance
22µF
10µF
6,3
4,0
6,3
6,3
6,3
6,3
6,3
6,3
0603
0402
0402
0402
0201
0201
0201
0201
Class 2
Class 2
Class 2
Class 2
Class 2
Class 2
Class 2
Class 2
X5R
X5R
X5R
X5R
X5R
X5R
X5R
X5R
- / + 20%
- / + 20%
- / + 20%
- / + 20%
- / + 20%
- / + 20%
- / + 20%
- / + 20%
-55 to + 85
-55 to + 85
-55 to + 85
-55 to + 85
-55 to + 85
-55 to + 85
-55 to + 85
-55 to + 85
- / + 15
- / + 15
- / + 15
- / + 15
- / + 15
- / + 15
- / + 15
- / + 15
GRM188R60J226MEA0L
GRM155R60G106ME44
GRM155R60J475ME95
GRM155R60J225ME95
GRM033R60J105MEA2
GRM033R60G474ME90
GRM033R60J224ME90
GRM033R60J104ME19
4.7µF
2.2µF
1µF
470nF
220nF
100nF
(1) Minimum value for each PCB capacitor: 100 nF.
(2) Among the different capacitors, 470 nF is recommended (not required) to filter at 5-MHz to 10-MHz frequency range.
(3) In comparison with the EIA Class 1 dielectrics, Class 2 dielectric capacitors tend to have severe temperature drift, high dependence of
capacitance on applied voltage, high voltage coefficient of dissipation factor, high frequency coefficient of dissipation, and problems with
aging due to gradual change of crystal structure. Aging causes gradual exponential loss of capacitance and decrease of dissipation
factor.
Recommended power supply decoupling capacitors main characteristics for automotive products are
shown in table below:
表 8-2. Automotive Applications Recommended Decoupling Capacitors Characteristics (1)(2)
Value
Voltage [V]
Package
Stability
Dielectric Capacitanc
Temp
Temp
REFERENCE
e
Range [°C] Sensitivity
[%]
Tolerance
22µF
10µF
6,3
6,3
10
6,3
16
16
25
16
1206
0805
0805
0603
0603
0603
0603
0402
Class 2
Class 2
Class 2
Class 2
Class 2
Class 2
Class 2
Class 2
X7R
X7R
X7R
X7R
X7R
X7R
X7R
X7R
- / + 20% -55 to + 125
- / + 20% -55 to + 125
- / + 15
GCM31CR70J226ME23
GCM21BR70J106ME22
GCM21BC71A475MA73
GCM188R70J225ME22
GCM188R71C105MA64
GCM188R71C474MA55
GCM188L81C224MA37
GCM155R71C104MA55
- / + 15
- / + 15
- / + 15
- / + 15
- / + 15
- / + 15
- / + 15
4.7µF
2.2µF
1µF
- / + 20% -55 to + 125
- / + 20% -55 to + 125
- / + 20% -55 to + 125
- / + 20% -55 to + 125
- / + 20% -55 to + 125
- / + 20% -55 to + 125
470nF
220nF
100nF
(1) Minimum value for each PCB capacitor: 100 nF.
(2) Among the different capacitors, 470 nF is recommended (not required) to filter at 5-MHz to 10-MHz frequency range.
8.3.3 Static PDN Analysis
One power net parameter derived from a PCB’s PDN static analysis is the Effective Resistance (Reff).
This is the total PCB power net routing resistance that is the sum of all the individual power net segments
used to deliver a supply voltage to the point of load and includes any series resistive elements (i.e. current
sensing resistor) that may be installed between the PMIC outputs and Processor inputs.
8.3.4 Dynamic PDN Analysis
Three power net parameters derived from a PCB’s PDN dynamic analysis are the Loop Inductance (LL),
Impedance (Z) and PCB Frequency of Interest (Fpcb).
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•
•
•
LL values shown are the recommended max PCB trace inductance between a decoupling capacitor’s
power supply and ground reference terminals when viewed from the decoupling capacitor with a
“theoretical shorted” applied across the Processor’s supply inputs to ground reference.
Z values shown are the recommended max PCB trace impedances allowed between Fpmic up to Fpcb
frequency range that limits transient noise drops to no more than 5% of min supply voltage during max
transient current events.
Fpcb (Frequency of Interest) is defined to be a power rail’s max frequency after which adding a
reasonable number of decoupling capacitors no longer significantly reduces the power rail impedance
below the desired impedance target (Zt2). This is due to the dominance of the PCB’s parasitic planar
spreading and internal package inductances.
表 8-3. Recommended PDN and Decoupling Characteristics (1)(2)(3)(4)(5)
PDN Analysis:
Supply
Static
Dynamic
Number of Recommended Decoupling Capacitors per
Supply
Frequency
range
of Interest
[MHz]
Max Reff
Dec. Cap.
Max
100
220
nF
470
nF
Max LL(8) (6) Impedance
1μF 2.2 μF 4.7 μF 10 μF 22 μF
(7)
nF(6)
[mΩ]
[nH]
[mΩ]
vdd_mpu
10
2
57
≤20
8
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
vdd_dsp,
vdd_gpu,
vdd_iva
13
2.5
54
≤20
1
vdd
27
2
2.5
6
87
≤50
≤100
N/A
N/A
N/A
N/A
6
8
1
4
1
2
1
1
1
1
1
2
vdds_ddr1
10
200
N/A
N/A
N/A
N/A
1
cap_vbbldo_dsp
cap_vbbldo_gpu
cap_vbbldo_iva
cap_vbbldo_mpu
N/A
N/A
N/A
N/A
6
6
6
cap_vddram_cor
e1
N/A
N/A
N/A
6
6
6
N/A
N/A
N/A
N/A
N/A
N/A
1
1
1
cap_vddram_cor
e3
cap_vddram_cor
e4
cap_vddram_dsp
cap_vddram_gpu
cap_vddram_iva
N/A
N/A
N/A
6
6
6
N/A
N/A
N/A
N/A
N/A
N/A
1
1
1
cap_vddram_mp
u
N/A
6
N/A
N/A
1
(1) For more information on peak-to-peak noise values, see the Recommended Operating Conditions table of the Specifications chapter.
(2) ESL must be as low as possible and must not exceed 0.5 nH.
(3) The PDN (Power Delivery Network) impedance characteristics are defined versus the device activity (that runs at different frequency)
based on the Recommended Operating Conditions table of the Specifications chapter.
(4) The static drop requirement drives the maximum acceptable PCB resistance between the PMIC or the external SMPS and the processor
power balls.
(5) Assuming that the external SMPS (power IC) feedback sense is taken close to processor power balls.
(6) High-frequency (30 to 70MHz) PCB decoupling capacitors
(7) Maximum Reff from SMPS to Processor.
(8) Maximum Loop Inductance for decoupling capacitor.
8.3.5 Power Supply Mapping
TPS65917 or TPS659039 are the Power Management ICs (PMICs) that should be used for the Device
designs. TI requires use of these PMICs for the following reasons:
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•
•
TI has validated their use with the Device
Board level margins including transient response and output accuracy are analyzed and optimized for
the entire system
•
•
Support for power sequencing requirements (refer to 节 5.9 Power Supply Sequences)
Support for Adaptive Voltage Scaling (AVS) Class 0 requirements, including TI provided software
Whenever we allow for combining of rails mapped on any of the SMPSes, the PDN guidelines that are the
most stringent of the rails combined should be implemented for the particular supply rail.
It is possible that some voltage domains on the device are unused in some systems. In such cases, to
ensure device reliability, it is still required that the supply pins for the specific voltage domains are
connected to some core power supply output.
These unused supplies though can be combined with any of the core supplies that are used (active) in the
system. e.g. if IVA and GPU domains are not used, they can be combined with the CORE domain,
thereby having a single power supply driving the combined CORE, IVA and GPU domains.
For the combined rail, the following relaxations do apply:
•
•
The AVS voltage of active rail in the combined rail needs to be used to set the power supply
The decoupling capacitance should be set according to the active rail in the combined rail
表 8-4 illustrates the approved and validated power supply connections to the Device for the SMPS
outputs of the TPS659039 PMIC.
表 8-4. TPS659039 Power Supply Connections(1)
SMPS
Valid Combination 1:
Reference Platform
Valid Combination 2:
MPU Centric
TPS659039 Current
Rating Limitation(3) (4)
SMPS1/2/3(2)
vdd_mpu
vdd_mpu
SMPS1/2: 6A
SMPS1/2/3: 9A
SMPS3(2)
SMPS4/5
vdds_ddr1
vdd_dsp
vdds_ddr1
SMPS3: 3A
vdd_dsp, vdd_gpu,
vdd_iva
SMPS4/5: 4A
SMPS6
vdd_gpu
vdd
SMPS6: 2-3A
(BOOST_CURRENT=0/1)
SMPS7
SMPS8
SMPS9
vdd
Free
Free
2A
1A
1A
vdd_iva
vdds18v
vdds18v
(1) Power consumption is highly application-specific. Separate analysis must be performed to ensure output current ratings (average and
peak) is within the limits of the PMIC for all rails of the device.
(2) Dual phase (SMPS1/2) can be used as long as the peak power consumption is maintained below the SMPS1/2 capacity
a. For the latest rated output current specifications for the TPS659039 device, please refer to the PMIC data manual.
b. MPU power consumption is highly system dependent. A detailed power consumption estimate must be performed to confirm
compatibility. Example: Single vs Dual MPU, OPP_NOM vs OPP_OD vs OPP_HIGH, TPS659039 configured with VI≥3V vs VI<3V,
etc. Contact your TI representative for details.
(3) Refer to the PMIC data manual for the latest TPS659039 specifications.
(4) A product’s maximum ambient temperature, thermal system design & heat spreading performance could limit the maximum power
dissipation below the full PMIC capacity in order to not exceed recommended SoC max Tj.
表 8-5 illustrates the approved and validated power supply connections to the Device for the SMPS
outputs of the TPS65917 PMIC.
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表 8-5. TPS65917 Power Supply Connections
TPS65917
Valid
Combination 1:
Valid
Combination
2:
TPS65917
Current Rating
Limitation (1) (3)
SMPS1
vdd_mpu
vdd_mpu
vdd
3.5A
3.5A
(2)
SMPS2
vdd_dsp,
vdd_gpu,
vdd_iva
(2)
SMPS3
vdd
vdd_dspeve,
vdd_gpu,
vdd_iva
3A
(3)
SMPS4
vdds18v
vdds18v
1.5A
2A
(4)
SMPS5
vdds_ddr1
vdds_ddr1
(1) Refer to the TPS65917 Data Manual for exact current rating limitations, including assumed VIN and other parameters. Values provided in
this table are for comparison purposes.
(2) DSP, EVE, GPU, and IVAHD power consumption is highly application-specific. Separate analysis must be performed to ensure output
current ratings (average and peak) is within the limits of the PMIC. VDD only supports OPP_NOM.
(3) Highly application-specific. Separate analysis must be performed to ensure average and peak power is within the limits of the PMIC.
(4) Furthermore, if SMPS5 is used for DDR power, both total memory + SoC power must be within the PMIC limits.
8.3.6 DPLL Voltage Requirement
The voltage input to the DPLLs has a low noise requirement. Board designs should supply these voltage
inputs with a low noise LDO to ensure they are isolated from any potential digital switching noise. The
TPS65917 PMIC LDOLN output is specifically designed to meet this low noise requirement.
注
For more information about Input Voltage Sources, see 节 6.2 DPLLs, DLLs Specifications.
表 8-4 present the voltage inputs that supply the DPLLs.
表 8-6. Input Voltage Power Supplies for the DPLLs
POWER SUPPLY
vdda_per
DPLLs
DPLL_PER and PER HSDIVIDER analog power supply
DPLL_DDR and DDR HSDIVIDER analog power supply
DPLL_DEBUG analog power supply
vdda_ddr
vdda_debug
vdda_dsp_iva
vdda_core_gmac
vdda_gpu
DPLL_DSP and DPLL_IVA analog power supply
DPLL_CORE and HSDIVIDER analog power supply
DPLL_GPU analog power supply
vdda_video
DPLL_VIDEO1 analog power supply
vdda_mpu_abe
vdda_osc
DPLL_MPU and DPLL_ABE analog power supply
not DPLL input but is required to be supplied by low noise input voltage
DPLL_SPARE analog power supply
vdda_pll_spare
8.3.7 Example PCB Design
The following sections describe an example PCB design and its resulting PDN performance for the
vdd_mpu key processor power domain.
注
Materials presented in this section are based on generic PDN analysis on PCB boards and
are not specific to systems integrating the Device.
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8.3.7.1 Example Stack-up
Layer Assignments:
•
Layer Top: Signal and Segmented Power Plane
Processor and PMIC components placed on Top-side
–
•
•
•
•
•
•
•
Layer 2: Gnd Plane1
Layer 3: Signals
Layer n: Power Plane1
Layer n+1: Power Plane 2
Layer n+2: Signal
Layer n+3: Gnd Plane2
Layer Bottom: Signal and Segmented Power Planes
–
Decoupling caps, etc.
Via Technology: Through-hole
Copper Weight:
•
•
½ oz for all signal layers.
1-2oz for all power plane for improved PCB heat spreading.
8.3.7.2 vdd Example Analysis
Maximum acceptable PCB resistance (Reff) between the PMIC and Processor input power balls should not
exceed 10mΩ.
Maximum decoupling capacitance loop inductance (LL) between Processor input power balls and
decoupling capacitances should not exceed 2.0nH (ESL NOT included )
Impedance target for key frequency of interest between Processor input power balls and PMIC’s SMPS
output power balls should not exceed 57mΩ at 20MHz.
表 8-7. Example PCB vdd PI Analysis Summary
Parameter
OPP
Recommendation
OPP_NOM
266 MHz
1 V
Example PCB
Clocking Rate
Voltage Level
Max Current Draw
1 V
1 A
1 A
Max Effective Resistance: Power
Inductor Segment Total Reff
10mΩ
9.7 mΩ
Max Loop Inductance
Impedance Target
2.0nH
0.97 –1.75nH
57mΩ F<20Mhz
57mΩ F<20Mhz
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图 8-15 show a PCB layout example and the resulting PI analysis results.
L1002
1.0uH, 4.5A, 1616
IHLP-1616ABER1R0M11
PMIC
CORE_VDD
SMPS2
SoC
SMPS2_SW
C1014
VDD
47uF, 6.3V, X7R, 1210
GCM32ER70J476ME19
C363, 364, 386, 388,
390, 498
0.1uF, 16V, X7R, 0402
GCM155R71C104KA55
C395
0.22uF, 25V, X7R, 0603
GCM188R71E224KA55
C394
0.47uF, 16V, X7R, 0603
GCM188R71C474KA55
C393
1.0uF, 16V, X7R, 0603
GCM188R71C105KA64
C456
2.2uF, 6.3V, X7R, 0603
GCM188R70J225KE22
C487
4.7uF, 16V, X7R, 0805
GCM21BR71C475KA73
图 8-15. vdd Simplified SCH Diagram
注
PCB Etch Resistance Breakdown, PDN Effective Resistance, and vdd routings are UNDER
DEVELOPMENT!
IR Drop: vdd (PCB Rev Oct25, CAD sPSI v13.1.1)
•
•
Source Conditions: 1V @ 1A
Power Plane/Trace Effective Resistances
–
–
–
From PMIC SMPS to SoC load = 9.7mohm
From Power Inductor to SoC load = 6mohm
"Open-Loop" Voltage/IR Drop for 1A = 6mV
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图 8-16. vdd Voltage/IR Drop [All Layers]
Dynamic analysis of this PCB design for the CORE power domain determined the vdd decoupling
capacitor loop inductance and impedance vs frequency analysis shown below. As you can see, the loop
inductance values ranged from 0.97 –1.75nH and were less than maximum 2.0nH recommended.
注
Comparing loop inductances for capacitors at different distances from the SoC’s input power
balls shows an 18% reduction for caps placed closer. This was derived by averaging the
inductances for the 3 caps with distances over 800mils (Avg LL = 1.33nH) vs the 3 caps with
distances less than 600mils (Avg LL = 1.096nH).
表 8-8. Rail - vdd
Cap Ref Model Port
Loop Inductacne
[nH]
Footprint
Types
PCB Side
Distance to
Ball-Field
[mils]
Value [μF]
Size
Des
#
C487
C393
C394
C456
C386
C395
C363
C390
C364
C498
C388
10
6
0.97
1.11
1.12
1.13
1.16
1.18
1.46
1.48
1.74
1.74
1.75
4vWSE
4vWSE
4vWSE
4vWSE
2vWSE
4vWSE
2vWSE
2vWSE
2vWSE
2vWSE
2vWSE
Top
521
358
357
403
40
4.7
1.0
0.47
2.2
0.1
0.22
0.1
0.1
0.1
0.1
0.1
0805
0603
0603
0603
0402
0603
0402
0402
0402
0402
0402
Bottom
Bottom
Bottom
Bottom
Bottom
Bottom
Bottom
Bottom
Bottom
Bottom
7
9
3
8
460
40
1
5
40
2
40
11
4
40
40
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Loop Inductance range: 0.97 –1.75nH
图 8-17. vdd Decoupling Cap Loop Inductances
图 8-18 shows vdd Impedance vs Frequency characteristics.
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173mohm @ 100MHz
87mohm @ 50MHz
27mohm @ 20MHz
9.9mohm @ 10MHz
图 8-18. vdd Impedance vs Frequency
8.4 Single-Ended Interfaces
8.4.1 General Routing Guidelines
The following paragraphs detail the routing guidelines that must be observed when routing the various
functional LVCMOS interfaces.
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•
Line spacing:
–
For a line width equal to W, the spacing between two lines must be 2W, at least. This minimizes the
crosstalk between switching signals between the different lines. On the PCB, this is not achievable
everywhere (for example, when breaking signals out from the device package), but it is
recommended to follow this rule as much as possible. When violating this guideline, minimize the
length of the traces running parallel to each other (see 图 8-19).
W
D+
S = 2 W = 200 µm
SPRS906_PCB_SE_GND_01
图 8-19. Ground Guard Illustration
•
Length matching (unless otherwise specified):
–
For bus or traces at frequencies less than 10 MHz, the trace length matching (maximum length
difference between the longest and the shortest lines) must be less than 25 mm.
–
For bus or traces at frequencies greater than 10 MHz, the trace length matching (maximum length
difference between the longest and the shortest lines) must be less than 2.5 mm.
•
•
Characteristic impedance
–
Unless otherwise specified, the characteristic impedance for single-ended interfaces is
recommended to be between 35-Ω and 65-Ω.
Multiple peripheral support
–
For interfaces where multiple peripherals have to be supported in the star topology, the length of
each branch has to be balanced. Before closing the PCB design, it is highly recommended to verify
signal integrity based on simulations including actual PCB extraction.
8.4.2 QSPI Board Design and Layout Guidelines
The following section details the routing guidelines that must be observed when routing the QSPI
interfaces.
•
•
The qspi1_sclk output signal must be looped back into the qspi1_rtclk input.
The signal propagation delay from the qspi1_sclk ball to the QSPI device CLK input pin (A to C) must
be approximately equal to the signal propagation delay from the QSPI device CLK pin to the
qspi1_rtclk ball (C to D).
•
The signal propagation delay from the QSPI device CLK pin to the qspi1_rtclk ball (C to D) must be
approximately equal to the signal propagation delay of the control and data signals between the QSPI
device and the SoC device (E to F, or F to E).
•
•
The signal propagation delay from the qspi1_sclk signal to the series terminators (R2 = 10 Ω) near the
QSPI device must be < 450pS (~7cm as stripline or ~8cm as microstrip)
50 Ω PCB routing is recommended along with series terminations, as shown in 图 8-20.
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•
Propagation delays and matching:
–
–
–
–
A to C = C to D = E to F.
Matching skew: < 60pS
A to B < 450pS
B to C = as small as possible (<60pS)
Locate both R2 resistors
close together near the QSPI device
A
B
C
R1
R2
0 Ω*
10 Ω
R2
10 Ω
qspi1_sclk
QSPI device
clock input
D
qspi1_rtclk
E
F
QSPI device
IOx, CS#
qspi1_d[x], qspi1_cs[y]
SPRS906_PCB_QSPI_01
图 8-20. QSPI Interface High Level Schematic
注
*0 Ω resistor (R1), located as close as possible to the qspi1_sclk pin, is placeholder for fine-
tuning if needed.
8.5 Differential Interfaces
8.5.1 General Routing Guidelines
To maximize signal integrity, proper routing techniques for differential signals are important for high-speed
designs. The following general routing guidelines describe the routing guidelines for differential lanes and
differential signals.
•
As much as possible, no other high-frequency signals must be routed in close proximity to the
differential pair.
•
Must be routed as differential traces on the same layer. The trace width and spacing must be chosen
to yield the differential impedance value recommended.
•
•
•
•
Minimize external components on differential lanes (like external ESD, probe points).
Through-hole pins are not recommended.
Differential lanes mustn’t cross image planes (ground planes).
No sharp bend on differential lanes.
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•
•
Number of vias on the differential pairs must be minimized, and identical on each line of the differential
pair. In case of multiple differential lanes in the same interface, all lines should have the same number
of vias.
Shielded routing is to be promoted as much as possible (for instance, signals must be routed on
internal layers that are inside power and/or ground planes).
8.5.2 USB 2.0 Board Design and Layout Guidelines
This section discusses schematic guidelines when designing a universal serial bus (USB) system.
8.5.2.1 Background
Clock frequencies generate the main source of energy in a USB design. The USB differential DP/DM pairs
operate in high-speed mode at 480 Mbps. System clocks can operate at 12 MHz, 48 MHz, and 60 MHz.
The USB cable can behave as a monopole antenna; take care to prevent RF currents from coupling onto
the cable.
When designing a USB board, the signals of most interest are:
•
•
Device interface signals: Clocks and other signal/data lines that run between devices on the PCB.
Power going into and out of the cable: The USB connector socket pin 1 (VBUS ) may be heavily
filtered and need only pass low frequency signals of less than ~100 KHz. The USB socket pin 4
(analog ground) must be able to return the current during data transmission, and must be filtered
sparingly.
•
•
Differential twisted pair signals going out on cable, DP and DM: Depending upon the data transfer rate,
these device terminals can have signals with fundamental frequencies of 240 MHz (high speed), 6
MHz (full speed), and 750 kHz (low speed).
External crystal circuit (device terminals XI and X0): 12 MHz, 19.2 MHz, 24 MHz, and 48 MHz
fundamental. When using an external crystal as a reference clock, a 24 MHz and higher crystal is
highly recommended.
8.5.2.2 USB PHY Layout Guide
The following sections describe in detail the specific guidelines for USB PHY Layout.
8.5.2.2.1 General Routing and Placement
Use the following routing and placement guidelines when laying out a new design for the USB physical
layer (PHY). These guidelines help minimize signal quality and electromagnetic interference (EMI)
problems on a four-or-more layer evaluation module (EVM).
•
Place the USB PHY and major components on the un-routed board first. For more details, see 节
8.5.2.2.2.3.
•
•
•
Route the high-speed clock and high-speed USB differential signals with minimum trace lengths.
Route the high-speed USB signals on the plane closest to the ground plane, whenever possible.
Route the high-speed USB signals using a minimum of vias and corners. This reduces signal
reflections and impedance changes.
•
•
•
•
When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90°
turn. This reduces reflections on the signal traces by minimizing impedance discontinuities.
Do not route USB traces under or near crystals, oscillators, clock signal generators, switching
regulators, mounting holes, magnetic devices or IC’s that use or duplicate clock signals.
Avoid stubs on the high-speed USB signals because they cause signal reflections. If a stub is
unavoidable, then the stub should be less than 200 mils.
Route all high-speed USB signal traces over continuous planes (VCC or GND), with no interruptions.
Avoid crossing over anti-etch, commonly found with plane splits.
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8.5.2.2.2 Specific Guidelines for USB PHY Layout
The following sections describe in detail the specific guidelines for USB PHY Layout.
8.5.2.2.2.1 Analog, PLL, and Digital Power Supply Filtering
To minimize EMI emissions, add decoupling capacitors with a ferrite bead at power supply terminals for
the analog, phase-locked loop (PLL), and digital portions of the chip. Place this array as close to the chip
as possible to minimize the inductance of the line and noise contributions to the system. An analog and
digital supply example is shown in 图 8-21. In case of multiple power supply pins with the same function,
tie them up to a single low-impedance point in the board and then add the decoupling capacitors, in
addition to the ferrite bead. This array of caps and ferrite bead improve EMI and jitter performance. Take
both EMI and jitter into account before altering the configuration.
Analog
Power Supply
Ferrite Bead
0.1 µF
0.01 µF
0.001 µF
1 µF
SoC Board
AGND
Digital
Power Supply
Ferrite Bead
0.1 µF
0.01 µF
0.001 µF
1 µF
DGND
SPRS906_PCB_USB20_01
图 8-21. Suggested Array Capacitors and a Ferrite Bead to Minimize EMI
Consider the recommendations listed below to achieve proper ESD/EMI performance:
•
•
•
Use a 0.01 μF cap on each cable power VBUS line to chassis GND close to the USB connector pin.
Use a 0.01 μF cap on each cable ground line to chassis GND next to the USB connector pin.
If voltage regulators are used, place a 0.01 μF cap on both input and output. This is to increase the
immunity to ESD and reduce EMI. For other requirements, see the device-specific datasheet.
8.5.2.2.2.2 Analog, Digital, and PLL Partitioning
If separate power planes are used, they must be tied together at one point through a low-impedance
bridge or preferably through a ferrite bead. Care must be taken to capacitively decouple each power rail
close to the device. The analog ground, digital ground, and PLL ground must be tied together to the low-
impedance circuit board ground plane.
8.5.2.2.2.3 Board Stackup
Because of the high frequencies associated with the USB, a printed circuit board with at least four layers
is recommended; two signal layers separated by a ground and power layer as shown in 图 8-22.
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Signal 1
GND Plane
Power Plane
Signal 2
SPRS906_PCB_USB20_02
图 8-22. Four-Layer Board Stack-Up
The majority of signal traces should run on a single layer, preferably SIGNAL1. Immediately next to this
layer should be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in
the ground or power plane. When running across split planes is unavoidable, sufficient decoupling must
be used. Minimizing the number of signal vias reduces EMI by reducing inductance at high frequencies.
8.5.2.2.2.4 Cable Connector Socket
Short the cable connector sockets directly to a small chassis ground plane (GND strap) that exists
immediately underneath the connector sockets. This shorts EMI (and ESD) directly to the chassis ground
before it gets onto the USB cable. This etch plane should be as large as possible, but all the conductors
coming off connector pins 1 through 6 must have the board signal GND plane run under. If needed, scoop
out the chassis GND strap etch to allow for the signal ground to extend under the connector pins. Note
that the etches coming from pins 1 and 4 (VBUS power and GND) should be wide and via-ed to their
respective planes as soon as possible, respecting the filtering that may be in place between the connector
pin and the plane. See 图 8-23 for a schematic example.
Place a ferrite in series with the cable shield pins near the USB connector socket to keep EMI from getting
onto the cable shield. The ferrite bead between the cable shield and ground may be valued between 10 Ω
and 50 Ω at 100 MHz; it should be resistive to approximately 1 GHz. To keep EMI from getting onto the
cable bus power wire (a very large antenna) a ferrite may be placed in series with cable bus power,
VBUS, near the USB connector pin 1. The ferrite bead between connector pin 1 and bus power may be
valued between 47 Ω and approximately 1000 Ω at 100 MHz. It should continue being resistive out to
approximately 1 GHz, as shown in 图 8-23.
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5
SHIELD_GND
4
3
GND
DP
2
DM
1
6
+5 V
Ferrite Bead
VBUS
U2
SHIELD_GND
USB Socket
U1
Ferrite Bead
SPRS906_PCB_USB20_03
图 8-23. USB Connector
8.5.2.2.2.5 Clock Routings
To address the system clock emissions between devices, place a ~10 to 130 Ω resistor in series with the
clock signal. Use a trial and error method of looking at the shape of the clock waveform on a high-speed
oscilloscope and of tuning the value of the resistance to minimize waveform distortion. The value on this
resistor should be as small as possible to get the desired effect. Place the resistor close to the device
generating the clock signal. If an external crystal is used, follow the guidelines detailed in the Selection
and Specification of Crystals for Texas Instruments USB 2.0 Devices (SLLA122).
When routing the clock traces from one device to another, try to use the 3W spacing rule. The distance
from the center of the clock trace to the center of any adjacent signal trace should be at least three times
the width of the clock trace. Many clocks, including slow frequency clocks, can have fast rise and fall
times. Using the 3W rule cuts down on crosstalk between traces. In general, leave space between each of
the traces running parallel between the devices. Avoid using right angles when routing traces to minimize
the routing distance and impedance discontinuities. For further protection from crosstalk, run guard traces
beside the clock signals (GND pin to GND pin), if possible. This lessens clock signal coupling, as shown in
图 8-24.
3W
3W
W
Trace
SPRS906_PCB_USB20_04
图 8-24. 3W Spacing Rule
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8.5.2.2.2.6 Crystals/Oscillator
Keep the crystal and its load capacitors close to the USB PHY pins, XI and XO (see 图 8-25). Note that
frequencies from power sources or large capacitors can cause modulations within the clock and should
not be placed near the crystal. In these instances, errors such as dropped packets occur. A placeholder
for a resistor, in parallel with the crystal, can be incorporated in the design to assist oscillator startup.
Power is proportional to the current squared. The current is I = C*dv/dt, because dv/dt is a function of the
PHY, current is proportional to the capacitive load. Cutting the load to 1/2 decreases the current by 1/2
and the power to 1/4 of the original value. For more details on crystal selection, see the Selection and
Specification of Crystals for Texas Instruments USB 2.0 Devices (SLLA122).
X1
0.1 µF
Power Pins
XTAL
X0
0.001 µF
USB PHY
SPRS906_PCB_USB20_05
图 8-25. Power Supply and Clock Connection to the USB PHY
8.5.2.2.2.7 DP/DM Trace
Place the USB PHY as close as possible to the USB 2.0 connector. The signal swing during high-speed
operation on the DP/DM lines is relatively small (400 mV ± 10%), so any differential noise picked up on
the twisted pair can affect the received signal. When the DP/DM traces do not have any shielding, the
traces tend to behave like an antenna and picks up noise generated by the surrounding components in
the environment. To minimize the effect of this behavior:
•
DP/DM traces should always be matched lengths and must be no more than 4 inches in length;
otherwise, the eye opening may be degraded (see 图 8-26).
•
Route DP/DM traces close together for noise rejection on differential signals, parallel to each other and
within two mils in length of each other. The measurement for trace length must be started from
device's balls.
•
•
A high-speed USB connection is made through a shielded, twisted pair cable with a differential
characteristic impedance of 90 Ω ±15%. In layout, the impedance of DP and DM should each be 45 Ω
± 10%.
DP/DM traces should not have any extra components to maintain signal integrity. For example, traces
cannot be routed to two USB connectors.
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Minimize
This Distance
VBUS
GND
D+
Cable
Connector
D+
D-
USB PHY
Connector
D-
SPRS906_PCB_USB20_06
图 8-26. USB PHY Connector and Cable Connector
8.5.2.2.2.8 DP/DM Vias
When a via must be used, increase the clearance size around it to minimize its capacitance. Each via
introduces discontinuities in the signal’s transmission line and increases the chance of picking up
interference from the other layers of the board. Be careful when designing test points on twisted pair lines;
through-hole pins are not recommended.
8.5.2.2.2.9 Image Planes
An image plane is a layer of copper (voltage plane or ground plane), physically adjacent to a signal routing
plane. Use of image planes provides a low impedance, shortest possible return path for RF currents. For a
USB board, the best image plane is the ground plane because it can be used for both analog and digital
circuits.
•
Do not route traces so they cross from one plane to the other. This can cause a broken RF return path
resulting in an EMI radiating loop as shown in 图 8-27. This is important for higher frequency or
repetitive signals. Therefore, on a multi-layer board, it is best to run all clock signals on the signal
plane above a solid ground plane.
•
Avoid crossing the image power or ground plane boundaries with high-speed clock signal traces
immediately above or below the separated planes. This also holds true for the twisted pair signals (DP,
DM). Any unused area of the top and bottom signal layers of the PCB can be filled with copper that is
connected to the ground plane through vias.
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Do
Don't
SPRS906_PCB_USB20_07
图 8-27. Do Not Cross Plane Boundaries
•
Do not overlap planes that do not reference each other. For example, do not overlap a digital power
plane with an analog power plane as this produces a capacitance between the overlapping areas that
could pass RF emissions from one plane to the other, as shown in 图 8-28.
Analog Power Plane
Unwanted Capacitance
Digital Power Plane
SPRS906_PCB_USB20_08
图 8-28. Do Not Overlap Planes
•
Avoid image plane violations. Traces that route over a slot in an image plane results in a possible RF
return loop, as shown in 图 8-29.
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RF Return
Current
RF Return
Current
Slot in Image Plane
Slot in Image Plane
Bad
Better
SPRS906_PCB_USB20_09
图 8-29. Do Not Violate Image Planes
8.5.2.2.2.10 Power Regulators
Switching power regulators are a source of noise and can cause noise coupling if placed close to sensitive
areas on a circuit board. Therefore, the switching power regulator should be kept away from the DP/DM
signals, the external clock crystal (or clock oscillator), and the USB PHY.
8.5.2.3 References
USB 2.0 Specification, Intel, 2000, http://www.usb.org/developers/docs/
•
•
High Speed USB Platform Design Guidelines, Intel, 2000,
http://www.intel.com/technology/usb/download/usb2dg_R1_0.pdf
•
Selection and Specification of Crystals for Texas Instruments USB 2.0 Devices (SLLA122)
8.5.3 USB 3.0 Board Design and Layout Guidelines
This section provides the timing specification for the USB3.0 (USB1 in the device) interface as a PCB
design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew,
signal integrity, cross-talk, and signal timing. TI has performed the simulation and system design work to
ensure the USB3.0 interface requirements are met. The design rules stated within this document are
targeted at DEVICE mode electrical compliance. HOST mode and/or systems that do not include the 3m
USB cable and far-end 11-inch PCB trace required by DEVICE mode compliance testing may not need
the complete list of optimizations shown in this document; however, applying these optimizations to HOST
mode systems will lead to optimal DEVICE mode performance.
8.5.3.1 USB 3.0 interface introduction
The USB 3.0 has two unidirectional differential pairs: TXp/TXn pair and RXp/RXn pair. AC coupling caps
are needed on the board for TX traces.
图 8-30 present high level schematic diagram for USB 3.0 interface.
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Device
AC Caps
usb_txp0
CMF
usb_txn0
Vias (if necessary)
Vias (if necessary)
usb_rxp0
usb_rxn0
CMF
Vias (if necessary)
Vias (if necessary)
Place near connector, and keep routing short
SPRS85x_PCB_USB30_1
图 8-30. USB 3.0 Interface High Level Schematic
注
ESD components should be on a PCB layer next to a system GND plane layer so the
inductance of the via to GND will be minimal.
If vias are used, place the vias near the AC Caps or CMFs and under the SoC BGA, if
necessary.
图 8-31 present placement diagram for USB 3.0 interface.
AC Cap
SoC TX
SoC RX
CMF
CMF
AC Cap
SPRS85x_PCB_USB30_2
图 8-31. USB 3.0 placement diagram
表 8-9. USB1 Component Reference
INTERFACE
COMPONENT
ESD
SUPPLIER
PART NUMBER
TPD1E05U06
TI
Murata
-
USB3 PHY
CMF
C
DLW21SN900HQ2
100nF (typical size: 0201)
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8.5.3.2 USB 3.0 General routing rules
Some general routing guidelines regarding USB 3.0:
•
•
•
•
•
•
Avoid crossing splits reference plane(s).
Shorter trace length is preferred.
Minimize the via usage and layer transition
Keep large spacing between TX and RX pairs.
Intra-lane delay mismatch between DP and DM less than 1ps. Same for RXp and RXn.
Distance between common mode filter (CMF) and ESD protection device should be as short as
possible
•
•
•
Distance between ESD protection device and USB connector should be as short as possible.
Distance between AC capacitors (TX only) and CMF should be as short as possible.
USB 3.0 signals should always be routed over an adjacent ground plane.
表 8-10 and 表 8-11 present routing specification and recommendations for USB1 in the device.
表 8-10. USB1 Routing Specifications
PARAMETER
MIN
TYP
MAX
UNIT
Device balls to USB 3.0 connector trace
length
3500
Mils
Skew within a differential pair
Number of stubs allowed on TX/RX traces
TX/RX pair differential impedance
3
6
0
Mils
Stubs
Ω
83.7
90
96.3
2
Number of vias on each TX/RX trace
Differential pair to any other trace spacing
Vias
2xDS
3xDS
Number of ground plane cuts allowed within
USB3 routing region (except for specific
ground carving as explained in this
document)
0
0
Cuts
Number of layers between USB3.0 routing
region and reference ground plane
Layers
PCB trace width
6
Mils
Mils
Mils
PCB BGA escape via pad size
PCB BGA escape via hole size
18
10
1. Vias must be used in pairs and spaced equally along a signal path.
2. DS = differential spacing of the traces.
3. Exceptions may be necessary in the SoC package BGA area.
4. GND guard-bands on the same layer may be closer, but should not be allowed to affect the impedance
of the differential pair routing. GND guard-bands to isolate USB3.0 differential pairs from all other
signals are recommended.
表 8-11. USB1 Routing Recommendations
Item
Description
Reason
Place ESD component on same layer as connector (no via or stub to Eliminate reflection loss from via
ESD location
ESD component)
TPD1E05U06
& stub to ESD
ESD part number
CMF part number
Minimize capacitance (0.42pF)
Manufacturer’s recommended
device
DLW21SN900HQ2
Enable full signal chain
simulation
Connector
Use USB3.0 connector with supporting s-parameter model
Carve GND underneath AC Caps, ESD, CMF, and connector
Minimize capacitance under ESD
and CMF
Carve Ground
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表 8-11. USB1 Routing Recommendations (continued)
Item
Description
Reason
Minimize pad size and round the corners of the pads for the ESD
and CMF components
Round pads
Minimize capacitance
Max 2 vias per signal trace. If vias are required, place vias close to
the AC Caps and CMFs. Vias under the SoC grid array may be used
if necessary to route signals away from BGA pattern.
Vias significantly degrade signal
integrity at 2.5GHz
Vias
图 8-32 presents an example layout, demonstrating the “carve GND” concept.
AC Cap
CMF
AC Cap
CMF
Layer2, GND: Gaps carved in GND underneath
AC Caps, CMF, ESD, and connector.
Top Layer: Routing from SoC through
AC Caps, CMF, and ESD to connector.
Layer3, Signal: Implement as keep-out
zone underneath carved GND areas.
Layer4, GND Plane underneath AC Caps,
CMF, ESD, and connector.
SPRS85x_PCB_USB30_3
图 8-32. USB 3.0 Example “carve GND” layout
8.5.4 HDMI Board Design and Layout Guidelines
This section provides the timing specification for the HDMI interface as a PCB design and manufacturing
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. TI has performed the simulation and system design work to ensure the HDMI interface
requirements are met. The design rules stated within this document are targeted at resolutions less than
or equal to 1080p60 with 8-bit color; deep color (10-bit) requires further signal integrity optimization.
8.5.4.1 HDMI Interface Schematic
The HDMI bus is separated into three main sections (HDMI Ethernet and the optional Audio Return
Channel are not specifically supported by this Device):
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1. Transition Minimized Differential Signaling (TMDS) high speed digital video interface
2. Display Data Channel (I2C bus for configuration and status exchange between two devices)
3. Consumer Electronics Control (optional) for remote control of connected devices.
The DDC and CEC are low speed interfaces, so nothing special is required for PCB layout of these
signals.
The TMDS channels are high speed differential pairs and therefore require the most care in layout.
Specifications for TMDS layout are below.
图 8-33 shows the HDMI interface schematic.
Device
hdmi_tx*-
CMF
hdmi_tx*+
Place near connector, and keep routing short
SPRS85x_PCB_HDMI_1
图 8-33. HDMI Interface High Level Schematic
图 8-34 presents placement diagram for HDMI interface.
CMF
CMF
CMF
CMF
SPRS85x_PCB_HDMI_2
图 8-34. HDMI Placement Diagram
表 8-12. HDMI Component Reference
INTERFACE
DEVICE
ESD
SUPPLIER
TI
PART NUMBER
TPD1E05U06
HDMI
CMF
Murata
DLW21SN900HQ2
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8.5.4.2 TMDS General Routing Guidelines
The TMDS signals are high speed differential pairs. Care must be taken in the PCB layout of these signals
to ensure good signal integrity.
The TMDS differential signal traces must be routed to achieve 100 Ohms (+/- 10%) differential impedance
and 60 ohms (+/-10%) single ended impedance. Single ended impedance control is required because
differential signals can’t be closely coupled on PCBs and therefore single ended impedance becomes
important.
These impedances are impacted by trace width, trace spacing, distance to reference planes, and dielectric
material. Verify with a PCB design tool that the trace geometry for both data signal pairs results in as
close to 60 ohms impedance traces as possible. For best accuracy, work with your PCB fabricator to
ensure this impedance is met.
In general, closely coupled differential signal traces are not an advantage on PCBs. When differential
signals are closely coupled, tight spacing and width control is necessary. Very small width and spacing
variations affect impedance dramatically, so tight impedance control can be more problematic to maintain
in production.
Loosely coupled PCB differential signals make impedance control much easier. Wider traces and spacing
make obstacle avoidance easier, and trace width variations don’t affect impedance as much, therefore it’s
easier to maintain accurate impedance over the length of the signal. The wider traces also show reduced
skin effect and therefore often result in better signal integrity.
Some general routing guidelines regarding TMDS:
•
•
•
Avoid crossing splits reference plane(s).
Shorter trace length is preferred.
Distance between common mode filter (CMF) and ESD protection device should be as short as
possible
•
Distance between ESD protection device and HDMI connector should be as short as possible.
表 8-13 shows the routing specifications for the TMDS signals.
表 8-13. TMDS Routing Specifications
PARAMETER
Device balls to HDMI header trace length
MIN
TYP
MAX
4000
5
UNIT
Mils
Mils
stubs
Ω
Skew within a differential pair
3
Number of stubs allowed on TMDS traces
TMDS pair differential impedance
TMDS single-ended impedance
0
90
54
100
60
110
66
Ω
Number of vias on each TMDS trace
TMDS differential pair to any other trace spacing
0
Vias
Mils
(1) (2) (3)
2×DS
3xDS
Number of ground plane cuts allowed within HDMI routing region (except for specific
ground carving as explained in this document)
0
0
Cuts
Number of layers between HDMI routing region and reference ground plane
PCB trace width
Layers
Mils
4.4
(1) DS = differential spacing of the traces.
(2) Exceptions may be necessary in the SoC package BGA area.
(3) GND guard-bands may be closer, but should not be allowed to affect the impedance of the differential pair routing. GND guard-bands to
isolate HDMI differential pairs from all other signals is recommended.
表 8-14. TDMS Routing Recommendations
Item
Description
Reason
ESD part number
TPD1E05U06
Minimize capacitance (0.42pF)
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表 8-14. TDMS Routing Recommendations (continued)
Item
Description
Reason
Minimize capacitance under ESD
and CMF
Carve Ground
Carve GND underneath ESD and CMF
Reduce pad size and round the corners of the pads for the ESD and
CMF components
Round pads
Routing layer
Minimize capacitance
Minimize reflection loss
Route all signals only on the same layer as SoC
图 8-35presents an example layout, demonstrating the “carve GND” concept.
CMF
CMF
CMF
CMF
Top Layer: Routing from SoC through CMF,
and ESD to connector.
Layer2, GND: Gaps carved in GND underneath,
CMF, ESD, and connector.
SPRS85x_PCB_HDMI_3
图 8-35. HDMI Example “carve GND” layout
8.5.4.3 TPD5S115
The TPD5S115 is an integrated HDMI companion chip solution. The device provides a regulated 5 V
output (5VOUT) for sourcing the HDMI power line. The TPD5S115 exceeds the IEC61000-4-2 (Level 4)
ESD protection level.
8.5.4.4 HDMI ESD Protection Device (Required)
Interfaces that connect to a cable such as HDMI generally require more ESD protection than can be built
into the processor’s outputs. Therefore this HDMI interface requires the use of an ESD protection chip to
provide adequate ESD.
When selecting an ESD protection chip, choose the lowest capacitance ESD protection available to
minimize signal degradation. In no case should be ESD protection circuit capacitance be more than 5pF.
TI manufactures these devices that provide ESD protection for HDMI signals such as the TPDxE05U06.
For more information see the www.ti.com website.
8.5.4.5 PCB Stackup Specifications
表 8-15 shows the stackup and feature sizes required for HDMI.
表 8-15. HDMI PCB Stackup Specifications
PARAMETER
MIN
TYP
MAX
UNIT
PCB Routing/Plane Layers
4
6
-
Layers
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表 8-15. HDMI PCB Stackup Specifications (continued)
PARAMETER
MIN
TYP
MAX
UNIT
Signal Routing Layers
2
3
-
Layers
Number of ground plane cuts allowed within HDMI routing
region
-
-
-
0
0
Cuts
Number of layers between HDMI routing region and
reference ground plane
-
Layers
Mils
PCB Trace width
4
8.5.4.6 Grounding
Each TMDS channel has its own shield pin and they should be grounded to provide a return current path
for the TMDS signal.
8.5.5 PCIe Board Design and Layout Guidelines
The PCIe interface on the device provides support for a 5.0 Gbps lane with polarity inversion.
8.5.5.1 PCIe Connections and Interface Compliance
The PCIe interface on the device is compliant with the PCIe revision 3.0 specification. Please refer to the
PCIe specifications for all connections that are described in it. Those recommendations are more
descriptive and exhaustive than what is possible here.
The use of PCIe compatible bridges and switches is allowed for interfacing with more than one other
processor or PCIe device.
8.5.5.1.1 Coupling Capacitors
AC coupling capacitors are required on the transmit data pair. 表 8-16 shows the requirements for these
capacitors.
表 8-16. PCIe AC Coupling Capacitors Requirements
PARAMETER
MIN
TYP
100
MAX
110
UNIT
nF
EIA(1)(2)
PCIe AC coupling capacitor value
PCIe AC coupling capacitor package size
90
0402
0603
(1) EIA LxW units, i.e., a 0402 is a 40x20 mils surface mount capacitor.
(2) The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair placed side by side.
8.5.5.1.2 Polarity Inversion
The PCIe specification requires polarity inversion support. This means for layout purposes, polarity is
unimportant because each signal can change its polarity on die inside the chip. This means polarity within
a lane is unimportant for layout.
8.5.5.2 Non-standard PCIe connections
The following sections contain suggestions for any PCIe connection that is NOT described in the official
PCIe specification, such as an on-board Device to Device or Device to other PCIe compliant processor
connection.
8.5.5.2.1 PCB Stackup Specifications
表 8-17 shows the stackup and feature sizes required for these types of PCIe connections.
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表 8-17. PCIe PCB Stackup Specifications
PARAMETER
MIN
TYP
MAX
UNIT
Number of ground plane cuts allowed within PCIe routing
region
-
-
0
Cuts
Number of layers between PCIe routing area and reference
-
-
0
Layers
(1)
plane
PCB Routing clearance
PCB Trace width
4
4
Mils
Mils
(1) A reference plane may be a ground plane or the power plane referencing the PCIe signals.
8.5.5.2.2 Routing Specifications
8.5.5.2.2.1 Impedance
The PCIe data signal traces must be routed to achieve 100-Ω (±10%) differential impedance and 60-Ω
(±10%) single-ended impedance. The single-ended impedance is required because differential signals are
extremely difficult to closely couple on PCBs and, therefore, single-ended impedance becomes important.
These requirements are the same as those recommended in the PCIe Motherboard Checklist 1.0
document, available from PCI-SIG (www.pcisig.com).
These impedances are impacted by trace width, trace spacing, distance between signals and referencing
planes, and dielectric material. Verify with a PCB design tool that the trace geometry for both data signal
pairs result in as close to 100-Ω differential impedance and 60-Ω single-ended impedance as possible. For
best accuracy, work with your PCB fabricator to ensure this impedance is met. See 表 8-18 below.
8.5.5.2.2.2 Differential Coupling
In general, closely coupled differential signal traces are not an advantage on PCBs. When differential
signals are closely coupled, tight spacing and width control is necessary. Very small width and spacing
variations affect impedance dramatically, so tight impedance control can be more problematic to maintain
in production. For PCBs with very tight space limitations (which are usually small) this can work, but for
most PCBs, the loosely coupled option is probably best.
Loosely coupled PCB differential signals make impedance control much easier. Wider traces and spacing
make obstacle avoidance easier (because each trace is not so fixed in position relative to the other), and
trace width variations don’t affect impedance as much, therefore it’s easier to maintain an accurate
impedance over the length of the signal. For longer routes, the wider traces also show reduced skin effect
and therefore often result in better signal integrity with a larger eye diagram opening.
表 8-18 shows the routing specifications for the PCIe data signals.
表 8-18. PCI-E Routing Specifications
PARAMETER
PCIe signal trace length (device balls to PCIe connector)
Differential pair trace matching
MIN
TYP
MAX
UNIT
Mils
Mils
stubs
Ω
(1)
4700
(2)
5
(3)
Number of stubs allowed on PCIe traces
0
TX/RX pair differential impedance
TX/RX single-ended impedance
Pad size of vias on PCIe trace
90
54
100
60
110
66
Ω
(4)
25
Mils
Mils
Vias
Hole size of vias on PCIe trace
14
0
Number of vias on each PCIe trace
PCIe differential pair to any other trace spacing
(5)
2×DS
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(1) Beyond this, signal integrity may suffer.
(2) For example, RXP0 within 5 Mils of RXN0.
(3) Inline pads may be used for probing.
(4) 35-Mil antipad maximum recommended.
(5) DS = differential spacing of the PCIe traces.
表 8-19. PCI-E Routing Recommendations
Item
Description
Reason
ESD suppression generally not
used on PCIe
ESD part number
None
8.5.5.2.2.3 Pair Length Matching
Each signal in the differential pair should be matched to within 5 mils of its matching differential signal.
Length matching should be done as close to the mismatch as possible.
8.5.5.3 LJCB_REFN/P Connections
A Common Refclk Rx Architecture is required to be used for the device PCIe interface. Specifically, two
modes of Common Refclk Rx Architecture are supported:
•
External REFCLK Mode: An common external 100MHz clock source is distributed to both the Device
and the link partner
•
Output REFCLK Mode: A 100MHz HCSL clock source is output by the device and used by the link
partner
In External REFCLK Mode, a high-quality, low-jitter, differential HCSL 100MHz clock source compliant to
the PCIe REFCLK AC Specifications should be provided on the Device’s ljcb_clkn / ljcb_clkp inputs.
Alternatively, an LVDS clock source can be used with the following additional requirements:
•
External AC coupling capacitors described in 表 8-20 should be populated at the ljcb_clkn / ljcb_clkp
inputs.
•
All termination requirements (ex. parallel 100ohm termination) from the clock source manufacturer
should be followed.
In Output REFCLK Mode, the 100MHz clock from the Device’s DPLL_PCIE_REF should be output on
the Device’s ljcb_clkn / ljcb_clkp pins and used as the HCSL REFCLK by the link partner. External near-
side termination to ground described in 表 8-21 is required on both of the ljcb_clkn / ljcb_clkp outputs in
this mode.
表 8-20. LJCB_REFN/P Requirements in External LVDS REFCLK Mode
PARAMETER
MIN
TYP
100
MAX
UNIT
nF
EIA(1)(2)
ljcb_clkn / ljcb_clkp AC coupling capacitor value
ljcb_clkn / ljcb_clkp AC coupling capacitor package size
0402
0603
(1) EIA LxW units, i.e., a 0402 is a 40x20 mils surface mount capacitor.
(2) The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair placed side by side.
表 8-21. LJCB_REFN/P Requirements in Output REFCLK Mode
PARAMETER
MIN
TYP
MAX
UNIT
ljcb_clkn / ljcb_clkp near-side termination to ground value
47.5
50
52.5
Ohms
8.5.6 CSI2 Board Design and Routing Guidelines
The MIPI D-PHY signals include the CSI2_0 and CSI2_1 camera serial interfaces to or from the Device.
For more information regarding the MIPI-PHY signals and corresponding balls, see 表 4-7, CSI2 Signal
Descriptions.
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For more information, you can also see the MIPI D-PHY specification v1-01-00_r0-03 (specifically the
Interconnect and Lane Configuration and Annex B Interconnect Design Guidelines chapters).
In the next section, the PCB guidelines of the following differential interfaces are presented:
•
CSI2_0 and CSI2_1 MIPI CSI-2 at 1.5 Gbps
表 8-22 lists the MIPI D-PHY interface signals in the Device.
表 8-22. MIPI D-PHY Interface Signals in the Device
SIGNAL NAME
csi2_0_dx0
csi2_0_dx1
csi2_0_dx2
csi2_0_dx3
csi2_0_dx4
csi2_1_dx0
csi2_1_dx1
csi2_1_dx2
BOTTOM BALL
SIGNAL NAME
csi2_0_dy0
csi2_0_dy1
csi2_0_dy2
csi2_0_dy3
csi2_0_dy4
csi2_1_dy0
csi2_1_dy1
csi2_1_dy2
BOTTOM BALL
AE1
AF1
AF2
AH4
AH3
AG5
AG6
AH7
AD2
AE2
AF3
AG4
AG3
AH5
AH6
AG7
8.5.6.1 CSI2_0 and CSI2_1 MIPI CSI-2 (1.5 Gbps)
8.5.6.1.1 General Guidelines
The general guidelines for the PCB differential lines are:
•
•
Differential trace impedance Z0 = 100 Ω (minimum = 85 Ω, maximum = 115 Ω)
Total conductor length from the Device package pins to the peripheral device package pins is 25 to 30
cm with common FR4 PCB and flex materials.
注
Longer interconnect length can be supported at the expense of detailed simulations of the
complete link including driver and receiver models.
The general rule of thumb for the space S = 2 × W is not designated (see 图 8-19, Guard Illustration). It is
because although the S = 2 × W rule is a good rule of thumb, it is not always the best solution. The
electrical performance will be checked with the frequency-domain specification. Even though the designer
does not follow the S = 2 × W rule, the differential lines are ok if the lines satisfy the frequency-domain
specification.
Because the MIPI signals are used for low-power, single-ended signaling in addition to their high-speed
differential implementation, the pairs must be loosely coupled.
8.5.6.1.2 Length Mismatch Guidelines
8.5.6.1.2.1 CSI2_0 and CSI2_1 MIPI CSI-2 (1.5 Gbps)
The guidelines of the length mismatch for CSI-2 are presented in 表 8-23.
表 8-23. Length Mismatch Guidelines for CSI-2 (1.5 Gbps)
PARAMETER
TYPICAL VALUE
UNIT
Mbps
ps
Operating speed
1500
667
UI (bit time)
(1)
Intralane skew
Have to satisfy mode-conversion S parameters
Interlane skew (UI / 50)
PCB lane-to-lane skew (0.1 UI)
13.34
66.7
ps
ps
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(1) sdc12, scd21, scd12, sdc21, scd11, sdc11, scd22, and sdc22
8.5.6.1.3 Frequency-domain Specification Guidelines
After the PCB design is finished, the S-parameters of the PCB differential lines will be extracted with a 3D
Maxwell Equation Solver such as the high-frequency structure simulator (HFSS) or equivalent, and
compared to the frequency-domain specification as defined in the section 7 of the MIPI Alliance
Specification for D-PHY Version v1-01-00_r0-03.
If the PCB lines satisfy the frequency-domain specification, the design is finished. Otherwise, the design
needs to be improved.
8.6 DDR3 Board Design and Layout Guidelines
8.6.1 DDR3 General Board Layout Guidelines
To help ensure good signaling performance, consider the following board design guidelines:
•
•
•
•
•
•
•
•
•
•
•
Avoid crossing splits in the power plane.
Minimize Vref noise.
Use the widest trace that is practical between decoupling capacitors and memory module.
Maintain a single reference.
Minimize ISI by keeping impedances matched.
Minimize crosstalk by isolating sensitive bits, such as strobes, and avoiding return path discontinuities.
Use proper low-pass filtering on the Vref pins.
Keep the stub length as short as possible.
Add additional spacing for on-clock and strobe nets to eliminate crosstalk.
Maintain a common ground reference for all bypass and decoupling capacitors.
Take into account the differences in propagation delays between microstrip and stripline nets when
evaluating timing constraints.
8.6.2 DDR3 Board Design and Layout Guidelines
8.6.2.1 Board Designs
TI only supports board designs using DDR3 memory that follow the guidelines in this document. The
switching characteristics and timing diagram for the DDR3 memory controller are shown in 表 8-24 and 图
8-36.
表 8-24. Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory
Controller
NO.
PARAMETER
MIN
MAX
UNIT
1
tc(DDR_CLK)
Cycle time, DDR_CLK
1.5
2.5(1)
ns
(1) This is the absolute maximum the clock period can be. Actual maximum clock period may be limited by DDR3 speed grade and
operating frequency (see the DDR3 memory device data sheet).
1
DDR_CLK
SPRS906_PCB_DDR3_01
图 8-36. DDR3 Memory Controller Clock Timing
8.6.2.2 DDR3 EMIF
The processor contains one DDR3 EMIF.
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8.6.2.3 DDR3 Device Combinations
Because there are several possible combinations of device counts and single- or dual-side mounting, 表
8-25 summarizes the supported device configurations.
表 8-25. Supported DDR3 Device Combinations
NUMBER OF DDR3 DEVICES
DDR3 DEVICE WIDTH (BITS)
MIRRORED?
DDR3 EMIF WIDTH (BITS)
1
2
2
2
3
4
4
5
16
8
N
Y(1)
N
Y(1)
N(3)
N
16
16
32
32
32
32
32
32
16
16
16
8
8
Y(2)
(3)
8
N
(1) Two DDR3 devices are mirrored when one device is placed on the top of the board and the second device is placed on the bottom of
the board.
(2) This is two mirrored pairs of DDR3 devices.
(3) Three or five DDR3 device combination is not available on this device, but combination types are retained for consistency with the
TDA2xx family of devices.
8.6.2.4 DDR3 Interface Schematic
8.6.2.4.1 32-Bit DDR3 Interface
The DDR3 interface schematic varies, depending upon the width of the DDR3 devices used and the width
of the bus used (16 or 32 bits). General connectivity is straightforward and very similar. 16-bit DDR
devices look like two 8-bit devices. 图 8-37 and 图 8-38 show the schematic connections for 32-bit
interfaces using x16 devices.
8.6.2.4.2 16-Bit DDR3 Interface
Note that the 16-bit wide interface schematic is practically identical to the 32-bit interface (see 图 8-37 and
图 8-38); only the high-word DDR memories are removed and the unused DQS inputs are tied off.
When not using all or part of a DDR interface, the proper method of handling the unused pins is to tie off
the ddr1_dqsi pins to ground via a 1k-Ω resistor and to tie off the ddr1_dqsni pins to the corresponding
vdds_ddrx supply via a 1k-Ω resistor. This needs to be done for each byte not used. Although these
signals have internal pullups and pulldowns, external pullups and pulldowns provide additional protection
against external electrical noise causing activity on the signals.
The vdds_ddrx and ddr1_vref0 power supply pins need to be connected to their respective power supplies
even if ddrx is not being used. All other DDR interface pins can be left unconnected. Note that the
supported modes for use of the DDR EMIF are 32-bits wide, 16-bits wide, or not used.
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32-bit DDR3 EMIF
16-Bit DDR3
Devices
ddr1_d31
ddr1_d24
DQ15
8
DQ8
ddr1_dqm3
ddr1_dqs3
ddr1_dqsn3
UDM
UDQS
UDQS
ddr1_d23
DQ7
8
ddr1_d16
ddr1_dqm2
ddr1_dqs2
ddr1_dqsn2
D08
LDM
LDQS
LDQS
ddr1_d15
DQ15
DQ8
8
8
ddr1_d8
ddr1_dqm1
ddr1_dqs1
ddr1_dqsn1
ddr1_d7
UDM
UDQS
UDQS
DQ7
ddr1_d0
ddr1_dqm0
ddr1_dqs0
ddr1_dqsn0
ddr1_ck
DQ0
LDM
LDQS
LDQS
CK
0.1 µF
Zo
Zo
CK
CK
DDR_1V5
ddr1_nck
CK
ddr1_odt0
ddr1_csn0
ddr1_odt1
ddr1_csn1
ODT
CS
ODT
CS
ddr1_ba0
ddr1_ba1
ddr1_ba2
ddr1_a0
BA0
BA1
BA2
A0
BA0
BA1
BA2
A0
DDR_VTT
Zo
Zo
16
ddr1_a15
ddr1_casn
ddr1_rasn
ddr1_wen
ddr1_cke
ddr1_rst
A15
A15
CAS
RAS
WE
CAS
RAS
WE
CKE
CKE
RST
DDR_VREF
RST
ZQ
ZQ
ZQ
ZQ
VREFDQ
VREFCA
VREFDQ
VREFCA
ddr1_vref0
0.1 µF
0.1 µF
0.1 µF
Zo
ZQ
Termination is required. See terminator comments.
Value determined according to the DDR memory device data sheet.
SPRS906_PCB_DDR3_02
图 8-37. 32-Bit, One-Bank DDR3 Interface Schematic Using Two 16-Bit DDR3 Devices
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32-bit DDR3 EMIF
8-Bit DDR3
Devices
8-Bit DDR3
Devices
ddrx_d31
8
DQ7
DQ0
ddrx_d24
ddrx_dqm3
DM/TQS
TDQS
DQS
NC
ddrx_dqs3
ddrx_dqsn3
DQS
ddrx_d23
8
DQ7
DQ0
ddrx_d16
ddrx_dqm2
DM/TQS
TDQS
NC
ddrx_dqs2
DQS
DQS
ddrx_dqsn2
ddrx_d15
8
DQ7
ddrx_d8
DQ0
ddrx_dqm1
DM/TQS
TDQS
DQS
NC
ddrx_dqs1
ddrx_dqsn1
DQS
ddrx_d7
ddrx_d0
DQ7
DQ0
8
NC
TDQS
DM/TQS
ddrx_dqm0
ddrx_dqs0
ddrx_dqsn0
ddrx_ck
DQS
DQS
CK
0.1 µF
Zo
Zo
CK
CK
CK
CK
CK
CK
DDR_1V5
ddrx_nck
CK
ddrx_odt0
ddrx_csn0
ddrx_odt1
ddrx_csn1
ddrx_ba0
ddrx_ba1
ddrx_ba2
ddrx_a0
ODT
CS
ODT
CS
ODT
CS
ODT
CS
BA0
BA1
BA2
A0
BA0
BA1
BA2
A0
BA0
BA1
BA2
A0
BA0
BA1
BA2
A0
DDR_VTT
Zo
Zo
16
ddrx_a15
ddrx_casn
ddrx_rasn
ddrx_wen
ddrx_cke
ddrx_rst
A15
A15
CAS
RAS
WE
A15
A15
CAS
RAS
WE
CAS
CAS
RAS
RAS
WE
WE
CKE
CKE
RST
CKE
CKE
RST
RST
RST
DDR_VREF
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
VREFCA
ddrx_vref0
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
Zo
Termination is required. See terminator comments.
Value determined according to the DDR memory device data sheet.
ZQ
SPRS906_PCB_DDR3_03
图 8-38. 32-Bit, One-Bank DDR3 Interface Schematic Using Four 8-Bit DDR3 Devices
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8.6.2.5 Compatible JEDEC DDR3 Devices
表 8-26 shows the parameters of the JEDEC DDR3 devices that are compatible with this interface.
Generally, the DDR3 interface is compatible with DDR3-1333 devices in the x8 or x16 widths.
表 8-26. Compatible JEDEC DDR3 Devices (Per Interface)
N
PARAMETER
CONDITION
MIN
MAX
UNIT
O.
1
JEDEC DDR3 device speed grade(1)
DDR clock rate = 400MHz
DDR3-800
DDR3-1066
DDR3-1333
x8
DDR3-1600
DDR3-1600
DDR3-1600
x16
400MHz< DDR clock rate ≤ 533MHz
533MHz< DDR clock rate ≤ 667MHz
2
3
JEDEC DDR3 device bit width
JEDEC DDR3 device count(2)
Bits
2
4
Devices
(1) Refer to 表 8-24 Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory Controller for the range of
supported DDR clock rates.
(2) For valid DDR3 device configurations and device counts, see 节 8.6.2.4, 图 8-37, and 图 8-38.
8.6.2.6 PCB Stackup
The minimum stackup for routing the DDR3 interface is a six-layer stack up as shown in 表 8-27.
Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance SI/EMI
performance, or to reduce the size of the PCB footprint. Complete stackup specifications are provided in
表 8-28.
表 8-27. Six-Layer PCB Stackup Suggestion
LAYER
TYPE
Signal
Plane
Plane
Plane
Plane
Signal
DESCRIPTION
1
2
3
4
5
6
Top routing mostly vertical
Ground
Split power plane
Split power plane or Internal routing
Ground
Bottom routing mostly horizontal
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表 8-28. PCB Stackup Specifications
NO.
PARAMETER
MIN
TYP
MAX
UNIT
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PS8
PS9
PS10
PCB routing/plane layers
Signal routing layers
6
3
1
1
Full ground reference layers under DDR3 routing region(1)
Full 1.5-V power reference layers under the DDR3 routing region(1)
Number of reference plane cuts allowed within DDR routing region(2)
Number of layers between DDR3 routing layer and reference plane(3)
PCB routing feature size
0
0
4
4
Mils
Mils
Ω
PCB trace width, w
Single-ended impedance, Zo
Impedance control(5)
50
75
Z-5
Z
Z+5
Ω
(1) Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer
return current as the trace routes switch routing layers.
(2) No traces should cross reference plane cuts within the DDR routing region. High-speed signal traces crossing reference plane cuts
create large return current paths which can lead to excessive crosstalk and EMI radiation.
(3) Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.
(4) An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available
for power routing. An 18-mil pad is required for minimum layer count escape.
(5) Z is the nominal singled-ended impedance selected for the PCB specified by PS9.
8.6.2.7 Placement
图 8-39 shows the required placement for the processor as well as the DDR3 devices. The dimensions for
this figure are defined in 表 8-29. The placement does not restrict the side of the PCB on which the
devices are mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and
allow for proper routing space. For a 16-bit DDR memory system, the high-word DDR3 devices are
omitted from the placement.
图 8-39. Placement Specifications
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表 8-29. Placement Specifications DDR3
NO.
PARAMETER
MIN
MAX
500
UNIT
Mils
Mils
Mils
Mils
Mils
KOD31 X1
KOD32 X2
KOD33 X3
KOD34 Y1
KOD35 Y2
600
600
1800
600
KOD36 DDR3 keepout region (1)
KOD37 Clearance from non-DDR3 signal
to DDR3 keepout region (2) (3)
4
W
(1) DDR3 keepout region to encompass entire DDR3 routing area.
(2) Non-DDR3 signals allowed within DDR3 keepout region provided they are separated from DDR3 routing layers by a ground plane.
(3) If a device has more than one DDR controller, the signals from the other controller(s) are considered non-DDR3 and should be
separated by this specification.
8.6.2.8 DDR3 Keepout Region
The region of the PCB used for DDR3 circuitry must be isolated from other signals. The DDR3 keepout
region is defined for this purpose and is shown in 图 8-40. The size of this region varies with the
placement and DDR routing. Additional clearances required for the keepout region are shown in 表 8-29.
Non-DDR3 signals should not be routed on the DDR signal layers within the DDR3 keepout region. Non-
DDR3 signals may be routed in the region, provided they are routed on layers separated from the DDR
signal layers by a ground layer. No breaks should be allowed in the reference ground layers in this region.
In addition, the 1.5-V DDR3 power plane should cover the entire keepout region. Also note that the two
signals from the DDR3 controller should be separated from each other by the specification in 表 8-29 (see
KOD37).
图 8-40. DDR3 Keepout Region
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8.6.2.9 Bulk Bypass Capacitors
Bulk bypass capacitors are required for moderate speed bypassing of the DDR3 and other circuitry. 表 8-
30 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this
table only covers the bypass needs of the DDR3 controllers and DDR3 devices. Additional bulk bypass
capacitance may be needed for other circuitry.
表 8-30. Bulk Bypass Capacitors
NO.
1
PARAMETER
vdds_ddrx bulk bypass capacitor count(1)
vdds_ddrx bulk bypass total capacitance
MIN
1
MAX
UNIT
Devices
μF
2
22
(1) These devices should be placed near the devices they are bypassing, but preference should be given to the placement of the high-
speed (HS) bypass capacitors and DDR3 signal routing.
8.6.2.10 High-Speed Bypass Capacitors
High-speed (HS) bypass capacitors are critcal for proper DDR3 interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass capacitors, processor/DDR power,
and processor/DDR ground connections. 表 8-31 contains the specification for the HS bypass capacitors
as well as for the power connections on the PCB. Generally speaking, it is good to:
1. Fit as many HS bypass capacitors as possible.
2. Minimize the distance from the bypass cap to the pins/balls being bypassed.
3. Use the smallest physical sized capacitors possible with the highest capacitance readily available.
4. Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest
hole size via possible.
5. Minimize via sharing. Note the limites on via sharing shown in 表 8-31.
表 8-31. High-Speed Bypass Capacitors
NO.
1
PARAMETER
HS bypass capacitor package size(1)
MIN
TYP
MAX
0402
400
UNIT
10 Mils
Mils
0201
2
Distance, HS bypass capacitor to processor being bypassed(2)(3)(4)
Processor HS bypass capacitor count per vdds_ddrx rail(12)
Processor HS bypass capacitor total capacitance per vdds_ddrx rail(12)
Number of connection vias for each device power/ground ball(5)
Trace length from device power/ground ball to connection via(2)
Distance, HS bypass capacitor to DDR device being bypassed(6)
DDR3 device HS bypass capacitor count(7)
3
See 表 8-3 and (11)
See 表 8-3 and (11)
Devices
μF
4
5
Vias
6
35
70
Mils
7
150
Mils
8
12
0.85
2
Devices
μF
9
DDR3 device HS bypass capacitor total capacitance(7)
10 Number of connection vias for each HS capacitor(8)(9)
11 Trace length from bypass capacitor connect to connection via(2)(9)
12 Number of connection vias for each DDR3 device power/ground ball(10)
13 Trace length from DDR3 device power/ground ball to connection via(2)(8)
(1) LxW, 10-mil units, that is, a 0402 is a 40x20-mil surface-mount capacitor.
(2) Closer/shorter is better.
Vias
35
35
100
60
Mils
1
Vias
Mils
(3) Measured from the nearest processor power/ground ball to the center of the capacitor package.
(4) Three of these capacitors should be located underneath the processor, between the cluster of DDR_1V5 balls and ground balls,
between the DDR interfaces on the package.
(5) See the Via Channel™ escape for the processor package.
(6) Measured from the DDR3 device power/ground ball to the center of the capacitor package.
(7) Per DDR3 device.
(8) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of
vias is permitted on the same side of the board.
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(9) An HS bypass capacitor may share a via with a DDR device mounted on the same side of the PCB. A wide trace should be used for the
connection and the length from the capacitor pad to the DDR device pad should be less than 150 mils.
(10) Up to a total of two pairs of DDR power/ground balls may share a via.
(11) The capacitor recommendations in this data manual reflect only the needs of this processor. Please see the memory vendor’s
guidelines for determining the appropriate decoupling capacitor arrangement for the memory device itself.
(12) For more information, see 节 8.3, Core Power Domains.
8.6.2.10.1 Return Current Bypass Capacitors
Use additional bypass capacitors if the return current reference plane changes due to DDR3 signals
hopping from one signal layer to another. The bypass capacitor here provides a path for the return current
to hop planes along with the signal. As many of these return current bypass capacitors should be used as
possible. Because these are returns for signal current, the signal via size may be used for these
capacitors.
8.6.2.11 Net Classes
表 8-32 lists the clock net classes for the DDR3 interface. 表 8-33 lists the signal net classes, and
associated clock net classes, for signals in the DDR3 interface. These net classes are used for the
termination and routing rules that follow.
表 8-32. Clock Net Class Definitions
CLOCK NET CLASS processor PIN NAMES
CK
ddr1_ck/ddr1_nck
DQS0
ddr1_dqs0 / ddr1_dqsn0
ddr1_dqs1 / ddr1_dqsn1
ddr1_dqs2 / ddr1_dqsn2
ddr1_dqs3 / ddr1_dqsn3
DQS1
DQS2(1)
DQS3(1)
(1) Only used on 32-bit wide DDR3 memory systems.
表 8-33. Signal Net Class Definitions
ASSOCIATED CLOCK
SIGNAL NET CLASS
processor PIN NAMES
NET CLASS
ADDR_CTRL
CK
ddr1_ba[2:0], ddr1_a[14:0], ddr1_csnj, ddr1_casn, ddr1_rasn, ddr1_wen,
ddr1_cke, ddr1_odti
DQ0
DQ1
DQ2(1)
DQ3(1)
DQS0
DQS1
DQS2
DQS3
ddr1_d[7:0], ddr1_dqm0
ddr1_d[15:8], ddr1_dqm1
ddr1_d[23:16], ddr1_dqm2
ddr1_d[31:24], ddr1_dqm3
(1) Only used on 32-bit wide DDR3 memory systems.
8.6.2.12 DDR3 Signal Termination
Signal terminators are required for the CK and ADDR_CTRL net classes. The data lines are terminated by
ODT and, thus, the PCB traces should be unterminated. Detailed termination specifications are covered in
the routing rules in the following sections.
8.6.2.13 VREF_DDR Routing
ddr1_vref0 (VREF) is used as a reference by the input buffers of the DDR3 memories as well as the
processor. VREF is intended to be half the DDR3 power supply voltage and is typically generated with the
DDR3 VDDS and VTT power supply. It should be routed as a nominal 20-mil wide trace with 0.1 µF
bypass capacitors near each device connection. Narrowing of VREF is allowed to accommodate routing
congestion.
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8.6.2.14 VTT
Like VREF, the nominal value of the VTT supply is half the DDR3 supply voltage. Unlike VREF, VTT is
expected to source and sink current, specifically the termination current for the ADDR_CTRL net class
Thevinen terminators. VTT is needed at the end of the address bus and it should be routed as a power
sub-plane. VTT should be bypassed near the terminator resistors.
8.6.2.15 CK and ADDR_CTRL Topologies and Routing Definition
The CK and ADDR_CTRL net classes are routed similarly and are length matched to minimize skew
between them. CK is a bit more complicated because it runs at a higher transition rate and is differential.
The following subsections show the topology and routing for various DDR3 configurations for CK and
ADDR_CTRL. The figures in the following subsections define the terms for the routing specification
detailed in 表 8-34.
8.6.2.15.1 Four DDR3 Devices
Four DDR3 devices are supported on the DDR EMIF consisting of four x8 DDR3 devices arranged as one
bank (CS). These four devices may be mounted on a single side of the PCB, or may be mirrored in two
pairs to save board space at a cost of increased routing complexity and parts on the backside of the PCB.
8.6.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
图 8-41 shows the topology of the CK net classes and 图 8-42 shows the topology for the corresponding
ADDR_CTRL net classes.
DDR Differential CK Input Buffers
–
–
–
–
+
+
+
+
Clock Parallel
Terminator
DDR_1V5
Rcp
A1
A1
A2
A2
A3
A3
A4
A4
A3
A3
AT
AT
Cac
Processor
Differential Clock
Output Buffer
+
–
0.1 µF
Rcp
Routed as Differential Pair
SPRS906_PCB_DDR3_06
图 8-41. CK Topology for Four x8 DDR3 Devices
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DDR Address and Control Input Buffers
Address and Control
Terminator
Rtt
Processor
Address and Control
Output Buffer
A1
A2
A3
A4
A3
AT
VTT
SPRS906_PCB_DDR3_07
图 8-42. ADDR_CTRL Topology for Four x8 DDR3 Devices
8.6.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
图 8-43 shows the CK routing for four DDR3 devices placed on the same side of the PCB. 图 8-44 shows
the corresponding ADDR_CTRL routing.
DDR_1V5
Cac
Rcp
Rcp
A2
A2
A3
A3
A4
A4
A3
A3
AT
AT
0.1 µF
=
SPRS906_PCB_DDR3_08
图 8-43. CK Routing for Four Single-Side DDR3 Devices
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Rtt
A2
A3
A4
A3
AT
VTT
=
SPRS906_PCB_DDR3_09
图 8-44. ADDR_CTRL Routing for Four Single-Side DDR3 Devices
To save PCB space, the four DDR3 memories may be mounted as two mirrored pairs at a cost of
increased routing and assembly complexity. 图 8-45 and 图 8-46 show the routing for CK and
ADDR_CTRL, respectively, for four DDR3 devices mirrored in a two-pair configuration.
DDR_1V5
Cac
Rcp
Rcp
A2
A2
A3
A3
A4
A4
A3
A3
AT
AT
0.1 µF
=
SPRS906_PCB_DDR3_10
图 8-45. CK Routing for Four Mirrored DDR3 Devices
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Rtt
A2
A3
A4
A3
AT
VTT
=
SPRS906_PCB_DDR3_11
图 8-46. ADDR_CTRL Routing for Four Mirrored DDR3 Devices
8.6.2.15.2 Two DDR3 Devices
Two DDR3 devices are supported on the DDR EMIF consisting of two x8 DDR3 devices arranged as one
bank (CS), 16 bits wide, or two x16 DDR3 devices arranged as one bank (CS), 32 bits wide. These two
devices may be mounted on a single side of the PCB, or may be mirrored in a pair to save board space at
a cost of increased routing complexity and parts on the backside of the PCB.
8.6.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
图 8-47 shows the topology of the CK net classes and 图 8-48 shows the topology for the corresponding
ADDR_CTRL net classes.
DDR Differential CK Input Buffers
–
–
+
+
Clock Parallel
Terminator
DDR_1V5
Rcp
A1
A1
A2
A2
A3
A3
AT
AT
Cac
Processor
Differential Clock
Output Buffer
+
–
0.1 µF
Rcp
Routed as Differential Pair
SPRS906_PCB_DDR3_12
图 8-47. CK Topology for Two DDR3 Devices
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DDR Address and Control Input Buffers
Address and Control
Terminator
Rtt
Processor
Address and Control
Output Buffer
A1
A2
A3
AT
VTT
SPRS906_PCB_DDR3_13
图 8-48. ADDR_CTRL Topology for Two DDR3 Devices
8.6.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
图 8-49 shows the CK routing for two DDR3 devices placed on the same side of the PCB. 图 8-50 shows
the corresponding ADDR_CTRL routing.
DDR_1V5
Cac
Rcp
Rcp
A2
A2
A3
A3
AT
AT
0.1 µF
=
SPRS906_PCB_DDR3_14
图 8-49. CK Routing for Two Single-Side DDR3 Devices
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Rtt
A2
A3
AT
VTT
=
SPRS906_PCB_DDR3_15
图 8-50. ADDR_CTRL Routing for Two Single-Side DDR3 Devices
To save PCB space, the two DDR3 memories may be mounted as a mirrored pair at a cost of increased
routing and assembly complexity. 图 8-51 and 图 8-52 show the routing for CK and ADDR_CTRL,
respectively, for two DDR3 devices mirrored in a single-pair configuration.
DDR_1V5
Cac
Rcp
Rcp
A2
A2
A3
A3
AT
AT
0.1 µF
=
SPRS906_PCB_DDR3_16
图 8-51. CK Routing for Two Mirrored DDR3 Devices
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Rtt
A2
A3
AT
VTT
=
SPRS906_PCB_DDR3_17
图 8-52. ADDR_CTRL Routing for Two Mirrored DDR3 Devices
8.6.2.15.3 One DDR3 Device
A single DDR3 device is supported on the DDR EMIF consisting of one x16 DDR3 device arranged as
one bank (CS), 16 bits wide.
8.6.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
图 8-53 shows the topology of the CK net classes and 图 8-54 shows the topology for the corresponding
ADDR_CTRL net classes.
DDR Differential CK Input Buffer
–
+
Clock Parallel
Terminator
DDR_1V5
Rcp
A1
A1
A2
A2
AT
AT
Cac
Processor
Differential Clock
Output Buffer
+
–
0.1 µF
Rcp
Routed as Differential Pair
SPRS906_PCB_DDR3_18
图 8-53. CK Topology for One DDR3 Device
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DDR Address and Control Input Buffers
Address and Control
Terminator
Rtt
Processor
Address and Control
Output Buffer
A1
A2
AT
VTT
SPRS906_PCB_DDR3_19
图 8-54. ADDR_CTRL Topology for One DDR3 Device
8.6.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
图 8-55 shows the CK routing for one DDR3 device placed on the same side of the PCB. 图 8-56 shows
the corresponding ADDR_CTRL routing.
DDR_1V5
Cac
Rcp
Rcp
A2
A2
AT
AT
0.1 µF
=
SPRS906_PCB_DDR3_20
图 8-55. CK Routing for One DDR3 Device
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Rtt
A2
AT
VTT
=
SPRS906_PCB_DDR3_21
图 8-56. ADDR_CTRL Routing for One DDR3 Device
8.6.2.16 Data Topologies and Routing Definition
No matter the number of DDR3 devices used, the data line topology is always point to point, so its
definition is simple.
Care should be taken to minimize layer transitions during routing. If a layer transition is necessary, it is
better to transition to a layer using the same reference plane. If this cannot be accommodated, ensure
there are nearby ground vias to allow the return currents to transition between reference planes if both
reference planes are ground or vdds_ddr. Ensure there are nearby bypass capacitors to allow the return
currents to transition between reference planes if one of the reference planes is ground. The goal is to
minimize the size of the return current loops.
8.6.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
DQS lines are point-to-point differential, and DQ/DM lines are point-to-point singled ended. 图 8-57 and 图
8-58 show these topologies.
Processor
DQS
DDR
DQSn+
DQSn-
DQS
IO Buffer
IO Buffer
Routed Differentially
n = 0, 1, 2, 3
SPRS906_PCB_DDR3_22
图 8-57. DQS Topology
Processor
DQ and DM
IO Buffer
DDR
Dn
DQ and DM
IO Buffer
n = 0, 1, 2, 3
SPRS906_PCB_DDR3_23
图 8-58. DQ/DM Topology
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8.6.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
图 8-59 and 图 8-60 show the DQS and DQ/DM routing.
DQS
DQSn+
DQSn-
Routed Differentially
n = 0, 1, 2, 3
SPRS906_PCB_DDR3_24
图 8-59. DQS Routing With Any Number of Allowed DDR3 Devices
DQ and DM
Dn
n = 0, 1, 2, 3
SPRS906_PCB_DDR3_25
图 8-60. DQ/DM Routing With Any Number of Allowed DDR3 Devices
8.6.2.17 Routing Specification
8.6.2.17.1 CK and ADDR_CTRL Routing Specification
Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this
skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter
traces up to the length of the longest net in the net class and its associated clock. A metric to establish
this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the
length between the points when connecting them only with horizontal or vertical segments. A reasonable
trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address
Control Longest Manhattan distance.
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Given the clock and address pin locations on the processor and the DDR3 memories, the maximum
possible Manhattan distance can be determined given the placement. 图 8-61 and 图 8-62 show this
distance for four loads and two loads, respectively. It is from this distance that the specifications on the
lengths of the transmission lines for the address bus are determined. CACLM is determined similarly for
other address bus configurations; that is, it is based on the longest net of the CK/ADDR_CTRL net class.
For CK and ADDR_CTRL routing, these specifications are contained in 表 8-34.
A8(A)
CACLMY
CACLMX
A8(A)
A8(A)
A8(A)
A8(A)
Rtt
A2
A3
A4
A3
AT
VTT
=
SPRS906_PCB_DDR3_26
A. It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3
memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that
satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control.
The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this
length calculation. Non-included lengths are grayed out in the figure.
Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.
The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.
图 8-61. CACLM for Four Address Loads on One Side of PCB
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A8(A)
CACLMY
CACLMX
A8(A)
A8(A)
Rtt
A2
A3
AT
VTT
=
SPRS906_PCB_DDR3_27
A. It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3
memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that
satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control.
The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this
length calculation. Non-included lengths are grayed out in the figure.
Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.
The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.
图 8-62. CACLM for Two Address Loads on One Side of PCB
表 8-34. CK and ADDR_CTRL Routing Specification(2)(3)
NO.
PARAMETER
MIN
TYP
MAX
500(1)
29
UNIT
ps
CARS31
CARS32
CARS33
CARS34
CARS35
CARS36
CARS37
CARS38
CARS39
CARS310
CARS311
CARS312
CARS313
CARS314
CARS315
CARS316
CARS317
CARS318
CARS319
CARS320
A1+A2 length
A1+A2 skew
A3 length
A3 skew(4)
A3 skew(5)
A4 length
ps
125
6
ps
ps
6
ps
125
6
17(1)
14(1)
12
ps
A4 skew
ps
AS length
5
1.3
5
ps
AS skew
ps
AS+/AS- length
AS+/AS- skew
AT length(6)
AT skew(7)
AT skew(8)
ps
1
ps
75
14
ps
ps
1
ps
CK/ADDR_CTRL trace length
1020
3(1)
1(15)
ps
Vias per trace
vias
vias
Via count difference
Center-to-center CK to other DDR3 trace spacing(9)
Center-to-center ADDR_CTRL to other DDR3 trace spacing(9)(10)
4w
4w
3w
Center-to-center ADDR_CTRL to other ADDR_CTRL trace
spacing(9)
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表 8-34. CK and ADDR_CTRL Routing Specification(2)(3) (continued)
NO.
PARAMETER
CK center-to-center spacing(11)(12)
CK spacing to other net(9)
Rcp(13)
MIN
TYP
MAX
UNIT
CARS321
CARS322
CARS323
CARS324
4w
Zo-1
Zo-5
Zo
Zo
Zo+1
Zo+5
Ω
Ω
Rtt(13)(14)
(1) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of
rise time and fall time confirms desired operation.
(2) The use of vias should be minimized.
(3) Additional bypass capacitors are required when using the DDR_1V5 plane as the reference plane to allow the return current to jump
between the DDR_1V5 plane and the ground plane when the net class switches layers at a via.
(4) Non-mirrored configuration (all DDR3 memories on same side of PCB).
(5) Mirrored configuration (one DDR3 device on top of the board and one DDR3 device on the bottom).
(6) While this length can be increased for convenience, its length should be minimized.
(7) ADDR_CTRL net class only (not CK net class). Minimizing this skew is recommended, but not required.
(8) CK net class only.
(9) Center-to-center spacing is allowed to fall to minimum 2w for up to 1250 mils of routed length.
(10) The ADDR_CTRL net class of the other DDR EMIF is considered other DDR3 trace spacing.
(11) CK spacing set to ensure proper differential impedance.
(12) The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking,
center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended
impedance, Zo.
(13) Source termination (series resistor at driver) is specifically not allowed.
(14) Termination values should be uniform across the net class.
(15) Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal
propagation through vias – has been applied to ensure all segment skew maximums are not exceeded.
8.6.2.17.2 DQS and DQ Routing Specification
Skew within the DQS and DQ/DM net classes directly reduces setup and hold margin and thus this skew
must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces
up to the length of the longest net in the net class and its associated clock. As with CK and ADDR_CTRL,
a reasonable trace route length is to within a percentage of its Manhattan distance. DQLMn is defined as
DQ Longest Manhattan distance n, where n is the byte number. For a 32-bit interface, there are four
DQLMs, DQLM0-DQLM3. Likewise, for a 16-bit interface, there are two DQLMs, DQLM0-DQLM1.
注
It is not required, nor is it recommended, to match the lengths across all bytes. Length
matching is only required within each byte.
Given the DQS and DQ/DM pin locations on the processor and the DDR3 memories, the maximum
possible Manhattan distance can be determined given the placement. 图 8-63 shows this distance for four
loads. It is from this distance that the specifications on the lengths of the transmission lines for the data
bus are determined. For DQS and DQ/DM routing, these specifications are contained in 表 8-35.
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DQLMX0
DB0
DQ[0:7]/DM0/DQS0
DQ[8:15]/DM1/DQS1
DB1
DQLMX1
DQ[16:23]/DM2/DQS2
DB2
DQLMX2
DQ[23:31]/DM3/DQS3
DQLMY0
DQLMY1
DQLMY3 DQLMY2
DB3
DQLMX3
3
2
1
0
DB0 - DB3 represent data bytes 0 - 3.
SPRS906_PCB_DDR3_28
There are four DQLMs, one for each byte (32-bit interface). Each DQLM is the longest Manhattan distance of the
byte; therefore:
DQLM0 = DQLMX0 + DQLMY0
DQLM1 = DQLMX1 + DQLMY1
DQLM2 = DQLMX2 + DQLMY2
DQLM3 = DQLMX3 + DQLMY3
图 8-63. DQLM for Any Number of Allowed DDR3 Devices
表 8-35. Data Routing Specification(2)
NO.
PARAMETER
MIN
TYP
MAX
340
340
340
340
5
UNIT
ps
DRS31
DRS32
DRS33
DRS34
DRS35
DRS36
DRS37
DRS38
DRS39
DRS310
DRS311
DRS312
DRS313
DB0 length
DB1 length
ps
DB2 length
ps
DB3 length
DBn skew(3)
ps
ps
DQSn+ to DQSn- skew
DQSn to DBn skew(3)(4)
Vias per trace
Via count difference
1
ps
5(10)
2(1)
0(10)
ps
vias
vias
w(5)
w(5)
Center-to-center DBn to other DDR3 trace spacing(6)
Center-to-center DBn to other DBn trace spacing(7)
DQSn center-to-center spacing(8)(9)
4
3
DQSn center-to-center spacing to other net
4
w(5)
(1) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of
rise time and fall time confirms desired operation.
(2) External termination disallowed. Data termination should use built-in ODT functionality.
(3) Length matching is only done within a byte. Length matching across bytes is neither required nor recommended.
(4) Each DQS pair is length matched to its associated byte.
(5) Center-to-center spacing is allowed to fall to minimum 2w for up to 1250 mils of routed length.
(6) Other DDR3 trace spacing means other DDR3 net classes not within the byte.
(7) This applies to spacing within the net classes of a byte.
(8) DQS pair spacing is set to ensure proper differential impedance.
(9) The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking,
center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended
impedance, Zo.
(10) Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal
propagation through vias – has been applied to ensure DBn skew and DQSn to DBn skew maximums are not exceeded.
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9 Device and Documentation Support
TI offers an extensive line of development tools, including methods to evaluate the performance of the
processors, generate code, develop algorithm implementations, and fully integrate and debug software
and hardware modules as listed below.
9.1 Device Nomenclature and Orderable Information
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix)
(for example, TDA2Ex). Texas Instruments recommends two of three possible prefix designators for its
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
X
Experimental device that is not necessarily representative of the final device's electrical
specifications and may not use production assembly flow.
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet
final electrical specifications.
null
Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality
and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
For orderable part numbers of TDA2Ex devices in the ABC package type, see the Package Option
Addendum of this document, the TI website (www.ti.com), or contact your TI sales representative.
For additional description of the device nomenclature markings on the die, see the Silicon Errata (literature
number SPRZ428 ).
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9.1.1 Standard Package Symbolization
TDA
aBBBBBIrzYTPPPQ1
XXXXXXX
PIN ONE INDICATOR
G1
ZZZ
YYY
O
SWPS859_PACK_01
图 9-1. Printed Device Reference
注
Some devices have a cosmetic circular marking visible on the top of the device package
which results from the production test process. These markings are cosmetic only with no
reliability impact.
9.1.2 Device Naming Convention
表 9-1. Nomenclature Description
FIELD
FIELD DESCRIPTION
VALUES
DESCRIPTION
PARAMETER
SYMBOLIZATION
ORDERABLE
a
Device evolution stage(1)
X
Contact TI
Prototype
P
Preproduction (production test flow, no
reliability data)
BLANK
Production
BBBBB
I
Base production part number
Device Identity
TDA2E
ADAS 2nd Generation Eco Tier
Scene Viewing
GFX enabled
SR 1.0
V
G
r
Device revision
Device Speed
BLANK
A
D
H
SR 2.0
z
Indicates the speed grade for each of the
cores in the device. For more information see
表 3-1, Device Comparison.
Y
Device type
BLANK
General purpose (Prototype and Production)
Emulation (E) devices
E
D
High security prototype devices with TI
Development keys (D)
(2)
T
Temperature
Q
Full temp range: -40°C to 125°C
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表 9-1. Nomenclature Description (continued)
FIELD
PARAMETER
FIELD DESCRIPTION
VALUES
SYMBOLIZATION
DESCRIPTION
ORDERABLE
PPP
c
Package designator
Carrier designator
ABC
S-PBGA-N760 (23mm × 23mm) Package
N/A
N/A
BLANK
R
Tray
Tape & Reel
Q1
Automotive Designator
Lot Trace Code
BLANK
Q1
Not meeting automotive qualification
Meeting Q100 equal requirements, with
exceptions as specified in DM.
XXXXXXX
YYY
As marked
As marked
N/A
N/A
Production Code, For TI use
only
ZZZ
Production Code, For TI use
only
As marked
N/A
O
Pin one designator
As marked
As marked
N/A
N/A
G1
ECAT—Green package
designator
(1) To designate the stages in the product development cycle, TI assigns prefixes to the part numbers. These prefixes represent
evolutionary stages of product development from engineering prototypes through fully qualified production devices.
Prototype devices are shipped against the following disclaimer:
“This product is still under development and is intended for internal evaluation purposes.”
Notwithstanding any provision to the contrary, TI makes no warranty expressed, implied, or statutory, including any implied warranty of
merchantability of fitness for a specific purpose, of this device.
(2) Applies to device max junction temperature.
注
BLANK in the symbol or part number is collapsed so there are no gaps between characters.
9.2 Tools and Software
The following products support development for TDA2Ex platforms:
Development Tools
TDA2Ex Clock Tree Tool is interactive clock tree configuration software that allows the user to
visualize the device clock tree, interact with clock tree elements and view the effect on PRCM
registers, interact with the PRCM registers and view the effect on the device clock tree, and view a
trace of all the device registers affected by the user interaction with the clock tree.
TDA2Ex Register Descriptor Tool is an interactive device register configuration tool that allows users
to visualize the register state on power-on reset, and then customize the configuration of the device for
the specific use-case.
TDA2Ex Pad Configuration Tool is an interactive pad-configuration tool that allows the user to
visualize the device pad configuration state on power-on reset and then customize the configuration of
the pads for the specific use-case and identify the device register settings associated to that
configuration.
For a complete listing of development-support tools for the processor platform, visit the Texas Instruments
website at www.ti.com. For information on pricing and availability, contact the nearest TI field sales office
or authorized distributor.
9.3 Documentation Support
The following documents describe the TDA2Ex devices.
TRM
TDA2Ex ADAS Applications ProcessorTechnical Reference Manual Details the
integration, the environment, the functional description, and the programming models for
each peripheral and subsystem in the TDA2Ex family of devices.
Errata
TDA2Ex Silicon Errata Describes known advisories on silicon and provides workarounds.
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9.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates — including silicon errata — go to the product folder for
your device on www.ti.com. In the upper right-hand corner, click the "Alert me" button. This registers you
to receive a weekly digest of product information that has changed (if any). For change details, check the
revision history of any revised document.
9.5 Community Resources
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术
规范，并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI Embedded Processors WikiTexas Instruments Embedded Processors Wiki.
Established to help developers get started with Embedded Processors from Texas
Instruments and to foster innovation and growth of general knowledge about the hardware
and software surrounding these devices.
9.6 商标
Arm, Cortex are registered trademarks of Arm Limited.
HDMI is a trademark of HDMI Licensing, LLC.
PowerVR is a registered trademark of Imagination Technologies Ltd.
MIPI is a registered trademark of Mobile Industry Processor Interface (MIPI) Alliance.
MMC, eMMC are trademarks of MultiMediaCard Association.
带有两个 5Gbps 通道的 PCI Express is a registered trademark of PCI-SIG.
SD is a registered trademark of Toshiba Corporation.
Vivante is a registered trademark of Vivante Corporation.
All other trademarks are the property of their respective owners.
9.7 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
9.8 出口管制提示
接收方同意：如果美国或其他适用法律限制或禁止将通过非披露义务的披露方获得的任何产品或技术数据
（其中包括软件）（见美国、欧盟和其他出口管理条例之定义）、或者其他适用国家条例限制的任何受管制
产品或此项技术的任何直接产品出口或再出口至任何目的地，那么在没有事先获得美国商务部和其他相关政
府机构授权的情况下，接收方不得在知情的情况下，以直接或间接的方式将其出口。
9.9 术语表
TI 术语表
这份术语表列出并解释术语、缩写和定义。
版权 © 2016–2018, Texas Instruments Incorporated
Device and Documentation Support
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产品主页链接: TDA2E
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ZHCSJC6F –MARCH 2016–REVISED JUNE 2018
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10 Mechanical Packaging Information
The following pages include mechanical packaging information. This information is the most current data
available for the designated devices. This data is subject to change without notice and revision of this
document. For browser-based versions of this data sheet, refer to the left-hand navigation.
10.1 Mechanical Data
图 10-1. Mechanical Package
390
Mechanical Packaging Information
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PACKAGE OPTION ADDENDUM
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30-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TDA2EGADQABCQ1
ACTIVE
FCBGA
ABC
760
60
RoHS & Green
Call TI
Level-3-250C-168 HR
-40 to 125
TDA2EGADQABCQ1
JACINTO
Samples
784
784 ABC
TDA2EGAHQABCQ1
TDA2EGAHQABCRQ1
ACTIVE
ACTIVE
FCBGA
FCBGA
ABC
ABC
760
760
60
RoHS & Green
RoHS & Green
Call TI
Call TI
Level-3-250C-168 HR
Level-3-250C-168 HR
-40 to 125
-40 to 125
TDA2EGAHQABCQ1
784
784 ABC
Samples
Samples
250
TDA2EGAHQABCQ1
784
784 ABC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jun-2022
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
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TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
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