TDA3MASBABFRQ1 [TI]

TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0;
TDA3MASBABFRQ1
型号: TDA3MASBABFRQ1
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

TDA3x SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

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TDA3MV, TDA3MA, TDA3MD  
TDA3LX, TDA3LA  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
TDA3x SoC for Advanced Driver Assistance Systems (ADAS)  
15mm Package (ABF) Silicon Revision 2.0  
1 Device Overview  
1.1 Features  
1
• Architecture designed for ADAS applications  
• Video and image processing support  
– Full-HD video (1920 × 1080p, 60 fps)  
– Video input and video output  
• Controller Area Network (DCAN) module  
– CAN 2.0B protocol  
• Modular Controller Area Network (MCAN) module  
– CAN 2.0B protocol  
• Up to 2 C66x floating-point VLIW DSP  
• Eight 32-bit general-purpose timers  
• Three configurable UART modules  
• Four Multichannel Serial Peripheral Interfaces  
(McSPI)  
• Quad SPI interface  
• Two Inter-Integrated Circuit ( I2C™) ports  
– Fully object-code compatible with C67x and  
C64x+  
– Up to thirty-two 16 × 16-bit fixed-point multiplies  
per cycle  
• Up to 512kB of on-chip L3 RAM  
• Level 3 (L3) and Level 4 (L4) interconnects  
• Memory Interface (EMIF) module  
– Supports DDR3/DDR3L up to DDR-1066  
– Supports DDR2 up to DDR-800  
– Supports LPDDR2 up to DDR-667  
– Up to 2GB supported  
• Dual Arm® Cortex®-M4 Image Processor Unit (IPU)  
• Vision accelerationPac  
– Embedded Vision Engine (EVE)  
• Display subsystem  
• Three Multichannel Audio Serial Port (McASP)  
modules  
• Secure Digital Input Output Interface (SDIO)  
• Up to 126 General-Purpose I/O (GPIO) pins  
• Power, reset, and clock management  
• On-chip debug with CTools technology  
• Automotive AEC-Q100 qualified  
• 15 × 15 mm, 0.65-mm pitch, 367-pin PBGA (ABF)  
• Seven Dual Clock Comparators (DCC)  
• Memory Cyclic Redundancy Check (CRC)  
– Display controller with DMA engine  
– CVIDEO / SD-DAC TV analog composite output  
• Video Input Port (VIP) module  
– Support for up to 4 multiplexed input ports  
• On-chip temperature sensor that is capable of  
generating temperature alerts  
• General-Purpose Memory Controller (GPMC)  
• Enhanced Direct Memory Access (EDMA)  
controller  
• TESOC (LBIST/PBIST) that enables field testing of  
logic and on-chip memory  
• Error Signaling Module (ESM)  
• Five instances of Real-Time Interrupt (RTI)  
modules that can be used as watch dog timers  
• 8-channel 10-bit ADC  
• MIPI® Camera Serial Interface 2 (CSI-2)  
• PWMSS  
• Full HW image pipe: DPC, CFA, 3D-NF, RGB-YUV  
– WDR, HW LDC and perspective  
• 3-port (2 external) Gigabit Ethernet (GMAC) switch  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 
 
TDA3MV, TDA3MA, TDA3MD  
TDA3LX, TDA3LA  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
www.ti.com  
1.2 Applications  
Mono, stereo or tri-optic front camera  
LVDS or ethernet surround view  
Object detection  
2D surround view  
3D surround view  
Rear object detection  
Parking assist  
Pedestrian detection  
Traffic sign recognition  
Lane detection and departure warning  
Automatic emergency braking  
Adaptive cruise control  
Forward collision warning  
High beam assist  
Pedestrian detection  
Lane tracking  
Drive recording  
Sensor fusion – vision, radar, ultrasonic, lidar  
sensors  
Object data fusion  
Raw data fusion  
1.3 Description  
TI’s TDA3x System-on-Chip (SoC) is a highly optimized and scalable family of devices designed to meet  
the requirements of leading Advanced Driver Assistance Systems (ADAS). The TDA3x family enables  
broad ADAS applications in automobiles by integrating an optimal mix of performance, low power, smaller  
form factor and ADAS vision analytics processing that aims to facilitate a more autonomous and collision-  
free driving experience.  
The TDA3x SoC enables sophisticated embedded vision technology in today’s automobile by enabling the  
industry’s broadest range of ADAS applications including front camera, rear camera, surround view, radar,  
and fusion on a single architecture.  
The TDA3x SoC incorporates a heterogeneous, scalable architecture that includes a mix of Texas  
Instruments (TI)’s fixed and floating-point TMS320C66x digital signal processor (DSP) generation cores,  
Vision AccelerationPac (EVE), and dual-Cortex-M4 processors. The device allows low power profile in  
different package options (including Package-On-Package) to enable small form factor designs. TDA3x  
SoC also integrates a host of peripherals including multi-camera interfaces (both parallel and serial) for  
LVDS-based surround view systems, displays, CAN and GigB Ethernet AVB.  
The Vision AccelerationPac for this family of products includes embedded vision engine (EVE) offloading  
the vision analytics functionality from the application processor while also reducing the power footprint.  
The Vision AccelerationPac is optimized for vision processing with a 32-bit RISC core for efficient program  
execution and a vector coprocessor for specialized vision processing.  
Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor,  
including C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a  
debugging interface for visibility into source code execution.  
The TDA3x ADAS processor is qualified according to AEC-Q100 standard.  
Device Information  
PART NUMBER  
TDA3LAxABFQ1  
TDA3MVxABFQ1  
TDA3MAxABFQ1  
TDA3MDxABFQ1  
TDA3LXxABFQ1  
PACKAGE  
FCBGA (367)  
FCBGA (367)  
FCBGA (367)  
FCBGA (367)  
FCBGA (367)  
BODY SIZE  
15.0 mm × 15.0 mm  
15.0 mm × 15.0 mm  
15.0 mm × 15.0 mm  
15.0 mm × 15.0 mm  
15.0 mm × 15.0 mm  
2
Device Overview  
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SPRS964H JUNE 2016REVISED FEBRUARY 2020  
1.4 Functional Block Diagram  
Figure 1-1 is functional block diagram of the superset.  
IPU with ECC  
DSP Subsystem x2  
Display  
Subsystem  
Dual Cortex M4  
32KB ROM  
L1P 32KB  
L2  
256KB  
Cache  
C66x  
DVOUT  
Vision  
Accelerator  
L1D 32KB  
EDMA 2TC  
EVE 16MAC  
SD-DAC  
EDMA 2TC  
OSD  
Resizing  
CSC  
Video Front End  
Video Input Port  
up to 512KB RAM  
with ECC  
CAL  
LVDSRX  
CSI2  
ISP  
Interconnect  
TDA3x  
Connectivity  
System  
Safety  
Clock Comparator (7xDCC)  
GMAC  
EDMA  
GPIO x4  
PWMSSx1  
MMUx1  
Timer x8  
JTAG  
PLLs  
OSC  
Mailbox/Spinlock  
10-bit ADC  
Error Handler (ESM)  
TESOC (LBIST/PBIST)  
1x CRC  
Serial Interfaces  
I2C x2  
McASP x3  
Control Module  
SPI x4  
QSPI x1  
SDIO x1  
UART x3  
PRCM  
5x RTI  
DCAN with ECC  
Memory Controllers  
MCAN(CAN-FD)  
with ECC  
LPDDR2 / DDR2/  
DDR3 / DDR3L  
32b with 8b ECC  
GPMC 8b/16b  
with up to 16b ECC  
SPRS916_Intro_001  
Figure 1-1. TDA3x Block Diagram  
Copyright © 2016–2020, Texas Instruments Incorporated  
Device Overview  
3
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SPRS964H JUNE 2016REVISED FEBRUARY 2020  
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Table of Contents  
1
Device Overview ......................................... 1  
1.1 Features ............................................. 1  
1.2 Applications........................................... 2  
1.3 Description............................................ 2  
1.4 Functional Block Diagram ........................... 3  
Revision History ......................................... 5  
Device Comparison ..................................... 6  
3.1 Related Products ..................................... 8  
Terminal Configuration and Functions.............. 9  
4.1 Terminal Assignment ................................. 9  
4.2 Ball Characteristics.................................. 10  
4.3 Multiplexing Characteristics ......................... 40  
4.4 Signal Descriptions.................................. 51  
Specifications .......................................... 75  
5.1 Absolute Maximum Ratings......................... 76  
5.2 ESD Ratings ........................................ 76  
5.3 Power-On Hours (POH)(1)(2)(3) ...................... 77  
5.4 Recommended Operating Conditions............... 77  
5.5 Operating Performance Points ...................... 79  
5.6 Power Consumption Summary...................... 89  
5.7 Electrical Characteristics ............................ 90  
5.8 Thermal Characteristics ............................. 96  
7.8 External Memory Interface (EMIF)................. 127  
7.9  
General-Purpose Memory Controller (GPMC)..... 127  
7.10 General-Purpose Timers........................... 148  
7.11 Inter-Integrated Circuit Interface (I2C)............. 148  
7.12 Universal Asynchronous Receiver Transmitter  
(UART) ............................................. 151  
2
3
7.13 Multichannel Serial Peripheral Interface (McSPI) . 153  
7.14 Quad Serial Peripheral Interface (QSPI) .......... 159  
7.15 Multichannel Audio Serial Port (McASP) .......... 163  
7.16 Controller Area Network Interface (DCAN and  
MCAN) ............................................. 171  
7.17 Ethernet Interface (GMAC_SW) ................... 172  
7.18 SDIO Controller .................................... 176  
7.19 General-Purpose Interface (GPIO) ................ 181  
7.20 Test Interfaces ..................................... 182  
Applications, Implementation, and Layout ...... 185  
8.1 Introduction ........................................ 185  
8.2 Power Optimizations ............................... 186  
8.3 Core Power Domains .............................. 197  
8.4 Single-Ended Interfaces ........................... 206  
8.5 Differential Interfaces .............................. 209  
8.6 Clock Routing Guidelines .......................... 211  
4
5
8
8.7  
8.8  
8.9  
LPDDR2 Board Design and Layout Guidelines.... 212  
DDR2 Board Design and Layout Guidelines....... 221  
DDR3 Board Design and Layout Guidelines....... 233  
5.9  
Analog-to-Digital ADC Subsystem Electrical  
Specifications........................................ 97  
5.10 Power Supply Sequences........................... 99  
Clock Specifications ................................. 105  
6.1 Input Clock Specifications ......................... 106  
6.2 DPLLs, DLLs Specifications ....................... 112  
8.10 CVIDEO/SD-DAC Guidelines and Electrical  
6
7
Data/Timing ........................................ 256  
9
Device and Documentation Support.............. 258  
9.1 Device Nomenclature .............................. 258  
9.2 Tools and Software ................................ 260  
9.3 Documentation Support............................ 262  
9.4 Related Links ...................................... 262  
9.5 Support Resources ................................ 262  
9.6 Trademarks ........................................ 262  
9.7 Electrostatic Discharge Caution ................... 262  
9.8 Glossary............................................ 262  
Timing Requirements and Switching  
Characteristics ........................................ 116  
7.1 Timing Test Conditions ............................ 116  
7.2 Interface Clock Specifications ..................... 116  
7.3 Timing Parameters and Information ............... 116  
7.4  
Recommended Clock and Control Signal Transition  
Behavior............................................ 118  
7.5 Video Input Ports (VIP) ............................ 119  
10 Mechanical, Packaging, and Orderable  
7.6  
Display Subsystem – Video Output Ports ......... 124  
Information............................................. 263  
10.1 Packaging Information ............................. 263  
7.7 Imaging Subsystem (ISS).......................... 126  
4
Table of Contents  
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www.ti.com  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
2 Revision History  
Changes from April 1, 2019 to February 29, 2020 (from G Revision (March 2019) to H Revision)  
Page  
Updated MMC naming in Section 1.1, Features.................................................................................. 1  
Updated clarification notes regarding XTDA3SX part number in Table 3-1, Device Comparison ......................... 7  
Updated Table 5-10, LVCMOS Analog OSC Buffers DC Electrical Characteristics........................................ 94  
Updated Figure 7-36, GMAC MDIO diagrams and MDIO7 parameter values in Table 7-38, Switching  
Characteristics Over Recommended Operating Conditions for MDIO Output............................................. 173  
Updated clarification notes regarding XTDA3SX part number in Table 9-1, Nomenclature Description............... 258  
Updated Device Type section of Table 9-1, Nomenclature Description to include additional GP Prime variants .... 258  
Copyright © 2016–2020, Texas Instruments Incorporated  
Revision History  
5
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TDA3LX, TDA3LA  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
www.ti.com  
3 Device Comparison  
Table 3-1 shows a comparison between devices, highlighting the differences.  
Table 3-1. Device Comparison(2)(5)  
DEVICE  
FEATURES  
TDA3MVx  
TDA3MAx TDA3MDx  
TDA3LXx  
TDA3LAx  
Features  
CTRL_WKUP_STD_FUSE_DIE_ID_2 [31:24]  
Base PN register bit field value(4)(5)  
TDA3MV: 147 (0x93)  
TDA3MA: TDA3MD:  
149 (0x95) 157 (0x9D)  
TDA3LX: 154 (0x9A)  
TDA3LA:  
151 (0x97)  
TDA3MV-FD: 148  
(0x94)  
TDA3LX–FD: 150  
(0x96)  
Processors/ Accelerators  
Speed Grades  
R, S  
D, R, S  
D, R, S  
Yes  
Yes  
No  
D, S  
Yes  
Yes  
No  
D, R, S  
B, D, R, S B, D, R, S  
C66x VLIW DSP  
DSP1  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
No  
DSP2  
No  
Display Subsystem  
VOUT1  
SD_DAC  
Yes  
Yes  
Yes  
Yes  
No  
No  
No  
No  
Embedded Vision Engine (EVE) EVE1  
Yes  
Yes  
No  
Yes  
Yes  
Dual Arm Cortex-M4 Image  
Processing Unit (IPU)  
IPU1  
Yes  
Imaging Subsystem Processor  
(ISS) with MIPI CSI-2 and CPI  
ports  
ISP  
Yes  
Yes  
No  
No  
No  
No  
Yes  
Yes  
No  
No  
WDR & Mesh  
LDC(1)  
CAL_A  
CAL_B  
LVDS-RX  
CPI  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Video Input VIP1  
Port (VIP)  
vin1a  
vin1b  
vin2a  
vin2b  
Program/Data Storage  
On-Chip Shared Memory (RAM) OCMC_RAM  
1
512kB  
Yes  
512kB  
Yes  
512kB  
Yes  
256kB  
Yes  
256kB  
Yes  
General-Purpose Memory  
Controller (GPMC)  
GPMC  
LPDDR2/DDR2/DDR3/DDR3L  
Memory Controller  
EMIF1  
(optional with  
SECDED)  
up to 2GB  
up to 2GB up to 2GB  
up to 2GB  
up to 2GB  
Peripherals  
Controller Area Network  
Interface (CAN)  
DCAN1  
Yes  
Yes  
Yes  
Yes  
Yes  
MCAN  
Yes(3)  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes(3)  
Yes  
Yes  
Yes  
Yes  
Enhanced DMA (EDMA)  
Embedded 8 channel ADC  
EDMA  
Yes  
Yes  
Yes  
Yes  
ADC  
Ethernet Subsystem (Ethernet  
SS)  
GMAC_SW[0]  
RGMII Only  
RGMII  
Only  
RGMII  
Only  
RGMII Only  
RGMII  
Only  
GMAC_SW[1]  
RGMII Only  
RGMII  
Only  
RGMII  
Only  
RGMII Only  
RGMII  
Only  
General-Purpose IO (GPIO)  
GPIO  
Up to 126  
2
Up to 126 Up to 126  
Up to 126  
2
Up to 126  
2
Inter-Integrated Circuit Interface I2C  
(I2C)  
2
2
System Mailbox Module  
MAILBOX  
2
2
2
2
2
6
Device Comparison  
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SPRS964H JUNE 2016REVISED FEBRUARY 2020  
Table 3-1. Device Comparison(2)(5) (continued)  
DEVICE  
FEATURES  
TDA3MVx  
TDA3MAx TDA3MDx  
TDA3LXx  
TDA3LAx  
Multichannel Audio Serial Port  
(McASP)  
McASP1  
McASP2  
McASP3  
MMC  
16 serializers  
16  
16  
16 serializers  
16  
serializers serializers  
serializers  
6 serializers  
6 serializers  
1x SDIO 4b  
6
6
6 serializers  
6 serializers  
1x SDIO 4b  
6
serializers serializers  
serializers  
6
6
6
serializers serializers  
serializers  
MultiMedia Card/Secure  
Digital/Secure Digital Input  
Output Interface  
1x SDIO  
4b  
1x SDIO  
4b  
1x SDIO  
4b  
(MMC/SD/SDIO)  
Multichannel Serial Peripheral  
Interface (McSPI)  
McSPI  
4
4
4
4
4
Quad SPI (QSPI)  
QSPI  
Yes  
Yes  
8
Yes  
Yes  
8
Yes  
Yes  
8
Yes  
Yes  
8
Yes  
Yes  
8
Spinlock Module  
SPINLOCK  
TIMER  
Timers, General-Purpose  
Dual Clock Comparators (DCC) DCC  
7
7
7
7
7
Pulse-Width Modulation  
Subsystem (PWMSS)  
PWMSS1  
Yes  
Yes  
Yes  
Yes  
Yes  
Universal Asynchronous  
Receiver/Transmitter (UART)  
UART  
CRC  
3
3
3
3
3
Memory Cyclic Redundancy  
Check (CRC)  
Yes  
Yes  
Yes  
Yes  
Yes  
TESOC (LBIST/PBIST)  
LBIST/PBIST  
ESM  
Yes  
Yes  
5
Yes  
Yes  
5
Yes  
Yes  
5
Yes  
Yes  
5
Yes  
Yes  
5
Error Signaling Module (ESM)  
Real Time Interrupt (RTI)  
RTI  
(1) Wide Dynamic Range and Lens Distortion Correction.  
(2) Listed devices are a sample of devices available in TDA3x family. The device name decoder can provide the details of individual part  
number.  
(3) Device supports FD (Flexible Data Rate) as an optional feature if the part number is designated with the “F” option.  
(4) For more details about the CTRL_WKUP_STD_FUSE_DIE_ID_2 register and Base PN bit field, see the device TRM.  
(5) XTDA3SX base part number with X speed grade indicator is the part number for the superset device. Software should constrain the  
features and speed used to match the intended production device. The Base PN register bit field value is 0x98.  
Copyright © 2016–2020, Texas Instruments Incorporated  
Device Comparison  
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3.1 Related Products  
Companion Products for TDA3 Review products that are frequently purchased or used in conjunction with  
this product.  
Reference Designs for TDA3 TI Designs Reference Design Library is a robust reference design library  
spanning analog, embedded processor and connectivity. Created by TI experts to help you jump-start your  
system design, all TI Designs include schematic or block diagrams, BOMs and design files to speed your  
time to market. Search and download designs at ti.com/tidesigns.  
8
Device Comparison  
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SPRS964H JUNE 2016REVISED FEBRUARY 2020  
4 Terminal Configuration and Functions  
4.1 Terminal Assignment  
Figure 4-1 shows the ball locations for the 367 plastic ball grid array (PBGA) package and are used in  
conjunction with Table 4-2 through Table 4-29 to locate signal names and ball grid numbers.  
AB  
AA  
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19 21  
10 12 18  
22  
6
8
2
4
14 16  
20  
SPRS916_BALL_01  
Figure 4-1. ABF FCBGA-N367 Package (Bottom View)  
NOTE  
The following bottom balls are not connected: C4 / C7 / C9 / C11 / C13 / C15 / C19 / D4 / D5  
/ D9 / D11 / D13 / D17 / D18 / D19 / D20 / E4 / E5 / E6 / E9 / E11 / E13 / E15 / E18 / E19 /  
F5 / F9 / F11 / F18 / G13 / G15 / G17 / G20 / H3 / H4 / H5 / H6 / J8 / J9 / J12 / J13 / J14 /  
J18 / J19 / J20 / K3 / K4 / K5 / K6 / L9 / L10 / L11 / L13 / L14 / L17 / L18 / L19 / L20 / M3 /  
M4 / M5 / M6 / N9 / N11 / N13 / N14 / N17 / N18 / N19 / N20 / P3 / P4 / P5 / P6 / R8 / R10 /  
R11 / R13 / R14 / R15 / R17 / R18 / R19 / R20 / T3 / T6 / U5 / U10 / U12 / U14 / U18 / V4 /  
V5 / V6 / V8 / V10 / V12 / V14 / V17 / V18 / V19 / W3 / W4 / W5 / W10 / W12 / W14 / W18 /  
W19 / W20 / Y4 / Y7 / Y10 / Y12 / Y14 / Y16 / Y19.  
These balls do not exist on the package.  
4.1.1 Unused Balls Connection Requirements  
This section describes the Unused/Reserved balls connection requirements.  
NOTE  
The following balls are reserved: A2 / F6 / A21 / B1  
These balls must be left unconnected.  
NOTE  
All unused power supply balls must be supplied with the voltages specified in the  
Section 5.4, Recommended Operating Conditions, unless alternative tie-off options are  
included in Section 4.4, Signal Descriptions.  
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Terminal Configuration and Functions  
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Table 4-1. Unused Balls Specific Connection Requirements  
BALLS  
CONNECTION REQUIREMENTS  
These balls must be connected to GND through an external pull  
resistor if unused  
B21 / E22 / J5 / AA10 / AA5 / AA20 / W1 / T21  
These balls must be connected to the corresponding power supply  
through an external pull resistor if unused  
J2 / G5 / G4 / L3 / L4 / AB10 / J3 / AB5 / Y20 / W2 / T22 / L6 / L5  
M19 / M20 / M21 / M22 / N22 / N21 / P19 / P18 / P20  
These balls must be connected together to GND through a single  
external 10kΩ resistor if unused.  
NOTE  
All other unused signal balls with a Pad Configuration Register can be left unconnected with  
their internal pullup or pulldown resistor enabled.  
NOTE  
All other unused signal balls without a Pad Configuration Register can be left unconnected.  
4.2 Ball Characteristics  
Table 4-2 describes the terminal characteristics and the signals multiplexed on each ball. The following list  
describes the table column headers:  
1. BALL NUMBER: Ball number(s) on the bottom side associated with each signal on the bottom.  
2. BALL NAME: Mechanical name from package device (name is taken from muxmode 0).  
3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the  
signal name in muxmode 0).  
NOTE  
Table 4-2 does not take into account the subsystem multiplexing signals. Subsystem  
multiplexing signals are described in Section 4.4, Signal Descriptions.  
NOTE  
In the Driver off mode, the buffer is configured in high-impedance.  
4. MA/LX/LA: This column shows if the functionality is applicable for TDA3MAx, TDA3LXx, TDA3LAx  
devices. Note that the ball characteristics table presents the functionality of TDA3MVx device. If the  
cell is empty it means that the signal is available in all devices.  
MA – TDA3MAx, TDA3MDx  
LX – TDA3LXx  
LA – TDA3LAx  
5. MUXMODE: Multiplexing mode number:  
a. MUXMODE 0 is the primary mode; this means that when MUXMODE=0 is set, the function  
mapped on the pin corresponds to the name of the pin. The primary muxmode is not necessarily  
the default muxmode.  
NOTE  
The default mode is the mode at the release of the reset; also see the RESET REL.  
MUXMODE column.  
b. MUXMODE 1 through 15 are possible muxmodes for alternate functions. On each pin, some  
10  
Terminal Configuration and Functions  
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muxmodes are effectively used for alternate functions, while some muxmodes are not used. Only  
MUXMODE values which correspond to defined functions should be used.  
c. An empty box means Not Applicable.  
6. TYPE: Signal type and direction:  
I = Input  
O = Output  
IO = Input or Output  
D = Open drain  
DS = Differential Signaling  
A = Analog  
PWR = Power  
GND = Ground  
CAP = LDO Capacitor  
7. BALL RESET STATE: The state of the terminal at power-on reset:  
drive 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated).  
drive 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated).  
OFF: High-impedance  
PD: High-impedance with an active pulldown resistor  
PU: High-impedance with an active pullup resistor  
An empty box means Not Applicable  
8. BALL RESET REL. STATE: The state of the terminal at the deactivation of the rstoutn signal (also  
mapped to the PRCM SYS_WARM_OUT_RST signal).  
drive 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated).  
drive clk (OFF): The buffer drives a toggling clock (pulldown or pullup resistor not activated).  
drive 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated).  
OFF: High-impedance  
PD: High-impedance with an active pulldown resistor  
PU: High-impedance with an active pullup resistor  
An empty box means Not Applicable  
NOTE  
For more information on the CORE_PWRON_RET_RST reset signal and its reset sources,  
see the Reset Management Functional Description section in the device TRM.  
9. BALL RESET REL. MUXMODE: This muxmode is automatically configured at the release of the  
rstoutn signal (also mapped to the PRCM SYS_WARM_OUT_RST signal).  
An empty box means Not Applicable.  
10. IO VOLTAGE VALUE: This column describes the IO voltage value (VDDS supply).  
An empty box means Not Applicable.  
11. POWER: The voltage supply that powers the terminal IO buffers.  
An empty box means Not Applicable.  
12. HYS: Indicates if the input buffer is with hysteresis:  
Yes: With hysteresis  
No: Without hysteresis  
An empty box: Not Applicable  
NOTE  
For more information, see the hysteresis values in Section 5.7, DC Electrical Characteristics.  
13. BUFFER TYPE: Drive strength of the associated output buffer.  
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An empty box means Not Applicable.  
NOTE  
For programmable buffer strength:  
The default value is given in Table 4-2.  
A note describes all possible values according to the selected muxmode.  
14. PULL UP / DOWN TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and  
pulldown resistors can be enabled or disabled via software.  
PU: Internal pullup  
PD: Internal pulldown  
PU/PD: Internal pullup and pulldown  
PUx/PDy: Programmable internal pullup and pulldown  
PDy: Programmable internal pulldown  
An empty box means No pull  
15. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0" or  
logic "1") when the peripheral pin function is not selected by any of the CTRL_CORE_PADx registers.  
0: Logic 0 driven on the peripheral's input signal port.  
1: Logic 1 driven on the peripheral's input signal port.  
blank: Pin state driven on the peripheral's input signal port.  
NOTE  
Configuring two pins to the same input signal is not supported as it can yield unexpected  
results. This can be easily prevented with the proper software configuration (Hi-Z mode is not  
an input signal).  
NOTE  
When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that  
pad’s behavior is undefined. This should be avoided.  
12  
Terminal Configuration and Functions  
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Table 4-2. Ball Characteristics(1)  
BALL  
RESET  
REL.  
MUXMODE VALUE [10]  
[9]  
BALL  
RESET  
REL.  
BALL  
RESET  
STATE [7]  
I/O  
VOLTAGE  
PULL  
MA/LX/LA MUXMODE  
POWER  
[11]  
BUFFER  
TYPE [13]  
BALL NUMBER [1]  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [6]  
HYS [12]  
UP/DOWN DSIS [15]  
TYPE [14]  
[4]  
[5]  
STATE [8]  
M19  
M20  
M21  
M22  
N22  
N21  
P19  
P18  
P20  
N15  
M15  
M14  
A11  
adc_in0  
adc_in1  
adc_in2  
adc_in3  
adc_in4  
adc_in5  
adc_in6  
adc_in7  
adc_in0  
adc_in1  
adc_in2  
adc_in3  
adc_in4  
adc_in5  
adc_in6  
adc_in7  
adc_vrefp  
0
0
0
0
0
0
0
0
0
A
A
A
A
A
A
A
A
A
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
0
0
0
0
0
0
0
0
0
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
vdda_adc  
vdda_adc  
vdda_adc  
vdda_adc  
vdda_adc  
vdda_adc  
vdda_adc  
vdda_adc  
vdda_adc  
GPADC  
GPADC  
GPADC  
GPADC  
GPADC  
GPADC  
GPADC  
GPADC  
GPADC  
adc_vrefp  
cap_vddram_core1  
cap_vddram_core2  
cap_vddram_dspeve  
csi2_0_dx0  
cap_vddram_core1  
cap_vddram_core2  
cap_vddram_dspeve  
csi2_0_dx0  
CAP  
CAP  
CAP  
I
0
0
0
0
0
0
0
0
0
0
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
0
0
0
0
0
0
0
0
0
0
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
vdda_csi  
vdda_csi  
vdda_csi  
vdda_csi  
vdda_csi  
vdda_csi  
vdda_csi  
vdda_csi  
vdda_csi  
vdda_csi  
Yes  
LVCMOS  
CSI2  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
A12  
A13  
A15  
A16  
B11  
B12  
B13  
B15  
B16  
csi2_0_dx1  
csi2_0_dx2  
csi2_0_dx3  
csi2_0_dx4  
csi2_0_dy0  
csi2_0_dy1  
csi2_0_dy2  
csi2_0_dy3  
csi2_0_dy4  
csi2_0_dx1  
csi2_0_dx2  
csi2_0_dx3  
csi2_0_dx4  
csi2_0_dy0  
csi2_0_dy1  
csi2_0_dy2  
csi2_0_dy3  
csi2_0_dy4  
I
I
I
I
I
I
I
I
I
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
LVCMOS  
CSI2  
LVCMOS  
CSI2  
LVCMOS  
CSI2  
LVCMOS  
CSI2  
LVCMOS  
CSI2  
LVCMOS  
CSI2  
LVCMOS  
CSI2  
LVCMOS  
CSI2  
LVCMOS  
CSI2  
T18  
T17  
P17  
N6  
cvideo_rset  
cvideo_tvout  
cvideo_vfb  
dcan1_rx  
cvideo_rset  
cvideo_tvout  
cvideo_vfb  
dcan1_rx  
N / Y / N  
N / Y / N  
N / Y / N  
0
A
A
A
IO  
IO  
I
OFF  
OFF  
OFF  
PU  
OFF  
OFF  
OFF  
PU  
0
1.8  
vdda_dac  
vdda_dac  
vdda_dac  
vddshv1  
AVDAC  
AVDAC  
AVDAC  
0
0
1.8  
0
0
1.8  
0
15  
1.8/3.3  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
gpio4_10  
14  
15  
Driver off  
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Table 4-2. Ball Characteristics(1) (continued)  
BALL  
RESET  
REL.  
MUXMODE VALUE [10]  
[9]  
BALL  
RESET  
REL.  
BALL  
RESET  
STATE [7]  
I/O  
VOLTAGE  
PULL  
MA/LX/LA MUXMODE  
[4] [5]  
POWER  
[11]  
BUFFER  
TYPE [13]  
BALL NUMBER [1]  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [6]  
HYS [12]  
UP/DOWN DSIS [15]  
TYPE [14]  
STATE [8]  
N5  
dcan1_tx  
dcan1_tx  
gpio4_9  
0
IO  
PU  
PU  
15  
1.8/3.3  
vddshv1  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
14  
15  
0
IO  
I
Driver off  
ddr1_casn  
F2  
ddr1_casn  
ddr1_ck  
O
PD  
PD  
PD  
PU  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
drive 1  
(OFF)  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1.2/1.35/1.5 vdds_ddr2  
/1.8  
LVCMOS  
DDR  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
G1  
AB13  
AB10  
AA10  
G2  
F1  
ddr1_ck  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
O
IO  
IO  
IO  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
drive clk  
(OFF)  
1.2/1.35/1.5 vdds_ddr2  
/1.8  
LVCMOS  
DDR  
ddr1_dqm_ecc  
ddr1_dqsn_ecc  
ddr1_dqs_ecc  
ddr1_nck  
ddr1_rasn  
ddr1_rst  
ddr1_dqm_ecc  
ddr1_dqsn_ecc  
ddr1_dqs_ecc  
ddr1_nck  
ddr1_rasn  
ddr1_rst  
PD  
PU  
PD  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
drive clk  
(OFF)  
1.2/1.35/1.5 vdds_ddr2  
/1.8  
LVCMOS  
DDR  
drive 1  
(OFF)  
1.2/1.35/1.5 vdds_ddr2  
/1.8  
LVCMOS  
DDR  
N1  
drive 0  
(OFF)  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
E3  
ddr1_wen  
ddr1_a0  
ddr1_wen  
ddr1_a0  
drive 1  
(OFF)  
1.2/1.35/1.5 vdds_ddr2  
/1.8  
LVCMOS  
DDR  
U4  
drive 1  
(OFF)  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
C1  
ddr1_a1  
ddr1_a1  
drive 1  
(OFF)  
1.2/1.35/1.5 vdds_ddr2  
/1.8  
LVCMOS  
DDR  
D3  
ddr1_a2  
ddr1_a2  
drive 1  
(OFF)  
1.2/1.35/1.5 vdds_ddr2  
/1.8  
LVCMOS  
DDR  
R4  
ddr1_a3  
ddr1_a3  
drive 1  
(OFF)  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
T4  
ddr1_a4  
ddr1_a4  
drive 1  
(OFF)  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
N3  
ddr1_a5  
ddr1_a5  
drive 1  
(OFF)  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
T2  
ddr1_a6  
ddr1_a6  
drive 1  
(OFF)  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
N2  
ddr1_a7  
ddr1_a7  
drive 1  
(OFF)  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
T1  
ddr1_a8  
ddr1_a8  
drive 1  
(OFF)  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
U1  
ddr1_a9  
ddr1_a9  
drive 1  
(OFF)  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
D1  
ddr1_a10  
ddr1_a11  
ddr1_a10  
ddr1_a11  
drive 1  
(OFF)  
1.2/1.35/1.5 vdds_ddr2  
/1.8  
LVCMOS  
DDR  
R3  
drive 1  
(OFF)  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
14  
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SPRS964H JUNE 2016REVISED FEBRUARY 2020  
Table 4-2. Ball Characteristics(1) (continued)  
BALL  
RESET  
REL.  
MUXMODE VALUE [10]  
[9]  
BALL  
RESET  
REL.  
BALL  
RESET  
STATE [7]  
I/O  
VOLTAGE  
PULL  
MA/LX/LA MUXMODE  
[4] [5]  
POWER  
[11]  
BUFFER  
TYPE [13]  
BALL NUMBER [1]  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [6]  
HYS [12]  
UP/DOWN DSIS [15]  
TYPE [14]  
STATE [8]  
U2  
ddr1_a12  
ddr1_a12  
ddr1_a13  
ddr1_a14  
ddr1_a15  
ddr1_ba0  
ddr1_ba1  
ddr1_ba2  
ddr1_cke0  
ddr1_csn0  
ddr1_d0  
ddr1_d1  
ddr1_d2  
ddr1_d3  
ddr1_d4  
ddr1_d5  
ddr1_d6  
ddr1_d7  
ddr1_d8  
ddr1_d9  
ddr1_d10  
ddr1_d11  
ddr1_d12  
ddr1_d13  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
O
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
drive 1  
(OFF)  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
C3  
ddr1_a13  
ddr1_a14  
ddr1_a15  
ddr1_ba0  
ddr1_ba1  
ddr1_ba2  
ddr1_cke0  
ddr1_csn0  
ddr1_d0  
ddr1_d1  
ddr1_d2  
ddr1_d3  
ddr1_d4  
ddr1_d5  
ddr1_d6  
ddr1_d7  
ddr1_d8  
ddr1_d9  
ddr1_d10  
ddr1_d11  
ddr1_d12  
ddr1_d13  
O
drive 1  
(OFF)  
1.2/1.35/1.5 vdds_ddr2  
/1.8  
LVCMOS  
DDR  
R2  
O
drive 1  
(OFF)  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
V1  
O
drive 1  
(OFF)  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
B3  
O
drive 1  
(OFF)  
1.2/1.35/1.5 vdds_ddr2  
/1.8  
LVCMOS  
DDR  
A3  
O
drive 1  
(OFF)  
1.2/1.35/1.5 vdds_ddr2  
/1.8  
LVCMOS  
DDR  
D2  
O
drive 1  
(OFF)  
1.2/1.35/1.5 vdds_ddr2  
/1.8  
LVCMOS  
DDR  
F3  
O
drive 0  
(OFF)  
1.2/1.35/1.5 vdds_ddr2  
/1.8  
LVCMOS  
DDR  
B2  
O
drive 1  
(OFF)  
1.2/1.35/1.5 vdds_ddr2  
/1.8  
LVCMOS  
DDR  
AA6  
AA8  
Y8  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
AA7  
AB4  
Y5  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
AA4  
Y6  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
AA18  
Y21  
AA21  
Y22  
AA19  
AB20  
1.2/1.35/1.5 vdds_ddr3  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr3  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr3  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr3  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr3  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr3  
/1.8  
LVCMOS  
DDR  
Copyright © 2016–2020, Texas Instruments Incorporated  
Terminal Configuration and Functions  
15  
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TDA3MV, TDA3MA, TDA3MD  
TDA3LX, TDA3LA  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
www.ti.com  
Table 4-2. Ball Characteristics(1) (continued)  
BALL  
RESET  
REL.  
MUXMODE VALUE [10]  
[9]  
BALL  
RESET  
REL.  
BALL  
RESET  
STATE [7]  
I/O  
VOLTAGE  
PULL  
MA/LX/LA MUXMODE  
[4] [5]  
POWER  
[11]  
BUFFER  
TYPE [13]  
BALL NUMBER [1]  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [6]  
HYS [12]  
UP/DOWN DSIS [15]  
TYPE [14]  
STATE [8]  
Y17  
AB18  
AA3  
AA2  
Y3  
ddr1_d14  
ddr1_d14  
ddr1_d15  
ddr1_d16  
ddr1_d17  
ddr1_d18  
ddr1_d19  
ddr1_d20  
ddr1_d21  
ddr1_d22  
ddr1_d23  
ddr1_d24  
ddr1_d25  
ddr1_d26  
ddr1_d27  
ddr1_d28  
ddr1_d29  
ddr1_d30  
ddr1_d31  
ddr1_dqm0  
ddr1_dqm1  
ddr1_dqm2  
ddr1_dqm3  
ddr1_dqs0  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1.2/1.35/1.5 vdds_ddr3  
/1.8  
LVCMOS  
DDR  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
ddr1_d15  
ddr1_d16  
ddr1_d17  
ddr1_d18  
ddr1_d19  
ddr1_d20  
ddr1_d21  
ddr1_d22  
ddr1_d23  
ddr1_d24  
ddr1_d25  
ddr1_d26  
ddr1_d27  
ddr1_d28  
ddr1_d29  
ddr1_d30  
ddr1_d31  
ddr1_dqm0  
ddr1_dqm1  
ddr1_dqm2  
ddr1_dqm3  
ddr1_dqs0  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
1.2/1.35/1.5 vdds_ddr3  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
V2  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
U3  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
V3  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
Y2  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
Y1  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
U21  
T20  
R21  
U20  
R22  
V20  
W22  
U22  
AB8  
Y18  
AB3  
W21  
AA5  
1.2/1.35/1.5 vdds_ddr3  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr3  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr3  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr3  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr3  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr3  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr3  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr3  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr3  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr3  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
16  
Terminal Configuration and Functions  
Copyright © 2016–2020, Texas Instruments Incorporated  
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TDA3MV, TDA3MA, TDA3MD  
TDA3LX, TDA3LA  
www.ti.com  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
Table 4-2. Ball Characteristics(1) (continued)  
BALL  
RESET  
REL.  
MUXMODE VALUE [10]  
[9]  
BALL  
RESET  
REL.  
BALL  
RESET  
STATE [7]  
I/O  
VOLTAGE  
PULL  
MA/LX/LA MUXMODE  
[4] [5]  
POWER  
[11]  
BUFFER  
TYPE [13]  
BALL NUMBER [1]  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [6]  
HYS [12]  
UP/DOWN DSIS [15]  
TYPE [14]  
STATE [8]  
AA20  
W1  
ddr1_dqs1  
ddr1_dqs1  
ddr1_dqs2  
ddr1_dqs3  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO  
PD  
PD  
PD  
PU  
PU  
PU  
PU  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PU  
PD  
PD  
PD  
PU  
PU  
PU  
PU  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1.2/1.35/1.5 vdds_ddr3  
/1.8  
LVCMOS  
DDR  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PUx/PDy  
PU/PD  
ddr1_dqs2  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
O
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
T21  
AB5  
Y20  
W2  
ddr1_dqs3  
1.2/1.35/1.5 vdds_ddr3  
/1.8  
LVCMOS  
DDR  
ddr1_dqsn0  
ddr1_dqsn1  
ddr1_dqsn2  
ddr1_dqsn3  
ddr1_ecc_d0  
ddr1_ecc_d1  
ddr1_ecc_d2  
ddr1_ecc_d3  
ddr1_ecc_d4  
ddr1_ecc_d5  
ddr1_ecc_d6  
ddr1_ecc_d7  
ddr1_odt0  
ddr1_dqsn0  
ddr1_dqsn1  
ddr1_dqsn2  
ddr1_dqsn3  
ddr1_ecc_d0  
ddr1_ecc_d1  
ddr1_ecc_d2  
ddr1_ecc_d3  
ddr1_ecc_d4  
ddr1_ecc_d5  
ddr1_ecc_d6  
ddr1_ecc_d7  
ddr1_odt0  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr3  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
T22  
Y11  
AA12  
AA11  
Y9  
1.2/1.35/1.5 vdds_ddr3  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
AA13  
AB11  
AA9  
AB9  
P2  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
drive 0  
(OFF)  
1.2/1.35/1.5 vdds_ddr1  
/1.8  
LVCMOS  
DDR  
H1  
emu0  
emu0  
0
IO  
IO  
I
PU  
1.8/3.3  
1.8/3.3  
1.8/3.3  
vddshv1  
vddshv1  
vddshv2  
Yes  
Dual  
Voltage  
LVCMOS  
gpio4_28  
Driver off  
emu1  
14  
15  
0
H2  
E8  
emu1  
IO  
IO  
I
PU  
PU  
0
Yes  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
gpio4_29  
Driver off  
gpmc_ad0  
rgmii1_rxd2  
gpio1_14  
sysboot0  
14  
15  
0
gpmc_ad0  
IO  
I
OFF  
OFF  
15  
Dual  
Voltage  
LVCMOS  
PU/PD  
0
0
1
14  
15  
IO  
I
Copyright © 2016–2020, Texas Instruments Incorporated  
Terminal Configuration and Functions  
17  
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Product Folder Links: TDA3MV TDA3MA TDA3MD TDA3LX TDA3LA  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
TDA3MV, TDA3MA, TDA3MD  
TDA3LX, TDA3LA  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
www.ti.com  
Table 4-2. Ball Characteristics(1) (continued)  
BALL  
RESET  
REL.  
MUXMODE VALUE [10]  
[9]  
BALL  
RESET  
REL.  
BALL  
RESET  
STATE [7]  
I/O  
VOLTAGE  
PULL  
MA/LX/LA MUXMODE  
POWER  
[11]  
BUFFER  
TYPE [13]  
BALL NUMBER [1]  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [6]  
HYS [12]  
UP/DOWN DSIS [15]  
TYPE [14]  
[4]  
[5]  
STATE [8]  
A7  
gpmc_ad1  
gpmc_ad1  
0
IO  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
15  
15  
15  
15  
15  
1.8/3.3  
1.8/3.3  
1.8/3.3  
1.8/3.3  
1.8/3.3  
vddshv2  
vddshv2  
vddshv2  
vddshv2  
vddshv2  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
0
0
rgmii1_rxd1  
gpio1_15  
sysboot1  
gpmc_ad2  
rgmii1_rxd0  
gpio1_16  
sysboot2  
gpmc_ad3  
qspi1_rtclk  
gpio1_17  
sysboot3  
gpmc_ad4  
cam_strobe  
gpio1_18  
sysboot4  
gpmc_ad5  
uart2_txd  
timer6  
1
I
14  
15  
0
IO  
I
F8  
B7  
A6  
F7  
gpmc_ad2  
gpmc_ad3  
gpmc_ad4  
gpmc_ad5  
IO  
I
Yes  
Yes  
Yes  
Yes  
Dual  
Voltage  
LVCMOS  
0
0
1
14  
15  
0
IO  
I
IO  
I
Dual  
Voltage  
LVCMOS  
0
0
1
14  
15  
0
IO  
I
IO  
O
IO  
I
Dual  
Voltage  
LVCMOS  
0
N / Y / N  
1
14  
15  
0
IO  
O
IO  
IO  
IO  
I
Dual  
Voltage  
LVCMOS  
0
0
2
3
spi3_d1  
4
gpio1_19  
14  
15  
sysboot5  
mcasp2_aclkx  
E7  
gpmc_ad6  
gpmc_ad6  
uart2_rxd  
timer5  
0
IO  
I
OFF  
OFF  
15  
1.8/3.3  
vddshv2  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
0
1
2
3
IO  
IO  
IO  
I
spi3_d0  
4
0
gpio1_20  
14  
15  
sysboot6  
mcasp2_fsx  
C6  
gpmc_ad7  
gpmc_ad7  
cam_shutter  
timer4  
0
IO  
O
OFF  
OFF  
0
1.8/3.3  
vddshv2  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
0
0
N / Y / N  
1
3
IO  
IO  
IO  
I
spi3_sclk  
gpio1_21  
4
14  
15  
Driver off  
mcasp2_ahclkx  
18  
Terminal Configuration and Functions  
Copyright © 2016–2020, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Links: TDA3MV TDA3MA TDA3MD TDA3LX TDA3LA  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
TDA3MV, TDA3MA, TDA3MD  
TDA3LX, TDA3LA  
www.ti.com  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
Table 4-2. Ball Characteristics(1) (continued)  
BALL  
RESET  
REL.  
MUXMODE VALUE [10]  
[9]  
BALL  
RESET  
REL.  
BALL  
RESET  
STATE [7]  
I/O  
VOLTAGE  
PULL  
MA/LX/LA MUXMODE  
[4] [5]  
POWER  
[11]  
BUFFER  
TYPE [13]  
BALL NUMBER [1]  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [6]  
HYS [12]  
UP/DOWN DSIS [15]  
TYPE [14]  
STATE [8]  
B6  
gpmc_ad8  
gpmc_ad8  
timer7  
0
IO  
OFF  
OFF  
15  
1.8/3.3  
vddshv2  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
0
1
3
IO  
IO  
IO  
I
spi3_cs0  
gpio1_22  
sysboot8  
4
14  
15  
mcasp2_aclkr  
A5  
gpmc_ad9  
gpmc_ad9  
0
IO  
IO  
IO  
IO  
I
OFF  
OFF  
15  
1.8/3.3  
vddshv2  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
0
0
1
eCAP1_in_PWM1_out  
spi3_cs1  
3
4
gpio1_23  
14  
15  
sysboot9  
mcasp2_fsr  
D6  
C5  
gpmc_ad10  
gpmc_ad11  
gpmc_ad10  
timer2  
0
IO  
IO  
IO  
I
OFF  
OFF  
OFF  
OFF  
15  
15  
1.8/3.3  
1.8/3.3  
vddshv2  
vddshv2  
Yes  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
PU/PD  
0
0
0
3
gpio1_24  
14  
15  
sysboot10  
mcasp2_axr0  
gpmc_ad11  
timer3  
0
IO  
IO  
IO  
I
Dual  
Voltage  
LVCMOS  
3
gpio1_25  
14  
15  
sysboot11  
mcasp2_axr1  
B5  
D7  
gpmc_ad12  
gpmc_ad13  
gpmc_ad12  
gpio1_26  
0
IO  
IO  
I
OFF  
OFF  
OFF  
OFF  
15  
15  
1.8/3.3  
1.8/3.3  
vddshv2  
vddshv2  
Yes  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
PU/PD  
14  
15  
sysboot12  
mcasp2_axr2  
gpmc_ad13  
rgmii1_rxc  
gpio1_27  
0
IO  
I
Dual  
Voltage  
LVCMOS  
0
0
1
14  
15  
IO  
I
sysboot13  
mcasp2_axr3  
B4  
gpmc_ad14  
gpmc_ad14  
spi2_cs1  
0
IO  
IO  
IO  
I
OFF  
OFF  
15  
1.8/3.3  
vddshv2  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
0
1
4
gpio1_28  
14  
15  
sysboot14  
mcasp2_axr4  
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19  
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TDA3MV, TDA3MA, TDA3MD  
TDA3LX, TDA3LA  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
www.ti.com  
Table 4-2. Ball Characteristics(1) (continued)  
BALL  
RESET  
REL.  
MUXMODE VALUE [10]  
[9]  
BALL  
RESET  
REL.  
BALL  
RESET  
STATE [7]  
I/O  
VOLTAGE  
PULL  
MA/LX/LA MUXMODE  
[4] [5]  
POWER  
[11]  
BUFFER  
TYPE [13]  
BALL NUMBER [1]  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [6]  
HYS [12]  
UP/DOWN DSIS [15]  
TYPE [14]  
STATE [8]  
A4  
gpmc_ad15  
gpmc_ad15  
0
IO  
OFF  
OFF  
15  
1.8/3.3  
vddshv2  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
0
1
spi2_cs0  
gpio1_29  
4
IO  
IO  
I
14  
15  
sysboot15  
mcasp2_axr5  
F12  
gpmc_advn_ale  
gpmc_advn_ale  
rgmii1_txd2  
ehrpwm1_tripzone_input  
clkout1  
0
O
O
IO  
O
I
PD  
PD  
0
1.8/3.3  
vddshv2  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
1
4
0
5
dma_evt4  
gpio1_3  
6
14  
15  
0
IO  
I
Driver off  
D12  
E12  
C12  
C10  
gpmc_ben0  
gpmc_ben1  
gpmc_clk  
gpmc_ben0  
rgmii1_txctl  
ehrpwm1A  
dma_evt2  
gpio1_1  
O
O
O
I
PD  
PD  
PD  
PU  
PD  
PD  
PD  
PU  
0
1.8/3.3  
1.8/3.3  
1.8/3.3  
1.8/3.3  
vddshv2  
vddshv2  
vddshv2  
vddshv2  
Yes  
Yes  
Yes  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
1
4
6
14  
15  
0
IO  
I
Driver off  
gpmc_ben1  
rgmii1_txd3  
ehrpwm1B  
dma_evt3  
gpio1_2  
O
O
O
I
15  
Dual  
Voltage  
LVCMOS  
1
4
6
14  
15  
0
IO  
I
Driver off  
gpmc_clk  
rgmii1_txc  
clkout0  
IO  
O
O
I
0
Dual  
Voltage  
LVCMOS  
0
1
5
dma_evt1  
gpio1_0  
6
14  
15  
0
IO  
I
Driver off  
gpmc_cs0  
gpmc_cs0  
rgmii1_rxctl  
gpio1_6  
O
I
0
Dual  
Voltage  
LVCMOS  
1
0
14  
15  
IO  
I
Driver off  
20  
Terminal Configuration and Functions  
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TDA3MV, TDA3MA, TDA3MD  
TDA3LX, TDA3LA  
www.ti.com  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
Table 4-2. Ball Characteristics(1) (continued)  
BALL  
RESET  
REL.  
MUXMODE VALUE [10]  
[9]  
BALL  
RESET  
REL.  
BALL  
RESET  
STATE [7]  
I/O  
VOLTAGE  
PULL  
MA/LX/LA MUXMODE  
[4] [5]  
POWER  
[11]  
BUFFER  
TYPE [13]  
BALL NUMBER [1]  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [6]  
HYS [12]  
UP/DOWN DSIS [15]  
TYPE [14]  
STATE [8]  
E10  
gpmc_cs1  
gpmc_cs1  
qspi1_cs0  
gpio1_7  
0
O
PU  
PU  
PU  
PU  
PU  
PU  
PD  
PU  
PU  
PU  
PU  
PU  
PU  
PD  
15  
15  
15  
15  
15  
15  
0
1.8/3.3  
1.8/3.3  
1.8/3.3  
1.8/3.3  
1.8/3.3  
1.8/3.3  
1.8/3.3  
vddshv2  
vddshv2  
vddshv2  
vddshv2  
vddshv2  
vddshv2  
vddshv2  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
1
1
IO  
IO  
I
14  
15  
0
Driver off  
gpmc_cs2  
qspi1_d3  
gpio1_8  
D10  
A9  
gpmc_cs2  
gpmc_cs3  
gpmc_cs4  
gpmc_cs5  
gpmc_cs6  
gpmc_oen_ren  
O
IO  
IO  
I
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
0
1
14  
15  
0
Driver off  
gpmc_cs3  
qspi1_d2  
gpio1_9  
O
IO  
IO  
I
Dual  
Voltage  
LVCMOS  
PU/PD  
0
1
14  
15  
0
Driver off  
gpmc_cs4  
qspi1_d0  
gpio1_10  
Driver off  
gpmc_cs5  
qspi1_d1  
gpio1_11  
Driver off  
gpmc_cs6  
qspi1_sclk  
gpio1_12  
Driver off  
B9  
O
IO  
IO  
I
Dual  
Voltage  
LVCMOS  
PU/PD  
0
1
14  
15  
0
F10  
C8  
O
IO  
IO  
I
Dual  
Voltage  
LVCMOS  
PU/PD  
0
1
14  
15  
0
O
O
IO  
I
Dual  
Voltage  
LVCMOS  
PU/PD  
1
14  
15  
0
A10  
gpmc_oen_ren  
rgmii1_txd1  
ehrpwm1_synci  
clkout2  
O
O
I
Dual  
Voltage  
LVCMOS  
PU/PD  
1
4
0
5
O
IO  
I
gpio1_4  
14  
15  
0
Driver off  
D8  
gpmc_wait0  
gpmc_wait0  
rgmii1_rxd3  
qspi1_rtclk  
dma_evt4  
gpio1_13  
I
PU  
PU  
0
1.8/3.3  
vddshv2  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
1
0
0
1
I
2
I
6
I
14  
15  
IO  
I
Driver off  
Copyright © 2016–2020, Texas Instruments Incorporated  
Terminal Configuration and Functions  
21  
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TDA3MV, TDA3MA, TDA3MD  
TDA3LX, TDA3LA  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
www.ti.com  
Table 4-2. Ball Characteristics(1) (continued)  
BALL  
RESET  
REL.  
MUXMODE VALUE [10]  
[9]  
BALL  
RESET  
REL.  
BALL  
RESET  
STATE [7]  
I/O  
VOLTAGE  
PULL  
MA/LX/LA MUXMODE  
POWER  
[11]  
BUFFER  
TYPE [13]  
BALL NUMBER [1]  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [6]  
HYS [12]  
UP/DOWN DSIS [15]  
TYPE [14]  
[4]  
[5]  
STATE [8]  
B10  
gpmc_wen  
gpmc_wen  
rgmii1_txd0  
0
O
PD  
PD  
0
1.8/3.3  
vddshv2  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
1
O
O
IO  
I
ehrpwm1_synco  
gpio1_5  
4
14  
15  
0
Driver off  
L3  
L4  
L6  
L5  
W6  
i2c1_scl  
i2c1_sda  
i2c2_scl  
i2c2_sda  
mcan_rx  
i2c1_scl  
IO  
OFF  
OFF  
OFF  
OFF  
PU  
OFF  
OFF  
OFF  
OFF  
PU  
0
1.8/3.3  
1.8/3.3  
1.8/3.3  
1.8/3.3  
1.8/3.3  
vddshv1  
vddshv1  
vddshv1  
vddshv1  
vddshv6  
Yes  
Yes  
Yes  
Yes  
Yes  
Dual  
PU  
PU  
PU  
PU  
Voltage  
LVCMOS  
I2C  
i2c1_sda  
i2c2_scl  
i2c2_sda  
0
0
0
IO  
IO  
IO  
0
Dual  
Voltage  
LVCMOS  
I2C  
0
Dual  
Voltage  
LVCMOS  
I2C  
0
Dual  
Voltage  
LVCMOS  
I2C  
mcan_rx  
0
IO  
IO  
I
15  
Dual  
Voltage  
LVCMOS  
PU/PD  
1
1
0
1
cam_nreset  
vin2a_vsync0  
spi1_cs3  
N / Y / N  
1
2
3
IO  
O
O
I
uart3_txd  
4
gpmc_cs7  
vin1b_vsync1  
gpio4_12  
5
7
14  
15  
0
IO  
I
Driver off  
W7  
mcan_tx  
mcan_tx  
IO  
I
PU  
PU  
15  
1.8/3.3  
vddshv6  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
vin2a_de0  
vin2a_hsync0  
spi1_cs2  
1
2
I
3
IO  
I
1
1
1
0
0
uart3_rxd  
4
gpmc_wait1  
vin1b_hsync1  
vin1b_de1  
gpio4_11  
6
I
7
I
8
I
14  
15  
IO  
I
Driver off  
22  
Terminal Configuration and Functions  
Copyright © 2016–2020, Texas Instruments Incorporated  
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Product Folder Links: TDA3MV TDA3MA TDA3MD TDA3LX TDA3LA  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
TDA3MV, TDA3MA, TDA3MD  
TDA3LX, TDA3LA  
www.ti.com  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
Table 4-2. Ball Characteristics(1) (continued)  
BALL  
RESET  
REL.  
MUXMODE VALUE [10]  
[9]  
BALL  
RESET  
REL.  
BALL  
RESET  
STATE [7]  
I/O  
VOLTAGE  
PULL  
MA/LX/LA MUXMODE  
POWER  
[11]  
BUFFER  
TYPE [13]  
BALL NUMBER [1]  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [6]  
HYS [12]  
UP/DOWN DSIS [15]  
TYPE [14]  
[4]  
[5]  
STATE [8]  
B17  
mdio_d  
mdio_d  
0
IO  
PU  
PU  
15  
1.8/3.3  
vddshv4  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
1
0
0
spi4_d0  
esm_error  
gpio3_18  
Driver off  
mdio_mclk  
spi4_d1  
gpio3_17  
Driver off  
nmin  
4
IO  
IO  
IO  
I
5
14  
15  
0
B19  
G5  
mdio_mclk  
O
IO  
IO  
I
PU  
PU  
PU  
PU  
15  
1.8/3.3  
1.8/3.3  
vddshv4  
vddshv1  
Yes  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
PU/PD  
1
0
4
14  
15  
0
nmin  
I
0
Dual  
1
Voltage  
LVCMOS  
G3  
G4  
porz  
porz  
0
0
I
I
OFF  
PU  
OFF  
PU  
0
0
1.8/3.3  
1.8/3.3  
vddshv1  
vddshv1  
Yes  
Yes  
IHHV1833 PU/PD  
resetn  
resetn  
Dual  
PU/PD  
Voltage  
LVCMOS  
B18  
C18  
C16  
rgmii0_rxc  
rgmii0_rxctl  
rgmii0_txc  
rgmii0_rxc  
0
I
PD  
PD  
PD  
PD  
PD  
PD  
15  
15  
15  
1.8/3.3  
1.8/3.3  
1.8/3.3  
vddshv4  
vddshv4  
vddshv4  
Yes  
Yes  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
0
1
cam_strobe  
mmc_clk  
N / Y / N  
N / Y / N  
N / Y / N  
3
O
IO  
IO  
I
5
gpio3_25  
Driver off  
rgmii0_rxctl  
cam_shutter  
mmc_cmd  
gpio3_26  
Driver off  
rgmii0_txc  
cam_strobe  
spi4_sclk  
mmc_clk  
14  
15  
0
I
Dual  
Voltage  
LVCMOS  
PU/PD  
PU/PD  
0
1
3
O
IO  
IO  
I
5
14  
15  
0
O
O
IO  
IO  
IO  
I
Dual  
Voltage  
LVCMOS  
3
4
0
1
5
gpio3_19  
Driver off  
rgmii0_txctl  
cam_shutter  
spi4_cs0  
14  
15  
0
C17  
rgmii0_txctl  
O
O
IO  
IO  
IO  
I
PD  
PD  
15  
1.8/3.3  
vddshv4  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
N / Y / N  
3
4
1
1
mmc_cmd  
gpio3_20  
Driver off  
5
14  
15  
Copyright © 2016–2020, Texas Instruments Incorporated  
Terminal Configuration and Functions  
23  
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TDA3MV, TDA3MA, TDA3MD  
TDA3LX, TDA3LA  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
www.ti.com  
Table 4-2. Ball Characteristics(1) (continued)  
BALL  
RESET  
REL.  
MUXMODE VALUE [10]  
[9]  
BALL  
RESET  
REL.  
BALL  
RESET  
STATE [7]  
I/O  
VOLTAGE  
PULL  
MA/LX/LA MUXMODE  
[4] [5]  
POWER  
[11]  
BUFFER  
TYPE [13]  
BALL NUMBER [1]  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [6]  
HYS [12]  
UP/DOWN DSIS [15]  
TYPE [14]  
STATE [8]  
A20  
rgmii0_rxd0  
rgmii0_rxd0  
0
I
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
15  
15  
15  
15  
15  
15  
15  
1.8/3.3  
1.8/3.3  
1.8/3.3  
1.8/3.3  
1.8/3.3  
1.8/3.3  
1.8/3.3  
vddshv4  
vddshv4  
vddshv4  
vddshv4  
vddshv4  
vddshv4  
vddshv4  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
0
1
mmc_dat3  
gpio3_30  
5
IO  
IO  
I
14  
15  
0
Driver off  
C20  
B20  
A19  
F17  
E17  
D16  
rgmii0_rxd1  
rgmii0_rxd2  
rgmii0_rxd3  
rgmii0_txd0  
rgmii0_txd1  
rgmii0_txd2  
rgmii0_rxd1  
mmc_dat2  
gpio3_29  
I
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Dual  
Voltage  
LVCMOS  
0
1
5
IO  
IO  
I
14  
15  
0
Driver off  
rgmii0_rxd2  
mmc_dat1  
gpio3_28  
I
Dual  
Voltage  
LVCMOS  
0
1
5
IO  
IO  
I
14  
15  
0
Driver off  
rgmii0_rxd3  
mmc_dat0  
gpio3_27  
I
Dual  
Voltage  
LVCMOS  
0
1
5
IO  
IO  
I
14  
15  
0
Driver off  
rgmii0_txd0  
mmc_dat3  
gpio3_24  
O
IO  
IO  
I
Dual  
Voltage  
LVCMOS  
5
1
1
14  
15  
0
Driver off  
rgmii0_txd1  
mmc_dat2  
gpio3_23  
O
IO  
IO  
I
Dual  
Voltage  
LVCMOS  
5
14  
15  
0
Driver off  
rgmii0_txd2  
eCAP1_in_PWM1_out  
mmc_dat1  
gpio3_22  
O
IO  
IO  
IO  
I
Dual  
Voltage  
LVCMOS  
3
0
1
5
14  
15  
0
Driver off  
E16  
F4  
rgmii0_txd3  
rstoutn  
rgmii0_txd3  
mmc_dat0  
gpio3_21  
O
IO  
IO  
I
PD  
PD  
PD  
15  
1.8/3.3  
1.8/3.3  
vddshv4  
vddshv1  
Yes  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
PU/PD  
5
1
14  
15  
0
Driver off  
rstoutn  
O
drive 1  
(OFF)  
0
Dual  
Voltage  
LVCMOS  
24  
Terminal Configuration and Functions  
Copyright © 2016–2020, Texas Instruments Incorporated  
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Product Folder Links: TDA3MV TDA3MA TDA3MD TDA3LX TDA3LA  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
TDA3MV, TDA3MA, TDA3MD  
TDA3LX, TDA3LA  
www.ti.com  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
Table 4-2. Ball Characteristics(1) (continued)  
BALL  
RESET  
REL.  
MUXMODE VALUE [10]  
[9]  
BALL  
RESET  
REL.  
BALL  
RESET  
STATE [7]  
I/O  
VOLTAGE  
PULL  
MA/LX/LA MUXMODE  
[4] [5]  
POWER  
[11]  
BUFFER  
TYPE [13]  
BALL NUMBER [1]  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [6]  
HYS [12]  
UP/DOWN DSIS [15]  
TYPE [14]  
STATE [8]  
J6  
rtck  
rtck  
0
O
PU  
PD  
drive clk  
(OFF)  
0
1.8/3.3  
1.8/3.3  
vddshv1  
vddshv1  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
gpio4_27  
Driver off  
spi1_sclk  
uart3_rxd  
gpio4_0  
Driver off  
spi2_sclk  
uart3_rxd  
ehrpwm1A  
timer3  
14  
15  
0
IO  
I
M2  
L1  
spi1_sclk  
spi2_sclk  
IO  
I
PD  
PD  
15  
Yes  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
PU/PD  
0
1
1
14  
15  
0
IO  
I
IO  
I
PD  
15  
1.8/3.3  
vddshv1  
Dual  
Voltage  
LVCMOS  
0
1
1
2
O
IO  
IO  
I
3
gpio4_5  
Driver off  
spi1_cs0  
uart3_txd  
gpio4_3  
Driver off  
spi1_cs1  
spi3_cs1  
timer6  
14  
15  
0
R6  
R5  
spi1_cs0  
spi1_cs1  
IO  
O
IO  
I
PU  
PU  
PU  
PU  
15  
15  
1.8/3.3  
1.8/3.3  
vddshv1  
vddshv1  
Yes  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
PU/PD  
1
1
14  
15  
0
IO  
IO  
IO  
IO  
IO  
I
Dual  
Voltage  
LVCMOS  
1
1
1
4
ehrpwm1_tripzone_input  
gpio4_4  
7
0
0
14  
15  
0
Driver off  
spi1_d0  
T5  
U6  
L2  
spi1_d0  
spi1_d1  
spi2_cs0  
IO  
O
IO  
I
OFF  
OFF  
PU  
OFF  
OFF  
PU  
15  
15  
15  
1.8/3.3  
1.8/3.3  
1.8/3.3  
vddshv1  
vddshv1  
vddshv1  
Yes  
Yes  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
uart3_rtsn  
gpio4_2  
1
14  
15  
0
Driver off  
spi1_d1  
IO  
I
Dual  
Voltage  
LVCMOS  
0
1
uart3_ctsn  
gpio4_1  
1
14  
15  
0
IO  
I
Driver off  
spi2_cs0  
uart3_txd  
ehrpwm1B  
timer4  
IO  
O
O
IO  
IO  
I
Dual  
Voltage  
LVCMOS  
1
1
2
3
gpio4_8  
14  
15  
Driver off  
Copyright © 2016–2020, Texas Instruments Incorporated  
Terminal Configuration and Functions  
25  
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TDA3MV, TDA3MA, TDA3MD  
TDA3LX, TDA3LA  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
www.ti.com  
Table 4-2. Ball Characteristics(1) (continued)  
BALL  
RESET  
REL.  
MUXMODE VALUE [10]  
[9]  
BALL  
RESET  
REL.  
BALL  
RESET  
STATE [7]  
I/O  
VOLTAGE  
PULL  
MA/LX/LA MUXMODE  
[4] [5]  
POWER  
[11]  
BUFFER  
TYPE [13]  
BALL NUMBER [1]  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [6]  
HYS [12]  
UP/DOWN DSIS [15]  
TYPE [14]  
STATE [8]  
R7  
spi2_d0  
spi2_d1  
spi2_d0  
uart3_rtsn  
timer1  
0
IO  
OFF  
OFF  
15  
1.8/3.3  
vddshv1  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
0
1
O
IO  
IO  
I
3
gpio4_7  
sysboot7  
spi2_d1  
uart3_ctsn  
timer5  
14  
15  
0
N4  
IO  
I
OFF  
OFF  
15  
1.8/3.3  
vddshv1  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
0
1
1
3
IO  
IO  
IO  
I
eCAP1_in_PWM1_out  
7
0
gpio4_6  
Driver off  
tclk  
14  
15  
0
J2  
J1  
tclk  
tdi  
I
PU  
PU  
PU  
PU  
0
0
1.8/3.3  
1.8/3.3  
vddshv1  
vddshv1  
Yes  
Yes  
IQ1833  
PU/PD  
PU/PD  
tdi  
0
I
Dual  
Voltage  
LVCMOS  
gpio4_25  
Driver off  
tdo  
14  
15  
0
IO  
I
J4  
tdo  
O
IO  
I
PU  
PU  
0
1.8/3.3  
vddshv1  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
gpio4_26  
Driver off  
tms  
14  
15  
0
J3  
tms  
IO  
OFF  
PD  
OFF  
PD  
0
1.8/3.3  
1.8/3.3  
1.8/3.3  
vddshv1  
vddshv1  
vddshv3  
Yes  
Yes  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
J5  
trstn  
trstn  
0
I
0
Dual  
Voltage  
LVCMOS  
F14  
uart1_ctsn  
uart1_ctsn  
xref_clk1  
uart3_rxd  
gpmc_a16  
spi4_sclk  
spi1_cs2  
0
I
PU  
PU  
15  
Dual  
Voltage  
LVCMOS  
1
1
1
I
2
I
3
O
IO  
IO  
IO  
I
4
0
1
5
timer3  
6
ehrpwm1_synci  
clkout0  
7
0
8
O
I
vin2a_hsync0  
gpmc_a12  
gpmc_clk  
dcan1_tx  
gpio4_15  
Driver off  
9
10  
11  
12  
14  
15  
O
IO  
IO  
IO  
I
0
26  
Terminal Configuration and Functions  
Copyright © 2016–2020, Texas Instruments Incorporated  
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TDA3MV, TDA3MA, TDA3MD  
TDA3LX, TDA3LA  
www.ti.com  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
Table 4-2. Ball Characteristics(1) (continued)  
BALL  
RESET  
REL.  
MUXMODE VALUE [10]  
[9]  
BALL  
RESET  
REL.  
BALL  
RESET  
STATE [7]  
I/O  
VOLTAGE  
PULL  
MA/LX/LA MUXMODE  
[4] [5]  
POWER  
[11]  
BUFFER  
TYPE [13]  
BALL NUMBER [1]  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [6]  
HYS [12]  
UP/DOWN DSIS [15]  
TYPE [14]  
STATE [8]  
C14  
uart1_rtsn  
uart1_rtsn  
uart3_txd  
gpmc_a17  
spi4_cs0  
spi1_cs3  
timer4  
0
O
PU  
PU  
15  
1.8/3.3  
vddshv3  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
2
O
O
IO  
IO  
IO  
O
I
3
4
1
1
5
6
ehrpwm1_synco  
qspi1_rtclk  
vin2a_vsync0  
gpmc_a13  
dcan1_rx  
gpio4_16  
Driver off  
uart1_rxd  
spi4_d1  
7
8
0
9
I
10  
12  
14  
15  
0
O
IO  
IO  
I
F13  
uart1_rxd  
I
PU  
PU  
15  
1.8/3.3  
vddshv3  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
1
0
0
4
IO  
I
qspi1_rtclk  
gpmc_a12  
mcan_tx  
5
10  
12  
14  
15  
0
O
IO  
IO  
I
1
gpio4_13  
Driver off  
uart1_txd  
spi4_d0  
E14  
uart1_txd  
O
IO  
O
IO  
IO  
I
PU  
PU  
15  
1.8/3.3  
vddshv3  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
4
0
1
gpmc_a13  
mcan_rx  
10  
12  
14  
15  
0
gpio4_14  
Driver off  
uart2_ctsn  
xref_clk1  
gpmc_a18  
spi3_sclk  
qspi1_cs1  
timer7  
F15  
uart2_ctsn  
I
OFF  
OFF  
15  
1.8/3.3  
vddshv3  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
1
2
I
3
O
IO  
IO  
IO  
I
4
0
1
5
6
vin2a_hsync0  
gpmc_clk  
mcan_tx  
9
10  
12  
14  
15  
IO  
IO  
IO  
I
0
1
gpio4_19  
Driver off  
Copyright © 2016–2020, Texas Instruments Incorporated  
Terminal Configuration and Functions  
27  
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TDA3MV, TDA3MA, TDA3MD  
TDA3LX, TDA3LA  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
www.ti.com  
Table 4-2. Ball Characteristics(1) (continued)  
BALL  
RESET  
REL.  
MUXMODE VALUE [10]  
[9]  
BALL  
RESET  
REL.  
BALL  
RESET  
STATE [7]  
I/O  
VOLTAGE  
PULL  
MA/LX/LA MUXMODE  
[4] [5]  
POWER  
[11]  
BUFFER  
TYPE [13]  
BALL NUMBER [1]  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [6]  
HYS [12]  
UP/DOWN DSIS [15]  
TYPE [14]  
STATE [8]  
F16  
uart2_rtsn  
uart2_rtsn  
0
O
PU  
PU  
PU  
PU  
PU  
PU  
15  
15  
15  
1.8/3.3  
1.8/3.3  
1.8/3.3  
vddshv3  
vddshv3  
vddshv3  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
0
eCAP1_in_PWM1_out  
gpmc_a19  
spi3_cs0  
timer8  
1
IO  
O
3
4
IO  
IO  
I
1
1
6
vin2a_vsync0  
mcan_rx  
9
12  
14  
15  
0
IO  
IO  
I
gpio4_20  
Driver off  
uart2_rxd  
spi3_d1  
D14  
uart2_rxd  
I
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
1
0
4
IO  
IO  
O
timer1  
6
ehrpwm1A  
gpmc_clk  
gpmc_a12  
dcan1_tx  
gpio4_17  
Driver off  
uart2_txd  
spi3_d0  
7
10  
11  
12  
14  
15  
0
IO  
O
0
IO  
IO  
I
D15  
uart2_txd  
O
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
4
IO  
IO  
O
0
timer2  
6
ehrpwm1B  
gpmc_a13  
dcan1_rx  
gpio4_18  
Driver off  
vdd  
7
11  
12  
14  
15  
O
IO  
IO  
I
H12, H13, H7, J10, vdd  
J11, J15, K12, L12,  
L15, N12, N16,  
PWR  
P10, P14  
P22  
A14  
U19  
N8  
vdda_adc  
vdda_adc  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
vdda_csi  
vdda_csi  
vdda_dac  
vdda_dac  
vdda_ddr_dsp  
vdda_gmac_core  
vdda_osc  
vdda_ddr_dsp  
vdda_gmac_core  
vdda_osc  
M8  
E21  
H14  
vdda_per  
vdda_per  
G12, J7, L16, P13, vdds18v  
T11  
vdds18v  
28  
Terminal Configuration and Functions  
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TDA3MV, TDA3MA, TDA3MD  
TDA3LX, TDA3LA  
www.ti.com  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
Table 4-2. Ball Characteristics(1) (continued)  
BALL  
RESET  
REL.  
MUXMODE VALUE [10]  
[9]  
BALL  
RESET  
REL.  
BALL  
RESET  
STATE [7]  
I/O  
VOLTAGE  
PULL  
MA/LX/LA MUXMODE  
[4] [5]  
POWER  
[11]  
BUFFER  
TYPE [13]  
BALL NUMBER [1]  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [6]  
HYS [12]  
UP/DOWN DSIS [15]  
TYPE [14]  
STATE [8]  
P7, T9  
vdds18v_ddr1  
vdds18v_ddr1  
PWR  
G7  
vdds18v_ddr2  
vdds18v_ddr3  
vddshv1  
vdds18v_ddr2  
vdds18v_ddr3  
vddshv1  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
T16, V21  
K2, K7, L7, M7  
B8, G11, G8, G9  
G14  
vddshv2  
vddshv2  
vddshv3  
vddshv3  
A18, E20  
H17, J16, J21  
vddshv4  
vddshv4  
vddshv5  
vddshv5  
AA16, T10, T12,  
T13  
vddshv6  
vddshv6  
AA1, AB6, R1, T7, vdds_ddr1  
T8  
vdds_ddr1  
PWR  
C2, E2, G6  
vdds_ddr2  
vdds_ddr3  
vdd_dspeve  
vdds_ddr2  
vdds_ddr3  
vdd_dspeve  
PWR  
PWR  
PWR  
AA22, AB19, T15  
K8, L8, M9, P11,  
P12, P8, P9  
F22  
vin1a_clk0  
vin1a_clk0  
cpi_pclk  
clkout0  
0
I
PD  
PD  
15  
1.8/3.3  
vddshv5  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
0
0
1
I
4
O
IO  
I
gpio1_30  
14  
15  
Driver off  
mcasp3_aclkx  
G18  
G21  
G22  
vin1a_d0  
vin1a_d1  
vin1a_d2  
vin1a_d0  
cpi_data2  
gpio2_3  
0
I
PD  
PD  
PD  
PD  
PD  
PD  
15  
15  
15  
1.8/3.3  
1.8/3.3  
1.8/3.3  
vddshv5  
vddshv5  
vddshv5  
Yes  
Yes  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
0
0
1
I
14  
15  
IO  
I
Driver off  
mcasp3_axr1  
vin1a_d1  
cpi_data3  
gpio2_4  
0
I
Dual  
Voltage  
LVCMOS  
0
0
1
I
14  
15  
IO  
I
Driver off  
mcasp3_axr2  
vin1a_d2  
cpi_data4  
gpio2_5  
0
I
Dual  
Voltage  
LVCMOS  
0
0
1
I
14  
15  
IO  
I
Driver off  
mcasp3_axr3  
Copyright © 2016–2020, Texas Instruments Incorporated  
Terminal Configuration and Functions  
29  
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TDA3MV, TDA3MA, TDA3MD  
TDA3LX, TDA3LA  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
www.ti.com  
Table 4-2. Ball Characteristics(1) (continued)  
BALL  
RESET  
REL.  
MUXMODE VALUE [10]  
[9]  
BALL  
RESET  
REL.  
BALL  
RESET  
STATE [7]  
I/O  
VOLTAGE  
PULL  
MA/LX/LA MUXMODE  
[4] [5]  
POWER  
[11]  
BUFFER  
TYPE [13]  
BALL NUMBER [1]  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [6]  
HYS [12]  
UP/DOWN DSIS [15]  
TYPE [14]  
STATE [8]  
H18  
vin1a_d3  
vin1a_d3  
cpi_data5  
gpio2_6  
0
I
I
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
15  
15  
15  
15  
1.8/3.3  
1.8/3.3  
1.8/3.3  
1.8/3.3  
vddshv5  
vddshv5  
vddshv5  
vddshv5  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
0
0
1
14  
15  
IO  
I
Driver off  
mcasp3_axr4  
H20  
H19  
H22  
vin1a_d4  
vin1a_d5  
vin1a_d6  
vin1a_d4  
0
I
Yes  
Yes  
Yes  
Dual  
Voltage  
LVCMOS  
0
0
cpi_data6  
gpio2_7  
1
I
14  
15  
IO  
I
Driver off  
mcasp3_axr5  
vin1a_d5  
cpi_data7  
gpio2_8  
0
I
Dual  
Voltage  
LVCMOS  
0
0
1
I
14  
15  
IO  
I
xref_clk2  
mcasp3_ahclkx  
vin1a_d6  
cpi_data8  
gpio2_9  
0
I
Dual  
Voltage  
LVCMOS  
0
0
1
I
14  
15  
IO  
I
Driver off  
mcasp3_fsx  
H21  
J17  
vin1a_d7  
vin1a_d8  
vin1a_d7  
cpi_data9  
gpio2_10  
Driver off  
vin1a_d8  
cpi_data10  
vin1b_d0  
gpmc_a8  
sys_nirq2  
gpio2_11  
Driver off  
vin1a_d9  
cpi_data11  
vin1b_d1  
gpmc_a9  
sys_nirq1  
gpio2_12  
Driver off  
0
I
PD  
PD  
PD  
PD  
15  
15  
1.8/3.3  
1.8/3.3  
vddshv5  
vddshv5  
Yes  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
PU/PD  
0
0
1
I
14  
15  
0
IO  
I
I
Dual  
Voltage  
LVCMOS  
0
0
0
1
I
2
I
3
O
I
7
14  
15  
0
IO  
I
K22  
vin1a_d9  
I
PD  
PD  
15  
1.8/3.3  
vddshv5  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
0
0
0
1
I
2
I
3
O
I
7
14  
15  
IO  
I
30  
Terminal Configuration and Functions  
Copyright © 2016–2020, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Links: TDA3MV TDA3MA TDA3MD TDA3LX TDA3LA  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
TDA3MV, TDA3MA, TDA3MD  
TDA3LX, TDA3LA  
www.ti.com  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
Table 4-2. Ball Characteristics(1) (continued)  
BALL  
RESET  
REL.  
MUXMODE VALUE [10]  
[9]  
BALL  
RESET  
REL.  
BALL  
RESET  
STATE [7]  
I/O  
VOLTAGE  
PULL  
MA/LX/LA MUXMODE  
[4] [5]  
POWER  
[11]  
BUFFER  
TYPE [13]  
BALL NUMBER [1]  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [6]  
HYS [12]  
UP/DOWN DSIS [15]  
TYPE [14]  
STATE [8]  
K21  
vin1a_d10  
vin1a_d10  
cpi_data12  
vin1b_d2  
gpmc_a10  
sys_nirq2  
gpio2_13  
Driver off  
vin1a_d11  
cpi_data13  
vin1b_d3  
gpmc_a11  
sys_nirq1  
gpio2_14  
Driver off  
vin1a_d12  
cpi_data14  
vin1b_d4  
gpmc_a12  
dma_evt1  
gpio2_15  
Driver off  
vin1a_d13  
cpi_wen  
0
I
I
I
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
15  
15  
15  
15  
15  
1.8/3.3  
1.8/3.3  
1.8/3.3  
1.8/3.3  
1.8/3.3  
vddshv5  
vddshv5  
vddshv5  
vddshv5  
vddshv5  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
0
0
0
1
2
3
O
I
7
14  
15  
0
IO  
I
K18  
K17  
K19  
K20  
vin1a_d11  
vin1a_d12  
vin1a_d13  
vin1a_d14  
I
Yes  
Yes  
Yes  
Yes  
Dual  
Voltage  
LVCMOS  
0
0
0
1
I
2
I
3
O
I
7
14  
15  
0
IO  
I
I
Dual  
Voltage  
LVCMOS  
0
0
0
1
I
2
I
3
O
I
6
14  
15  
0
IO  
I
I
Dual  
Voltage  
LVCMOS  
0
0
0
1
I
vin1b_d5  
gpmc_a13  
dma_evt2  
gpio2_16  
Driver off  
vin1a_d14  
cpi_fid  
2
I
3
O
I
6
14  
15  
0
IO  
I
I
Dual  
Voltage  
LVCMOS  
0
0
0
1
IO  
I
vin1b_d6  
gpmc_a14  
gpio2_17  
Driver off  
2
3
O
IO  
I
14  
15  
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Terminal Configuration and Functions  
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TDA3LX, TDA3LA  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
www.ti.com  
Table 4-2. Ball Characteristics(1) (continued)  
BALL  
RESET  
REL.  
MUXMODE VALUE [10]  
[9]  
BALL  
RESET  
REL.  
BALL  
RESET  
STATE [7]  
I/O  
VOLTAGE  
PULL  
MA/LX/LA MUXMODE  
[4] [5]  
POWER  
[11]  
BUFFER  
TYPE [13]  
BALL NUMBER [1]  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [6]  
HYS [12]  
UP/DOWN DSIS [15]  
TYPE [14]  
STATE [8]  
L21  
vin1a_d15  
vin1a_d15  
cpi_data15  
vin1b_d7  
gpmc_a15  
gpio2_18  
Driver off  
vin1a_de0  
cpi_hsync  
vin1b_clk1  
clkout1  
0
I
I
I
PD  
PD  
PD  
PD  
PD  
PD  
15  
15  
15  
1.8/3.3  
1.8/3.3  
1.8/3.3  
vddshv5  
vddshv5  
vddshv5  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
0
0
0
1
2
3
O
IO  
I
14  
15  
0
F21  
vin1a_de0  
I
Yes  
Dual  
Voltage  
LVCMOS  
0
0
0
1
IO  
I
2
4
O
IO  
I
gpio1_31  
Driver off  
vin1a_fld0  
cpi_vsync  
vin2b_clk1  
clkout2  
14  
15  
0
F20  
vin1a_fld0  
I
Yes  
Dual  
Voltage  
LVCMOS  
0
0
0
1
IO  
I
2
4
O
IO  
I
gpio2_0  
14  
15  
Driver off  
mcasp3_aclkr  
vin1a_hsync0  
cpi_data0  
F19  
vin1a_hsync0  
0
I
PD  
PD  
15  
1.8/3.3  
vddshv5  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
0
0
0
1
I
vin1a_de0  
gpio2_1  
2
I
14  
15  
IO  
I
Driver off  
mcasp3_fsr  
G19  
L22  
vin1a_vsync0  
vin2a_clk0  
vin1a_vsync0  
cpi_data1  
gpio2_2  
0
I
PD  
PD  
PD  
PD  
15  
15  
1.8/3.3  
1.8/3.3  
vddshv5  
vddshv5  
Yes  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
PU/PD  
0
0
1
I
14  
15  
IO  
I
Driver off  
mcasp3_axr0  
vin2a_clk0  
gpio2_19  
Driver off  
0
I
Dual  
Voltage  
LVCMOS  
14  
15  
IO  
I
32  
Terminal Configuration and Functions  
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TDA3MV, TDA3MA, TDA3MD  
TDA3LX, TDA3LA  
www.ti.com  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
Table 4-2. Ball Characteristics(1) (continued)  
BALL  
RESET  
REL.  
MUXMODE VALUE [10]  
[9]  
BALL  
RESET  
REL.  
BALL  
RESET  
STATE [7]  
I/O  
VOLTAGE  
PULL  
MA/LX/LA MUXMODE  
POWER  
[11]  
BUFFER  
TYPE [13]  
BALL NUMBER [1]  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [6]  
HYS [12]  
UP/DOWN DSIS [15]  
TYPE [14]  
[4]  
[5]  
STATE [8]  
M17  
vin2a_de0  
vin2a_de0  
0
I
PD  
PD  
15  
1.8/3.3  
vddshv5  
Yes  
Dual  
PU/PD  
Voltage  
LVCMOS  
cam_strobe  
vin2b_hsync1  
vin2b_de1  
gpio4_21  
N / Y / N  
1
O
I
2
0
0
5
I
14  
15  
0
IO  
I
Driver off  
M18  
vin2a_fld0  
vout1_clk  
vin2a_fld0  
cam_shutter  
vin2b_vsync1  
gpio4_22  
I
PD  
PD  
PD  
PD  
15  
15  
1.8/3.3  
1.8/3.3  
vddshv5  
vddshv6  
Yes  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
N / Y / N  
1
O
I
2
0
14  
15  
0
IO  
I
Driver off  
AB17  
vout1_clk  
vin1a_d12  
clkout0  
N / Y / N  
O
I
Dual  
Voltage  
LVCMOS  
PU/PD  
0
2
4
O
I
vin2a_clk0  
gpio2_20  
9
14  
15  
0
IO  
I
Driver off  
U17  
vout1_de  
vout1_de  
N / Y / N  
N / Y / N  
N / Y / N  
O
IO  
I
PD  
PD  
PD  
PD  
PD  
PD  
15  
15  
15  
1.8/3.3  
1.8/3.3  
1.8/3.3  
vddshv6  
vddshv6  
vddshv6  
Yes  
Yes  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
mcasp1_aclkx  
vin1a_d13  
clkout1  
1
0
0
2
4
O
IO  
I
gpio2_21  
14  
15  
0
Driver off  
W17  
vout1_fld  
vout1_fld  
O
IO  
I
Dual  
Voltage  
LVCMOS  
PU/PD  
mcasp1_fsx  
vin1a_d14  
clkout2  
1
0
0
2
4
O
IO  
I
gpio2_22  
14  
15  
0
Driver off  
AA17  
vout1_hsync  
vout1_hsync  
mcasp1_aclkr  
vin1a_d15  
vin2a_de0  
gpio2_23  
O
IO  
I
Dual  
Voltage  
LVCMOS  
PU/PD  
1
0
0
2
9
I
14  
15  
IO  
I
Driver off  
Copyright © 2016–2020, Texas Instruments Incorporated  
Terminal Configuration and Functions  
33  
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TDA3MV, TDA3MA, TDA3MD  
TDA3LX, TDA3LA  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
www.ti.com  
Table 4-2. Ball Characteristics(1) (continued)  
BALL  
RESET  
REL.  
MUXMODE VALUE [10]  
[9]  
BALL  
RESET  
REL.  
BALL  
RESET  
STATE [7]  
I/O  
VOLTAGE  
PULL  
MA/LX/LA MUXMODE  
POWER  
[11]  
BUFFER  
TYPE [13]  
BALL NUMBER [1]  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [6]  
HYS [12]  
UP/DOWN DSIS [15]  
TYPE [14]  
[4]  
[5]  
STATE [8]  
U16  
vout1_vsync  
vout1_vsync  
N / Y / N  
0
O
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
15  
15  
15  
15  
1.8/3.3  
1.8/3.3  
1.8/3.3  
1.8/3.3  
vddshv6  
vddshv6  
vddshv6  
vddshv6  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
0
mcasp1_fsr  
vin2a_fld0  
gpio2_24  
1
IO  
I
9
14  
15  
0
IO  
I
Driver off  
W16  
V16  
U15  
vout1_d0  
vout1_d1  
vout1_d2  
vout1_d0  
N / Y / N  
N / Y / N  
N / Y / N  
O
IO  
IO  
IO  
I
Yes  
Yes  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
mcasp1_axr0  
mmc_clk  
1
0
1
5
gpio2_25  
14  
15  
0
Driver off  
vout1_d1  
O
IO  
IO  
IO  
I
Dual  
Voltage  
LVCMOS  
PU/PD  
mcasp1_axr1  
mmc_cmd  
gpio2_26  
1
0
1
5
14  
15  
0
Driver off  
vout1_d2  
O
IO  
IO  
IO  
IO  
I
Dual  
Voltage  
LVCMOS  
PU/PD  
mcasp1_axr2  
mcasp1_axr8  
mmc_dat0  
gpio2_27  
1
0
0
1
4
5
14  
15  
0
Driver off  
V15  
vout1_d3  
vout1_d3  
N / Y / N  
O
IO  
IO  
IO  
IO  
I
PD  
PD  
15  
1.8/3.3  
vddshv6  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
mcasp1_axr3  
mcasp1_axr9  
mmc_dat1  
gpio2_28  
1
0
0
1
4
5
14  
15  
0
Driver off  
Y15  
vout1_d4  
vout1_d4  
N / Y / N  
O
IO  
IO  
IO  
IO  
I
PD  
PD  
15  
1.8/3.3  
vddshv6  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
mcasp1_axr4  
mcasp1_axr10  
mmc_dat2  
gpio2_29  
1
0
0
1
4
5
14  
15  
Driver off  
34  
Terminal Configuration and Functions  
Copyright © 2016–2020, Texas Instruments Incorporated  
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TDA3MV, TDA3MA, TDA3MD  
TDA3LX, TDA3LA  
www.ti.com  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
Table 4-2. Ball Characteristics(1) (continued)  
BALL  
RESET  
REL.  
MUXMODE VALUE [10]  
[9]  
BALL  
RESET  
REL.  
BALL  
RESET  
STATE [7]  
I/O  
VOLTAGE  
PULL  
MA/LX/LA MUXMODE  
POWER  
[11]  
BUFFER  
TYPE [13]  
BALL NUMBER [1]  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [6]  
HYS [12]  
UP/DOWN DSIS [15]  
TYPE [14]  
[4]  
[5]  
STATE [8]  
W15  
vout1_d5  
vout1_d5  
N / Y / N  
0
O
PD  
PD  
15  
1.8/3.3  
vddshv6  
Yes  
Dual  
PU/PD  
Voltage  
LVCMOS  
mcasp1_axr5  
mcasp1_axr11  
mmc_dat3  
vin2a_clk0  
gpio2_30  
1
IO  
IO  
IO  
I
0
0
1
4
5
9
14  
15  
0
IO  
I
Driver off  
AA15  
vout1_d6  
vout1_d6  
N / Y / N  
O
IO  
IO  
IO  
O
I
PD  
PD  
15  
1.8/3.3  
vddshv6  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
mcasp1_axr6  
mcasp1_axr12  
esm_error  
emu2  
1
0
0
0
4
5
6
vin2a_de0  
gpio2_31  
9
14  
15  
0
IO  
I
Driver off  
AB15  
vout1_d7  
vout1_d7  
N / Y / N  
O
IO  
IO  
IO  
O
I
PD  
PD  
15  
1.8/3.3  
vddshv6  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
mcasp1_axr7  
eCAP1_in_PWM1_out  
mcasp1_axr13  
emu3  
1
0
0
0
3
4
6
vin2a_fld0  
gpio3_0  
9
14  
15  
0
IO  
I
Driver off  
AA14  
vout1_d8  
vout1_d8  
N / Y / N  
O
IO  
I
PD  
PD  
15  
1.8/3.3  
vddshv6  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
mcasp1_axr8  
vin2a_d0  
1
0
0
2
gpmc_a20  
emu4  
3
O
O
IO  
I
6
gpio3_1  
14  
15  
0
Driver off  
AB14  
vout1_d9  
vout1_d9  
N / Y / N  
O
IO  
I
PD  
PD  
15  
1.8/3.3  
vddshv6  
Yes  
Dual  
PU/PD  
Voltage  
LVCMOS  
mcasp1_axr9  
vin2a_d1  
1
0
0
2
gpmc_a21  
emu5  
3
O
O
IO  
I
6
gpio3_2  
14  
15  
Driver off  
Copyright © 2016–2020, Texas Instruments Incorporated  
Terminal Configuration and Functions  
35  
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TDA3MV, TDA3MA, TDA3MD  
TDA3LX, TDA3LA  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
www.ti.com  
Table 4-2. Ball Characteristics(1) (continued)  
BALL  
RESET  
REL.  
MUXMODE VALUE [10]  
[9]  
BALL  
RESET  
REL.  
BALL  
RESET  
STATE [7]  
I/O  
VOLTAGE  
PULL  
MA/LX/LA MUXMODE  
POWER  
[11]  
BUFFER  
TYPE [13]  
BALL NUMBER [1]  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [6]  
HYS [12]  
UP/DOWN DSIS [15]  
TYPE [14]  
[4]  
[5]  
STATE [8]  
U13  
vout1_d10  
vout1_d10  
N / Y / N  
0
O
PD  
PD  
PD  
PD  
PD  
PD  
15  
15  
15  
1.8/3.3  
1.8/3.3  
1.8/3.3  
vddshv6  
vddshv6  
vddshv6  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
mcasp1_axr10  
vin2a_d2  
gpmc_a22  
emu6  
1
IO  
I
0
0
2
3
O
O
IO  
I
6
gpio3_3  
14  
15  
0
Driver off  
vout1_d11  
mcasp1_axr11  
vin2a_d3  
gpmc_a23  
emu7  
V13  
vout1_d11  
N / Y / N  
O
IO  
I
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
1
0
0
2
3
O
O
IO  
I
6
gpio3_4  
14  
15  
0
Driver off  
vout1_d12  
mcasp1_axr12  
vin2a_d4  
gpmc_a24  
emu8  
Y13  
vout1_d12  
N / Y / N  
O
IO  
I
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
1
0
0
2
3
O
O
IO  
I
6
gpio3_5  
14  
15  
Driver off  
mcasp2_ahclkx  
W13  
vout1_d13  
vout1_d13  
mcasp1_axr13  
vin2a_d5  
gpmc_a25  
emu9  
N / Y / N  
0
O
IO  
I
PD  
PD  
15  
1.8/3.3  
vddshv6  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
1
0
0
2
3
O
O
IO  
I
6
gpio3_6  
14  
15  
Driver off  
mcasp2_aclkr  
U11  
vout1_d14  
vout1_d14  
mcasp1_axr14  
vin2a_d6  
gpmc_a26  
emu10  
N / Y / N  
0
O
IO  
I
PD  
PD  
15  
1.8/3.3  
vddshv6  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
1
0
0
2
3
O
O
IO  
I
6
gpio3_7  
14  
15  
Driver off  
mcasp2_aclkx  
36  
Terminal Configuration and Functions  
Copyright © 2016–2020, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Links: TDA3MV TDA3MA TDA3MD TDA3LX TDA3LA  
 
 
 
 
 
 
 
 
 
 
TDA3MV, TDA3MA, TDA3MD  
TDA3LX, TDA3LA  
www.ti.com  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
Table 4-2. Ball Characteristics(1) (continued)  
BALL  
RESET  
REL.  
MUXMODE VALUE [10]  
[9]  
BALL  
RESET  
REL.  
BALL  
RESET  
STATE [7]  
I/O  
VOLTAGE  
PULL  
MA/LX/LA MUXMODE  
POWER  
[11]  
BUFFER  
TYPE [13]  
BALL NUMBER [1]  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [6]  
HYS [12]  
UP/DOWN DSIS [15]  
TYPE [14]  
[4]  
[5]  
STATE [8]  
V11  
vout1_d15  
vout1_d15  
N / Y / N  
0
O
PD  
PD  
15  
1.8/3.3  
vddshv6  
Yes  
Dual  
PU/PD  
Voltage  
LVCMOS  
mcasp1_axr15  
vin2a_d7  
gpmc_a27  
emu11  
1
IO  
I
0
0
2
3
O
O
IO  
I
6
gpio3_8  
14  
15  
Driver off  
mcasp2_fsx  
U9  
vout1_d16  
vout1_d16  
mcasp1_ahclkx  
vin2a_d8  
gpmc_a0  
mcasp1_axr8  
vin2b_d0  
emu12  
N / Y / N  
0
O
O
I
PD  
PD  
15  
1.8/3.3  
vddshv6  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
1
2
0
3
O
IO  
I
4
0
0
5
6
O
IO  
I
gpio3_9  
14  
15  
0
Driver off  
vout1_d17  
vin2a_d9  
gpmc_a1  
mcasp1_axr9  
vin2b_d1  
emu13  
W11  
vout1_d17  
N / Y / N  
O
I
PD  
PD  
15  
1.8/3.3  
vddshv6  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
0
2
3
O
IO  
I
4
0
0
5
6
O
IO  
I
gpio3_10  
14  
15  
Driver off  
mcasp2_fsr  
V9  
vout1_d18  
vout1_d18  
vin2a_d10  
gpmc_a2  
mcasp1_axr10  
vin2b_d2  
emu14  
N / Y / N  
0
O
I
PD  
PD  
15  
1.8/3.3  
vddshv6  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
0
2
3
O
IO  
I
4
0
0
5
6
O
IO  
I
gpio3_11  
14  
15  
Driver off  
mcasp2_axr0  
Copyright © 2016–2020, Texas Instruments Incorporated  
Terminal Configuration and Functions  
37  
Submit Documentation Feedback  
Product Folder Links: TDA3MV TDA3MA TDA3MD TDA3LX TDA3LA  
 
 
 
 
 
 
 
 
TDA3MV, TDA3MA, TDA3MD  
TDA3LX, TDA3LA  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
www.ti.com  
Table 4-2. Ball Characteristics(1) (continued)  
BALL  
RESET  
REL.  
MUXMODE VALUE [10]  
[9]  
BALL  
RESET  
REL.  
BALL  
RESET  
STATE [7]  
I/O  
VOLTAGE  
PULL  
MA/LX/LA MUXMODE  
POWER  
[11]  
BUFFER  
TYPE [13]  
BALL NUMBER [1]  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [6]  
HYS [12]  
UP/DOWN DSIS [15]  
TYPE [14]  
[4]  
[5]  
STATE [8]  
W9  
vout1_d19  
vout1_d19  
vin2a_d11  
gpmc_a3  
N / Y / N  
0
O
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
15  
15  
15  
15  
1.8/3.3  
1.8/3.3  
1.8/3.3  
1.8/3.3  
vddshv6  
vddshv6  
vddshv6  
vddshv6  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
0
2
I
3
O
IO  
I
mcasp1_axr11  
vin2b_d3  
emu15  
4
0
0
5
6
O
IO  
I
gpio3_12  
14  
15  
Driver off  
mcasp2_axr1  
U8  
W8  
U7  
vout1_d20  
vout1_d21  
vout1_d22  
vout1_d20  
vin2a_d12  
gpmc_a4  
mcasp1_axr12  
vin2b_d4  
emu16  
N / Y / N  
N / Y / N  
N / Y / N  
0
O
I
Yes  
Yes  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
0
2
3
O
IO  
I
4
0
0
5
6
O
IO  
I
gpio3_13  
14  
15  
Driver off  
mcasp2_axr2  
vout1_d21  
vin2a_d13  
gpmc_a5  
mcasp1_axr13  
vin2b_d5  
emu17  
0
O
I
Dual  
Voltage  
LVCMOS  
PU/PD  
0
2
3
O
IO  
I
4
0
0
5
6
O
IO  
I
gpio3_14  
14  
15  
Driver off  
mcasp2_axr3  
vout1_d22  
vin2a_d14  
gpmc_a6  
mcasp1_axr14  
vin2b_d6  
emu18  
0
O
I
Dual  
Voltage  
LVCMOS  
PU/PD  
0
2
3
O
IO  
I
4
0
0
5
6
O
IO  
I
gpio3_15  
14  
15  
Driver off  
mcasp2_axr4  
38  
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Table 4-2. Ball Characteristics(1) (continued)  
BALL  
RESET  
REL.  
MUXMODE VALUE [10]  
[9]  
BALL  
RESET  
REL.  
BALL  
RESET  
STATE [7]  
I/O  
VOLTAGE  
PULL  
MA/LX/LA MUXMODE  
POWER  
[11]  
BUFFER  
TYPE [13]  
BALL NUMBER [1]  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [6]  
HYS [12]  
UP/DOWN DSIS [15]  
TYPE [14]  
[4]  
[5]  
STATE [8]  
V7  
vout1_d23  
vout1_d23  
vin2a_d15  
gpmc_a7  
N / Y / N  
0
O
PD  
PD  
15  
1.8/3.3  
vddshv6  
Yes  
Dual  
Voltage  
LVCMOS  
PU/PD  
0
2
I
3
O
IO  
I
mcasp1_axr15  
vin2b_d7  
emu19  
4
0
0
5
6
O
IO  
I
gpio3_16  
14  
15  
Driver off  
mcasp2_axr5  
A1, A17, A22, A8, vss  
AB1, AB12, AB16,  
AB2, AB21, AB22,  
AB7, B22, E1, G10,  
G16, H10, H11,  
vss  
GND  
H15, H16, H8, H9,  
J22, K1, K10, K11,  
K13, K14, K15,  
K16, K9, M10, M11,  
M12, M13, M16,  
N10, N7, P1, P15,  
P16, R12, R16, R9,  
T14, V22  
P21  
B14  
T19  
D21  
C22  
E22  
vssa_adc  
vssa_csi  
vssa_adc  
vssa_csi  
vssa_dac  
vssa_osc0  
vssa_osc1  
xi_osc0  
GND  
GND  
GND  
GND  
GND  
I
vssa_dac  
vssa_osc0  
vssa_osc1  
xi_osc0  
0
0
0
0
0
1.8  
vdda_osc  
vdda_osc  
vdda_osc  
vdda_osc  
vddshv1  
Yes  
Yes  
Yes  
Yes  
Yes  
LVCMOS  
Analog  
B21  
D22  
C21  
M1  
xi_osc1  
xo_osc0  
xo_osc1  
xref_clk0  
xi_osc1  
xo_osc0  
xo_osc1  
I
0
1.8  
LVCMOS  
Analog  
O
O
0
1.8  
LVCMOS  
Analog  
0
1.8  
LVCMOS  
Analog  
xref_clk0  
clkout0  
0
I
PD  
PD  
15  
1.8/3.3  
Dual  
Voltage  
LVCMOS  
PU/PD  
1
O
IO  
IO  
IO  
IO  
IO  
I
spi3_cs0  
spi2_cs1  
spi1_cs0  
spi1_cs1  
gpio3_31  
Driver off  
4
1
1
1
1
5
6
7
14  
15  
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(1) N/A stands for Not Applicable.  
(2) For more information on recommended operating conditions, see , Recommended Operating Conditions.  
(3) The pullup or pulldown block strength is equal to: minimum = 50 μA, typical = 100 μA, maximum = 250 μA.  
(4) The output impedance settings of this IO cell are programmable; by default, the value is DS[1:0] = 10, this means 40 . For more information on DS[1:0] register configuration, see the  
Device TRM.  
(5) In PUx / PDy, x and y = 60 to 300 μA.  
The output impedance settings (or drive strengths) of this IO are programmable (60 Ω, 80 Ω, 120 Ω) depending on the values of the I[2:0] registers.  
4.3 Multiplexing Characteristics  
Table 4-3 describes the device multiplexing (no characteristics are available in this table).  
NOTE  
This table doesn't take into account subsystem multiplexing signals. Subsystem multiplexing signals are described in Section 4.4, Signal  
Descriptions.  
NOTE  
For more information, see the Pad Configuration Registers section in the device TRM.  
NOTE  
Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the  
proper software configuration (Hi-Z mode is not an input signal).  
NOTE  
When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad’s behavior is undefined. This should be  
avoided.  
CAUTION  
The IO timings provided in Section 7, Timing Requirements and Switching Characteristics are only valid if signals within  
a single IOSET are used. The IOSETs are defined in the corresponding tables.  
40  
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SPRS964H JUNE 2016REVISED FEBRUARY 2020  
Table 4-3. Multiplexing Characteristics  
MUXMODE[15:0] SETTINGS  
BALL  
NUMBER  
ADDRESS REGISTER NAME  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
14  
15  
E22  
xi_osc0  
N2  
ddr1_a7  
AB4  
W1  
U3  
ddr1_d4  
ddr1_dqs2  
ddr1_d20  
ddr1_a1  
C1  
M19  
U1  
adc_in0  
ddr1_a9  
Y6  
ddr1_d7  
A15  
V1  
csi2_0_dx3  
ddr1_a15  
ddr1_d17  
ddr1_a8  
AA2  
T1  
R3  
ddr1_a11  
ddr1_d16  
ddr1_d23  
ddr1_d14  
ddr1_dqs1  
ddr1_d0  
AA3  
Y1  
Y17  
AA20  
AA6  
F3  
ddr1_cke0  
ddr1_dqsn1  
adc_in5  
Y20  
N21  
T2  
ddr1_a6  
W2  
E3  
ddr1_dqsn2  
ddr1_wen  
adc_in7  
P18  
AA11  
ddr1_ecc_d  
2
B3  
ddr1_ba0  
cvideo_tvout  
ddr1_d30  
xi_osc1  
T17  
W22  
B21  
V3  
ddr1_d21  
ddr1_d25  
csi2_0_dx0  
ddr1_nck  
ddr1_d24  
T20  
A11  
G2  
U21  
Y9  
ddr1_ecc_d  
3
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Table 4-3. Multiplexing Characteristics (continued)  
MUXMODE[15:0] SETTINGS  
BALL  
NUMBER  
ADDRESS REGISTER NAME  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
14  
15  
R21  
U4  
ddr1_d26  
ddr1_a0  
AB18  
A3  
ddr1_d15  
ddr1_ba1  
ddr1_ba2  
csi2_0_dy3  
ddr1_d10  
ddr1_d1  
D2  
B15  
AA21  
AA8  
B13  
AB8  
M22  
D1  
csi2_0_dy2  
ddr1_dqm0  
adc_in3  
ddr1_a10  
ddr1_d18  
xo_osc1  
Y3  
C21  
M20  
R22  
AA9  
adc_in1  
ddr1_d28  
ddr1_ecc_d  
6
N3  
ddr1_a5  
ddr1_odt0  
ddr1_a4  
P2  
T4  
AB10  
ddr1_dqsn_  
ecc  
AB3  
ddr1_dqm2  
AA12  
ddr1_ecc_d  
1
AA4  
T18  
N22  
R4  
ddr1_d6  
cvideo_rset  
adc_in4  
ddr1_a3  
ddr1_d29  
V20  
AB13  
ddr1_dqm_e  
cc  
AA5  
A16  
R2  
ddr1_dqs0  
csi2_0_dx4  
ddr1_a14  
ddr1_d22  
ddr1_d9  
Y2  
Y21  
W21  
P20  
ddr1_dqm3  
adc_vrefp  
42  
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SPRS964H JUNE 2016REVISED FEBRUARY 2020  
Table 4-3. Multiplexing Characteristics (continued)  
MUXMODE[15:0] SETTINGS  
BALL  
NUMBER  
ADDRESS REGISTER NAME  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
14  
15  
Y5  
ddr1_d5  
F2  
ddr1_casn  
ddr1_d13  
csi2_0_dy0  
AB20  
B11  
AB9  
ddr1_ecc_d  
7
D22  
U2  
xo_osc0  
ddr1_a12  
adc_in6  
P19  
AA18  
U22  
Y18  
A13  
T22  
G1  
ddr1_d8  
ddr1_d31  
ddr1_dqm1  
csi2_0_dx2  
ddr1_dqsn3  
ddr1_ck  
P17  
G3  
cvideo_vfb  
porz  
T21  
Y22  
AA19  
AB5  
U20  
AA13  
ddr1_dqs3  
ddr1_d11  
ddr1_d12  
ddr1_dqsn0  
ddr1_d27  
ddr1_ecc_d  
4
B16  
F1  
csi2_0_dy4  
ddr1_rasn  
ddr1_a2  
D3  
AA10  
ddr1_dqs_e  
cc  
AA7  
B2  
ddr1_d3  
ddr1_csn0  
ddr1_rst  
N1  
V2  
ddr1_d19  
ddr1_d2  
Y8  
B12  
C3  
csi2_0_dy1  
ddr1_a13  
csi2_0_dx1  
A12  
AB11  
ddr1_ecc_d  
5
M21  
adc_in2  
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Table 4-3. Multiplexing Characteristics (continued)  
MUXMODE[15:0] SETTINGS  
BALL  
NUMBER  
ADDRESS REGISTER NAME  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
14  
15  
Y11  
ddr1_ecc_d  
0
0x1400  
0x1404  
0x1408  
0x140C  
0x1410  
0x1414  
0x1418  
0x141C  
0x1420  
0x1424  
0x1428  
0x142C  
0x1430  
0x1434  
0x1438  
0x143C  
0x1440  
0x1444  
0x1448  
0x144C  
CTRL_CORE_PAD_ C12  
GPMC_CLK  
gpmc_clk  
rgmii1_txc  
clkout0  
dma_evt1  
dma_evt2  
dma_evt3  
dma_evt4  
gpio1_0  
gpio1_1  
gpio1_2  
gpio1_3  
gpio1_4  
gpio1_5  
gpio1_6  
gpio1_7  
gpio1_8  
gpio1_9  
gpio1_10  
gpio1_11  
gpio1_12  
gpio1_13  
gpio1_14  
gpio1_15  
gpio1_16  
gpio1_17  
gpio1_18  
gpio1_19  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
sysboot0  
sysboot1  
sysboot2  
sysboot3  
sysboot4  
CTRL_CORE_PAD_ D12  
GPMC_BEN0  
gpmc_ben0 rgmii1_txctl  
gpmc_ben1 rgmii1_txd3  
ehrpwm1A  
ehrpwm1B  
CTRL_CORE_PAD_ E12  
GPMC_BEN1  
CTRL_CORE_PAD_ F12  
GPMC_ADVN_ALE  
gpmc_advn_ rgmii1_txd2  
ale  
ehrpwm1_tri clkout1  
pzone_input  
CTRL_CORE_PAD_ A10  
GPMC_OEN_REN  
gpmc_oen_r rgmii1_txd1  
en  
ehrpwm1_sy clkout2  
nci  
CTRL_CORE_PAD_ B10  
GPMC_WEN  
gpmc_wen rgmii1_txd0  
ehrpwm1_sy  
nco  
CTRL_CORE_PAD_ C10  
GPMC_CS0  
gpmc_cs0  
gpmc_cs1  
gpmc_cs2  
gpmc_cs3  
gpmc_cs4  
gpmc_cs5  
gpmc_cs6  
rgmii1_rxctl  
qspi1_cs0  
qspi1_d3  
qspi1_d2  
qspi1_d0  
qspi1_d1  
qspi1_sclk  
CTRL_CORE_PAD_ E10  
GPMC_CS1  
CTRL_CORE_PAD_ D10  
GPMC_CS2  
CTRL_CORE_PAD_ A9  
GPMC_CS3  
CTRL_CORE_PAD_ B9  
GPMC_CS4  
CTRL_CORE_PAD_ F10  
GPMC_CS5  
CTRL_CORE_PAD_ C8  
GPMC_CS6  
CTRL_CORE_PAD_ D8  
GPMC_WAIT0  
gpmc_wait0 rgmii1_rxd3 qspi1_rtclk  
gpmc_ad0 rgmii1_rxd2  
gpmc_ad1 rgmii1_rxd1  
gpmc_ad2 rgmii1_rxd0  
gpmc_ad3 qspi1_rtclk  
dma_evt4  
CTRL_CORE_PAD_ E8  
GPMC_AD0  
CTRL_CORE_PAD_ A7  
GPMC_AD1  
CTRL_CORE_PAD_ F8  
GPMC_AD2  
CTRL_CORE_PAD_ B7  
GPMC_AD3  
CTRL_CORE_PAD_ A6  
GPMC_AD4  
gpmc_ad4 cam_strobe  
CTRL_CORE_PAD_ F7  
GPMC_AD5  
gpmc_ad5  
uart2_txd  
uart2_rxd  
timer6  
spi3_d1  
sysboot5  
mcasp2_acl  
kx  
0x1450  
0x1454  
CTRL_CORE_PAD_ E7  
GPMC_AD6  
gpmc_ad6  
timer5  
timer4  
spi3_d0  
gpio1_20  
gpio1_21  
sysboot6  
mcasp2_fsx  
CTRL_CORE_PAD_ C6  
GPMC_AD7  
gpmc_ad7 cam_shutter  
spi3_sclk  
Driver off  
mcasp2_ahc  
lkx  
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Table 4-3. Multiplexing Characteristics (continued)  
MUXMODE[15:0] SETTINGS  
BALL  
NUMBER  
ADDRESS REGISTER NAME  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
14  
15  
0x1458  
CTRL_CORE_PAD_ B6  
GPMC_AD8  
gpmc_ad8  
timer7  
spi3_cs0  
gpio1_22  
sysboot8  
mcasp2_acl  
kr  
0x145C  
0x1460  
CTRL_CORE_PAD_ A5  
GPMC_AD9  
gpmc_ad9  
eCAP1_in_P spi3_cs1  
WM1_out  
gpio1_23  
gpio1_24  
sysboot9  
mcasp2_fsr  
CTRL_CORE_PAD_ D6  
GPMC_AD10  
gpmc_ad10  
timer2  
sysboot10  
mcasp2_axr  
0
0x1464  
0x1468  
0x146C  
0x1470  
0x1474  
0x1478  
CTRL_CORE_PAD_ C5  
GPMC_AD11  
gpmc_ad11  
gpmc_ad12  
timer3  
gpio1_25  
gpio1_26  
gpio1_27  
gpio1_28  
gpio1_29  
gpio1_30  
sysboot11  
mcasp2_axr  
1
CTRL_CORE_PAD_ B5  
GPMC_AD12  
sysboot12  
mcasp2_axr  
2
CTRL_CORE_PAD_ D7  
GPMC_AD13  
gpmc_ad13 rgmii1_rxc  
gpmc_ad14  
sysboot13  
mcasp2_axr  
3
CTRL_CORE_PAD_ B4  
GPMC_AD14  
spi2_cs1  
spi2_cs0  
clkout0  
sysboot14  
mcasp2_axr  
4
CTRL_CORE_PAD_ A4  
GPMC_AD15  
gpmc_ad15  
sysboot15  
mcasp2_axr  
5
CTRL_CORE_PAD_ F22  
VIN1A_CLK0  
vin1a_clk0 cpi_pclk  
Driver off  
mcasp3_acl  
kx  
0x147C  
0x1480  
CTRL_CORE_PAD_ F21  
VIN1A_DE0  
vin1a_de0  
vin1a_fld0  
cpi_hsync  
cpi_vsync  
vin1b_clk1  
vin2b_clk1  
clkout1  
clkout2  
gpio1_31  
gpio2_0  
Driver off  
CTRL_CORE_PAD_ F20  
VIN1A_FLD0  
Driver off  
mcasp3_acl  
kr  
0x1484  
0x1488  
CTRL_CORE_PAD_ F19  
VIN1A_HSYNC0  
vin1a_hsync cpi_data0  
0
vin1a_de0  
gpio2_1  
gpio2_2  
Driver off  
mcasp3_fsr  
CTRL_CORE_PAD_ G19  
VIN1A_VSYNC0  
vin1a_vsync cpi_data1  
0
Driver off  
mcasp3_axr  
0
0x148C  
0x1490  
0x1494  
0x1498  
0x149C  
CTRL_CORE_PAD_ G18  
VIN1A_D0  
vin1a_d0  
vin1a_d1  
vin1a_d2  
vin1a_d3  
vin1a_d4  
cpi_data2  
cpi_data3  
cpi_data4  
cpi_data5  
cpi_data6  
gpio2_3  
gpio2_4  
gpio2_5  
gpio2_6  
gpio2_7  
Driver off  
mcasp3_axr  
1
CTRL_CORE_PAD_ G21  
VIN1A_D1  
Driver off  
mcasp3_axr  
2
CTRL_CORE_PAD_ G22  
VIN1A_D2  
Driver off  
mcasp3_axr  
3
CTRL_CORE_PAD_ H18  
VIN1A_D3  
Driver off  
mcasp3_axr  
4
CTRL_CORE_PAD_ H20  
VIN1A_D4  
Driver off  
mcasp3_axr  
5
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TDA3LX, TDA3LA  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
www.ti.com  
Table 4-3. Multiplexing Characteristics (continued)  
MUXMODE[15:0] SETTINGS  
BALL  
NUMBER  
ADDRESS REGISTER NAME  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
14  
15  
0x14A0  
CTRL_CORE_PAD_ H19  
VIN1A_D5  
vin1a_d5  
cpi_data7  
gpio2_8  
xref_clk2  
mcasp3_ahc  
lkx  
0x14A4  
0x14A8  
0x14AC  
0x14B0  
0x14B4  
0x14B8  
0x14BC  
0x14C0  
0x14C4  
0x14C8  
0x14CC  
0x14D0  
0x14D4  
0x14D8  
0x14DC  
0x14E0  
0x14E4  
0x14E8  
0x14EC  
0x14F0  
0x14F4  
0x14F8  
CTRL_CORE_PAD_ H22  
VIN1A_D6  
vin1a_d6  
vin1a_d7  
vin1a_d8  
vin1a_d9  
vin1a_d10  
vin1a_d11  
vin1a_d12  
vin1a_d13  
vin1a_d14  
vin1a_d15  
vin2a_clk0  
vin2a_de0  
vin2a_fld0  
vout1_clk  
vout1_de  
vout1_fld  
cpi_data8  
cpi_data9  
gpio2_9  
Driver off  
mcasp3_fsx  
CTRL_CORE_PAD_ H21  
VIN1A_D7  
gpio2_10  
gpio2_11  
gpio2_12  
gpio2_13  
gpio2_14  
gpio2_15  
gpio2_16  
gpio2_17  
gpio2_18  
gpio2_19  
gpio4_21  
gpio4_22  
gpio2_20  
gpio2_21  
gpio2_22  
gpio2_23  
gpio2_24  
gpio2_25  
gpio2_26  
gpio2_27  
gpio2_28  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
CTRL_CORE_PAD_ J17  
VIN1A_D8  
cpi_data10 vin1b_d0  
cpi_data11 vin1b_d1  
cpi_data12 vin1b_d2  
cpi_data13 vin1b_d3  
cpi_data14 vin1b_d4  
gpmc_a8  
sys_nirq2  
sys_nirq1  
sys_nirq2  
sys_nirq1  
CTRL_CORE_PAD_ K22  
VIN1A_D9  
gpmc_a9  
CTRL_CORE_PAD_ K21  
VIN1A_D10  
gpmc_a10  
gpmc_a11  
gpmc_a12  
gpmc_a13  
gpmc_a14  
gpmc_a15  
CTRL_CORE_PAD_ K18  
VIN1A_D11  
CTRL_CORE_PAD_ K17  
VIN1A_D12  
dma_evt1  
dma_evt2  
CTRL_CORE_PAD_ K19  
VIN1A_D13  
cpi_wen  
cpi_fid  
vin1b_d5  
vin1b_d6  
CTRL_CORE_PAD_ K20  
VIN1A_D14  
CTRL_CORE_PAD_ L21  
VIN1A_D15  
cpi_data15 vin1b_d7  
CTRL_CORE_PAD_ L22  
VIN2A_CLK0  
CTRL_CORE_PAD_ M17  
VIN2A_DE0  
cam_strobe vin2b_hsync  
1
vin2b_de1  
CTRL_CORE_PAD_ M18  
VIN2A_FLD0  
cam_shutter vin2b_vsync  
1
CTRL_CORE_PAD_ AB17  
VOUT1_CLK  
vin1a_d12  
clkout0  
clkout1  
clkout2  
vin2a_clk0  
CTRL_CORE_PAD_ U17  
VOUT1_DE  
mcasp1_acl vin1a_d13  
kx  
CTRL_CORE_PAD_ W17  
VOUT1_FLD  
mcasp1_fsx vin1a_d14  
CTRL_CORE_PAD_ AA17  
VOUT1_HSYNC  
vout1_hsync mcasp1_acl vin1a_d15  
kr  
vin2a_de0  
vin2a_fld0  
CTRL_CORE_PAD_ U16  
VOUT1_VSYNC  
vout1_vsync mcasp1_fsr  
CTRL_CORE_PAD_ W16  
VOUT1_D0  
vout1_d0  
vout1_d1  
vout1_d2  
vout1_d3  
mcasp1_axr  
0
mmc_clk  
CTRL_CORE_PAD_ V16  
VOUT1_D1  
mcasp1_axr  
1
mmc_cmd  
CTRL_CORE_PAD_ U15  
VOUT1_D2  
mcasp1_axr  
2
mcasp1_axr mmc_dat0  
8
CTRL_CORE_PAD_ V15  
VOUT1_D3  
mcasp1_axr  
3
mcasp1_axr mmc_dat1  
9
46  
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SPRS964H JUNE 2016REVISED FEBRUARY 2020  
Table 4-3. Multiplexing Characteristics (continued)  
MUXMODE[15:0] SETTINGS  
BALL  
NUMBER  
ADDRESS REGISTER NAME  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
14  
15  
0x14FC  
0x1500  
0x1504  
0x1508  
0x150C  
0x1510  
0x1514  
0x1518  
0x151C  
CTRL_CORE_PAD_ Y15  
VOUT1_D4  
vout1_d4  
mcasp1_axr  
4
mcasp1_axr mmc_dat2  
10  
gpio2_29  
Driver off  
CTRL_CORE_PAD_ W15  
VOUT1_D5  
vout1_d5  
vout1_d6  
vout1_d7  
vout1_d8  
vout1_d9  
mcasp1_axr  
5
mcasp1_axr mmc_dat3  
11  
vin2a_clk0  
vin2a_de0  
vin2a_fld0  
gpio2_30  
gpio2_31  
gpio3_0  
gpio3_1  
gpio3_2  
gpio3_3  
gpio3_4  
gpio3_5  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
CTRL_CORE_PAD_ AA15  
VOUT1_D6  
mcasp1_axr  
6
mcasp1_axr esm_error  
12  
emu2  
emu3  
emu4  
emu5  
emu6  
emu7  
emu8  
CTRL_CORE_PAD_ AB15  
VOUT1_D7  
mcasp1_axr  
7
eCAP1_in_P mcasp1_axr  
WM1_out  
13  
CTRL_CORE_PAD_ AA14  
VOUT1_D8  
mcasp1_axr vin2a_d0  
8
gpmc_a20  
CTRL_CORE_PAD_ AB14  
VOUT1_D9  
mcasp1_axr vin2a_d1  
9
gpmc_a21  
gpmc_a22  
gpmc_a23  
gpmc_a24  
CTRL_CORE_PAD_ U13  
VOUT1_D10  
vout1_d10 mcasp1_axr vin2a_d2  
10  
CTRL_CORE_PAD_ V13  
VOUT1_D11  
vout1_d11 mcasp1_axr vin2a_d3  
11  
CTRL_CORE_PAD_ Y13  
VOUT1_D12  
vout1_d12 mcasp1_axr vin2a_d4  
12  
Driver off  
mcasp2_ahc  
lkx  
0x1520  
0x1524  
CTRL_CORE_PAD_ W13  
VOUT1_D13  
vout1_d13 mcasp1_axr vin2a_d5  
13  
gpmc_a25  
gpmc_a26  
emu9  
gpio3_6  
gpio3_7  
Driver off  
mcasp2_acl  
kr  
CTRL_CORE_PAD_ U11  
VOUT1_D14  
vout1_d14 mcasp1_axr vin2a_d6  
14  
emu10  
Driver off  
mcasp2_acl  
kx  
0x1528  
0x152C  
0x1530  
0x1534  
CTRL_CORE_PAD_ V11  
VOUT1_D15  
vout1_d15 mcasp1_axr vin2a_d7  
15  
gpmc_a27  
gpmc_a0  
gpmc_a1  
gpmc_a2  
emu11  
emu12  
emu13  
emu14  
gpio3_8  
gpio3_9  
gpio3_10  
gpio3_11  
Driver off  
mcasp2_fsx  
CTRL_CORE_PAD_ U9  
VOUT1_D16  
vout1_d16 mcasp1_ahc vin2a_d8  
lkx  
mcasp1_axr vin2b_d0  
8
Driver off  
CTRL_CORE_PAD_ W11  
VOUT1_D17  
vout1_d17  
vin2a_d9  
mcasp1_axr vin2b_d1  
9
Driver off  
mcasp2_fsr  
CTRL_CORE_PAD_ V9  
VOUT1_D18  
vout1_d18  
vin2a_d10  
mcasp1_axr vin2b_d2  
10  
Driver off  
mcasp2_axr  
0
0x1538  
0x153C  
0x1540  
0x1544  
0x1548  
CTRL_CORE_PAD_ W9  
VOUT1_D19  
vout1_d19  
vout1_d20  
vout1_d21  
vout1_d22  
vout1_d23  
vin2a_d11  
vin2a_d12  
vin2a_d13  
vin2a_d14  
vin2a_d15  
gpmc_a3  
gpmc_a4  
gpmc_a5  
gpmc_a6  
gpmc_a7  
mcasp1_axr vin2b_d3  
11  
emu15  
emu16  
emu17  
emu18  
emu19  
gpio3_12  
gpio3_13  
gpio3_14  
gpio3_15  
gpio3_16  
Driver off  
mcasp2_axr  
1
CTRL_CORE_PAD_ U8  
VOUT1_D20  
mcasp1_axr vin2b_d4  
12  
Driver off  
mcasp2_axr  
2
CTRL_CORE_PAD_ W8  
VOUT1_D21  
mcasp1_axr vin2b_d5  
13  
Driver off  
mcasp2_axr  
3
CTRL_CORE_PAD_ U7  
VOUT1_D22  
mcasp1_axr vin2b_d6  
14  
Driver off  
mcasp2_axr  
4
CTRL_CORE_PAD_ V7  
VOUT1_D23  
mcasp1_axr vin2b_d7  
15  
Driver off  
mcasp2_axr  
5
Copyright © 2016–2020, Texas Instruments Incorporated  
Terminal Configuration and Functions  
47  
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TDA3MV, TDA3MA, TDA3MD  
TDA3LX, TDA3LA  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
www.ti.com  
Table 4-3. Multiplexing Characteristics (continued)  
MUXMODE[15:0] SETTINGS  
BALL  
NUMBER  
ADDRESS REGISTER NAME  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
14  
15  
0x154C  
0x1550  
0x1554  
0x1558  
0x155C  
0x1560  
0x1564  
0x1568  
0x156C  
0x1570  
0x1574  
0x1578  
0x157C  
0x1580  
0x1584  
0x1588  
0x158C  
0x1590  
0x1594  
0x1598  
0x159C  
0x15A0  
0x15A4  
0x15A8  
CTRL_CORE_PAD_ W7  
MCAN_TX  
mcan_tx  
vin2a_de0  
vin2a_hsync spi1_cs2  
0
uart3_rxd  
gpmc_wait1 vin1b_hsync vin1b_de1  
1
gpio4_11  
Driver off  
CTRL_CORE_PAD_ W6  
MCAN_RX  
mcan_rx  
cam_nreset vin2a_vsync spi1_cs3  
0
uart3_txd  
spi4_d1  
spi4_d0  
gpmc_cs7  
vin1b_vsync  
1
gpio4_12  
gpio3_17  
gpio3_18  
gpio3_19  
gpio3_20  
gpio3_21  
gpio3_22  
gpio3_23  
gpio3_24  
gpio3_25  
gpio3_26  
gpio3_27  
gpio3_28  
gpio3_29  
gpio3_30  
gpio3_31  
gpio4_0  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
CTRL_CORE_PAD_ B19  
MDIO_MCLK  
mdio_mclk  
mdio_d  
CTRL_CORE_PAD_ B17  
MDIO_D  
esm_error  
mmc_clk  
CTRL_CORE_PAD_ C16  
RGMII0_TXC  
rgmii0_txc  
rgmii0_txctl  
rgmii0_txd3  
rgmii0_txd2  
rgmii0_txd1  
rgmii0_txd0  
rgmii0_rxc  
rgmii0_rxctl  
rgmii0_rxd3  
rgmii0_rxd2  
rgmii0_rxd1  
rgmii0_rxd0  
xref_clk0  
cam_strobe spi4_sclk  
cam_shutter spi4_cs0  
CTRL_CORE_PAD_ C17  
RGMII0_TXCTL  
mmc_cmd  
mmc_dat0  
mmc_dat1  
mmc_dat2  
mmc_dat3  
mmc_clk  
CTRL_CORE_PAD_ E16  
RGMII0_TXD3  
CTRL_CORE_PAD_ D16  
RGMII0_TXD2  
eCAP1_in_P  
WM1_out  
CTRL_CORE_PAD_ E17  
RGMII0_TXD1  
CTRL_CORE_PAD_ F17  
RGMII0_TXD0  
CTRL_CORE_PAD_ B18  
RGMII0_RXC  
cam_strobe  
cam_shutter  
CTRL_CORE_PAD_ C18  
RGMII0_RXCTL  
mmc_cmd  
mmc_dat0  
mmc_dat1  
mmc_dat2  
mmc_dat3  
spi2_cs1  
CTRL_CORE_PAD_ A19  
RGMII0_RXD3  
CTRL_CORE_PAD_ B20  
RGMII0_RXD2  
CTRL_CORE_PAD_ C20  
RGMII0_RXD1  
CTRL_CORE_PAD_ A20  
RGMII0_RXD0  
CTRL_CORE_PAD_ M1  
XREF_CLK0  
clkout0  
spi3_cs0  
spi1_cs0  
spi1_cs1  
CTRL_CORE_PAD_ M2  
SPI1_SCLK  
spi1_sclk  
spi1_d1  
uart3_rxd  
uart3_ctsn  
uart3_rtsn  
uart3_txd  
spi3_cs1  
uart3_rxd  
uart3_ctsn  
CTRL_CORE_PAD_ U6  
SPI1_D1  
gpio4_1  
CTRL_CORE_PAD_ T5  
SPI1_D0  
spi1_d0  
gpio4_2  
CTRL_CORE_PAD_ R6  
SPI1_CS0  
spi1_cs0  
gpio4_3  
CTRL_CORE_PAD_ R5  
SPI1_CS1  
spi1_cs1  
timer6  
ehrpwm1_tri  
pzone_input  
gpio4_4  
CTRL_CORE_PAD_ L1  
SPI2_SCLK  
spi2_sclk  
spi2_d1  
ehrpwm1A timer3  
timer5  
gpio4_5  
CTRL_CORE_PAD_ N4  
SPI2_D1  
eCAP1_in_P  
WM1_out  
gpio4_6  
48  
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SPRS964H JUNE 2016REVISED FEBRUARY 2020  
Table 4-3. Multiplexing Characteristics (continued)  
MUXMODE[15:0] SETTINGS  
BALL  
NUMBER  
ADDRESS REGISTER NAME  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
14  
15  
0x15AC  
0x15B0  
0x15B8  
0x15B4  
0x15BC  
0x15C0  
0x15C4  
0x15C8  
0x15CC  
0x15D0  
0x15D4  
0x15D8  
0x15DC  
0x15E0  
0x15E4  
0x15E8  
0x15EC  
0x15F0  
0x15F4  
0x15F8  
0x15FC  
0x1600  
0x1604  
0x1608  
CTRL_CORE_PAD_ R7  
SPI2_D0  
spi2_d0  
uart3_rtsn  
timer1  
gpio4_7  
sysboot7  
CTRL_CORE_PAD_ L2  
SPI2_CS0  
spi2_cs0  
dcan1_rx  
dcan1_tx  
uart1_rxd  
uart1_txd  
uart3_txd  
ehrpwm1B timer4  
gpio4_8  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
Driver off  
CTRL_CORE_PAD_ N6  
DCAN1_RX  
gpio4_10  
gpio4_9  
CTRL_CORE_PAD_ N5  
DCAN1_TX  
CTRL_CORE_PAD_ F13  
UART1_RXD  
spi4_d1  
spi4_d0  
qspi1_rtclk  
gpmc_a12  
gpmc_a13  
mcan_tx  
mcan_rx  
gpio4_13  
gpio4_14  
gpio4_15  
gpio4_16  
gpio4_17  
gpio4_18  
gpio4_19  
gpio4_20  
CTRL_CORE_PAD_ E14  
UART1_TXD  
CTRL_CORE_PAD_ F14  
UART1_CTSN  
uart1_ctsn xref_clk1  
uart1_rtsn  
uart3_rxd  
uart3_txd  
gpmc_a16 spi4_sclk  
gpmc_a17 spi4_cs0  
spi3_d1  
spi1_cs2  
spi1_cs3  
timer3  
ehrpwm1_sy clkout0  
nci  
vin2a_hsync gpmc_a12 gpmc_clk  
0
dcan1_tx  
CTRL_CORE_PAD_ C14  
UART1_RTSN  
timer4  
timer1  
timer2  
timer7  
timer8  
ehrpwm1_sy qspi1_rtclk vin2a_vsync gpmc_a13  
dcan1_rx  
nco  
0
CTRL_CORE_PAD_ D14  
UART2_RXD  
uart2_rxd  
ehrpwm1A  
gpmc_clk  
gpmc_a12 dcan1_tx  
gpmc_a13 dcan1_rx  
mcan_tx  
CTRL_CORE_PAD_ D15  
UART2_TXD  
uart2_txd  
spi3_d0  
ehrpwm1B  
CTRL_CORE_PAD_ F15  
UART2_CTSN  
uart2_ctsn  
xref_clk1  
gpmc_a18 spi3_sclk  
gpmc_a19 spi3_cs0  
qspi1_cs1  
vin2a_hsync gpmc_clk  
0
CTRL_CORE_PAD_ F16  
UART2_RTSN  
uart2_rtsn  
i2c1_sda  
i2c1_scl  
i2c2_sda  
i2c2_scl  
tms  
eCAP1_in_P  
WM1_out  
vin2a_vsync  
0
mcan_rx  
CTRL_CORE_PAD_ L4  
I2C1_SDA  
CTRL_CORE_PAD_ L3  
I2C1_SCL  
CTRL_CORE_PAD_ L5  
I2C2_SDA  
CTRL_CORE_PAD_ L6  
I2C2_SCL  
CTRL_CORE_PAD_ J3  
TMS  
CTRL_CORE_PAD_ J1  
TDI  
tdi  
gpio4_25  
gpio4_26  
Driver off  
Driver off  
CTRL_CORE_PAD_ J4  
TDO  
tdo  
CTRL_CORE_PAD_ J2  
TCLK  
tclk  
CTRL_CORE_PAD_ J5  
TRSTN  
trstn  
CTRL_CORE_PAD_ J6  
RTCK  
rtck  
gpio4_27  
gpio4_28  
gpio4_29  
Driver off  
Driver off  
Driver off  
CTRL_CORE_PAD_ H1  
EMU0  
emu0  
emu1  
CTRL_CORE_PAD_ H2  
EMU1  
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Terminal Configuration and Functions  
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SPRS964H JUNE 2016REVISED FEBRUARY 2020  
www.ti.com  
Table 4-3. Multiplexing Characteristics (continued)  
MUXMODE[15:0] SETTINGS  
BALL  
NUMBER  
ADDRESS REGISTER NAME  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
14  
15  
0x160C  
0x1610  
0x1614  
CTRL_CORE_PAD_ G4  
RESETN  
resetn  
nmin  
CTRL_CORE_PAD_ G5  
NMIN  
CTRL_CORE_PAD_ F4  
RSTOUTN  
rstoutn  
1. NA in table stands for Not Applicable.  
50  
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SPRS964H JUNE 2016REVISED FEBRUARY 2020  
4.4 Signal Descriptions  
Many signals are available on multiple pins, according to the software configuration of the pin multiplexing  
options.  
1. SIGNAL NAME: The name of the signal passing through the pin.  
NOTE  
The subsystem multiplexing signals are not described in Table 4-2 and Table 4-3.  
2. DESCRIPTION: Description of the signal  
3. TYPE: Signal direction and type:  
I = Input  
O = Output  
IO = Input or output  
D = Open Drain  
DS = Differential  
A = Analog  
PWR = Power  
GND = Ground  
4. BALL: Associated ball(s) bottom  
NOTE  
For more information, see the Control Module Register Manual section in the device TRM.  
4.4.1 Video Input Ports (VIP)  
NOTE  
For more information, see the Video Input Port (VIP) section in the device TRM.  
CAUTION  
The IO timings provided in Section 7, Timing Requirements and Switching  
Characteristics are only valid for VIN1 and VIN2 if signals within a single IOSET  
are used. The IOSETs are defined in Table 7-3 and Table 7-4.  
Table 4-4. VIP Signal Descriptions  
SIGNAL NAME  
Video Input 1  
vin1a_clk0  
DESCRIPTION  
TYPE  
BALL  
Video Input 1 Port A Clock input. Input clock for 8-bit 16-bit or 24-bit Port A video  
capture. Input data is sampled on the CLK0 edge.  
I
F22  
vin1a_d0  
vin1a_d1  
vin1a_d2  
vin1a_d3  
vin1a_d4  
vin1a_d5  
vin1a_d6  
vin1a_d7  
vin1a_d8  
Video Input 1 Port A Data input  
Video Input 1 Port A Data input  
Video Input 1 Port A Data input  
Video Input 1 Port A Data input  
Video Input 1 Port A Data input  
Video Input 1 Port A Data input  
Video Input 1 Port A Data input  
Video Input 1 Port A Data input  
Video Input 1 Port A Data input  
I
I
I
I
I
I
I
I
I
G18  
G21  
G22  
H18  
H20  
H19  
H22  
H21  
J17  
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Table 4-4. VIP Signal Descriptions (continued)  
SIGNAL NAME  
vin1a_d9  
DESCRIPTION  
TYPE  
BALL  
Video Input 1 Port A Data input  
Video Input 1 Port A Data input  
Video Input 1 Port A Data input  
Video Input 1 Port A Data input  
Video Input 1 Port A Data input  
Video Input 1 Port A Data input  
Video Input 1 Port A Data input  
Video Input 1 Port A Field ID input  
Video Input 1 Port A Field ID input  
Video Input 1 Port A Horizontal Sync input  
Video Input 1 Port A Vertical Sync input  
Video Input 1 Port B Clock input  
Video Input 1 Port B Data input  
Video Input 1 Port B Data input  
Video Input 1 Port B Data input  
Video Input 1 Port B Data input  
Video Input 1 Port B Data input  
Video Input 1 Port B Data input  
Video Input 1 Port B Data input  
Video Input 1 Port B Data input  
Video Input 1 Port B Field ID input  
Video Input 1 Port B Horizontal Sync input  
Video Input 1 Port B Vertical Sync input  
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
K22  
K21  
vin1a_d10  
vin1a_d11  
vin1a_d12  
vin1a_d13  
vin1a_d14  
vin1a_d15  
vin1a_de0  
vin1a_fld0  
vin1a_hsync0  
vin1a_vsync0  
vin1b_clk1  
vin1b_d0  
K18  
AB17, K17  
K19, U17  
K20, W17  
AA17, L21  
F19, F21  
F20  
F19  
G19  
F21  
J17  
vin1b_d1  
K22  
vin1b_d2  
K21  
vin1b_d3  
K18  
vin1b_d4  
K17  
vin1b_d5  
K19  
vin1b_d6  
K20  
vin1b_d7  
L21  
vin1b_de1  
vin1b_hsync1  
vin1b_vsync1  
Video Input 2  
vin2a_clk0  
vin2a_d0  
W7  
W7  
W6  
Video Input 2 Port A Clock input  
Video Input 2 Port A Data input  
Video Input 2 Port A Data input  
Video Input 2 Port A Data input  
Video Input 2 Port A Data input  
Video Input 2 Port A Data input  
Video Input 2 Port A Data input  
Video Input 2 Port A Data input  
Video Input 2 Port A Data input  
Video Input 2 Port A Data input  
Video Input 2 Port A Data input  
Video Input 2 Port A Data input  
Video Input 2 Port A Data input  
Video Input 2 Port A Data input  
Video Input 2 Port A Data input  
Video Input 2 Port A Data input  
Video Input 2 Port A Data input  
Video Input 2 Port A Field ID input  
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
AB17, L22, W15  
AA14  
AB14  
U13  
V13  
Y13  
W13  
U11  
V11  
U9  
vin2a_d1  
vin2a_d2  
vin2a_d3  
vin2a_d4  
vin2a_d5  
vin2a_d6  
vin2a_d7  
vin2a_d8  
vin2a_d9  
W11  
V9  
vin2a_d10  
vin2a_d11  
vin2a_d12  
vin2a_d13  
vin2a_d14  
vin2a_d15  
vin2a_de0  
W9  
U8  
W8  
U7  
V7  
AA15, AA17, M17,  
W7  
vin2a_fld0  
vin2a_hsync0  
vin2a_vsync0  
vin2b_clk1  
Video Input 2 Port A Field ID input  
Video Input 2 Port A Horizontal Sync input  
Video Input 2 Port A Vertical Sync input  
Video Input 2 Port B Clock input  
I
I
I
I
I
AB15, M18, U16  
F14, F15, W7  
C14, F16, W6  
F20  
vin2b_d0  
Video Input 2 Port B Data input  
U9  
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Table 4-4. VIP Signal Descriptions (continued)  
SIGNAL NAME  
DESCRIPTION  
TYPE  
BALL  
W11  
V9  
vin2b_d1  
vin2b_d2  
Video Input 2 Port B Data input  
Video Input 2 Port B Data input  
Video Input 2 Port B Data input  
Video Input 2 Port B Data input  
Video Input 2 Port B Data input  
Video Input 2 Port B Data input  
Video Input 2 Port B Data input  
Video Input 2 Port B Field ID input  
Video Input 2 Port B Horizontal Sync input  
Video Input 2 Port B Vertical Sync input  
I
I
I
I
I
I
I
I
I
I
vin2b_d3  
W9  
vin2b_d4  
U8  
vin2b_d5  
W8  
vin2b_d6  
U7  
vin2b_d7  
V7  
vin2b_de1  
vin2b_hsync1  
vin2b_vsync1  
M17  
M17  
M18  
4.4.2 Display Subsystem – Video Output Ports  
Table 4-5. DSS Signal Descriptions  
SIGNAL NAME  
DPI Video Output 1  
vout1_clk  
DESCRIPTION  
TYPE  
BALL  
Video Output 1 Clock output  
Video Output 1 Data output  
Video Output 1 Data output  
Video Output 1 Data output  
Video Output 1 Data output  
Video Output 1 Data output  
Video Output 1 Data output  
Video Output 1 Data output  
Video Output 1 Data output  
Video Output 1 Data output  
Video Output 1 Data output  
Video Output 1 Data output  
Video Output 1 Data output  
Video Output 1 Data output  
Video Output 1 Data output  
Video Output 1 Data output  
Video Output 1 Data output  
Video Output 1 Data output  
Video Output 1 Data output  
Video Output 1 Data output  
Video Output 1 Data output  
Video Output 1 Data output  
Video Output 1 Data output  
Video Output 1 Data output  
Video Output 1 Data output  
Video Output 1 Data Enable output  
Video Output 1 Field ID output. This signal is not used for embedded sync modes.  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
AB17  
W16  
V16  
U15  
V15  
Y15  
W15  
AA15  
AB15  
AA14  
AB14  
U13  
V13  
Y13  
W13  
U11  
V11  
U9  
vout1_d0  
vout1_d1  
vout1_d2  
vout1_d3  
vout1_d4  
vout1_d5  
vout1_d6  
vout1_d7  
vout1_d8  
vout1_d9  
vout1_d10  
vout1_d11  
vout1_d12  
vout1_d13  
vout1_d14  
vout1_d15  
vout1_d16  
vout1_d17  
vout1_d18  
vout1_d19  
vout1_d20  
vout1_d21  
vout1_d22  
vout1_d23  
vout1_de  
W11  
V9  
W9  
U8  
W8  
U7  
V7  
U17  
W17  
AA17  
vout1_fld  
vout1_hsync  
Video Output 1 Horizontal Sync output. This signal is not used for embedded sync  
modes.  
vout1_vsync  
Video Output 1 Vertical Sync output. This signal is not used for embedded sync modes.  
O
U16  
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4.4.3 Digital-to-Analog Converter (SD_DAC)  
NOTE  
For more information, see Video Encoder Overview in the device TRM.  
Table 4-6. CVIDEO SD_DAC Signal Descriptions  
SIGNAL NAME  
cvideo_tvout  
cvideo_vfb  
DESCRIPTION  
TYPE  
BALL  
SD_DAC TV analog composite output  
SD_DAC input feedback thru resistor to out  
SD_DAC input reference current resistor setting  
A
A
A
T17  
P17  
T18  
cvideo_rset  
4.4.4 Embedded 8 channel Analog-To-Digital Converter (ADC)  
NOTE  
For more information, see the ADC Overview in the device TRM.  
Table 4-7. ADC Signal Descriptions  
SIGNAL NAME  
adc_in0  
DESCRIPTION  
TYPE  
BALL  
M19  
M20  
M21  
M22  
N22  
N21  
P19  
P18  
P20  
ADC analog channel input 0  
ADC analog channel input 1  
ADC analog channel input 2  
ADC analog channel input 3  
ADC analog channel input 4  
ADC analog channel input 5  
ADC analog channel input 6  
ADC analog channel input 7  
ADC positive reference voltage  
A
A
A
A
A
A
A
A
A
adc_in1  
adc_in2  
adc_in3  
adc_in4  
adc_in5  
adc_in6  
adc_in7  
adc_vrefp  
4.4.5 Camera Control  
NOTE  
For more information, see the Imaging Subsystem (ISS) section in the device TRM.  
Table 4-8. Camera Control Signal Descriptions  
SIGNAL NAME  
cam_strobe  
cam_shutter  
cam_nreset  
DESCRIPTION  
TYPE  
BALL  
A6, B18, C16, M17  
C6, C18, C17, M18  
W6  
Camera flash activation trigger  
Camera mechanical shutter control  
Camera sensor reset  
O
O
IO  
4.4.6 Camera Parallel Interface (CPI)  
Table 4-9. CPI Signal Descriptions  
SIGNAL NAME  
cpi_pclk  
DESCRIPTION  
TYPE  
BALL  
F22  
Camera pixel clock  
I
cpi_hsync  
cpi_vsync  
cpi_data0  
Camera horizontal synchonization  
Camera vertical synchonization  
Camera parallel data 0  
IO  
IO  
I
F21  
F20  
F19  
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Table 4-9. CPI Signal Descriptions (continued)  
SIGNAL NAME  
cpi_data1  
cpi_data2  
cpi_data3  
cpi_data4  
cpi_data5  
cpi_data6  
cpi_data7  
cpi_data8  
cpi_data9  
cpi_data10  
cpi_data11  
cpi_data12  
cpi_data13  
cpi_data14  
cpi_data15  
cpi_wen  
DESCRIPTION  
TYPE  
BALL  
G19  
G18  
G21  
G22  
H18  
H20  
H19  
H22  
H21  
J17  
Camera parallel data 1  
I
I
Camera parallel data 2  
Camera parallel data 3  
I
Camera parallel data 4  
I
Camera parallel data 5  
I
Camera parallel data 6  
I
Camera parallel data 7  
I
Camera parallel data 8  
I
Camera parallel data 9  
I
Camera parallel data 10  
I
Camera parallel data 11  
I
K22  
K21  
K18  
K17  
L21  
Camera parallel data 12  
I
Camera parallel data 13  
I
Camera parallel data 14  
I
Camera parallel data 15  
I
Camera parallel external write enable  
Camera parallel field identification for interlaced sensors (i mode)  
I
K19  
K20  
cpi_fid  
IO  
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4.4.7 Imaging Subsystem (ISS)  
NOTE  
For more information, see the Imaging Subsystem in the device TRM.  
CAUTION  
The IO timings provided in Section 7 Timing Requirements and Switching  
Characteristics are only valid if signals within a single IOSET are used. The  
IOSETs are defined in Table 7-6.  
Table 4-10. CSI 2 Signal Descriptions  
SIGNAL NAME  
csi2_0_dx0  
csi2_0_dy0  
csi2_0_dx1  
csi2_0_dy1  
csi2_0_dx2  
csi2_0_dy2  
csi2_0_dx3  
csi2_0_dy3  
csi2_0_dx4  
csi2_0_dy4  
DESCRIPTION  
TYPE  
BALL  
Serial Differential data/clock positive input - lane 0 (position 1)  
Serial Differential data/clock negative input - lane 0 (position 1)  
Serial Differential data/clock positive input - lane 1 (position 2)  
Serial Differential data/clock negative input - lane 1 (position 2)  
Serial Differential data/clock positive input - lane 2 (position 3)  
Serial Differential data/clock negative input - lane 2 (position 3)  
Serial Differential data/clock positive input - lane 3 (position 4)  
Serial Differential data/clock negative input - lane 3 (position 4)  
Serial Differential data positive input only - lane 4 (position 5) (1)  
Serial Differential data negative input only - lane 4 (position 5) (1)  
I
I
I
I
I
I
I
I
I
I
A11  
B11  
A12  
B12  
A13  
B13  
A15  
B15  
A16  
B16  
(1) Lane 4 (position 5) supports only data. For more information, see the Imaging Subsystem in the device TRM.  
4.4.8 External Memory Interface (EMIF)  
NOTE  
For more information, see the EMIF Controller section in the device TRM.  
NOTE  
The index number 1 which is part of the EMIF1 signal prefixes (ddr1_*) listed in Table 4-11,  
EMIF Signal Descriptions, column "SIGNAL NAME" is not to be confused with DDR1 type of  
SDRAM memories.  
Table 4-11. EMIF Signal Descriptions  
SIGNAL NAME DESCRIPTION  
TYPE  
O
BALL  
F3  
ddr1_cke0  
ddr1_nck  
ddr1_odt0  
ddr1_rasn  
EMIF1 Clock Enable 0  
EMIF1 Negative Clock  
O
G2  
EMIF1 On-Die Termination for Chip Select 0  
O
P2  
EMIF1 Row Address Strobe; When LPDDR2 is used this signal functions as to  
ddr1_ca0  
O
F1  
ddr1_rst  
ddr1_wen  
ddr1_csn0  
ddr1_ck  
EMIF1 Reset output  
O
O
O
O
O
N1  
E3  
B2  
G1  
F2  
EMIF1 Write Enable; When LPDDR2 is used this signal functions as ddr1_ca2  
EMIF1 Chip Select 0  
EMIF1 Clock  
ddr1_casn  
EMIF1 Column Address Strobe; When LPDDR2 is used this signal functions as  
ddr1_ca1  
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Table 4-11. EMIF Signal Descriptions (continued)  
SIGNAL NAME DESCRIPTION  
TYPE  
O
BALL  
B3  
ddr1_ba0  
ddr1_ba1  
ddr1_ba2  
ddr1_a0  
ddr1_a1  
ddr1_a2  
ddr1_a3  
ddr1_a4  
ddr1_a5  
ddr1_a6  
ddr1_a7  
ddr1_a8  
ddr1_a9  
ddr1_a10  
ddr1_a11  
ddr1_a12  
ddr1_a13  
ddr1_a14  
ddr1_a15  
ddr1_d0  
ddr1_d1  
ddr1_d2  
ddr1_d3  
ddr1_d4  
ddr1_d5  
ddr1_d6  
ddr1_d7  
ddr1_d8  
ddr1_d9  
ddr1_d10  
ddr1_d11  
ddr1_d12  
ddr1_d13  
ddr1_d14  
ddr1_d15  
ddr1_d16  
ddr1_d17  
ddr1_d18  
ddr1_d19  
ddr1_d20  
ddr1_d21  
ddr1_d22  
ddr1_d23  
ddr1_d24  
ddr1_d25  
ddr1_d26  
ddr1_d27  
EMIF1 Bank Address; When LPDDR2 is used this signal functions as ddr1_ca7  
EMIF1 Bank Address; When LPDDR2 is used this signal functions as ddr1_ca8  
O
A3  
EMIF1 Bank Address; When LPDDR2 is used this signal functions as ddr1_ca9  
O
D2  
EMIF1 Address Bus  
O
U4  
EMIF1 Address Bus; When LPDDR2 is used this signal functions as ddr1_ca5  
O
C1  
EMIF1 Address Bus; When LPDDR2 is used this signal functions as ddr1_ca6  
O
D3  
EMIF1 Address Bus  
EMIF1 Address Bus  
EMIF1 Address Bus  
EMIF1 Address Bus  
EMIF1 Address Bus  
EMIF1 Address Bus  
EMIF1 Address Bus  
EMIF1 Address Bus; When LPDDR2 is used this signal functions as ddr1_ca4  
EMIF1 Address Bus  
EMIF1 Address Bus  
EMIF1 Address Bus; When LPDDR2 is used this signal functions as ddr1_ca3  
EMIF1 Address Bus  
EMIF1 Address Bus  
EMIF1 Data Bus  
O
R4  
O
T4  
O
N3  
O
T2  
O
N2  
O
T1  
O
U1  
O
D1  
O
R3  
O
U2  
O
C3  
O
R2  
O
V1  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
AA6  
AA8  
Y8  
EMIF1 Data Bus  
EMIF1 Data Bus  
EMIF1 Data Bus  
AA7  
AB4  
Y5  
EMIF1 Data Bus  
EMIF1 Data Bus  
EMIF1 Data Bus  
AA4  
Y6  
EMIF1 Data Bus  
EMIF1 Data Bus  
AA18  
Y21  
AA21  
Y22  
AA19  
AB20  
Y17  
AB18  
AA3  
AA2  
Y3  
EMIF1 Data Bus  
EMIF1 Data Bus  
EMIF1 Data Bus  
EMIF1 Data Bus  
EMIF1 Data Bus  
EMIF1 Data Bus  
EMIF1 Data Bus  
EMIF1 Data Bus  
EMIF1 Data Bus  
EMIF1 Data Bus  
EMIF1 Data Bus  
V2  
EMIF1 Data Bus  
U3  
EMIF1 Data Bus  
V3  
EMIF1 Data Bus  
Y2  
EMIF1 Data Bus  
Y1  
EMIF1 Data Bus  
U21  
T20  
R21  
U20  
EMIF1 Data Bus  
EMIF1 Data Bus  
EMIF1 Data Bus  
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Table 4-11. EMIF Signal Descriptions (continued)  
SIGNAL NAME DESCRIPTION  
TYPE  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
BALL  
ddr1_d28  
ddr1_d29  
EMIF1 Data Bus  
R22  
V20  
EMIF1 Data Bus  
ddr1_d30  
EMIF1 Data Bus  
W22  
U22  
Y11  
ddr1_d31  
EMIF1 Data Bus  
ddr1_ecc_d0  
ddr1_ecc_d1  
ddr1_ecc_d2  
ddr1_ecc_d3  
ddr1_ecc_d4  
ddr1_ecc_d5  
ddr1_ecc_d6  
ddr1_ecc_d7  
ddr1_dqm0  
ddr1_dqm1  
ddr1_dqm2  
ddr1_dqm3  
ddr1_dqm_ecc  
ddr1_dqs0  
EMIF1 ECC Data Bus  
EMIF1 ECC Data Bus  
EMIF1 ECC Data Bus  
EMIF1 ECC Data Bus  
EMIF1 ECC Data Bus  
EMIF1 ECC Data Bus  
EMIF1 ECC Data Bus  
EMIF1 ECC Data Bus  
EMIF1 Data Mask  
AA12  
AA11  
Y9  
AA13  
AB11  
AA9  
AB9  
AB8  
Y18  
EMIF1 Data Mask  
EMIF1 Data Mask  
AB3  
W21  
AB13  
AA5  
EMIF1 Data Mask  
EMIF1 ECC Data Mask  
Data strobe 0 input/output for byte 0 of the 32-bit data bus. This signal is output to the  
EMIF1 memory when writing and input when reading.  
ddr1_dqs1  
ddr1_dqs2  
ddr1_dqs3  
Data strobe 1 input/output for byte 1 of the 32-bit data bus. This signal is output to the  
EMIF1 memory when writing and input when reading.  
IO  
IO  
IO  
AA20  
W1  
Data strobe 2 input/output for byte 2 of the 32-bit data bus. This signal is output to the  
EMIF1 memory when writing and input when reading.  
Data strobe 3 input/output for byte 3 of the 32-bit data bus. This signal is output to the  
EMIF1 memory when writing and input when reading.  
T21  
ddr1_dqsn0  
ddr1_dqsn1  
ddr1_dqsn2  
ddr1_dqsn3  
Data strobe 0 invert  
Data strobe 1 invert  
Data strobe 2 invert  
Data strobe 3 invert  
IO  
IO  
IO  
IO  
IO  
IO  
AB5  
Y20  
W2  
T22  
ddr1_dqsn_ecc EMIF1 ECC Complementary Data strobe  
ddr1_dqs_ecc EMIF1 ECC Data strobe input/output. This signal is output to the EMIF1 memory when  
writing and input when reading.  
AB10  
AA10  
4.4.9 General-Purpose Memory Controller (GPMC)  
NOTE  
For more information, see the General-Purpose Memory Controller section in the device  
TRM.  
Table 4-12. GPMC Signal Descriptions  
SIGNAL NAME  
DESCRIPTION  
TYPE  
BALL  
gpmc_ad0  
GPMC Data 0 in A/D nonmultiplexed mode and additionally Address 1  
in A/D multiplexed mode  
IO  
E8  
A7  
F8  
B7  
gpmc_ad1  
gpmc_ad2  
gpmc_ad3  
GPMC Data 1 in A/D nonmultiplexed mode and additionally Address 2  
in A/D multiplexed mode  
IO  
IO  
IO  
GPMC Data 2 in A/D nonmultiplexed mode and additionally Address 3  
in A/D multiplexed mode  
GPMC Data 3 in A/D nonmultiplexed mode and additionally Address 4  
in A/D multiplexed mode  
58  
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Table 4-12. GPMC Signal Descriptions (continued)  
SIGNAL NAME  
DESCRIPTION  
TYPE  
BALL  
gpmc_ad4  
gpmc_ad5  
gpmc_ad6  
gpmc_ad7  
gpmc_ad8  
gpmc_ad9  
gpmc_ad10  
gpmc_ad11  
gpmc_ad12  
gpmc_ad13  
gpmc_ad14  
gpmc_ad15  
gpmc_a0  
GPMC Data 4 in A/D nonmultiplexed mode and additionally Address 5  
in A/D multiplexed mode  
IO  
A6  
GPMC Data 5 in A/D nonmultiplexed mode and additionally Address 6  
in A/D multiplexed mode  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
O
F7  
GPMC Data 6 in A/D nonmultiplexed mode and additionally Address 7  
in A/D multiplexed mode  
E7  
GPMC Data 7 in A/D nonmultiplexed mode and additionally Address 8  
in A/D multiplexed mode  
C6  
GPMC Data 8 in A/D nonmultiplexed mode and additionally Address 9  
in A/D multiplexed mode  
B6  
GPMC Data 9 in A/D nonmultiplexed mode and additionally Address 10  
in A/D multiplexed mode  
A5  
GPMC Data 10 in A/D nonmultiplexed mode and additionally Address  
11 in A/D multiplexed mode  
D6  
GPMC Data 11 in A/D nonmultiplexed mode and additionally Address  
12 in A/D multiplexed mode  
C5  
GPMC Data 12 in A/D nonmultiplexed mode and additionally Address  
13 in A/D multiplexed mode  
B5  
GPMC Data 13 in A/D nonmultiplexed mode and additionally Address  
14 in A/D multiplexed mode  
D7  
GPMC Data 14 in A/D nonmultiplexed mode and additionally Address  
15 in A/D multiplexed mode  
B4  
GPMC Data 15 in A/D nonmultiplexed mode and additionally Address  
16 in A/D multiplexed mode  
A4  
GPMC Address 0. Only used to effectively address 8-bit data  
nonmultiplexed memories  
U9  
gpmc_a1  
GPMC address 1 in A/D nonmultiplexed mode and Address 17 in A/D  
multiplexed mode  
O
W11  
gpmc_a2  
GPMC address 2 in A/D nonmultiplexed mode and Address 18 in A/D  
multiplexed mode  
O
V9  
gpmc_a3  
GPMC address 3 in A/D nonmultiplexed mode and Address 19 in A/D  
multiplexed mode  
O
W9  
gpmc_a4  
GPMC address 4 in A/D nonmultiplexed mode and Address 20 in A/D  
multiplexed mode  
O
U8  
gpmc_a5  
GPMC address 5 in A/D nonmultiplexed mode and Address 21 in A/D  
multiplexed mode  
O
W8  
gpmc_a6  
GPMC address 6 in A/D nonmultiplexed mode and Address 22 in A/D  
multiplexed mode  
O
U7  
gpmc_a7  
GPMC address 7 in A/D nonmultiplexed mode and Address 23 in A/D  
multiplexed mode  
O
V7  
gpmc_a8  
GPMC address 8 in A/D nonmultiplexed mode and Address 24 in A/D  
multiplexed mode  
O
J17  
gpmc_a9  
GPMC address 9 in A/D nonmultiplexed mode and Address 25 in A/D  
multiplexed mode  
O
K22  
gpmc_a10  
gpmc_a11  
gpmc_a12  
gpmc_a13  
gpmc_a14  
gpmc_a15  
GPMC address 10 in A/D nonmultiplexed mode and Address 26 in A/D  
multiplexed mode  
O
K21  
GPMC address 11 in A/D nonmultiplexed mode and unused in A/D  
multiplexed mode  
O
K18  
D14, F13, F14, K17  
C14, D15, E14, K19  
K20  
GPMC address 12 in A/D nonmultiplexed mode and unused in A/D  
multiplexed mode  
O
GPMC address 13 in A/D nonmultiplexed mode and unused in A/D  
multiplexed mode  
O
GPMC address 14 in A/D nonmultiplexed mode and unused in A/D  
multiplexed mode  
O
GPMC address 15 in A/D nonmultiplexed mode and unused in A/D  
multiplexed mode  
O
L21  
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Table 4-12. GPMC Signal Descriptions (continued)  
SIGNAL NAME  
DESCRIPTION  
TYPE  
BALL  
gpmc_a16  
GPMC address 16 in A/D nonmultiplexed mode and unused in A/D  
multiplexed mode  
O
F14  
C14  
F15  
gpmc_a17  
gpmc_a18  
gpmc_a19  
gpmc_a20  
gpmc_a21  
gpmc_a22  
gpmc_a23  
gpmc_a24  
gpmc_a25  
gpmc_a26  
gpmc_a27  
GPMC address 17 in A/D nonmultiplexed mode and unused in A/D  
multiplexed mode  
O
O
O
O
O
O
O
O
O
O
O
GPMC address 18 in A/D nonmultiplexed mode and unused in A/D  
multiplexed mode  
GPMC address 19 in A/D nonmultiplexed mode and unused in A/D  
multiplexed mode  
F16  
GPMC address 20 in A/D nonmultiplexed mode and unused in A/D  
multiplexed mode  
AA14  
AB14  
U13  
V13  
Y13  
W13  
U11  
V11  
GPMC address 21 in A/D nonmultiplexed mode and unused in A/D  
multiplexed mode  
GPMC address 22 in A/D nonmultiplexed mode and unused in A/D  
multiplexed mode  
GPMC address 23 in A/D nonmultiplexed mode and unused in A/D  
multiplexed mode  
GPMC address 24 in A/D nonmultiplexed mode and unused in A/D  
multiplexed mode  
GPMC address 25 in A/D nonmultiplexed mode and unused in A/D  
multiplexed mode  
GPMC address 26 in A/D nonmultiplexed mode and unused in A/D  
multiplexed mode  
GPMC address 27 in A/D nonmultiplexed mode and Address 27 in A/D  
multiplexed mode  
gpmc_cs0  
gpmc_cs1  
GPMC Chip Select 0 (active low)  
GPMC Chip Select 1 (active low)  
GPMC Chip Select 2 (active low)  
GPMC Chip Select 3 (active low)  
GPMC Chip Select 4 (active low)  
GPMC Chip Select 5 (active low)  
GPMC Chip Select 6 (active low)  
GPMC Chip Select 7 (active low)  
GPMC Clock output  
O
O
O
O
O
O
O
O
IO  
O
O
O
O
O
I
C10  
E10  
gpmc_cs2  
D10  
gpmc_cs3  
A9  
gpmc_cs4  
B9  
gpmc_cs5  
F10  
gpmc_cs6  
C8  
gpmc_cs7  
W6  
gpmc_clk(1)  
gpmc_advn_ale  
gpmc_oen_ren  
gpmc_wen  
gpmc_ben0  
gpmc_ben1  
gpmc_wait0  
gpmc_wait1  
C12, D14, F14, F15  
GPMC address valid active low or address latch enable  
GPMC output enable active low or read enable  
GPMC write enable active low  
F12  
A10  
B10  
D12  
E12  
D8  
GPMC lower-byte enable active low  
GPMC upper-byte enable active low  
GPMC external indication of wait 0  
GPMC external indication of wait 1  
I
W7  
(1) The gpio6_16.clkout0 signal can be used as an “always-on” alternative to gpmc_clk provided that the external device can support the  
associated timing. See Table 7-8, GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - 1 Load and Table 7-10,  
GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - 5 Loads for timing information.  
4.4.10 Timers  
NOTE  
For more information, see the Timers section in the device TRM.  
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Table 4-13. Timers Signal Descriptions  
SIGNAL NAME  
timer1  
DESCRIPTION  
TYPE  
IO  
BALL  
D14, R7  
D15, D6  
C5, F14, L1  
C14, C6, L2  
E7, N4  
PWM output/event trigger input  
PWM output/event trigger input  
PWM output/event trigger input  
PWM output/event trigger input  
PWM output/event trigger input  
PWM output/event trigger input  
PWM output/event trigger input  
PWM output/event trigger input  
timer2  
IO  
timer3  
IO  
timer4  
IO  
timer5  
IO  
timer6  
IO  
F7, R5  
timer7  
IO  
B6, F15  
F16  
timer8  
IO  
4.4.11 Inter-Integrated Circuit Interface (I2C)  
NOTE  
For more information, see the I2C Pins for Typical Connections in I2C Mode section in the  
device TRM.  
Table 4-14. I2C Signal Descriptions  
SIGNAL NAME  
DESCRIPTION  
TYPE  
BALL  
Inter-Integrated Circuit Interface (I2C1)  
i2c1_scl  
I2C1 Clock  
I2C1 Data  
IOD  
IOD  
L3  
L4  
i2c1_sda  
Inter-Integrated Circuit Interface (I2C2)  
i2c2_scl  
I2C2 Clock  
I2C2 Data  
IOD  
IOD  
L6  
L5  
i2c2_sda  
4.4.12 Universal Asynchronous Receiver Transmitter (UART)  
NOTE  
For more information, see the UART section in the device TRM.  
CAUTION  
The IO timings provided in Section 7, Timing Requirements and Switching  
Characteristics are only valid if signals within a single IOSET are used. The  
IOSETs are defined in Table 7-19.  
Table 4-15. UART Signal Descriptions  
SIGNAL NAME  
DESCRIPTION  
TYPE  
BALL  
Universal Asynchronous Receiver/Transmitter (UART1)  
uart1_ctsn  
uart1_rtsn  
uart1_rxd  
uart1_txd  
UART1 clear to send active low  
UART1 request to send active low  
UART1 Receive Data  
I
F14  
C14  
F13  
E14  
O
I
UART1 Transmit Data  
O
Universal Asynchronous Receiver/Transmitter (UART2)  
uart2_ctsn  
uart2_rtsn  
uart2_rxd  
UART2 clear to send active low  
UART2 request to send active low  
UART2 Receive Data  
I
O
I
F15  
F16  
D14, E7  
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Table 4-15. UART Signal Descriptions (continued)  
SIGNAL NAME  
DESCRIPTION  
UART2 Transmit Data  
TYPE  
BALL  
uart2_txd  
O
D15, F7  
Universal Asynchronous Receiver/Transmitter (UART3)  
uart3_ctsn  
uart3_rtsn  
uart3_rxd  
uart3_txd  
UART3 clear to send active low  
UART3 request to send active low  
UART3 Receive Data  
I
N4, U6  
R7, T5  
O
I
F14, L1, M2, W7  
C14, L2, R6, W6  
UART3 Transmit Data  
O
4.4.13 Multichannel Serial Peripheral Interface (McSPI)  
NOTE  
For more information, see the Multichannel Serial Peripheral Interface (McSPI) section in the  
device TRM.  
CAUTION  
The IO timings provided in Section 7, Timing Requirements and Switching  
Characteristics are applicable for all combinations of signals for SPI2 and SPI4.  
However, the timings are only valid for SPI1 and SPI3 if signals within a single  
IOSET are used. The IOSETs are defined in Table 7-22.  
Table 4-16. SPI Signal Descriptions  
SIGNAL NAME  
DESCRIPTION  
TYPE  
BALL  
Serial Peripheral Interface 1  
spi1_sclk  
spi1_d0  
spi1_d1  
spi1_cs0  
spi1_cs1  
spi1_cs2  
spi1_cs3  
SPI1 Clock  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
M2  
T5  
SPI1 Data. Can be configured as either MISO or MOSI.  
SPI1 Data. Can be configured as either MISO or MOSI.  
SPI1 Chip Select  
U6  
M1, R6  
M1, R5  
F14, W7  
C14, W6  
SPI1 Chip Select  
SPI1 Chip Select  
SPI1 Chip Select  
Serial Peripheral Interface 2  
spi2_sclk  
spi2_d0  
spi2_d1  
spi2_cs0  
spi2_cs1  
SPI2 Clock  
IO  
IO  
IO  
IO  
IO  
L1  
R7  
SPI2 Data. Can be configured as either MISO or MOSI.  
SPI2 Data. Can be configured as either MISO or MOSI.  
SPI2 Chip Select  
N4  
A4, L2  
B4, M1  
SPI2 Chip Select  
Serial Peripheral Interface 3  
spi3_sclk  
spi3_d0  
spi3_d1  
spi3_cs0  
spi3_cs1  
SPI3 Clock  
IO  
IO  
IO  
IO  
IO  
C6, F15  
D15, E7  
SPI3 Data. Can be configured as either MISO or MOSI.  
SPI3 Data. Can be configured as either MISO or MOSI.  
SPI3 Chip Select  
D14, F7  
B6, F16, M1  
A5, R5  
SPI3 Chip Select  
Serial Peripheral Interface 4  
spi4_sclk  
spi4_d0  
spi4_d1  
SPI4 Clock  
IO  
IO  
IO  
C16, F14  
B17, E14  
B19, F13  
SPI4 Data. Can be configured as either MISO or MOSI.  
SPI4 Data. Can be configured as either MISO or MOSI.  
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Table 4-16. SPI Signal Descriptions (continued)  
SIGNAL NAME  
spi4_cs0  
DESCRIPTION  
SPI4 Chip Select  
TYPE  
BALL  
IO  
C14, C17  
4.4.14 Quad Serial Peripheral Interface (QSPI)  
NOTE  
For more information, see the Quad Serial Peripheral Interface section in the device TRM.  
CAUTION  
The IO timings provided in Section 7, Timing Requirements and Switching  
Characteristics are only valid if signals within a single IOSET are used. The  
IOSETs are defined in Table 7-25.  
Table 4-17. QSPI Signal Descriptions  
SIGNAL NAME  
qspi1_sclk  
DESCRIPTION  
TYPE  
BALL  
C8  
QSPI1 Serial Clock  
O
I
qspi1_rtclk  
QSPI1 Return Clock Input. Must be connected from QSPI1_SCLK on PCB. Refer  
to PCB Guidelines for QSPI1  
B7, C14, D8, F13  
qspi1_d0  
QSPI1 Data[0]. This pin is output data for all commands/writes and for dual read  
and quad read modes it becomes input data pin during read phase.  
IO  
B9  
qspi1_d1  
qspi1_d2  
QSPI1 Data[1]. Input read data in all modes.  
IO  
IO  
F10  
A9  
QSPI1 Data[2]. This pin is used only in quad read mode as input data pin during  
read phase  
qspi1_d3  
QSPI1 Data[3]. This pin is used only in quad read mode as input data pin during  
read phase  
IO  
D10  
qspi1_cs0  
qspi1_cs1  
QSPI1 Chip Select[0]. This pin is used for QSPI1 boot modes.  
QSPI1 Chip Select[1]  
IO  
IO  
E10  
F15  
4.4.15 Multichannel Audio Serial Port (McASP)  
NOTE  
For more information, see the Multichannel Audio Serial Port (McASP) section in the device  
TRM.  
CAUTION  
The IO timings provided in Section 7, Timing Requirements and Switching  
Characteristics are only valid if signals within a single IOSET are used. The  
IOSETs are defined in Table 7-32.  
Table 4-18. McASP Signal Descriptions  
SIGNAL NAME  
DESCRIPTION  
TYPE  
BALL  
Multichannel Audio Serial Port 1  
mcasp1_axr0  
mcasp1_axr1  
mcasp1_axr2  
McASP1 Transmit/Receive Data  
IO  
IO  
IO  
W16  
V16  
U15  
McASP1 Transmit/Receive Data  
McASP1 Transmit/Receive Data  
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Table 4-18. McASP Signal Descriptions (continued)  
SIGNAL NAME  
mcasp1_axr3  
mcasp1_axr4  
mcasp1_axr5  
mcasp1_axr6  
mcasp1_axr7  
mcasp1_axr8  
mcasp1_axr9  
mcasp1_axr10  
mcasp1_axr11  
mcasp1_axr12  
mcasp1_axr13  
mcasp1_axr14  
mcasp1_axr15  
mcasp1_fsx  
DESCRIPTION  
TYPE  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
O
BALL  
McASP1 Transmit/Receive Data  
McASP1 Transmit/Receive Data  
McASP1 Transmit/Receive Data  
McASP1 Transmit/Receive Data  
McASP1 Transmit/Receive Data  
McASP1 Transmit/Receive Data  
McASP1 Transmit/Receive Data  
McASP1 Transmit/Receive Data  
McASP1 Transmit/Receive Data  
McASP1 Transmit/Receive Data  
McASP1 Transmit/Receive Data  
McASP1 Transmit/Receive Data  
McASP1 Transmit/Receive Data  
McASP1 Transmit Frame Sync  
McASP1 Receive Bit Clock  
V15  
Y15  
W15  
AA15  
AB15  
AA14, U15, U9  
AB14, V15, W11  
U13, V9, Y15  
V13, W15, W9  
AA15, U8, Y13  
AB15, W13, W8  
U11, U7  
V11, V7  
W17  
mcasp1_aclkr  
mcasp1_fsr  
AA17  
McASP1 Receive Frame Sync  
McASP1 Transmit High-Frequency Master Clock  
McASP1 Transmit Bit Clock  
U16  
mcasp1_ahclkx  
mcasp1_aclkx  
U9  
IO  
U17  
Multichannel Audio Serial Port 2  
mcasp2_axr0  
mcasp2_axr1  
mcasp2_axr2  
mcasp2_axr3  
mcasp2_axr4  
mcasp2_axr5  
mcasp2_fsx  
McASP2 Transmit/Receive Data  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
O
D6, V9  
C5, W9  
B5, U8  
McASP2 Transmit/Receive Data  
McASP2 Transmit/Receive Data  
McASP2 Transmit/Receive Data  
McASP2 Transmit/Receive Data  
McASP2 Transmit/Receive Data  
McASP2 Transmit Frame Sync  
McASP2 Receive Bit Clock  
D7, W8  
B4, U7  
A4, V7  
E7, V11  
B6, W13  
A5, W11  
C6, Y13  
F7, U11  
mcasp2_aclkr  
mcasp2_fsr  
McASP2 Receive Frame Sync  
McASP2 Transmit High-Frequency Master Clock  
McASP2 Transmit Bit Clock  
mcasp2_ahclkx  
mcasp2_aclkx  
IO  
Multichannel Audio Serial Port 3  
mcasp3_axr0  
mcasp3_axr1  
mcasp3_axr2  
mcasp3_axr3  
mcasp3_axr4  
mcasp3_axr5  
mcasp3_fsx  
McASP3 Transmit/Receive Data  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
O
G19  
G18  
G21  
G22  
H18  
H20  
H22  
H19  
F22  
F20  
F19  
McASP3 Transmit/Receive Data  
McASP3 Transmit/Receive Data  
McASP3 Transmit/Receive Data  
McASP3 Transmit/Receive Data  
McASP3 Transmit/Receive Data  
McASP3 Transmit Frame Sync  
McASP3 Transmit High-Frequency Master Clock  
McASP3 Transmit Bit Clock  
mcasp3_ahclkx  
mcasp3_aclkx  
mcasp3_aclkr  
mcasp3_fsr  
IO  
IO  
IO  
McASP3 Receive Bit Clock  
McASP3 Receive Frame Sync  
4.4.16 Controller Area Network Interface (DCAN and MCAN)  
NOTE  
For more information, see the DCAN section in the device TRM.  
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CAUTION  
The IO timings provided in Section 7, Timing Requirements and Switching  
Characteristics are only valid if signals within a single IOSET are used. The  
IOSETs are defined in Table 7-36.  
Table 4-19. DCAN and MCAN Signal Descriptions  
SIGNAL NAME  
DCAN 1  
dcan1_rx  
DESCRIPTION  
TYPE  
BALL  
DCAN1 receive data pin  
DCAN1 transmit data pin  
IO  
IO  
C14, D15, N6  
D14, F14, N5  
dcan1_tx  
MCAN  
mcan_rx  
mcan_tx  
MCAN receive data pin  
MCAN transmit data pin  
IO  
IO  
E14, F16, W6  
F13, F15, W7  
4.4.17 Ethernet Interface (GMAC_SW)  
NOTE  
For more information, see the Gigabit Ethernet Switch (GMAC_SW) section in the device  
TRM.  
Table 4-20. GMAC Signal Descriptions  
SIGNAL NAME  
rgmii0_rxc  
DESCRIPTION  
TYPE  
BALL  
B18  
C18  
A20  
C20  
B20  
A19  
C16  
C17  
F17  
E17  
D16  
E16  
D7  
RGMII0 Receive Clock  
RGMII0 Receive Control  
RGMII0 Receive Data  
RGMII0 Receive Data  
RGMII0 Receive Data  
RGMII0 Receive Data  
RGMII0 Transmit Clock  
RGMII0 Transmit Enable  
RGMII0 Transmit Data  
RGMII0 Transmit Data  
RGMII0 Transmit Data  
RGMII0 Transmit Data  
RGMII1 Receive Clock  
RGMII1 Receive Control  
RGMII1 Receive Data  
RGMII1 Receive Data  
RGMII1 Receive Data  
RGMII1 Receive Data  
RGMII1 Transmit Clock  
RGMII1 Transmit Enable  
RGMII1 Transmit Data  
RGMII1 Transmit Data  
RGMII1 Transmit Data  
RGMII1 Transmit Data  
Management Data  
I
I
rgmii0_rxctl  
rgmii0_rxd0  
rgmii0_rxd1  
rgmii0_rxd2  
rgmii0_rxd3  
rgmii0_txc  
I
I
I
I
O
O
O
O
O
O
I
rgmii0_txctl  
rgmii0_txd0  
rgmii0_txd1  
rgmii0_txd2  
rgmii0_txd3  
rgmii1_rxc  
rgmii1_rxctl  
rgmii1_rxd0  
rgmii1_rxd1  
rgmii1_rxd2  
rgmii1_rxd3  
rgmii1_txc  
I
C10  
F8  
I
I
A7  
I
E8  
I
D8  
O
O
O
O
O
O
IO  
C12  
D12  
B10  
A10  
F12  
E12  
B17  
rgmii1_txctl  
rgmii1_txd0  
rgmii1_txd1  
rgmii1_txd2  
rgmii1_txd3  
mdio_d  
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Table 4-20. GMAC Signal Descriptions (continued)  
SIGNAL NAME  
DESCRIPTION  
Management Data Serial Clock  
TYPE  
BALL  
mdio_mclk  
O
B19  
4.4.18 SDIO Controller  
NOTE  
For more information, see the SDIO Controller section in the device TRM.  
CAUTION  
The IO timings provided in Section 7, Timing Requirements and Switching  
Characteristics are only valid if signals within a single IOSET are used. The  
IOSETs are defined in Table 7-51.  
Table 4-21. SDIO Controller Signal Descriptions  
SIGNAL NAME  
Multi Media Card 1  
mmc_clk  
DESCRIPTION  
TYPE  
BALL  
MMC1 clock  
IO  
IO  
IO  
IO  
IO  
IO  
B18, C16, W16  
C17, C18, V16  
A19, E16, U15  
B20, D16, V15  
C20, E17, Y15  
A20, F17, W15  
mmc_cmd  
MMC1 command  
MMC1 data bit 0  
MMC1 data bit 1  
MMC1 data bit 2  
MMC1 data bit 3  
mmc_dat0  
mmc_dat1  
mmc_dat2  
mmc_dat3  
4.4.19 General-Purpose Interface (GPIO)  
NOTE  
For more information, see the General-Purpose Interface section in the device TRM.  
CAUTION  
The IO timings provided in Section 7, Timing Requirements and Switching  
Characteristics are only valid if signals within a single IOSET are used. The  
IOSETs are defined in Table 7-52.  
Table 4-22. GPIOs Signal Descriptions  
SIGNAL NAME  
GPIO 1  
DESCRIPTION  
TYPE  
BALL  
gpio1_0  
gpio1_1  
gpio1_2  
gpio1_3  
gpio1_4  
gpio1_5  
gpio1_6  
gpio1_7  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
C12  
D12  
E12  
F12  
A10  
B10  
C10  
E10  
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Table 4-22. GPIOs Signal Descriptions (continued)  
SIGNAL NAME  
DESCRIPTION  
TYPE  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
BALL  
D10  
A9  
gpio1_8  
gpio1_9  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
gpio1_10  
gpio1_11  
gpio1_12  
gpio1_13  
gpio1_14  
gpio1_15  
gpio1_16  
gpio1_17  
gpio1_18  
gpio1_19  
gpio1_20  
gpio1_21  
gpio1_22  
gpio1_23  
gpio1_24  
gpio1_25  
gpio1_26  
gpio1_27  
gpio1_28  
gpio1_29  
gpio1_30  
gpio1_31  
B9  
F10  
C8  
D8  
E8  
A7  
F8  
B7  
A6  
F7  
E7  
C6  
B6  
A5  
D6  
C5  
B5  
D7  
B4  
A4  
F22  
F21  
GPIO 2  
gpio2_0  
gpio2_1  
gpio2_2  
gpio2_3  
gpio2_4  
gpio2_5  
gpio2_6  
gpio2_7  
gpio2_8  
gpio2_9  
gpio2_10  
gpio2_11  
gpio2_12  
gpio2_13  
gpio2_14  
gpio2_15  
gpio2_16  
gpio2_17  
gpio2_18  
gpio2_19  
gpio2_20  
gpio2_21  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
F20  
F19  
G19  
G18  
G21  
G22  
H18  
H20  
H19  
H22  
H21  
J17  
K22  
K21  
K18  
K17  
K19  
K20  
L21  
L22  
AB17  
U17  
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Table 4-22. GPIOs Signal Descriptions (continued)  
SIGNAL NAME  
gpio2_22  
gpio2_23  
gpio2_24  
gpio2_25  
gpio2_26  
gpio2_27  
gpio2_28  
gpio2_29  
gpio2_30  
gpio2_31  
DESCRIPTION  
TYPE  
IO  
BALL  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
W17  
AA17  
U16  
IO  
IO  
IO  
W16  
V16  
IO  
IO  
U15  
IO  
V15  
IO  
Y15  
IO  
W15  
AA15  
IO  
GPIO 3  
gpio3_0  
gpio3_1  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
AB15  
AA14  
AB14  
U13  
V13  
Y13  
W13  
U11  
V11  
U9  
gpio3_2  
gpio3_3  
gpio3_4  
gpio3_5  
gpio3_6  
gpio3_7  
gpio3_8  
gpio3_9  
gpio3_10  
gpio3_11  
gpio3_12  
gpio3_13  
gpio3_14  
gpio3_15  
gpio3_16  
gpio3_17  
gpio3_18  
gpio3_19  
gpio3_20  
gpio3_21  
gpio3_22  
gpio3_23  
gpio3_24  
gpio3_25  
gpio3_26  
gpio3_27  
gpio3_28  
gpio3_29  
gpio3_30  
gpio3_31  
W11  
V9  
W9  
U8  
W8  
U7  
V7  
B19  
B17  
C16  
C17  
E16  
D16  
E17  
F17  
B18  
C18  
A19  
B20  
C20  
A20  
M1  
GPIO 4  
gpio4_0  
gpio4_1  
gpio4_2  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
IO  
IO  
IO  
M2  
U6  
T5  
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Table 4-22. GPIOs Signal Descriptions (continued)  
SIGNAL NAME  
DESCRIPTION  
TYPE  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
BALL  
R6  
gpio4_3  
gpio4_4  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
General-Purpose Input/Output  
R5  
gpio4_5  
L1  
gpio4_6  
N4  
gpio4_7  
R7  
gpio4_8  
L2  
gpio4_9  
N5  
gpio4_10  
gpio4_11  
gpio4_12  
gpio4_13  
gpio4_14  
gpio4_15  
gpio4_16  
gpio4_17  
gpio4_18  
gpio4_19  
gpio4_20  
gpio4_21  
gpio4_22  
gpio4_25  
gpio4_26  
gpio4_27  
gpio4_28(1)  
gpio4_29(1)  
N6  
W7  
W6  
F13  
E14  
F14  
C14  
D14  
D15  
F15  
F16  
M17  
M18  
J1  
J4  
J6  
H1  
H2  
(1) gpio4_28 is multiplexed with EMU0 and gpio4_29 is multiplexed with EMU1. These pins will be sampled at reset release by the test and  
emulation logic. Therefore, if they are used as GPIO pins, they must return to the high state whenever the device enters reset. This can  
be controlled by logic driven from rstoutn. After the device exits reset (indicated by rstoutn rising), these can return to GPIO mode.  
4.4.20 Pulse-Width Modulation Subsystem (PWMSS)  
NOTE  
For more information, see the Pulse-Width Modulation Subsystem (PWMSS) section in the  
device TRM.  
Table 4-23. PWMSS Signal Descriptions  
SIGNAL NAME  
DESCRIPTION  
TYPE  
BALL  
PWMSS1  
ehrpwm1A  
ehrpwm1B  
EHRPWM1 Output A  
O
O
D12, D14, L1  
D15, E12, L2  
F12, R5  
EHRPWM1 Output B  
ehrpwm1_tripzone_input  
eCAP1_in_PWM1_out  
EHRPWM1 Trip Zone Input  
ECAP1 Capture Input / PWM Output  
IO  
IO  
A5, AB15, D16, F16,  
N4  
ehrpwm1_synci  
ehrpwm1_synco  
EHRPWM1 Sync Input  
EHRPWM1 Sync Output  
I
A10, F14  
B10, C14  
O
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4.4.21 Test Interfaces  
NOTE  
For more information, see the On-Chip Debug Support section in the device TRM.  
Table 4-24. Debug Signal Descriptions  
SIGNAL NAME  
DESCRIPTION  
JTAG return clock  
JTAG test clock  
JTAG test data  
TYPE  
BALL  
rtck  
tclk  
tdi  
O
I
J6  
J2  
J1  
J4  
J3  
I
tdo  
tms  
JTAG test port data  
O
IO  
JTAG test port mode select. An external pullup resistor should be used on this  
ball.  
trstn  
emu0(1)  
emu1(1)  
emu2  
JTAG test reset  
Emulator pin 0  
Emulator pin 1  
Emulator pin 2  
Emulator pin 3  
Emulator pin 4  
Emulator pin 5  
Emulator pin 6  
Emulator pin 7  
Emulator pin 8  
Emulator pin 9  
Emulator pin 10  
Emulator pin 11  
Emulator pin 12  
Emulator pin 13  
Emulator pin 14  
Emulator pin 15  
Emulator pin 16  
Emulator pin 17  
Emulator pin 18  
Emulator pin 19  
I
J5  
H1  
IO  
IO  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
H2  
AA15  
AB15  
AA14  
AB14  
U13  
V13  
Y13  
W13  
U11  
V11  
U9  
emu3  
emu4  
emu5  
emu6  
emu7  
emu8  
emu9  
emu10  
emu11  
emu12  
emu13  
emu14  
emu15  
emu16  
emu17  
emu18  
emu19  
W11  
V9  
W9  
U8  
W8  
U7  
V7  
(1) EMU0 and EMU1 are multiplexed with GPIO. These pins will be sampled at reset release by the test and emulation logic. Therefore, if  
they are used as GPIO pins, they must return to the high state whenever the device enters reset. This can be controlled by logic driven  
from rstoutn. After the device exits reset (indicated by rstoutn rising), these can return to GPIO mode.  
4.4.22 System and Miscellaneous  
4.4.22.1 Sysboot  
NOTE  
For more information, see the Initialization section in the device TRM.  
Table 4-25. Sysboot Signal Descriptions  
SIGNAL NAME DESCRIPTION  
sysboot0 Boot Mode Configuration 0. The value latched on this pin upon porz reset release  
will determine the boot mode configuration of the device.  
TYPE  
BALL  
I
E8  
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Table 4-25. Sysboot Signal Descriptions (continued)  
SIGNAL NAME DESCRIPTION  
TYPE  
BALL  
sysboot1  
sysboot2  
sysboot3  
sysboot4  
sysboot5  
sysboot6  
sysboot7  
sysboot8  
sysboot9  
sysboot10  
sysboot11  
sysboot12  
sysboot13  
sysboot14  
sysboot15  
Boot Mode Configuration 1. The value latched on this pin upon porz reset release  
will determine the boot mode configuration of the device.  
I
A7  
Boot Mode Configuration 2. The value latched on this pin upon porz reset release  
will determine the boot mode configuration of the device.  
I
I
I
I
I
I
I
I
I
I
I
I
I
I
F8  
B7  
A6  
F7  
E7  
R7  
B6  
A5  
D6  
C5  
B5  
D7  
B4  
A4  
Boot Mode Configuration 3. The value latched on this pin upon porz reset release  
will determine the boot mode configuration of the device.  
Boot Mode Configuration 4. The value latched on this pin upon porz reset release  
will determine the boot mode configuration of the device.  
Boot Mode Configuration 5. The value latched on this pin upon porz reset release  
will determine the boot mode configuration of the device.  
Boot Mode Configuration 6. The value latched on this pin upon porz reset release  
will determine the boot mode configuration of the device.  
Boot Mode Configuration 7. The value latched on this pin upon porz reset release  
will determine the boot mode configuration of the device.  
Boot Mode Configuration 8. The value latched on this pin upon porz reset release  
will determine the boot mode configuration of the device.  
Boot Mode Configuration 9. The value latched on this pin upon porz reset release  
will determine the boot mode configuration of the device.  
Boot Mode Configuration 10. The value latched on this pin upon porz reset release  
will determine the boot mode configuration of the device.  
Boot Mode Configuration 11. The value latched on this pin upon porz reset release  
will determine the boot mode configuration of the device.  
Boot Mode Configuration 12. The value latched on this pin upon porz reset release  
will determine the boot mode configuration of the device.  
Boot Mode Configuration 13. The value latched on this pin upon porz reset release  
will determine the boot mode configuration of the device.  
Boot Mode Configuration 14. The value latched on this pin upon porz reset release  
will determine the boot mode configuration of the device.  
Boot Mode Configuration 15. The value latched on this pin upon porz reset release  
will determine the boot mode configuration of the device.  
4.4.22.2 Power, Reset and Clock Management (PRCM)  
NOTE  
For more information, see the Power, Reset, and Clock Management section in the device  
TRM.  
Table 4-26. PRCM Signal Descriptions  
SIGNAL NAME DESCRIPTION  
TYPE  
BALL  
clkout0  
Device Clock output 1. Can be used externally for devices with non-critical timing  
requirements, or for debug, or as a reference clock on GPMC as described in  
Table 7-8, GPMC/NOR Flash Interface Switching Characteristics - Synchronous  
Mode - 1 Load and Table 7-10, GPMC/NOR Flash Interface Switching  
Characteristics - Synchronous Mode - 5 Loads.  
O
AB17, C12, F14, F22,  
M1  
clkout1  
clkout2  
rstoutn  
Device Clock output 2. Can be used as a system clock for other devices.  
Device Clock output 3. Can be used as a system clock for other devices.  
O
O
O
F12, F21, U17  
A10, F20, W17  
F4  
Reset out (Active low). This pin asserts low in response to any global reset condition  
on the device.  
resetn  
porz  
Device Reset Input  
I
I
G4  
G3  
Power on Reset (active low). This pin must be asserted low until all device supplies  
are valid (see reset sequence/requirements).  
xref_clk0  
xref_clk1  
External Reference Clock 0. For Audio and other Peripherals.  
External Reference Clock 1. For Audio and other Peripherals.  
I
I
M1  
F14, F15  
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Table 4-26. PRCM Signal Descriptions (continued)  
SIGNAL NAME DESCRIPTION  
TYPE  
BALL  
xref_clk2  
xi_osc0  
External Reference Clock 2. For Audio and other Peripherals.  
I
I
H19  
E22  
System Oscillator OSC0 Crystal input / LVCMOS clock input. Functions as the input  
connection to a crystal when the internal oscillator OSC0 is used. Functions as an  
LVCMOS-compatible input clock when an external oscillator is used.  
xi_osc1  
Auxiliary Oscillator OSC1 Crystal input / LVCMOS clock input. Functions as the  
input connection to a crystal when the internal oscillator OSC1 is used. Functions as  
an LVCMOS-compatible input clock when an external oscillator is used.  
I
B21  
xo_osc0  
xo_osc1  
System Oscillator OSC0 Crystal output  
Auxiliary Oscillator OSC1 Crystal output  
O
O
D22  
C21  
4.4.22.3 Enhanced Direct Memory Access (EDMA)  
NOTE  
For more information, see the Enhanced DMA section in the device TRM.  
Table 4-27. EDMA Signal Descriptions  
SIGNAL NAME DESCRIPTION  
TYPE  
BALL  
C12, K17  
D12, K19  
E12  
dma_evt1  
dma_evt2  
dma_evt3  
dma_evt4  
Enhanced DMA Event Input 1  
Enhanced DMA Event Input 2  
Enhanced DMA Event Input 3  
Enhanced DMA Event Input 4  
I
I
I
I
F12, D8  
4.4.22.4 Interrupt Controllers (INTC)  
NOTE  
For more information, see the Interrupt Controllers section in the device TRM.  
Table 4-28. INTC Signal Descriptions  
SIGNAL NAME DESCRIPTION  
TYPE  
BALL  
nmin  
Non maskable interrupt input - active-low. This pin can be optionally routed to the  
DSP NMI input or as generic input to the Arm cores.  
I
G5  
sys_nirq1  
sys_nirq2  
esm_error  
External interrupt event to any device INTC  
External interrupt event to any device INTC  
I
I
K18, K22  
J17, K21  
This signal indicates a severe device failure. For more information, see Error  
Signaling Module in the Device TRM.  
IO  
AA15 , B17  
4.4.23 Power Supplies  
NOTE  
For more information, see the External Voltage Inputs section in the device TRM.  
Table 4-29. Power Supply Signal Descriptions  
SIGNAL NAME  
DESCRIPTION  
TYPE  
BALL  
vdd  
Core voltage domain supply  
PWR  
H7 , H12 , H13 , J10 ,  
J11 , J15 , K12 , L12 ,  
L15 , N12 , N16 ,  
P10 , P14  
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Table 4-29. Power Supply Signal Descriptions (continued)  
SIGNAL NAME  
DESCRIPTION  
TYPE  
BALL  
vss  
Ground  
GND  
A1 , A8 , A17 , A22 ,  
B22 , E1 , G10 ,  
G16 , H8 , H9 , H10 ,  
H11 , H15 , H16 ,  
J22 , K1 , K9 , K10 ,  
K11 , K13 , K14 ,  
K15 , K16 , M10 ,  
M11 , M12 , M13 ,  
M16 , N7 , N10 , P1 ,  
P15 , P16 , R9 , R12 ,  
R16 , T14 , V22 ,  
AB1 , AB2 , AB7 ,  
AB12 , AB16 , AB21 ,  
AB22  
vdd_dspeve  
DSP-EVE voltage domain supply  
PWR  
K8 , L8 , M9 , P8 ,  
P9 , P11 , P12  
vdda_per  
PER PLL and PER HSDIVIDER analog power supply  
PWR  
PWR  
PWR  
H14  
N8  
vdda_ddr_dsp  
vdda_gmac_core  
EVE PLL, DPLL_DDR and DDR HSDIVIDER analog power supply  
GMAC PLL, GMAC HSDIVIDER, DPLL_CORE and CORE HSDIVIDER  
analog power supply  
M8  
vdda_osc  
vssa_osc0  
vssa_osc1  
vdda_csi  
vssa_csi  
IO supply for oscillator section  
OSC0 analog ground  
PWR  
GND  
GND  
PWR  
GND  
PWR  
GND  
PWR  
GND  
PWR  
E21  
D21  
C22  
A14  
B14  
U19  
T19  
P22  
P21  
OSC1 analog ground  
CSI analog power supply  
CSI analog ground  
vdda_dac  
vssa_dac  
vdda_adc  
vssa_adc  
vdds18v  
DAC analog power supply  
DAC analog ground  
ADC analog power supply  
ADC analog ground  
1.8V power supply and Power Group bias supply  
G12, J7, L16, P13,  
T11  
vdds18v_ddr1  
vdds18v_ddr2  
vdds18v_ddr3  
vdds_ddr1  
1.8v bias supply for Byte0, Byte2, ECC Byte, Addr Cmd  
1.8v bias supply for Addr Cmd  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
P7, T9  
G7  
1.8v bias supply for Byte1, Byte3  
T16, V21  
IO power supply for Byte0, Byte2, ECC Byte, Addr Cmd  
IO power supply for Addr Cmd  
R1, T7, T8, AA1, AB6  
C2, E2, G6  
vdds_ddr2  
vdds_ddr3  
IO power supply for Byte1, Byte3  
T15, AA22, AB19  
K2, K7, L7, M7  
vddshv1  
Dual Voltage (1.8V or 3.3V) power supply for the GENERAL Power  
Group pins  
vddshv2  
vddshv3  
vddshv4  
vddshv5  
vddshv6  
Dual Voltage (1.8V or 3.3V) power supply for the GPMC Power Group  
pins  
PWR  
PWR  
PWR  
PWR  
PWR  
G8, G9, G11, B8  
G14  
Dual Voltage (1.8V or 3.3V) power supply for the UART1 and UART2  
Power Group pins  
Dual Voltage (1.8V or 3.3V) power supply for the RGMII Power Group  
pins  
A18, E20  
Dual Voltage (1.8V or 3.3V) power supply for the VIN1 Power Group  
pins  
H17, J16, J21  
T10, T12, T13, AA16  
Dual Voltage (1.8V or 3.3V) power supply for the VOUT1 Power Group  
pins  
cap_vddram_core1(1)  
cap_vddram_core2(1)  
cap_vddram_dspeve(1)  
SRAM array supply for core voltage domain memories  
SRAM array supply for core voltage domain memories  
SRAM array supply for DSP-EVE memories  
CAP  
CAP  
CAP  
N15  
M15  
M14  
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(1) This pin must always be connected via a 1-uF capacitor to vss.  
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5 Specifications  
NOTE  
For more information, see Power, Reset and Clock Management / PRCM Subsystem  
Environment / External Voltage Inputs or Initialization / Preinitialization / Power Requirements  
section of the Device TRM.  
NOTE  
The index number 1 which is part of the EMIF1 signal prefixes (ddr1_*) listed in  
Section 4.4.8, External Memory Interface (EMIF), column "SIGNAL NAME" are not to be  
confused with DDR1 type of SDRAM memories.  
NOTE  
Audio Back End (ABE) module is not supported for this family of devices, but “ABE” name is  
still present in some clock or DPLL names.  
CAUTION  
All IO Cells are NOT Fail-safe compliant and should not be externally driven in  
absence of their IO supply.  
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Specifications  
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5.1 Absolute Maximum Ratings  
Stresses beyond those listed as absolute maximum ratings may cause permanent damage to the device. These are stress  
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Section 5.4,  
Recommended Operating Conditions, is not implied. Exposure to absolute maximum rated conditions for extended periods  
may affect device reliability.  
PARAMETER(1)  
DESCRIPTION  
MIN  
-0.3  
-0.3  
MAX  
1.5  
UNIT  
V
VSUPPLY (Steady-State)  
Supply Voltage Ranges (Steady-  
Core (vdd, vdd_dspeve)  
State)  
Analog (vdda_per, vdda_ddr_dsp,  
vdda_gmac_core, vdda_osc,  
vdda_csi, vdda_dac, vdda_adc)  
2.0  
V
vdds_ddr1, vdds_ddr2, vdds_ddr3  
(1.35V mode)  
-0.3  
-0.3  
-0.3  
-0.3  
1.65  
1.8  
V
V
V
V
vdds_ddr1, vdds_ddr2, vdds_ddr3  
(1.5V mode)  
vdds_ddr1, vdds_ddr2, vdds_ddr3  
(1.8V mode)  
2.1  
vdds18v, vdds18v_ddr1,  
2.1  
vdds18v_ddr2, vdds18v_ddr3  
vddshv1-6 (1.8V mode)  
vddshv1-6 (3.3V mode)  
Core I/Os  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
2.1  
3.8  
1.5  
2.0  
1.65  
1.8  
2.1  
3.8  
105  
V
V
VIO (Steady-State)  
Input and Output Voltage Ranges  
(Steady-State)  
V
Analog I/Os  
V
I/O 1.35V  
V
I/O 1.5V  
V
1.8V I/Os  
V
3.3V I/Os  
V
SR  
Maximum slew rate, all supplies  
V/s  
V
VIO (Transient Overshoot /  
Undershoot)  
Input and Output Voltage Ranges (Transient Overshoot / Undershoot)  
Note: valid for up to 20% of the signal period  
0.2×VDD  
(2)  
TJ  
Operating junction temperature range Automotive  
-40  
-55  
+125  
+150  
100  
°C  
°C  
mA  
V
TSTG  
Storage temperature range after soldered onto PC Board  
I-test(3), All I/Os (if different levels then one line per level)  
Over-voltage Test(4), All supplies (if different levels then one line per level)  
Latch-up I-Test  
Latch-up OV-Test  
-100  
N/A  
1.5×Vsup  
ply max  
(1) See I/Os supplied by this power pin in Table 4-2, Ball Characteristics.  
(2) VDD is the voltage on the corresponding power-supply pin(s) for the IO.  
(3) Per JEDEC JESD78 at 125°C with specified I/O pin injection current and clamp voltage of 1.5 times maximum recommended I/O  
voltage and negative 0.5 times maximum recommended I/O voltage.  
(4) Per JEDEC JESD78 at 125°C.  
5.2 ESD Ratings  
VALUE  
±1000  
±250  
UNIT  
Human-Body model (HBM), per AEC Q100-002(1)  
All pins  
VESD Electrostatic discharge  
V
Charged-device model (CDM), per AEC  
Q100-011  
Corner pins (A1,  
AB1, A22, AB22)  
±750  
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.  
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5.3 Power-On Hours (POH)(1)(2)(3)  
IP  
DUTY  
CYCLE  
VOLTAGE DOMAIN  
VOLTAGE (V)  
(MAX)  
FREQUENCY (MHz)  
(MAX)  
Tj(°C)  
POH  
All  
100%  
All  
All Support OPPs  
Automotive Profile(1)  
20000  
(1) Automotive profile is defined as 20000 power on hours with junction temperature as follows: 5%@-40°C, 65%@70°C, 20%@110°C,  
10%@125°C.  
(2) POH is a functional of voltage, temperature and time. Usage at higher voltages and temperatures will result in a reduction in POH to  
achieve the same reliability performance. For assessment of alternate use cases, contact your local TI representative.  
(3) The information in this section is provided solely for your convenience and does not extend or modify the warranty provided under TI’s  
standard terms and conditions for TI semiconductor products.  
5.4 Recommended Operating Conditions  
over operating free-air temperature range (unless otherwise noted)  
PARAMETER  
DESCRIPTION  
MIN (2)  
NOM  
MAX DC (3)  
MAX (2)  
UNIT  
Input Power Supply Voltage Range  
vdd  
Core voltage domain supply  
See Section 5.5  
See Section 5.5  
1.80 1.836  
V
V
V
vdd_dspeve  
vdda_per  
DSP-EVE voltage domain supply  
PER PLL and PER HSDIVIDER  
analog power supply  
1.71  
1.71  
1.71  
1.89  
1.89  
1.89  
Maximum noise (peak-peak)  
50  
mVPPmax  
V
vdda_ddr_dsp  
EVE PLL, DPLL_DDR and DDR  
HSDIVIDER analog power supply  
1.80  
1.836  
1.836  
Maximum noise (peak-peak)  
50  
mVPPmax  
V
vdda_gmac_core  
GMAC PLL, GMAC HSDIVIDER,  
DPLL_CORE and CORE HSDIVIDER  
analog power supply  
1.80  
Maximum noise (peak-peak)  
I/O supply for oscillator section  
Maximum noise (peak-peak)  
CSI analog power supply  
50  
1.80  
50  
mVPPmax  
vdda_osc  
vdda_csi  
vdda_dac  
vdda_adc  
vdds18v  
1.71  
1.71  
1.71  
1.71  
1.71  
1.836  
1.836  
1.836  
1.836  
1.836  
1.89  
1.89  
1.89  
1.89  
1.89  
V
mVPPmax  
1.80  
50  
V
Maximum noise (peak-peak)  
DAC analog power supply  
Maximum noise (peak-peak)  
ADC analog power supply  
Maximum noise (peak-peak)  
mVPPmax  
1.80  
50  
V
mVPPmax  
V
1.80  
50  
mVPPmax  
V
1.8V power supply and Power Group  
bias supply  
1.80  
Maximum noise (peak-peak)  
50  
mVPPmax  
V
vdds18v_ddr1  
1.8v bias supply for Byte0, Byte2,  
ECC Byte, Addr Cmd  
1.71  
1.80  
1.836  
1.89  
Maximum noise (peak-peak)  
1.8v bias supply for Addr Cmd  
Maximum noise (peak-peak)  
1.8v bias supply for Byte1, Byte3  
Maximum noise (peak-peak)  
50  
1.80  
50  
mVPPmax  
vdds18v_ddr2  
vdds18v_ddr3  
vdds_ddr1  
1.71  
1.71  
1.28  
1.836  
1.836  
1.377  
1.89  
1.89  
1.42  
V
mVPPmax  
V
1.80  
50  
mVPPmax  
V
EMIF power supply  
1.35-V  
Mode  
1.35  
(1.8V for DDR2 mode /  
1.5V for DDR3 mode /  
1.35V DDR3L mode)  
1.5-V Mode  
1.8-V Mode  
1.43  
1.71  
1.50  
1.80  
50  
1.53  
1.57  
1.89  
1.836  
Maximum noise (peak-  
peak)  
1.35-V  
Mode  
mVPPmax  
1.5-V Mode  
1.8-V Mode  
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Recommended Operating Conditions (continued)  
over operating free-air temperature range (unless otherwise noted)  
PARAMETER  
vdds_ddr2  
DESCRIPTION  
MIN (2)  
NOM  
MAX DC (3)  
MAX (2)  
UNIT  
EMIF power supply  
1.35-V  
Mode  
1.28  
1.35  
1.377  
1.42  
V
(1.8V for DDR2 mode /  
1.5V for DDR3 mode /  
1.35V DDR3L mode)  
1.5-V Mode  
1.8-V Mode  
1.43  
1.71  
1.50  
1.80  
50  
1.53  
1.57  
1.89  
1.836  
Maximum noise (peak-  
peak)  
1.35-V  
Mode  
mVPPmax  
1.5-V Mode  
1.8-V Mode  
vdds_ddr3  
EMIF power supply  
1.35-V  
Mode  
1.28  
1.35  
1.377  
1.42  
V
mVPPmax  
V
(1.8V for DDR2 mode /  
1.5V for DDR3 mode /  
1.35V DDR3L mode)  
1.5-V Mode  
1.8-V Mode  
1.43  
1.71  
1.50  
1.80  
50  
1.53  
1.57  
1.89  
1.836  
Maximum noise (peak-  
peak)  
1.35-V  
Mode  
1.5-V Mode  
1.8-V Mode  
1.8-V Mode  
3.3-V Mode  
vddshv1  
vddshv2  
vddshv3  
vddshv4  
vddshv5  
vddshv6  
vss  
Dual Voltage (1.8V or  
3.3V) power supply for  
the GENERAL Power  
Group pins  
1.71  
1.80  
3.30  
1.836  
3.366  
1.89  
3.135  
3.465  
Maximum noise (peak-  
peak)  
1.8-V Mode  
3.3-V Mode  
1.8-V Mode  
3.3-V Mode  
50  
mVPPmax  
Dual Voltage (1.8V or  
3.3V) power supply for  
the GPMC Power Group  
pins  
1.71  
1.80  
3.30  
1.836  
3.366  
1.89  
V
3.135  
3.465  
Maximum noise (peak-  
peak)  
1.8-V Mode  
3.3-V Mode  
1.8-V Mode  
3.3-V Mode  
50  
mVPPmax  
Dual Voltage (1.8V or  
3.3V) power supply for  
the UART1 and UART2  
Power Group pins  
1.71  
1.80  
3.30  
1.836  
3.366  
1.89  
V
3.135  
3.465  
Maximum noise (peak-  
peak)  
1.8-V Mode  
3.3-V Mode  
1.8-V Mode  
3.3-V Mode  
50  
mVPPmax  
Dual Voltage (1.8V or  
3.3V) power supply for  
the RGMII Power Group  
pins  
1.71  
1.80  
3.30  
1.836  
3.366  
1.89  
V
3.135  
3.465  
Maximum noise (peak-  
peak)  
1.8-V Mode  
3.3-V Mode  
1.8-V Mode  
3.3-V Mode  
50  
mVPPmax  
Dual Voltage (1.8V or  
3.3V) power supply for  
the VIN1 Power Group  
pins  
1.71  
1.80  
3.30  
1.836  
3.366  
1.89  
V
3.135  
3.465  
Maximum noise (peak-  
peak)  
1.8-V Mode  
3.3-V Mode  
1.8-V Mode  
3.3-V Mode  
50  
mVPPmax  
Dual Voltage (1.8V or  
3.3V) power supply for  
the VOUT1 Power  
Group pins  
1.71  
1.80  
3.30  
1.836  
3.366  
1.89  
V
3.135  
3.465  
Maximum noise (peak-  
peak)  
1.8-V Mode  
3.3-V Mode  
50  
mVPPmax  
Ground supply  
0
V
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Recommended Operating Conditions (continued)  
over operating free-air temperature range (unless otherwise noted)  
PARAMETER  
vssa_osc0  
DESCRIPTION  
OSC0 analog ground  
MIN (2)  
NOM  
MAX DC (3)  
MAX (2)  
UNIT  
V
0
0
0
0
0
vssa_osc1  
vssa_csi  
OSC1 analog ground  
V
CSI analog ground supply  
DAC analog ground supply  
ADC analog ground supply  
V
vssa_dac  
vssa_adc  
V
V
(1)  
TJ  
Operating junction  
temperature range  
Automotive  
-40  
125(4)  
°C  
(1) Refer to Power on Hours table for limitations.  
(2) The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This  
requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc.  
(3) The DC voltage at the device ball should never be above the MAX DC voltage to avoid impact on device reliability and lifetime POH  
(Power-On-Hours). The MAX DC voltage is defined as the highest allowed DC regulated voltage, without transients, seen at the ball.  
(4) The TSHUT feature of the SoC resets the device by default when one of the on-die temp sensors reports 123 °C. This is intended to  
protect the device from exceeding 125 °C. Though not recommended, the TSHUT temperature threshold can be modified in software if  
other mechanisms are in place to avoid exceeding 125 °C. Refer to the device TRM for details on the TSHUT feature.  
5.5 Operating Performance Points  
This section describes the operating conditions of the device. This section also contains the description of  
each Operating Performance Point (OPP) for processor clocks and device core clocks.  
Table 5-1 describes the maximum supported frequency per speed grade for the devices.  
Table 5-1. Speed Grade Maximum Frequency  
MAXIMUM FREQUENCY (MHz)  
DEVICE  
DSP  
250  
EVE  
250  
355  
500  
667  
900  
IPU  
ISS  
L3  
DDR3/DDR3L  
DDR2  
LPDDR2  
ADC  
20  
TDA3xxA  
TDA3xxB  
TDA3xxD  
TDA3xxR  
TDA3xxS  
212.8  
212.8  
212.8  
212.8  
212.8  
212.8  
212.8  
212.8  
212.8  
212.8  
266  
266  
266  
266  
266  
333 (DDR-667)  
333 (DDR-667) 333 (DDR-667)  
355  
532 (DDR-1066) 400 (DDR-800) 333 (DDR-667)  
532 (DDR-1066) 400 (DDR-800) 333 (DDR-667)  
532 (DDR-1066) 400 (DDR-800) 333 (DDR-667)  
532 (DDR-1066) 400 (DDR-800) 333 (DDR-667)  
20  
500  
20  
745  
20  
1000  
20  
5.5.1 AVS Requirements  
Adaptive Voltage Scaling (AVS) is required on most of the vdd_* supplies as defined in Table 5-2.  
Table 5-2. AVS Requirements per vdd_* Supply  
SUPPLY  
vdd  
AVS REQUIRED?  
Yes, for all OPPs  
Yes, for all OPPs  
vdd_dspeve  
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5.5.2 Voltage And Core Clock Specifications  
Table 5-3 shows the recommended OPP per voltage domain.  
Table 5-3. Voltage Domains Operating Performance Points  
OPP_NOM  
OPP_OD  
OPP_HIGH/OPP_PLUS(6)  
DOMAIN  
CONDITION  
MIN (2) NOM (1) MAX (2) MIN (2) NOM (1) MAX (2) MIN (2) NOM (1) MAX DC (3) MAX (2)  
BOOT (Before  
AVS is enabled)  
1.02  
1.06  
AVS  
1.11  
1.20  
1.11  
1.11  
Not Applicable  
Not Applicable  
Not Applicable  
Not Applicable  
Not Applicable  
(4)  
VD_CORE (V)  
AVS  
After AVS is  
enabled (4)  
Voltage  
Voltage  
(5)  
(5)  
3.5%  
BOOT (Before  
AVS is enabled)  
1.02  
1.06  
AVS  
Not Applicable  
AVS  
(4)  
VD_DSPEVE  
(V)  
AVS  
AVS  
AVS  
AVS  
AVS  
AVS  
AVS  
After AVS is  
enabled (4)  
Voltage  
Voltage  
Voltage  
Voltage  
Voltage Voltage  
Voltage Voltage (5) Voltage  
(5)  
(5)  
(5)  
(5)  
(5)  
(5)  
(5) + 5%  
+ 2%  
(5) + 5%  
3.5%  
3.5%  
3.5%  
(1) In a typical implementation, the power supply should target the NOM voltage.  
(2) The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This  
requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc.  
(3) The DC voltage at the device ball should never be above the MAX DC voltage to avoid impact on device reliability and lifetime POH  
(Power-On-Hours). The MAX DC voltage is defined as the highest allowed DC regulated voltage, without transients, seen at the ball.  
(4) For all OPPs, AVS must be enabled to avoid impact on device reliability, lifetime POH (Power-On-Hours), and device power.  
(5) The AVS voltages are device-dependent, voltage domain-dependent, and OPP-dependent. They must be read from the  
STD_FUSE_OPP. For information about STD_FUSE_OPP Registers address, refer to the Control Module section in the device TRM.  
The power supply should be adjustable over the following ranges for each required OPP:  
OPP_NOM: 0.85V - 1.06V  
OPP_OD: 0.94V - 1.15V  
OPP_HIGH: 1.05V - 1.25V  
OPP_PLUS: 1.05V - 1.25V  
The AVS Voltages will be within the above specified ranges.  
(6) The required PRCM and DCC software configuration sequence for OPP_PLUS (DSP 1 GHz or EVE 900 MHz) is different than other  
OPPs. For more information, see PRCM Software Configuration for OPP_PLUS section of the device TRM.  
Table 5-4 describes the standard processor clocks speed characteristics vs OPP of the device.  
Table 5-4. Supported OPP vs Max Frequency(1)(2)  
CLOCK  
OPP_NOM  
OPP_OD  
OPP_HIGH  
OPP_PLUS  
MAX FREQUENCY  
(MHz)  
MAX FREQUENCY  
(MHz)  
MAX FREQUENCY  
(MHz)  
MAX FREQUENCY (MHz)  
VD_DSPEVE  
DSP_CLK  
EVE_FCLK  
VD_CORE  
CORE_IPU1_CLK  
ISS  
500  
500  
709  
667  
745  
667  
1000  
900  
212.8  
212.8  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
L3_CLK  
266  
DDR3 / DDR3L  
DDR2  
532 (DDR-1066)  
400 (DDR-800)  
333 (DDR-667)  
20  
LPPDR2  
ADC  
80  
Specifications  
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(1) N/A stands for Not Applicable.  
(2) Maximum supported frequency is limited to the device speed grade (see Table 5-1, Speed Grade Maximum Frequency).  
5.5.3 Maximum Supported Frequency  
Device modules either receive their clock directly from an external clock input, directly from a PLL, or from  
a PRCM. Table 5-5 lists the clock source options for each module on this device, along with the maximum  
frequency that module can accept. To ensure proper module functionality, the device PLLs and dividers  
must be programmed not to exceed the maximum frequencies listed in this table.  
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Specifications  
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Table 5-5. Maximum Supported Frequency  
Module  
Clock Sources  
Instance Name Input Clock Name  
Clock Type  
Max. Clock  
Allowed (MHz)  
PRCM Clock  
Name  
PLL / OSC /  
Source Clock  
Name  
PLL / OSC /  
Source Name  
ADC  
OCP_CLK  
ADC_CLK  
Int  
133  
20  
L4PER2_L3_GICL  
K
CORE_X2_CLK  
DPLL_CORE  
Func  
ADC_CLK  
SYS_CLK1  
SYS_CLK2  
XREF_CLK0  
OSC0  
OSC1  
xref_clk0  
DPLL_CORE  
CSI2  
SCPCLK  
Int & Func  
Func  
106.4  
0.032  
38.4  
ISS_MAIN_FCLK CORE_ISS_MAIN_  
CLK  
COUNTER_32K COUNTER_32K_F  
CLK  
FUNC_32K_CLK  
SYS_CLK1/610  
OSC0  
OSC0  
COUNTER_32K_I  
CLK  
Int  
WKUPAON_GICL  
K
SYS_CLK1  
CRC  
CTRL_MODULE_ L3INSTR_TS_GCL  
BANDGAP  
OCP_CLK_PI  
Int & Func  
Int  
133  
5
CRC_L3_GICLK  
CORE_X2_CLK  
SYS_CLK1  
DPLL_CORE  
OSC0  
L3INSTR_TS_GCL  
K
K
ABE_LP_CLK  
CORE_X2_CLK  
DPLL_DDR  
DPLL_CORE  
CTRL_MODULE_ L4CFG_L4_GICLK  
CORE  
Int  
Int  
133  
L4_ICLK  
CTRL_MODULE_ WKUPAON_GICL  
38.4  
WKUPAON_GICL  
K
SYS_CLK1  
ABE_LP_CLK  
SYS_CLK1  
OSC0  
DPLL_DDR  
OSC0  
WKUP  
K
DCAN1  
DCAN1_FCLK  
Func  
Int  
20  
DCAN1_SYS_CLK  
SYS_CLK2  
OSC1  
DCAN1_ICLK  
133  
WKUPAON_GICL  
K
SYS_CLK1  
OSC0  
ABE_LP_CLK  
MCAN_CLK  
CORE_X2_CLK  
DPLL_DDR  
DPLL_GMAC_DSP  
DPLL_CORE  
MCAN  
MCAN_FCLK  
MCAN_ICLK  
Func  
Int  
80  
MCAN_CLK  
133  
L4PER2_L3_GICL  
K
DCC1  
DCC2  
DCC3  
DCC4  
OCP_CLK_PI  
OCP_CLK_PI  
OCP_CLK_PI  
OCP_CLK_PI  
Int  
Int  
Int  
Int  
133  
133  
133  
133  
L4PER3_L3_GICL  
K
CORE_X2_CLK  
CORE_X2_CLK  
CORE_X2_CLK  
CORE_X2_CLK  
DPLL_CORE  
DPLL_CORE  
DPLL_CORE  
DPLL_CORE  
L4PER3_L3_GICL  
K
L4PER3_L3_GICL  
K
L4PER3_L3_GICL  
K
DCC5  
DCC6  
DCC7  
DLL  
OCP_CLK_PI  
OCP_CLK_PI  
OCP_CLK_PI  
EMIF_DLL_FCLK  
DSP1_FICLK  
Int  
Int  
133  
133  
L4PER_L3_GICLK  
L4PER_L3_GICLK  
L4PER_L3_GICLK  
CORE_X2_CLK  
CORE_X2_CLK  
CORE_X2_CLK  
DPLL_CORE  
DPLL_CORE  
DPLL_CORE  
DPLL_DDR  
Int  
133  
Func  
Int & Func  
266  
EMIF_DLL_GCLK EMIF_DLL_GCLK  
DSP1  
DSP_CLK  
DSP1_GFCLK  
DSP_GFCLK  
DPLL_EVE_VID_D  
SP  
DPLL_CORE  
DPLL_GMAC_DSP  
DSP2  
DSS  
DSP2_FICLK  
Int & Func  
DSP_CLK  
DSP2_GFCLK  
DSP_GFCLK  
DPLL_EVE_VID_D  
SP  
DPLL_CORE  
DPLL_GMAC_DSP  
DPLL_PER  
DSS_FCK_CLK  
DSS_VP_CLK  
Int & Func  
Func  
192  
165  
DSS_GFCLK  
VID_PIX_CLK  
DSS_GFCLK  
VID_PIX_CLK  
DPLL_EVE_VID_D  
SP  
82  
Specifications  
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SPRS964H JUNE 2016REVISED FEBRUARY 2020  
Table 5-5. Maximum Supported Frequency (continued)  
Module  
Instance Name Input Clock Name  
Clock Sources  
Clock Type  
Max. Clock  
Allowed (MHz)  
PRCM Clock  
Name  
PLL / OSC /  
Source Clock  
Name  
PLL / OSC /  
Source Name  
DSS DISPC  
DISPC_FCK_CLK  
DISPC_CLK1  
Int & Func  
Int  
192  
165  
DSS_GFCLK  
VID_PIX_CLK  
DSS_GFCLK  
VID_PIX_CLK  
DPLL_PER  
DPLL_EVE_VID_D  
SP  
EFUSE_CTRL_C  
UST  
ocp_clk  
sys_clk  
Int  
133  
CUSTEFUSE_L4_  
GICLK  
CORE_X2_CLK  
SYS_CLK1  
DPLL_CORE  
Func  
38.4  
CUSTEFUSE_SYS  
_GFCLK  
OSC0  
ELM  
ELM_ICLK  
L3_CLK  
Int  
Int  
133  
266  
L4PER_L3_GICLK  
EMIF_L3_GICLK  
EMIF_L4_GICLK  
CORE_X2_CLK  
CORE_X2_CLK  
CORE_X2_CLK  
DPLL_CORE  
DPLL_CORE  
DPLL_CORE  
DPLL_DDR  
DPLL_DDR  
DPLL_CORE  
-
EMIF_OCP_FW  
L4_CLKEN  
Int  
133  
EMIF_PHY  
EMIF  
EMIF_PHY_FCLK  
EMIF_DLL_FCLK  
EMIF_ICLK  
Func  
Int  
DDR  
266  
EMIF_PHY_GCLK EMIF_PHY_GCLK  
EMIF_DLL_GCLK  
EMIF_L3_GICLK  
L3_EOCP_GICLK  
-
Int  
266  
CORE_X2_CLK  
-
EMIF_L3_ICLK  
EMIF_FICLK  
Int  
266  
Func  
DDR/2  
EMIF_PHY_GCLK/ EMIF_PHY_GCLK  
2
DPLL_DDR  
ESM  
EVE  
OCP_CLK  
EVE_FCLK  
Int & Func  
Func  
133  
L4PER_L3_GICLK  
EVE_CLK  
CORE_X2_CLK  
EVE_GCLK  
DPLL_CORE  
DPLL_CORE  
EVE_FCLK  
DPLL_GMAC_DSP  
EVE_GFCLK  
DPLL_EVE_VID_D  
SP  
GMAC_SW  
CPTS_RFT_CLK  
Func  
266  
GMAC_RFT_CLK  
L3_ICLK  
DPLL_CORE  
OSC0  
SYS_CLK1  
MAIN_CLK  
Int  
125  
250  
GMAC_MAIN_CLK GMAC_250M_CLK DPLL_GMAC_DSP  
GMII_250MHZ_CL GMII_250MHZ_CL DPLL_GMAC_DSP  
MHZ_250_CLK  
Func  
K
K
MHZ_5_CLK  
MHZ_50_CLK  
GPIO1_ICLK  
GPIO1_DBCLK  
Func  
Func  
Int  
5
RGMII_5MHZ_CLK RMII_50MHZ_CLK DPLL_GMAC_DSP  
/10  
50  
RMII_50MHZ_CLK GMAC_RMII_HS_ DPLL_GMAC_DSP  
CLK  
GPIO1  
38.4  
0.032  
WKUPAON_GICL  
K
SYS_CLK1  
OSC0  
Func  
WKUPAON_32K_  
GFCLK  
SYS_CLK1/610  
OSC0  
GPIO2  
GPIO3  
GPIO4  
GPIO2_ICLK  
GPIO2_DBCLK  
GPIO3_ICLK  
GPIO3_DBCLK  
GPIO4_ICLK  
GPIO4_DBCLK  
GPMC_ICLK  
Int  
Func  
Int  
133  
0.032  
133  
L4PER_L3_GICLK  
FUNC_32K_CLK  
L4PER_L3_GICLK  
FUNC_32K_CLK  
L4PER_L3_GICLK  
FUNC_32K_CLK  
CORE_X2_CLK  
SYS_CLK1/610  
CORE_X2_CLK  
SYS_CLK1/610  
CORE_X2_CLK  
SYS_CLK1/610  
CORE_X2_CLK  
DPLL_CORE  
OSC0  
DPLL_CORE  
OSC0  
Func  
Int  
0.032  
133  
DPLL_CORE  
OSC0  
Func  
Int & Func  
0.032  
266  
GPMC  
I2C1  
L3MAIN1_L3_GIC  
LK  
DPLL_CORE  
I2C1_ICLK  
I2C1_FCLK  
I2C2_ICLK  
I2C2_FCLK  
PI_L3CLK  
Int  
Func  
133  
96  
L4PER_L3_GICLK  
CORE_X2_CLK  
DPLL_CORE  
DPLL_PER  
DPLL_CORE  
DPLL_PER  
DPLL_CORE  
PER_96M_GFCLK FUNC_192M_CLK  
L4PER_L3_GICLK CORE_X2_CLK  
PER_96M_GFCLK FUNC_192M_CLK  
L3INIT_L3_GICLK CORE_X2_CLK  
I2C2  
Int  
133  
96  
Func  
IEEE1500_2_OC  
P
Int & Func  
266  
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Table 5-5. Maximum Supported Frequency (continued)  
Module  
Instance Name Input Clock Name  
Clock Sources  
Clock Type  
Max. Clock  
Allowed (MHz)  
PRCM Clock  
Name  
PLL / OSC /  
Source Clock  
Name  
PLL / OSC /  
Source Name  
IPU1  
IPU1_GFCLK  
Int & Func  
IPU_CLK  
IPU1_GFCLK  
DPLL_ABE_X2_CL  
K
DPLL_DDR  
CORE_IPU_ISS_B  
OOST_CLK  
DPLL_CORE  
DPLL_CORE  
L3_INSTR  
L3_CLK  
Int  
L3_CLK  
L3INSTR_L3_GICL  
K
CORE_X2_CLK  
L4_CFG  
L4_PER1  
L4_PER2  
L4_CFG_CLK  
L4_PER1_CLK  
L4_PER2_CLK  
Int  
Int  
Int  
133  
133  
133  
L4CFG_L3_GICLK  
L4PER_L3_GICLK  
CORE_X2_CLK  
CORE_X2_CLK  
CORE_X2_CLK  
DPLL_CORE  
DPLL_CORE  
DPLL_CORE  
L4PER2_L3_GICL  
K
L4_PER3  
L4_WKUP  
L4_PER3_CLK  
L4_WKUP_CLK  
Int  
Int  
133  
L4PER3_L3_GICL  
K
CORE_X2_CLK  
DPLL_CORE  
38.4  
WKUPAON_GICL  
K
SYS_CLK1  
ABE_LP_CLK  
CORE_X2_CLK  
CORE_X2_CLK  
OSC0  
DPLL_DDR  
DPLL_CORE  
DPLL_CORE  
DPLL_DDR  
SYS_CLK1  
DPLL_PER  
MAILBOX1  
MAILBOX2  
MCASP1  
MAILBOX1_FLCK  
MAILBOX2_FLCK  
Int  
Int  
133  
133  
50  
L4CFG_L3_GICLK  
L4CFG_L3_GICLK  
MCASP1_AHCLK  
R
Func  
MCASP1_AHCLK ABE_24M_GFCLK  
R
ABE_SYS_CLK  
FUNC_24M_GFCL  
K
SYS_CLK1  
ATL_CLK0  
OSC0  
Module ATL  
Module ATL  
Module ATL  
Module ATL  
OSC1  
ATL_CLK1  
ATL_CLK2  
ATL_CLK3  
SYS_CLK2  
XREF_CLK0  
REF_CLKIN0  
REF_CLKIN1  
REF_CLKIN2  
DPLL_DDR  
SYS_CLK1  
DPLL_PER  
XREF_CLK1  
XREF_CLK2  
MCASP1_AHCLKX  
Func  
50  
MCASP1_AHCLKX ABE_24M_GFCLK  
ABE_SYS_CLK  
FUNC_24M_GFCL  
K
SYS_CLK1  
ATL_CLK0  
ATL_CLK1  
ATL_CLK2  
ATL_CLK3  
SYS_CLK2  
XREF_CLK0  
XREF_CLK1  
XREF_CLK2  
OSC0  
Module ATL  
Module ATL  
Module ATL  
Module ATL  
OSC1  
REF_CLKIN0  
REF_CLKIN1  
REF_CLKIN2  
DPLL_CORE  
OSC0  
MCASP1_FCLK  
MCASP1_ICLK  
Func  
Int  
133  
266  
MCASP1_AUX_GF  
CLK  
L4_ICLK  
SYS_CLK1  
IPU_L3_GICLK  
CORE_X2_CLK  
DPLL_CORE  
84  
Specifications  
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SPRS964H JUNE 2016REVISED FEBRUARY 2020  
Table 5-5. Maximum Supported Frequency (continued)  
Module  
Instance Name Input Clock Name  
Clock Sources  
Clock Type  
Max. Clock  
Allowed (MHz)  
PRCM Clock  
Name  
PLL / OSC /  
Source Clock  
Name  
PLL / OSC /  
Source Name  
MCASP2  
MCASP2_AHCLK  
R
Func  
50  
MCASP6_AHCLK ABE_24M_GFCLK  
DPLL_DDR  
SYS_CLK1  
DPLL_PER  
R
ABE_SYS_CLK  
FUNC_24M_GFCL  
K
SYS_CLK1  
ATL_CLK0  
OSC0  
Module ATL  
Module ATL  
Module ATL  
Module ATL  
OSC1  
ATL_CLK1  
ATL_CLK2  
ATL_CLK3  
SYS_CLK2  
XREF_CLK0  
REF_CLKIN0  
REF_CLKIN1  
REF_CLKIN2  
DPLL_DDR  
SYS_CLK1  
DPLL_PER  
XREF_CLK1  
XREF_CLK2  
MCASP2_AHCLKX  
Func  
50  
MCASP4_AHCLKX ABE_24M_GFCLK  
ABE_SYS_CLK  
FUNC_24M_GFCL  
K
SYS_CLK1  
ATL_CLK0  
ATL_CLK1  
ATL_CLK2  
ATL_CLK3  
SYS_CLK2  
XREF_CLK0  
XREF_CLK1  
XREF_CLK2  
OSC0  
Module ATL  
Module ATL  
Module ATL  
Module ATL  
OSC1  
REF_CLKIN0  
REF_CLKIN1  
REF_CLKIN2  
DPLL_CORE  
OSC0  
MCASP2_FCLK  
MCASP2_ICLK  
Func  
Int  
133  
133  
MCASP4_AUX_GF  
CLK  
L4_ICLK  
SYS_CLK1  
L4PER2_L3_GICL  
K
CORE_X2_CLK  
DPLL_CORE  
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Table 5-5. Maximum Supported Frequency (continued)  
Module  
Instance Name Input Clock Name  
Clock Sources  
Clock Type  
Max. Clock  
Allowed (MHz)  
PRCM Clock  
Name  
PLL / OSC /  
Source Clock  
Name  
PLL / OSC /  
Source Name  
MCASP3  
MCASP3_AHCLK  
Func  
50  
MCASP7_AHCLK ABE_24M_GFCLK  
DPLL_DDR  
SYS_CLK1  
DPLL_PER  
R
R
ABE_SYS_CLK  
FUNC_24M_GFCL  
K
SYS_CLK1  
ATL_CLK0  
OSC0  
Module ATL  
Module ATL  
Module ATL  
Module ATL  
OSC1  
ATL_CLK1  
ATL_CLK2  
ATL_CLK3  
SYS_CLK2  
XREF_CLK0  
REF_CLKIN0  
REF_CLKIN1  
REF_CLKIN2  
DPLL_DDR  
SYS_CLK1  
DPLL_PER  
XREF_CLK1  
XREF_CLK2  
MCASP3_AHCLKX  
Func  
50  
MCASP5_AHCLKX ABE_24M_GFCLK  
ABE_SYS_CLK  
FUNC_24M_GFCL  
K
SYS_CLK1  
ATL_CLK0  
ATL_CLK1  
ATL_CLK2  
ATL_CLK3  
SYS_CLK2  
XREF_CLK0  
XREF_CLK1  
XREF_CLK2  
OSC0  
Module ATL  
Module ATL  
Module ATL  
Module ATL  
OSC1  
REF_CLKIN0  
REF_CLKIN1  
REF_CLKIN2  
DPLL_CORE  
OSC0  
MCASP3_FCLK  
MCASP3_ICLK  
Func  
Int  
133  
133  
MCASP5_AUX_GF  
CLK  
L4_ICLK  
SYS_CLK1  
L4PER2_L3_GICL  
K
CORE_X2_CLK  
DPLL_CORE  
MCSPI1  
MCSPI2  
MCSPI3  
MCSPI4  
MMC1  
SPI1_ICLK  
SPI1_FCLK  
SPI2_ICLK  
Int  
Func  
Int  
133  
48  
L4PER_L3_GICLK  
CORE_X2_CLK  
DPLL_CORE  
DPLL_PER  
DPLL_CORE  
DPLL_PER  
DPLL_CORE  
DPLL_PER  
DPLL_CORE  
DPLL_PER  
OSC0  
PER_48M_GFCLK FUNC_192M_CLK  
L4PER_L3_GICLK CORE_X2_CLK  
PER_48M_GFCLK FUNC_192M_CLK  
L4PER_L3_GICLK CORE_X2_CLK  
PER_48M_GFCLK FUNC_192M_CLK  
L4PER_L3_GICLK CORE_X2_CLK  
PER_48M_GFCLK FUNC_192M_CLK  
133  
48  
SPI2_FCLK  
SPI3_ICLK  
Func  
Int  
133  
48  
SPI3_FCLK  
SPI4_ICLK  
Func  
Int  
133  
48  
SPI4_FCLK  
MMC_CLK_32K  
MMC_FCLK  
Func  
Func  
Func  
0.032  
192  
48  
FUNC_32K_CLK  
MMC4_GFCLK  
SYS_CLK1/610  
FUNC_192M_CLK  
FUNC_48M_FCLK  
CORE_X2_CLK  
CORE_X2_CLK  
DPLL_PER  
DPLL_PER  
DPLL_CORE  
DPLL_CORE  
MMC_ICLK  
MMU_CLK  
Int  
Int  
133  
266  
L3INIT_L3_GICLK  
MMU_EDMA  
OCMC_RAM  
L3MAIN1_L3_GIC  
LK  
OCMC_L3_CLK  
Int  
266  
L3MAIN1_L3_GIC  
LK  
CORE_X2_CLK  
DPLL_CORE  
86  
Specifications  
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Table 5-5. Maximum Supported Frequency (continued)  
Module  
Instance Name Input Clock Name  
Clock Sources  
Clock Type  
Max. Clock  
Allowed (MHz)  
PRCM Clock  
Name  
PLL / OSC /  
Source Clock  
Name  
PLL / OSC /  
Source Name  
OCP_WP_NOC  
PWMSS1  
QSPI  
PICLKOCPL3  
PWMSS1_GICLK  
QSPI_ICLK  
Int  
Int & Func  
Int  
266  
133  
266  
128  
L3INSTR_L3_GICL  
K
CORE_X2_CLK  
CORE_X2_CLK  
CORE_X2_CLK  
DPLL_CORE  
DPLL_CORE  
DPLL_CORE  
L4PER2_L3_GICL  
K
L4PER2_L3_GICL  
K
QSPI_FCLK  
Func  
QSPI_GFCLK  
FUNC_128M_CLK  
PER_QSPI_CLK  
CORE_X2_CLK  
DPLL_PER  
DPLL_PER  
DPLL_CORE  
RTI1  
RTI2  
OCP_CLK_PI  
RTI_CLK_PI  
Int  
133  
13  
WKUPAON_GICL  
K
Func  
RTI1_CLK  
SYS_CLK1/4  
SYS_CLK2/4  
OSC0  
OSC1  
FUNC_32K_CLK  
CORE_X2_CLK  
OSC0  
OCP_CLK_PI  
RTI_CLK_PI  
Int  
133  
13  
WKUPAON_GICL  
K
DPLL_CORE  
Func  
RTI2_CLK  
SYS_CLK1/4  
SYS_CLK2/4  
OSC0  
OSC1  
FUNC_32K_CLK  
CORE_X2_CLK  
OSC0  
RTI3  
OCP_CLK_PI  
RTI_CLK_PI  
Int  
133  
13  
WKUPAON_GICL  
K
DPLL_CORE  
Func  
RTI3_CLK  
SYS_CLK1/4  
SYS_CLK2/4  
OSC0  
OSC1  
FUNC_32K_CLK  
CORE_X2_CLK  
OSC0  
RTI4  
OCP_CLK_PI  
RTI_CLK_PI  
Int  
133  
13  
WKUPAON_GICL  
K
DPLL_CORE  
Func  
RTI4_CLK  
SYS_CLK1/4  
SYS_CLK2/4  
OSC0  
OSC1  
FUNC_32K_CLK  
CORE_X2_CLK  
OSC0  
RTI5  
OCP_CLK_PI  
RTI_CLK_PI  
Int  
133  
13  
WKUPAON_GICL  
K
DPLL_CORE  
Func  
RTI5_CLK  
SYS_CLK1/4  
SYS_CLK2/4  
OSC0  
OSC1  
OSC0  
FUNC_32K_CLK  
VID_PIX_CLK  
SD_DAC  
CLKDAC  
Func  
50  
VID_PIX_CLK  
DPLL_EVE_VID_D  
SP  
SL2  
piclk  
Int  
Int  
IVA_GCLK  
133  
IVA_GCLK  
IVA_GFCLK  
CORE_X2_CLK  
CORE_X2_CLK  
DPLL_IVA  
DPLL_CORE  
DPLL_CORE  
SPINLOCK  
TESOC  
SPINLOCK_ICLK  
L3_CLK  
L4CFG_L3_GICLK  
Func  
266  
L3MAIN1_L3_GIC  
LK  
EXT_CLK  
Func  
Int  
50  
EXT_CLK  
TESOC_EXT_CLK  
SYS_CLK1  
DPLL_CORE  
OSC0  
TIMER1  
TIMER1_ICLK  
133  
WKUPAON_GICL  
K
ABE_LP_CLK  
SYS_CLK1  
DPLL_DDR  
OSC0  
TIMER1_FCLK  
Func  
38.4  
TIMER1_GFCLK  
FUNC_32K_CLK  
SYS_CLK2  
OSC0  
OSC1  
XREF_CLK0  
XREF_CLK1  
ABE_GICLK  
xref_clk0  
xref_clk1  
DPLL_DDR  
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Table 5-5. Maximum Supported Frequency (continued)  
Module  
Instance Name Input Clock Name  
Clock Sources  
Clock Type  
Max. Clock  
Allowed (MHz)  
PRCM Clock  
Name  
PLL / OSC /  
Source Clock  
Name  
PLL / OSC /  
Source Name  
TIMER2  
TIMER3  
TIMER4  
TIMER5  
TIMER2_ICLK  
Int  
133  
100  
L4PER_L3_GICLK  
TIMER2_GFCLK  
CORE_X2_CLK  
SYS_CLK1  
DPLL_CORE  
OSC0  
TIMER2_FCLK  
Func  
FUNC_32K_CLK  
SYS_CLK2  
OSC0  
OSC1  
XREF_CLK0  
XREF_CLK1  
ABE_GICLK  
CORE_X2_CLK  
SYS_CLK1  
xref_clk0  
xref_clk1  
DPLL_DDR  
DPLL_CORE  
OSC0  
TIMER3_ICLK  
TIMER3_FCLK  
Int  
133  
100  
L4PER_L3_GICLK  
TIMER3_GFCLK  
Func  
FUNC_32K_CLK  
SYS_CLK2  
OSC0  
OSC1  
XREF_CLK0  
XREF_CLK1  
ABE_GICLK  
CORE_X2_CLK  
SYS_CLK1  
xref_clk0  
xref_clk1  
DPLL_DDR  
DPLL_CORE  
OSC0  
TIMER4_ICLK  
TIMER4_FCLK  
Int  
133  
100  
L4PER_L3_GICLK  
TIMER4_GFCLK  
Func  
FUNC_32K_CLK  
SYS_CLK2  
OSC0  
OSC1  
XREF_CLK0  
XREF_CLK1  
ABE_GICLK  
CORE_X2_CLK  
SYS_CLK1  
xref_clk0  
xref_clk1  
DPLL_DDR  
DPLL_CORE  
OSC0  
TIMER5_ICLK  
TIMER5_FCLK  
Int  
133  
100  
IPU_L3_GICLK  
TIMER5_GFCLK  
Func  
FUNC_32K_CLK  
SYS_CLK2  
OSC0  
OSC1  
XREF_CLK0  
XREF_CLK1  
ABE_GICLK  
xref_clk0  
xref_clk1  
DPLL_DDR  
CLKOUTMUX0  
CLKOUTMUX0_CL  
K
TIMER6  
TIMER6_ICLK  
TIMER6_FCLK  
Int  
133  
100  
IPU_L3_GICLK  
TIMER6_GFCLK  
CORE_X2_CLK  
SYS_CLK1  
DPLL_CORE  
OSC0  
Func  
FUNC_32K_CLK  
SYS_CLK2  
OSC0  
OSC1  
XREF_CLK0  
XREF_CLK1  
ABE_GICLK  
xref_clk0  
xref_clk1  
DPLL_DDR  
CLKOUTMUX0  
CLKOUTMUX0_CL  
K
88  
Specifications  
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SPRS964H JUNE 2016REVISED FEBRUARY 2020  
Table 5-5. Maximum Supported Frequency (continued)  
Module  
Instance Name Input Clock Name  
Clock Sources  
Clock Type  
Max. Clock  
Allowed (MHz)  
PRCM Clock  
Name  
PLL / OSC /  
Source Clock  
Name  
PLL / OSC /  
Source Name  
TIMER7  
TIMER7_ICLK  
TIMER7_FCLK  
Int  
133  
100  
IPU_L3_GICLK  
TIMER7_GFCLK  
CORE_X2_CLK  
SYS_CLK1  
DPLL_CORE  
OSC0  
Func  
FUNC_32K_CLK  
SYS_CLK2  
OSC0  
OSC1  
XREF_CLK0  
XREF_CLK1  
ABE_GICLK  
xref_clk0  
xref_clk1  
DPLL_DDR  
CLKOUTMUX0  
CLKOUTMUX0_CL  
K
TIMER8  
TIMER8_ICLK  
TIMER8_FCLK  
Int  
133  
100  
IPU_L3_GICLK  
TIMER8_GFCLK  
CORE_X2_CLK  
SYS_CLK1  
DPLL_CORE  
OSC0  
Func  
FUNC_32K_CLK  
SYS_CLK2  
OSC0  
OSC1  
XREF_CLK0  
XREF_CLK1  
ABE_GICLK  
xref_clk0  
xref_clk1  
DPLL_DDR  
CLKOUTMUX0  
CLKOUTMUX0_CL  
K
TPCC  
TPTC1  
TPTC2  
UART1  
TPCC_GCLK  
TPTC0_GCLK  
TPTC1_GCLK  
UART1_FCLK  
Int  
Int  
266  
266  
266  
L3MAIN1_L3_GIC  
LK  
CORE_X2_CLK  
CORE_X2_CLK  
CORE_X2_CLK  
DPLL_CORE  
DPLL_CORE  
DPLL_CORE  
L3MAIN1_L3_GIC  
LK  
Int  
L3MAIN1_L3_GIC  
LK  
Func  
192  
48  
UART1_GFCLK  
FUNC_192M_CLK  
FUNC_48M_FCLK  
CORE_X2_CLK  
DPLL_PER  
DPLL_PER  
DPLL_CORE  
DPLL_PER  
DPLL_PER  
DPLL_CORE  
DPLL_PER  
DPLL_PER  
DPLL_CORE  
DPLL_CORE  
UART1_ICLK  
UART2_FCLK  
Int  
133  
192  
48  
L4PER_L3_GICLK  
UART2_GFCLK  
UART2  
UART3  
Func  
FUNC_192M_CLK  
FUNC_48M_FCLK  
CORE_X2_CLK  
UART2_ICLK  
UART3_FCLK  
Int  
133  
192  
48  
L4PER_L3_GICLK  
UART3_GFCLK  
Func  
FUNC_192M_CLK  
FUNC_48M_FCLK  
CORE_X2_CLK  
UART3_ICLK  
VCP1_CLK  
Int  
Int  
133  
266  
L4PER_L3_GICLK  
VCP1  
VIP1  
L3MAIN1_L3_GIC  
LK  
CORE_X2_CLK  
PROC_CLK  
L3_CLK  
Func  
Int  
266  
133  
VIP1_GCLK  
L3_ICLK  
DPLL_CORE  
DPLL_CORE  
CORE_ISS_MAIN_  
CLK  
L4_CLK  
Int  
VIP1_GCLKDIV2  
VIP1_GCLK/2  
DPLL_CORE  
5.6 Power Consumption Summary  
NOTE  
Maximum power consumption for this SoC depends on the specific use conditions for the  
end system. Contact your TI representative for assistance in estimating maximum power  
consumption for the end system use case.  
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Specifications  
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5.7 Electrical Characteristics  
NOTE  
The data specified in Section 5.7.1 through Section 5.7.6 are subject to change.  
NOTE  
The interfaces or signals described in Section 5.7.1 through Section 5.7.6 correspond to the  
interfaces or signals available in multiplexing mode 0 (Function 1).  
All interfaces or signals multiplexed on the balls described in these tables have the same DC  
electrical characteristics, unless multiplexing involves a PHY/GPIO combination in which  
case different DC electrical characteristics are specified for the different multiplexing modes  
(Functions).  
5.7.1 LVCMOS DDR DC Electrical Characteristics  
Table 5-6 summarizes the DC electrical characteristics for LVCMOS DDR Buffers.  
NOTE  
For more information on the I/O cell configurations (i[2:0], sr[1:0]), see Control Module  
section of the Device TRM.  
90  
Specifications  
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Table 5-6. LVCMOS DDR DC Electrical Characteristics  
PARAMETER  
MIN  
NOM  
MAX  
UNIT  
Signal Names in MUXMODE 0 (Single-Ended Signals) ABF: ddr1_d[31:0], ddr1_a[15:0], ddr1_dqm[3:0], ddr1_ba[2:0], ddr1_csn[1:0],  
ddr1_cke[1:0], ddr1_odt[0], ddr1_casn, ddr1_rasn, ddr1_wen, ddr1_rst, ddr1_ecc_d[7:0], ddr1_dqm_ecc;  
Driver Mode  
VOH  
VOL  
CPAD  
ZO  
High-level output threshold (IOH = 0.1 mA)  
Low-level output threshold (IOL = 0.1 mA)  
Pad capacitance (including package capacitance)  
0.9×VDDS  
V
V
0.1×VDDS  
3
pF  
Ω
Output impedance (drive  
strength)  
l[2:0] = 000  
(Imp80)  
80  
60  
48  
40  
34  
l[2:0] = 001  
(Imp60)  
l[2:0] = 010  
(Imp48)  
l[2:0] = 011  
(Imp40)  
l[2:0] = 100  
(Imp34)  
Single-Ended Receiver Mode  
VIH  
VIL  
High-level input threshold  
DDR3/DDR3L  
DDR3/DDR3L  
VREF+0.1  
-0.2  
VDDS+0.2  
VREF-0.1  
V
V
V
Low-level input threshold  
VCM  
Input common-mode voltage  
VREF  
VREF+  
-1%VDDS  
1%VDDS  
CPAD  
Pad capacitance (including package capacitance)  
pF  
Signal Names in MUXMODE 0 (Differential Signals): ddr1_dqs[3:0], ddr1_dqsn[3:0], ddr1_ck, ddr1_nck, ddr1_dqs_ecc, ddr1_dqsn_ecc;  
Driver Mode  
VOH  
VOL  
CPAD  
ZO  
High-level output threshold (IOH = 0.1 mA)  
Low-level output threshold (IOL = 0.1 mA)  
Pad capacitance (including package capacitance)  
0.9×VDDS  
V
V
0.1×VDDS  
3
pF  
Ω
Output impedance (drive  
strength)  
l[2:0] = 000  
(Imp80)  
80  
60  
48  
40  
34  
l[2:0] = 001  
(Imp60)  
l[2:0] = 010  
(Imp48)  
l[2:0] = 011  
(Imp40)  
l[2:0] = 100  
(Imp34)  
Single-Ended Receiver Mode  
VIH  
VIL  
High-level input threshold  
DDR3/DDR3L  
DDR3/DDR3L  
VREF+0.1  
-0.2  
VDDS+0.2  
VREF-0.1  
V
V
V
Low-level input threshold  
VCM  
Input common-mode voltage  
VREF  
VREF+  
-1%VDDS  
1%VDDS  
CPAD  
Pad capacitance (including package capacitance)  
3
pF  
Differential Receiver Mode  
VSWING Input voltage swing  
VCM Input common-mode voltage  
DDR3/DDR3L  
0.4×vdds  
0.6×vdds  
V
V
VREF  
VREF+  
-1%VDDS  
1%VDDS  
CPAD  
Pad capacitance (including package capacitance)  
3
pF  
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(1) VDDS stands for corresponding power supply (i.e. vdds_ddr1 or vdds_ddr2). For more information on the power supply name and the  
corresponding ball, see Table 4-2, POWER [11] column.  
5.7.2 Dual Voltage LVCMOS I2C DC Electrical Characteristics  
Table 5-7 summarizes the DC electrical characteristics for Dual Voltage LVCMOS I2C Buffers.  
NOTE  
For more information on the I/O cell configurations, see the Control Module section of the  
Device TRM.  
Table 5-7. Dual Voltage LVCMOS I2C DC Electrical Characteristics  
PARAMETER  
Signal Names in MUXMODE 0: i2c2_scl; i2c1_scl; i2c1_sda; i2c2_sda;  
Balls ABF: L3, L4, L6, L5;  
MIN  
NOM  
MAX  
UNIT  
I2C Standard Mode – 1.8 V  
VIH  
VIL  
Vhys  
II  
Input high-level threshold  
Input low-level threshold  
Hysteresis  
0.7×VDDS  
0.1×VDDS  
V
V
0.3×VDDS  
V
Input current at each I/O pin with an input voltage between 0.1×VDDS to  
0.9×VDDS  
12  
12  
µA  
IOZ  
IOZ(IPAD Current) at each IO pin. PAD is swept from 0 to VDDS and the  
Max(I(PAD)) is measured and is reported as IOZ  
µA  
CI  
Input capacitance  
10  
pF  
V
VOL3  
IOLmin  
tOF  
Output low-level threshold open-drain at 3-mA sink current  
Low-level output current @VOL=0.2×VDDS  
0.2×VDDS  
3
mA  
ns  
Output fall time from VIHmin to VILmax with a bus capacitance CB from 5 pF  
to 400 pF  
250  
I2C Fast Mode – 1.8 V  
VIH  
VIL  
Vhys  
II  
Input high-level threshold  
0.7×VDDS  
0.1×VDDS  
V
V
Input low-level threshold  
Hysteresis  
0.3×VDDS  
V
Input current at each I/O pin with an input voltage between 0.1×VDDS to  
0.9×VDDS  
12  
12  
µA  
IOZ  
IOZ(IPAD Current) at each IO pin. PAD is swept from 0 to VDDS and the  
Max(I(PAD)) is measured and is reported as IOZ  
µA  
CI  
Input capacitance  
10  
pF  
V
VOL3  
IOLmin  
tOF  
Output low-level threshold open-drain at 3-mA sink current  
Low-level output current @VOL=0.2×VDDS  
0.2×VDDS  
3
mA  
ns  
Output fall time from VIHmin to VILmax with a bus capacitance CB from 10 pF 20+0.1×C  
250  
to 400 pF  
b
I2C Standard Mode – 3.3 V  
VIH  
VIL  
Input high-level threshold  
0.7×VDDS  
V
V
V
Input low-level threshold  
Hysteresis  
0.3×VDDS  
Vhys  
0.05×VDD  
S
II  
Input current at each I/O pin with an input voltage between 0.1×VDDS to  
0.9×VDDS  
31  
80  
80  
µA  
µA  
IOZ  
IOZ(IPAD Current) at each IO pin. PAD is swept from 0 to VDDS and the  
Max(I(PAD)) is measured and is reported as IOZ  
31  
CI  
Input capacitance  
10  
pF  
V
VOL3  
IOLmin  
Output low-level threshold open-drain at 3-mA sink current  
Low-level output current @VOL=0.4V  
0.4  
3
mA  
92  
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SPRS964H JUNE 2016REVISED FEBRUARY 2020  
Table 5-7. Dual Voltage LVCMOS I2C DC Electrical Characteristics (continued)  
PARAMETER  
MIN  
NOM  
MAX  
UNIT  
mA  
ns  
IOLmin  
tOF  
Low-level output current @VOL=0.6V for full drive load (400pF/400KHz)  
6
Output fall time from VIHmin to VILmax with a bus capacitance CB from 5 pF  
to 400 pF  
250  
I2C Fast Mode – 3.3 V  
VIH  
VIL  
Input high-level threshold  
0.7×VDDS  
V
V
V
Input low-level threshold  
Hysteresis  
0.3×VDDS  
Vhys  
0.05×VDD  
S
II  
Input current at each I/O pin with an input voltage between 0.1×VDDS to  
0.9×VDDS  
31  
80  
80  
µA  
µA  
IOZ  
IOZ(IPAD Current) at each IO pin. PAD is swept from 0 to VDDS and the  
Max(I(PAD)) is measured and is reported as IOZ  
31  
CI  
Input capacitance  
10  
pF  
V
VOL3  
IOLmin  
IOLmin  
tOF  
Output low-level threshold open-drain at 3-mA sink current  
Low-level output current @VOL=0.4V  
0.4  
3
6
mA  
mA  
ns  
Low-level output current @VOL=0.6V for full drive load (400pF/400KHz)  
Output fall time from VIHmin to VILmax with a bus capacitance CB from 10  
pF to 200 pF (Proper External Resistor Value should be used as per I2C  
spec)  
20+0.1×C  
b
250  
290  
Output fall time from VIHmin to VILmax with a bus capacitance CB from 300  
pF to 400 pF (Proper External Resistor Value should be used as per I2C  
spec)  
40  
(1) VDDS stands for corresponding power supply (i.e. vddshv3). For more information on the power supply name and the corresponding  
ball, see Table 4-2, POWER [11] column.  
5.7.3 IQ1833 Buffers DC Electrical Characteristics  
Table 5-8 summarizes the DC electrical characteristics for IQ1833 Buffers.  
Table 5-8. IQ1833 Buffers DC Electrical Characteristics  
PARAMETER  
MIN  
NOM  
MAX  
UNIT  
Signal Names in MUXMODE 0: tclk;  
Balls ABF: J2;  
1.8-V Mode  
VIH  
Input high-level threshold  
Input low-level threshold  
0.75 ×  
VDDS  
V
V
VIL  
0.25 ×  
VDDS  
VHYS  
IIN  
Input hysteresis voltage  
100  
2
mV  
µA  
pF  
Input current at each I/O pin  
11  
1
CPAD  
3.3-V Mode  
VIH  
Pad capacitance (including package capacitance)  
Input high-level threshold  
2.0  
V
V
VIL  
Input low-level threshold  
0.6  
VHYS  
IIN  
Input hysteresis voltage  
400  
5
mV  
µA  
pF  
Input current at each I/O pin  
Pad capacitance (including package capacitance)  
11  
1
CPAD  
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(1) VDDS stands for corresponding power supply (i.e. vddshv1). For more information on the power supply name and the corresponding  
ball, see Table 4-2, POWER [11] column.  
5.7.4 IHHV1833 Buffers DC Electrical Characteristics  
Table 5-9 summarizes the DC electrical characteristics for IHHV1833 Buffers.  
Table 5-9. IHHV1833 Buffers DC Electrical Characteristics  
PARAMETER  
Signal Names in MUXMODE 0: porz;  
MIN  
NOM  
MAX  
UNIT  
Balls ABF: G3;  
1.8-V Mode  
VIH  
Input high-level threshold  
1.2  
V
V
VIL  
Input low-level threshold  
0.4  
VHYS  
IIN  
Input hysteresis voltage  
40  
mV  
µA  
pF  
Input current at each I/O pin  
Pad capacitance (including package capacitance)  
0.02  
1
1
CPAD  
3.3-V Mode  
VIH  
Input high-level threshold  
1.2  
V
V
VIL  
Input low-level threshold  
0.4  
VHYS  
IIN  
Input hysteresis voltage  
40  
5
mV  
µA  
pF  
Input current at each I/O pin  
Pad capacitance (including package capacitance)  
8
1
CPAD  
5.7.5 LVCMOS Analog OSC Buffers DC Electrical Characteristics  
Table 5-10 summarizes the DC electrical characteristics for LVCMOS Analog OSC Buffers.  
Table 5-10. LVCMOS Analog OSC Buffers DC Electrical Characteristics  
PARAMETER  
DESCRIPTION  
MIN  
NOM  
MAX  
UNIT  
Signal Names in MUXMODE 0: xi_osc0, xi_osc1;  
Balls ABF: E22, B21;  
VIH  
VIL  
IOH  
Input high-level threshold  
Input low-level threshold  
0.65×VDDS  
V
0.35×VDDS  
V
hfenable=0  
hfenable=1  
hfenable=0  
hfenable=1  
MODE-1  
1.18  
2
mA  
mA  
mA  
mA  
mV  
pF  
IOL  
2
3.2  
150  
12  
VHYS  
CPAD  
Input hysteresis voltage  
Capacitance connected on input and output Pad on  
Board, CL1=CL2  
24  
(1) VDDS stands for corresponding power supply (i.e. vdda_osc). For more information on the power supply name and the corresponding  
ball, see Table 4-2, POWER [11] column.  
5.7.6 LVCMOS CSI2 DC Electrical Characteristics  
Table 5-11 summarizes the DC electrical characteristics for LVSMOS CSI2 Buffers.  
Table 5-11. LVCMOS CSI2 DC Electrical Characteristics  
PARAMETER  
MIN  
NOM  
MAX  
UNIT  
Signals MUXMODE 0: csi2_0_dx[4:0]; csi2_0_dy[4:0];  
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Table 5-11. LVCMOS CSI2 DC Electrical Characteristics (continued)  
PARAMETER  
MIN  
NOM  
MAX  
UNIT  
Bottom Balls: A11 / B11 / A12 / B12 / A13 / B13 / A15 / B15 / A16 / B16  
MIPI D-PHY Mode Low-Power Receiver (LP-RX)  
VIH  
VIL  
Input high-level voltage  
Input low-level voltage  
Input high-level threshold(1)  
Input low-level threshold(2)  
Input hysteresis(3)  
880  
1350  
550  
mV  
mV  
mV  
mV  
mV  
VITH  
VITL  
VHYS  
880  
550  
25  
MIPI D-PHY Mode Ultralow Power Receiver (ULP-RX)  
VIL  
VITL  
VHYS  
Input low-level voltage  
Input low-level threshold(4)  
Input hysteresis(3)  
300  
mV  
mV  
mV  
300  
25  
MIPI D-PHY Mode High Speed Receiver (HS-RX)  
VIDTH  
VIDTL  
Differential input high-level threshold  
Differential input low-level threshold  
Maximum differential input voltage(7)  
Single-ended input high voltage(5)  
Single-ended input low voltage(5)  
Differential input common-mode voltage(5)(6)  
Differential input impedance  
70  
mV  
mV  
mV  
mV  
mV  
mV  
Ω
–70  
270  
460  
VIDMAX  
VIHHS  
VILHS  
–40  
70  
VCMRXDC  
ZID  
330  
125  
80  
100  
(1) VITH is the voltage at which the receiver is required to detect a high state in the input signal.  
(2) VITL is the voltage at which the receiver is required to detect a low state in the input signal. VITL is larger than the maximum single-ended  
line high voltage during HS transmission. Therefore, both low-power (LP) receivers will detect low during HS signaling.  
(3) To reduce noise sensitivity on the received signal, the LP receiver is required to incorporate a hysteresis, VHYST. VHYST is the difference  
between the VITH threshold and the VITL threshold.  
(4) VITL is the voltage at which the receiver is required to detect a low state in the input signal. Specification is relaxed for detecting 0 during  
ultralow power (ULP) state. The LP receiver is not required to detect HS single-ended voltage as 0 in this state.  
(5) Excluding possible additional RF interference of 200 mVPP beyond 450 MHz.  
(6) This value includes a ground difference of 50 mV between the transmitter and the receiver, the static common-mode level tolerance and  
variations below 450 MHz.  
(7) This number corresponds to the VODMAX transmitter.  
(8) Common mode is defined as the average voltage level of X and Y: VCMRX = (VX + VY) / 2.  
(9) Common mode ripple may be due to tR or tF and transmission line impairments in the PCB.  
5.7.7 Dual Voltage LVCMOS DC Electrical Characteristics  
Table 5-12 summarizes the DC electrical characteristics for Dual Voltage LVCMOS Buffers.  
Table 5-12. Dual Voltage LVCMOS DC Electrical Characteristics  
PARAMETER  
1.8-V Mode  
DESCRIPTION  
MIN  
NOM  
MAX  
UNIT  
VIH  
VIL  
Input high-level threshold  
0.65×VDDS  
V
V
Input low-level threshold  
0.35×VDDS  
VHYS  
VOH  
VOL  
Input hysteresis voltage  
100  
mV  
V
Output high-level threshold (IOH = 2 mA)  
Output low-level threshold (IOL = 2 mA)  
VDDS-0.45  
0.45  
16  
V
IDRIVE  
Pin Drive strength at PAD Voltage = 0.45 V or VDDS-  
0.45 V  
6
mA  
IIN  
Input current at each I/O pin  
µA  
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Table 5-12. Dual Voltage LVCMOS DC Electrical Characteristics (continued)  
PARAMETER  
DESCRIPTION  
MIN  
NOM  
MAX  
UNIT  
IOZ  
IOZ(IPAD Current) at each IO pin. PAD is swept from 0  
to VDDS and the Max(I(PAD)) is measured and is  
reported as IOZ  
11.5  
µA  
IIN with pulldown enabled  
IIN with pullup enabled  
Input current at each I/O pin with weak pulldown  
enabled measured when PAD = VDDS  
60  
60  
120  
120  
200  
210  
4
µA  
µA  
Input current at each I/O pin with weak pullup enabled  
measured when PAD = 0  
CPAD  
ZO  
Pad capacitance (including package capacitance)  
Output impedance (drive strength)  
pF  
40  
Ω
3.3-V Mode  
VIH  
VIL  
Input high-level threshold  
2
V
V
Input low-level threshold  
0.8  
0.2  
VHYS  
VOH  
VOL  
Input hysteresis voltage  
200  
mV  
V
Output high-level threshold (IOH =100 µA)  
Output low-level threshold (IOL = 100 µA)  
VDDS-0.2  
V
IDRIVE  
Pin Drive strength at PAD Voltage = 0.45 V or VDDS-  
0.45 V  
6
mA  
IIN  
Input current at each I/O pin  
64  
64  
µA  
µA  
IOZ  
IOZ(IPAD Current) at each IO pin. PAD is swept from 0  
to VDDS and the Max(I(PAD)) is measured and is  
reported as IOZ  
IIN with pulldown enabled  
IIN with pullup enabled  
Input current at each I/O pin with weak pulldown  
enabled measured when PAD = VDDS  
10  
40  
100  
100  
290  
200  
4
µA  
µA  
Input current at each I/O pin with weak pullup enabled  
measured when PAD = 0  
CPAD  
ZO  
Pad capacitance (including package capacitance)  
Output impedance (drive strength)  
pF  
40  
Ω
(1) VDDS stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Table 4-  
2, POWER [11] column.  
5.8 Thermal Characteristics  
For reliability and operability concerns, the maximum junction temperature of the Device has to be at or  
below the TJ value identified in Section 5.4, Recommended Operating Conditions.  
A BCI compact thermal model for this Device is available and recommended for use when modeling  
thermal performance in a system.  
Therefore, it is recommended to perform thermal simulations at the system level with the worst case  
device power consumption.  
5.8.1 Package Thermal Characteristics  
Table 5-13 provides the thermal resistance characteristics for the package used on this device.  
NOTE  
Power dissipation of 4.14 W and an ambient temperature of 65ºC is assumed for ABF  
package.  
Table 5-13. Thermal Resistance Characteristics  
NO.  
PARAMET DESCRIPTION  
ER  
°C/W(1)  
AIR FLOW (m/s)(2)  
T1  
RΘJC  
Junction-to-case  
1.41  
N/A  
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Table 5-13. Thermal Resistance Characteristics (continued)  
NO.  
PARAMET DESCRIPTION  
°C/W(1)  
AIR FLOW (m/s)(2)  
ER  
T2  
T3  
RΘJB  
Junction-to-board  
Junction-to-free air  
5.96  
15.4  
13.1  
12.2  
11.6  
0.94  
0.94  
0.94  
0.94  
5.12  
4.78  
4.63  
4.52  
N/A  
0
T4  
1
RΘJA  
T5  
Junction-to-moving air  
Junction-to-free air  
Junction-to-package top  
Junction-to-free air  
Junction-to-board  
2
T6  
3
T7  
0
T8  
1
ΨJT  
T9  
2
T10  
T11  
T12  
T13  
T14  
3
0
1
ΨJB  
2
3
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a  
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these  
EIA/JEDEC standards:  
JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)  
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages  
JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions - Forced Convection (Moving Air)  
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages  
JESD51-9, Test Boards for Area Array Surface Mount Packages  
(2) m/s = meters per second  
5.9 Analog-to-Digital ADC Subsystem Electrical Specifications  
The analog-to-digital converter (ADC) module is  
generalpurpose analog-to-digital converter.  
a
successive-approximation-register (SAR)  
The main features of the ADC include:  
10-bit data.  
8 general-purpose ADC channels.  
750 KSPS at 13.5-MHz ADC_CLK.  
Programmable FSM sequencer.  
Support interrupts and status, with masking  
Table 5-14 summarizes the ADC subsystem electrical specifications.  
Table 5-14. ADC Electrical Specifications  
PARAMETER  
Analog Input  
CONDITIONS  
MIN  
NOM  
MAX  
UNIT  
Full-scale Input Range  
Vref  
adc_vrefp  
V
V
Should be less than or equal to vdds_18v.  
1.62  
-1  
vdds_18v  
Differential Non-Linearity  
(DNL)  
1
LSB  
Integral Non-Linearity (INL)  
Gain Error  
adc_vrefp = vdds_18v  
adc_vrefp = vdds_18v  
adc_vrefp = vdds_18v  
±2  
LSB  
LSB  
LSB  
pF  
±4  
±3  
Offset Error  
Input Sampling Capacitance  
Input Frequency adc_in[7:0]  
3.2  
5
0
30  
kHz  
Input Signal: 30 kHz sine wave at -0.5 dB  
Full Scale  
Signal-to-Noise Ratio (SNR)  
50  
dB  
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Table 5-14. ADC Electrical Specifications (continued)  
PARAMETER  
CONDITIONS  
MIN  
NOM  
MAX  
UNIT  
Total Harmonic Distortion  
(THD)  
1.8 Vpp, 30 kHz sine wave  
60  
dB  
Spurious Free Dynamic  
Range  
1.8 Vpp, 30 kHz sine wave  
1.8 Vpp, 30 kHz sine wave  
60  
dB  
Signal-to-Noise Plus  
Distortion  
50  
20  
dB  
adc_vrefp Input Impedance  
Sampling Dynamics  
Ω
Time from Start to Start  
17  
10 + 1  
4
Clock Cycles  
Clock Cycles  
Clock Cycles  
MSPS  
Conversion Time + Error Correction  
Acquisition time  
Throughput Rate  
CLK = 20 MHz (Pin : clk)  
1
Channel to Channel Isolation  
90  
dB  
See  
Table 5-1  
ADC Clock Frequency  
MHz  
(1) Connect adc_vrefp to vdda_adc when not using a positive external reference voltage.  
(2) This parameter is valid when the respective AIN terminal is configured to operate as a general-purpose ADC input.  
(3) The maximum sample rate assumes a conversion time of 13 ADC clock cycles with the acquisition time configured for the minimum of 2  
ADC clock cycles, where it takes a total of 15 ADC clock cycles to sample the analog input and convert it to a positive binary weighted  
digital value.  
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5.10 Power Supply Sequences  
This section describes the power-up and power-down sequence required to ensure proper device  
operation.  
Figure 5-1 through Figure 5-5 and associated notes describes the device Recommended Power  
Sequencing.  
I/O Buffer Voltages  
vdds18v, vdds18v_ddr1, vdds18v_ddr2,  
vdds18v_ddr3  
Note 3  
Note 4  
PLL and Analog PHY Voltages  
EMIF Voltages  
vdda_adc, vdda_csi, vdda_dac, vdda_ddr_dsp,  
vdda_gmac_core, vdda_osc, vdda_per  
vdds_ddr1, vdds_ddr2, vdds_ddr3  
Note 5  
CORE AVS Voltage  
vdd  
Note 6  
DSPEVE AVS Voltage  
vdd_dspeve  
Note 7  
vddshv1, vddshv2, vddshv3,  
vddshv4, vddshv5(3), vddshv6  
xi_osc0  
Note 8  
resetn, porz  
Note 10  
Note 9  
sysboot[15:0]  
rstoutn  
Valid Config  
Note 11  
SPRS916_ELCH_01  
Figure 5-1. Power-Up Sequencing  
(1) Grey shaded areas are windows where it is valid to ramp-up a voltage rail.  
(2) Blue dashed lines are not valid windows but show alternate ramp-up possibilities based on whether I/O voltage levels are 1.8V or 3.3V  
(see associated note for more details).  
(3) vdds18v_* and vdda_* rails should not be combined for best performance to avoid transient switching noise impacts on analog domains.  
vdda_* should not ramp-up before vdds18v_* but could ramp concurrently if design ensures final operational voltage will not be reached  
until after vdds18v. The preferred sequence is to follow all vdds18v_* to ensure circuit components and PCB design do not cause an  
inadvertent violation.  
(4) vdds_ddr* should not ramp-up before vdds18v_*. The preferred sequence is to follow all vdds18v_* to ensure circuit components and  
PCB design do not cause an inadvertent violation. vdds_ddr* can ramp-up before, concurrently or after vdda_*, there are no  
dependencies between vdds_ddr* and vdda_* domains.  
vdds_ddr* supplies can be combined with vdds18v_* and vdds18v_ddr supplies for DDR2 mode of operation (1.8V) and ramped up  
together for simplified power sequencing.  
If vdds18v_ddr and vdds_ddr* are kept separate from vdds18v_* on board, then this combined DDR supply can come up together  
or after the vdds18v_* supply. The DDR supply in this case should never ramp up before the vdds18v_*.  
(5) vdd should not ramp-up before vdds18v_* or vdds_ddr* domains.  
(6) vdd_dspeve must not exceed vdd core supply and maintain at least 150mV lower voltage on vdd_dspeve vs vdd. vdd_dspeve could  
ramp concurrently with vdd if design ensures final operational voltage will not be reached until after vdd and maintains minimum of  
150mV less than vdd during entire ramp time. The preferred sequence is to follow vdd to ensure circuit components and PCB design do  
not cause an inadvertent violation.  
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(7) If any of the vddshv[1-6] power rails are used for 1.8V I/O signaling, then these rails can be combined with vdds18v_*.  
If 3.3V I/O signaling is required, then these rails must be the last to ramp following vdd_dspeve.  
(8) resetn and porz must remain asserted low for a minimum of 12P(12) after xi_osc0 is stable at a valid frequency.  
(9) Setup time: SYSBOOT[15:0] pins must be valid 2P(12) before porz is de-asserted high.  
(10) Hold time: SYSBOOT[15:0] pins must be valid 15P(12) after porz is de-asserted high.  
(11) resetn to rstoutn delay is 2ms.  
(12) P = 1/(SYS_CLK1/610) frequency in ns.  
(13) Ramped Up is defined as reaching the minimum operational voltage level for the corresponding power domain. For information about  
voltage levels, refer to , Recommended Operating Conditions.  
T0  
T1  
T2  
T3  
T4  
Note 4  
porz  
vddshv1, vddshv2, vddshv3,  
vddshv4, vddshv5, vddshv6  
Note 5  
Note 6  
V1  
Note 7  
Note 8  
DSPEVE voltage  
CORE voltage  
vdd_dspeve  
vdd  
EMIF voltage  
Note 9  
vdds_ddr1, vdds_ddr2, vdds_ddr3  
vdda_osc, vdda_per, vdda_ddr_dsp,  
vdda_gmac_core, vdda_csi,  
vdda_dac, vdda_adc  
Note 10  
Note 12  
Note 11  
vdds18v_ddr1, vdds18v_ddr2,  
vdds18v_ddr3, vdds18v,  
xi_osc0  
SPRS916_ELCH_02  
Figure 5-2. Recommended Power-Down Sequencing  
(1) T1 100 µs; T2 = 500 µs; T3 = 1.0 ms; T4 = 1.5 ms; V1 = 2.7 V. All "Tn" markers are intended to show total elapsed time, not interval  
times.  
(2) Terminology:  
VOPR MIN = Minimum Operational Voltage level that ensures device functionality and specified performance in , Recommended  
Operating Conditions.  
VOFF = OFF Voltage level is defined to be less than 0.6 V where any current draw has no impact to POH.  
Ramp Down = transition time from VOPR MIN to VOFF and is slew rate independent.  
(3) General timing diagram items:  
Grey shaded areas show valid transition times for supplies between VOPR MIN and VOFF.  
Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.  
Dashed vertical lines show approximate elapse times based upon TI recommended PMIC power-down sequencer circuit  
performance.  
(4) porz must be asserted low for 100 µs min to ensure SoC is set to a safe functional state before any voltage begins to ramp down.  
(5) vddshv[1-6] domains supplied by 3.3 V:  
must remain greater than 2.7 V to enable Dual Voltage GPIO selector circuit operation for 100 µs min after porz is asserted low.  
must be in first group of supplies ramping down after porz has been asserted low for 100 µs min.  
must not exceed vdds18v by more than 2 V during ramp down, see Figure 5-3, "vdds18v versus vddshv[1-6] Discharge  
Relationship".  
(6) vddshv[1-6] domains supplied by 1.8 V must ramp down concurrently with vdds18v and be sourced from common vdds18v supply.  
(7) vdd_dspeve domain can ramp down before or concurrently with vdd.  
(8) vdd must ramp down after or concurrently with vdd_dspeve.  
(9) vdds_ddr[1-3] domains:  
should ramp down after vdd begins ramping down.  
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If DDR2 memory is used (requiring 1.8V supply),  
then vdds_ddr[1-3] can be combined with vdds18v and vdds18v_ddr[1-3] domains and sourced from a common supply.  
Accordingly, all domains can ramp down concurrently with vdds18v.  
if vdds_ddr[1-3] and vdds18v_ddr[1-3] are combined but kept separate from vdds18v, then the combined 1.8V DDR supply can  
ramp down before or concurrently with vdds18v.  
(10) vdda_* domains:  
can ramp down before, concurrently or after vdds_ddr[1-3], there is no dependency between these supplies.  
can ramp down before or concurrently with vdds18v.  
must satisfy the vdds18v versus vdda_* discharge relationship (see Figure 5-5) if any of the vdda_* disable point is later or  
discharge rate is slower than vdds18v.  
(11) vdds18v domain:  
should maintain VOPR MIN (VNOM -5% = 1.71 V) until all other supplies start to ramp down.  
must satisfy the vdds18v versus vddshv[1-6] discharge relationship (see Figure 5-3) if any of the vddshv[1-6] is operating at 3.3 V.  
must satisfy the vdds18v versus vdds_ddr[1-3] discharge relationship (see Figure 5-4) if vdds_ddr[1-3] discharge rate is slower than  
vdds18v.  
Figure 5-3 describes vddshv[1-6] supplies falling before vdds18v supplies delta.  
vddshv1, vddshv2, vddshv3,  
vddshv4, vddshv5, vddshv6  
vdds18v  
Vdelta  
(Note1)  
SPRS916_ELCH_03  
Figure 5-3. vdds18v versus vddshv[1-6] Discharge Relationship  
(1) Vdelta MAX = 2 V  
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If vdds18v and vdds_ddr* are disabled at the same time due to a loss of input power event or if vdds_ddr*  
discharges more slowly than vdds18v, analysis has shown no reliability impacts when the elapsed time  
period beginning with vdds18v dropping below 1.0 V and ending with vdds_ddr* dropping below 0.6 V is  
less than 10 ms (Figure 5-4).  
vdds18v  
vdds_ddr1, vdds_ddr2,  
vdds_ddr3  
V1  
V2  
T1  
SPRS916_ELCH_04  
Figure 5-4. vdds18v and vdds_ddr* Discharge Relationship(1)  
(1) V1 > 1.0 V; V2 < 0.6 V; T1 < 10 ms.  
Note 1  
vdds18v  
vdda_*  
V1  
Note 2  
V2  
SPRS916_ELCH_05  
Figure 5-5. vdds18v and vdda_* Discharge Relationship(3)  
(1) vdda_* can be vdds18v, until vdds18v drops below 1.62 V.  
(2) vdds18v must be vdda_*, until vdds18v reaches 0.6 V.  
(3) V1 = 1.62 V; V2 < 0.6 V.  
102  
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Figure 5-3 through Figure 5-6 and associated notes described the device Abrupt Power Down Sequence.  
A ”loss of input power event” occurs when the system’s input power is unexpectedly removed. Normally,  
the recommended power-down sequence should be followed and can be accomplished within 1.5-2 ms of  
elapsed time. This is the typical range of elapsed time available following a loss of power event, see  
Section 8.3.7, Loss of Input Power Event for design recommendations. If sufficient elapse time is not  
provided, then an “abrupt” power-down sequence can be supported without impacting POH reliability if all  
of the following conditions are met (Figure 5-6).  
Tdelta1  
Note 4  
porz  
V2  
Note 5  
V3  
vddshv1, vddshv2, vddshv3,  
V1  
vddshv4, vddshv5, vddshv6  
Note 7  
vdd, vdd_dspeve  
Note 7, Note 8  
V4  
vdds_ddr1, vdds_ddr2, vdds_dd3  
Note 9  
V7  
V8  
vdda_osc, vdda_per, vdda_ddr_dsp,  
vdda_gmac_core, vdda_csi,  
vdda_dac, vdda_adc  
V5  
V6  
Tdelta2  
vddshv1, vddshv2, vddshv3,  
vddshv4, vddshv5, vddshv6,  
vdds18v_ddr1, vdds18v_ddr2,  
vdds18v_ddr3, vdds18v  
V9  
Note 6, Note 10  
V10  
V11  
xi_osc0  
SPRS916_ELCH_06  
Figure 5-6. Abrupt Power-Down Sequencing(1)  
(1) V1 = 2.7 V; V2 = 3.3 V; V3 = 2.0 V; V4 = V5 = V6 = 0.6 V; V7 = V8 = 1.62 V; V9 = 1.3 V; V10 = 1.0 V; V11 = 0.0 V; Tdelta1 > 100 µs;  
Tdelta2 < 10 ms.  
(2) Terminology:  
VOPR MIN = Minimum Operational Voltage level that ensures device functionality and specified performance in , Recommended  
Operating Conditions.  
VOFF = OFF Voltage level is defined to be less than 0.6 V, where any current draw has no impact to POH.  
Ramp Down = transition time from VOPR MIN to VOFF and is slew rate independent.  
(3) General timing diagram items:  
Grey shaded areas show valid transition times for supplies between VOPR MIN and VOFF.  
Dashed vertical lines show approximate elapse times based upon TI recommended PMIC power-down sequencer circuit  
performance.  
(4) porz must be asserted low for 100 µs min to ensure SoC is set to a safe functional state before any voltage begins to ramp down.  
(5) vddshv[1-6] domains supplied by 3.3 V:  
must remain greater than 2.7 V to enable Dual Voltage GPIO selector circuit operation for 100µs min, after porz is asserted low.  
must not exceed vdds18v voltage level by more than 2V during ramp down, until vdds18v drops below VOFF (0.6 V).  
(6) vddshv[1-6] domains supplied by 1.8 V must ramp down concurrently with vdds18v and be sourced from common vdds18v supply.  
(7) vdd_dspeve, vdd, vdds_ddr[1-3], vdda_* domains can all start to ramp down in any order after 100 µs low assertion of porz.  
(8) vdds_ddr* domains:  
can remain at VOPR MIN or a level greater than vdds18v during ramp down.  
elapsed time from vdds18v dropping below 1.0 V to vdds_ddr[1-3] dropping below 0.6 V must not exceed 10 ms.  
(9) vdda_* domains:  
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can start to ramp down before or concurrently with vdds18v.  
must not exceed vdds18v voltage level after vdds18v drops below 1.62 V until vdds18v drops below VOFF (0.6 V).  
(10) vdds18v domain should maintain a minimum level of 1.62 V (VNOM – 10%) until vdd_dspeve and vdd start to ramp down.  
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6 Clock Specifications  
NOTE  
For more information, see Power, Reset, and Clock Management / PRCM Subsystem  
Environment / External Clock Signals and Clock Management Functional Description section  
of the Device TRM.  
NOTE  
Audio Back End (ABE) module is not supported for this family of devices, but “ABE” name is  
still present in some clock or DPLL names.  
The device operation requires the following clocks:  
The system clocks, SYS_CLK1 (Mandatory) and SYS_CLK2 (Optional) are the main clock sources of  
the device. They supply the reference clock to the DPLLs as well as functional clock to several  
modules.  
Figure 6-1 shows the external input clock sources and the output clocks to peripherals.  
DEVICE  
rstoutn  
Warm reset output.  
Device reset input.  
Power ON Reset.  
resetn  
porz  
From quartz (19.2, 20 or 27 MHz)  
or from CMOS square clock source (19.2, 20 or 27MHz).  
xi_osc0  
xo_osc0  
To quartz (from oscillator output).  
From quartz (range from 19.2 to 32 MHz)  
or from CMOS square clock source(range from 12 to 38.4 MHz).  
xi_osc1  
xo_osc1  
clkout0  
clkout1  
clkout2  
To quartz (from oscillator output).  
Output clkout[0:2] clocks come from:  
• Either the input system clock and alternate clock (xi_osc0 or xi_osc1)  
• Or a CORE clock (from CORE output)  
• Or a 192-MHz clock (from PER DPLL output).  
xref_clk0  
xref_clk1  
External Reference Clock [0:2].  
For Audio and other Peripherals  
xref_clk2  
Boot Mode Configuration  
sysboot[15:0]  
SPRS91v_CLK_01_SR2.0  
Figure 6-1. Clock Interface  
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6.1 Input Clock Specifications  
6.1.1 Input Clock Requirements  
The source of the internal system clock (SYS_CLK1) could be either:  
A CMOS clock that enters on the xi_osc0 ball (with xo_osc0 left unconnected on the CMOS clock  
case).  
A crystal oscillator clock managed by xi_osc0 and xo_osc0.  
The source of the internal system clock (SYS_CLK2) could be either:  
A CMOS clock that enters on the xi_osc1 ball (with xo_osc1 left unconnected on the CMOS clock  
case).  
A crystal oscillator clock managed by xi_osc1 and xo_osc1.  
6.1.2 System Oscillator OSC0 Input Clock  
SYS_CLK1 is received directly from oscillator OSC0. For more information about SYS_CLK1, see the  
Power, Reset, and Clock Management section in the device TRM.  
6.1.2.1 OSC0 External Crystal  
An external crystal is connected to the device pins. Figure 6-2 describes the crystal implementation.  
Device  
xo_osc0  
vssa_osc0  
xi_osc0  
Rd  
(Optional)  
Crystal  
Cf2  
Cf1  
SPRS91v_CLK_02  
Figure 6-2. Crystal Implementation  
NOTE  
The load capacitors, Cf1 and Cf2 in Figure 6-2, should be chosen such that the below  
equation is satisfied. CL in the equation is the load specified by the crystal manufacturer. All  
discrete components used to implement the oscillator circuit should be placed as close as  
possible to the associated oscillator xi_osc0, xo_osc0, and vssa_osc0 pins.  
Cf1Cf2  
C
= (Cf1+Cf2)  
L
Figure 6-3. Load Capacitance Equation  
The crystal must be in the fundamental mode of operation and parallel resonant. Table 6-1 summarizes  
the required electrical constraints.  
106  
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Table 6-1. OSC0 Crystal Electrical Characteristics  
NAME  
fp  
DESCRIPTION  
Parallel resonance crystal frequency  
MIN  
TYP  
MAX  
UNIT  
MHz  
pF  
19.2, 20, 27  
Cf1  
Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2  
Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2  
12  
12  
24  
24  
Cf2  
pF  
ESR(Cf1,Cf2) Crystal ESR  
100  
Ω
ESR = 30 Ω  
ESR = 40 Ω  
19.2 MHz, 20 MHz, 27  
MHz  
7
pF  
19.2 MHz, 20 MHz  
27 MHz  
7
5
7
pF  
pF  
pF  
-
ESR = 50 Ω  
ESR = 60 Ω  
ESR = 80 Ω  
ESR = 100 Ω  
19.2 MHz, 20 MHz  
27 MHz  
CO  
Crystal shunt capacitance  
Not Supported  
Not Supported  
19.2 MHz, 20 MHz  
27 MHz  
5
3
pF  
-
19.2 MHz, 20 MHz  
27 MHz  
pF  
-
Not Supported  
10.16  
LM  
Crystal motional inductance for fp = 20 MHz  
mH  
fF  
CM  
Crystal motional capacitance  
3.42  
Ethernet not used  
±200  
±50  
ppm  
tj(xiosc0)  
Frequency accuracy(1), xi_osc0  
Ethernet RGMII using  
derived clock  
ppm  
(1) Crystal characteristics should account for tolerance+stability+aging.  
When selecting a crystal, the system design must take into account the temperature and aging  
characteristics of a crystal versus the user environment and expected lifetime of the system.  
Table 6-2 details the switching characteristics of the oscillator and the requirements of the input clock.  
Table 6-2. Oscillator Switching Characteristics-Crystal Mode  
NAME  
fp  
DESCRIPTION  
MIN  
TYP  
MAX  
UNIT  
MHz  
ms  
Oscillation frequency  
Start-up time  
19.2, 20, 27 MHz  
tsX  
4
6.1.2.2 OSC0 Input Clock  
A 1.8-V LVCMOS-compatible clock input can be used instead of the internal oscillator to provide the  
SYS_CLK1 clock input to the system. The external connections to support this are shown in Figure 6-4.  
The xi_osc0 pin is connected to the 1.8-V LVCMOS-compatible clock source. The xi_osc0 pin is left  
unconnected. The vssa_osc0 pin is connected to board ground (vss).  
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Device  
xo_osc0  
vssa_osc0  
xi_osc0  
NC  
SPRS91v_CLK_03  
Figure 6-4. 1.8-V LVCMOS-Compatible Clock Input  
Table 6-3 summarizes the OSC0 input clock electrical characteristics.  
Table 6-3. OSC0 Input Clock Electrical Characteristics-Bypass Mode  
NAME  
DESCRIPTION  
MIN  
TYP  
19.2, 20, 27  
2.384  
MAX  
UNIT  
MHz  
pF  
f
Frequency  
CIN  
IIN  
Input capacitance  
2.184  
4
2.584  
10  
Input current (3.3V mode)  
6
µA  
Table 6-4 details the OSC0 input clock timing requirements.  
Table 6-4. OSC0 Input Clock Timing Requirements  
NAME  
CK0  
DESCRIPTION  
1 / tc(xiosc0) Frequency, xi_osc0  
MIN  
TYP  
MAX  
UNIT  
MHz  
ns  
19.2, 20, 27  
CK1  
tw(xiosc0)  
tj(xiosc0)  
tR(xiosc0)  
tF(xiosc0)  
Pulse duration, xi_osc0 low or high  
Period jitter(1), xi_osc0  
Rise time, xi_osc0  
0.45 × tc(xiosc0)  
0.55 × tc(xiosc0)  
0.01 × tc(xiosc0)  
ns  
5
5
ns  
Fall time, xi_osc0  
ns  
Ethernet not used  
±200  
ppm  
tj(xiosc0)  
Frequency accuracy(2), xi_osc0  
Ethernet RGMII using  
derived clock  
±50  
ppm  
(1) Period jitter is meant here as follows:  
– The maximum value is the difference between the longest measured clock period and the expected clock period  
– The minimum value is the difference between the shortest measured clock period and the expected clock period  
(2) Crystal characteristics should account for tolerance+stability+aging.  
CK0  
CK1  
CK1  
xi_osc0  
SPRS91v_CLK_04  
Figure 6-5. xi_osc0 Input Clock  
6.1.3 Auxiliary Oscillator OSC1 Input Clock  
SYS_CLK2 is received directly from oscillator OSC1. For more information about SYS_CLK2, see the  
Power, Reset, and Clock Management section in the device TRM.  
108  
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6.1.3.1 OSC1 External Crystal  
An external crystal is connected to the device pins. Figure 6-6 describes the crystal implementation.  
Device  
xo_osc1  
xi_osc1  
vssa_osc1  
Rd  
(Optional)  
Crystal  
Cf2  
Cf1  
SPRS91v_CLK_05  
Figure 6-6. Crystal Implementation  
NOTE  
The load capacitors, Cf1 and Cf2 in Figure 6-6, should be chosen such that the below  
equation is satisfied. CL in the equation is the load specified by the crystal manufacturer. All  
discrete components used to implement the oscillator circuit should be placed as close as  
possible to the associated oscillator xi_osc1, xo_osc1, and vssa_osc1 pins.  
Cf1Cf2  
C
= (Cf1+Cf2)  
L
Figure 6-7. Load Capacitance Equation  
The crystal must be in the fundamental mode of operation and parallel resonant. Table 6-5 summarizes  
the required electrical constraints.  
Table 6-5. OSC1 Crystal Electrical Characteristics  
NAME  
fp  
DESCRIPTION  
Parallel resonance crystal frequency  
MIN  
TYP  
MAX  
UNIT  
MHz  
pF  
Range from 19.2 to 32  
Cf1  
Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2  
Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2  
12  
12  
24  
24  
Cf2  
pF  
ESR(Cf1,Cf2) Crystal ESR  
100  
Ω
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Table 6-5. OSC1 Crystal Electrical Characteristics (continued)  
NAME  
DESCRIPTION  
ESR = 30 Ω  
ESR = 40 Ω  
MIN  
TYP  
MAX  
UNIT  
pF  
pF  
pF  
pF  
-
19.2 MHz fp 32 MHz  
19.2 MHz fp 32 MHz  
19.2 MHz fp 25 MHz  
25 MHz < fp 27 MHz  
27 MHz < fp 32 MHz  
19.2 MHz fp 23 MHz  
23 MHz < fp 25 MHz  
25 MHz < fp 32 MHz  
19.2 MHz fp 23 MHz  
23 MHz < fp 25 MHz  
25 MHz < fp 32 MHz  
19.2 MHz fp 20 MHz  
20 MHz < fp 32 MHz  
7
5
7
5
ESR = 50 Ω  
ESR = 60 Ω  
Not Supported  
Not Supported  
Not Supported  
7
5
pF  
pF  
-
CO  
Crystal shunt capacitance  
5
3
pF  
pF  
-
ESR = 80 Ω  
3
pF  
-
ESR = 100 Ω  
Not Supported  
10.16  
LM  
Crystal motional inductance for fp = 20 MHz  
Crystal motional capacitance  
mH  
fF  
CM  
3.42  
Ethernet not used  
±200  
±50  
ppm  
tj(xiosc0)  
Frequency accuracy(1), xi_osc1  
Ethernet RGMII using  
derived clock  
ppm  
(1) Crystal characteristics should account for tolerance+stability+aging.  
When selecting a crystal, the system design must take into account the temperature and aging  
characteristics of a crystal versus the user environment and expected lifetime of the system.  
Table 6-6 details the switching characteristics of the oscillator and the requirements of the input clock.  
Table 6-6. Oscillator Switching Characteristics-Crystal Mode  
NAME  
fp  
DESCRIPTION  
MIN  
TYP  
MAX  
UNIT  
MHz  
ms  
Oscillation frequency  
Start-up time  
Range from 19.2 to 32  
tsX  
4
6.1.3.2 OSC1 Input Clock  
A 1.8-V LVCMOS-compatible clock input can be used instead of the internal oscillator to provide the  
SYS_CLK2 clock input to the system. The external connections to support this are shown in, Figure 6-8.  
The xi_osc1 pin is connected to the 1.8-V LVCMOS-compatible clock sources. The xo_osc1 pin is left  
unconnected. The vssa_osc1 pin is connected to board ground (VSS).  
110  
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Device  
xo_osc1  
vssa_osc1  
xi_osc1  
NC  
SPRS91v_CLK_06  
Figure 6-8. 1.8-V LVCMOS-Compatible Clock Input  
Table 6-7 summarizes the OSC1 input clock electrical characteristics.  
Table 6-7. OSC1 Input Clock Electrical Characteristics—Bypass Mode  
NAME  
f
DESCRIPTION  
MIN  
TYP  
MAX  
UNIT  
MHz  
pF  
Frequency  
Range from 12 to 38.4  
CIN  
IIN  
Input capacitance  
2.819  
4
3.019  
3.219  
10  
Input current (3.3V mode)  
Start-up time(1)  
6
µA  
tsX  
See(2)  
ms  
(1) To switch from bypass mode to crystal or from crystal mode to bypass mode, there is a waiting time about 100 μs; however, if the chip  
comes from bypass mode to crystal mode the crystal will start-up after time mentioned in Table 6-6, tsX parameter.  
(2) Before the processor boots up and the oscillator is set to bypass mode, there is a waiting time when the internal oscillator is in  
application mode and receives a wave. The switching time in this case is about 100 μs.  
Table 6-8 details the OSC1 input clock timing requirements.  
Table 6-8. OSC1 Input Clock Timing Requirements  
NAME  
CK0  
DESCRIPTION  
1 / tc(xiosc1) Frequency, xi_osc1  
MIN  
TYP  
MAX  
UNIT  
MHz  
ns  
Range from 12 to 38.4  
CK1  
tw(xiosc1)  
tj(xiosc1)  
tR(xiosc1)  
tF(xiosc1)  
Pulse duration, xi_osc1 low or high  
Period jitter(1), xi_osc1  
Rise time, xi_osc1  
0.45 × tc(xiosc1)  
0.55 × tc(xiosc1)  
(3)  
0.01 × tc(xiosc1)  
ns  
5
5
ns  
Fall time, xi_osc1  
ns  
Ethernet not used  
±200  
ppm  
tj(xiosc1)  
Frequency accuracy(2), xi_osc1  
Ethernet RGMII using  
derived clock  
±50  
ppm  
(1) Period jitter is meant here as follows:  
– The maximum value is the difference between the longest measured clock period and the expected clock period  
– The minimum value is the difference between the shortest measured clock period and the expected clock period  
(2) Crystal characteristics should account for tolerance+stability+aging.  
(3) The Period jitter requirement for osc1 can be relaxed to 0.02*tc(xiosc1) under the following constraints:  
a. The osc1/SYS_CLK2 clock bypasses all device PLLs  
b. The osc1/SYS_CLK2 clock is only used to source the DSS pixel clock outputs  
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CK0  
CK1  
CK1  
xi_osc1  
SPRS91v_CLK_07  
Figure 6-9. xi_osc1 Input Clock  
6.1.4 RC On-die Oscillator Clock  
RCOSC_32K_CLK is received directly through a network of resistor and capacitor (an RC network) inside  
of the SoC. This RC oscillator do not have good frequency stability. The Frequency range is described in  
Table 6-9, which depends on the temperature. For more information about RCOSC_32K_CLK see the  
Device TRM, Chapter: Power, Reset, and Clock Management.  
Table 6-9. RC On-die Oscillator Clock Frequency Range  
NAME  
DESCRIPTION  
MIN  
TYP  
MAX  
UNIT  
RCOSC_32K_CLK Internal RC Oscillator  
Range from 28 to 42  
kHz  
6.2 DPLLs, DLLs Specifications  
NOTE  
For more information, see:  
Power, Reset, and Clock Management / Clock Management Functional Description /  
Internal Clock Sources / Generators / Generic DPLL Overview Section  
and  
Display Subsystem / Display Subsystem Overview section of the Device TRM.  
To generate high-frequency clocks, the device supports multiple on-chip DPLLs controlled directly by the  
PRCM module.  
They have their own independent power domain (each one embeds its own switch and can be  
controlled as an independent functional power domain)  
They are fed with ALWAYS ON system clock, with independent control per DPLL.  
The different DPLLs managed by the PRCM are listed below:  
DPLL_CORE: It supplies all interface clocks and also few module functional clocks.  
DPLL_PER: It supplies several clock sources: a 192-MHz clock for the display functional clock , a  
96-MHz functional clock to subsystems and peripherals.  
DPLL_GMAC_DSP: It supplies RGMII, EVE1 and DSP0 module functional clocks.  
DPLL_EVE_VID_DSP: It provides a few module functional clocks (EVE_GFCLK, VID_PIX_CLK  
and DSP1_CLK).  
DPLL_DDR: It generates clocks for the one External Memory Interface (EMIF) controller and its  
associated EMIF PHYs.  
NOTE  
The following DPLLs are controlled by the clock manager located in the always-on Core  
power domain (CM_CORE_AON):  
DPLL_CORE, DPLL_DDR, DPLL_GMAC_DSP, DPLL_PER, DPLL_EVE_VID_DSP.  
For more information on CM_CORE_AON and CM_CORE or PRCM DPLLs, see the Power, Reset, and  
Clock Management (PRCM) chapter of the Device TRM.  
112  
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6.2.1 DPLL Characteristics  
The DPLL has three relevant input clocks. One of them is the reference clock (CLKINP) used to generated  
the synthesized clock but can also be used as the bypass clock whenever the DPLL enters a bypass  
mode. It is therefore mandatory. The second one is a fast bypass clock (CLKINPULOW) used when  
selected as the bypass clock and is optional. The third clock (CLKINPHIF) is explained in the next  
paragraph.  
The DPLL has three output clocks (namely CLKOUT, CLKOUTX2, and CLKOUTHIF). CLKOUT and  
CLKOUTX2 run at the bypass frequency whenever the DPLL enters a bypass mode. Both of them are  
generated from the lock frequency divided by a post-divider (namely M2 post-divider). The third clock,  
CLKOUTHIF, has no automatic bypass capability. It is an output of a post-divider (M3 post-divider) with  
the input clock selectable between the internal lock clock (Fdpll) and CLKINPHIF input of the PLL through  
an asynchronous multplexing.  
For more information, see the Power, Reset, and Clock Management chapter of the Device TRM.  
Table 6-10 summarizes DPLL type described in Section 6.2, DPLLs, DLLs Specifications.  
Table 6-10. DPLL Control  
DPLL NAME  
DPLL_CORE  
CONTROLLED BY PRCM  
(1)  
Yes  
(1)  
DPLL_EVE_VID_DSP  
DPLL_GMAC_DSP  
DPLL_PER  
Yes  
(1)  
Yes  
(1)  
Yes  
(1)  
DPLL_DDR  
Yes  
(1) DPLL is in the always-on domain.  
Table 6-11 and summarize the DPLL characteristics and assume testing over recommended operating  
conditions.  
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Table 6-11. DPLL Characteristics  
NAME  
finput  
DESCRIPTION  
MIN  
0.032  
0.15  
10  
TYP  
MAX  
52  
UNIT  
MHz  
MHz  
MHz  
COMMENTS  
CLKINP input frequency  
Internal reference frequency  
CLKINPHIF input frequency  
FINP  
finternal  
52  
REFCLK  
FINPHIF  
fCLKINPHIF  
1400  
Bypass mode: fCLKOUT  
=
fCLKINPULOW  
CLKINPULOW input frequency  
0.001  
600  
MHz  
MHz  
fCLKINPULOW / (M1 + 1) if  
ulowclken = 1  
(6)  
[M / (N + 1)] × FINP × [1 / M2]  
(in locked condition)  
(1)  
(2)  
fCLKOUT  
CLKOUT output frequency  
CLKOUTx2 output frequency  
20  
1800  
2 × [M / (N + 1)] × FINP × [1 /  
M2] (in locked condition)  
(1)  
(2)  
(4)  
(4)  
fCLKOUTx2  
40  
2200  
1400  
2200  
MHz  
MHz  
MHz  
(3)  
20  
FINPHIF / M3 if clkinphifsel = 1  
fCLKOUTHIF  
CLKOUTHIF output frequency  
2 × [M / (N + 1)] × FINP × [1 /  
M3] if clkinphifsel = 0  
(3)  
40  
DCOCLKLDO output  
frequency  
2 × [M / (N + 1)] × FINP (in  
locked condition)  
fCLKDCOLDO  
tlock  
40  
2800  
MHz  
µs  
6 + 350 ×  
REFCLK  
Frequency lock time  
Phase lock time  
6 + 500 ×  
REFCLK  
plock  
µs  
(5)  
Relock time—Frequency lock  
(LP relock time from bypass)  
6 + 70 ×  
REFCLK  
DPLL in LP relock time:  
lowcurrstdby = 1  
trelock-L  
prelock-L  
trelock-F  
prelock-F  
µs  
(5)  
Relock time—Phase lock (LP  
relock time from bypass)  
6 + 120 ×  
REFCLK  
DPLL in LP relock time:  
lowcurrstdby = 1  
µs  
(5)  
Relock time—Frequency lock  
(fast relock time from bypass)  
3.55 + 70 ×  
REFCLK  
DPLL in fast relock time:  
lowcurrstdby = 0  
µs  
(5)  
Relock time—Phase lock  
3.55 + 120 ×  
REFCLK  
DPLL in fast relock time:  
lowcurrstdby = 0  
µs  
(fast relock time from bypass)  
(1) The minimum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1.  
For M2 > 1, the minimum frequency on these clocks will further scale down by factor of M2.  
(2) The maximum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1.  
(3) The minimum frequency on CLKOUTHIF is assuming M3 = 1. For M3 > 1, the minimum frequency on this clock will further scale down  
by factor of M3.  
(4) The maximum frequency on CLKOUTHIF is assuming M3 = 1.  
(5) Relock time assumes typical operating conditions, 10°C maximum temperature drift.  
(6) Bypass mode: fCLKOUT = FINP if ulowclken = 0. For more information, see the Device TRM.  
114  
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6.2.2 DLL Characteristics  
Table 6-12 summarizes the DLL characteristics and assumes testing over recommended operating  
conditions.  
Table 6-12. DLL Characteristics  
NAME  
finput  
DESCRIPTION  
Input clock frequency (EMIF_DLL_FCLK)  
MIN  
TYP  
MAX  
266  
50k  
UNIT  
MHz  
tlock  
Lock time  
cycles  
cycles  
trelock  
Relock time (a change of the DLL frequency implies that DLL must relock)  
50k  
6.2.2.1 DPLL and DLL Noise Isolation  
NOTE  
For more information on DPLL and DLL decoupling capacitor requirements, see the External  
Capacitors / Voltage Decoupling Capacitors / I/O and Analog Voltage Decoupling / VDDA  
Power Domain section.  
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7 Timing Requirements and Switching Characteristics  
7.1 Timing Test Conditions  
All timing requirements and switching characteristics are valid over the recommended operating conditions  
unless otherwise specified.  
7.2 Interface Clock Specifications  
7.2.1 Interface Clock Terminology  
The interface clock is used at the system level to sequence the data and/or to control transfers accordingly  
with the interface protocol.  
7.2.2 Interface Clock Frequency  
The two interface clock characteristics are:  
The maximum clock frequency  
The maximum operating frequency  
The interface clock frequency documented in this document is the maximum clock frequency, which  
corresponds to the maximum frequency programmable on this output clock. This frequency defines the  
maximum limit supported by the Device IC and does not take into account any system consideration  
(PCB, peripherals).  
The system designer will have to consider these system considerations and the Device IC timing  
characteristics as well to define properly the maximum operating frequency that corresponds to the  
maximum frequency supported to transfer the data on this interface.  
7.3 Timing Parameters and Information  
The timing parameter symbols used in the timing requirement and switching characteristic tables are  
created in accordance with JEDEC Standard 100. To shorten the symbols, some of pin names and other  
related terminologies have been abbreviated as follows:  
Table 7-1. Timing Parameters  
SUBSCRIPTS  
SYMBOL  
PARAMETER  
c
Cycle time (period)  
d
Delay time  
dis  
Disable time  
en  
Enable time  
h
Hold time  
su  
Setup time  
START  
Start bit  
t
v
Transition time  
Valid time  
w
X
F
Pulse duration (width)  
Unknown, changing, or don't care level  
Fall time  
High  
H
L
Low  
R
V
IV  
Rise time  
Valid  
Invalid  
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Table 7-1. Timing Parameters (continued)  
SUBSCRIPTS  
SYMBOL  
PARAMETER  
Active Edge  
First Edge  
AE  
FE  
LE  
Z
Last Edge  
High impedance  
7.3.1 Parameter Information  
Tester Pin Electronics  
Transmission Line  
Data Sheet Timing Reference Point  
42 Ω  
3.5 nH  
Output  
Under  
Test  
Z0 = 50 Ω  
(see Note)  
Device Pin  
(see Note)  
4.0 pF  
1.85 pF  
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be  
taken into account.Atransmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission line is  
intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings.  
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.  
pm_tstcirc_prs403  
Figure 7-1. Test Load Circuit for AC Timing Measurements  
The load capacitance value stated is only for characterization and measurement of AC timing signals.  
This load capacitance value does not indicate the maximum load the device is capable of driving.  
7.3.1.1 1.8 V and 3.3 V Signal Transition Levels  
All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. Vref  
(VDDI/O)/2.  
=
Vref  
pm_io_volt_prs403  
Figure 7-2. Input and Output Voltage Reference Levels for AC Timing Measurements  
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL  
MAX and VOH MIN for output clocks.  
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Vref = VIH MIN (or VOH MIN)  
Vref = VIL MAX (or VOL MAX)  
pm_transvolt_prs403  
Figure 7-3. Rise and Fall Transition Time Voltage Reference Levels  
7.3.1.2 1.8 V and 3.3 V Signal Transition Rates  
The default SLEWCONTROL settings in each pad configuration register must be used to ensured timings,  
unless specific instructions otherwise are given in the individual timing subsections of the datasheet.  
All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).  
7.3.1.3 Timing Parameters and Board Routing Analysis  
The timing parameter values specified in this data manual do not include delays by board routes. As a  
good board design practice, such delays must always be taken into account. Timing values may be  
adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer  
information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS  
models to attain accurate timing analysis for a given system, see the Using IBIS Models for timing  
Analysis application report. If needed, external logic hardware such as buffers may be used to  
compensate any timing differences.  
7.4 Recommended Clock and Control Signal Transition Behavior  
All clocks and control signals must transition between VIH and V (or between VIL and VIH) in a monotonic  
IL  
manner. Monotonic transitions are more easily ensured with faster switching signals. Slower input  
transitions are more susceptible to glitches due to noise and special care should be taken for slow input  
clocks.  
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7.5 Video Input Ports (VIP)  
The device includes 1 Video Input Ports (VIP).  
Table 7-2, Figure 7-4 and Figure 7-5 present timings and switching characteristics of the VIPs  
(1)(2)  
Table 7-2. Timing Requirements for VIP  
NO.  
V1  
V2  
V3  
V4  
PARAMETER  
tc(CLK)  
DESCRIPTION  
MODE  
MIN  
MAX  
UNIT  
ns  
(3)(5)  
(1)  
Cycle time, vinx_clki  
5.99  
0.45×P  
0.45×P  
2.52  
2.52  
3.7  
(3)(5)  
(2)  
(2)  
tw(CLKH)  
Pulse duration, vinx_clki high  
ns  
(3)(5)  
tw(CLKL)  
Pulse duration, vinx_clki low  
ns  
tsu(CTL/DATA-CLK)  
Input setup time, Control (vinx_dei,  
vinx_vsynci, vinx_fldi, vinx_hsynci) and  
Data (vinx_dn) valid to vinx_clki transition  
All other IOSETs  
VIN2 IOSET4  
VIN2 IOSET5  
VIN2 IOSET6  
All other IOSETs  
VIN2 IOSET4  
VIN2 IOSET5  
VIN2 IOSET6  
ns  
ns  
(3)(4)(5)  
ns  
4.2  
ns  
V5  
th(CLK-CTL/DATA)  
Input hold time, Control (vinx_dei,  
vinx_vsynci, vinx_fldi, vinx_hsynci) and  
Data (vinx_dn) valid from vinx_clki  
-0.05  
3
ns  
ns  
(3)(4)(5)  
1
ns  
transition  
1
ns  
(1) For maximum frequency of 165 MHz.  
(2) P = vinx_clki period.  
(3) x in vinx = 1a, 1b, 2a and 2b.  
(4) n in dn = 0 to 7 when x = 1b, 2b;  
n = 0 to 23 when x = 1a and 2a;  
(5) i in clki, dei, vsynci, hsynci and fldi = 0 or 1.  
V3  
V2  
V1  
vinx_clki  
SPRS91v_VIP_01  
Figure 7-4. Video Input Ports Clock Signal  
vinx_clki  
(positive-edge clocking)  
vinx_clki  
(negative-edge clocking)  
V5  
V4  
vinx_d[23:0]/sig  
SPRS8xx_VIP_02  
Figure 7-5. Video Input Ports Timings  
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CAUTION  
The IO timings provided in this section are only valid for VIN1 and VIN2 if  
signals within a single IOSET are used. The IOSETs are defined in Table 7-3  
and Table 7-4.  
In Table 7-3 and Table 7-4 are presented the specific groupings of signals (IOSET) for use with vin1a,  
vin1b, vin2a and vin2b.  
Table 7-3. VIN1 IOSETs  
SIGNALS  
IOSET1  
IOSET2  
IOSET3  
IOSET4  
BALL  
MUX  
BALL  
MUX  
BALL  
MUX  
BALL  
MUX  
vin1a  
vin1a_clk0  
vin1a_de0  
vin1a_fld0  
vin1a_hsync0  
vin1a_vsync0  
vin1a_d0  
F22  
F21  
F20  
F19  
G19  
G18  
G21  
G22  
H18  
H20  
H19  
H22  
H21  
J17  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F22  
F21  
F20  
F19  
G19  
G18  
G21  
G22  
H18  
H20  
H19  
H22  
H21  
0
0
0
0
0
0
0
0
0
0
0
0
0
F22  
F21  
F20  
F19  
G19  
G18  
G21  
G22  
H18  
H20  
H19  
H22  
H21  
J17  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
2
2
2
F22  
F19  
F20  
F19  
G19  
G18  
G21  
G22  
H18  
H20  
H19  
H22  
H21  
0
2
0
0
0
0
0
0
0
0
0
0
0
vin1a_d1  
vin1a_d2  
vin1a_d3  
vin1a_d4  
vin1a_d5  
vin1a_d6  
vin1a_d7  
vin1a_d8  
vin1a_d9  
K22  
K21  
K18  
K17  
K19  
K20  
L21  
K22  
K21  
K18  
AB17  
U17  
W17  
AA17  
vin1a_d10  
vin1a_d11  
vin1a_d12  
vin1a_d13  
vin1a_d14  
vin1a_d15  
vin1b  
vin1b_clk1  
vin1b_hsync1  
vin1b_vsync1  
vin1b_d0  
F21  
W7  
2
7
7
2
2
2
2
2
2
2
2
8
W6  
J17  
K22  
K21  
K18  
K17  
K19  
K20  
L21  
W7  
vin1b_d1  
vin1b_d2  
vin1b_d3  
vin1b_d4  
vin1b_d5  
vin1b_d6  
vin1b_d7  
vin1b_de1  
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Table 7-4. VIN2 IOSETs  
SIGNALS  
IOSET1  
IOSET2  
IOSET3  
IOSET4  
IOSET5  
IOSET6  
BALL  
MUX  
BALL  
MUX  
BALL  
MUX  
vin2a  
0
BALL  
MUX  
BALL  
MUX  
BALL  
MUX  
vin2a_clk0  
vin2a_de0  
vin2a_fld0  
vin2a_hsync0  
vin2a_vsync0  
vin2a_d0  
L22  
M17  
M18  
0
0
0
AB17  
AA17  
U16  
W7  
9
9
9
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
L22  
L22  
AA15  
AB15  
F15  
0
9
9
9
9
2
2
2
2
2
2
2
2
L22  
W7  
0
1
9
9
9
2
2
2
2
2
2
2
2
W15  
AA17  
U16  
W7  
9
9
9
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
AB15  
F15  
F14  
C14  
AA14  
AB14  
U13  
V13  
9
9
2
2
2
2
2
2
2
2
W6  
AA14  
AB14  
U13  
V13  
2
2
2
2
2
2
2
2
2
W6  
F16  
F16  
W6  
AA14  
AB14  
U13  
V13  
Y13  
W13  
U11  
V11  
U9  
AA14  
AB14  
U13  
AA14  
AB14  
U13  
V13  
Y13  
W13  
U11  
V11  
AA14  
AB14  
U13  
V13  
Y13  
W13  
U11  
V11  
U9  
vin2a_d1  
vin2a_d2  
vin2a_d3  
V13  
vin2a_d4  
Y13  
Y13  
Y13  
vin2a_d5  
W13  
U11  
V11  
W13  
U11  
V11  
W13  
U11  
vin2a_d6  
vin2a_d7  
V11  
vin2a_d8  
vin2a_d9  
W11  
V9  
W11  
V9  
vin2a_d10  
vin2a_d11  
vin2a_d12  
vin2a_d13  
vin2a_d14  
vin2a_d15  
W9  
W9  
U8  
U8  
W8  
W8  
U7  
U7  
V7  
V7  
vin2b  
vin2b_clk1  
vin2b_hsync1  
vin2b_vsync1  
vin2b_d0  
F20  
M17  
M18  
U9  
2
2
2
5
5
5
5
5
5
vin2b_d1  
W11  
V9  
vin2b_d2  
vin2b_d3  
W9  
U8  
vin2b_d4  
vin2b_d5  
W8  
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Table 7-4. VIN2 IOSETs (continued)  
IOSET1  
IOSET2  
IOSET3  
IOSET4  
IOSET5  
IOSET6  
BALL  
MUX  
BALL  
MUX  
BALL  
U7  
MUX  
BALL  
MUX  
BALL  
MUX  
BALL  
MUX  
vin2b_d6  
vin2b_d7  
5
5
V7  
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7.6 Display Subsystem – Video Output Ports  
Display Parallel interfaces(DPI) channels are available in DSS named DPI Video Output 1.  
Every VOUT interface consists of:  
24-bit data bus (data[23:0])  
Horizontal synchronization signal (HSYNC)  
Vertical synchronization signal (VSYNC)  
Data enable (DE)  
Field ID (FID)  
Pixel clock (CLK)  
NOTE  
For more information, see the Display Subsystem section of the Device TRM.  
CAUTION  
All pads/balls configured as vouti_* signals must be programmed to use slow  
slew rate by setting the corresponding CTRL_CORE_PAD_*[SLEWCONTROL]  
register field to SLOW (0b1).  
Table 7-5 and Figure 7-6 assume testing over the recommended operating conditions and electrical  
characteristic conditions.  
Table 7-5. DPI Video Output 1 Switching Characteristics (1)(2)  
NO.  
D1  
D2  
D3  
D5  
PARAMETER  
tc(clk)  
DESCRIPTION  
MODE  
MIN  
6.73  
MAX  
UNIT  
ns  
Cycle time, output pixel clock vouti_clk  
Pulse duration, output pixel clock vouti_clk low  
Pulse duration, output pixel clock vouti_clk high  
tw(clkL)  
P×0.5-1  
P×0.5-1  
-1.33  
ns  
tw(clkH)  
ns  
td(clk-ctlV)  
Delay time, output pixel clock vouti_clk transition to output  
data vouti_d[23:0] valid  
DPI1  
DPI1  
1.01  
1.01  
ns  
D6  
td(clk-dV)  
Delay time, output pixel clock vouti_clk transition to output  
control signals vouti_vsync, vouti_hsync, vouti_de, and  
vouti_fld valid  
-1.33  
ns  
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(1) P = output vout1_clk period in ns.  
(2) All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding  
CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).  
(3) SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note SPRAC62 for additional guidance.  
D2  
D3  
D1  
D6  
D4  
Falling-edge Clock Reference  
Rising-edge Clock Reference  
vouti_clk  
vouti_clk  
vouti_vsync  
D6  
vouti_hsync  
vouti_d[23:0]  
vouti_de  
D5  
data_1 data_2  
D6  
data_n  
D6  
even  
vouti_fld  
odd  
SWPS049-018  
Figure 7-6. DPI Video Output (1)(2)(3)  
(1) The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock.  
(2) The polarity and the pulse width of vout1_hsync and vout1_vsync are programmable, refer to the DSS section of the device TRM.  
(3) The vout1_clk frequency can be configured, refer to the DSS section of the device TRM.  
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7.7 Imaging Subsystem (ISS)  
NOTE  
For more information, see the Imaging Subsystem chapter of the device TRM.  
The imaging subsystem (ISS) deals with the processing of the pixel data coming from an external image  
sensor or data from memory (image format encoding and decoding can be done to and from memory).  
With its subparts, such as interfaces and interconnects, image signal processor (ISP), and still image  
coprocessor (SIMCOP), the ISS is a key component for the following use cases:  
Rear View Camera  
Front View Stereo Camera  
Surround View Camera  
The ISS is mainly composed of CAL_A, CAL_B, LVDS-RX camera interfaces, a parallel interface (CPI),  
an ISP, and a block-based imaging accelerator (SIMCOP).  
The Camera Adapter Layer (CAL_A) supports MIPI® CSI2 protocol with four data lanes. The CAL_A is  
targeted as sensor capture interface and write DMA, while CAL_B is targeted as read DMA engine and  
does not support sensor capture.  
The LVDS receiver (LVDS-RX) support Sony / Aptina / Omnivision / Panasonic / AltaSens serial  
interfaces.  
The parallel interface (CPI) supports up to 16 data lanes.  
All interfaces can use the image signal processor (ISP), but not concurrently. When one interface uses the  
ISP, the other must send data to memory. However, the ISP can still be used to process this data in  
memory-to-memory. Time multiplex processing is also possible.  
CAUTION  
The IO timings provided in this section are only valid if signals within a single  
IOSET are used. The IOSETs are defined in Table 7-6.  
In Table 7-6 are presented the specific groupings of signals (IOSET) for use with ISS.  
Table 7-6. Camera Parallel Interface (CPI) IOSETs  
SIGNALS  
IOSET1  
IOSET2  
BALL  
F22  
F19  
G19  
G18  
G21  
G22  
H18  
H20  
H19  
H22  
H21  
J17  
MUX  
1
BALL  
F22  
F19  
G19  
G18  
G21  
G22  
H18  
H20  
H19  
H22  
H21  
J17  
MUX  
1
cpi_pclk  
cpi_data0  
cpi_data1  
cpi_data2  
cpi_data3  
cpi_data4  
cpi_data5  
cpi_data6  
cpi_data7  
cpi_data8  
cpi_data9  
cpi_data10  
cpi_data11  
cpi_data12  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
K22  
K21  
1
K22  
K21  
1
1
1
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Table 7-6. Camera Parallel Interface (CPI) IOSETs (continued)  
SIGNALS  
IOSET1  
IOSET2  
BALL  
K18  
MUX  
BALL  
K18  
K17  
L21  
MUX  
cpi_data13  
cpi_data14  
cpi_data15  
cpi_wen  
1
1
1
1
1
1
1
1
1
1
1
1
K17  
K19  
K20  
F21  
F20  
1
1
1
1
K19  
K20  
F21  
F20  
W6  
cpi_fid  
cpi_hsync  
cpi_vsync  
cam_nreset  
cam_strobe  
cam_shutter  
B18  
C18  
3
3
M17  
M18  
For more information, please contact your local TI representative.  
7.8 External Memory Interface (EMIF)  
The device has a dedicated interface to DDR3 and DDR3L SDRAM. It supports JEDEC standard  
compliant DDR3 and DDR3L SDRAM devices with the following features:  
16-bit or 32-bit data path to external SDRAM memory  
Memory device capacity: 128Mb, 256Mb, 512Mb, 1Gb, 2Gb, 4Gb and 8Gb devices (Single die only)  
One interface with associated DDR3/DDR3L PHYs  
NOTE  
For more information, see the EMIF Controller section of the Device TRM.  
7.9 General-Purpose Memory Controller (GPMC)  
The GPMC is the unified memory controller that interfaces external memory devices such as:  
Asynchronous SRAM-like memories and ASIC devices  
Asynchronous page mode and synchronous burst NOR flash  
NAND flash  
NOTE  
For more information, see the General-Purpose Memory Controller section of the Device  
TRM.  
7.9.1 GPMC/NOR Flash Interface Synchronous Timing  
Table 7-7 through Table 7-10 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see Figure 7-7 through Figure 7-12).  
Table 7-7. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - 1 Load  
NO.  
F12  
F13  
F21  
F22  
PARAMETER  
tsu(dV-clkH)  
DESCRIPTION  
MIN  
1.9  
1
MAX  
UNIT  
ns  
Setup time, read gpmc_ad[15:0] valid before gpmc_clk high  
Hold time, read gpmc_ad[15:0] valid after gpmc_clk high  
Setup time, gpmc_wait[1:0] valid before gpmc_clk high  
Hold Time, gpmc_wait[1:0] valid after gpmc_clk high  
th(clkH-dV)  
ns  
tsu(waitV-clkH)  
th(clkH-waitV)  
1.9  
1
ns  
ns  
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NOTE  
Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of  
wait monitoring feature, see the Device TRM.  
Table 7-8. GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - 1 Load  
NO.  
F0  
F2  
F3  
F4  
F5  
PARAMETER  
tc(clk)  
DESCRIPTION  
Cycle time, output clock gpmc_clk period (12)  
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition (14)  
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] invalid (14)  
Delay time, gpmc_a[27:0] address bus valid to gpmc_clk first edge  
MIN  
11.3  
MAX  
UNIT  
ns  
td(clkH-nCSV)  
td(clkH-nCSIV)  
td(ADDV-clk)  
td(clkH-ADDIV)  
F-0.8  
E-0.8  
B-0.8  
-0.8  
F+3.1  
E+3.1  
B+3.1  
ns  
ns  
ns  
Delay time, gpmc_clk rising edge to gpmc_a[27:0] gpmc address bus  
invalid  
ns  
F6  
F7  
td(nBEV-clk)  
Delay time, gpmc_ben[1:0] valid to gpmc_clk rising edge  
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] invalid  
Delay time, gpmc_clk rising edge to gpmc_advn_ale transition (14)  
Delay time, gpmc_clk rising edge to gpmc_advn_ale invalid (14)  
Delay time, gpmc_clk rising edge to gpmc_oen_ren transition (14)  
Delay time, gpmc_clk rising edge to gpmc_oen_ren invalid (14)  
Delay time, gpmc_clk rising edge to gpmc_wen transition (14)  
B-3.8  
D-0.4  
G-0.8  
D-0.8  
H-0.8  
E-0.8  
I-0.8  
B+1.1  
D+1.1  
G+3.1  
D+3.1  
H+2.1  
E+2.1  
I+3.1  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
td(clkH-nBEIV)  
td(clkH-nADV)  
td(clkH-nADVIV)  
td(clkH-nOE)  
td(clkH-nOEIV)  
td(clkH-nWE)  
td(clkH-Data)  
F8  
F9  
F10  
F11  
F14  
F15  
Delay time, gpmc_clk rising edge to gpmc_ad[15:0] data bus  
transition  
J-1.1  
J+3.92  
F17  
F18  
F19  
F20  
F23  
td(clkH-nBE)  
tw(nCSV)  
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] transition  
Pulse duration, gpmc_cs[7:0] low  
J-1.1  
A
J+3.8  
ns  
ns  
ns  
ns  
ns  
tw(nBEV)  
Pulse duration, gpmc_ben[1:0] low  
C
tw(nADVV)  
td(CLK-GPIO)  
Pulse duration, gpmc_advn_ale low  
Delay time, gpmc_clk transition to gpio6_16.clkout0 transition (13)  
K
1.2  
6.1  
Table 7-9. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - 5 Loads  
NO.  
F12  
F13  
F21  
F22  
PARAMETER  
tsu(dV-clkH)  
DESCRIPTION  
MIN  
2.5  
1.9  
2.5  
1.9  
MAX  
UNIT  
ns  
Setup time, read gpmc_ad[15:0] valid before gpmc_clk high  
Hold time, read gpmc_ad[15:0] valid after gpmc_clk high  
Setup time, gpmc_wait[1:0] valid before gpmc_clk high  
Hold Time, gpmc_wait[1:0] valid after gpmc_clk high  
th(clkH-dV)  
ns  
tsu(waitV-clkH)  
th(clkH-waitV)  
ns  
ns  
Table 7-10. GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - 5 Loads  
NO.  
F0  
F2  
F3  
F4  
F5  
PARAMETER  
tc(clk)  
DESCRIPTION  
Cycle time, output clock gpmc_clk period (12)  
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition (14)  
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] invalid (14)  
Delay time, gpmc_a[27:0] address bus valid to gpmc_clk first edge  
MIN  
MAX  
UNIT  
ns  
15.04  
td(clkH-nCSV)  
td(clkH-nCSIV)  
td(ADDV-clk)  
td(clkH-ADDIV)  
F+0.7 (6) F+6.1 (6)  
E+0.7 (5) E+6.1 (5)  
B+0.7 (2) B+6.1 (2)  
0.7  
ns  
ns  
ns  
Delay time, gpmc_clk rising edge to gpmc_a[27:0] gpmc address bus  
invalid  
ns  
F6  
F7  
F8  
F9  
td(nBEV-clk)  
Delay time, gpmc_ben[1:0] valid to gpmc_clk rising edge  
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] invalid  
Delay time, gpmc_clk rising edge to gpmc_advn_ale transition (14)  
Delay time, gpmc_clk rising edge to gpmc_advn_ale invalid (14)  
B-4.9  
D-0.4  
B+0.4  
D+4.9  
ns  
ns  
ns  
ns  
td(clkH-nBEIV)  
td(clkH-nADV)  
td(clkH-nADVIV)  
G+0.7 (7) G+6.1 (7)  
D+0.7 (4) D+6.1 (4)  
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Table 7-10. GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - 5  
Loads (continued)  
NO.  
F10  
F11  
F14  
F15  
PARAMETER  
td(clkH-nOE)  
DESCRIPTION  
MIN  
MAX  
UNIT  
ns  
Delay time, gpmc_clk rising edge to gpmc_oen_ren transition (14)  
Delay time, gpmc_clk rising edge to gpmc_oen_ren invalid (14)  
Delay time, gpmc_clk rising edge to gpmc_wen transition (14)  
H+0.7 (8) H+5.1 (8)  
E+0.7 (5) E+5.1 (5)  
I+0.7 (9) I+6.1 (9)  
td(clkH-nOEIV)  
td(clkH-nWE)  
td(clkH-Data)  
ns  
ns  
Delay time, gpmc_clk rising edge to gpmc_ad[15:0] data bus  
transition  
J-0.4 (10)  
J+4.9  
(10)  
ns  
F17  
td(clkH-nBE)  
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] transition  
J-0.4 (10)  
J+4.9  
(10)  
ns  
F18  
F19  
F20  
F23  
tw(nCSV)  
Pulse duration, gpmc_cs[7:0] low  
A (1)  
C (3)  
K (11)  
1.2  
ns  
ns  
ns  
ns  
tw(nBEV)  
Pulse duration, gpmc_ben[1:0] low  
tw(nADVV)  
td(CLK-GPIO)  
Pulse duration, gpmc_advn_ale low  
Delay time, gpmc_clk transition to gpio6_16.clkout0 transition (13)  
6.1  
(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK period  
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK period  
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK period  
with n the page burst access number.  
(2) B = ClkActivationTime × GPMC_FCLK  
(3) For single read: C = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK  
For burst read: C = (RdCycleTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK  
For Burst write: C = (WrCycleTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK with n the page  
burst access number.  
(4) For single read: D = (RdCycleTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK  
For burst read: D = (RdCycleTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK  
For burst write: D = (WrCycleTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK  
(5) For single read: E = (CSRdOffTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK  
For burst read: E = (CSRdOffTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK  
For burst write: E = (CSWrOffTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK  
(6) For nCS falling edge (CS activated):  
Case GpmcFCLKDivider = 0 :  
F = 0.5 × CSExtraDelay × GPMC_FCLK  
Case GpmcFCLKDivider = 1:  
F = 0.5 × CSExtraDelay × GPMC_FCLK if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are even)  
F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK otherwise  
Case GpmcFCLKDivider = 2:  
F = 0.5 × CSExtraDelay × GPMC_FCLK if ((CSOnTime – ClkActivationTime) is a multiple of 3)  
F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK if ((CSOnTime – ClkActivationTime – 1) is a multiple of 3)  
F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK if ((CSOnTime – ClkActivationTime – 2) is a multiple of 3)  
Case GpmcFCLKDivider = 3:  
F = 0.5 × CSExtraDelay × GPMC_FCLK if ((CSOnTime - ClkActivationTime) is a multiple of 4)  
F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK if ((CSOnTime - ClkActivationTime - 1) is a multiple of 4)  
F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK if ((CSOnTime - ClkActivationTime - 2) is a multiple of 4)  
F = (3 + 0.5 × CSExtraDelay) × GPMC_FCLK if ((CSOnTime - ClkActivationTime - 3) is a multiple of 4)  
(7) For ADV falling edge (ADV activated):  
Case GpmcFCLKDivider = 0 :  
G = 0.5 × ADVExtraDelay × GPMC_FCLK  
Case GpmcFCLKDivider = 1:  
G = 0.5 × ADVExtraDelay × GPMC_FCLK if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are  
even)  
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK otherwise  
Case GpmcFCLKDivider = 2:  
G = 0.5 × ADVExtraDelay × GPMC_FCLK if ((ADVOnTime – ClkActivationTime) is a multiple of 3)  
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVOnTime – ClkActivationTime – 1) is a multiple of 3)  
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVOnTime – ClkActivationTime – 2) is a multiple of 3)  
For ADV rising edge (ADV deactivated) in Reading mode:  
Case GpmcFCLKDivider = 0:  
G = 0.5 × ADVExtraDelay × GPMC_FCLK  
Case GpmcFCLKDivider = 1:  
G = 0.5 × ADVExtraDelay × GPMC_FCLK if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and ADVRdOffTime  
are even)  
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK otherwise  
Case GpmcFCLKDivider = 2:  
G = 0.5 × ADVExtraDelay × GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime) is a multiple of 3)  
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G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 1) is a multiple of 3)  
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 2) is a multiple of 3)  
Case GpmcFCLKDivider = 3:  
G = 0.5 × ADVExtraDelay × GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime) is a multiple of 4)  
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 1) is a multiple of 4)  
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 2) is a multiple of 4)  
G = (3 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 3) is a multiple of 4)  
For ADV rising edge (ADV deactivated) in Writing mode:  
Case GpmcFCLKDivider = 0:  
G = 0.5 × ADVExtraDelay × GPMC_FCLK  
Case GpmcFCLKDivider = 1:  
G = 0.5 × ADVExtraDelay × GPMC_FCLK if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and ADVWrOffTime  
are even)  
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK otherwise  
Case GpmcFCLKDivider = 2:  
G = 0.5 × ADVExtraDelay × GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime) is a multiple of 3)  
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 1) is a multiple of 3)  
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 2) is a multiple of 3)  
Case GpmcFCLKDivider = 3:  
G = 0.5 × ADVExtraDelay × GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime) is a multiple of 4)  
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 1) is a multiple of 4)  
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 2) is a multiple of 4)  
G = (3 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 3) is a multiple of 4)  
(8) For OE falling edge (OE activated):  
Case GpmcFCLKDivider = 0:  
- H = 0.5 × OEExtraDelay × GPMC_FCLK  
Case GpmcFCLKDivider = 1:  
- H = 0.5 × OEExtraDelay × GPMC_FCLK if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are  
even)  
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK otherwise  
Case GpmcFCLKDivider = 2:  
- H = 0.5 × OEExtraDelay × GPMC_FCLK if ((OEOnTime – ClkActivationTime) is a multiple of 3)  
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOnTime – ClkActivationTime – 1) is a multiple of 3)  
- H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOnTime – ClkActivationTime – 2) is a multiple of 3)  
Case GpmcFCLKDivider = 3:  
- H = 0.5 × OEExtraDelay × GPMC_FCLK if ((OEOnTime - ClkActivationTime) is a multiple of 4)  
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOnTime - ClkActivationTime - 1) is a multiple of 4)  
- H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOnTime - ClkActivationTime - 2) is a multiple of 4)  
- H = (3 + 0.5 × OEExtraDelay)) × GPMC_FCLK if ((OEOnTime - ClkActivationTime - 3) is a multiple of 4)  
For OE rising edge (OE deactivated):  
Case GpmcFCLKDivider = 0:  
- H = 0.5 × OEExtraDelay × GPMC_FCLK  
Case GpmcFCLKDivider = 1:  
- H = 0.5 × OEExtraDelay × GPMC_FCLK if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are  
even)  
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK otherwise  
Case GpmcFCLKDivider = 2:  
- H = 0.5 × OEExtraDelay × GPMC_FCLK if ((OEOffTime – ClkActivationTime) is a multiple of 3)  
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOffTime – ClkActivationTime – 1) is a multiple of 3)  
- H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOffTime – ClkActivationTime – 2) is a multiple of 3)  
Case GpmcFCLKDivider = 3:  
- H = 0.5 × OEExtraDelay × GPMC_FCLK if ((OEOffTime – ClkActivationTime) is a multiple of 4)  
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOffTime – ClkActivationTime – 1) is a multiple of 4)  
- H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOffTime – ClkActivationTime – 2) is a multiple of 4)  
- H = (3 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOffTime – ClkActivationTime – 3) is a multiple of 4)  
(9) For WE falling edge (WE activated):  
Case GpmcFCLKDivider = 0:  
- I = 0.5 × WEExtraDelay × GPMC_FCLK  
Case GpmcFCLKDivider = 1:  
- I = 0.5 × WEExtraDelay × GPMC_FCLK if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are  
even)  
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK otherwise  
Case GpmcFCLKDivider = 2:  
- I = 0.5 × WEExtraDelay × GPMC_FCLK if ((WEOnTime – ClkActivationTime) is a multiple of 3)  
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOnTime – ClkActivationTime – 1) is a multiple of 3)  
- I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOnTime – ClkActivationTime – 2) is a multiple of 3)  
Case GpmcFCLKDivider = 3:  
- I = 0.5 × WEExtraDelay × GPMC_FCLK if ((WEOnTime - ClkActivationTime) is a multiple of 4)  
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOnTime - ClkActivationTime - 1) is a multiple of 4)  
- I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOnTime - ClkActivationTime - 2) is a multiple of 4)  
- I = (3 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOnTime - ClkActivationTime - 3) is a multiple of 4)  
For WE rising edge (WE deactivated):  
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Case GpmcFCLKDivider = 0:  
- I = 0.5 × WEExtraDelay × GPMC_FCLK  
Case GpmcFCLKDivider = 1:  
- I = 0.5 × WEExtraDelay × GPMC_FCLK if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are  
even)  
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK otherwise  
Case GpmcFCLKDivider = 2:  
- I = 0.5 × WEExtraDelay × GPMC_FCLK if ((WEOffTime – ClkActivationTime) is a multiple of 3)  
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOffTime – ClkActivationTime – 1) is a multiple of 3)  
- I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOffTime – ClkActivationTime – 2) is a multiple of 3)  
Case GpmcFCLKDivider = 3:  
- I = 0.5 × WEExtraDelay × GPMC_FCLK if ((WEOffTime - ClkActivationTime) is a multiple of 4)  
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOffTime - ClkActivationTime - 1) is a multiple of 4)  
- I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOffTime - ClkActivationTime - 2) is a multiple of 4)  
- I = (3 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOffTime - ClkActivationTime - 3) is a multiple of 4)  
(10) J = GPMC_FCLK period, where GPMC_FCLK is the General Purpose Memory Controller internal functional clock  
(11) For read:  
K = (ADVRdOffTime – ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK  
For write: K = (ADVWrOffTime – ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK  
(12) The gpmc_clk output clock maximum and minimum frequency is programmable in the I/F module by setting the GPMC_CONFIG1_CSx  
configuration register bit fields GpmcFCLKDivider  
(13) gpio6_16 programmed to MUXMODE=9 (clkout1), CM_CLKSEL_CLKOUTMUX1 programmed to 7 (CORE_DPLL_OUT_DCLK),  
CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX programmed to 1.  
(14) CSEXTRADELAY = 0, ADVEXTRADELAY = 0, WEEXTRADELAY = 0, OEEXTRADELAY = 0. Extra half-GPMC_FCLK cycle delay  
mode is not timed.  
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F1  
F0  
F1  
gpmc_clk  
F2  
F3  
F18  
gpmc_csi  
F4  
gpmc_a[10:1]  
gpmc_a[27]  
Address (MSB)  
F19  
F6  
F7  
F7  
gpmc_ben1  
F6  
F19  
gpmc_ben0  
gpmc_advn_ale  
gpmc_oen_ren  
F8  
F8  
F20  
F9  
F10  
F11  
F13  
F4  
F5  
F12  
D 0  
gpmc_ad[15:0]  
Address (LSB)  
F22  
F21  
gpmc_waitj  
F23  
F23  
gpio6_16.clkout0  
GPMC_01  
Figure 7-7. GPMC / Multiplexed 16bits NOR Flash - Synchronous Single Read -  
(GpmcFCLKDivider = 0)(1)(2)  
(1) In gpmc_csi, i = 0 to 7.  
(2) In gpmc_waitj, j = 0 to 1.  
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F1  
F0  
F1  
gpmc_clk  
F2  
F3  
F18  
gpmc_csi  
F4  
F6  
gpmc_a[27:1]  
Address  
F7  
F7  
F19  
gpmc_ben1  
gpmc_ben0  
F6  
F19  
F8  
F8  
F9  
F20  
gpmc_advn_ale  
gpmc_oen_ren  
F10  
F11  
F13  
F12  
D 0  
gpmc_ad[15:0]  
F22  
F21  
gpmc_waitj  
F23  
F23  
gpio6_16.clkout0  
GPMC_02  
Figure 7-8. GPMC / Non-Multiplexed 16bits NOR Flash - Synchronous Single Read -  
(GpmcFCLKDivider = 0)(1)(2)  
(1) In gpmc_csi, i = 0 to 7.  
(2) In gpmc_waitj, j = 0 to 1.  
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F1  
F1  
F0  
gpmc_clk  
F2  
F3  
F18  
gpmc_csi  
F4  
F6  
gpmc_a[10:1]  
gpmc_a[27]  
Address (MSB)  
F7  
F7  
F19  
gpmc_ben1  
gpmc_ben0  
Valid  
F6  
F19  
Valid  
F8  
F8  
F9  
F20  
gpmc_advn_ale  
gpmc_oen_ren  
F10  
F5  
F11  
F12  
F4  
F13  
D1  
F12  
gpmc_ad[15:0]  
D0  
D2  
D3  
Address (LSB)  
F22  
F21  
gpmc_waitj  
F23  
F23  
gpio6_16.clkout0  
GPMC_03  
Figure 7-9. GPMC / Multiplexed 16bits NOR Flash - Synchronous Burst Read 4x16 bits -  
(GpmcFCLKDivider = 0)(1)(2)  
(1) In gpmc_csi, i= 0 to 7.  
(2) In gpmc_waitj, j = 0 to 1.  
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F1  
F1  
F0  
gpmc_clk  
F2  
F3  
F18  
gpmc_csi  
gpmc_a[27:1]  
gpmc_ben1  
gpmc_ben0  
F4  
F6  
Address  
F7  
F19  
Valid  
F7  
F6  
F19  
Valid  
F8  
F8  
F20  
F9  
gpmc_advn_ale  
gpmc_oen_ren  
F10  
F11  
F12  
F13  
D1  
F12  
gpmc_ad[15:0]  
D0  
D3  
D2  
F21  
F22  
gpmc_waitj  
F23  
F23  
gpio6_16.clkout0  
GPMC_04  
Figure 7-10. GPMC / Non-Multiplexed 16bits NOR Flash - Synchronous Burst Read 4x16 bits -  
(GpmcFCLKDivider = 0)(1)(2)  
(1) In gpmc_csi, i = 0 to 7.  
(2) In gpmc_waitj, j = 0 to 1.  
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F1  
F1  
F0  
gpmc_clk  
F2  
F3  
F18  
gpmc_csi  
F4  
gpmc_a[10:1]  
gpmc_a[27]  
Address (MSB)  
F17  
F17  
F6  
F6  
F17  
F17  
F17  
F17  
gpmc_ben1  
gpmc_ben0  
F8  
F20  
F8  
F9  
gpmc_advn_ale  
F14  
F14  
gpmc_wen  
gpmc_ad[15:0]  
gpmc_waitj  
F15  
D 1  
F15  
D 2  
F15  
Address (LSB)  
D 0  
D 3  
F22  
F21  
F23  
F23  
gpio6_16.clkout0  
GPMC_05  
Figure 7-11. GPMC / Multiplexed 16bits NOR Flash - Synchronous Burst Write 4x16bits -  
(GpmcFCLKDivider = 0)(1)(2)  
(1) In “gpmc_csi”, i = 0 to 7.  
(2) In “gpmc_waitj”, j = 0 to 1.  
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F1  
F1  
F0  
gpmc_clk  
F2  
F3  
F18  
gpmc_csi  
F4  
F6  
F6  
gpmc_a[27:1]  
Address  
F17  
F17  
F17  
F17  
gpmc_ben1  
gpmc_ben0  
F17  
F17  
F8  
F20  
F8  
F9  
gpmc_advn_ale  
F14  
F14  
gpmc_wen  
gpmc_ad[15:0]  
gpmc_waitj  
F15  
D 1  
F15  
D 2  
F15  
D 0  
D 3  
F21  
F22  
F23  
F23  
gpio6_16.clkout0  
GPMC_06  
Figure 7-12. GPMC / Non-Multiplexed 16bits NOR Flash - Synchronous Burst Write 4x16bits -  
(GpmcFCLKDivider = 0)(1)(2)  
(1) In “gpmc_csi”, i = 1 to 7.  
(2) In “gpmc_waitj”, j = 0 to 1.  
7.9.2 GPMC/NOR Flash Interface Asynchronous Timing  
Table 7-11 and Table 7-12 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see Figure 7-13 through Figure 7-18).  
Table 7-11. GPMC/NOR Flash Interface Timing Requirements - Asynchronous Mode  
NO.  
FA5  
PARAMETER  
tacc(DAT)  
DESCRIPTION  
MIN  
MAX  
UNIT  
cycles  
cycles  
(1)  
Data Maximum Access Time (GPMC_FCLK cycles)  
H
FA20  
tacc1-pgmode(DAT)  
Page Mode Successive Data Maximum Access Time (GPMC_FCLK  
cycles)  
P (2)  
(1)  
FA21  
tacc2-pgmode(DAT)  
tsu(DV-OEH)  
Page Mode First Data Maximum Access Time (GPMC_FCLK cycles)  
Setup time, read gpmc_ad[15:0] valid before gpmc_oen_ren high  
Hold time, read gpmc_ad[15:0] valid after gpmc_oen_ren high  
H
cycles  
ns  
-
-
1.9  
1
th(OEH-DV)  
ns  
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(1) H = Access Time × (TimeParaGranularity + 1)  
(2) P = PageBurstAccessTime × (TimeParaGranularity + 1)  
Table 7-12. GPMC/NOR Flash Interface Switching Characteristics - Asynchronous Mode  
NO.  
-
PARAMETER  
tr(DO)  
DESCRIPTION  
MIN  
0.447  
0.43  
MAX  
4.067  
4.463  
N
UNIT  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Rising time, gpmc_ad[15:0] output data  
-
tf(DO)  
Fallling time, gpmc_ad[15:0] output data  
FA0  
FA1  
FA3  
FA4  
FA9  
FA10  
FA12  
FA13  
FA16  
FA18  
FA20  
FA25  
FA27  
FA28  
FA29  
FA37  
tw(nBEV)  
Pulse duration, gpmc_ben[1:0] valid time  
tw(nCSV)  
Pulse duration, gpmc_cs[7:0] low  
A
td(nCSV-nADVIV)  
td(nCSV-nOEIV)  
td(AV-nCSV)  
td(nBEV-nCSV)  
td(nCSV-nADVV)  
td(nCSV-nOEV)  
tw(AIV)  
Delay time, gpmc_cs[7:0] valid to gpmc_advn_ale invalid  
Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren invalid (Single read)  
Delay time, address bus valid to gpmc_cs[7:0] valid  
Delay time, gpmc_ben[1:0] valid to gpmc_cs[7:0] valid  
Delay time, gpmc_cs[7:0] valid to gpmc_advn_ale valid  
Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren valid  
Pulse duration, address invalid between 2 successive R/W accesses  
Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren invalid (Burst read)  
Pulse duration, address valid : 2nd, 3rd and 4th accesses  
Delay time, gpmc_cs[7:0] valid to gpmc_wen valid  
Delay time, gpmc_cs[7:0] valid to gpmc_wen invalid  
Delay time, gpmc_ wen valid to data bus valid  
Delay time, data bus valid to gpmc_cs[7:0] valid  
B - 0.2  
C - 0.2  
J - 0.2  
J - 0.2  
K - 0.2  
L - 0.2  
G
B + 2.0  
C + 2.0  
J + 2.0  
J + 2.0  
K + 2.0  
L + 2.0  
td(nCSV-nOEIV)  
tw(AV)  
I - 0.2  
D
I + 2.0  
td(nCSV-nWEV)  
td(nCSV-nWEIV)  
td(nWEV-DV)  
td(DV-nCSV)  
td(nOEV-AIV)  
E - 2  
E + 2.0  
F + 2.0  
2
F - 0.2  
J - 0.2  
J + 2.0  
2
Delay time, gpmc_oen_ren valid to gpmc_ad[15:0] multiplexed  
address bus phase end  
(1) For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK  
For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK  
For burst read: N = (RdCycleTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK  
For burst write: N = (WrCycleTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK  
(2) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK  
For single write: A = (CSWrOffTime – CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK  
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK period  
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK period  
with n the page burst access number.  
(3) For reading: B = ((ADVRdOffTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay – CSExtraDelay)) ×  
GPMC_FCLK  
For writing: B = ((ADVWrOffTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay – CSExtraDelay)) × GPMC_FCLK  
(4) C = ((OEOffTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay – CSExtraDelay)) × GPMC_FCLKFor single read: C  
= RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK  
(5) J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK  
(6) K = ((ADVOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay – CSExtraDelay)) × GPMC_FCLK  
(7) L = ((OEOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay – CSExtraDelay)) × GPMC_FCLK  
(8) G = Cycle2CycleDelay × GPMC_FCLK × (TimeParaGranularity + 1)  
(9) I = ((OEOffTime + (n – 1) × PageBurstAccessTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay – CSExtraDelay))  
× GPMC_FCLK  
(10) D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK  
(11) E = ((WEOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – CSExtraDelay)) × GPMC_FCLK  
(12) F = ((WEOffTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – CSExtraDelay)) × GPMC_FCLK  
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GPMC_FCLK  
gpmc_clk  
FA5  
FA1  
gpmc_csi  
FA9  
gpmc_a[27:1]  
Valid Address  
FA0  
FA10  
gpmc_ben0  
gpmc_ben1  
Valid  
FA0  
Valid  
FA10  
FA3  
FA12  
gpmc_advn_ale  
FA4  
FA13  
gpmc_oen_ren  
gpmc_ad[15:0]  
Data IN 0  
Data IN 0  
gpmc_waitj  
FA15  
FA14  
OUT  
IN  
OUT  
DIR  
GPMC_07  
Figure 7-13. GPMC / NOR Flash - Asynchronous Read - Single Word Timing(1)(2)(3)  
(1) In gpmc_csi, i = 0 to 7. In gpmc_waitj, j = 0 to 1.  
(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock  
cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock  
edge. FA5 value must be stored inside AccessTime register bits field.  
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
(4) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal  
direction on the GPMC data bus.  
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GPMC_FCLK  
gpmc_clk  
FA5  
FA5  
FA1  
FA1  
gpmc_csi  
FA16  
FA9  
FA9  
gpmc_a[27:1]  
Address 0  
FA0  
Address 1  
FA0  
FA10  
FA10  
gpmc_ben0  
gpmc_ben1  
Valid  
FA0  
Valid  
FA0  
Valid  
Valid  
FA10  
FA10  
FA3  
FA12  
FA3  
FA12  
gpmc_advn_ale  
FA4  
FA4  
FA13  
FA13  
gpmc_oen_ren  
gpmc_ad[15:0]  
Data Upper  
gpmc_waitj  
FA15  
FA15  
FA14  
OUT  
FA14  
OUT  
DIR  
IN  
IN  
GPMC_08  
Figure 7-14. GPMC / NOR Flash - Asynchronous Read - 32-bit Timing(1)(2)(3)  
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.  
(2) FA5 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional clock  
cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock  
edge. FA5 value should be stored inside AccessTime register bits field  
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally  
(4) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal  
direction on the GPMC data bus.  
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GPMC_FCLK  
gpmc_clk  
FA21  
FA20  
FA20 FA20  
FA1  
gpmc_csi  
FA9  
gpmc_a[27:1]  
Add0  
Add1  
Add2  
Add3  
Add4  
FA0  
FA10  
FA10  
gpmc_ben0  
FA0  
gpmc_ben1  
FA12  
gpmc_advn_ale  
FA18  
FA13  
gpmc_oen_ren  
gpmc_ad[15:0]  
D3  
D2  
D3  
D0  
D1  
gpmc_waitj  
FA15  
FA14  
OUT  
OUT  
DIR  
IN  
SPRS91v_GPMC_09  
Figure 7-15. GPMC / NOR Flash - Asynchronous Read - Page Mode 4x16-bit Timing(1)(2)(3)(4)  
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1  
(2) FA21 parameter illustrates amount of time required to internally sample first input Page Data. It is expressed in number of GPMC  
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, First input Page Data will be internally sampled  
by active functional clock edge. FA21 calculation is detailled in a separated application note (ref …) and should be stored inside  
AccessTime register bits field.  
(3) FA20 parameter illustrates amount of time required to internally sample successive input Page Data. It is expressed in number of GPMC  
functional clock cycles. After each access to input Page Data, next input Page Data will be internally sampled by active functional clock  
edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input Page Data (excluding first  
input Page Data). FA20 value should be stored in PageBurstAccessTime register bits field.  
(4) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally  
(5) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal  
direction on the GPMC data bus.  
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gpmc_fclk  
gpmc_clk  
FA1  
gpmc_csi  
FA9  
gpmc_a[27:1]  
Valid Address  
FA0  
FA10  
gpmc_ben0  
FA0  
FA10  
gpmc_ben1  
FA3  
FA12  
gpmc_advn_ale  
FA27  
FA25  
gpmc_wen  
FA29  
gpmc_ad[15:0]  
gpmc_waitj  
DIR  
Data OUT  
OUT  
GPMC_10  
Figure 7-16. GPMC / NOR Flash - Asynchronous Write - Single Word Timing(1)  
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.  
(2) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal  
direction on the GPMC data bus.  
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GPMC_FCLK  
gpmc_clk  
FA1  
FA5  
gpmc_csi  
FA9  
gpmc_a27  
gpmc_a[10:1]  
Address (MSB)  
FA0  
FA10  
FA10  
gpmc_ben0  
gpmc_ben1  
Valid  
FA0  
Valid  
FA3  
FA12  
gpmc_advn_ale  
FA4  
FA13  
gpmc_oen_ren  
gpmc_ad[15:0]  
FA29  
FA37  
Data IN  
Data IN  
Address (LSB)  
FA15  
FA14  
OUT  
DIR  
OUT  
IN  
gpmc_waitj  
GPMC_11  
Figure 7-17. GPMC / Multiplexed NOR Flash - Asynchronous Read - Single Word Timing(1)(2)(3)  
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1  
(2) FA5 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional clock  
cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock  
edge. FA5 value should be stored inside AccessTime register bits field.  
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally  
(4) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal  
direction on the GPMC data bus.  
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gpmc_fclk  
gpmc_clk  
gpmc_csi  
FA1  
FA9  
gpmc_a27  
gpmc_a[10:1]  
Address (MSB)  
FA0  
FA10  
gpmc_ben0  
FA0  
FA10  
gpmc_ben1  
FA3  
FA12  
gpmc_advn_ale  
FA27  
FA25  
gpmc_wen  
FA29  
Valid Address (LSB)  
FA28  
Data OUT  
gpmc_ad[15:0]  
gpmc_waitj  
DIR  
OUT  
GPMC_12  
Figure 7-18. GPMC / Multiplexed NOR Flash - Asynchronous Write - Single Word Timing(1)  
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.  
(2) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal  
direction on the GPMC data bus.  
7.9.3 GPMC/NAND Flash Interface Asynchronous Timing  
Table 7-13 and Table 7-14 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see Figure 7-19 through Figure 7-22).  
Table 7-13. GPMC/NAND Flash Interface Timing Requirements(1)  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
cycles  
ns  
GNF12 tacc(DAT)  
Data maximum access time (GPMC_FCLK Cycles)  
Setup time, read gpmc_ad[15:0] valid before gpmc_oen_ren high  
Hold time, read gpmc_ad[15:0] valid after gpmc_oen_ren high  
J
-
-
tsu(DV-OEH)  
th(OEH-DV)  
1.9  
1
ns  
(1) J = AccessTime × (TimeParaGranularity + 1)  
Table 7-14. GPMC/NAND Flash Interface Switching Characteristics  
NO.  
PARAMETER  
tr(DO)  
DESCRIPTION  
MIN  
0.447  
0.43  
MAX  
4.067  
4.463  
A (1)  
UNIT  
ns  
-
Rising time, gpmc_ad[15:0] output data  
Fallling time, gpmc_ad[15:0] output data  
Pulse duration, gpmc_wen valid time  
Delay time, gpmc_cs[7:0] valid to gpmc_wen valid  
-
tf(DO)  
ns  
GNF0  
GNF1  
tw(nWEV)  
ns  
td(nCSV-nWEV)  
B - 0.2 (2) B + 2.0  
ns  
(2)  
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Table 7-14. GPMC/NAND Flash Interface Switching Characteristics (continued)  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
GNF2  
td(CLEH-nWEV)  
Delay time, gpmc_ben[1:0] high to gpmc_wen valid  
C - 0.2 (3) C + 2.0  
ns  
(3)  
GNF3  
GNF4  
GNF5  
GNF6  
GNF7  
GNF8  
GNF9  
td(nWEV-DV)  
Delay time, gpmc_ad[15:0] valid to gpmc_wen valid  
Delay time, gpmc_wen invalid to gpmc_ad[15:0] invalid  
Delay time, gpmc_wen invalid to gpmc_ben[1:0] invalid  
Delay time, gpmc_wen invalid to gpmc_cs[7:0] invalid  
Delay time, gpmc_advn_ale high to gpmc_wen valid  
Delay time, gpmc_wen invalid to gpmc_advn_ale invalid  
D - 0.2 (4) D + 2.0  
ns  
ns  
ns  
ns  
ns  
ns  
(4)  
td(nWEIV-DIV)  
td(nWEIV-CLEIV)  
td(nWEIV-nCSIV)  
td(ALEH-nWEV)  
td(nWEIV-ALEIV)  
tc(nWE)  
E - 0.2 (5) E + 2.0  
(5)  
F - 0.2 (6) F + 2.0  
(6)  
G - 0.2 (7) G + 2.0  
(7)  
C - 0.2 (3) C + 2.0  
(3)  
F - 0.2 (6) F + 2.0  
(6)  
(8)  
Cycle time, write cycle time  
H
ns  
ns  
ns  
ns  
ns  
GNF10 td(nCSV-nOEV)  
GNF13 tw(nOEV)  
Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren valid  
Pulse duration, gpmc_oen_ren valid time  
Cycle time, read cycle time  
I - 0.2 (9) I + 2.0 (9)  
K
(10)  
GNF14 tc(nOE)  
L
GNF15 td(nOEIV-nCSIV)  
Delay time, gpmc_oen_ren invalid to gpmc_cs[7:0] invalid  
M - 0.2  
M + 2.0  
(11)  
(11)  
(1) A = (WEOffTime – WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK  
(2) B = ((WEOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – CSExtraDelay)) × GPMC_FCLK  
(3) C = ((WEOnTime – ADVOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – ADVExtraDelay)) × GPMC_FCLK  
(4) D = (WEOnTime × (TimeParaGranularity + 1) + 0.5 × WEExtraDelay ) × GPMC_FCLK  
(5) E = (WrCycleTime – WEOffTime × (TimeParaGranularity + 1) – 0.5 × WEExtraDelay ) × GPMC_FCLK  
(6) F = (ADVWrOffTime – WEOffTime × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay – WEExtraDelay ) × GPMC_FCLK  
(7) G = (CSWrOffTime – WEOffTime × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay – WEExtraDelay ) × GPMC_FCLK  
(8) H = WrCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK  
(9) I = ((OEOffTime + (n – 1) × PageBurstAccessTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay – CSExtraDelay))  
× GPMC_FCLK  
(10) K = (OEOffTime – OEOnTime) × (1 + TimeParaGranularity) × GPMC_FCLK  
(11) L = RdCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK  
(12) M = (CSRdOffTime – OEOffTime × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay – OEExtraDelay ) × GPMC_FCLK  
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GPMC_FCLK  
gpmc_csi  
GNF1  
GNF2  
GNF6  
GNF5  
gpmc_ben0  
gpmc_advn_ale  
gpmc_oen_ren  
gpmc_wen  
GNF0  
GNF3  
GNF4  
Command  
gpmc_ad[15:0]  
GPMC_13  
Figure 7-19. GPMC / NAND Flash - Command Latch Cycle Timing(1)  
(1) In gpmc_csi, i = 0 to 7.  
GPMC_FCLK  
gpmc_csi  
GNF1  
GNF7  
GNF6  
GNF8  
gpmc_ben0  
gpmc_advn_ale  
gpmc_oen_ren  
GNF9  
GNF0  
gpmc_wen  
GNF3  
GNF4  
gpmc_ad[15:0]  
Address  
GPMC_14  
Figure 7-20. GPMC / NAND Flash - Address Latch Cycle Timing(1)  
(1) In gpmc_csi, i = 0 to 7.  
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GPMC_FCLK  
GNF12  
GNF10  
GNF15  
gpmc_csi  
gpmc_ben0  
gpmc_advn_ale  
GNF14  
GNF13  
gpmc_oen_ren  
gpmc_ad[15:0]  
DATA  
gpmc_waitj  
GPMC_15  
Figure 7-21. GPMC / NAND Flash - Data Read Cycle Timing(1)(2)(3)  
(1) GNF12 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional  
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional  
clock edge. GNF12 value must be stored inside AccessTime register bits field.  
(2) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
(3) In gpmc_csi, i = 0 to 7. In gpmc_waitj, j = 0 to 1.  
GPMC_FCLK  
GNF1  
GNF6  
gpmc_csi  
gpmc_ben0  
gpmc_advn_ale  
gpmc_oen_ren  
GNF9  
GNF0  
gpmc_wen  
GNF3  
GNF4  
gpmc_ad[15:0]  
DATA  
GPMC_16  
Figure 7-22. GPMC / NAND Flash - Data Write Cycle Timing(1)  
(1) In gpmc_csi, i = 0 to 7.  
NOTE  
To configure the desired virtual mode the user must set MODESELECT bit and  
DELAYMODE bit field for each corresponding pad control register.  
The pad control registers are presented Table 4-3 and described in Device TRM, Control  
Module section.  
7.10 General-Purpose Timers  
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The device has eight GP timers: TIMER1 through TIMER8.  
TIMER1 (1-ms tick) includes a specific function to generate accurate tick interrupts to the operating  
system and it belongs to the PD_WKUPAON domain.  
TIMER2 through TIMER8 belong to the PD_COREAON module.  
Each timer can be clocked from the system clock (19.2, 20, or 27 MHz) or the 32-kHz clock. Select the  
clock source at the power, reset, and clock management (PRCM) module level.  
Each timer provides an interrupt through the device IRQ_CROSSBAR.  
Each timer is connected to an external pin by their PWM output or their event capture input pin (for  
external timer triggering).  
7.10.1 GP Timer Features  
The following are the main features of the GP timer controllers:  
Level 4 (L4) slave interface support:  
32-bit data bus width  
32- or 16-bit access supported  
8-bit access not supported  
10-bit address bus width  
Burst mode not supported  
Write nonposted transaction mode supported  
Interrupts generated on overflow, compare, and capture  
Free-running 32-bit upward counter  
Compare and capture modes  
Autoreload mode  
Start and stop mode  
Programmable divider clock source (2n, where n = [0:8])  
Dedicated input trigger for capture mode and dedicated output trigger/PWM signal  
Dedicated GP output signal for using the TIMERi_GPO_CFG signal  
On-the-fly read/write register (while counting)  
1-ms tick with 32.768-Hz functional clock generated (only TIMER1)  
7.11 Inter-Integrated Circuit Interface (I2C)  
The device includes 2 inter-integrated circuit (I2C) modules which provide an interface to other devices  
compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External  
components attached to this 2-wire serial bus can transmit/receive 8-bit data to/from the device through  
the I2C module.  
NOTE  
Note that, I2C1 and I2C2, due to characteristics of the open drain IO cells, HS mode is not  
supported  
NOTE  
Inter-integrated circuit i ( i=1 to 2) module is also referred to as I2Ci.  
NOTE  
For more information, see the Multimaster I2C Controller section of the Device TRM.  
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Table 7-15 and Figure 7-23 assume testing over the recommended operating conditions and electrical  
characteristic conditions below.  
Table 7-15. Timing Requirements for I2C Input Timings(1)  
STANDARD MODE  
FAST MODE  
NO.  
PARAMETER  
DESCRIPTION  
UNIT  
MIN  
MAX  
MIN  
MAX  
1
2
t c(SCL)  
Cycle time, SCL  
10  
2.5  
µs  
µs  
Setup time, SCL high before SDA low (for a  
repeated START condition)  
t su(SCLH-SDAL)  
4.7  
4
0.6  
Hold time, SCL low after SDA low (for a START  
and a repeated START condition)  
3
t h(SDAL-SCLL)  
0.6  
µs  
4
5
6
7
t w(SCLL)  
Pulse duration, SCL low  
4.7  
4
1.3  
0.6  
100 (2)  
µs  
µs  
ns  
µs  
t w(SCLH)  
Pulse duration, SCL high  
t su(SDAV-SCLH)  
t h(SCLL-SDAV)  
Setup time, SDA valid before SCL high  
Hold time, SDA valid after SCL low  
250  
(3)  
(3)  
0
3.45 (4)  
0
0.9 (4)  
Pulse duration, SDA high between STOP and  
START conditions  
8
t w(SDAH)  
t r(SDA)  
t r(SCL)  
t f(SDA)  
t f(SCL)  
4.7  
1.3  
µs  
ns  
ns  
ns  
ns  
µs  
20 + 0.1C b  
9
Rise time, SDA  
Rise time, SCL  
Fall time, SDA  
Fall time, SCL  
1000  
1000  
300  
300  
300  
300  
300  
(5)  
20 + 0.1C b  
10  
11  
12  
13  
(5)  
20 + 0.1C b  
(5)  
20 + 0.1C b  
300  
(5)  
Setup time, SCL high before SDA high (for  
STOP condition)  
t su(SCLH-SDAH)  
t w(SP)  
4
0.6  
0
14  
15  
Pulse duration, spike (must be suppressed)  
Capacitive load for each bus line  
50  
ns  
(5)  
C b  
400  
400  
pF  
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered  
down.  
(2) A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus system, but the requirement t su(SDA-SCLH)250 ns must then  
be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch  
the LOW period of the SCL signal, it must output the next data bit to the SDA line t r max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns  
(according to the Standard-mode I2C-Bus Specification) before the SCL line is released.  
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the  
undefined region of the falling edge of SCL.  
(4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.  
(5) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.  
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9
11  
I2Ci_SDA  
6
8
14  
4
13  
5
10  
I2Ci_SCL  
1
12  
3
7
2
3
Stop  
Start  
Repeated  
Start  
Stop  
SPRS91v_I2C_01  
Figure 7-23. I2C Receive Timing  
Table 7-16 and Figure 7-24 assume testing over the recommended operating conditions and electrical  
characteristic conditions below.  
Table 7-16. Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings(2)  
STANDARD MODE  
FAST MODE  
NO.  
PARAMETER  
DESCRIPTION  
UNIT  
MIN  
MAX  
MIN  
MAX  
16  
17  
t c(SCL)  
Cycle time, SCL  
10  
2.5  
µs  
µs  
Setup time, SCL high before SDA low (for a  
repeated START condition)  
t su(SCLH-SDAL)  
4.7  
4
0.6  
Hold time, SCL low after SDA low (for a  
START and a repeated START condition)  
18  
t h(SDAL-SCLL)  
0.6  
µs  
19  
20  
21  
t w(SCLL)  
Pulse duration, SCL low  
4.7  
4
1.3  
0.6  
100  
µs  
µs  
ns  
t w(SCLH)  
Pulse duration, SCL high  
t su(SDAV-SCLH)  
Setup time, SDA valid before SCL high  
250  
Hold time, SDA valid after SCL low (for I2C  
bus devices)  
22  
23  
24  
25  
26  
27  
t h(SCLL-SDAV)  
t w(SDAH)  
t r(SDA)  
0
3.45  
0
0.9  
µs  
µs  
ns  
ns  
ns  
ns  
Pulse duration, SDA high between STOP and  
START conditions  
4.7  
1.3  
20 + 0.1C b  
Rise time, SDA  
Rise time, SCL  
Fall time, SDA  
Fall time, SCL  
1000  
1000  
300  
300  
300  
300  
300  
(1)  
20 + 0.1C b  
t r(SCL)  
(1)  
20 + 0.1C b  
t f(SDA)  
(1)  
20 + 0.1C b  
t f(SCL)  
300  
(1)  
Setup time, SCL high before SDA high (for  
STOP condition)  
28  
29  
t su(SCLH-SDAH)  
C p  
4
0.6  
µs  
pF  
Capacitance for each I2C pin  
10  
10  
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(1) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.  
(2) Software must properly configure the I2C module registers to achieve the timings shown in this table. See the Device TRM for details.  
26  
24  
I2Ci_SDA  
I2Ci_SCL  
21  
23  
19  
28  
20  
25  
27  
16  
18  
22  
17  
18  
Stop  
Start  
Repeated  
Start  
Stop  
SPRS91v_I2C_02  
Figure 7-24. I2C Transmit Timing  
7.12 Universal Asynchronous Receiver Transmitter (UART)  
The UART performs serial-to-parallel conversions on data received from a peripheral device and parallel-  
to-serial conversion on data received from the CPU. There are 3 UART modules in the device. Each  
UART can be used for configuration and data exchange with a number of external peripheral devices or  
interprocessor communication between devices.  
The UARTi (where i = 1 to 3) include the following features:  
16C750 compatibility  
64-byte FIFO buffer for receiver and 64-byte FIFO for transmitter  
Baud generation based on programmable divisors N (where N = 1…16 384) operating from a fixed  
functional clock of 48 MHz or 192 MHz  
Break character detection and generation  
Configurable data format:  
Data bit: 5, 6, 7, or 8 bits  
Parity bit: Even, odd, none  
Stop-bit: 1, 1.5, 2 bit(s)  
Flow control: Hardware (RTS/CTS) or software (XON/XOFF)  
NOTE  
For more information, see the UART section of the Device TRM.  
Table 7-17, Table 7-18 and Figure 7-25 assume testing over the recommended operating conditions and  
electrical characteristic conditions below.  
Table 7-17. Timing Requirements for UART  
NO.  
4
PARAMETER  
DESCRIPTION  
MIN  
0.96U(1)  
0.96U(1)  
P(2)  
MAX  
UNIT  
ns  
tw(RX)  
Pulse width, receive data bit, 15/30/100pF high or low  
Pulse width, receive start bit, 15/30/100pF high or low  
Delay time, transmit start bit to transmit data  
Delay time, receive start bit to transmit data  
1.05U(1)  
1.05U(1)  
5
tw(CTS)  
ns  
td(RTS-TX)  
td(CTS-TX)  
ns  
P(2)  
ns  
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(1) U = UART baud time = 1/programmed baud rate  
(2) P = Clock period of the reference clock (FCLK, usually 48 MHz or 192MHz).  
Table 7-18. Switching Characteristics Over Recommended Operating Conditions for UART  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
12  
UNIT  
15 pF  
30 pF  
100 pF  
f(baud)  
Maximum programmable baud rate  
0.23  
MHz  
0.115  
U + 2(1)  
U + 2(1)  
2
3
tw(TX)  
Pulse width, transmit data bit, 15/30/100 pF high or low  
Pulse width, transmit start bit, 15/30/100 pF high or low  
U - 2(1)  
U - 2(1)  
ns  
ns  
tw(RTS)  
(1) U = UART baud time = 1/programmed baud rate  
3
2
Start  
Bit  
UARTi_TXD  
Data Bits  
5
4
Start  
Bit  
UARTi_RXD  
Data Bits  
SPRS91v_UART_01  
Figure 7-25. UART Timing  
CAUTION  
The IO timings provided in this section are only valid if signals within a single  
IOSET are used. The IOSETs are defined in Table 7-19.  
In Table 7-19 are presented the specific groupings of signals (IOSET) for use with UART.  
Table 7-19. UART1-3 IOSETs  
SIGNALS  
IOSET1  
IOSET2  
IOSET3  
BALL  
MUX  
BALL  
UART1  
F13  
MUX  
BALL  
MUX  
uart1_rxd  
uart1_txd  
uart1_rtsn  
uart1_ctsn  
F13  
E14  
0
0
0
0
0
0
E14  
C14  
F14  
UART2  
D14  
uart2_rxd  
uart2_txd  
uart2_rtsn  
uart2_ctsn  
E7  
F7  
2
2
0
0
0
0
D15  
F16  
F15  
UART3  
L1  
uart3_rxd  
uart3_txd  
uart3_rtsn  
W7  
W6  
4
4
1
1
1
M2  
R6  
T5  
1
1
1
L2  
R7  
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Table 7-19. UART1-3 IOSETs (continued)  
SIGNALS  
IOSET1  
IOSET2  
IOSET3  
BALL  
MUX  
BALL  
MUX  
BALL  
MUX  
uart3_ctsn  
N4  
1
U6  
1
7.13 Multichannel Serial Peripheral Interface (McSPI)  
The McSPI is a master/slave synchronous serial bus. There are four separate McSPI modules (SPI1,  
SPI2, SPI3, and SPI4) in the device. All these four modules support up to four external devices (four chip  
selects) and are able to work as both master and slave.  
The McSPI modules include the following main features:  
Serial clock with programmable frequency, polarity, and phase for each channel  
Wide selection of SPI word lengths, ranging from 4 to 32 bits  
Up to four master channels, or single channel in slave mode  
Master multichannel mode:  
Full duplex/half duplex  
Transmit-only/receive-only/transmit-and-receive modes  
Flexible input/output (I/O) port controls per channel  
Programmable clock granularity  
SPI configuration per channel. This means, clock definition, polarity enabling and word width  
Power management through wake-up capabilities  
Programmable timing control between chip select and external clock generation  
Built-in FIFO available for a single channel.  
Each SPI module supports multiple chip select pins spim_cs[i], where i = 1 to 4.  
NOTE  
For more information, see the Serial Communication Interface section of the device TRM.  
NOTE  
The McSPIm module (m = 1 to 4) is also referred to as SPIm.  
Table 7-20, Figure 7-26 and Figure 7-27 present Timing Requirements for McSPI - Master Mode.  
Table 7-20. Timing Requirements for SPI - Master Mode  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
MIN  
MAX  
UNIT  
SM1  
tc(SPICLK)  
Cycle time, spi_sclk (1) (2)  
SPI1/2/3/  
4
20.8  
ns  
SM2  
SM3  
tw(SPICLKL)  
tw(SPICLKH)  
Typical Pulse duration, spi_sclk low (1)  
Typical Pulse duration, spi_sclk high (1)  
0.5×P-1  
(3)  
ns  
ns  
0.5×P-1  
(3)  
SM4  
SM5  
SM6  
tsu(MISO-SPICLK)  
th(SPICLK-MISO)  
td(SPICLK-SIMO)  
Setup time, spi_d[x] valid before spi_sclk active edge (1)  
Hold time, spi_d[x] valid after spi_sclk active edge (1)  
Delay time, spi_sclk active edge to spi_d[x] transition (1)  
2.29  
2.67  
ns  
ns  
ns  
ns  
ns  
SPI1/2/4  
SPI3  
-3.57  
-3.57  
3.57  
3.57  
3.57  
SM7  
td(CS-SIMO)  
Delay time, spi_cs[x] active edge to spi_d[x] transition  
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Table 7-20. Timing Requirements for SPI - Master Mode (continued)  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
MIN  
MAX  
UNIT  
SM8  
td(CS-SPICLK)  
Delay time, spi_cs[x] active to spi_sclk first edge (1)  
MASTER B-4.2 (5)  
ns  
_PHA0  
(4)  
MASTER A-4.2 (6)  
ns  
ns  
ns  
_PHA1  
(4)  
SM9  
td(SPICLK-CS)  
Delay time, spi_sclk last edge to spi_cs[x] inactive (1)  
MASTER A-4.2 (6)  
_PHA0  
(4)  
MASTER B-4.2 (5)  
_PHA1  
(4)  
(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture  
input data.  
(2) Related to the SPI_CLK maximum frequency.  
(3) P = SPICLK period.  
(4) SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.  
(5) B = (TCS + 0.5) × TSPICLKREF × Fratio, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even 2.  
(6) When P = 20.8 ns, A = (TCS + 1) × TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8 ns, A = (TCS  
+ 0.5) × Fratio × TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.  
(7) The IO timings provided in this section are applicable for all combinations of signals for spi1 and spi2. However, the timings are only  
valid for spi3 and spi4 if signals within a single IOSET are used. The IOSETs are defined in the following tables.  
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PHA=0  
EPOL=1  
spim_cs(OUT)  
spim_sclk(OUT)  
SM1  
SM3  
SM8  
SM2  
SM9  
POL=0  
POL=1  
SM1  
SM3  
SM2  
spim_sclk(OUT)  
spim_d(OUT)  
SM7  
Bit n-1  
SM6  
Bit n-2  
SM6  
Bit n-3  
Bit n-4  
Bit 0  
PHA=1  
EPOL=1  
spim_cs(OUT)  
SM1  
SM2  
SM8  
SM3  
SM2  
SM9  
POL=0  
POL=1  
spim_sclk(OUT)  
SM1  
SM3  
spim_sclk(OUT)  
spim_d(OUT)  
SM6  
Bit n-1  
SM6  
Bit n-2  
SM6  
Bit n-3  
SM6  
Bit 1  
Bit0  
SPRS91v_McSPI_01  
Figure 7-26. McSPI - Master Mode Transmit  
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PHA=0  
EPOL=1  
spim_cs(OUT)  
SM1  
SM3  
SM8  
SM2  
SM9  
POL=0  
spim_sclk(OUT)  
SM1  
SM3  
SM2  
POL=1  
spim_sclk(OUT)  
SM5  
SM5  
SM4  
SM4  
Bit n-1  
Bit n-2  
Bit n-3  
Bit n-4  
Bit 0  
spim_d(IN)  
PHA=1  
EPOL=1  
spim_cs(OUT)  
SM2  
SM1  
SM8  
SM3  
SM2  
SM9  
POL=0  
POL=1  
spim_sclk(OUT)  
SM1  
SM3  
spim_sclk(OUT)  
SM5  
SM4  
SM5  
SM4  
Bit n-1  
Bit n-2  
Bit n-3  
Bit 1  
Bit 0  
spim_d(IN)  
SPRS91v_McSPI_02  
Figure 7-27. McSPI - Master Mode Receive  
Table 7-21, Figure 7-28 and Figure 7-29 present Timing Requirements for McSPI - Slave Mode.  
Table 7-21. Timing Requirements for SPI - Slave Mode(5)  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
SPI1  
MIN  
25  
MAX  
UNIT  
ns  
SS1 (1) tc(SPICLK)  
Cycle time, spi_sclk  
(2)  
SPI2/3/4  
33.3  
0.45×P  
0.45×P  
2.82  
2.82  
2
ns  
(3)  
(3)  
SS2 (1) tw(SPICLKL)  
SS3 (1) tw(SPICLKH)  
Typical Pulse duration, spi_sclk low  
ns  
Typical Pulse duration, spi_sclk high  
ns  
SS4 (1) tsu(SIMO-SPICLK)  
SS5 (1) th(SPICLK-SIMO)  
SS6 (1) td(SPICLK-SOMI)  
Setup time, spi_d[x] valid before spi_sclk active edge  
Hold time, spi_d[x] valid after spi_sclk active edge  
Delay time, spi_sclk active edge to mcspi_somi transition  
ns  
ns  
SPI1  
9.8  
21  
16  
ns  
SPI2/3/4  
2
ns  
SS7 (4) td(CS-SOMI)  
SS8 (1) tsu(CS-SPICLK)  
Delay time, spi_cs[x] active edge to mcspi_somi transition  
Setup time, spi_cs[x] valid before spi_sclk first edge  
ns  
2.82  
ns  
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Table 7-21. Timing Requirements for SPI - Slave Mode(5) (continued)  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
MIN  
MAX  
UNIT  
SS9 (1) th(SPICLK-CS)  
Hold time, spi_cs[x] valid after spi_sclk last edge  
2.82  
ns  
(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture  
input data.  
(2) When operating the SPI interface in RX-only mode, the minimum Cycle time is 26ns (38.4MHz)  
(3) P = SPICLK period.  
(4) PHA = 0; SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.  
(5) The IO timings provided in this section are applicable for all combinations of signals for spi1 and spi2. However, the timings are only  
valid for spi3 and spi4 if signals within a single IOSET are used. The IOSETs are defined in the following tables.  
PHA=0  
EPOL=1  
spim_cs(IN)  
SS1  
SS2  
SS8  
SS3  
SS3  
SS9  
POL=0  
POL=1  
spim_sclk(IN)  
SS1  
SS2  
spim_sclk(IN)  
spim_d(OUT)  
SS7  
Bit n-1  
SS6  
Bit n-2  
SS6  
Bit n-3  
Bit n-4  
Bit 0  
PHA=1  
EPOL=1  
spim_cs(IN)  
spim_sclk(IN)  
SS1  
SS2  
SS8  
SS3  
SS2  
SS9  
POL=0  
POL=1  
SS1  
SS3  
spim_sclk(IN)  
spim_d(OUT)  
SS6  
Bit n-1  
SS6  
Bit n-2  
SS6  
Bit n-3  
SS6  
Bit 1  
Bit 0  
SPRS91v_McSPI_03  
Figure 7-28. McSPI - Slave Mode Transmit  
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PHA=0  
EPOL=1  
spim_cs(IN)  
SS1  
SS2  
SS8  
SS3  
SS3  
SS9  
POL=0  
spim_sclk(IN)  
SS1  
SS2  
POL=1  
spim_sclk(IN)  
SS5  
SS4  
SS4  
SS5  
Bit n-2  
Bit n-1  
Bit n-3  
Bit n-4  
Bit 0  
spim_d(IN)  
PHA=1  
EPOL=1  
spim_cs(IN)  
SS1  
SS2  
SS8  
SS3  
SS2  
SS9  
POL=0  
spim_sclk(IN)  
SS1  
SS3  
POL=1  
spim_sclk(IN)  
SS4  
SS5  
SS4  
SS5  
Bit n-1  
Bit n-2  
Bit n-3  
Bit 1  
Bit 0  
spim_d(IN)  
SPRS91v_McSPI_04  
Figure 7-29. McSPI - Slave Mode Receive  
CAUTION  
The IO timings provided in this section are applicable for all combinations of  
signals for SPI2 and SPI4. However, the timings are only valid for SPI1 and  
SPI3 if signals within a single IOSET are used. The IOSETs are defined in  
Table 7-22.  
In Table 7-22 are presented the specific groupings of signals (IOSET) for use with McSPI.  
Table 7-22. McSPI1/3 IOSETs  
SIGNALS  
IOSET1  
IOSET2  
IOSET3  
BALL  
MUX  
BALL  
SPI1  
M2  
MUX  
BALL  
MUX  
spi1_sclk  
spi1_d1  
M2  
U6  
0
0
0
0
M2  
U6  
0
0
U6  
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Table 7-22. McSPI1/3 IOSETs (continued)  
SIGNALS  
IOSET1  
IOSET2  
IOSET3  
BALL  
T5  
MUX  
BALL  
T5  
MUX  
BALL  
T5  
MUX  
spi1_d0  
spi1_cs0  
spi1_cs1  
spi1_cs2  
spi1_cs3  
0
0
0
0
0
0
0
R6  
R6  
R6  
R5  
F14  
C14  
SPI3  
C6  
5
5
spi3_sclk  
spi3_d1  
spi3_d0  
spi3_cs0  
F15  
D14  
D15  
F16  
4
4
4
4
4
4
4
4
F7  
E7  
B6  
7.14 Quad Serial Peripheral Interface (QSPI)  
The Quad SPI (QSPI) module is a type of SPI module that allows single, dual or quad read access to  
external SPI devices. This module has a memory mapped register interface, which provides a direct  
interface for accessing data from external SPI devices and thus simplifying software requirements. It  
works as a master only. There is one QSPI module in the device and it is primary intended for fast  
booting from quad-SPI flash memories.  
General SPI features:  
Programmable clock divider  
Six pin interface (DCLK, CS_N, DOUT, DIN, QDIN1, QDIN2)  
4 external chip select signals  
Support for 3-, 4- or 6-pin SPI interface  
Programmable CS_N to DOUT delay from 0 to 3 DCLKs  
Programmable signal polarities  
Programmable active clock edge  
Software controllable interface allowing for any type of SPI transfer  
NOTE  
For more information, see the Quad Serial Peripheral Interface section of the Device TRM.  
Table 7-23 and Table 7-24 present Timing and Switching Characteristics for Quad SPI Interface.  
Table 7-23. Switching Characteristics for QSPI  
No  
PARAMETER  
DESCRIPTION  
Mode  
MIN  
MAX  
UNIT  
1
tc(SCLK)  
Cycle time, sclk  
Default  
Timing  
Mode,  
Clock  
10.4  
ns  
Mode 0  
Default  
Timing  
Mode,  
Clock  
15.625  
ns  
Mode 3  
2
3
tw(SCLKL)  
tw(SCLKH)  
Pulse duration, sclk low  
Pulse duration, sclk high  
Y×P-1  
(1)  
ns  
ns  
Y×P-1  
(1)  
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Table 7-23. Switching Characteristics for QSPI (continued)  
No  
PARAMETER  
DESCRIPTION  
Mode  
MIN  
MAX  
UNIT  
4
td(CS-SCLK)  
Delay time, sclk falling edge to cs active edge, CS3:0  
Default  
Timing  
Mode  
-M×P-1  
(2) (3)  
-M×P+1  
(2) (3)  
ns  
5
6
td(SCLK-CS)  
Delay time, sclk falling edge to cs inactive edge, CS3:0  
Delay time, sclk falling edge to d[0] transition  
Default  
Timing  
Mode  
N×P-1  
(2) (3)  
N×P+1  
(2) (3)  
ns  
ns  
td(SCLK-D1)  
Default  
Timing  
Mode  
-1  
1
7
8
9
tena(CS-D1LZ)  
tdis(CS-D1Z)  
td(SCLK-D1)  
Enable time, cs active edge to d[0] driven (lo-z)  
Disable time, cs active edge to d[0] tri-stated (hi-z)  
Delay time, sclk first falling edge to first d[0] transition  
-P-3.5  
-P-2.5  
-1-P  
-P+2.5  
-P+2.0  
-1-P  
ns  
ns  
ns  
PHA=0  
Only,  
Default  
Timing  
Mode  
(1) The Y parameter is defined as follows: If DCLK_DIV is 0 or ODD then, Y equals 0.5. If DCLK_DIV is EVEN then, Y equals  
(DCLK_DIV/2) / (DCLK_DIV+1). For best performance, it is recommended to use a DCLK_DIV of 0 or ODD to minimize the duty cycle  
distortion. The HSDIVIDER on CLKOUTX2_H13 output of DPLL_PER can be used to achieve the desired clock divider ratio. All  
required details about clock division factor DCLK_DIV can be found in the device-specific Technical Reference Manual.  
(2) P = SCLK period.  
(3) M=QSPI_SPI_DC_REG.DDx + 1 when Clock Mode 0. M=QSPI_SPI_DC_REG.DDx when Clock Mode 3. N = 2 when Clock Mode 0. N  
= 3 when Clock Mode 3.  
cs  
Q5  
Q1  
PHA=1  
POL=1  
Q4  
Q3  
Q2  
sclk  
Q15  
Q14  
Q12  
Q6  
Q13  
Read Data  
Bit 1  
Q6  
Q7  
Command  
Bit n-1  
Command  
Bit n-2  
Read Data  
Bit 0  
d[0]  
Q15  
Q14  
Q12 Q13  
Read Data  
Bit 1  
Read Data  
Bit 0  
d[3:1]  
SPRS91v_QSPI_01  
Figure 7-30. QSPI Read (Clock Mode 3)  
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cs  
Q5  
Q4  
Q1  
PHA=0  
POL=0  
Q2  
Q3  
sclk  
rtclk  
POL=0  
Q12  
Q13  
Q12 Q13  
Read Data  
Bit 0  
Q6  
Q7  
Q9  
Command  
Bit n-1  
Command  
Bit n-2  
Read Data  
Bit 1  
d[0]  
Q12 Q13  
Read Data  
Bit 1  
Q12 Q13  
Read Data  
Bit 0  
d[3:1]  
SPRS91v_QSPI_02  
Figure 7-31. QSPI Read (Clock Mode 0)  
CAUTION  
The IO Timings provided in this section are only valid when all QSPI Chip  
Selects used in a system are configured to use the same Clock Mode (either  
Clock Mode 0 or Clock Mode 3).  
Table 7-24. Timing Requirements for QSPI  
No  
PARAMETER  
DESCRIPTION  
MODE  
MIN  
MAX  
UNIT  
12  
tsu(D-RTCLK)  
Setup time, d[3:0] valid before falling rtclk edge  
Default  
Timing  
Mode,  
Clock  
2.9  
ns  
Mode 0  
tsu(D-SCLK)  
th(RTCLK-D)  
th(SCLK-D)  
Setup time, d[3:0] valid before falling sclk edge  
Hold time, d[3:0] valid after falling rtclk edge  
Hold time, d[3:0] valid after falling sclk edge  
Default  
Timing  
Mode,  
Clock  
5.7  
-0.1  
0.1  
ns  
ns  
ns  
Mode 3  
13  
Default  
Timing  
Mode,  
Clock  
Mode 0  
Default  
Timing  
Mode,  
Clock  
Mode 3  
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Table 7-24. Timing Requirements for QSPI (continued)  
No  
PARAMETER  
DESCRIPTION  
MODE  
MIN  
MAX  
UNIT  
14  
tsu(D-SCLK)  
Setup time, final d[3:0] bit valid before final falling sclk edge  
Default 5.7-P (1)  
Timing  
ns  
Mode,  
Clock  
Mode 3  
15  
th(SCLK-D)  
Hold time, final d[3:0] bit valid after final falling sclk edge  
Default 0.1+P (1)  
Timing  
ns  
Mode,  
Clock  
Mode 3  
(1) P = SCLK period.  
(2) Clock Modes 1 and 2 are not supported.  
(3) The Device captures data on the falling clock edge in Clock Mode 0 and 3, as opposed to the traditional rising clock edge. Although  
non-standard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI devices that  
launch data on the falling edge in Clock Modes 0 and 3.  
cs  
Q5  
Q1  
PHA=1  
Q4  
Q3  
Q2  
POL=1  
sclk  
Q8  
Q6  
Q6  
Q6  
Q6  
Q7  
Command  
Bit n-1  
Command  
Bit n-2  
Write Data  
Bit 1  
Write Data  
Bit 0  
d[0]  
d[3:1]  
SPRS91v_QSPI_03  
Figure 7-32. QSPI Write (Clock Mode 3)  
cs  
Q5  
Q4  
Q1  
PHA=0  
POL=0  
Q2  
Q3  
sclk  
Q8  
Q6  
Q6  
Q7  
Q9  
Q6  
Command  
Bit n-1  
Command  
Bit n-2  
Write Data  
Bit 1  
Write Data  
Bit 0  
d[0]  
d[3:1]  
SPRS91v_QSPI_04  
Figure 7-33. QSPI Write (Clock Mode 0)  
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NOTE  
To configure the desired virtual mode the user must set MODESELECT bit and  
DELAYMODE bit field for each corresponding pad control register.  
The pad control registers are presented in Table 4-3 and described in Device TRM, Control  
Module section.  
CAUTION  
The IO timings provided in this section are only valid if signals within a single  
IOSET are used. The IOSETs are defined in Table 7-25.  
In Table 7-25 are presented the specific groupings of signals (IOSET) for use with QSPI.  
Table 7-25. QSPI IOSETs  
SIGNALS  
IOSET1  
IOSET2  
IOSET3  
IOSET4  
BALL  
C8  
MUX  
BALL  
C8  
MUX  
BALL  
C8  
MUX  
BALL  
C8  
MUX  
qspi1_sclk  
qspi1_rtclk  
qspi1_d0  
qspi1_d1  
qspi1_d2  
qspi1_d3  
qspi1_cs0  
qspi1_cs1  
1
8
1
1
1
1
1
5
1
1
1
1
1
1
1
5
1
5
1
1
1
1
1
5
1
2
1
1
1
1
1
5
C14  
B9  
B7  
F13  
B9  
D8  
B9  
B9  
F10  
A9  
F10  
A9  
F10  
A9  
F10  
A9  
D10  
E10  
F15  
D10  
E10  
F15  
D10  
E10  
F15  
D10  
E10  
F15  
7.15 Multichannel Audio Serial Port (McASP)  
The multichannel audio serial port (McASP) functions as a general-purpose audio serial port optimized for  
the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM)  
stream, Inter-Integrated Sound (I2S) protocols, and inter-component digital audio interface transmission  
(DIT).  
The device has integrated 3 McASP modules (McASP1-McASP3) with:configure the desired virtual  
McASP1 and McASP2 modules supporting 16 channels with independent TX/RX clock/sync domain  
McASP3 module supporting 4 channels with independent TX/RX clock/sync domain  
NOTE  
For more information, see the Serial Communication Interface section of the Device TRM.  
Table 7-26, Table 7-27, Table 7-28 and Figure 7-34 present Timing Requirements for McASP1 to  
McASP3.  
(1)  
Table 7-26. Timing Requirements for McASP1  
NO.  
1
PARAMETER  
tc(AHCLKX)  
DESCRIPTION  
MODE  
MIN  
MAX  
UNIT  
ns  
Cycle time, AHCLKX  
20  
2
tw(AHCLKX)  
Pulse duration, AHCLKX high or low  
0.35P  
ns  
(2)  
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(1)  
Table 7-26. Timing Requirements for McASP1 (continued)  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
MIN  
20  
MAX  
UNIT  
ns  
3
tc(ACLKRX)  
Cycle time, ACLKR/X  
Any Other Conditions  
ACLKX/AFSX (In Sync  
Mode), ACLKR/AFSR (In  
Async Mode), and AXR  
are all inputs  
15.258  
ns  
4
tw(ACLKRX)  
Pulse duration, ACLKR/X high or low  
Any Other Conditions  
0.5R - 3  
ns  
ns  
(3)  
ACLKX/AFSX (In Sync  
Mode), ACLKR/AFSR (In  
Async Mode), and AXR  
are all inputs  
0.38R  
(3)  
5
6
7
8
t su(AFSRX-ACLK)  
t h(ACLK-AFSRX)  
t su(AXR-ACLK)  
t h(ACLK-AXR)  
Setup time, AFSR/X input valid before ACLKR/X  
Hold time, AFSR/X input valid after ACLKR/X  
Setup time, AXR input valid before ACLKR/X  
Hold time, AXR input valid after ACLKR/X  
ACLKR/X int  
18.5  
3
ns  
ns  
ACLKR/X ext in  
ACLKR/X ext out  
ACLKR/X int  
0.5  
0.4  
ns  
ns  
ACLKR/X ext in  
ACLKR/X ext out  
ACLKR/X int  
18.5  
3
ns  
ns  
ACLKR/X ext in  
ACLKR/X ext out  
ACLKR/X int  
0.5  
0.4  
ns  
ns  
ACLKR/X ext in  
ACLKR/X ext out  
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1  
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0  
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1  
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1  
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0  
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1  
(2) P = AHCLKX period in ns.  
(3) R = ACLKR/X period in ns.  
(1)  
Table 7-27. Timing Requirements for McASP2  
NO.  
1
PARAMETER  
tc(AHCLKX)  
DESCRIPTION  
MODE  
MIN  
MAX  
UNIT  
ns  
Cycle time, AHCLKX  
20  
2
tw(AHCLKX)  
Pulse duration, AHCLKX high or low  
0.35P  
ns  
(2)  
3
tc(ACLKRX)  
Cycle time, ACLKR/X  
Any Other Conditions  
20  
ns  
ns  
IOSET1 only,  
ACLKX/AFSX (In Sync  
Mode), ACLKR/AFSR (In  
Async Mode), and AXR  
are all inputs  
15.258  
4
tw(ACLKRX)  
Pulse duration, ACLKR/X high or low  
Any Other Conditions  
0.5R - 3  
ns  
ns  
(3)  
IOSET1 only,  
ACLKX/AFSX (In Sync  
Mode), ACLKR/AFSR (In  
Async Mode), and AXR  
are all inputs  
0.38R  
(3)  
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(1)  
Table 7-27. Timing Requirements for McASP2 (continued)  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
MIN  
18.5  
4
MAX  
UNIT  
ns  
5
t su(AFSRX-ACLK)  
Setup time, AFSR/X input valid before ACLKR/X  
ACLKR/X int  
IOSET1 (vout1_*):  
ACLKR/X ext in  
ns  
IOSET1 (vout1_*):  
ACLKR/X ext out  
IOSET2 (gpmc_*):  
ACLKR/X ext in  
3
ns  
IOSET2 (gpmc_*):  
ACLKR/X ext out  
6
7
t h(ACLK-AFSRX)  
Hold time, AFSR/X input valid after ACLKR/X  
Setup time, AXR input valid before ACLKR/X  
ACLKR/X int  
0.5  
0.4  
ns  
ns  
ACLKR/X ext in  
ACLKR/X ext out  
t su(AXR-ACLK)  
ACLKR/X int  
18.5  
12  
ns  
ns  
IOSET1 (vout1_*):  
ACLKR/X ext in  
IOSET1 (vout1_*):  
ACLKR/X ext out  
IOSET2 (gpmc_*):  
ACLKR/X ext in  
3
ns  
IOSET2 (gpmc_*):  
ACLKR/X ext out  
8
t h(ACLK-AXR)  
Hold time, AXR input valid after ACLKR/X  
ACLKR/X int  
0.5  
0.4  
ns  
ns  
ACLKR/X ext in  
ACLKR/X ext out  
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1  
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0  
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1  
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1  
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0  
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1  
(2) P = AHCLKX period in ns.  
(3) R = ACLKR/X period in ns.  
(1)  
Table 7-28. Timing Requirements for McASP3  
NO.  
1
PARAMETER  
tc(AHCLKX)  
DESCRIPTION  
MODE  
MIN  
20  
MAX  
UNIT  
ns  
Cycle time, AHCLKX  
2
tw(AHCLKX)  
Pulse duration, AHCLKX high or low  
Cycle time, ACLKR/X  
0.35P  
20  
ns  
3
tc(ACLKRX)  
ns  
4
tw(ACLKRX)  
Pulse duration, ACLKR/X high or low  
Setup time, AFSR/X input valid before ACLKR/X  
0.5R - 3  
18.2  
4
ns  
5
t su(AFSRX-ACLK)  
ACLKR/X int  
ns  
ACLKR/X ext in  
ACLKR/X ext out  
ns  
6
8
t h(ACLK-AFSRX)  
t su(AXR-ACLK)  
t h(ACLK-AXR)  
Hold time, AFSR/X input valid after ACLKR/X  
Setup time, AXR input valid before ACLKX  
Hold time, AXR input valid after ACLKX  
ACLKR/X int  
0.5  
0.4  
ns  
ns  
ACLKR/X ext in  
ACLKR/X ext out  
ACLKX int (ASYNC=0)  
18.2  
12  
ns  
ns  
ACLKR/X ext in  
ACLKR/X ext out  
ACLKX int (ASYNC=0)  
0.5  
0.5  
ns  
ns  
ACLKR/X ext in  
ACLKR/X ext out  
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(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1 (NOT SUPPORTED)  
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0  
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1  
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1  
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0  
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1  
(2) P = AHCLKX period in ns.  
(3) R = ACLKR/X period in ns.  
2
1
2
AHCLKX (Falling Edge Polarity)  
AHCLKX (Rising Edge Polarity)  
4
3
4
(A)  
ACLKR/X (CLKRP = CLKXP = 0)  
(B)  
ACLKR/X (CLKRP = CLKXP = 1)  
6
5
AFSR/X (Bit Width, 0 Bit Delay)  
AFSR/X (Bit Width, 1 Bit Delay)  
AFSR/X (Bit Width, 2 Bit Delay)  
AFSR/X (Slot Width, 0 Bit Delay)  
AFSR/X (Slot Width, 1 Bit Delay)  
AFSR/X (Slot Width, 2 Bit Delay)  
8
7
AXR[n] (Data In/Receive)  
A0 A1  
A30 A31 B0 B1  
B30 B31 C0 C1 C2 C3  
C31  
SPRS91v_McASP_01  
A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP  
receiver is configured for falling edge (to shift data in).  
B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP  
receiver is configured for rising edge (to shift data in).  
Figure 7-34. McASP Input Timing  
Table 7-29, Table 7-30, Table 7-31 and Figure 7-35 present Switching Characteristics Over  
Recommended Operating Conditions for McASP1 to McASP3.  
(1)  
Table 7-29. Switching Characteristics Over Recommended Operating Conditions for McASP1  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
MIN  
MAX  
UNIT  
9
tc(AHCLKX)  
Cycle time, AHCLKX  
20  
ns  
166  
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Table 7-29. Switching Characteristics Over Recommended Operating Conditions for McASP1  
(1)  
(continued)  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
MIN  
MAX  
UNIT  
10  
tw(AHCLKX)  
Pulse duration, AHCLKX high or low  
0.5P -  
2.5 (2)  
ns  
11  
12  
tc(ACLKRX)  
tw(ACLKRX)  
Cycle time, ACLKR/X  
20  
ns  
ns  
Pulse duration, ACLKR/X high or low  
0.5P -  
2.5 (3)  
13  
14  
t d(ACLK-AFSXR)  
Delay time, ACLKR/X transmit edge to AFSX/R output  
valid  
ACLKR/X int  
0
2
6
ns  
ns  
ACLKR/X ext in  
ACLKR/X ext out  
22.2  
t d(ACLK-AXR)  
Delay time, ACLKR/X transmit edge to AXR output  
valid  
ACLKR/X int  
0
2
6
ns  
ns  
ACLKR/X ext in  
ACLKR/X ext out  
22.2  
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1  
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0  
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1  
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1  
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0  
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1  
(2) P = AHCLKX period in ns.  
(3) R = ACLKR/X period in ns.  
(1)  
Table 7-30. Switching Characteristics Over Recommended Operating Conditions for McASP2  
NO.  
9
PARAMETER  
tc(AHCLKX)  
DESCRIPTION  
MODE  
MIN  
MAX  
UNIT  
ns  
Cycle time, AHCLKX  
20  
10  
tw(AHCLKX)  
Pulse duration, AHCLKX high or low  
0.5P -  
2.5 (2)  
ns  
11  
12  
tc(ACLKRX)  
tw(ACLKRX)  
Cycle time, ACLKR/X  
20  
ns  
ns  
Pulse duration, ACLKR/X high or low  
0.5P -  
2.5 (3)  
13  
14  
t d(ACLK-AFSXR)  
Delay time, ACLKR/X transmit edge to AFSX/R output  
valid  
ACLKR/X int  
0
2
6
ns  
ns  
ACLKR/X ext in  
ACLKR/X ext out  
22.2  
t d(ACLK-AXR)  
Delay time, ACLKR/X transmit edge to AXR output  
valid  
ACLKR/X int  
0
2
6
ns  
ns  
ACLKR/X ext in  
ACLKR/X ext out  
22.2  
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1  
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0  
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1  
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1  
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0  
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1  
(2) P = AHCLKX period in ns.  
(3) R = ACLKR/X period in ns.  
(1)  
Table 7-31. Switching Characteristics Over Recommended Operating Conditions for McASP3  
NO.  
9
PARAMETER  
tc(AHCLKX)  
DESCRIPTION  
MODE  
MIN  
MAX  
UNIT  
ns  
Cycle time, AHCLKX  
20  
10  
tw(AHCLKX)  
Pulse duration, AHCLKX high or low  
0.5P -  
2.5  
ns  
11  
12  
tc(ACLKRX)  
tw(ACLKRX)  
Cycle time, ACLKR/X  
20  
ns  
ns  
Pulse duration, ACLKR/X high or low  
0.5P -  
2.5  
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Table 7-31. Switching Characteristics Over Recommended Operating Conditions for McASP3  
(1)  
(continued)  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
MIN  
0
MAX  
6
UNIT  
ns  
13  
t d(ACLK-AFSXR)  
Delay time, ACLKR/X transmit edge to AFSX/R output  
valid  
ACLKR/X int  
ACLKR/X ext in  
ACLKR/X ext out  
2
23.1  
ns  
14  
t d(ACLK-AXR)  
Delay time, ACLKR/X transmit edge to AXR output  
valid  
ACLKR/X int  
0
2
6
ns  
ns  
ACLKR/X ext in  
ACLKR/X ext out  
23.1  
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1  
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0  
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1  
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1  
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0  
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1  
(2) P = AHCLKX period in ns.  
(3) R = ACLKR/X period in ns.  
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10  
10  
9
AHCLKX (Falling Edge Polarity)  
AHCLKX (Rising Edge Polarity)  
12  
11  
12  
(A)  
(B)  
ACLKR/X (CLKRP = CLKXP = 1)  
ACLKR/X (CLKRP = CLKXP = 0)  
13  
13  
13  
13  
AFSR/X (Bit Width, 0 Bit Delay)  
AFSR/X (Bit Width, 1 Bit Delay)  
AFSR/X (Bit Width, 2 Bit Delay)  
AFSR/X (Slot Width, 0 Bit Delay)  
AFSR/X (Slot Width, 1 Bit Delay)  
AFSR/X (Slot Width, 2 Bit Delay)  
AXR[n] (Data Out/Transmit)  
13  
13  
13  
14  
15  
A0 A1  
A30 A31 B0 B1  
B30 B31 C0 C1 C2 C3  
C31  
SPRS91v_McASP_02  
A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP  
receiver is configured for rising edge (to shift data in).  
B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP  
receiver is configured for falling edge (to shift data in).  
Figure 7-35. McASP Output Timing  
NOTE  
To configure the desired virtual mode the user must set MODESELECT bit and  
DELAYMODE bit field for each corresponding pad control register.  
The pad control registers are presented Table 4-3 and described in Device TRM, Control  
Module section.  
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CAUTION  
The IO timings provided in this section are only valid if signals within a single  
IOSET are used. The IOSETs are defined in Table 7-32.  
In Table 7-32 and Table 7-33 are presented the specific groupings of signals (IOSET) for use with  
McASP1 and McASP2.  
Table 7-32. McASP1 IOSETs  
SIGNALS  
IOSET1  
IOSET2  
IOSET3  
BALL  
U17  
MUX  
1
BALL  
U17  
MUX  
BALL  
U17  
MUX  
mcasp1_aclkx  
mcasp1_fsx  
1
1
1
1
W17  
AA17  
U16  
1
W17  
W17  
mcasp1_aclkr  
mcasp1_fsr  
1
1
mcasp1_axr0  
mcasp1_axr1  
mcasp1_axr2  
mcasp1_axr3  
mcasp1_axr4  
mcasp1_axr5  
mcasp1_axr6  
mcasp1_axr7  
mcasp1_axr8  
mcasp1_axr9  
mcasp1_axr10  
mcasp1_axr11  
mcasp1_axr12  
mcasp1_axr13  
mcasp1_axr14  
mcasp1_axr15  
W16  
V16  
1
W16  
V16  
1
1
W16  
V16  
1
1
1
U15  
1
V15  
1
Y15  
1
W15  
AA15  
AB15  
AA14  
AB14  
1
1
1
1
AA14  
AB14  
U13  
V13  
1
1
1
1
1
1
1
1
U15  
V15  
Y15  
W15  
AA15  
AB15  
U7  
4
4
4
4
4
4
4
4
1
Y13  
W13  
U11  
V11  
V7  
Table 7-33. McASP2 IOSETs  
SIGNALS  
IOSET1  
MUX(1)  
15  
IOSET2  
BALL  
Y13  
U11  
V11  
W13  
W11  
V9  
BALL  
C6  
F7  
MUX(1)  
mcasp2_ahclkx  
mcasp2_aclkx  
mcasp2_fsx  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
E7  
mcasp2_aclkr  
mcasp2_fsr  
15  
B6  
15  
A5  
mcasp2_axr0  
mcasp2_axr1  
mcasp2_axr2  
mcasp2_axr3  
mcasp2_axr4  
mcasp2_axr5  
15  
D6  
C5  
B5  
W9  
15  
U8  
15  
W8  
15  
D7  
B4  
U7  
15  
V7  
15  
A4  
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(1) All McASP2 signals are virtual functions that present alternate multiplexing options. These virtual functions are controlled via  
CTRL_CORE_SMA_SW_* registers. For more information on how to use these options, please refer to the Device TRM, Chapter  
Control Module, Section Pad Configuration Registers.  
7.16 Controller Area Network Interface (DCAN and MCAN)  
7.16.1 DCAN  
The device provides one DCAN interface for supporting distributed realtime control with a high level of  
security.  
The DCAN interface implements the following features:  
Supports CAN protocol version 2.0 part A, B  
Bit rates up to 1 MBit/s  
64 message objects  
Individual identifier mask for each message object  
Programmable FIFO mode for message objects  
Programmable loop-back modes for self-test operation  
Suspend mode for debug support  
Automatic bus on after Bus-Off state by a programmable 32-bit timer  
Message RAM single error correction and double error detection (SECDED) mechanism  
Direct access to Message RAM during test mode  
Support for two interrupt lines: Level 0 and Level 1, plus separate ECC interrupt line  
Local power down and wakeup support  
Automatic message RAM initialization  
Support for DMA access  
7.16.2 MCAN  
The device supports one MCAN module connecting to the CAN network through external (for the device)  
transceiver for connection to the physical layer. The MCAN module supports up to 5 Mbit/s data rate and  
is compliant to ISO 11898-1:2015.  
The MCAN module implements the following features:  
Conforms with ISO 11898-1:2015  
Full CAN FD support (up to 64 data bytes)  
AUTOSAR and SAE J1939 support  
Up to 32 dedicated Transmit Buffers  
Configurable Transmit FIFO, up to 32 elements  
Configurable Transmit Queue, up to 32 elements  
Configurable Transmit Event FIFO, up to 32 elements  
Up to 64 dedicated Receive Buffers  
Two configurable Receive FIFOs, up to 64 elements each  
Up to 128 filter elements  
Internal Loopback mode for self-test  
Maskable interrupts, two interrupt lines  
Two clock domains (CAN clock/Host clock)  
Parity/ECC support - Message RAM single error correction and double error detection (SECDED)  
mechanism  
Local power-down and wakeup support  
Timestamp Counter  
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NOTE  
For more information, see the Serial Communication Interfaces / DCAN and MCAN sections  
of the Device TRM.  
NOTE  
Refer to the CAN Specification for calculations necessary to validate timing compliance. Jitter  
tolerance calculations must be performed to validate the implementation.  
Table 7-34 and Table 7-35 present Timing and Switching characteristics for DCAN and MCAN Interface.  
Table 7-34. Timing Requirements for CAN Receive  
NO.  
PARAMETER  
f(baud)  
t d(CANnRX)  
DESCRIPTION  
Maximum programmable baud rate  
MIN  
NOM  
MAX  
1
UNIT  
Mbps  
ns  
-
Delay time, CANnRX pin to receive shift register  
10  
Table 7-35. Switching Characteristics Over Recommended Operating Conditions for CAN Transmit  
NO.  
PARAMETER  
f(baud)  
t d(CANnTX)  
DESCRIPTION  
Maximum programmable baud rate  
Delay time, Transmit shift register to CANnTX pin(1)  
MIN  
MAX  
1
UNIT  
Mbps  
ns  
-
10  
(1) These values do not include rise/fall times of the output buffer.  
CAUTION  
The IO timings provided in this section are only valid if signals within a single  
IOSET are used. The IOSETs are defined in Table 7-36.  
In Table 7-36 are presented the specific groupings of signals (IOSET) for use with DCAN and MCAN.  
Table 7-36. DCAN and MCAN IOSETs  
SIGNALS  
IOSET1  
IOSET2  
IOSET3  
IOSET4  
BALL  
MUX  
BALL  
MUX  
DCAN1  
12  
BALL  
MUX  
BALL  
MUX  
dcan1_tx  
dcan1_rx  
N5  
N6  
0
0
D14  
D15  
F14  
C14  
12  
12  
12  
MCAN  
0
mcan_tx  
mcan_rx  
W7  
W6  
F13  
E14  
12  
12  
F15  
F16  
12  
12  
0
7.17 Ethernet Interface (GMAC_SW)  
The two-port gigabit ethernet switch subsystem (GMAC_SW) provides ethernet packet communication  
and can be configured as an ethernet switch. It provides Reduced Gigabit Media Independent Interface  
(RGMII), and the Management Data Input/Output (MDIO) for physical layer device (PHY) management.  
NOTE  
For more information, see the Gigabit Ethernet Switch (GMAC_SW) section of the Device  
TRM.  
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NOTE  
The Gigabit, Reduced and Media Independent Interface n (n = 0 to 1) are also referred to as  
RGMIIn  
7.17.1 GMAC MDIO Interface Timings  
Table 7-37, Table 7-38 and Figure 7-36 present Timing Requirements for MDIO.  
Table 7-37. Timing Requirements for MDIO Input  
No  
PARAMETER  
DESCRIPTION  
MIN  
400  
160  
160  
90  
MAX  
UNIT  
ns  
MDIO1 tc(MDC)  
Cycle time, MDC  
MDIO2 tw(MDCH)  
MDIO3 tw(MDCL)  
MDIO4 tsu(MDIO-MDC)  
MDIO5 th(MDIO_MDC)  
Pulse Duration, MDC High  
Pulse Duration, MDC Low  
Setup time, MDIO valid before MDC High  
Hold time, MDIO valid from MDC High  
ns  
ns  
ns  
0
ns  
Table 7-38. Switching Characteristics Over Recommended Operating Conditions for MDIO Output  
No  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
5
UNIT  
ns  
MDIO6 tt(MDC)  
Transition time, MDC  
MDIO7 td(MDC-MDIO)  
Delay time, MDC low to MDIO valid  
-150  
150  
ns  
MDIO1  
MDIO2  
MDIO3  
MDCLK  
MDIO6  
MDIO6  
MDIO4  
MDIO5  
MDIO  
(input)  
MDIO7  
MDIO  
(output)  
Figure 7-36. GMAC MDIO diagrams  
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7.17.2 GMAC RGMII Timings  
Table 7-39, Table 7-40 and Figure 7-37 present Timing Requirements for receive RGMIIn operation.  
Table 7-39. Timing Requirements for rgmiin_rxc - RGMIIn Operation  
NO.  
PARAMETER  
DESCRIPTION  
SPEED  
10 Mbps  
MIN  
360  
36  
MAX  
440  
44  
UNIT  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
1
tc(RXC)  
Cycle time, rgmiin_rxc  
100 Mbps  
1000 Mbps  
10 Mbps  
7.2  
160  
16  
8.8  
2
3
4
tw(RXCH)  
tw(RXCL)  
tt(RXC)  
Pulse duration, rgmiin_rxc high  
Pulse duration, rgmiin_rxc low  
Transition time, rgmiin_rxc  
240  
24  
100 Mbps  
1000 Mbps  
10 Mbps  
3.6  
160  
16  
4.4  
240  
24  
100 Mbps  
1000 Mbps  
10 Mbps  
3.6  
4.4  
0.75  
0.75  
0.75  
100 Mbps  
1000 Mbps  
Table 7-40. Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps  
NO.  
5
PARAMETER  
tsu(RXD-RXCH)  
th(RXCH-RXD)  
DESCRIPTION  
MIN  
1.15  
1.15  
MAX  
UNIT  
ns  
Setup time, receive selected signals valid before rgmiin_rxc high/low  
Hold time, receive selected signals valid after rgmiin_rxc high/low  
6
ns  
(1) For RGMII, receive selected signals include: rgmiin_rxd[3:0] and rgmiin_rxctl.  
(2) RGMII0 requires that the 4 data pins rgmii0_rxd[3:0] and rgmii0_rxctl have their board propagation delays matched within 50pS of  
rgmii0_rxc.  
(3) RGMII1 requires that the 4 data pins rgmii1_rxd[3:0] and rgmii1_rxctl have their board propagation delays matched within 50pS of  
rgmii1_rxc.  
1
4
2
4
3
rgmiin_rxc(A)  
5
1st Half-byte  
6
2nd Half-byte  
rgmiin_rxd[3:0](B)  
rgmiin_rxctl(B)  
RGRXD[3:0]  
RXDV  
RGRXD[7:4]  
RXERR  
SPRS91v_GMAC_08  
A. rgmiin_rxc must be externally delayed relative to the data and control pins.  
B. Data and control information is received using both edges of the clocks. rgmiin_rxd[3:0] carries data bits 3-0 on the  
rising edge of rgmiin_rxc and data bits 7-4 on the falling edge ofrgmiin_rxc. Similarly, rgmiin_rxctl carries RXDV on  
rising edge of rgmiin_rxc and RXERR on falling edge of rgmiin_rxc.  
Figure 7-37. GMAC Receive Interface Timing, RGMIIn operation  
Table 7-41, Table 7-42 and Figure 7-38 present Switching Characteristics for rgmiin_txctl - RGMIIn  
Operation for 10/100/1000 Mbit/s  
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Table 7-41. Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn  
Operation for 10/100/1000 Mbit/s  
NO.  
PARAMETER  
DESCRIPTION  
SPEED  
10 Mbps  
MIN  
360  
36  
MAX  
440  
44  
UNIT  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
1
tc(TXC)  
Cycle time, rgmiin_txc  
100 Mbps  
1000 Mbps  
10 Mbps  
7.2  
160  
16  
8.8  
2
3
4
tw(TXCH)  
tw(TXCL)  
tt(TXC)  
Pulse duration, rgmiin_txc high  
Pulse duration, rgmiin_txc low  
Transition time, rgmiin_txc  
240  
24  
100 Mbps  
1000 Mbps  
10 Mbps  
3.6  
160  
16  
4.4  
240  
24  
100 Mbps  
1000 Mbps  
10 Mbps  
3.6  
4.4  
0.75  
0.75  
0.75  
100 Mbps  
1000 Mbps  
Table 7-42. Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps (1)  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
MIN  
MAX  
UNIT  
5
tosu(TXD-TXC)  
Output Setup time, transmit selected signals  
valid to rgmiin_txc high/low  
RGMII0, Internal Delay  
Enabled, 1000 Mbps  
ns  
RGMII0, Internal Delay  
Enabled, 10/100 Mbps  
1.2  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RGMII1, Internal Delay  
Enabled, 1000 Mbps  
RGMII1, Internal Delay  
Enabled, 10/100 Mbps  
1.2  
1.2  
1.2  
6
toh(TXC-TXD)  
Output Hold time, transmit selected signals  
valid after rgmiin_txc high/low  
RGMII0, Internal Delay  
Enabled, 1000 Mbps  
RGMII0, Internal Delay  
Enabled, 10/100 Mbps  
RGMII1, Internal Delay  
Enabled, 1000 Mbps  
RGMII1, Internal Delay  
Enabled, 10/100 Mbps  
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(1) For RGMII, transmit selected signals include: rgmiin_txd[3:0] and rgmiin_txctl.  
(2) RGMII0 1000Mbps operation is not supported.  
(3) RGMII1 1000Mbps operation is not supported.  
1
4
2
4
3
rgmiin_txc(A)  
[internal delay enabled]  
5
rgmiin_txd[3:0](B)  
rgmiin_txctl(B)  
1st Half-byte  
TXEN  
2nd Half-byte  
TXERR  
6
SPRS91v_GMAC_09  
A. TXC is delayed internally before being driven to the rgmiin_txc pin. This internal delay is always enabled.  
B. Data and control information is transmitted using both edges of the clocks. rgmiin_txd[3:0] carries data bits 3-0 on the  
rising edge of rgmiin_txc and data bits 7-4 on the falling edge of rgmiin_txc. Similarly, rgmiin_txctl carries TXEN on  
rising edge of rgmiin_txc and TXERR of falling edge of rgmiin_txc.  
Figure 7-38. GMAC Transmit Interface Timing RGMIIn operation  
7.18 SDIO Controller  
MMC interface is compliant with the SDIO3.0 standard v1.0, SD Part E1 and for generic SDIO devices, it  
supports the following applications:  
MMC 4-bit data, SD Default speed, SDR  
MMC 4-bit data, SD High speed, SDR  
MMC 4-bit data, UHS-I SDR12 (SD Standard v3.01), 4-bit data, SDR, half cycle  
MMC 4-bit data, UHS-I SDR25 (SD Standard v3.01), 4-bit data, SDR, half cycle  
NOTE  
For more information, see the SDIO Controller chapter of the Device TRM.  
7.18.1 MMC, SD Default Speed  
Figure 7-39, Figure 7-40, and Table 7-43 through Table 7-44 present Timing requirements and Switching  
characteristics for MMC - SD and SDIO Default speed in receiver and transmiter mode.  
Table 7-43. Timing Requirements for MMC - Default Speed Mode  
NO.  
DS5  
DS6  
DS7  
DS8  
PARAMETER  
tsu(cmdV-clkH)  
th(clkH-cmdV)  
tsu(dV-clkH)  
DESCRIPTION  
MIN  
5.11  
MAX  
UNIT  
ns  
Setup time, mmc_cmd valid before mmc_clk rising clock edge  
Hold time, mmc_cmd valid after mmc_clk rising clock edge  
Setup time, mmc_dat[i:0] valid before mmc_clk rising clock edge  
Hold time, mmc_dat[i:0] valid after mmc_clk rising clock edge  
20.46  
5.11  
ns  
ns  
th(clkH-dV)  
20.46  
ns  
(1) i in [i:0] = 3  
Table 7-44. Switching Characteristics for MMC - SD/SDIO Default Speed Mode  
NO.  
DS0  
DS1  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
tw(clkH)  
Operating frequency, mmc_clk  
Pulse duration, mmc_clk high  
24  
0.5×P-  
0.270  
176  
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Table 7-44. Switching Characteristics for MMC - SD/SDIO Default Speed Mode (continued)  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
DS2  
tw(clkL)  
Pulse duration, mmc_clk low  
0.5×P-  
0.270  
ns  
DS3  
DS4  
td(clkL-cmdV)  
td(clkL-dV)  
Delay time, mmc_clk falling clock edge to mmc_cmd transition  
Delay time, mmc_clk falling clock edge to mmc_dat[i:0] transition  
-14.93  
-14.93  
14.93  
14.93  
ns  
ns  
(1) P = output mmc_clk period in ns  
(2) i in [i:0] = 3  
DS2  
DS1  
DS0  
mmc_clk  
mmc_cmd  
DS6  
DS5  
DS8  
DS7  
mmc_dat[3:0]  
SPRS91v_MMC_01  
Figure 7-39. MMC/SD/SDIOj in - Default Speed - Receiver Mode  
DS2  
DS1  
DS0  
mmc_clk  
DS3  
DS4  
mmc_cmd  
mmc_dat[3:0]  
SPRS91v_MMC_02  
Figure 7-40. MMC/SD/SDIOj in - Default Speed - Transmiter Mode  
7.18.2 MMC, SD High Speed  
Figure 7-41, Figure 7-42, and Table 7-45 through Table 7-46 present Timing requirements and Switching  
characteristics for MMC - SD and SDIO High speed in receiver and transmiter mode.  
Table 7-45. Timing Requirements for MMC - SD/SDIO High Speed Mode  
NO.  
HS3  
HS4  
HS7  
HS8  
PARAMETER  
tsu(cmdV-clkH)  
th(clkH-cmdV)  
tsu(dV-clkH)  
DESCRIPTION  
MIN  
5.3  
2.6  
5.3  
2.6  
MAX  
UNIT  
ns  
Setup time, mmc_cmd valid before mmc_clk rising clock edge  
Hold time, mmc_cmd valid after mmc_clk rising clock edge  
Setup time, mmc_dat[i:0] valid before mmc_clk rising clock edge  
Hold time, mmc_dat[i:0] valid after mmc_clk rising clock edge  
ns  
ns  
th(clkH-dV)  
ns  
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Table 7-46. Switching Characteristics for MMC - SD/SDIO High Speed Mode  
NO.  
HS1  
PARAMETER  
fop(clk)  
DESCRIPTION  
MIN  
MAX  
UNIT  
MHz  
ns  
Operating frequency, mmc_clk  
Pulse duration, mmc_clk high  
48  
HS2H  
tw(clkH)  
0.5×P-  
0.270  
HS2L  
tw(clkL)  
Pulse duration, mmc_clk low  
0.5×P-  
0.270  
ns  
HS5  
HS6  
td(clkL-cmdV)  
td(clkL-dV)  
Delay time, mmc_clk falling clock edge to mmc_cmd transition  
Delay time, mmc_clk falling clock edge to mmc_dat[i:0] transition  
-7.6  
-7.6  
3.6  
3.6  
ns  
ns  
(1) P = output mmc_clk period in ns  
(2) i in [i:0] = 3  
HS1  
HS2H  
HS2L  
mmc_clk  
mmc_cmd  
HS4  
HS3  
HS7  
HS8  
mmc_dat[3:0]  
SPRS91v_MMC_03  
Figure 7-41. MMC/SD/SDIOj in - High Speed - Receiver Mode  
HS1  
HS2H  
HS2L  
mmc_clk  
mmc_cmd  
HS5  
HS5  
HS6  
HS6  
mmc_dat[3:0]  
SPRS91v_MMC_04  
Figure 7-42. MMC/SD/SDIOj in - High Speed - Transmiter Mode  
7.18.3 MMC, SD and SDIO SDR12 Mode  
Figure 7-43, Figure 7-44, and Table 7-47, through Table 7-48 present Timing requirements and Switching  
characteristics for MMC - SD and SDIO SDR12 in receiver and transmiter mode.  
Table 7-47. Timing Requirements for MMC - SDR12 Mode  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
25.99  
1.6  
MAX  
UNIT  
ns  
SDR125 tsu(cmdV-clkH)  
SDR126 th(clkH-cmdV)  
SDR127 tsu(dV-clkH)  
SDR128 th(clkH-dV)  
Setup time, mmc_cmd valid before mmc_clk rising clock edge  
Hold time, mmc_cmd valid after mmc_clk rising clock edge  
Setup time, mmc_dat[i:0] valid before mmc_clk rising clock edge  
Hold time, mmc_dat[i:0] valid after mmc_clk rising clock edge  
ns  
25.99  
1.6  
ns  
ns  
178  
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Table 7-48. Switching Characteristics for MMC - SDR12 Mode  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
MHz  
ns  
SDR120 fop(clk)  
SDR121 tw(clkH)  
Operating frequency, mmc_clk  
Pulse duration, mmc_clk high  
24  
0.5×P-  
0.270  
SDR122 tw(clkL)  
Pulse duration, mmc_clk low  
0.5×P-  
0.270  
ns  
SDR123 td(clkL-cmdV)  
SDR124 td(clkL-dV)  
Delay time, mmc_clk falling clock edge to mmc_cmd transition  
Delay time, mmc_clk falling clock edge to mmc_dat[i:0] transition  
-19.13  
-19.13  
16.93  
16.93  
ns  
ns  
(1) P = output mmc_clk period in ns  
(2) i in [i:0] = 3  
SDR122  
SDR121  
SDR120  
mmc_clk  
mmc_cmd  
SDR126  
SDR125  
SDR128  
SDR127  
mmc_dat[3:0]  
SPRS91v_MMC_05  
Figure 7-43. MMC/SD/SDIOj in - SDR12 - Receiver Mode  
SDR122  
SDR121  
SDR120  
mmc_clk  
SDR123  
SDR124  
mmc_cmd  
mmc_dat[3:0]  
SPRS91v_MMC_06  
Figure 7-44. MMC/SD/SDIOj in - SDR12 - Transmiter Mode  
7.18.4 MMC, SD SDR25 Mode  
Figure 7-45, Figure 7-46, and Table 7-49, through Table 7-50 present Timing requirements and Switching  
characteristics for MMC - SD and SDIO SDR25 in receiver and transmiter mode.  
(1)  
Table 7-49. Timing Requirements for MMC - SDR25 Mode  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
5.3  
1.6  
5.3  
1.6  
MAX  
UNIT  
ns  
SDR253 tsu(cmdV-clkH)  
SDR254 th(clkH-cmdV)  
SDR257 tsu(dV-clkH)  
SDR258 th(clkH-dV)  
Setup time, mmc_cmd valid before mmc_clk rising clock edge  
Hold time, mmc_cmd valid after mmc_clk rising clock edge  
Setup time, mmc_dat[i:0] valid before mmc_clk rising clock edge  
Hold time, mmc_dat[i:0] valid after mmc_clk rising clock edge  
ns  
ns  
ns  
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(2)  
Table 7-50. Switching Characteristics for MMC - SDR25 Mode  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
MHz  
ns  
SDR251 fop(clk)  
Operating frequency, mmc_clk  
Pulse duration, mmc_clk high  
48  
SDR252 tw(clkH)  
H
0.5×P-  
0.270  
SDR252L tw(clkL)  
Pulse duration, mmc_clk low  
0.5×P-  
0.270  
ns  
SDR255 td(clkL-cmdV)  
SDR256 td(clkL-dV)  
Delay time, mmc_clk falling clock edge to mmc_cmd transition  
Delay time, mmc_clk falling clock edge to mmc_dat[i:0] transition  
-8.8  
-8.8  
6.6  
6.6  
ns  
ns  
(1) P = output mmc_clk period in ns  
(2) i in [i:0] = 3  
SDR251  
SDR252L  
SDR253  
SDR252H  
mmc_clk  
mmc_cmd  
SDR254  
SDR258  
SDR257  
mmc_dat[3:0]  
SPRS91v_MMC_07  
Figure 7-45. MMC/SD/SDIOj in - SDR25 - Receiver Mode  
SDR251  
SDR252H  
SDR252L  
SDR255  
mmc_clk  
mmc_cmd  
SDR255  
SDR256  
SDR256  
mmc_dat[3:0]  
SPRS91v_MMC_08  
Figure 7-46. MMC/SD/SDIOj in - SDR25 - Transmiter Mode  
CAUTION  
The IO timings provided in this section are only valid if signals within a single  
IOSET are used. The IOSETs are defined in Table 7-51.  
In Table 7-51 are presented the specific groupings of signals (IOSET) for use with MMC.  
Table 7-51. MMC IOSETs  
SIGNALS  
IOSET1  
IOSET2  
IOSET3  
BALL  
C16  
C17  
E16  
MUX  
BALL  
W16  
V16  
MUX  
BALL  
B18  
MUX  
mmc_clk  
mmc_cmd  
mmc_dat0  
mmc_dat1  
5
5
5
5
5
5
5
5
5
5
5
5
C18  
A19  
U15  
D16  
V15  
B20  
180  
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Table 7-51. MMC IOSETs (continued)  
SIGNALS  
IOSET1  
IOSET2  
IOSET3  
BALL  
E17  
MUX  
BALL  
Y15  
MUX  
BALL  
C20  
MUX  
mmc_dat2  
mmc_dat3  
5
5
5
5
5
5
F17  
W15  
A20  
7.19 General-Purpose Interface (GPIO)  
The general-purpose interface combines four general-purpose input/output (GPIO) banks. Each GPIO  
module provides up to 32 dedicated general-purpose pins with input and output capabilities; thus, the  
general-purpose interface supports up to 126 pins.  
These pins can be configured for the following applications:  
Data input (capture)/output (drive)  
Keyboard interface with a debounce cell  
Interrupt generation in active mode upon the detection of external events. Detected events are  
processed by two parallel independent interrupt-generation submodules to support biprocessor  
operations  
Wake-up request generation in idle mode upon the detection of external events  
NOTE  
For more information, see the General-Purpose Interface chapter of the Device TRM.  
NOTE  
The general-purpose input/output i (i = 1 to 4) bank is also referred to as GPIOi.  
CAUTION  
The IO timings provided in this section are only valid if signals within a single  
IOSET are used. The IOSETs are defined in Table 7-52.  
In Table 7-52 are presented the specific groupings of signals (IOSET) for use with GPIO.  
Table 7-52. GPIO2/3/4 IOSETs  
SIGNALS  
IOSET1  
IOSET2  
BALL  
MUX  
BALL  
MUX  
GPIO2  
gpio2_11  
gpio2_12  
gpio2_13  
gpio2_14  
gpio2_20  
gpio2_23  
gpio2_24  
gpio2_27  
gpio2_28  
gpio2_29  
gpio2_30  
gpio2_31  
J17  
K22  
14  
14  
14  
14  
14  
14  
14  
K21  
K18  
AB17  
AA17  
U16  
AA17  
U16  
14  
14  
14  
14  
14  
14  
14  
U15  
V15  
Y15  
W15  
AA15  
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Table 7-52. GPIO2/3/4 IOSETs (continued)  
SIGNALS  
IOSET1  
IOSET2  
BALL  
MUX  
GPIO3  
14  
BALL  
MUX  
gpio3_0  
gpio3_9  
AB15  
U9  
14  
U9  
W11  
V9  
14  
14  
14  
14  
14  
14  
gpio3_10  
gpio3_11  
gpio3_12  
gpio3_13  
gpio3_14  
gpio3_15  
gpio3_16  
W11  
V9  
14  
14  
W9  
U8  
14  
W9  
U8  
14  
W8  
U7  
14  
W8  
14  
V7  
14  
GPIO4  
gpio4_4  
gpio4_6  
gpio4_7  
gpio4_8  
gpio4_9  
gpio4_10  
R5  
N4  
R7  
L2  
14  
14  
14  
14  
14  
14  
N5  
N6  
7.20 Test Interfaces  
The device includes the following Test interfaces:  
IEEE 1149.1 Standard-Test-Access Port ( JTAG®)  
Trace Port Interface Unit (TPIU)  
7.20.1 JTAG Electrical Data/Timing  
Table 7-53, Table 7-54 and Figure 7-47 assume testing over the recommended operating conditions and  
electrical characteristic conditions below.  
Table 7-53. Timing Requirements for IEEE 1149.1 JTAG  
NO.  
1
PARAMETER  
tc(TCK)  
DESCRIPTION  
MIN  
62.29  
24.92  
24.92  
6.23  
MAX  
UNIT  
ns  
Cycle time, TCK  
1a  
1b  
3
tw(TCKH)  
Pulse duration, TCK high (40% of tc)  
Pulse duration, TCK low (40% of tc)  
Input setup time, TDI valid to TCK high  
Input setup time, TMS valid to TCK high  
Input hold time, TDI valid from TCK high  
Input hold time, TMS valid from TCK high  
ns  
tw(TCKL)  
ns  
tsu(TDI-TCK)  
tsu(TMS-TCK)  
th(TCK-TDI)  
th(TCK-TMS)  
ns  
6.23  
ns  
4
31.15  
31.15  
ns  
ns  
Table 7-54. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
2
td(TCKL-TDOV)  
Delay time, TCK low to TDO valid  
0
30.5  
ns  
182  
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1
1a  
1b  
TCK  
TDO  
2
3
4
TDI/TMS  
SPRS91v_JTAG_01  
Figure 7-47. JTAG Timing  
Table 7-55, Table 7-56 and Figure 7-48 assume testing over the recommended operating conditions and  
electrical characteristic conditions below.  
Table 7-55. Timing Requirements for IEEE 1149.1 JTAG With RTCK  
NO.  
1
PARAMETER  
tc(TCK)  
DESCRIPTION  
MIN  
62.29  
24.92  
24.92  
6.23  
MAX  
UNIT  
ns  
Cycle time, TCK  
1a  
1b  
3
tw(TCKH)  
Pulse duration, TCK high (40% of tc)  
Pulse duration, TCK low(40% of tc)  
Input setup time, TDI valid to TCK high  
Input setup time, TMS valid to TCK high  
Input hold time, TDI valid from TCK high  
Input hold time, TMS valid from TCK high  
ns  
tw(TCKL)  
ns  
tsu(TDI-TCK)  
tsu(TMS-TCK)  
th(TCK-TDI)  
th(TCK-TMS)  
ns  
6.23  
ns  
4
31.15  
31.15  
ns  
ns  
Table 7-56. Switching Characteristics Over Recommended Operating Conditions for  
IEEE 1149.1 JTAG With RTCK  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
5
td(TCK-RTCK)  
Delay time, TCK to RTCK with no selected subpaths (i.e. ICEPick is  
the only tap selected - when the Arm is in the scan chain, the delay  
time is a function of the Arm functional clock).  
0
27  
ns  
6
7
8
tc(RTCK)  
Cycle time, RTCK  
62.29  
24.92  
24.92  
ns  
ns  
ns  
tw(RTCKH)  
tw(RTCKL)  
Pulse duration, RTCK high (40% of tc)  
Pulse duration, RTCK low (40% of tc)  
5
TCK  
6
7
8
RTCK  
SPRS91v_JTAG_02  
Figure 7-48. JTAG With RTCK Timing  
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7.20.2 Trace Port Interface Unit (TPIU)  
7.20.2.1 TPIU PLL DDR Mode  
Table 7-57 and Figure 7-49 assume testing over the recommended operating conditions and electrical  
characteristic conditions below.  
Table 7-57. Switching Characteristics for TPIU  
NO.  
PARAMETER  
tc(clk)  
DESCRIPTION  
MIN  
5.56  
-1.61  
-1.61  
MAX  
UNIT  
ns  
TPIU1  
TPIU4  
TPIU5  
Cycle time, TRACECLK period  
td(clk-ctlV)  
Skew time, TRACECLK transition to TRACECTL transition  
Skew time, TRACECLK transition to TRACEDATA[17:0] transition  
1.98  
1.98  
ns  
td(clk-dataV)  
ns  
(1) P = TRACECLK period in ns  
(2) The listed pulse duration is a typical value  
TPIU1  
TPIU2  
TPIU3  
TRACECLK  
TRACECTL  
TPIU4  
TPIU4  
TPIU5  
TPIU5  
TRACEDATA[X:0]  
SPRS91v_TPIU_01  
Figure 7-49. TPIU—PLL DDR Transmit Mode(1)  
(1) In d[X:0], X is equal to 15 or 17.  
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8 Applications, Implementation, and Layout  
NOTE  
Information in the following applications sections is not part of the TI component  
specification, and TI does not warrant its accuracy or completeness. TI’s customers are  
responsible for determining suitability of components for their purposes. Customers should  
validate and test design implementation to confirm system functionality.  
8.1 Introduction  
This chapter is intended to communicate, guide and illustrate a PCB design strategy resulting in a PCB  
that can support TI’s latest Application Processor. This Processor is a high-performance processor  
designed for automotive Infotainment based on enhanced OMAP™ architecture integrated on a 28-nm  
CMOS process technology.  
These guidelines first focus on designing a robust Power Delivery Network (PDN) which is essential to  
achieve the desirable high performance processing available on Device. The general principles and step-  
by-step approach for implementing good power integrity (PI) with specific requirements will be described  
for the key Device power domains.  
TI strongly believes that simulating a PCB’s proposed PDN is required for first pass PCB design success.  
Key Device processor high-current power domains need to be evaluated for Power Rail IR Drop,  
Decoupling Capacitor Loop-Inductance and Power Rail Target Impedance. Only then can a PCB’s PDN  
performance be truly accessed by comparing these model PI parameters vs. TI’s recommended values.  
Ultimately for any high-volume product, TI recommends conducting a "Processor PDN Validation" test on  
prototype PCBs across processor "split lots" to verify PDN robustness meets desired performance goals  
for each customer’s worst-case scenario. Please contact your TI representative to receive guidance on  
PDN PI modeling and validation testing.  
Likewise, the methodology and requirements needed to route Device high speed, differential interfaces ,  
single-ended interfaces (i.e. DDR3, QSPI) and general purpose interfaces using LVCMOS drivers that  
meet timing requirements while minimizing signal integrity (SI) distortions on the PCB’s signaling traces.  
Signal trace lengths and flight times are aligned with FR-4 standard specification for PCBs.  
Several different PCB layout stack-up examples have been presented to illustrate a typical number of  
layers, signal assignments and controlled impedance requirements. Different Device interface signals  
demand more or less complexity for routing and controlled impedance stack-ups. Optimizing the PCB’s  
PDN stack-up needs with all of these different types of signal interfaces will ultimately determine the final  
layer count and layer assignments in each customer’s PCB design.  
This guideline must be used as a supplement in complement to TI’s Application Processor, Power  
Management IC (PMIC) and Audio Companion components along with other TI component technical  
documentation (i.e. Technical Reference Manual, Data Manual, Data Sheets, Silicon Errata, Pin-Out  
Spreadsheet, Application Notes, etc.).  
NOTE  
Notwithstanding any provision to the contrary, TI makes no warranty expressed, implied, or  
statutory, including any implied warranty of merchantability of fitness for a specific purpose,  
for customer boards. The data described in this appendix are intended as guidelines only.  
NOTE  
These PCB guidelines are in a draft maturity and consequently, are subject to change  
depending on design verification testing conducted during IC development and validation.  
Note also that any references to Application Processor’s ballout or pin muxing are subject to  
change following the processor’s ballout maturity.  
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8.1.1 Initial Requirements and Guidelines  
Unless otherwise specified, the characteristic impedance for single-ended interfaces is recommended to  
be between 35 Ω and 65 Ω to minimize the overshoot or undershoot on far-end loads.  
Characteristic impedance for differential interfaces must be routed as differential traces on the same layer.  
The trace width and spacing must be chosen to yield the recommended differential impedance. For more  
information see Section 8.5.1.  
The PDN must be optimized for low trace resistance and low trace inductance for all high-current power  
nets from PMIC to the device.  
An external interface using a connector must be protected following the IEC61000-4-2 level 4 system  
ESD.  
8.2 Power Optimizations  
This section describes the necessary steps for designing a robust Power Distribution Network (PDN):  
Section 8.2.1, Step 1: PCB Stack-up  
Section 8.2.2, Step 2: Physical Placement  
Section 8.2.3, Step 3: Static Analysis  
Section 8.2.4, Step 4: Frequency Analysis  
8.2.1 Step 1: PCB Stack-up  
The PCB stack-up (layer assignment) is an important factor in determining the optimal performance of the  
power distribution system. An optimized PCB stack-up for higher power integrity performance can be  
achieved by following these recommendations:  
Power and ground plane pairs must be closely coupled together. The capacitance formed between the  
planes can decouple the power supply at high frequencies. Whenever possible, the power and ground  
planes must be solid to provide continuous return path for return current.  
Use a thin dielectric between the power and ground plane pair. Capacitance is inversely proportional to  
the separation of the plane pair. Minimizing the separation distance (the dielectric thickness)  
maximizes the capacitance.  
Optimize the power and ground plane pair carrying high current supplies to key component power  
domains as close as possible to the same surface where these components are placed (see Figure 8-  
1). This will help to minimize "loop inductance" encountered between supply decoupling capacitors and  
component supply inputs and between power and ground plane pairs.  
NOTE  
1-2oz Cu weight for power / ground plane is preferred to enable better PCB heat spreading,  
helping to reduce Processor junction temperatures. In addition, it is preferable to have the  
power / ground planes be adjacent to the PCB surface on which the Processor is mounted.  
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Capacitor  
Trace  
DIE  
Package  
Via  
3
1
Power/Ground  
Ground/Power  
2
Loop inductance  
Note: 1. BGA via pair loop inductance  
2. Power/Ground net spreading inductance  
3. Capacitor trace inductance  
SPRS91v_PCB_STACKUP_01  
Figure 8-1. Minimize Loop Inductance With Proper Layer Assignment  
The placement of power and ground planes in the PCB stackup (determined by layer assignment) has a  
significant impact on the parasitic inductances of power current path as shown in Figure 8-1. For this  
reason, it is recommended to consider layer order in the early stages of the PCB PDN design cycle,  
putting high-priority supplies in the top half of the stackup (assuming high load and priority components  
are mounted on the top-side of PCB) and low-priority supplies in the bottom half of the stackup as shown  
in the examples below (vias have parasitic inductances which impact the bottom layers more, so it is  
advised to put the sensitive and high-priority power supplies on the top/same layers).  
8.2.2 Step 2: Physical Placement  
A critical step in designing an optimized PDN is that proper care must be taken to making sure that the  
initial floor planning of the PCB layout is done with good power integrity design guidelines in mind. The  
following points are important for optimizing a PCB’s PDN:  
Minimizing the physical distance between power sources and key high load components is the first  
step toward optimization. Placing source and load components on the same side of the PCB is  
desirable. This will minimize via inductance impact for high current loads and steps  
External trace routing between components must be as wide as possible. The wider the traces, the  
lower the DC resistance and consequently the lower the static IR drop.  
Whenever possible for the internal layers (routing and plane), wide traces and copper area fills are  
preferred for PDN layout. The routing of power nets in plane provide for more interplane capacitance  
and improved high frequency performance of the PDN.  
Whenever possible, use a via to component pin/pad ratio of 1:1 or better (i.e. especially decoupling  
capacitors, power inductors and current sensing resistors). Do not share vias among multiple  
capacitors for connecting power supply and ground planes.  
Placement of vias must be as close as possible or even within a component’s solder pad if the PCB  
technology you are using provides this capability.  
To avoid any "ampacity” issue – maximum current-carrying capacity of each transitional via should be  
evaluated to determine the appropriate number of vias required to connect components.  
Adding vias to bring the "via-to-pad” ratio to 1:1 will improve PDN performance.  
For noise sensitive power supplies (i.e. Phase Lock-Loops, analog signals like audio and video), a Gnd  
shield can be used to isolate coplanar supplies that may have high step currents or high frequency  
switching transitions from coupling into low-noise supplies.  
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vdd_mpu  
vss  
vdd  
SPRS91v_PCB_PHYS_05  
Figure 8-2. Coplanar Shielding of Power Net Using Ground Guard-band  
8.2.3 Step 3: Static Analysis  
Delivering reliable power to circuits is always of critical importance because voltage drops (also known as  
IR drops) can happen at every level within an electronic system, on-chip, within a package, and across the  
board. Robust system performance can only be ensured by understanding how the system elements will  
perform under typical stressful Use Cases. Therefore, it is a good practice to perform a Static or DC  
Analysis.  
Static or DC analysis and design methodology results in a PDN design that minimizes voltage or IR drops  
across power and ground planes, traces and vias. This ensures the application processor’s internal  
transistors will be operating within their specified voltage ranges for proper functionality. The amount of IR  
drop that will be encounter is based upon amount power drawn for a desired Use Case and PCB trace  
(widths, geometry and number of parallel traces) and via (size, type and number) characteristics.  
Components that are distant from their power source are particularly susceptible to IR drop. Designs that  
rely on battery power must minimize voltage drops to avoid unacceptable power loss that can negatively  
impact system performance. Early assessments a PDN’s static (DC) performance helps to determine  
basic power distribution parameters such as best system input power point, optimal PCB layer stackup,  
and copper area needed for load currents.  
The resistance Rs of a plane conductor  
for a unit length and unit width is called  
the surface resistivity (ohms per square).  
r
1
L
Rs =  
=
t
σ ×t  
l
t
R = Rs ×  
W
w
SPRS91v_PCB_STATIC_01  
Figure 8-3. Depiction of Sheet Resistivity and Resistance  
Ohm’s Law (V = I × R) relates conduction current to voltage drop. At DC, the relation coefficient is a  
constant and represents the resistance of the conductor. Even current carrying conductors will dissipate  
power at high currents even though their resistance may be very small. Both voltage drop and power  
dissipation are proportional to the resistance of the conductor.  
Figure 8-4 shows a PCB-level static IR drop budget defined between the power management device  
(PMIC) pins and the application processor’s balls when the PMIC is supplying power.  
It is highly recommended to physically place the PMIC as close as possible to the processor and on  
the same side. The orientation of the PMIC vs. the processor should be aligned to minimize distance  
for the highest current rail.  
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The resistance Rs of a plane conductor  
for a unit length and unit width is called  
the surface resistivity (ohms per square).  
r
1
L
Rs =  
=
t
σ ×t  
l
t
R = Rs ×  
W
w
SPRS91v_PCB_STATIC_01  
Figure 8-4. Static IR Drop Budget for PCB Only  
The system-level IR drop budget is made up of three portions: on-chip, package, and PCB board. Static IR  
or dc analysis/design methodology consists of designing the PDN such that the voltage drop (under dc  
operating conditions) across power and ground pads of the transistors of the application processor device  
is within a specified value of the nominal voltage for proper functionality of the device.  
A PCB system-level voltage drop budget for proper device functionality is typically 1.5% of nominal  
voltage. For a 1.35-V supply, this would be 20 mV.  
To accurately analyze PCB static IR drop, the actual geometry of the PDN must be modeled properly and  
simulated to accurately characterize long distribution paths, copper weight impacts, electro-migration  
violations of current-carrying vias, and "Swiss-cheese” effects via placement has on power rails. It is  
recommended to perform the following analyses:  
Lumped resistance/IR drop analysis  
Distributed resistance/IR drop analysis  
NOTE  
The PMIC companion device supporting Processor has been designed with voltage sensing  
feedback loop capabilities that enable a remote sense of the SMPS output voltage at the  
point of use.  
The NOTE above means the SMPS feedback signals and returns must be routed across PCB and  
connected to the Device input power ball for which a particular SMPS is supplying power. This feedback  
loop provides compensation for some of the voltage drop encountered across the PDN within limits. As  
such, the effective resistance of the PDN within this loop should be determined in order to optimize  
voltage compensation loop performance. The resistance of two PDN segments are of interest: one from  
the power inductor/bulk power filtering capacitor node to the Processor’s input power and second is the  
entire PDN route from SMPS output pin/ball to the Processor input power.  
In the following sections each methodology is described in detail and an example has been provided of  
analysis flow that can be used by the PCB designer to validate compliance to the requirements on their  
PCB PDN design.  
8.2.3.1 PDN Resistance and IR Drop  
Lumped methodology consists of grouping all of the power pins on both the PMIC (voltage source) and  
processor (current sink) devices. Then the PMIC source is set to an expected Use Case voltage level and  
the processor load has its Use Case current sink value set as well. Now the lumped/effective resistance  
for the power rail trace/plane routes can be determine based upon the actual layout’s power rail etch wide,  
shape, length, via count and placement Figure 8-5 illustrates the pin-grouping/lumped concept.  
The lumped methodology consists of importing the PCB layout database (from Cadence Allegro tool or  
any other layout design tool) into the static IR drop modeling and simulation tool of preference for the PCB  
designer. This is followed by applying the correct PCB stack-up information (thickness, material  
properties) of the PCB dielectric and metallization layers. The material properties of dielectric consist of  
permittivity (Dk) and loss tangent (Df).  
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For the conductor layers, the correct conductivity needs to be programmed into the simulation tool. This is  
followed by pin-grouping of the power and ground nets, and applying appropriate voltage/current sources.  
The current and voltage information can be obtained from the power and voltage specifications of the  
device under different operating conditions / Use Cases.  
Sources  
Sources  
Multiport net  
Branch  
Grouped Power/Ground  
pins to create 1 equivalent  
resistive branch  
Port/Pin  
Sinks  
Sinks  
SPRS91v_PCB_PDN_01  
Figure 8-5. Pin-grouping concept: Lumped and Distributed Methodologies  
8.2.4 Step 4: Frequency Analysis  
Delivering low noise voltage sources are very important to allowing a system to operate at the lowest  
possible Operational Performance Point (OPP) for any one Use Case. An OPP is a combination of the  
supply voltage level and clocking rate for key internal processor domains. A SCH and PCB designed to  
provide low noise voltage supplies will then enable the processor to enter optimal OPPs for each Use  
Case that in turn will minimize power dissipation and junction temperatures on-die. Therefore, it is a good  
engineering practice to perform a Frequency Analysis over the key power domains.  
Frequency analysis and design methodology results in a PDN design that minimizes transient noise  
voltages at the processor’s input power balls. This allows the processor’s internal transistors to operate  
near the minimum specified operating supply voltage levels. To accomplish this one must evaluate how a  
voltage supply will change due to impedance variations over frequency. This analysis will focus on the  
decoupling capacitor network (VDD_xxx and VSS/Gnd rails) at the load. Sufficient capacitance with a  
distribution of self-resonant points will provide for an overall lower impedance vs frequency response for  
each power domain.  
Decoupling components that are distant from their load’s input power are susceptible to encountering  
spreading loop inductance from the PCB design. Early analysis of each key power domain’s frequency  
response helps to determine basic decoupling capacitor placement, optimal footprint, layer assignment,  
and types needed for minimizing supply voltage noise/fluctuations due to switching and load current  
transients.  
NOTE  
Evaluation of loop inductance values for decoupling capacitors placed ~300mils closer to the  
load’s input power balls has shown an 18% reduction in loop inductance due to reduced  
distance.  
Decoupling capacitors must be carefully placed in order to minimize loop inductance impact on supply  
voltage transients. A real capacitor has characteristics not only of capacitance but also inductance and  
resistance.  
Figure 8-6 shows the parasitic model of a real capacitor. A real capacitor must be treated as an RLC  
circuit with effective series resistance (ESR) and effective series inductance (ESL).  
C
ESL  
ESR  
SPRS91v_PCB_FREQ_01  
Figure 8-6. Characteristics of a Real Capacitor With ESL and ESR  
The magnitude of the impedance of this series model is given as:  
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1
æ
ö2
2
Z = ESR +
ωESL -  
ç
÷
ωC  
è
ø
where : w = ¦  
SPRS91v_PCB_FREQ_02  
Figure 8-7. Series Model Impedance Equation  
Figure 8-8 shows the resonant frequency response of a typical capacitor with a self-resonant frequency of  
55 MHz. The impedance of the capacitor is a combination of its series resistance and reactive capacitance  
and inductance as shown in the equation above.  
S-Parameter Magnitude  
Job: GCM155R71E153KA55_15NF;  
1.0e+01  
1.0e+00  
1.0e–01  
1.0e–02  
XC=1/ωC  
XL=ωL  
1.0e–03  
Resonant frequency  
(55 MHz) (minimum)  
1.0e–04  
1.00e–002  
1.00e+000  
1.00e+002  
1.00e+004  
1.00e+006  
1.00e+008  
Frequency (MHz)  
SPRS91v_PCB_FREQ_03  
Figure 8-8. Typical Impedance Profile of a Capacitor  
Because a capacitor has series inductance and resistance that impacts its effectiveness, it is important  
that the following recommendations are adopted in placing capacitors on the PDN.  
Wherever possible, mount the capacitor with the geometry that minimizes the mounting inductance and  
resistance. This was shown earlier in Figure 8-1. The capacitor mounting inductance and resistance  
values include the inductance and resistance of the pads, trace, and vias. Whenever possible, use  
footprints that have the lowest inductance configuration as shown in Figure 8-9  
The length of a trace used to connect a capacitor has a big impact on parasitic inductance and resistance  
of the mounting. This trace must be as short and as wide as possible. wherever possible, minimize  
distance to supply and Gnd vias by locating vias nearby or within the capacitor’s solder pad landing.  
Further improvements can be made to the mounting by placing vias to the side of capacitor lands or  
doubling the number of vias as shown in Figure 8-9. If the PCB manufacturing processes allow it and if  
cost-effective, via-in-pad (VIP) geometries are strongly recommended.  
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In addition to mounting inductance and resistance associated with placing a capacitor on the PCB, the  
effectiveness of a decoupling capacitor also depends on the spreading inductance and resistance that the  
capacitor sees with respect to the load. The spreading inductance and resistance is strongly dependent on  
the layer assignment in the PCB stack-up. Therefore, try to minimize X, Y and Z dimensions where the Z  
is due to PCB thickness (as shown in Figure 8-9).  
From left (highest inductance) to right (lowest inductance) the capacitor footprint types shown in Figure 8-  
9 are known as:  
2-via, Skinny End Exit (2vSEE)  
2-via, Wide End Exit (2vWEE)  
2-via, Wide Side Exit (2vWSE)  
4-via, Wide Side Exit (4vWSE)  
2-via, In-Pad (2vIP)  
Via  
Via-in-pad  
Pad  
Trace  
Mounting geometry for reduced inductance  
SPRS91v_PCB_FREQ_04  
Figure 8-9. Capacitor Placement Geometry for Improved Mounting Inductance  
NOTE  
Evaluation of loop inductance values for decoupling capacitor footprints 2vSEE (worst case)  
vs 4vWSE (2nd best) has shown a 30% reduction in inductance when 4vWSE footprint was  
used in place of 2vSEE.  
Decoupling Capacitor (Dcap) Strategy:  
1. Use lowest inductance footprint and trace connection scheme possible for given PCB technology and  
layout area in order to minimize Dcap loop inductance to power pin as much as possible (see Figure 8-  
9).  
2. Place Dcaps on "same-side” as component within their power plane outline to minimize "decoupling  
loop inductance”. Target distance to power pin should be less than ~500mils depending upon PCB  
layout characteristics (plane's layer assignment and solid nature). Use PI modeling CAD tool to verify  
minimum inductance for top vs bottom-side placement.  
3. Place Dcaps on "opposite-side” as component within their power plane outline if "same-side” is not  
feasible or if distance to power pin is greater than ~500mils for top-side location. Use PI modeling CAD  
tool to verify minimum inductance for top vs bottom-side placement.  
4. Use minimum 10mil trace width for all voltage and gnd planes connections (i.e. Dcap pads, component  
power pins, etc.).  
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5. Place all voltage and gnd plane vias "as close as possible” to point of use (i.e. Dcap pads, component  
power pins, etc.).  
6. Use a "Power/Gnd pad/pin to via” ratio of 1:1 whenever possible. Do not exceed 2:1 ratio for small  
number of vias within restricted PCB areas (i.e. underneath BGA components).  
Frequency analysis for the CORE power domain (vdd) has yielded the Impedance vs Frequency  
responses shown in Section 8.3.8.2, vdd Example Analysis.  
8.2.5 System ESD Generic Guidelines  
8.2.5.1 System ESD Generic PCB Guideline  
Protection devices must be placed close to the ESD source which means close to the connector. This  
allows the device to subtract the energy associated with an ESD strike before it reaches the internal  
circuitry of the application board.  
To help minimize the residual voltage pulse that will be built-up at the protection device due to its nonzero  
turn-on impedance, it is mandatory to route the ESD device with minimum stub length so that the low-  
resistive, low-inductive path from the signal to the ground is granted and not increasing the impedance  
between signal and ground.  
For ESD protection array being railed to a power supply when no decoupling capacitor is available in close  
vicinity, consider using a decoupling capacitor (0.1 µF) tight to the VCC pin of the ESD protection. A  
positive strike will be partially diverted to this capacitance resulting in a lower residual voltage pulse.  
Ensure that there is sufficient metallization for the supply of signals at the interconnect side (VCC and  
GND in Figure 8-10) from connector to external protection because the interconnect may see between 15-  
A to 30-A current in a short period of time during the ESD event.  
Bypass  
capacitor  
0.1 mf  
(minimum)  
Stub  
inductance  
Stub  
Interconnection  
inductance  
inductance  
vcc  
Signal  
VCC  
VCC  
Protected  
circuit  
Signal  
Stub  
inductance  
ESD  
strike  
Minimize such  
inductance by  
optimizing layout  
External  
protection  
Ground  
inductance  
Keep distance  
between protected  
circuit and external  
protection  
Keep external  
protection closed by  
connector  
SPRS91v_PCB_ESD_01  
Figure 8-10. Placement Recommendation for an ESD External Protection  
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NOTE  
To ensure normal behavior of the ESD protection (unwanted leakage), it is better to ground  
the ESD protection to the board ground rather than any local ground (example isolated shield  
or audio ground).  
8.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity  
Avoid running critical signal traces (clocks, resets, interrupts, control signals, and so forth) near PCB  
edges.  
Add high frequency filtering: Decoupling capacitors close to the receivers rather than close to the  
drivers to minimize ESD coupling.  
Put a ground (guard) ring around the entire periphery of the PCB to act as a lightning rod.  
Connect the guard ring to the PCB ground plane to provide a low impedance path for ESD-coupled  
current on the ring.  
Fill unused portions of the PCB with ground plane.  
Minimize circuit loops between power and ground by using multilayer PCB with dedicated power and  
ground planes.  
Shield long line length (strip lines) to minimize radiated ESD.  
Avoid running traces over split ground planes. It is better to use a bridge connecting the two planes in  
one area.  
BAD  
BETTER  
SPRS91v_PCB_EMC_01  
Figure 8-11. Trace Examples  
Always route signal traces and their associated ground returns as close to one another as possible to  
minimize the loop area enclosed by current flow:  
At high frequencies current follows the path of least inductance.  
At low frequencies current flows through the path of least resistance.  
8.2.5.3 ESD Protection System Design Consideration  
ESD protection system design consideration is covered in of this document. The following are additional  
considerations for ESD protection in a system.  
Metallic shielding for both ESD and EMI  
Chassis GND isolation from the board GND  
Air gap designed on board to absorb ESD energy  
Clamping diodes to absorb ESD energy  
Capacitors to divert ESD energy  
The use of external ESD components on the DP/DM lines may affect signal quality and are not  
recommended.  
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8.2.6 EMI / EMC Issues Prevention  
All high speed digital integrated circuits can be sources of unwanted radiation, which can affect nearby  
sensitive circuitry and cause the final product to have radiated emissions levels above the limits allowed  
by the EMC regulations if some preventative steps are not taken.  
Likewise, analog and digital circuits can be susceptible to interference from the outside world and picked  
up by the circuitry interconnections.  
To minimize the potential for EMI/EMC issues, the following guidelines are recommended to be followed.  
8.2.6.1 Signal Bandwidth  
To evaluate the frequency of a digital signal, an estimated rule of thumb is to consider its bandwidth fBW  
with respect to its rise time, tR:  
fBW 0.35 / tR  
This frequency actually corresponds to the break point in the signal spectrum, where the harmonics start  
to decay at 40 dB per decade instead of 20 dB per decade.  
8.2.6.2 Signal Routing  
8.2.6.2.1 Signal Routing-Sensitive Signals and Shielding  
Keep radio frequency (RF) sensitive circuitry (like GPS receivers, GSM/WCDMA, Bluetooth/WLAN  
transceivers, frequency modulation (FM) radio) away from high speed ICs (the device, power and audio  
manager, chargers, memories, and so forth) and ideally on the opposite side of the PCB. For improved  
protection it is recommended to place these emission sources in a shield can. If the shield can have a  
removable lid (two-piece shield), ensure there is low contact impedance between the fence and the lid.  
Leave some space between the lid and the components under it to limit the high-frequency currents  
induced in the lid. Limit the shield size to put any potential shield resonances above the frequencies of  
interest; see Figure 8-8, Typical Impedance Profile of a Capacitor.  
8.2.6.2.2 Signal Routing-Outer Layer Routing  
In case there is a need to use the outer layers for routing outside of shielded areas, it is recommended to  
route only static signals and ensure that these static signals do not carry any high-frequency components  
(due to parasitic coupling with other signals). In case of long traces, make provision for a bypass capacitor  
near the signal source.  
Routing of high-frequency clock signals on outer layers, even for a short distance, is discouraged,  
because their emissions energy is concentrated at the discrete harmonics and can become significant  
even with poor radiators.  
Coplanar shielding of traces on outer layers (placing ground near the sides of a track along its length) is  
effective only if the distance between the trace sides and the ground is smaller that the trace height above  
the ground reference plane. For modern multilayer PCBs this is often not possible, so coplanar shielding  
will not be effective. Do not route high-frequency traces near the periphery of the PCB, as the lack of a  
ground reference near the trace edges can increase EMI: see Section 8.2.6.3, Ground Guidelines.  
8.2.6.3 Ground Guidelines  
8.2.6.3.1 PCB Outer Layers  
Ideally the areas on the top and bottom layers of the PCB that are not enclosed by a shield should be  
filled with ground after the routing is completed and connected with an adequate number of vias to the  
ground on the inner ground planes.  
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8.2.6.3.2 Metallic Frames  
Ensure that all metallic parts are well connected to the PCB ground (like LCD screens metallic frames,  
antennas reference planes, connector cages, flex cables grounds, and so forth). If using flex PCB ribbon  
cables to bring high-frequency signals off the PCB, ensure they are adequately shielded (coaxial cables or  
flex ribbons with a solid reference ground).  
8.2.6.3.3 Connectors  
For high-frequency signals going to connectors choose a fully shielded connector, if possible (for example,  
SD card connectors). For signals going to external connectors or which are routed over long distances, it  
is recommended to reduce their bandwidth by using low-pass filters (resistor, capacitor (RC) combinations  
or lossy ferrite inductors). These filters will help to prevent emissions from the board and can also improve  
the immunity from external disturbances.  
8.2.6.3.4 Guard Ring on PCB Edges  
The major advantage of a multilayer PCB with ground-plane is the ground return path below each and  
every signal or power trace.  
As shown in Figure 8-12 the field lines of the signal return to PCB ground as long as an infinite ground is  
available.  
Traces near the PCB-edges do not have this infinite ground and therefore may radiate more than the  
others. Thus, signals (clocks) or power traces (core power) identified to be critical must not be routed in  
the vicinity of PCB edges, or, if not avoidable, must be accompanied by a guard ring on the PCB edge.  
SPRS91v_PCB_EMC_02  
Figure 8-12. Field Lines of a Signal Above Ground  
Signal  
Power  
Ground  
Signal  
SPRS91v_PCB_EMC_03  
Figure 8-13. Guard Ring Routing  
The intention of the guard ring is that HF-energy, that otherwise would have been emitted from the PCB  
edge, is reflected back into the board where it partially will be absorbed. For this purpose ground traces on  
the borders of all layers (including power layer) must be applied as shown in Figure 8-13.  
As these traces must have the same (HF–) potential as the ground plane they must be connected to the  
ground plane at least every 10 mm.  
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8.2.6.3.5 Analog and Digital Ground  
For the optimum solution, the AGND and the DGND planes must be connected together at the power  
supply source in a same point. This ensures that both planes are at the same potential, while the transfer  
of noise from the digital to the analog domain is minimized.  
8.3 Core Power Domains  
This section provides boundary conditions and theoretical background to be applied as a guide for  
optimizing a PCB design. The decoupling capacitor and PDN characteristics tables shown below give  
recommended capacitors and PCB parameters to be followed for schematic and PCB designs. Board  
designs that meet the static and dynamic PDN characteristics shown in tables below will be aligned to the  
expected PDN performance needed to optimize SoC performance.  
8.3.1 General Constraints and Theory  
Max PCB static/DC voltage drop (IRd) budget of 1.5% of supply voltage when using PMICs without  
remote sensing as measured from PMIC’s power inductor and filter capacitor node to Processor input  
including any ground return losses.  
Max PCB static/DC voltage drop (IRd) budget can be relaxed to 7.5% of supply voltage when using  
TI recommended PMICs with remote sensing at the load as measured from PMIC’s power inductor  
and filter capacitor node to Device’s supply input including any ground return losses.  
PMIC component DM and guidelines should be referenced for the following:  
Routing remote feedback sensing to optimize per each SMPS’s implementation  
Selecting power filtering capacitor values and PCB placement.  
Max Total Effective Resistance (Reff) budget can range from 4 – 100 mfor key Device power rails not  
including ground returns depending upon maximum load currents and maximum DC voltage drop  
budget (as discussed above).  
Max Device supply input voltage difference budget of 5 mV under max current loading shall be  
maintained across all balls connected to a common power rail. This represents any voltage difference  
that may exist between a remote sense point to any power input.  
Max PCB Loop Inductance (LL) budget between Device’s power inputs and local bulk and high  
frequency decoupling capacitors including ground returns should range from 0.4 – 2.5 nH depending  
upon maximum transient load currents.  
Max PCB dynamic/AC peak-to-peak transient noise voltage budgets between PMIC and Device  
including ground returns are as follows:  
+/-3% of nominal supply voltage for frequencies below the PMIC bandwidth (typ Fpmic ~  
200kHz)  
+/-5% of nominal supply voltage for frequencies between Fpmic to Fpcb (typ 20 – 100MHz)  
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Max PCB Impedance (Z) vs Frequency (F) budget between Device’s power inputs and PMIC’s output  
power filter node including ground return is determined by applying the Frequency Domain Target  
Impedance Method to determine the PCB’s maximum frequency of interest (Fpcb). Ideally a properly  
designed and decoupled PDN will exhibit smoothly increasing Z vs. F curve. There are 2 general  
regions of interest as can be seen in Figure 8-14.  
1st area is from DC (0Hz) up to Fpmic (typ a few 100 kHz) where a PMIC’s transient response  
characteristic (i.e. Switching Freq, Compensation Loop BW) dominate. A PDN’s Z is typically very  
low due to power filtering and bulk capacitor values when PDN has very low trace resistance (i.e.  
good Reff performance). The goal is to maintain a smoothly increasing Z that is less than Zt1 over  
this low frequency range. This will ensure that a max transient current event will not cause a  
voltage drop more than the PMIC’s current step response can support (typ 3%).  
2nd area is from Fpmic up to Fpcb (typ 20-100MHz) where a PCB’s inherent characteristics (i.e.  
parasitic capacitance, planar spreading inductances) dominate. A PDN’s Z will naturally increase  
with frequency. At frequencies between Fpmic up to Fpcb, the goal is to maintain a smoothly  
increasing Z to be less than Zt2. This will ensue that the high frequency content of a max transient  
current event will not cause a voltage drop to be more than 5% of the min supply voltage.  
Figure 8-14. PDN’s Target impedance  
1.Voltage Rail Drop includes regulation accuracy, voltage distribution drops, and all dynamic events  
such as transient noise, AC ripple, voltage dips etc.  
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2.Typical max transient current is defined as 50% of max current draw possible.  
8.3.2 Voltage Decoupling  
Recommended power supply decoupling capacitors main characteristics for commercial products whose  
ambient temperature is not to exceed +85C are shown in table below:  
Table 8-1. Commercial Applications Recommended Decoupling Capacitors Characteristics(1)(2)(3)  
VALUE  
VOLTAGE PACKAGE  
[V]  
STABILITY  
DIELECTR CAPACIT  
TEMP  
TEMP  
REFERENCE  
IC  
ANCE  
TOLERAN  
CE  
RANGE [°C] SENSITIVI  
TY [%]  
22 µF  
10 µF  
4.7 µF  
2.2 µF  
1 µF  
6,3  
4,0  
6,3  
6,3  
6,3  
6,3  
6,3  
6,3  
0603  
0402  
0402  
0402  
0201  
0201  
0201  
0201  
Class 2  
Class 2  
Class 2  
Class 2  
Class 2  
Class 2  
Class 2  
Class 2  
X5R  
X5R  
X5R  
X5R  
X5R  
X5R  
X5R  
X5R  
- / + 20%  
- / + 20%  
- / + 20%  
- / + 20%  
- / + 20%  
- / + 20%  
- / + 20%  
- / + 20%  
-55 to + 85  
-55 to + 85  
-55 to + 85  
-55 to + 85  
-55 to + 85  
-55 to + 85  
-55 to + 85  
-55 to + 85  
- / + 15  
- / + 15  
- / + 15  
- / + 15  
- / + 15  
- / + 15  
- / + 15  
- / + 15  
GRM188R60J226MEA0L  
GRM155R60G106ME44  
GRM155R60J475ME95  
GRM155R60J225ME95  
GRM033R60J105MEA2  
GRM033R60G474ME90  
GRM033R60J224ME90  
GRM033R60J104ME19  
470 nF  
220 nF  
100 nF  
(1) Minimum value for each PCB capacitor: 100 nF.  
(2) Among the different capacitors, 470 nF is recommended (not required) to filter at 5-MHz to 10-MHz frequency range.  
(3) In comparison with the EIA Class 1 dielectrics, Class 2 dielectric capacitors tend to have severe temperature drift, high dependence of  
capacitance on applied voltage, high voltage coefficient of dissipation factor, high frequency coefficient of dissipation, and problems with  
aging due to gradual change of crystal structure. Aging causes gradual exponential loss of capacitance and decrease of dissipation  
factor.  
Recommended power supply decoupling capacitors main characteristics for automotive products are  
shown in table below:  
Table 8-2. Automotive Applications Recommended Decoupling Capacitors Characteristics (1)(2)  
VALUE  
VOLTAGE PACKAGE  
[V]  
STABILITY  
DIELECTRI CAPACITA  
TEMP  
RANGE  
[°C]  
TEMP  
SENSITIVIT  
Y [%]  
REFERENCE  
C
NCE  
TOLERAN  
CE  
22 µF  
10 µF  
4.7 µF  
2.2 µF  
1 µF  
6,3  
6,3  
10  
6,3  
16  
16  
25  
16  
1206  
0805  
0805  
0603  
0603  
0603  
0603  
0402  
Class 2  
Class 2  
Class 2  
Class 2  
Class 2  
Class 2  
Class 2  
Class 2  
X7R  
X7R  
X7R  
X7R  
X7R  
X7R  
X7R  
X7R  
- / + 20% -55 to + 125  
- / + 20% -55 to + 125  
- / + 20% -55 to + 125  
- / + 20% -55 to + 125  
- / + 20% -55 to + 125  
- / + 20% -55 to + 125  
- / + 20% -55 to + 125  
- / + 20% -55 to + 125  
- / + 15  
- / + 15  
- / + 15  
- / + 15  
- / + 15  
- / + 15  
- / + 15  
- / + 15  
GCM31CR70J226ME23  
GCM21BR70J106ME22  
GCM21BC71A475MA73  
GCM188R70J225ME22  
GCM188R71C105MA64  
GCM188R71C474MA55  
GCM188L81C224MA37  
GCM155R71C104MA55  
470 nF  
220 nF  
100 nF  
(1) Minimum value for each PCB capacitor: 100 nF.  
(2) Among the different capacitors, 470 nF is recommended (not required) to filter at 5-MHz to 10-MHz frequency range.  
8.3.3 Static PDN Analysis  
One power net parameter derived from a PCB’s PDN static analysis is the Effective Resistance (Reff).  
This is the total PCB power net routing resistance that is the sum of all the individual power net segments  
used to deliver a supply voltage to the point of load and includes any series resistive elements (i.e. current  
sensing resistor) that may be installed between the PMIC outputs and Processor inputs.  
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8.3.4 Dynamic PDN Analysis  
Three power net parameters derived from a PCB’s PDN dynamic analysis are the Loop Inductance (LL),  
Impedance (Z) and PCB Frequency of Interest (Fpcb).  
LL values shown are the recommended max PCB trace inductance between a decoupling capacitor’s  
power supply and ground reference terminals when viewed from the decoupling capacitor with a  
"theoretical shorted” applied across the Processor’s supply inputs to ground reference.  
Z values shown are the recommended max PCB trace impedances allowed between Fpmic up to Fpcb  
frequency range that limits transient noise drops to no more than 5% of min supply voltage during max  
transient current events.  
Fpcb (Frequency of Interest) is defined to be a power rail’s max frequency after which adding a  
reasonable number of decoupling capacitors no longer significantly reduces the power rail impedance  
below the desired impedance target (Zt2). This is due to the dominance of the PCB’s parasitic planar  
spreading and internal package inductances.  
Table 8-3. Recommended PDN and Decoupling Characteristics (1)(2)(3)(4)(5)  
PDN ANALYSIS: STATIC  
DYNAMIC  
NUMBER OF RECOMMENDED DECOUPLING CAPACITORS  
PER SUPPLY  
Supply  
Frequency  
range  
of Interest  
[MHz]  
Max Reff  
Dec. Cap.  
Max  
100  
220  
nF  
470  
nF  
Max LL(8) (6) Impedance  
1μF 2.2 μF 4.7 μF 10 μF 22 μF  
(7)  
nF(6)  
[mΩ]  
[nH]  
[mΩ]  
vdd_dspeve  
vdd  
33  
83  
2.5  
2
54  
87  
20  
50  
6
6
1
1
1
1
1
1
1
1
1
1
1
1
vdds_ddr1,  
vdds_ddr2,  
vdds_ddr3  
33  
2.5  
200  
100  
8
4
2
2
cap_vddram_cor  
e1  
N/A  
N/A  
N/A  
6
6
6
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
1
1
1
cap_vddram_cor  
e2  
cap_vddram_dsp  
eve  
(1) For more information on peak-to-peak noise values, see the Recommended Operating Conditions table of the Electrical Characteristics  
chapter.  
(2) ESL must be as low as possible and must not exceed 0.5 nH.  
(3) The PDN (Power Delivery Network) impedance characteristics are defined versus the device activity (that runs at different frequency)  
based on the Recommended Operating Conditions table of the Electrical Characteristics chapter.  
(4) The static drop requirement drives the maximum acceptable PCB resistance between the PMIC or the external SMPS and the processor  
power balls.  
(5) Assuming that the external SMPS (power IC) feedback sense is taken close to processor power balls.  
(6) High-frequency (30 to 70MHz) PCB decoupling capacitors  
(7) Maximum Total Reff from PMIC output to remote sensing feedback point located as close to the Device's point of load as possible.  
(8) Maximum Loop Inductance for decoupling capacitor.  
8.3.5 Power Supply Mapping  
TPS65917 is a Power management IC (PMIC) that can be used for the Device design. TI is now  
investigating an optimized solution for high power use cases so the TPS65917 is subject to change. An  
alternate dual converter power solution using LP8732Q and LP8733Q are recommended. TI requires the  
use of one of these PMIC solutions for the following reasons:  
TI has validated its use with the Device  
Board level margins including transient response and output accuracy are analyzed and optimized for  
the entire system  
Support for power sequencing requirements (refer to Section 5.10 Power Sequencing)  
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Support for Adaptive Voltage Scaling (AVS) Class 0 requirements, including TI provided software  
It is possible that some voltage domains on the device are unused in some systems. In such cases, to  
ensure device reliability, it is still required that the supply pins for the specific voltage domains are  
connected to some core power supply output.  
These unused supplies though can be combined with any of the core supplies that are used (active) in the  
system. e.g. if IVA and GPU domains are not used, they can be combined with the CORE domain,  
thereby having a single power supply driving the combined CORE, IVA and GPU domains.  
For the combined rail, the following relaxations do apply:  
The AVS voltage of active rail in the combined rail needs to be used to set the power supply  
The decoupling capacitance should be set according to the active rail in the combined rail  
Whenever we allow for combining of rails mapped on any of the SMPSes, the PDN guidelines that are the  
most stringent of the rails combined should be implemented for the particular supply rail.  
Table 8-4 illustrates the approved and validated power supply connections to the Device for the SMPS  
outputs of the TPS65917 and LP8732 combined with LP8733 PMICs.  
Table 8-4. Power Supply Connections  
TPS65917  
DUAL CONVERTER  
SOLUTION  
VALID COMBINATION 1:  
SMPS1  
SMPS2  
SMPS3  
SMPS4  
LP8733Q Buck0  
LP8733Q Buck1  
LP8732Q Buck0  
LP8732Q Buck1  
vdd_dspeve  
vdd  
vdds18v, vdds18v_ddr[3:1], vddshv[6:1]  
vdds_ddr1, vdds_ddr2, vdds_ddr3  
Table 8-5 illustrates the LP8733 and LP8732 OTP IDs required for TDA3 processor systems using  
different DDR memory types.  
Table 8-5. OTP ID Memory Types Support  
DDR Type  
LP8733Q  
LP8732Q  
OTP VERSION  
OTP VERSION  
DDR2  
LPDDR2  
DDR3  
2A  
2A  
2A  
2A  
2D  
2B  
2F  
2E  
DDR3L  
8.3.6 DPLL Voltage Requirement  
The voltage input to the DPLLs has a low noise requirement. Board designs should supply these voltage  
inputs with a low noise LDO to ensure they are isolated from any potential digital switching noise. The  
TPS65917 PMIC LDOLN output or LDO0 on LP8733Q dual power solution is specifically designed to  
meet this low noise requirement.  
NOTE  
For more information about Input Voltage Sources, see DPLLs, DLLs Specifications  
Table 8-6 presents the voltage inputs that supply the DPLLs.  
Table 8-6. Input Voltage Power Supplies for the DPLLs  
POWER SUPPLY  
DPLLs  
vdda_per  
DPLL_PER and PER HSDIVIDER analog power supply  
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Table 8-6. Input Voltage Power Supplies for the DPLLs (continued)  
POWER SUPPLY  
vdda_ddr_dsp  
DPLLs  
DPLL_EVE_VID_DSP, DPLL_DDR and DDR HSDIVIDER analog power supply  
vdda_gmac_core  
GMAC PLL, GMAC HSDIVIDER, DPLL_CORE and CORE HSDIVIDER analog power  
supply  
8.3.7 Loss of Input Power Event  
A few key PDN design items needed to enable a controlled and compliant SoC power down sequence for  
a “Loss of Input Power” event are:  
“Loss of Input Power” early warning  
TI EVM and Reference Design Study SCHs and PDNs achieve this by using the 1st Stage  
Converter’s (i.e. LM536033-Q1) Power Good status output to enable and disable the 2nd Stage  
PMIC devices (i.e. TPS65917/919, LP8733, and LP8732). If a different 1st Stage Converter is used,  
care must be taken to ensure an adequate “PG_Status” or “Vbatt_Status” signal is provided that  
can disable 2nd Stage PMIC to begin a controlled and compliant SoC power down sequence. The  
total elapsed time from asserting “PG_Status” low until SoC’s PMIC input voltage reaches minimum  
level of 2.75 V should be minimum of 1.5 ms and 2 ms preferred.  
Maximize discharge time of 1st Stage Vout (VSYS_3V3 power rail = input voltage to SoC PMIC).  
TI EVM and Reference Design Study SCHs and PDNs achieve this by opening an in-line load  
switch immediately upon “PG_Status” low assertion in order to remove the SoC’s 3.3V IO load  
current from VSYS_3V3. This will extend the VSYS_3V3 power rail’s discharge time in order to  
maximize elapsed time for allowing SoC PMIC to execute a controlled and compliant power down  
sequence. Care should be taken to either disable or isolate any additional peripheral components  
that may be loading the VSYS_3V3 rail as well.  
Sufficient bulk decoupling capacitance on the 1st Stage Vout (VSYS_3V3 per PDN) that allows for  
desired 1.5 – 2 ms elapsed time as described above.  
TI EVM and Reference Design Study SCHs and PDNs achieve this by using 200µF of total  
capacitance on VSYS_3V3. The 1st Stage Converter (i.e. LM536033-Q1) can typically drive a max  
of 400 µF to help extend VSYS_3V3 discharge time for a compliant SoC power down sequence.  
Optimizing the 2nd Stage SoC PMIC’s OTP settings that determines SoC power up and down  
sequences and total elapsed time needed for a controlled sequence.  
TI EVM and Reference Design Study SCHs and PDNs achieve this by using optimized OTPs per  
the SCH and components used. The definition of these OTPs is captured in the detailed timing  
diagrams for both power up and down sequences. The PDN diagram typically shows a  
recommended PMIC OTP ID based upon the SoC and DDR memory types.  
8.3.8 Example PCB Design  
The following sections describe an example PCB design and its resulting PDN performance for the  
vdd_dspeve key processor power domain.  
NOTE  
Materials presented in this section are based on generic PDN analysis on PCB boards and  
are not specific to systems integrating the Device.  
8.3.8.1 Example Stack-up  
Layer Assignments:  
Layer Top: Signal and Segmented Power Plane  
Processor and PMIC components placed on Top-side  
Layer 2: Gnd Plane1  
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Layer 3: Signals  
Layer n: Power Plane1  
Layer n+1: Power Plane 2  
Layer n+2: Signal  
Layer n+3: Gnd Plane2  
Layer Bottom: Signal and Segmented Power Planes  
Decoupling caps, etc.  
Via Technology: Through-hole  
Copper Weight:  
½ oz for all signal layers.  
1-2oz for all power plane for improved PCB heat spreading  
8.3.8.2 vdd_dspeve Example Analysis  
Maximum acceptable PCB resistance (Reff) between the PMIC and Processor input power balls should not  
exceed 33mΩ per Table 8-3 and (7).  
Maximum decoupling capacitance loop inductance (LL) between Processor input power balls and  
decoupling capacitances should not exceed 2.5nH per Table 8-3 and (7) (ESL NOT included).  
Impedance target for key frequency of interest between Processor input power balls and PMIC’s SMPS  
output power balls should not exceed 54mΩ per Table 8-3 and (7).  
Table 8-7. Example PCB vdd_dspeve PI Analysis Summary  
PARAMETER  
OPP  
RECOMMENDATION  
EXAMPLE PCB  
OPP_NOM  
500 MHz  
1 V  
Clocking Rate  
Voltage Level  
Max Current Draw  
1 V  
1 A  
1 A  
Max Effective Resistance: Power  
Inductor Segment Total Reff  
13 mΩ  
11.4mΩ  
Max Loop Inductance  
Impedance Target  
< 2.5 nH  
0.73 - 1.58 nH  
54 mΩ for F < 20 MHz  
28.8 mΩ for F < 20MHz  
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Figure 8-15 shows a PCB layout example and the resulting PI analysis results.  
Figure 8-15. vdd_dspeve Simplified SCH Diagram  
Table 8-8. DCap Scheme  
VALUE [µF]  
SIZE  
QTY  
CAPACITANCE [µF]  
Cap Type: Automotive GCM series, X7R  
22  
4.7  
2.2  
1
1206  
805  
603  
603  
603  
603  
402  
1
1
1
1
1
1
6
22  
4.7  
2.2  
1
0.47  
0.22  
0.1  
0.47  
0.22  
0.6  
TOTALS  
12  
31.19  
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IR Drop: vdd_dspeve  
Figure 8-16. vdd_dspeve Voltage/IR Drop [All Layers]  
Dynamic analysis of this PCB design for the CORE power domain determined the vdd_dspeve decoupling  
capacitor loop inductance and impedance vs frequency analysis shown below. As you can see, the loop  
inductance values ranged from 0.68 –1.79nH and were less than maximum 2.0nH recommended.  
Table 8-9. Decoupling Design Detail Summary  
CAP  
REFERENCE  
DESCRIPTION  
LOOP INDUCTANCE FOOTPRINT TYPES  
AT 50MHz [nH]  
PCB SIDE  
DISTANCE TO  
BALL-FIELD  
[mils]  
VALUE  
SIZE  
C5101  
C5100  
C5085  
C5019  
C5111  
C5030  
C5037  
C5018  
C5021  
C5026  
C5079  
C5080  
0.73  
0.78  
0.84  
1.09  
1.09  
1.11  
1.11  
1.14  
1.17  
1.18  
1.32  
1.58  
2vWEE  
2vWEE  
2vWEE  
4vWE  
4vWE  
4vWE  
4vWE  
4vWE  
4vWE  
4vWE  
4vWE  
4vWE  
Bottom  
Bottom  
Bottom  
Top  
82  
0.1  
0.1  
0.1  
0.47  
0.1  
4.7  
2.2  
1
0402  
0402  
0402  
0603  
0402  
0805  
0603  
0603  
0603  
1206  
0402  
0402  
107  
35  
631  
681  
738  
563  
681  
761  
792  
542  
602  
Bottom  
Top  
Top  
Top  
Top  
0.22  
22  
Top  
Bottom  
Bottom  
0.1  
0.1  
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Figure 8-17 shows vdd_dspeve Impedance vs Frequency characteristics.  
Figure 8-17. vdd_dspeve Impedance vs Frequency  
8.4 Single-Ended Interfaces  
8.4.1 General Routing Guidelines  
The following paragraphs detail the routing guidelines that must be observed when routing the various  
functional LVCMOS interfaces.  
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Line spacing:  
For a line width equal to W, the spacing between two lines must be 2W, at least. This minimizes the  
crosstalk between switching signals between the different lines. On the PCB, this is not achievable  
everywhere (for example, when breaking signals out from the device package), but it is  
recommended to follow this rule as much as possible. When violating this guideline, minimize the  
length of the traces running parallel to each other (see Figure 8-18).  
W
D+  
S = 2 W = 200 µm  
SPRS91v_PCB_SE_GND_01  
Figure 8-18. Ground Guard Illustration  
Length matching (unless otherwise specified):  
For bus or traces at frequencies less than 10 MHz, the trace length matching (maximum length  
difference between the longest and the shortest lines) must be less than 25 mm.  
For bus or traces at frequencies greater than 10 MHz, the trace length matching (maximum length  
difference between the longest and the shortest lines) must be less than 2.5 mm.  
Characteristic impedance  
Unless otherwise specified, the characteristic impedance for single-ended interfaces is  
recommended to be between 35-Ω and 65-Ω.  
Multiple peripheral support  
For interfaces where multiple peripherals have to be supported in the star topology, the length of  
each branch has to be balanced. Before closing the PCB design, it is highly recommended to verify  
signal integrity based on simulations including actual PCB extraction.  
8.4.2 QSPI Board Design and Layout Guidelines  
The following section details the routing guidelines that must be observed when routing the QSPI  
interfaces.  
8.4.2.1 If QSPI is operated in Mode 0 (POL=0, PHA=0):  
The qspi1_sclk output signal must be looped back into the qspi1_rtclk input.  
The signal propagation delay from the qspi1_sclk ball to the QSPI device CLK input pin (A to C) must  
be approximately equal to the signal propagation delay from the QSPI device CLK pin to the  
qspi1_rtclk ball (C to D).  
The signal propagation delay from the QSPI device CLK pin to the qspi1_rtclk ball (C to D) must be  
approximately equal to the signal propagation delay of the control and data signals between the QSPI  
device and the SoC device (E to F, or F to E).  
The signal propagation delay from the qspi1_sclk signal to the series terminators (R2 = 10 Ω) near the  
QSPI device must be < 450pS (~7cm as stripline or ~8cm as microstrip)  
50 Ω PCB routing is recommended along with series terminations, as shown in Figure 8-19.  
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Propagation delays and matching:  
A to C = C to D = E to F  
Matching skew: < 60pS  
A to B < 450pS  
B to C = as small as possible (<60pS)  
Locate both R2 resistors  
close together near the QSPI device  
A
B
C
R1  
R2  
0 Ω*  
10 Ω  
R2  
10 Ω  
qspi1_sclk  
QSPI device  
clock input  
D
qspi1_rtclk  
E
F
QSPI device  
IOx, CS#  
qspi1_d[x], qspi1_cs[y]  
SPRS906_PCB_QSPI_01  
Figure 8-19. QSPI Interface High Level Schematic Mode 0 (POL=0, PHA=0)  
NOTE  
*0 Ω resistor (R1), located as close as possible to the qspi1_sclk pin, is placeholder for fine-  
tuning if needed.  
8.4.2.2 If QSPI is operated in Mode 3 (POL=1, PHA=1):  
The qspi1_rtclk input can be left unconnected.  
The signal propagation delay from the qspi1_sclk signal to the QSPI device CLK pin (A to C) must be  
approximately equal to the signal propagation delay of the control and data signals between the QSPI  
device and the SoC device (E to F, or F to E).  
The signal propagation delay from the qspi1_sclk signal to the QSPI device CLK pin (A to C) must be  
< 450pS (~7cm as stripline or ~8cm as microstrip).  
50 Ω PCB routing is recommended along with series terminations, as shown in Figure 8-20.  
Propagation delays and matching:  
A to C = E to F.  
Matching skew: < 60Ps  
A to B < 450pS  
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A
C
R1  
0 Ω*  
qspi1_sclk  
QSPI device  
clock input  
E
F
QSPI deice  
IOx, CS#  
qspi1_d[x], qspi1_cs[y]  
SPRS91v_PCB_QSPI_01  
Figure 8-20. QSPI Interface High Level Schematic Mode 3 (POL=1, PHA=1)  
NOTE  
*0 Ω resistor (R1), located as close as possible to the qspi1_sclk pin, is placeholder for fine-  
tuning if needed.  
8.5 Differential Interfaces  
8.5.1 General Routing Guidelines  
To maximize signal integrity, proper routing techniques for differential signals are important for high speed  
designs. The following general routing guidelines describe the routing guidelines for differential lanes and  
differential signals.  
As much as possible, no other high-frequency signals must be routed in close proximity to the  
differential pair.  
Must be routed as differential traces on the same layer. The trace width and spacing must be chosen  
to yield the differential impedance value recommended.  
Minimize external components on differential lanes (like external ESD, probe points).  
Through-hole pins are not recommended.  
Differential lanes mustn’t cross image planes (ground planes).  
No sharp bend on differential lanes.  
Number of vias on the differential pairs must be minimized, and identical on each line of the differential  
pair. In case of multiple differential lanes in the same interface, all lines should have the same number  
of vias.  
Shielded routing is to be promoted as much as possible (for instance, signals must be routed on  
internal layers that are inside power and/or ground planes).  
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8.5.2 CSI2 Board Design and Routing Guidelines  
The MIPI D-PHY signals include the CSI2 camera serial interfaces to or from the Device.  
For more information regarding the MIPI-PHY signals and corresponding balls, see Table 4-10, CSI2  
Signal Descriptions.  
For more information, you can also see the MIPI D-PHY specification v1-01-00_r0-03 (specifically the  
Interconnect and Lane Configuration and Annex B Interconnect Design Guidelines chapters).  
In the next section, the PCB guidelines of the following differential interfaces are presented:  
CSI2_0 MIPI CSI-2 at 1.5 Gbps  
Table 8-10 lists the MIPI D-PHY interface signals in the Device.  
Table 8-10. MIPI D-PHY Interface Signals in the Device  
SIGNAL NAME  
csi2_0_dx0  
csi2_0_dx1  
csi2_0_dx2  
csi2_0_dx3  
csi2_0_dx4  
BALL  
A11  
A12  
A13  
A15  
A16  
SIGNAL NAME  
csi2_0_dy0  
csi2_0_dy1  
csi2_0_dy2  
csi2_0_dy3  
csi2_0_dy4  
BALL  
B11  
B12  
B13  
B15  
B16  
8.5.2.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)  
8.5.2.1.1 General Guidelines  
The general guidelines for the PCB differential lines are:  
Differential trace impedance Z0 = 100 Ω (minimum = 85 Ω, maximum = 115 Ω)  
Total conductor length from the Device package pins to the peripheral device package pins is 25 to 30  
cm with common FR4 PCB and flex materials.  
NOTE  
Longer interconnect length can be supported at the expense of detailed simulations of the  
complete link including driver and receiver models.  
The general rule of thumb for the space S = 2 × W is not designated (see Figure 8-18, Guard Illustration).  
It is because although the S = 2 × W rule is a good rule of thumb, it is not always the best solution. The  
electrical performance will be checked with the frequency-domain specification. Even though the designer  
does not follow the S = 2 × W rule, the differential lines are ok if the lines satisfy the frequency-domain  
specification.  
Because the MIPI signals are used for low-power, single-ended signaling in addition to their high speed  
differential implementation, the pairs must be loosely coupled.  
8.5.2.1.2 Length Mismatch Guidelines  
8.5.2.1.2.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)  
The guidelines of the length mismatch for CSI-2 are presented in Table 8-11.  
Table 8-11. Length Mismatch Guidelines for CSI-2 (1.5 Gbps)  
PARAMETER  
TYPICAL VALUE  
UNIT  
Mbps  
ps  
Operating speed  
UI (bit time)  
1500  
667  
(1)  
Intralane skew  
Have to satisfy mode-conversion S parameters  
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Table 8-11. Length Mismatch Guidelines for CSI-2 (1.5 Gbps) (continued)  
PARAMETER  
TYPICAL VALUE  
UNIT  
ps  
Interlane skew (UI / 50)  
13.34  
66.7  
PCB lane-to-lane skew (0.1 UI)  
ps  
(1) sdc12, scd21, scd12, sdc21, scd11, sdc11, scd22, and sdc22  
8.5.2.1.3 Frequency-domain Specification Guidelines  
After the PCB design is finished, the S-parameters of the PCB differential lines will be extracted with a 3D  
Maxwell Equation Solver such as the high-frequency structure simulator (HFSS) or equivalent, and  
compared to the frequency-domain specification as defined in the section 7 of the MIPI Alliance  
Specification for D-PHY Version v1-01-00_r0-03.  
If the PCB lines satisfy the frequency-domain specification, the design is finished. Otherwise, the design  
needs to be improved.  
8.6 Clock Routing Guidelines  
8.6.1 Oscillator Ground Connection  
Although the impedance of a ground plane is low it is, of course, not zero. Therefore, any noise current in  
the ground plane causes a voltage drop in the ground. Figure 8-21 shows the grounding scheme for slow  
(low frequency) clock generated from the internal oscillator.  
Device  
rtc_osc_xo  
Rd  
rtc_osc_xi_clkin32  
Crystal  
(Optional)  
Cf2  
Cf1  
SPRS91v_PCB_CLK_OSC_02  
Figure 8-21. Grounding Scheme for Low-Frequency Clock  
Figure 8-22 shows the grounding scheme for high-frequency clock.  
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Device  
xi_oscj  
xo_oscj  
vssa_oscj  
Rd  
(Optional)  
Crystal  
Cf2  
Cf1  
SPRS91v_PCB_CLK_OSC_03  
(1) j in *_osc = 0 or 1  
Figure 8-22. Grounding Scheme for High-Frequency Clock  
8.7 LPDDR2 Board Design and Layout Guidelines  
8.7.1 LPDDR2 Board Designs  
TI only supports board designs using LPDDR2 memory that follow the guidelines in this document. The  
switching characteristics and timing diagram for the LPDDR2 memory interface are shown in Table 8-12  
and Figure 8-23.  
Table 8-12. Switching Characteristics for LPDDR2 Memory Interface  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
1
tc(DDR_CK)  
Cycle time, ddr1_ck and ddr1_nck  
7.52  
3.00(1)  
ns  
(1) The JEDEC JESD209-2F standard defines the maximum clock period of 100 ns for all standard-speed bin LPDDR2 memory. The  
device has only been tested per the limits published in this table.  
1
ddr1_ck  
ddr1_nck  
SPRS917_LPDDR2_01  
Figure 8-23. LPDDR2 Memory Interface Clock Timing  
8.7.2 LPDDR2 Device Configurations  
There is signal device configuration supported, supporting either 32b or 16b data widths. Table 8-13 lists  
all the supported configuration.  
Table 8-13. Supported LPDDR2 Device Combinations  
NUMBER OF LPDDR2  
LPDDR2 DEVICE WIDTH (BITS)  
MIRRORED?  
LPDDR2 EMIF WIDTH (BITS)  
DEVICES  
1
32 / 16  
N
32 / 16  
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8.7.3 LPDDR2 Interface  
8.7.3.1 LPDDR2 Interface Schematic  
Figure 8-24 shows the schematic connections for 32-bit interface with or without ECC using one x32  
LPDDR2 device.  
32-Bit LPDDR2  
Interface  
32-Bit LPDDR2  
Device  
R
R
R
R
DAT  
DAT  
DAT  
DAT  
DQ[31:0]  
ddr1_d[31:0]  
ddr1_dqm[3:0]  
ddr1_dqs[3:0]  
ddr1_dqsn[3:0]  
DM[3:0]  
DQS_t[3:0]  
DQS_c[3:0]  
R
R
R
R
CA  
CA  
CA  
CA  
CK_t  
CK_c  
CKE  
ddr1_ck  
ddr1_nck  
ddr1_cke0  
ddr1_csn0  
CS_n  
ddr1_rasn (ddr1_ca0)(1)  
ddr1_casn (ddr1_ca1)(1)  
ddr1_wen (ddr1_ca2)(1)  
ddr1_a13 (ddr1_ca3)(1)  
ddr1_a10 (ddr1_ca4)(1)  
ddr1_a1 (ddr1_ca5)(1)  
ddr1_a2 (ddr1_ca6)(1)  
ddr1_ba0 (ddr1_ca7)(1)  
ddr1_ba1 (ddr1_ca8)(1)  
ddr1_ba2 (ddr1_ca9)(1)  
R
R
R
R
R
R
R
R
R
R
CA  
CA  
CA  
CA  
CA  
CA  
CA  
CA  
CA  
CA  
CA[0]  
CA[1]  
CA[2]  
CA[3]  
CA[4]  
CA[5]  
CA[6]  
CA[7]  
CA[8]  
CA[9]  
8
ddr1_ecc_d[7:0]  
ddr1_dqm_ecc  
ddr1_dqs_ecc  
ddr1_dqsn_ecc  
vdds_ddr  
1 K  
vdds_ddr  
1 K  
0.1 µF  
0.1 µF  
ZQ0/1  
ZQ  
Vref(CA)  
Vref(DQ)  
DDR_VREF  
vdds_ddr  
1 K  
0.1 µF  
1 K  
SPRS917_LPDDR2_02  
Figure 8-24. 32-Bit Interface with and without ECC using one x32 LPDDR2 device(1)(3)(4)  
(1) When LPDDR2 memory are used, these signal function as ddr1_ca[9:0]. For more information, see Table 4-11, EMIF1 Signal  
Descriptions  
(2) Rca is 10 resistor and is to be placed near TDA3x device.  
(3) The RDAT is 22 resistor and is to be placed near TDA3x device  
(4) If ECC is required, pins available behind data lane 3 (data would then only use 16bit (lanes 1 and 2))  
When not using a part of LPDDR2 interface (using x16 or not using the LPDDR2 interface):  
Connect the vdds_ddr supply to 1.8 V  
Tie off ddr1_dqsx (x=0,1,2,3) that are unused to vss via 1 kΩ  
Tie off ddr1_dqsnx (x=0,1,2,3) that are unused to vdds_ddr via 1 kΩ  
All other unused pins can be left as NC.  
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Note: All the unused DDR ADDR_CTRL lines used for DDR3 operation should be left as NC.  
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8.7.3.2 Compatible JEDEC LPDDR2 Devices  
Table 8-14 shows the supported LPDDR2 device configurations which are compatible with this interface.  
Table 8-14. Compatible JEDEC LPDDR2 Devices (Per Interface)  
NO.  
1
PARAMETER  
JEDEC LPDDR2 device speed grade  
JEDEC LPDDR2 device bit width  
JEDEC LPDDR2 device count  
CONDITION  
MIN  
MAX  
UNIT  
tc(DDR_CK) and tc(DDR_NCK)  
LPDDR2-667  
2
x16  
1
x32  
1
Bits  
3
Devices  
8.7.3.3 LPDDR2 PCB Stackup  
Table 8-15 shows the minimum stackup requirements. Additional layers may be added to the PCB  
stackup to accommodate other circuitry, enhance signal integrity and electromagnetic interference  
performance, or to reduce the size of the PCB footprint.  
Table 8-15. Six-Layer PCB Stackup Suggestion  
LAYER  
TYPE  
Signal  
Plane  
Signal  
Plane  
Plane  
Signal  
DESCRIPTION  
Top signal routing  
Ground  
1
2
3
4
5
6
Signal routing  
Split power plane  
Ground  
Bottom signal routing  
PCB stackup specifications for LPDDR2 interface are listed in Table 8-16.  
Table 8-16. PCB Stackup Specifications  
NO.  
1
PARAMETER  
MIN  
6
TYP  
MAX  
UNIT  
PCB routing and plane layers  
Signal routing layers  
2
3
3
Full ground reference layers under LPDDR2 routing region(1)  
Full vdds_ddr power reference layers under the LPDDR2 routing region(1)  
Number of reference plane cuts allowed within LPDDR2 routing region(2)  
Number of layers between LPDDR2 routing layer and reference plane(3)  
PCB routing feature size  
1
4
1
5
0
0
6
7
4
4
mils  
mils  
mils  
mils  
8
PCB trace width, w  
PCB BGA escape via pad size(4)  
9
18  
8
20  
10 PCB BGA escape via hole size  
11 Single-ended impedance, Zo(5)  
12 Impedance control(6)(7)  
50  
Zo  
75  
Zo-5  
Zo+5  
(1) Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer  
return current as the trace routes switch routing layers.  
(2) No traces should cross reference plane cuts within the LPDDR2 routing region. High speed signal traces crossing reference plane cuts  
create large return current paths which can lead to excessive crosstalk and EMI radiation.  
(3) Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.  
(4) An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available  
for power routing. An 18-mil pad is required for minimum layer count escape.  
(5) Zo is the nominal singled-ended impedance selected for the PCB.  
(6) This parameter specifies the AC characteristic impedance tolerance for each segment of a PCB signal trace relative to the chosen Zo  
defined by the single-ended impedance parameter.  
(7) Tighter impedance control is required to ensure flight time skew is minimal.  
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8.7.3.4 LPDDR2 Placement  
Figure 8-25 shows the placement rules for the device as well as the LPDDR2 memory device. Placement  
restrictions are provided as a guidance to restrict maximum trace lengths and allow for proper routing  
space.  
X1  
LPDDR2  
DATA  
LPDDR2  
ADDT_CTRL  
Y
SPRS917_LPDDR2_04  
Figure 8-25. Placement Specifications  
Table 8-17. Placement Specifications(1)  
NO.  
1
PARAMETER  
MIN  
MAX  
900  
UNIT  
mils  
mils  
w
X1 Offset(2)(3)  
Y Offset  
2
200  
3
Clearance from non-LPDDR2 signal to LPDDR2 keepout region(4)(5)  
4
(1) LPDDR2 keepout region to encompass entire LPDDR2 routing area.  
(2) Measurements from center of device to center of LPDDR2 device.  
(3) Minimizing X1 and Y improves timing margins.  
(4) w is defined as the signal trace width.  
(5) Non-LPDDR2 signals allowed within LPDDR2 keepout region provided they are separated from LPDDR2 routing layers by a ground  
plane.  
8.7.3.5 LPDDR2 Keepout Region  
The region of the PCB used for LPDDR2 circuitry must be isolated from other signals. The LPDDR2  
keepout region is defined for this purpose and is shown in Figure 8-26. This region should encompass all  
LPDDR2 circuitry and the region size varies with component placement and LPDDR2 routing. Non-  
LPDDR2 signals should not be routed on the same signal layer as LPDDR2 signals within the LPDDR2  
keepout region. Non-LPDDR2 signals may be routed in the region provided they are routed on layers  
separated from LPDDR2 signal layers by a ground layer. No breaks should be allowed in the reference  
ground or vdds_ddr power plane in this region. In addition, the vdds_ddr power plane should cover the  
entire keepout region.  
LPDDR2 Keepout Region  
Encompasses Entire  
LPDDR2 Routing Area  
LPDDR2  
DATA  
LPDDR2  
ADDT_CTRL  
SPRS917_LPDDR2_05  
Figure 8-26. LPDDR2 Keepout Region  
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8.7.3.6 LPDDR2 Net Classes  
Table 8-18. Clock Net Class Definitions for the LPDDR2 Interface  
CLOCK NET CLASS  
PIN NAMES  
CK  
ddr1_ck and ddr1_nck  
ddr1_dqs0 and ddr1_dqsn0  
ddr1_dqs1 and ddr1_dqsn1  
ddr1_dqs2 and ddr1_dqsn2  
ddr1_dqs3 and ddr1_dqsn3  
DQS0  
DQS1  
DQS2  
DQS3  
Table 8-19. Signal Net Class and Associated Clock Net Class for LPDDR2 Interface  
ASSOCIATED CLOCK  
SIGNAL NET CLASS  
BALL NAMES  
NET CLASS  
ADDR_CTRL  
CK  
ddr1_ba[2:0], ddr1_csn0, ddr1_cke0, ddr1_rasn, ddr1_casn, ddr1_wen,  
ddr1_a1, ddr1_a2, dr1_a10, ddr1_a13  
(1)  
DQ0  
DQS0  
DQS1  
DQS2  
DQS3  
ddr1_d[7:0], ddr1_dqm0, ddr1_dqs0, ddr1_dqsn0  
(1)  
DQ1  
ddr1_d[15:8], ddr1_dqm1, ddr1_dqs1, ddr1_dqsn1  
(1)  
DQ2  
ddr1_d[23:16], ddr1_dqm2, ddr1_dqs2, ddr1_dqsn2  
(1)  
DQ3  
ddr1_d[31:24], ddr1_dqm3, ddr1_dqs3, ddr1_dqsn3  
(1) DQ data class includes DQS/N pins  
8.7.3.7 LPDDR2 Signal Termination  
On-device termination (ODT) is available for DQ[3:0] signal net classes, but is not specifically required for  
normal operation. System designers may evaluate the need for additional series termination if required  
based on signal integrity, EMI and overshoot/undershoot reduction.  
On board series termination is recommended for all ADDR_CTRL and CK class signals. It is  
recommended a resistor with value of 10 to be placed close to the TDA3x source pin (within 350 mils).  
On board series termination is recommended for all DQx and DQSx class signals. It is recommended a  
resistor with value of 22 to be placed close to the TDA3x source pin (within 500 mils).  
8.7.3.8 LPDDR2 DDR_VREF Routing  
DDR_VREF is the reference voltage for the input buffers on the LPDDR2 memory. DDR_VREF is  
intended to be half the LPDDR2 power supply voltage and is typically generated with a voltage divider  
connected to the VDDS_DDR power supply. It should be routed as a nominal 20-mil wide trace with 0.1-  
µF bypass capacitors near each device connection. Narrowing of DDR_VREF is allowed to accommodate  
routing congestion.  
8.7.4 Routing Specification  
8.7.4.1 DQS[x] and DQ[x] Routing Specification  
DQS[x] lines are point-to-point differential and DQ[x] lines are point-to-point single ended. Figure 8-27 and  
Figure 8-28 represent the supported topologies. Figure 8-29 and Figure 8-30 show the DQS[x] and DQ[x]  
routing. Figure 8-31 shows the DQLM for the LPDDR2 interface.  
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Device  
DQS[x]  
DDR3  
DQS[x]+  
DQS[x]-  
DQS[x]  
IO Buffer  
IO Buffer  
Routed Differentially  
SPRS917_LPDDR2_06  
x = 0, 1, 2, 3  
Figure 8-27. DQS[x] Topology  
Device  
DQ[x]  
DDR3  
DQ[x]  
DQ[x]  
IO Buffer  
IO Buffer  
SPRS917_LPDDR2_07  
x = 0, 1, 2, 3  
Figure 8-28. DQ[x] Topology  
LPDDR2  
DATA  
RDAT  
RDAT  
LPDDR2  
ADDT_CTRL  
Routed Differentially  
SPRS917_LPDDR2_08  
x = 0, 1, 2, 3  
Figure 8-29. DQS[x] Routing  
LPDDR2  
DATA  
LPDDR2  
ADDT_CTRL  
DQ[x]  
SPRS917_LPDDR2_09  
x = 0, 1, 2, 3  
Figure 8-30. DQ[x] Routing  
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DQLMXi  
DQi  
LPDDR2  
interface  
i = 0, 1, 2, 3  
DQLMYi  
DQLM0 = DQLMX0 + DQLMY0  
DQLM1 = DQLMX1 + DQLMY1  
DQLM2 = DQLMX2 + DQLMY2  
DQLM3 = DQLMX3 + DQLMY3  
DQ0 - DQ3 represent data bytes 0 - 3.  
SPRS917_LPDDR2_10  
There are four DQLMs, one for each data byte, in a 32-bit interface and two DQLMs, one for each data byte, in a 16-  
bit interface. Each DQLM is the longest Manhattan distance of the byte.  
Figure 8-31. DQLM for LPDDR2 Interface  
Trace routing specifications for the DQ[x] and the DQS[x] are specified in Table 8-20.  
Table 8-20. DQS[x] and DQ[x] Routing Specification(1)(2)  
NO.  
1
PARAMETER  
MIN  
TYP  
MAX  
DQLM0  
DQLM1  
DQLM2  
DQLM3  
10  
UNIT  
mils  
mils  
mils  
mils  
ps  
DQ0 nominal length(3)(4)  
DQ1 nominal length(3)(5)  
DQ2 nominal length (3)(6)  
DQ3 nominal length (3)(7)  
DQ[x] skew(8)  
2
3
4
5
6
DQS[x] skew  
5
ps  
7
Via count per each trace in DQ[x], DQS[x]  
Via count difference across a given DQ[x], DQS[x]  
DQS[x]-to-DQ[x] skew(8)(9)  
2
8
0
9
10  
ps  
w
10 Center-to-center DQ[x] to other LPDDR2 trace spacing(10)(11)  
11 Center-to-center DQ[x] to other DQ[x] trace spacing(10)(12)  
12 DQS[x] center-to-center spacing(13)  
4
3
w
13 DQS[x] center-to-center spacing to other net(10)  
4
w
(1) DQS[x] represents the DQS0, DQS1, DQS2, DQS3 clock net classes, and DQ[x] represents the DQ0, DQ1, DQ2, DQ3 signal net  
classes.  
(2) External termination disallowed. Data termination should use built-in ODT functionality.  
(3) DQLMn is the longest Manhattan distance of a byte.  
(4) DQLM0 is the longest Manhattan length for the DQ0 net class.  
(5) DQLM1 is the longest Manhattan length for the DQ1 net class.  
(6) DQLM2 is the longest Manhattan length for the DQ2 net class.  
(7) DQLM3 is the longest Manhattan length for the DQ3 net class.  
(8) Length matching is only done within a byte. Length matching across bytes is not required.  
(9) Each DQS clock net class is length matched to its associated DQ signal net class.  
(10) Center-to-center spacing is allowed to fall to minimum for up to 1000 mils of routed length.  
(11) Other LPDDR2 trace spacing means signals that are not part of the same DQ[x] signal net class.  
(12) This applies to spacing within same DQ[x] signal net class.  
(13) DQS[x] pair spacing is set to ensure proper differential impedance. Differential impedance should be Zo x 2, where Zo is the single-  
ended impedance.  
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8.7.4.2 CK and ADDR_CTRL Routing Specification  
CK signals are routed as point-to-point differential, and ADDR_CTRL signals are routed as point-to-point  
single ended. The supported topology for CK and ADDR_CTRL are shown in Figure 8-32 through  
Figure 8-35. Note that ADDR_CTRL are routed very similar to DQ and CK is routed very similar to DQS.  
CK+  
Device CK  
LPDDR2  
Output Buffer  
Input Buffer  
CK-  
Routed Differentially  
SPRS917_LPDDR2_11  
Figure 8-32. CK Signals Topology  
Device  
ADDR_CTRL  
Output Buffer  
LPDDR2  
ADDR_CTRL  
ADDR_CTRL  
Input Buffer  
SPRS917_LPDDR2_12  
Figure 8-33. ADDR_CTRL Signals Topology  
LPDDR2  
DATA  
LPDDR2  
ADDT_CTRL  
SPRS917_LPDDR2_13  
Figure 8-34. CK Signals Routing  
LPDDR2  
DATA  
ADDR_CTRL  
LPDDR2  
ADDT_CTRL  
SPRS917_LPDDR2_14  
Figure 8-35. ADDR_CTRL Signals Routing  
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CACLMX  
LPDDR2  
interface  
CACLM = CACLMX + CACLMY  
CACLMY  
SPRS917_LPDDR2_15  
CACLM is the longest Manhattan distance of the CK/ADDR_CTRL signal class.  
Figure 8-36. CACLM for LPDDR2 Interface  
Trace routing specifications for the CK and the ADD_CTRL are specified in Table 8-21.  
Table 8-21. CK and ADDR_CTRL Routing Specification  
NO.  
1
PARAMETER  
CK and ADDR_CTRL nominal trace length(1)  
ADDR_CTRL skew  
MIN  
TYP  
MAX  
UNIT  
mils  
ps  
CACLM  
2
20  
5
3
CK skew  
ps  
4
Via count per each trace ADDR_CTRL, CK  
Via count difference across ADDR_CTRL, CK  
ADDR_CTRL-to-CK skew  
2
5
0
6
20  
ps  
w
7
Center-to-center ADDR_CTRL to other LPDDR2 trace spacing(2)(3)  
Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing(2)  
CK center-to-center spacing(4)  
4
3
8
w
9
10 CK center-to-center spacing to other net(2)  
4
w
(1) CACLM is the longest Manhattan distance of ADDR_CTRL and CK.  
(2) Center-to-center spacing is allowed to fall to minimum for up to 1000 mils of routed length.  
(3) Other LPDDR2 trace spacing means signals that are not part of the same CK, ADDR_CTRL signal net class.  
(4) CK pair spacing is set to ensure proper differential impedance. Differential impedance should be Zo x 2, where Zo is the single ended  
impedance.  
8.8 DDR2 Board Design and Layout Guidelines  
8.8.1 DDR2 General Board Layout Guidelines  
To help ensure good signaling performance, consider the following board design guidelines:  
Avoid crossing splits in the power plane.  
Minimize Vref noise.  
Use the widest trace that is practical between decoupling capacitors and memory module.  
Maintain a single reference.  
Minimize ISI by keeping impedances matched.  
Minimize crosstalk by isolating sensitive bits, such as strobes, and avoiding return path discontinuities.  
Use proper low-pass filtering on the Vref pins.  
Keep the stub length as short as possible.  
Add additional spacing for on-clock and strobe nets to eliminate crosstalk.  
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Maintain a common ground reference for all bypass and decoupling capacitors.  
Take into account the differences in propagation delays between microstrip and stripline nets when  
evaluating timing constraints.  
8.8.2 DDR2 Board Design and Layout Guidelines  
8.8.2.1 Board Designs  
TI only supports board designs that follow the guidelines outlined in this document. The switching  
characteristics and the timing diagram for the DDR2 memory controller are shown in Table 8-22 and  
Figure 8-37.  
Table 8-22. Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory  
Controller  
PARAMETE  
NO.  
DESCRIPTION  
MIN  
MAX  
UNIT  
R
DDR21  
tc(DDR_CLK)  
Cycle time, DDR_CLK  
2.5  
8
ns  
1
ddrx_ck  
PCB_DDR2_0  
Figure 8-37. DDR2 Memory Controller Clock Timing  
8.8.2.2 DDR2 Interface  
This section provides the timing specification for the DDR2 interface as a PCB design and manufacturing  
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,  
and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need  
for a complex timing closure process. For more information regarding the guidelines for using this DDR2  
specification, see the Understanding TI’s PCB Routing Rule-Based DDR Timing Specification Application  
Report (Literature Number: SPRAAV0).  
8.8.2.2.1 DDR2 Interface Schematic  
Figure 8-38 shows the DDR2 interface schematic for a x32 DDR2 memory system. In Figure 8-39 the x16  
DDR2 system schematic is identical except that the high-word DDR2 device is deleted.  
When not using all or part of a DDR2 interface, the proper method of handling the unused pins is to tie off  
the ddrx_dqsi pins to ground via a 1k-Ω resistor and to tie off the ddrx_dqsni pins to the corresponding  
vdds_ddrx supply via a 1k-Ω resistor. This needs to be done for each byte not used. The vdds_ddrx and  
ddrx_vref0 power supply pins need to be connected to their respective power supplies even if DDRx is not  
being used. All other DDR interface pins can be left unconnected. Note that the supported modes for use  
of the DDR EMIF are 32-bits wide, 16-bits wide, or not used.  
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DDR2  
DQ0  
ddrx_d0  
ddrx_d7  
DQ7  
DQM0  
DQS0  
ddrx_dqm0  
ddrx_dqs0  
ddrx_dqsn0  
ddrx_d8  
DQS0n  
DQ8  
ddrx_d15  
ddrx_dqm1  
ddrx_dqs1  
DQ15  
DQM1  
DQS1  
ddrx_dqsn1  
ddrx_odt0  
DQS1n  
ODT  
ddrx_d16  
DQ16  
ddrx_d23  
ddrx_dqm2  
ddrx_dqs2  
DQ23  
DQM2  
DQS2  
DQS2n  
DQ24  
ddrx_dqsn2  
ddrx_d24  
DQ31  
ddrx_d31  
ddrx_dqm3  
ddrx_dqs3  
ddrx_dqsn3  
DQM3  
DQS3  
DQS3n  
ddrx_ba0  
BA0  
ddrx_ba2  
ddrx_a0  
BA2  
A0  
ddrx_a14  
A14  
CS  
ddrx_csn0  
vdds_ddrx(A)  
ddrx_casn  
ddrx_rasn  
CAS  
RAS  
ddrx_wen  
ddrx_cke  
ddrx_ck  
WE  
CKE  
CK  
0.1 µF  
0.1 µF  
1 K Ω 1%  
CK  
ddrx_nck  
VREF  
VREF  
1 K Ω 1%  
ddrx_rst  
NC  
PCB_DDR2_1  
A. vdds_ddrx is the power supply for the DDR2 memories and the Device DDR2 interface.  
B. One of these capacitors can be eliminated if the divider and its capacitors are placed near a VREF pin.  
Figure 8-38. 32-Bit DDR2 High-Level Schematic  
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DDR2  
DQ0  
ddrx_d0  
ddrx_d7  
DQ7  
LDM  
LDQS  
ddrx_dqm0  
ddrx_dqs0  
ddrx_dqsn0  
ddrx_d8  
LDQS  
DQ8  
ddrx_d15  
ddrx_dqm1  
ddrx_dqs1  
ddrx_dqsn1  
ddrx_odt0  
DQ15  
UDM  
UDQS  
UDQS  
ODT  
ddrx_d16  
NC  
vdds_ddrx(A)  
ddrx_d23  
NC  
NC  
ddrx_dqm2  
1 KΩ  
1 KΩ  
ddrx_dqsn2  
ddrx_dqs2  
NC  
ddrx_d24  
vdds_ddrx(A)  
ddrx_d31  
NC  
NC  
1 KΩ  
1 KΩ  
ddrx_dqm3  
ddrx_dqsn3  
ddrx_dqs3  
ddrx_ba0  
NC  
BA0  
ddrx_ba2  
ddrx_a0  
BA2  
A0  
ddrx_a14  
A14  
CS  
ddrx_csn0  
CAS  
RAS  
ddrx_casn  
ddrx_rasn  
vdds_ddrx(A)  
WE  
ddrx_wen  
ddrx_cke  
ddrx_ck  
CKE  
CK  
CK  
1 K Ω 1%  
0.1 µF  
0.1 µF  
ddrx_nck  
VREF  
VREF  
1 K Ω 1%  
ddrx_rst  
NC  
PCB_DDR2_2  
A. vdds_ddrx is the power supply for the DDR2 memories and the Device DDR2 interface.  
B. One of these capacitors can be eliminated if the divider and its capacitors are placed near a VREF pin.  
Figure 8-39. 16-Bit DDR2 High-Level Schematic  
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8.8.2.2.2 Compatible JEDEC DDR2 Devices  
Table 8-23 shows the parameters of the JEDEC DDR2 devices that are compatible with this interface.  
Generally, the DDR2 interface is compatible with x16/x32 DDR2-800 speed grade DDR2 devices.  
Table 8-23. Compatible JEDEC DDR2 Devices (Per Interface)  
NO.  
PARAMETER  
JEDEC DDR2 device speed grade(1)  
MIN  
DDR2-800  
x16  
MAX  
UNIT  
CJ21  
CJ22  
CJ23  
JEDEC DDR2 device bit width  
JEDEC DDR2 device count(2)  
x32  
1
Bits  
1
Devices  
(1) Higher DDR2 speed grades are supported due to inherent JEDEC DDR2 backwards compatibility.  
(2) One DDR2 device is used for a 16-bit DDR2 and 32-bit DDR2 memory system.  
8.8.2.2.3 PCB Stackup  
The minimum stackup required for routing the Device is a six-layer stackup as shown in Table 8-24.  
Additional layers may be added to the PCB stackup to accommodate other circuitry or to reduce the size  
of the PCB footprint.  
Table 8-24. Minimum PCB Stackup  
LAYER  
TYPE  
Signal  
Plane  
Plane  
Signal  
Plane  
Signal  
DESCRIPTION  
External Routing  
Ground  
1
2
3
4
5
6
Power  
Internal routing  
Ground  
External Routing  
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Complete stackup specifications are provided in Table 8-25.  
Table 8-25. PCB Stackup Specifications  
NO.  
PARAMETER  
MIN  
6
TYP  
MAX  
UNIT  
PS21  
PS22  
PS23  
PS24  
PCB routing/plane layers  
Signal routing layers  
3
Full ground reference layers under DDR2 routing region(1)  
1
Full vdds_ddrx power reference layers under the DDR2 routing  
1
region(1)  
PS25  
PS26  
PS27  
PS28  
PS29  
PS210  
Number of reference plane cuts allowed within DDR routing region(2)  
Number of layers between DDR2 routing layer and reference plane(3)  
PCB routing feature size  
0
0
4
4
Mils  
Mils  
PCB trace width, w  
Single-ended impedance, Zo  
Impedance control(4)  
50  
75  
Z-5  
Z
Z+5  
(1) Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer  
return current as the trace routes switch routing layers. A full ground reference layer should be placed adjacent to each DDR routing  
layer in PCB stack up.  
(2) No traces should cross reference plane cuts within the DDR routing region. High speed signal traces crossing reference plane cuts  
create large return current paths which can lead to excessive crosstalk and EMI radiation.  
(3) Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.  
(4) Z is the nominal singled-ended impedance selected for the PCB specified by PS29.  
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8.8.2.2.4 Placement  
Figure 8-40 shows the required placement for the Device as well as the DDR2 devices. The dimensions  
for this figure are defined in Table 8-26. The placement does not restrict the side of the PCB on which the  
devices are mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and  
allow for proper routing space. For a 16-bit DDR memory system, the high-word DDR2 device is omitted  
from the placement.  
X1  
A1  
DDR2  
Memory  
DDR2 Controller  
Y1  
PCB_DDR2_3  
Figure 8-40. Device and DDR2 Device Placement  
Table 8-26. Placement Specifications DDR2  
NO.  
PARAMETER  
MIN  
MAX  
1100  
500  
UNIT  
Mils  
KOD21  
KOD22  
KOD24  
KOD25  
X1  
Y1  
Mils  
DDR2 keepout region (1)  
Clearance from non-DDR2 signal to DDR2 keepout region (2) (3)  
4
W
(1) DDR2 keepout region to encompass entire DDR2 routing area.  
(2) Non-DDR2 signals allowed within DDR2 keepout region provided they are separated from DDR2 routing layers by a ground plane.  
(3) If a device has more than one DDR controller, the signals from the other controller(s) are considered non-DDR2 and should be  
separated by this specification.  
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8.8.2.2.5 DDR2 Keepout Region  
The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2  
keepout region is defined for this purpose and is shown in Figure 8-41. The size of this region varies with  
the placement and DDR routing. Additional clearances required for the keepout region are shown in  
Table 8-26.  
The region shown in Table 8-26 should encompass all the DDR2 circuitry and varies depending on  
placement. Non-DDR2 signals should not be routed on the DDR signal layers within the DDR2 keepout  
region. Non-DDR2 signals may be routed in the region, provided they are routed on layers separated from  
DDR2 signal layers by a ground layer. No breaks should be allowed in the reference ground layers in this  
region. In addition, the vdds_ddrx power plane should cover the entire keepout region. Routes for the two  
DDR interfaces must be separated by at least 4x; the more separation, the better.  
DDR2 Controller  
A1  
Device  
PCB_DDR2_4  
Figure 8-41. DDR2 Keepout Region  
8.8.2.2.6 Bulk Bypass Capacitors  
Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry.  
Table 8-27 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note  
that this table only covers the bypass needs of the DDR2 interfaces and DDR2 device. Additional bulk  
bypass capacitance may be needed for other circuitry.  
Table 8-27. Bulk Bypass Capacitors  
NO.  
PARAMETER  
vdds_ddrx bulk bypass capacitor (1µF) count(1)  
MIN  
TYP  
10  
MAX  
UNIT  
Devices  
μF  
BC21  
BC22  
vdds_ddrx bulk bypass total capacitance  
50  
(1) These devices should be placed near the devices they are bypassing, but preference should be given to the placement of the high  
speed (HS) bypass capacitors and DDR2 signal routing.  
8.8.2.2.7 High Speed Bypass Capacitors  
TI recommends that a PDN/power integrity analysis is performed to ensure that capacitor selection and  
placement is optimal for a given implementation. This section provides guidelines that can serve as a  
good starting point.  
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High speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly  
important to minimize the parasitic series inductance of the HS bypass capacitors, processor/DDR power,  
and processor/DDR ground connections. Table 8-28 contains the specification for the HS bypass  
capacitors as well as for the power connections on the PCB. Generally speaking, it is good to:  
1. Fit as many HS bypass capacitors as possible.  
2. HS bypass capacitor value is < 1µF  
3. Minimize the distance from the bypass cap to the pins/balls being bypassed.  
4. Use the smallest physical sized capacitors possible with the highest capacitance readily available.  
5. Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest  
hole size via possible.  
6. Minimize via sharing. Note the limites on via sharing shown in Table 8-28.  
Table 8-28. High Speed Bypass Capacitors  
NO.  
PARAMETER  
HS bypass capacitor package size(1)  
Distance, HS bypass capacitor to processor being bypassed(2)(3)(4)  
Processor HS bypass capacitor count (12)  
MIN  
TYP  
MAX  
0402  
400(12)  
UNIT  
10 Mils  
Mils  
HS21  
HS22  
HS23  
HS24  
0201  
12(11)  
3.4  
Devices  
μF  
Processor HS bypass capacitor total capacitance per vdds_ddrx rail  
(12)  
HS25  
Number of connection vias for each device power/ground ball per  
vdds_ddrx rail (5)  
1
Vias  
HS26  
HS27  
Trace length from device power/ground ball to connection via(2)  
Distance, HS bypass capacitor to DDR device being bypassed(6)  
Number of connection vias for each HS capacitor(8)(9)  
DDR2 device HS bypass capacitor count(7)  
DDR2 device HS bypass capacitor total capacitance(7)  
Trace length from bypass capacitor connect to connection via(2)(9)  
35  
70  
Mils  
Mils  
150  
(14)  
HS28  
4
Vias  
Devices  
μF  
(13)  
HS29  
12  
HS210  
HS211  
HS212  
0.85  
1
35  
35  
100  
60  
Mils  
Number of connection vias for each DDR2 device power/ground  
ball(10)  
Vias  
HS213  
Trace length from DDR2 device power/ground ball to connection  
via(2)(8)  
Mils  
(1) LxW, 10-mil units, that is, a 0402 is a 40x20-mil surface-mount capacitor.  
(2) Closer/shorter is better.  
(3) Measured from the nearest processor power/ground ball to the center of the capacitor package.  
(4) Three of these capacitors should be located underneath the processor, between the cluster of vdds_ddrx balls and ground balls,  
between the DDR interfaces on the package.  
(5) See the Via Channel™ escape for the processor package.  
(6) Measured from the DDR2 device power/ground ball to the center of the capacitor package.  
(7) Per DDR2 device.  
(8) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of  
vias is permitted on the same side of the board.  
(9) An HS bypass capacitor may share a via with a DDR device mounted on the same side of the PCB. A wide trace should be used for the  
connection and the length from the capacitor pad to the DDR device pad should be less than 150 mils.  
(10) Up to a total of two pairs of DDR power/ground balls may share a via.  
(11) The capacitor recommendations in this data manual reflect only the needs of this processor. Please see the memory vendor’s  
guidelines for determining the appropriate decoupling capacitor arrangement for the memory device itself.  
(12) For more information, see Section 8.3, Core Power Domains  
(13) For more information refer to DDR2 specification.  
(14) Preferred configuration is 4 vias: 2 to power and 2 to ground.  
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8.8.2.2.8 Net Classes  
Table 8-29 lists the clock net classes for the DDR2 interface. Table 8-30 lists the signal net classes, and  
associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the  
termination and routing rules that follow.  
Table 8-29. Clock Net Class Definitions  
CLOCK NET CLASS PIN NAMES  
CK  
ddrx_ck / ddrx_nck  
DQS0  
ddrx_dqs0 / ddrx_dqsn0  
ddrx_dqs1 / ddrx_dqsn1  
ddrx_dqs2 / ddrx_dqsn2  
ddrx_dqs3 / ddrx_dqsn3  
DQS1  
DQS2(1)  
DQS3(1)  
(1) Only used on 32-bit wide DDR2 memory systems.  
Table 8-30. Signal Net Class Definitions  
ASSOCIATED CLOCK  
SIGNAL NET CLASS  
PIN NAMES  
NET CLASS  
ADDR_CTRL  
CK  
ddrx_ba[2:0], ddrx_a[14:0], ddrx_csnj, ddrx_casn, ddrx_rasn, ddrx_wen,  
ddrx_cke, ddrx_odti  
DQ0  
DQ1  
DQ2(1)  
DQ3(1)  
DQS0  
DQS1  
DQS2  
DQS3  
ddrx_d[7:0], ddrx_dqm0  
ddrx_d[15:8], ddrx_dqm1  
ddrx_d[23:16], ddrx_dqm2  
ddrx_d[31:24], ddrx_dqm3  
(1) Only used on 32-bit wide DDR2 memory systems.  
8.8.2.2.9 DDR2 Signal Termination  
Signal terminators are NOT required in CK, ADDR_CTRL, and DATA net classes. Serial terminators may  
be used to reduce EMI risk; however, serial terminations are the only type permitted. ODTs are integrated  
on the data byte net classes. They should be enabled to ensure signal integrity. Table 8-31 shows the  
specifications for the series terminators.  
Table 8-31. DDR2 Signal Terminations  
NO.  
PARAMETER  
MIN  
0
TYP  
MAX  
10  
UNIT  
ST21  
ST22  
ST23  
CK net class(1)(2)  
ADDR_CTRL net class(1) (2)(3)(4)  
Data byte net classes (DQS0-DQS3, DQ0-DQ3)(5)  
0
Zo  
0
Zo  
(1) Only series termination is permitted, parallel or SST specifically disallowed on board.  
(2) Only required for EMI reduction.  
(3) Terminator values larger than typical only recommended to address EMI issues.  
(4) Termination value should be uniform across net class.  
(5) No external terminations allowed for data byte net classes ODT is to be used.  
8.8.2.2.10 VREF Routing  
VREF (ddrx_vref0) is used as a reference by the input buffers of the DDR2 memories. VREF is intended  
to be half the DDR2 power supply voltage and should be created using a resistive divider as shown in  
Figure 8-39. Other methods of creating VREF are not recommended. Figure 8-42 shows the layout  
guidelines for VREF.  
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VREF Nominal Max Trace  
width is 20 mils  
VREF Bypass Capacitor  
vdds_ddrx(A)  
1 K Ω 1%  
VREF  
0.1 µF  
0.1 µF  
DDR2 Controller  
1 K Ω 1%  
Neck down to minimum in BGA escape  
regions is acceptable. Narrowing to  
accomodate via congestion for short  
distances is also acceptable. Best  
performance is obtained if the width  
of VREF is maximized.  
A. vdds_ddrx is the power supply for the DDR2 memories and the Device DDR2 interface.  
PCB_DDR2_5  
Figure 8-42. VREF Routing and Topology  
8.8.2.3 DDR2 CK and ADDR_CTRL Routing  
Figure 8-43 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a  
point to point connection with required skew matching.  
DDR2 Controller  
A’  
PCB_DDR2_6  
Figure 8-43. CK and ADDR_CTRL Routing and Topology  
Table 8-32. CK and ADDR_CTRL Routing Specification  
NO.  
PARAMETER  
Center-to-center ddrx_ck - ddrx_nck spacing  
MIN  
MAX  
2w  
5
UNIT  
RSC21  
RSC22  
RSC25  
RSC26  
RSC27  
RSC28  
RSC29  
ddrx_ck / ddrx_nck skew  
ps  
Center-to-center CK to other DDR2 trace spacing(2)  
CK/ADDR_CTRL trace length(3)  
4w  
680  
25  
ps  
ps  
ps  
ADDR_CTRL-to-CK skew mismatch  
ADDR_CTRL-to-ADDR_CTRL skew mismatch  
Center-to-center ADDR_CTRL to other DDR2 trace spacing(2)  
25  
4w  
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UNIT  
Table 8-32. CK and ADDR_CTRL Routing Specification (continued)  
NO.  
PARAMETER  
MIN  
MAX  
Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing(2)  
RSC210  
3w  
(1) Series terminator, if used, should be located closest to the Device.  
(2) Center-to-center spacing is allowed to fall to minimum 2w for up to 500 mils of routed length to accommodate BGA escape and routing  
congestion.  
(3) This is the longest routing length of the CK and ADDR_CTRL net classes.  
Figure 8-44 shows the topology and routing for the DQS and DQ net classes; the routes are point to point.  
Skew matching across bytes is not needed nor recommended. The termination resistor should be placed  
near the processor.  
E0  
E1  
DDR2 Controller  
E2  
E3  
PCB_DDR2_7  
Figure 8-44. DQS and DQ Routing and Topology  
Table 8-33. DQS and DQ Routing Specification  
NO.  
PARAMETER  
Center-to-center DQS-DQSn spacing in E0|E1|E2|E3  
DQS-DQSn skew in E0|E1|E2|E3  
Center-to-center DQS to other DDR2 trace spacing(1)  
DQS/DQ trace length (2)(3)(4)  
DQ-to-DQS skew mismatch(2)(3)(4)  
DQ-to-DQ skew mismatch(2)(3)(4)  
DQ-to-DQ/DQS via count mismatch(2)(3)(4)  
Center-to-center DQ to other DDR2 trace spacing(1)(5)  
Center-to-center DQ to other DQ trace spacing(1)(6)(7)  
DQ/DQS E skew mismatch(2)(3)(4)  
MIN  
MAX  
UNIT  
RSDQ21  
RSDQ22  
RSDQ23  
RSDQ24  
RSDQ25  
RSDQ26  
RSDQ27  
RSDQ28  
RSDQ29  
RSDQ210  
2w  
5
ps  
4w  
325  
10  
10  
1
ps  
ps  
ps  
Vias  
4w  
3w  
25  
ps  
(1) Center-to-center spacing is allowed to fall to minimum 2w for up to 500 mils of routed length to accommodate BGA escape and routing  
congestion.  
(2) A 16-bit DDR memory system has two sets of data net classes; one for data byte 0, and one for data byte 1, each with an associated  
DQS (2 DQSs) per DDR EMIF used.  
(3) A 32-bit DDR memory system has four sets of data net classes; one each for data bytes 0 through 3, and each associated with a DQS  
(4 DQSs) per DDR EMIF used.  
(4) There is no need, and it is not recommended, to skew match across data bytes; that is, from DQS0 and data byte 0 to DQS1 and data  
byte1.  
(5) DQs from other DQS domains are considered other DDR2 trace.  
(6) DQs from other data bytes are considered other DDR2 trace.  
(7) This is the longest routing distance of each of the DQS and DQ net classes.  
8.9 DDR3 Board Design and Layout Guidelines  
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8.9.1 DDR3 General Board Layout Guidelines  
To help ensure good signaling performance, consider the following board design guidelines:  
Avoid crossing splits in the power plane.  
Use the widest trace that is practical between decoupling capacitors and memory module.  
Maintain a single reference  
Minimize ISI by keeping impedances matched.  
Minimize crosstalk by isolating sensitive bits, such as strobes, and avoiding return path discontinuities.  
Keep the stub length as short as possible.  
Add additional spacing for on-clock and strobe nets to eliminate crosstalk.  
Maintain a common ground reference for all bypass and decoupling capacitors.  
Take into account the differences in propagation delays between microstrip and stripline nets when  
evaluating timing constraints.  
8.9.2 DDR3 Board Design and Layout Guidelines  
8.9.2.1 Board Designs  
TI only supports board designs using DDR3 memory that follow the guidelines in this document. The  
switching characteristics and timing diagram for the DDR3 memory controller are shown in Table 8-34 and  
Figure 8-45.  
Table 8-34. Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory  
Controller  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
1
tc(DDR_CLK)  
Cycle time, DDR_CLK  
1.875  
2.5(1)  
ns  
(1) This is the absolute maximum the clock period can be. Actual maximum clock period may be limited by DDR3 speed grade and  
operating frequency (see the DDR3 memory device data sheet).  
1
DDR_CLK  
SPRS91v_PCB_DDR3_01  
Figure 8-45. DDR3 Memory Controller Clock Timing  
8.9.2.2 DDR3 Device Combinations  
There are several possible combinations of device counts and single- or dual-side mounting, Table 8-35  
summarizes the supported device configurations.  
Table 8-35. Supported DDR3 Device Combinations  
NUMBER OF DDR3  
DEVICES  
DDR3 DEVICE WIDTH  
(BITS)  
ECC DEVICE WIDTH  
(BITS)  
DDR3 EMIF WIDTH  
(BITS)  
MIRRORED?  
1
2
2
2
2
3
3
1x16  
2x8  
-
-
N
Y(1)  
N
16  
16  
32  
32  
16  
16  
32  
2x16  
2x16  
1x16  
2x8  
-
-
Y(1)  
1x8  
1x8  
1x8  
N
N
2x16  
N
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(1) Two DDR3 devices are mirrored when one device is placed on the top of the board and the second device is placed on the bottom of  
the board.  
8.9.2.3 DDR3 Interface Schematic  
8.9.2.3.1 32-Bit DDR3 Interface  
The DDR3 interface schematic varies, depending upon the width of the DDR3 devices used and the width  
of the bus used (16 or 32 bits). General connectivity is straightforward and very similar. 16-bit DDR  
devices look like two 8-bit devices. Figure 8-46 and show the schematic connections for 32-bit interfaces  
using x16 devices.  
8.9.2.3.2 16-Bit DDR3 Interface  
Note that the 16-bit wide interface schematic is practically identical to the 32-bit interface (see Figure 8-  
46); only the high-word DDR memories are removed and the unused DQS inputs are tied off.  
When not using all or part of a DDR interface, the proper method of handling the unused pins is to tie off  
the ddrx_dqsi pins to ground via a 1k-resistor and to tie off the ddrx_dqsni pins to the corresponding  
vdds_ddrx supply via a 1k-resistor. This needs to be done for each byte not used. Although these  
signals have internal pullups and pulldowns, external pullups and pulldowns provide additional protection  
against external electrical noise causing activity on the signals.  
The vdds_ddr and vdds18v_ddrx power supply pins need to be connected to their respective power  
supplies even if upper data byte lanes are not being used. All other DDR interface pins can be left  
unconnected. Note that the supported modes for use of the DDR EMIF are 32-bits wide, 16-bits wide, or  
not used.  
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32-bit DDR3 EMIF  
16-Bit DDR3  
Devices  
ddrx_d31  
ddrx_d24  
DQ15  
8
DQ8  
ddrx_dqm3  
ddrx_dqs3  
ddrx_dqsn3  
UDM  
UDQS  
UDQS  
ddrx_d23  
DQ7  
8
ddrx_d16  
D08  
ddrx_dqm2  
ddrx_dqs2  
ddrx_dqsn2  
LDM  
LDQS  
LDQS  
ddrx_d15  
DQ15  
DQ8  
8
ddrx_d8  
ddrx_dqm1  
ddrx_dqs1  
ddrx_dqsn1  
UDM  
UDQS  
UDQS  
ddrx_d7  
DQ7  
8
ddrx_d0  
DQ0  
ddrx_dqm0  
ddrx_dqs0  
ddrx_dqsn0  
LDM  
LDQS  
LDQS  
0.1 µF  
Zo  
Zo  
ddrx_ck  
CK  
CK  
CK  
CK  
DDR_1V5  
ddrx_nck  
ddrx_odt0  
ddrx_csn0  
ddrx_ba0  
ddrx_ba1  
ddrx_ba2  
ODT  
ODT  
CS  
CS  
BA0  
BA1  
BA2  
BA0  
BA1  
BA2  
DDR_VTT  
Zo  
Zo  
ddrx_a0  
A0  
A0  
16  
ddrx_a15  
A15  
A15  
ddrx_casn  
ddrx_rasn  
ddrx_wen  
ddrx_cke  
ddrx_rst  
CAS  
CAS  
RAS  
WE  
RAS  
WE  
CKE  
CKE  
RST  
DDR_VREF  
RST  
ZQ  
ZQ  
ZQ  
ZQ  
VREFDQ  
VREFCA  
VREFDQ  
VREFCA  
0.1 µF  
0.1 µF  
Zo  
Termination is required. See terminator comments.  
ZQ  
Value determined according to the DDR memory device data sheet.  
Figure 8-46. 32-Bit, One-Bank DDR3 Interface Schematic Using Two 16-Bit DDR3 Devices  
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8.9.2.4 Compatible JEDEC DDR3 Devices  
Table 8-36 shows the parameters of the JEDEC DDR3 devices that are compatible with this interface.  
Generally, the DDR3 interface is compatible with DDR3-1066 devices in the x8 or x16 widths.  
Table 8-36. Compatible JEDEC DDR3 Devices  
N
PARAMETER  
CONDITION  
MIN  
MAX  
UNIT  
O.  
1
JEDEC DDR3 device speed grade(1)  
DDR clock rate = 400MHz  
DDR3-800  
DDR3-1600  
400MHz< DDR clock rate 533MHz  
DDR3-1066  
DDR3-1600  
2
3
JEDEC DDR3 device bit width  
JEDEC DDR3 device count(2)  
x8  
1
x16  
3
Bits  
Devices  
(1) Refer to Table 8-34 Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory Controller for the range of  
supported DDR clock rates.  
(2) For valid DDR3 device configurations and device counts, see Table 8-35 DDR3 Device Combinations.  
8.9.2.5 PCB Stackup  
The minimum stackup for routing the DDR3 interface is a six-layer stack up as shown in Table 8-37.  
Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance SI/EMI  
performance, or to reduce the size of the PCB footprint. Complete stackup specifications are provided in  
Table 8-38.  
Table 8-37. Six-Layer PCB Stackup Suggestion  
LAYER  
TYPE  
Signal  
Plane  
Plane  
Plane  
Plane  
Signal  
DESCRIPTION  
1
2
3
4
5
6
Top routing mostly vertical  
Ground  
Split power plane  
Split power plane or Internal routing  
Ground  
Bottom routing mostly horizontal  
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Table 8-38. PCB Stackup Specifications  
NO.  
PS1  
PS2  
PS3  
PS4  
PS5  
PS6  
PS7  
PS8  
PS9  
PS10  
PARAMETER  
MIN  
6
TYP  
MAX  
UNIT  
PCB routing/plane layers  
Signal routing layers  
3
Full ground reference layers under DDR3 routing region(1)  
Full 1.5-V power reference layers under the DDR3 routing region(1)  
Number of reference plane cuts allowed within DDR routing region(2)  
Number of layers between DDR3 routing layer and reference plane(3)  
PCB routing feature size  
1
1
0
0
4
4
Mils  
Mils  
PCB trace width, w  
Single-ended impedance, Zo  
50  
75  
Impedance control(5)  
Z-5  
Z
Z+5  
(1) Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer  
return current as the trace routes switch routing layers.  
(2) No traces should cross reference plane cuts within the DDR routing region. High speed signal traces crossing reference plane cuts  
create large return current paths which can lead to excessive crosstalk and EMI radiation.  
(3) Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.  
(4) An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available  
for power routing. An 18-mil pad is required for minimum layer count escape.  
(5) Z is the nominal singled-ended impedance selected for the PCB specified by PS9.  
8.9.2.6 Placement  
Figure 8-47 shows the required placement for the processor as well as the DDR3 devices. The  
dimensions for this figure are defined in Table 8-39. The placement does not restrict the side of the PCB  
on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace  
lengths and allow for proper routing space. For a 16-bit DDR memory system, the high-word DDR3  
devices are omitted from the placement.  
x1  
y2  
DDR3  
Controller  
y2  
Three Devices  
SPRS91v_PCB_DDR3_04  
Figure 8-47. Placement Specifications  
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Table 8-39. Placement Specifications  
No.  
PARAMETER  
MIN  
MAX  
1700  
1800  
600  
UNIT  
Mils  
Mils  
Mils  
KOD31  
KOD34  
KOD35  
KOD36  
X1  
Y1  
Y2  
DDR3 keepout  
region(1)  
KOD37  
Clearance from non-  
DDR3 signal to  
DDR3 keepout  
region (2)(3)  
4
W
(1) DDR3 keepout region to encompass entire DDR3 routing area.  
(2) Non-DDR3 signals allowed within DDR3 keepout region provided they are separated from DDR3 routing layers by a ground plane.  
(3) If a device has more than one DDR controller, the signals from the other controller(s) are considered non-DDR3 and should be  
separated by this specification.  
8.9.2.7 DDR3 Keepout Region  
The region of the PCB used for DDR3 circuitry must be isolated from other signals. The DDR3 keepout  
region is defined for this purpose and is shown in Figure 8-48. The size of this region varies with the  
placement and DDR routing. Additional clearances required for the keepout region are shown in Table 8-  
39. Non-DDR3 signals should not be routed on the DDR signal layers within the DDR3 keepout region.  
Non-DDR3 signals may be routed in the region, provided they are routed on layers separated from the  
DDR signal layers by a ground layer. No breaks should be allowed in the reference ground layers in this  
region. In addition, the 1.5-V DDR3 power plane should cover the entire keepout region. Also note that the  
two signals from the DDR3 controller should be separated from each other by the specification in Table 8-  
39 (see KOD37).  
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DDR3 Keepout Region  
DDR3  
Controller  
Three Devices  
SPRS91v_PCB_DDR3_05  
Figure 8-48. DDR3 Keepout Region  
8.9.2.8 Bulk Bypass Capacitors  
Bulk bypass capacitors are required for moderate speed bypassing of the DDR3 and other circuitry.  
Table 8-40 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note  
that this table only covers the bypass needs of the DDR3 controllers and DDR3 devices. Additional bulk  
bypass capacitance may be needed for other circuitry.  
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Table 8-40. Bulk Bypass Capacitors  
NO.  
PARAMETER  
vdds_ddrx bulk bypass capacitor count(1)  
MIN  
1
MAX  
UNIT  
Devices  
μF  
1
2
vdds_ddrx bulk bypass total capacitance  
22  
(1) These devices should be placed near the devices they are bypassing, but preference should be given to the placement of the high  
speed (HS) bypass capacitors and DDR3 signal routing.  
8.9.2.9 High Speed Bypass Capacitors  
High speed (HS) bypass capacitors are critcal for proper DDR3 interface operation. It is particularly  
important to minimize the parasitic series inductance of the HS bypass capacitors, processor/DDR power,  
and processor/DDR ground connections. Table 8-41 contains the specification for the HS bypass  
capacitors as well as for the power connections on the PCB. Generally speaking, it is good to:  
1. Fit as many HS bypass capacitors as possible.  
2. Minimize the distance from the bypass cap to the pins/balls being bypassed.  
3. Use the smallest physical sized capacitors possible with the highest capacitance readily available.  
4. Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest  
hole size via possible.  
5. Minimize via sharing. Note the limites on via sharing shown in Table 8-41.  
Table 8-41. High Speed Bypass Capacitors  
NO.  
1
PARAMETER  
HS bypass capacitor package size(1)  
MIN  
TYP  
MAX  
0402  
400  
UNIT  
10 Mils  
Mils  
0201  
2
Distance, HS bypass capacitor to processor being bypassed(2)(3)(4)  
Processor HS bypass capacitor count per vdds_ddrx rail(12)  
Processor HS bypass capacitor total capacitance per vdds_ddrx rail(12)  
Number of connection vias for each device power/ground ball(5)  
Trace length from device power/ground ball to connection via(2)  
Distance, HS bypass capacitor to DDR device being bypassed(6)  
DDR3 device HS bypass capacitor count(7)  
3
See Table 8-3 and (11)  
See Table 8-3 and (11)  
Devices  
μF  
4
5
Vias  
6
35  
70  
Mils  
7
150  
Mils  
8
12  
0.85  
2
Devices  
μF  
9
DDR3 device HS bypass capacitor total capacitance(7)  
10 Number of connection vias for each HS capacitor(8)(9)  
11 Trace length from bypass capacitor connect to connection via(2)(9)  
12 Number of connection vias for each DDR3 device power/ground ball(10)  
13 Trace length from DDR3 device power/ground ball to connection via(2)(8)  
(1) LxW, 10-mil units, that is, a 0402 is a 40x20-mil surface-mount capacitor.  
(2) Closer/shorter is better.  
Vias  
35  
35  
100  
60  
Mils  
1
Vias  
Mils  
(3) Measured from the nearest processor power/ground ball to the center of the capacitor package.  
(4) Three of these capacitors should be located underneath the processor, between the cluster of DDR_1V5 balls and ground balls,  
between the DDR interfaces on the package.  
(5) See the Via Channel™ escape for the processor package.  
(6) Measured from the DDR3 device power/ground ball to the center of the capacitor package.  
(7) Per DDR3 device.  
(8) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of  
vias is permitted on the same side of the board.  
(9) An HS bypass capacitor may share a via with a DDR device mounted on the same side of the PCB. A wide trace should be used for the  
connection and the length from the capacitor pad to the DDR device pad should be less than 150 mils.  
(10) Up to a total of two pairs of DDR power/ground balls may share a via.  
(11) The capacitor recommendations in this data manual reflect only the needs of this processor. Please see the memory vendor’s  
guidelines for determining the appropriate decoupling capacitor arrangement for the memory device itself.  
(12) For more information, see Section 8.3, Core Power Domains.  
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8.9.2.9.1 Return Current Bypass Capacitors  
Use additional bypass capacitors if the return current reference plane changes due to DDR3 signals  
hopping from one signal layer to another. The bypass capacitor here provides a path for the return current  
to hop planes along with the signal. As many of these return current bypass capacitors should be used as  
possible. These are returns for signal current, the signal via size may be used for these capacitors.  
8.9.2.10 Net Classes  
Table 8-42 lists the clock net classes for the DDR3 interface. Table 8-43 lists the signal net classes, and  
associated clock net classes, for signals in the DDR3 interface. These net classes are used for the  
termination and routing rules that follow.  
Table 8-42. Clock Net Class Definitions  
CLOCK NET CLASS processor PIN NAMES  
CK  
ddrx_ck/ddrx_nck  
DQS0  
ddrx_dqs0 / ddrx_dqsn0  
ddrx_dqs1 / ddrx_dqsn1  
ddrx_dqs2 / ddrx_dqsn2  
ddrx_dqs3 / ddrx_dqsn3  
DQS1  
DQS2(1)  
DQS3(1)  
(1) Only used on 32-bit wide DDR3 memory systems.  
Table 8-43. Signal Net Class Definitions  
ASSOCIATED CLOCK  
SIGNAL NET CLASS  
PROCESSOR PIN NAMES  
NET CLASS  
ADDR_CTRL  
CK  
ddrx_ba[2:0], ddrx_a[15:0], ddrx_csnj, ddrx_casn, ddrx_rasn, ddrx_wen,  
ddrx_cke, ddrx_odti  
DQ0  
DQ1  
DQ2(1)  
DQ3(1)  
DQS0  
DQS1  
DQS2  
DQS3  
ddrx_d[7:0], ddrx_dqm0  
ddrx_d[15:8], ddrx_dqm1  
ddrx_d[23:16], ddrx_dqm2  
ddrx_d[31:24], ddrx_dqm3  
(1) Only used on 32-bit wide DDR3 memory systems.  
8.9.2.11 DDR3 Signal Termination  
Signal terminators are required for the CK and ADDR_CTRL net classes. The data lines are terminated by  
ODT and, thus, the PCB traces should be unterminated. Detailed termination specifications are covered in  
the routing rules in the following sections.  
8.9.2.12 VTT  
Like VREF, the nominal value of the VTT supply is half the DDR3 supply voltage. Unlike VREF, VTT is  
expected to source and sink current, specifically the termination current for the ADDR_CTRL net class  
Thevinen terminators. VTT is needed at the end of the address bus and it should be routed as a power  
sub-plane. VTT should be bypassed near the terminator resistors.  
8.9.2.13 CK and ADDR_CTRL Topologies and Routing Definition  
The CK and ADDR_CTRL net classes are routed similarly and are length matched to minimize skew  
between them. CK is a bit more complicated because it runs at a higher transition rate and is differential.  
The following subsections show the topology and routing for various DDR3 configurations for CK and  
ADDR_CTRL. The figures in the following subsections define the terms for the routing specification  
detailed in Table 8-44.  
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8.9.2.13.1 Three DDR3 Devices  
Three DDR3 devices are supported on the DDR EMIF consisting of two x16 DDR3 devices and one  
device for ECC, arranged as one bank (CS). These three devices may be mounted on a single side of the  
PCB, or may be mirrored in two pairs to save board space at a cost of increased routing complexity and  
parts on the backside of the PCB.  
8.9.2.13.1.1 CK and ADDR_CTRL Topologies, Three DDR3 Devices  
Figure 8-49 shows the topology of the CK net classes and Figure 8-50 shows the topology for the  
corresponding ADDR_CTRL net classes.  
DDR Differential CK Input Buffers  
+
+
+
Clock Parallel  
Terminator  
DDR_1V5  
Rcp  
A1  
A1  
A2  
A2  
A3  
A3  
A4  
A4  
AT  
AT  
Cac  
Processor  
Differential Clock  
Output Buffer  
+
0.1 µF  
Rcp  
Routed as Differential Pair  
SPRS91v_PCB_DDR3_06  
Figure 8-49. CK Topology for Three DDR3 Devices  
DDR Address and Control Input Buffers  
Address and Control  
Terminator  
Rtt  
Processor  
Address and Control  
Output Buffer  
A1  
A2  
A3  
A4  
AT  
Vtt  
SPRS91v_PCB_DDR3_07  
Figure 8-50. ADDR_CTRL Topology for Three DDR3 Devices  
8.9.2.13.1.2 CK and ADDR_CTRL Routing, Three DDR3 Devices  
Figure 8-51 shows the CK routing for three DDR3 devices placed on the same side of the PCB. Figure 8-  
52 shows the corresponding ADDR_CTRL routing.  
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DDR_1V5  
Cac  
Rcp  
Rcp  
A2  
A2  
A3  
A3  
A4  
A4  
AT  
AT  
0.1 µF  
=
SPRS91v_PCB_DDR3_08  
Figure 8-51. CK Routing for Three Single-Side DDR3 Devices  
Rtt  
A2  
A3  
A4  
AT  
Vtt  
=
SPRS91v_PCB_DDR3_09  
Figure 8-52. ADDR_CTRL Routing for Three Single-Side DDR3 Devices  
To save PCB space, the two DDR3 memories may be mounted as one mirrored pair at a cost of  
increased routing and assembly complexity. Figure 8-53 and Figure 8-54 show the routing for CK and  
ADDR_CTRL, respectively, for two DDR3 devices mirrored in a pair configuration.  
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DDR_1V5  
Cac  
Rcp  
Rcp  
A2  
A2  
A3  
A3  
AT  
AT  
0.1 µF  
=
SPRS91v_PCB_DDR3_10  
Figure 8-53. CK Routing for Two Mirrored DDR3 Devices  
Rtt  
A2  
A3  
AT  
Vtt  
=
SPRS91v_PCB_DDR3_11  
Figure 8-54. ADDR_CTRL Routing for Two Mirrored DDR3 Devices  
8.9.2.13.2 Two DDR3 Devices  
Two DDR3 devices are supported on the DDR EMIF consisting of two x8 DDR3 devices arranged as one  
bank (CS), 16 bits wide, or two x16 DDR3 devices arranged as one bank (CS), 32 bits wide. These two  
devices may be mounted on a single side of the PCB, or may be mirrored in a pair to save board space at  
a cost of increased routing complexity and parts on the backside of the PCB.  
8.9.2.13.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices  
Figure 8-55 shows the topology of the CK net classes and Figure 8-56 shows the topology for the  
corresponding ADDR_CTRL net classes.  
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DDR Differential CK Input Buffers  
+
+
Clock Parallel  
Terminator  
DDR_1V5  
Rcp  
A1  
A1  
A2  
A2  
A3  
A3  
AT  
Cac  
Processor  
+
Differential Clock  
Output Buffer  
0.1 µF  
Rcp  
AT  
Routed as Differential Pair  
SPRS91v_PCB_DDR3_12  
Figure 8-55. CK Topology for Two DDR3 Devices  
DDR Address and Control Input Buffers  
Address and Control  
Terminator  
Rtt  
Processor  
Address and Control  
Output Buffer  
A1  
A2  
A3  
AT  
Vtt  
SPRS91v_PCB_DDR3_13  
Figure 8-56. ADDR_CTRL Topology for Two DDR3 Devices  
8.9.2.13.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices  
Figure 8-57 shows the CK routing for two DDR3 devices placed on the same side of the PCB. Figure 8-58  
shows the corresponding ADDR_CTRL routing.  
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DDR_1V5  
Cac  
Rcp  
Rcp  
A2  
A2  
A3  
A3  
AT  
AT  
0.1 µF  
=
SPRS91v_PCB_DDR3_14  
Figure 8-57. CK Routing for Two Single-Side DDR3 Devices  
Rtt  
A2  
A3  
AT  
Vtt  
=
SPRS91v_PCB_DDR3_15  
Figure 8-58. ADDR_CTRL Routing for Two Single-Side DDR3 Devices  
To save PCB space, the two DDR3 memories may be mounted as a mirrored pair at a cost of increased  
routing and assembly complexity. Figure 8-59 and Figure 8-60 show the routing for CK and ADDR_CTRL,  
respectively, for two DDR3 devices mirrored in a single-pair configuration.  
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DDR_1V5  
Cac  
Rcp  
Rcp  
A2  
A2  
A3  
A3  
AT  
AT  
0.1 µF  
=
SPRS91v_PCB_DDR3_16  
Figure 8-59. CK Routing for Two Mirrored DDR3 Devices  
Rtt  
A2  
A3  
AT  
Vtt  
=
SPRS91v_PCB_DDR3_17  
Figure 8-60. ADDR_CTRL Routing for Two Mirrored DDR3 Devices  
8.9.2.13.3 One DDR3 Device  
A single DDR3 device is supported on the DDR EMIF consisting of one x16 DDR3 device arranged as  
one bank (CS), 16 bits wide.  
8.9.2.13.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device  
Figure 8-61 shows the topology of the CK net classes and Figure 8-62 shows the topology for the  
corresponding ADDR_CTRL net classes.  
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DDR Differential CK Input Buffer  
+
Clock Parallel  
Terminator  
DDR_1V5  
Rcp  
A1  
A1  
A2  
A2  
AT  
AT  
Cac  
Processor  
Differential Clock  
Output Buffer  
+
0.1 µF  
Rcp  
Routed as Differential Pair  
SPRS91v_PCB_DDR3_18  
Figure 8-61. CK Topology for One DDR3 Device  
DDR Address and Control Input Buffers  
Address and Control  
Terminator  
Rtt  
Processor  
Address and Control  
Output Buffer  
A1  
A2  
AT  
Vtt  
SPRS91v_PCB_DDR3_19  
Figure 8-62. ADDR_CTRL Topology for One DDR3 Device  
8.9.2.13.3.2 CK and ADDR/CTRL Routing, One DDR3 Device  
Figure 8-63 shows the CK routing for one DDR3 device placed on the same side of the PCB. Figure 8-64  
shows the corresponding ADDR_CTRL routing.  
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DDR_1V5  
Cac  
Rcp  
Rcp  
A2  
A2  
AT  
AT  
0.1 µF  
=
SPRS91v_PCB_DDR3_20  
Figure 8-63. CK Routing for One DDR3 Device  
Rtt  
A2  
AT  
Vtt  
=
SPRS91v_PCB_DDR3_21  
Figure 8-64. ADDR_CTRL Routing for One DDR3 Device  
8.9.2.14 Data Topologies and Routing Definition  
No matter the number of DDR3 devices used, the data line topology is always point to point, so its  
definition is simple.  
Care should be taken to minimize layer transitions during routing. If a layer transition is necessary, it is  
better to transition to a layer using the same reference plane. If this cannot be accommodated, ensure  
there are nearby ground vias to allow the return currents to transition between reference planes if both  
reference planes are ground or vdds_ddr. Ensure there are nearby bypass capacitors to allow the return  
currents to transition between reference planes if one of the reference planes is ground. The goal is to  
minimize the size of the return current loops.  
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8.9.2.14.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices  
DQS lines are point-to-point differential, and DQ/DM lines are point-to-point singled ended. Figure 8-65  
and Figure 8-66 show these topologies.  
Processor  
DQS  
DDR  
DQSn+  
DQSn-  
DQS  
IO Buffer  
IO Buffer  
Routed Differentially  
n = 0, 1, 2, 3  
SPRS91v_PCB_DDR3_22  
Figure 8-65. DQS Topology  
Processor  
DQ and DM  
IO Buffer  
DDR  
Dn  
DQ and DM  
IO Buffer  
n = 0, 1, 2, 3  
SPRS91v_PCB_DDR3_23  
Figure 8-66. DQ/DM Topology  
8.9.2.14.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices  
Figure 8-67 and Figure 8-68 show the DQS and DQ/DM routing.  
DQS  
DQSn+  
DQSn-  
Routed Differentially  
n = 0, 1, 2  
SPRS91v_PCB_DDR3_24  
Figure 8-67. DQS Routing With Any Number of Allowed DDR3 Devices  
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DQ and DM  
Dn  
n = 0, 1, 2  
SPRS91v_PCB_DDR3_25  
Figure 8-68. DQ/DM Routing With Any Number of Allowed DDR3 Devices  
8.9.2.15 Routing Specification  
8.9.2.15.1 CK and ADDR_CTRL Routing Specification  
Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this  
skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter  
traces up to the length of the longest net in the net class and its associated clock. A metric to establish  
this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the  
length between the points when connecting them only with horizontal or vertical segments. A reasonable  
trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address  
Control Longest Manhattan distance.  
Given the clock and address pin locations on the processor and the DDR3 memories, the maximum  
possible Manhattan distance can be determined given the placement. Figure 8-69 and Figure 8-70 show  
this distance for three loads and two loads, respectively. It is from this distance that the specifications on  
the lengths of the transmission lines for the address bus are determined. CACLM is determined similarly  
for other address bus configurations; that is, it is based on the longest net of the CK/ADDR_CTRL net  
class. For CK and ADDR_CTRL routing, these specifications are contained in Table 8-44.  
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A8(A)  
CACLMY  
CACLMX  
A8(A)  
A8(A)  
A8(A)  
Rtt  
A2  
A3  
A4  
AT  
Vtt  
=
SPRS91v_PCB_DDR3_26  
A. It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3  
memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that  
satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control.  
The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this  
length calculation. Non-included lengths are grayed out in the figure.  
Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.  
The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.  
Figure 8-69. CACLM for Three Address Loads on One Side of PCB  
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A8(A)  
CACLMY  
CACLMX  
A8(A)  
A8(A)  
Rtt  
A2  
A3  
AT  
Vtt  
=
SPRS91v_PCB_DDR3_27  
A. It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3  
memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that  
satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control.  
The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this  
length calculation. Non-included lengths are grayed out in the figure.  
Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.  
The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.  
Figure 8-70. CACLM for Two Address Loads on One Side of PCB  
Table 8-44. CK and ADDR_CTRL Routing Specification(2)(3)  
NO.  
PARAMETER  
MIN  
TYP  
MAX  
500(1)  
29  
UNIT  
ps  
CARS31  
CARS32  
CARS33  
CARS34  
CARS35  
CARS36  
CARS37  
CARS38  
CARS39  
CARS310  
CARS311  
CARS312  
CARS313  
CARS314  
CARS315  
CARS316  
CARS317  
CARS318  
CARS319  
CARS320  
A1+A2 length  
A1+A2 skew  
A3 length  
A3 skew(4)  
A3 skew(5)  
A4 length  
ps  
125  
6
ps  
ps  
6
ps  
125  
6
17(1)  
14(1)  
12  
ps  
A4 skew  
ps  
AS length  
5
1.3  
5
ps  
AS skew  
ps  
AS+/AS- length  
AS+/AS- skew  
AT length(6)  
AT skew(7)  
AT skew(8)  
ps  
1
ps  
75  
14  
ps  
ps  
1
ps  
CK/ADDR_CTRL trace length  
1020  
3(1)  
1(15)  
ps  
Vias per trace  
vias  
vias  
Via count difference  
Center-to-center CK to other DDR3 trace spacing(9)  
Center-to-center ADDR_CTRL to other DDR3 trace spacing(9)(10)  
4w  
4w  
3w  
Center-to-center ADDR_CTRL to other ADDR_CTRL trace  
spacing(9)  
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UNIT  
Table 8-44. CK and ADDR_CTRL Routing Specification(2)(3) (continued)  
NO.  
PARAMETER  
CK center-to-center spacing(11)(12)  
CK spacing to other net(9)  
Rcp(13)  
MIN  
TYP  
MAX  
CARS321  
CARS322  
CARS323  
CARS324  
4w  
Zo-1  
Zo-5  
Zo  
Zo  
Zo+1  
Zo+5  
Ω
Ω
Rtt(13)(14)  
(1) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of  
rise time and fall time confirms desired operation.  
(2) The use of vias should be minimized.  
(3) Additional bypass capacitors are required when using the DDR_1V5 plane as the reference plane to allow the return current to jump  
between the DDR_1V5 plane and the ground plane when the net class switches layers at a via.  
(4) Non-mirrored configuration (all DDR3 memories on same side of PCB).  
(5) Mirrored configuration (one DDR3 device on top of the board and one DDR3 device on the bottom).  
(6) While this length can be increased for convenience, its length should be minimized.  
(7) ADDR_CTRL net class only (not CK net class). Minimizing this skew is recommended, but not required.  
(8) CK net class only.  
(9) Center-to-center spacing is allowed to fall to minimum (2w) for up to 1250 mils of routed length.  
(10) The ADDR_CTRL net class of the other DDR EMIF is considered other DDR3 trace spacing.  
(11) CK spacing set to ensure proper differential impedance.  
(12) The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking,  
center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended  
impedance, Zo.  
(13) Source termination (series resistor at driver) is specifically not allowed.  
(14) Termination values should be uniform across the net class.  
(15) Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal  
propagation through vias – has been applied to ensure all segment skew maximums are not exceeded.  
8.9.2.15.2 DQS and DQ Routing Specification  
Skew within the DQS and DQ/DM net classes directly reduces setup and hold margin and thus this skew  
must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces  
up to the length of the longest net in the net class and its associated clock. As with CK and ADDR_CTRL,  
a reasonable trace route length is to within a percentage of its Manhattan distance. DQLMn is defined as  
DQ Longest Manhattan distance n, where n is the byte number. For a 32-bit interface, there are three  
DQLMs, DQLM0-DQLM2. Likewise, for a 16-bit interface, there are two DQLMs, DQLM0-DQLM1.  
NOTE  
It is not required, nor is it recommended, to match the lengths across all bytes. Length  
matching is only required within each byte.  
Given the DQS and DQ/DM pin locations on the processor and the DDR3 memories, the maximum  
possible Manhattan distance can be determined given the placement. Figure 8-71 shows this distance for  
four loads. It is from this distance that the specifications on the lengths of the transmission lines for the  
data bus are determined. For DQS and DQ/DM routing, these specifications are contained in Table 8-45.  
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DQLMX0  
DB0  
DQ[0:7]/DM0/DQS0  
DQ[8:15]/DM1/DQS1  
DB1  
DQLMX1  
DQ[16:23]/DM2/DQS2  
DB2  
DQLMY0  
DQLMX2  
DQLMY1  
DQLMY2  
2
1
0
DB0 - DB2 represent data bytes 0 - 2.  
SPRS91v_PCB_DDR3_28  
There are three DQLMs, one for each byte (32-bit interface). Each DQLM is the longest Manhattan distance of the  
byte; therefore:  
DQLM0 = DQLMX0 + DQLMY0  
DQLM1 = DQLMX1 + DQLMY1  
DQLM2 = DQLMX2 + DQLMY2  
Figure 8-71. DQLM for Any Number of Allowed DDR3 Devices  
Table 8-45. Data Routing Specification(2)  
NO.  
PARAMETER  
MIN  
TYP  
MAX  
340  
340  
340  
5
UNIT  
ps  
DRS31  
DRS32  
DRS33  
DRS35  
DRS36  
DRS37  
DRS38  
DRS39  
DRS310  
DRS311  
DRS312  
DRS313  
DB0 length  
DB1 length  
ps  
DB2 length  
DBn skew(3)  
ps  
ps  
DQSn+ to DQSn- skew  
DQSn to DBn skew(3)(4)  
Vias per trace  
1
ps  
5(10)  
2(1)  
0(10)  
ps  
vias  
vias  
w(5)  
w(5)  
Via count difference  
Center-to-center DBn to other DDR3 trace spacing(6)  
Center-to-center DBn to other DBn trace spacing(7)  
DQSn center-to-center spacing(8)(9)  
4
3
DQSn center-to-center spacing to other net  
4
w(5)  
(1) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of  
rise time and fall time confirms desired operation.  
(2) External termination disallowed. Data termination should use built-in ODT functionality.  
(3) Length matching is only done within a byte. Length matching across bytes is neither required nor recommended.  
(4) Each DQS pair is length matched to its associated byte.  
(5) Center-to-center spacing is allowed to fall to minimum (2w) for up to 1250 mils of routed length.  
(6) Other DDR3 trace spacing means other DDR3 net classes not within the byte.  
(7) This applies to spacing within the net classes of a byte.  
(8) DQS pair spacing is set to ensure proper differential impedance.  
(9) The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking,  
center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended  
impedance, Zo.  
(10) Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal  
propagation through vias – has been applied to ensure DBn skew and DQSn to DBn skew maximums are not exceeded.  
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8.10 CVIDEO/SD-DAC Guidelines and Electrical Data/Timing  
The device's analog video CVIDEO/SD-DAC TV analog composite output can be operate in one of two  
modes: Normal mode and TVOUT Bypass mode. In Normal mode, the device’s internal video amplifier is  
used. In TVOUT Bypass mode, the internal video amplifier is bypassed and an external amplifier is  
required.  
Figure 8-72 shows a typical circuit that permits connecting the analog video output from the device to  
standard 75-Ω impedance video systems in Normal mode.  
Reconstruction  
Filter(A)  
~9.5 MHz  
cvideo_tvout  
(B)  
CAC  
ROUT  
cvideo_vfb  
A. Reconstruction Filter (optional)  
B. AC coupling capacitor (optional)  
Figure 8-72. TV Output (Normal Mode)  
Figure 8-73 shows a typical circuit that permits connecting the analog video output from the device to  
standard 75-Ω impedance video systems in TVOUT Bypass mode.  
75 W  
Reconstruction  
Filter(A)  
~9.5 MHz  
Amplifier  
3.7 V/V  
cvideo_vfb  
(B)  
CAC  
RLOAD  
A. Reconstruction Filter (optional). Note: An amplifier with an integrated reconstruction filter can alternatively be used  
instead of a discrete reconstruction filter.  
B. AC coupling capacitor (optional)  
Figure 8-73. TV Output (TVOUT Bypass Mode)  
During board design, the onboard traces and parasitics must be matched for the channel. The video DAC  
output pins (cvideo_tvout / cvideo_vfb) are very high-frequency analog signals and must be routed with  
extreme care. As a result, the paths of these signals must be as short as possible, and as isolated as  
possible from other interfering signals. In TVOUT Bypass mode, the load resistor and amplifier/buffer  
should be placed as close as possible to the cvideo_vfb pin. Other layout guidelines include:  
Take special care to bypass the vdda_dac power supply pin with a capacitor.  
In TVOUT Bypass mode, place the RLOAD resistor as close as possible to the Reconstruction Filter  
and Amplifier. In addition, place the 75-Ω resistor as close as possible (< 0.5 inch) to the  
Amplifier/buffer output pin. To maintain a high-quality video signal, the onboard traces after the 75-Ω  
resistor should have a characteristic impedance of 75 Ω (± 20%).  
In Normal mode,cvideo_vfb is the most sensitive pin in the TV out system. The ROUT resistor should  
be placed as close as possible to the device pins. To maintain a high-quality video signal, the onboard  
traces leading to the cvideo_tvout pin should have a characteristic impedance of 75 Ω (± 20%) starting  
from the closest possible place to the device pin output.  
Minimize input trace lengths to the device to reduce parasitic capacitance.  
Include solid ground return paths.  
Match trace lengths as close as possible within a video format group.  
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Table 8-46 and Table 8-47 present the Static and Dynamic CVIDEO / SD-DAC TV analog composite  
output specifications  
Table 8-46. Static CVIDEO/SD-DAC Specifications  
PARAMETER  
TEST CONDITIONS  
MIN  
4653  
9900  
2673  
TYP  
4700  
10000  
2700  
MAX  
4747  
10100  
2727  
UNIT  
Ω
Reference Current Setting Resistor Normal Mode  
(RSET  
)
TVOUT Bypass Mode  
Normal Mode  
Ω
Output resistor between  
Ω
cvideo_tvout and cvideo_vfb pins  
TVOUT Bypass Mode  
N/A  
(ROUT  
)
Load Resistor (RLOAD  
)
Normal Mode  
75-Ω Inside the Display  
TVOUT Bypass Mode  
Normal Mode  
1485  
220  
1500  
1515  
Ω
AC-Coupling Capacitor (Optional)  
[CAC  
µF  
]
TVOUT Bypass Mode  
Normal Mode  
See External Amplifier Specification  
Total Capacitance from  
cvideo_tvout to vssa_dac  
300  
pF  
TVOUT Bypass Mode  
N/A  
Resolution  
10  
Bits  
LSB  
LSB  
LSB  
LSB  
V
Integral Non-Linearity (INL), Best  
Fit  
Normal Mode  
-4  
-1  
4
TVOUT Bypass Mode  
Normal Mode  
1
Differential Non-Linearity (DNL)  
-2.5  
-1  
2.5  
1
TVOUT Bypass Mode  
Normal Mode (RLOAD = 75 Ω)  
Full-Scale Output Voltage  
1.3  
TVOUT Bypass Mode (RLOAD  
1.5 kΩ)  
=
0.7  
V
Full-Scale Output Current  
Gain Error  
Normal Mode  
N/A  
TVOUT Bypass Mode  
470  
uA  
Normal Mode (Composite) and  
TVOUT Bypass Mode  
-10  
-20  
10  
%FS  
%FS  
Normal Mode (S-Video)  
20  
Gain Mismatch (Luma-to-Chroma)  
Output Impedance  
Normal Mode (Composite)  
Normal Mode (S-Video)  
N/A  
-10  
10  
%
Looking into cvideo_tvout nodes  
75  
Ω
Table 8-47. Dynamic CVIDEO/SD-DAC Specifications  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
54  
6
MAX  
UNIT  
MHz  
MHz  
Output Update Rate (FCLK  
)
60  
Signal Bandwidth  
3 dB  
Spurious-Free Dynamic Range  
(SFDR) within bandwidth  
FCLK = 54 MHz, FOUT = 1 MHz  
FCLK = 54 MHz, FOUT = 1 MHz  
50  
54  
6
dBc  
dB  
Signal-to-Noise Ration (SNR)  
Normal Mode, 100 mVpp @ 6  
MHz on vdda_dac  
Power Supply Rejection (PSR)  
dB  
TVOUT Bypass Mode, 100  
mVpp @ 6 MHz on vdda_dac  
20  
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9 Device and Documentation Support  
TI offers an extensive line of development tools, including tools to evaluate the performance of the  
processors, generate code, develop algorithm implementations, and fully integrate and debug software  
and hardware modules are listed below.  
9.1 Device Nomenclature  
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all  
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix)  
(for example, TDA3x). Texas Instruments recommends two of three possible prefix designators for its  
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development  
from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).  
Device development evolutionary flow:  
X
Experimental device that is not necessarily representative of the final device's electrical  
specifications and may not use production assembly flow.  
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet  
final electrical specifications.  
null  
Production version of the silicon die that is fully qualified.  
Support tool development evolutionary flow:  
TMDX  
Development-support product that has not yet completed Texas Instruments internal  
qualification testing.  
TMDS  
Fully-qualified development-support product.  
X and P devices and TMDX development-support tools are shipped against the following disclaimer:  
"Developmental product is intended for internal evaluation purposes."  
Production devices and TMDS development-support tools have been characterized fully, and the quality  
and reliability of the device have been demonstrated fully. TI's standard warranty applies.  
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production  
devices. Texas Instruments recommends that these devices not be used in any production system  
because their expected end-use failure rate still is undefined. Only qualified production devices are to be  
used.  
For orderable part numbers of TDA3x devices in the ABF package type, see the Package Option  
Addendum of this document, the TI website (ti.com), or contact your TI sales representative.  
For additional description of the device nomenclature markings on the die, see the TDA3x SoC for  
Advanced Driver Assistance Systems (ADAS) Silicon Revision 2.0, 1.0A, 1.0.  
9.1.1 Standard Package Symbolization  
NOTE  
Some devices may have a cosmetic circular marking visible on the top of the device package  
which results from the production test process. In addition, some devices may also show a  
color variation in the package substrate which results from the substrate manufacturer.  
These differences are cosmetic only with no reliability impact.  
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Figure 9-1. Printed Device Reference  
9.1.2 Device Naming Convention  
Table 9-1. Nomenclature Description  
FIELD  
FIELD DESCRIPTION  
VALUES  
DESCRIPTION  
PARAMETER  
MARKING  
ORDERABLE  
a
Device evolution stage  
X
Contact TI  
Prototype  
P
Preproduction (production test flow, no  
reliability data)  
BLANK  
Production  
(2)  
TDA3  
Base production part number  
Device Tier  
TDA3  
ADAS 3rd Generation Family  
t
S
Super  
M
Mid  
L
Low  
I
Device Identity  
Device Speed  
A
Scene Analysis  
Scene Viewing  
Dual-DSP Scene Analysis  
Radar  
V
D
R
X
ADAS Superset  
z
A
Indicates the speed grade for each of the  
cores in the device. For more information  
see , Device Comparison Table and Table 5-  
1, Speed Grade Maximum Frequency  
B
D
R
S
r
Device revision  
Device type  
BLANK  
SR 1.0  
A
SR 1.0A  
B
SR 2.0  
Y
BLANK  
Standard devices  
GP Prime Emulation (E) devices  
JTAG lock & random key devices  
E
J
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Table 9-1. Nomenclature Description (continued)  
FIELD  
FIELD DESCRIPTION  
VALUES  
DESCRIPTION  
PARAMETER  
MARKING  
ORDERABLE  
D
GP Prime prototype devices with TI  
Development keys (D)  
S
n
GP Prime devices  
GP Prime devices with customer key  
(n=1-9, Z...)  
C
CAN2 designator  
BLANK  
F
Standard CAN  
CAN-FD  
PPP  
c
Package designator  
Carrier designator  
ABF  
ABF FCBGA-N367 (15mm x 15mm) Package  
N/A  
N/A  
BLANK  
R
Tray  
Tape & Reel  
Q1  
Automotive Designator  
BLANK  
Q1  
Does not meet automotive qualification  
Meets Q100 equal requirements, with  
exceptions as specified in DM.  
XXXXXXX  
YYY  
ZZZ  
As marked  
As marked  
As marked  
As marked  
As marked  
N/A  
N/A  
N/A  
N/A  
N/A  
Lot Trace Code  
Production Code, For TI use only  
Production Code, For TI use only  
Pin one designator  
O
G1  
ECAT—Green package designator  
(1) To designate the stages in the product development cycle, TI assigns prefixes to the part numbers. These prefixes represent  
evolutionary stages of product development from engineering prototypes through fully qualified production devices.  
Prototype devices are shipped against the following disclaimer:  
“This product is still in development and is intended for internal evaluation purposes.”  
Notwithstanding any provision to the contrary, TI makes no warranty expressed, implied, or statutory, including any implied warranty of  
merchantability of fitness for a specific purpose, of this device.  
(2) XTDA3SX base part number with X speed grade indicator is the part number for the superset device. Software should constrain the  
features and speed used to match the intended production device.  
NOTE  
BLANK in the symbol or part number is collapsed so there are no gaps between characters.  
9.2 Tools and Software  
The following products support development for TDA3x platforms:  
Design Kits and Evaluation Modules  
TDA3X Evaluation Module The TDA3x evaluation module (EVM) is an evaluation platform designed to  
speed up development efforts and reduce time-to-market for ADAS applications. The EVM also integrates  
a host of peripherals including multicamera interfaces (both parallel and serial) for LVDS-based surround  
view systems, displays, CAN, and GigB Ethernet AVB. The EVM also integrates key peripherals such as  
Ethernet, FPD-Link and HDMI, while provides interfaces for popular imagers.  
Software  
Processor SDK for TDAx ADAS SoCs - Linux and TI-RTOS Support Processor SDK-Vision (Vision SDK)  
and Processor SDK-Radar (Radar SDK) are multi-processor software development kits for TDAx  
processors. The software framework allows users to create different ADAS application data flows involving  
radar capture, radar processing, video capture, video pre-processing, video analytics algorithms and video  
display. This release also integrates Processor SDK Linux to enable Automotive ADAS features and  
demos which needs Linux and GPU. The SDK has foundational drivers, compute & vision kernels for EVE  
and DSP. It also has demo use cases using TI sample algorithms which exercises different CPUs and HW  
accelerators in the ADAS SoC and shows customers how to effectively use different sub-systems.  
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SPRS964H JUNE 2016REVISED FEBRUARY 2020  
Development Tools  
Clock Tree Tool for Sitara, Automotive, Vision Analytics, & Digital Signal Processors The Clock Tree Tool  
(CTT) for Sitara™ Arm®, Automotive, and Digital Signal Processors is an interactive clock tree  
configuration software that provides information about the clocks and modules in these TI devices. It  
allows the user to: Visualize the device clock tree. Interact with clock tree elements and view the effect on  
PRCM registers. Interact with the PRCM registers and view the effect on the device clock tree. View a  
trace of all the device registers affected by the user interaction with clock tree.  
Pin mux tool The Pin MUX Utility is a software tool which provides a Graphical User Interface for  
configuring pin multiplexing settings, resolving conflicts and specifying I/O cell characteristics for TI MPUs.  
Results are output as C header/code files that can be imported into software development kits (SDKs) or  
used to configure customer's custom software. Version 4 of the Pin Mux utility adds the capability of  
automatically selecting a mux configuration that satisfies the entered requirements.  
XDS110 JTAG Debug Probe The Texas Instruments XDS110 is a new class of debug probe (emulator) for  
TI embedded processors. The XDS110 replaces the XDS100 family while supporting a wider variety of  
standards (IEEE1149.1, IEEE1149.7, SWD) in a single pod. Also, all XDS debug probes support Core and  
System Trace in all Arm and DSP processors that feature an Embedded Trace Buffer (ETB).  
The Texas Instruments XDS110 connects to the target board via a TI 20-pin connector (with multiple  
adapters for TI 14-pin and, Arm 10-pin and Arm 20-pin) and to the host PC via USB2.0 High Speed  
(480Mbps). It also features two additional connections: the Auxiliary 14-pin port connector that enables  
EnergyTrace™, a full duplex UART port and four General-Purpose I/Os, and the Expansion 30-pin  
connector to connect the XDS110 EnergyTrace HDR add-on.  
Models  
TDA3x BSDL Model BSDL Model  
TDA3x IBIS Model IBIS Model  
TDA3x Thermal Model Thermal Model  
For a complete listing of development-support tools for the processor platform, visit the Texas Instruments  
website at ti.com. For information on pricing and availability, contact the nearest TI field sales office or  
authorized distributor.  
Copyright © 2016–2020, Texas Instruments Incorporated  
Device and Documentation Support  
261  
Submit Documentation Feedback  
Product Folder Links: TDA3MV TDA3MA TDA3MD TDA3LX TDA3LA  
TDA3MV, TDA3MA, TDA3MD  
TDA3LX, TDA3LA  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
www.ti.com  
9.3 Documentation Support  
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the  
upper right corner, click on Alert me to register and receive a weekly digest of any product information that  
has changed. For change details, review the revision history included in any revised document.  
The following documents describe the TDA3x devices.  
Technical Reference Manual  
TDA3x SoC for Advanced Driver Assistance Systems (ADAS) Silicon Revision 2.0, 1.0A, 1.0 Technical  
Reference Manual Details the integration, the environment, the functional description, and the  
programming models for each peripheral and subsystem in the TDA3 family of devices.  
Errata  
TDA3x SoC for Advanced Driver Assistance Systems (ADAS) Silicon Revision 2.0, 1.0A, 1.0 Silicon Errata  
Describes the known exceptions to the functional specifications for the device.  
9.4 Related Links  
The table below lists quick access links. Categories include technical documents, support and community  
resources, tools and software, and quick access to order now.  
Table 9-2. Related Links  
TECHNICAL  
DOCUMENTS  
TOOLS &  
SOFTWARE  
SUPPORT &  
COMMUNITY  
PARTS  
PRODUCT FOLDER  
SAMPLE & BUY  
TDA3MV  
TDA3MA  
TDA3MD  
TDA3LX  
TDA3LA  
Click here  
Click here  
Click here  
Click here  
Click here  
Click here  
Click here  
Click here  
Click here  
Click here  
Click here  
Click here  
Click here  
Click here  
Click here  
Click here  
Click here  
Click here  
Click here  
Click here  
Click here  
Click here  
Click here  
Click here  
Click here  
9.5 Support Resources  
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help —  
straight from the experts. Search existing answers or ask your own question to get the quick design help  
you need.  
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications  
and do not necessarily reflect TI's views; see TI's Terms of Use.  
9.6 Trademarks  
E2E is a trademark of Texas Instruments.  
Arm, Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.  
JTAG is a registered trademark of JTAG Technologies B.V. .  
MIPI is a registered trademark of MIPI Alliance, Inc.  
I2C is a trademark of NXP Semiconductors.  
All other trademarks are the property of their respective owners.  
9.7 Electrostatic Discharge Caution  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with  
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more  
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.  
9.8 Glossary  
TI Glossary This glossary lists and explains terms, acronyms, and definitions.  
262  
Device and Documentation Support  
Copyright © 2016–2020, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Links: TDA3MV TDA3MA TDA3MD TDA3LX TDA3LA  
TDA3MV, TDA3MA, TDA3MD  
TDA3LX, TDA3LA  
www.ti.com  
SPRS964H JUNE 2016REVISED FEBRUARY 2020  
10 Mechanical, Packaging, and Orderable Information  
10.1 Packaging Information  
The following pages include mechanical, packaging, and orderable information. This information is the  
most current data available for the designated devices. This data is subject to change without notice and  
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.  
Copyright © 2016–2020, Texas Instruments Incorporated  
Mechanical, Packaging, and Orderable Information  
Submit Documentation Feedback  
Product Folder Links: TDA3MV TDA3MA TDA3MD TDA3LX TDA3LA  
263  
PACKAGE OPTION ADDENDUM  
www.ti.com  
13-Apr-2021  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
TDA3LABBABFQ1  
ACTIVE  
FCBGA  
FCBGA  
FCBGA  
FCBGA  
FCBGA  
FCBGA  
FCBGA  
FCBGA  
FCBGA  
ABF  
367  
367  
367  
367  
367  
367  
367  
367  
367  
90  
RoHS & Green  
RoHS & Green  
RoHS & Green  
RoHS & Green  
RoHS & Green  
RoHS & Green  
RoHS & Green  
RoHS & Green  
RoHS & Green  
SNAGCU  
Level-3-250C-168 HR  
Level-3-250C-168 HR  
Level-3-250C-168 HR  
Level-3-250C-168 HR  
Level-3-250C-168 HR  
Level-3-250C-168 HR  
Level-3-250C-168 HR  
Level-3-250C-168 HR  
Level-3-250C-168 HR  
-40 to 125  
TDA3LABBABFQ1  
TDA  
775  
775 ABF G1  
TDA3LABBABFRQ1  
TDA3LADBABFQ1  
TDA3LADBABFRQ1  
TDA3LADBJFABFQ1  
TDA3LADBJFABFRQ1  
TDA3LXBBABFQ1  
TDA3LXBBABFRQ1  
TDA3LXRBFABFQ1  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ABF  
ABF  
ABF  
ABF  
ABF  
ABF  
ABF  
ABF  
750  
90  
Call TI | SNAGCU  
SNAGCU  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
TDA3LABBABFQ1  
TDA  
775  
775 ABF G1  
TDA3LADBABFQ1  
TDA  
775  
775 ABF G1  
750  
90  
SNAGCU  
TDA3LADBABFQ1  
TDA  
775  
775 ABF G1  
SNAGCU  
TDA3LADBJFABFQ1  
TDA  
775  
775 ABF G1  
750  
90  
SNAGCU  
TDA3LADBJFABFQ1  
TDA  
775  
775 ABF G1  
SNAGCU  
TDA3LXBBABFQ1  
TDA  
775  
775 ABF G1  
750  
90  
SNAGCU  
TDA3LXBBABFQ1  
TDA  
775  
775 ABF G1  
SNAGCU  
TDA3LXRBFABFQ1  
TDA  
775  
775 ABF G1  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
13-Apr-2021  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
TDA3LXRBFABFRQ1  
TDA3MADBABFQ1  
TDA3MADBABFRQ1  
TDA3MADBFABFQ1  
TDA3MADBFABFRQ1  
ACTIVE  
FCBGA  
FCBGA  
FCBGA  
FCBGA  
FCBGA  
ABF  
367  
367  
367  
367  
367  
750  
RoHS & Green  
RoHS & Green  
RoHS & Green  
RoHS & Green  
RoHS & Green  
SNAGCU  
Level-3-250C-168 HR  
Level-3-250C-168 HR  
Level-3-250C-168 HR  
Level-3-250C-168 HR  
Level-3-250C-168 HR  
-40 to 125  
TDA3LXRBFABFQ1  
TDA  
775  
775 ABF G1  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ABF  
ABF  
ABF  
ABF  
90  
750  
90  
Call TI | SNAGCU  
Call TI | SNAGCU  
Call TI | SNAGCU  
Call TI | SNAGCU  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
TDA3MADBABFQ1  
TDA  
775  
775 ABF  
TDA3MADBABFQ1  
TDA  
775  
775 ABF  
TDA3MADBFABFQ1  
TDA  
775  
775 ABF  
750  
TDA3MADBFABFQ1  
TDA  
775  
775 ABF  
TDA3MASBABFQ1  
TDA3MASBABFRQ1  
TDA3MDDBABFQ1  
ACTIVE  
ACTIVE  
ACTIVE  
FCBGA  
FCBGA  
FCBGA  
ABF  
ABF  
ABF  
367  
367  
367  
90  
750  
90  
Non-RoHS &  
Non-Green  
Call TI  
Call TI  
Call TI  
Call TI  
-40 to 125  
-40 to 125  
-40 to 125  
Non-RoHS &  
Non-Green  
RoHS & Green  
RoHS & Green  
RoHS & Green  
RoHS & Green  
SNAGCU  
Level-3-250C-168 HR  
TDA3MDDBABFQ1  
TDA  
775  
775 ABF G1  
TDA3MDDBABFRQ1  
TDA3MVDBABFQ1  
TDA3MVDBABFRQ1  
ACTIVE  
ACTIVE  
ACTIVE  
FCBGA  
FCBGA  
FCBGA  
ABF  
ABF  
ABF  
367  
367  
367  
750  
90  
SNAGCU  
SNAGCU  
SNAGCU  
Level-3-250C-168 HR  
Level-3-250C-168 HR  
Level-3-250C-168 HR  
-40 to 125  
-40 to 125  
-40 to 125  
TDA3MDDBABFQ1  
TDA  
775  
775 ABF G1  
TDA3MVDBABFQ1  
TDA  
775  
775 ABF G1  
750  
TDA3MVDBABFQ1  
TDA  
Addendum-Page 2  
PACKAGE OPTION ADDENDUM  
www.ti.com  
13-Apr-2021  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
775  
775 ABF G1  
TDA3MVRBFABFQ1  
TDA3MVRBFABFRQ1  
ACTIVE  
ACTIVE  
FCBGA  
FCBGA  
ABF  
367  
367  
90  
RoHS & Green  
RoHS & Green  
Call TI | SNAGCU  
Level-3-250C-168 HR  
Level-3-250C-168 HR  
-40 to 125  
-40 to 125  
TDA3MVRBFABFQ1  
TDA  
775  
775 ABF  
ABF  
750  
Call TI | SNAGCU  
TDA3MVRBFABFQ1  
TDA  
775  
775 ABF  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
Addendum-Page 3  
PACKAGE OPTION ADDENDUM  
www.ti.com  
13-Apr-2021  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 4  
PACKAGE OUTLINE  
ABF0367A  
FCBGA - 2.82 mm max height  
SCALE 0.900  
BALL GRID ARRAY  
15.12  
14.88  
A
B
BALL A1 CORNER  
15.12  
14.88  
(
11.6)  
(
14.6)  
(1.3)  
(2.39)  
0.25 C  
C
2.82 MAX  
SEATING PLANE  
NOTE 4  
(0.99)  
BALL TYP  
0.1 C  
0.4  
0.2  
TYP  
13.65 TYP  
SYMM  
(0.68) TYP  
(0.68) TYP  
0.65 TYP  
AB  
AA  
Y
V
T
W
U
R
N
L
13.65  
P
M
K
H
F
TYP  
SYMM  
J
G
E
C
A
0.45  
0.35  
367X  
D
B
0.15  
0.08  
C A B  
C
NOTE 3  
1
3
5
7
9
11 13 15 17 19 21  
10 12 18  
22  
0.65 TYP  
6
8
2
4
14 16  
20  
4221430/C 04/2019  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. Dimension is measured at the maximum solder ball diameter, parallel to primary datum C.  
4. Primary datum C and seating plane are defined by the spherical crown of the solder balls.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
ABF0367A  
FCBGA - 2.82 mm max height  
BALL GRID ARRAY  
(0.65) TYP  
1
2
3 4 6 7  
5 8  
9 10 11 12 13  
14 15 16 17 18 19 20 21 22  
A
B
C
(0.65) TYP  
D
E
F
0.365  
0.335  
367X  
G
H
J
K
SYMM  
L
M
N
P
R
T
U
V
W
Y
AA  
AB  
SYMM  
LAND PATTERN EXAMPLE  
SCALE:6X  
0.05 MAX  
0.05 MIN  
METAL  
UNDER  
MASK  
(
0.35)  
METAL  
(
0.35)  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
NON-SOLDER MASK  
DEFINED  
SOLDER MASK  
DEFINED  
(PREFERRED)  
SOLDER MASK DETAILS  
NOT TO SCALE  
4221430/C 04/2019  
NOTES: (continued)  
5. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.  
For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).  
www.ti.com  
EXAMPLE STENCIL DESIGN  
ABF0367A  
FCBGA - 2.82 mm max height  
BALL GRID ARRAY  
(0.65) TYP  
1
2
3 4 6 7  
5 8  
9 10 11 12 13  
14 15 16 17 18 19 20 21 22  
A
B
C
(0.65)  
TYP  
D
E
0.365  
0.335  
F
362X  
G
H
J
K
SYMM  
L
M
N
P
R
T
U
V
W
Y
AA  
AB  
SYMM  
SOLDER PASTE EXAMPLE  
BASED ON 0.125 mm THICK STENCIL  
SCALE:6X  
4221430/C 04/2019  
NOTES: (continued)  
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.  
www.ti.com  
IMPORTANT NOTICE AND DISCLAIMER  
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE  
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”  
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY  
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD  
PARTY INTELLECTUAL PROPERTY RIGHTS.  
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate  
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable  
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you  
permission to use these resources only for development of an application that uses the TI products described in the resource. Other  
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party  
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,  
costs, losses, and liabilities arising out of your use of these resources.  
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either  
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s  
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2021, Texas Instruments Incorporated  

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