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TDA4VL-Q1 [TI]

具有 AI 和图形、适用于环视泊车辅助应用的汽车片上系统;
TDA4VL-Q1
型号： TDA4VL-Q1
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

具有 AI 和图形、适用于环视泊车辅助应用的汽车片上系统
文件： 总255页 (文件大小：5431K)
中文：  中文翻译
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TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
TDA4VE TDA4AL TDA4VL Jacinto™ 处理器，器件版本1.0  
功能安全：  
1 特性  
• 以功能安全合规型为目标（在部分器件型号上）  
• 专为功能安全应用开发  
处理器内核：  
• 可提供使ISO 26262 功能安全系统设计满足ASIL-  
D/SIL-3 要求的文档  
• 两个C7x 浮点、矢量DSP，性能高达1.0GHz、  
160GFLOPS、512GOPS  
• 系统功能符合ASIL-D/SIL-3 要求  
• 对于MCU 域，硬件完整性符合ASIL-D/SIL-3 要求  
• 对于MAIN 域，硬件完整性符合ASIL-B/SIL-2 要求  
• 对于MAIN 域的扩展MCU (EMCU) 部分，硬件完  
整性符合ASIL-D/SIL-3 要求  
• 深度学习矩阵乘法加速器(MMA)，性能高达  
8TOPS (8b)（频率为1.0GHz）  
• 具有图像信号处理器(ISP) 和多个视觉辅助加速器  
的视觉处理加速器(VPAC)  
• 深度和运动处理加速器(DMPAC)  
• 双核64 位Arm® Cortex®-A72 微处理器子系统，性  
能高达2 GHz  
• 安全相关认证  
– 计划通过ISO 26262 认证  
– 每个双核Cortex®-A72 集群具有1MB L2 共享缓  
存
器件安全（在部分器件型号上）：  
– 每个Cortex®-A72 内核具有32KB L1 数据缓存  
• 安全引导，提供安全运行时支持  
• 客户可编程的根密钥，级别高达RSA-4K 或  
ECC-512  
• 嵌入式硬件安全模块  
• 加密硬件加速器–带ECC 的PKA、AES、SHA、  
RNG、DES 和3DES  
和48KB L1 指令缓存  
• 多达六个Arm® Cortex®-R5F MCU，性能高达  
1.0GHz  
– 16K 指令缓存，16K 数据缓存，64K L2 TCM  
– 隔离MCU 子系统中有两个Arm® Cortex®-R5F  
MCU  
高速串行接口：  
– 通用计算分区中有四个(TDA4VE) 或两个  
(TDA4AL/TDA4VL) Arm® Cortex®-R5F MCU  
• GPU IMG BXS-64-4，256KB 缓存，高达  
800MHz，50GFLOPS，4GTexels/s（TDA4VE 和  
TDA4VL）  
• 一个PCI-Express® (PCIe) 第3 代控制器  
– 每个控制器多达四个通道  
– 第1 代(2.5GT/s)、第2 代(5.0GT/s) 和第3 代  
(8.0GT/s) 运行，具有自动协商功能  
• 一个USB 3.0 双重角色器件(DRD) 子系统  
• 定制设计的互联结构，支持接近于最高的处理能力  
– 增强型超高速第一代端口  
– 支持Type-C 开关  
存储器子系统：  
• 高达4MB 的片上L3 RAM（具有ECC 和一致性）  
– 可独立配置为USB 主机、USB 外设或USB  
DRD  
• 两个CSI2.0 4L RX 加上两个CSI2.04L TX  
– ECC 错误保护  
– 共享一致性缓存  
– 支持内部DMA 引擎  
• 多达两个具有ECC 的外部存储器接口(EMIF) 模块  
汽车接口：  
• 20 个模块化控制器局域网(MCAN) 模块，具有完整  
CAN-FD 支持  
– 支持LPDDR4 存储器类型  
– 支持高达4266MT/s 的速度  
– 两条(TDA4VE) 或一条(TDA4AL/TDA4VL) 32  
位数据总线，每个EMIF 具有高达17Gb/s 的内  
联ECC  
显示子系统：  
• 一个(TDA4AL/TDA4VL) 或两个(TDA4VE) DSI 4L  
TX（高达2.5K）  
• 一个eDP 4L (TDA4VE/TDA4VL)  
• 通用存储器控制器(GPMC)  
• MAIN 域中有一个(TDA4AL/TDA4VL) 或两个  
(TDA4VE) 512KB 片上SRAM，受ECC 保护  
• 一个DPI  
音频接口：  
• 5 个多通道音频串行端口(MCASP) 模块  
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问  
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。  
English Data Sheet: SPRSP62  
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
视频加速：  
片上系统(SoC) 架构：  
• 16nm FinFET 技术  
• TDA4VE：H.264/H.265 编码/解码（高达  
480MP/s）  
• 23mm x 23mm、0.8mm 间距、770 引脚FCBGA  
• TDA4AL：仅限H.264/H.265 编码/解码（高达  
(ALZ)  
480MP/s）  
配套电源管理IC (PMIC)：  
• TDA4VL：H.264/H.265 编码/解码（高达  
240MP/s）  
• 以功能安全合规型为目标，最高支持ASIL-D/SIL-3  
• 灵活的映射，可支持不同的用例  
以太网：  
• 两个RMII/RGMII 接口  
闪存接口：  
• 嵌入式多媒体卡接口(eMMC™ 5.1)  
• 一个Secure Digital® 3.0/安全数字输入输出3.0 接  
口(SD3.0/SDIO3.0)  
• 2 个同步闪存接口，配置为  
– 一个OSPI 或HyperBus™ 或QSPI，以及  
– 一个QSPI  
2 应用  
• 高级驾驶员辅助系统(ADAS)  
• 机器视觉  
• 工业运输  
• 零售自动化  
• 监控  
3 说明  
TDA4VE TDA4AL TDA4VL 处理器系列采用不断发展的 Jacinto™ 7 架构，面向智能视觉摄像头应用，基于 TI 在  
视觉处理器市场上十多年所积累的广泛先进市场知识而构建。TDA4AL 以业界卓越的功耗/性能比为传统和深度学  
习算法提供高性能计算，并且系统集成度高，可为高级视觉摄像头应用实现可扩展性和更低的成本。关键内核包  
括具有标量和矢量内核的下一代 DSP、专用深度学习和传统算法加速器、用于通用计算的最新 Arm 和 GPU 处理  
器、集成式下一代成像子系统 (ISP)、视频编解码器以及隔离式 MCU 岛。所有这些都由汽车级安全硬件加速器提  
供保护。  
主要高性能内核概述：“C7x”下一代 DSP 将 TI 先进的 DSP 和 EVE 内核整合到单个性能更高的内核中，并增  
加了浮点矢量计算功能，从而实现了对旧代码的向后兼容性，同时简化了软件编程。在典型的汽车最坏情况结温  
125°C 下运行时，新型“MMA”深度学习加速器可在业界超低的功率范围内实现高达 8TOPS 的性能。专用的视  
觉硬件加速器可提供视觉预处理而不会影响系统性能。  
通用计算内核和集成概述：对 Arm® Cortex®-A72 的独立双核集群配置有助于实现多操作系统应用，而且对软件  
管理程序的需求非常低。最多四个 Arm® Cortex®-R5F 子系统能够管理低级的时序关键型处理任务，使 Arm®  
Cortex®-A72 内核不受应用的影响。TI 的第7 代ISP 以现有出色的 ISP 为基础，能够灵活地处理更广泛的传感器  
套件，支持更高的位深度，并且具有面向分析应用的特性。集成的诊断和安全功能可支持高达 ASIL-D 级别的运  
行，同时集成的安全功能可保护数据免受现代攻击。CSI2.0 端口支持多传感器输入。为了进一步集成，TDA4VE  
TDA4AL TDA4VL 系列还包含一个MCU 岛，从而无需使用外部系统微控制器。  
封装信息  
封装(1)  
器件型号  
封装尺寸  
TDA4VE...ALZQ1  
TDA4AL...ALZQ1  
FCBGA (770)  
FCBGA (770)  
23mm × 23mm  
23mm × 23mm  
Copyright © 2023 Texas Instruments Incorporated  
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
English Data Sheet: SPRSP62  
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
封装信息(continued)  
封装(1)  
器件型号  
封装尺寸  
TDA4VL...ALZQ1  
FCBGA (770)  
23mm × 23mm  
(1) 有关更多信息，请参阅机械、封装和可订购信息部分。  
Copyright © 2023 Texas Instruments Incorporated  
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
English Data Sheet: SPRSP62  
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
3.1 功能方框图  
图3-1 是器件的功能方框图。  
MAIN Domain  
WKUP/MCU Domain  
WKUP_SMS  
M4F  
AES  
INTA  
H.264/H.265  
Encode/Decode  
SECMGR  
ROM 160K  
WKUP_CTRL_MMR  
WKUP_PSC  
1× C71SS  
1× C71SS  
2× R5FSS  
1× A72SS  
WKUP_VTM  
CTRL_MMR  
DebugSS  
WKUP_PLLCTRL  
2×WKUP_GPIO  
1×WKUP_I2C  
1× C71x  
1× C71x  
DSP  
2× Arm  
2×Arm  
WKUP_SA2SS  
Cortex-A72  
Cortex-R5F  
DSP+MMA  
MCU_SA2_UL  
WKUP_DMSS_HSM  
1×WKUP_UART  
1×WKUP_ESM  
PLLs  
SecProxy/RA  
AES3DES PKA  
512KB L2  
512KB L2  
2MB L2  
TCM 64KB  
DBG  
SHA  
PSI-L PKTDMA  
20×TIMER  
10×WWDT  
GPU BSX-64-4  
MCU_CTRL_MMR  
MSMC  
MSMC  
3×MCU_PLL  
10×MCU_TIMER  
2×MCU_WWDT  
1024KB L3 RAM  
DDRSS  
2× 32b + in-line  
ECC + MFLAG  
ESM  
1× DRU  
+ CMMU  
Compression  
4MB SRAM with ECC  
10× DCC  
512B Scratchpad RAM  
1× ATL  
R5FSS  
NAVSS  
R5F  
R5F  
Spinlock  
Channelized FW  
2×TIMER_MGR  
UDMA-P  
VIRTSS  
I-cache 32KB  
I-cache 32KB  
To CPSW  
2×Mailbox  
3×INTA  
Proxy  
D-cache 32KB  
D-cache 32KB  
2×PVU  
CPTS  
TCM 64KB  
TCM 64KB  
MCRC  
RINGACC  
MCU Internal Diagnostics  
3x MCU_DCC 1×MCU_ESM  
To MCU NAVSS  
PSI-L  
Local Interconnect  
MCU NAVSS  
2 x 512 KB SRAM  
Interconnect  
Channelized FW  
INTA  
INTR  
RINGACC  
UDMA-P  
Proxy  
MCRC  
PSI-L  
1×MCU_CPSW  
To NAVSS  
MCU_PDMA  
2×MCU_I2C  
1×MCU_I3C  
3×MCU_MCSPI  
1×MCU_UART  
2×MCU_MCAN  
2×OSPI  
1×HPB  
MCU_FSS  
MUX  
MUX  
DPHY_RX  
2×DPHY_TX  
1×SERDES (4L)  
2×MCU_ADC  
(18ch/2b/4MSPS)  
intro-001  
A. 黑色实线框表示IP 是扩展MCU (eMCU) 的一部分。  
B. 黑色虚线框表示IP 的某些实例存在于eMCU 中，而某些实例存在于MAIN 域的非eMCU 部分中。  
图3-1. 功能方框图  
Copyright © 2023 Texas Instruments Incorporated  
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
English Data Sheet: SPRSP62  
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
4 Revision History  
表4-1. TDA4AL, TDA4VE, TDA4VL Revisions  
DATE  
REVISION  
NOTES  
December 2022  
*
Initial external release.  
Copyright © 2023 Texas Instruments Incorporated  
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
English Data Sheet: SPRSP62  
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
5 Device Comparison  
表5-1 shows the features of the SoC.  
表5-1. Device Comparison  
FEATURES(6)  
PROCESSORS AND ACCELERATORS  
Speed Grades  
REFERENCE NAME  
TDA4VE88  
TDA4AL88  
TDA4VL21  
T, N  
Dual Core  
Hexa Core  
Optional(1)  
Yes  
T, N  
Dual Core  
Quad Core  
Optional(1)  
Yes  
H
Dual Core  
Quad Core  
Optional(1)  
Yes  
Arm Cortex-A72 Microprocessor Subsystem Arm A72  
Arm Cortex-R5F  
Arm R5F  
Lockstep  
SMS  
Security Management Subsystem  
Security Accelerators  
SA  
Yes  
Yes  
Yes  
C7x Floating Point, Vector DSP  
Deep Learning Accelerator  
Graphics Accelerator IMG BXS-64-4  
Depth and Motion Processing Accelerators  
Vision Processing Accelerators  
Video Encoder/Decoder  
C7x DSP  
MMA  
Dual Core  
Yes  
Dual Core  
Yes  
Dual Core  
Yes  
GPU  
Yes  
No  
Yes  
DMPAC  
VPAC  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
VENC/VDEC  
Enc/Dec  
Enc only  
Enc/Dec  
SAFETY AND SECURITY  
Safety Targeted  
Safety  
Security  
Q1  
Optional(1)  
Optional(2)  
Optional(3)  
Optional(1)  
Optional(2)  
Optional(3)  
Optional(1)  
Optional(2)  
Optional(3)  
Device Security  
AEC-Q100 Qualified  
PROGRAM AND DATA STORAGE  
On-Chip Shared Memory (RAM) in MAIN  
Domain  
OCSRAM  
MCU_MSRAM  
MSMC  
2x512KB SRAM  
1MB SRAM  
1x512KB SRAM  
1x512KB SRAM  
On-Chip Shared Memory (RAM) in MCU  
Domain  
1MB SRAM  
1MB SRAM  
Multicore Shared Memory Controller  
4MB (On-Chip SRAM 4MB (On-Chip SRAM 4MB (On-Chip SRAM  
with ECC)  
with ECC)  
with ECC)  
LPDDR4 DDR Subsystem  
DDRSS0  
DDRSS1  
Up to 8GB (32-bit  
data) with inline ECC data) with inline ECC data) with inline ECC  
Up to 8GB (32-bit  
Up to 8GB (32-bit  
Up to 8GB (32-bit  
No(8)  
No(8)  
data) with inline ECC  
SECDED  
GPMC  
7-Bit  
7-Bit  
7-Bit  
General-Purpose Memory Controller  
PERIPHERALS  
Up to 1GB with ECC Up to 1GB with ECC Up to 1GB with ECC  
Display Subsystem  
DSS  
Yes  
2
Yes  
1(10)  
0
Yes  
1(10)  
1
DSI 4L TX  
eDP 4L  
DPI  
1
1
1
1
Modular Controller Area Network Interface  
with Full CAN-FD Support  
MCAN  
20  
20  
20  
General-Purpose I/O  
GPIO  
155  
10  
1
155  
10  
1
155  
10  
1
Inter-Integrated Circuit Interface  
Improved Inter-Integrated Circuit Interface  
Analog-to-Digital Converter  
I2C  
I3C  
ADC  
2
2
2
Capture Subsystem with Camera Serial  
Interface (CSI2)  
CSI2.0 4L RX  
CSI2.0 4L TX  
MCSPI  
2
2
2
2
2
2
Multichannel Serial Peripheral Interface  
11  
11  
11  
Copyright © 2023 Texas Instruments Incorporated  
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
English Data Sheet: SPRSP62  
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
表5-1. Device Comparison (continued)  
FEATURES(6)  
REFERENCE NAME  
MCASP0  
MCASP1  
MCASP2  
MCASP3  
MCASP4  
MMCSD0  
MMCSD1  
UFS 2L  
TDA4VE88  
16 Serializers  
5 Serializers  
5 Serializers  
3 Serializers  
5 Serializers  
eMMC (8-bits)  
SD/SDIO (4-bits)  
No  
TDA4AL88  
16 Serializers  
5 Serializers  
5 Serializers  
3 Serializers  
5 Serializers  
eMMC (8-bits)  
SD/SDIO (4-bits)  
No  
TDA4VL21  
16 Serializers  
5 Serializers  
5 Serializers  
3 Serializers  
5 Serializers  
eMMC (8-bits)  
SD/SDIO (4-bits)  
No  
Multichannel Audio Serial Port  
MultiMedia Card/ Secure Digital Interface  
Universal Flash Storage  
Flash Subsystem (FSS)  
OSPI0  
8-bits(5)  
8-bits(5)  
8-bits(5)  
OSPI1(7)  
HyperBus  
PCIE0  
4-bits  
4-bits  
4-bits  
Yes(5)  
Yes(5)  
Yes(5)  
4x PCI Express Port with Integrated PHY  
Hyperlink  
Up to Four Lanes(4)  
No(9)  
Up to Four Lanes(4)  
No(9)  
Up to Four Lanes(4)  
No(9)  
HYP  
Gigabit Ethernet Interface  
MCU  
1x RGMII or RMII  
1x RGMII or RMII  
30  
1x RGMII or RMII  
1x RGMII or RMII  
30  
1x RGMII or RMII  
1x RGMII or RMII  
30  
Main  
General-Purpose Timers  
TIMER  
Enhanced High Resolution Pulse-Width  
Modulator Module  
eHRPWM  
6
6
6
Enhanced Capture Module  
eCAP  
3
3
3
3
3
3
Enhanced Quadrature Encoder Pulse Module eQEP  
Universal Asynchronous Receiver and  
Transmitter  
UART  
12  
12  
12  
Universal Serial Bus (USB3.1) SuperSpeed  
Dual-Role-Device (DRD) Ports with SS PHY  
USB0  
Yes(4)  
Yes(4)  
Yes(4)  
(1) Safety features including R5F Lockstep and SIL/ASIL ratings are only applicable to select part number variants as indicated by the  
Device Type (Y) identifier in the Table 10-1, Nomenclature Description table.  
(2) Device security features including Secure Boot and Customer Programmable Keys are applicable to select part number variants as  
indicated by the Device Type (Y) identifier in the Table 10-1, Nomenclature Description table  
(3) AEC-Q100 qualification is applicable to select part number variants as indicated by the Automotive Designator (Q1) identifier in the  
Table 10-1, Nomenclature Description table  
(4) USB3.0 and PCIE share a total of four SerDes lanes.  
(5) Two simultaneous flash interfaces configured as OSPI0 and OSPI1, or HyperBus and OSPI1.  
(6) J721S2 is the base part number for the superset device. Software should constrain the features used to match the intended production  
device.  
(7) OSPI1 module only pins out 4 pins and is referred to as QSPI in some contexts.  
(8) Part number variants with DDRSS1 as "No" should not use the DDR1_* pins. The DDR1_* pins should be connected as recommended  
in the section titled "Connections for Unused Pins"  
(9) Hyperlink is not supported on this SoC. System designs should not use the signals HYP_*, HYP0_*, HYP1_*.  
(10) Part number variants with DSI 4L TX as "1" can only use the DSI0 interface for DSI functionality. DSI1* balls can still be used for CSI1  
functionality.  
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
English Data Sheet: SPRSP62  
 
 
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
6 Terminal Configuration and Functions  
6.1 Pin Diagrams  
See Packaging Information.  
6.2 Pin Attributes  
1. BALL NUMBER: Ball numbers on the bottom side associated with each signal on the bottom.  
2. BALL NAME: Mechanical name from package device (name is taken from muxmode 0).  
3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the  
signal name in muxmode 0).  
4. MUXMODE: Multiplexing mode number.  
5. TYPE: Signal type and direction:  
• I = Input  
• O = Output  
• OD = Open drain terminal - Output  
• IO = Input or Output  
• IOD = Open drain terminal - Input or Output  
• IOZ = Input, Output or Three-state terminal  
• OZ = Output or Three-state terminal  
• A = Analog  
• PWR = Power  
• GND = Ground  
• CAP = LDO Capacitor.  
6. I/O VOLTAGE VALUE: This column describes the IO voltage value (the corresponding power supply).  
An empty box means Not Applicable.  
7. BALL STATE DURING RESET:This column describes the state of the transmit buffer, receive buffer, and  
internal pull during reset.  
8. BALL STATE AFTER RESET:This column describes the state of the transmit buffer, receive buffer, and  
internal pull after reset.  
9. MUX MODE AFTER RESET:The active multiplexing mode after reset.  
10. POWER: The voltage supply that powers the terminal IO buffers.  
An empty box means Not Applicable.  
11. VOLTAGE BUFFER TYPE: This column describes the associated output buffer type.  
An empty box means Not Applicable.  
12. IO RET:Yes means WKUP and IO retention supported.  
13. PADCFG NAME:Name of the pad configuration register.  
14. PADCFG ADDRESSAddress of the pad configuration register.  
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English Data Sheet: SPRSP62  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
表6-1 shows the pull type [pullup/pulldown] and Hysteresis associations to buffer types.  
表6-1. Buffer Types with Pull Type and Hysteresis Associations  
PULL TYPE  
BUFFER TYPE  
HYSTERESIS(2)  
(PU/PD)(1)  
4L_PHY  
ADC12B  
AUX-PHY  
D-PHY  
DDR  
eMMCPHY  
FS_RESET  
HFXOSC  
PU/PD  
Yes  
Yes  
Yes  
Yes  
Yes  
I2C OPEN DRAIN  
LVCMOS  
PU/PD  
PU/PD  
SDIO  
USB2PHY  
(1) PULL TYPE: Indicates the presence of an internal pullup or pulldown resistor. Pullup and pulldown  
resistors can be enabled or disabled via software.  
(2) HYS: Indicates if the input buffer has hysteresis:  
•
•
•
Yes: With hysteresis  
No: Without hysteresis  
An empty box means No  
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English Data Sheet: SPRSP62  
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
备注  
When DDR1 is used concurrently with either OSPI0 or Hyperbus, VDDSHV1_MCU is limited to 1.8V.  
表6-2. Pin Attributes (ALZ Package)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
DURING  
Reset  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
T21  
J20  
CAP_VDDS0  
CAP_VDDS0  
CAP  
CAP  
CAP  
CAP  
CAP  
CAP  
CAP_VDDS0_MCU  
CAP_VDDS1_MCU  
CAP_VDDS2  
CAP_VDDS0_MCU  
CAP_VDDS1_MCU  
CAP_VDDS2  
G16  
P21  
H17  
M22  
CAP_VDDS2_MCU  
CAP_VDDS5  
CAP_VDDS2_MCU  
CAP_VDDS5  
VDDA_0P8_CS  
IRX0_1 /  
VDDA_1P8_CS  
IRX0_1  
AH19  
AH20  
AC18  
AH22  
AH23  
AC21  
AG18  
AF19  
AE18  
CSI0_RXCLKN  
CSI0_RXCLKP  
CSI0_RXRCALIB  
CSI1_RXCLKN  
CSI1_RXCLKP  
CSI1_RXRCALIB  
CSI0_RXN0  
CSI0_RXCLKN  
CSI0_RXCLKP  
CSI0_RXRCALIB  
CSI1_RXCLKN  
CSI1_RXCLKP  
CSI1_RXRCALIB  
CSI0_RXN0  
I
I
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
D-PHY  
D-PHY  
D-PHY  
D-PHY  
D-PHY  
D-PHY  
D-PHY  
D-PHY  
D-PHY  
VDDA_0P8_CS  
IRX0_1 /  
VDDA_1P8_CS  
IRX0_1  
VDDA_0P8_CS  
IRX0_1 /  
VDDA_1P8_CS  
IRX0_1  
A
I
VDDA_0P8_CS  
IRX0_1 /  
VDDA_1P8_CS  
IRX0_1  
VDDA_0P8_CS  
IRX0_1 /  
VDDA_1P8_CS  
IRX0_1  
I
VDDA_0P8_CS  
IRX0_1 /  
VDDA_1P8_CS  
IRX0_1  
A
I
VDDA_0P8_CS  
IRX0_1 /  
VDDA_1P8_CS  
IRX0_1  
VDDA_0P8_CS  
IRX0_1 /  
VDDA_1P8_CS  
IRX0_1  
CSI0_RXN1  
CSI0_RXN1  
I
VDDA_0P8_CS  
IRX0_1 /  
VDDA_1P8_CS  
IRX0_1  
CSI0_RXN2  
CSI0_RXN2  
I
Copyright © 2023 Texas Instruments Incorporated  
English Data Sheet: SPRSP62  
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
VDDA_0P8_CS  
IRX0_1 /  
VDDA_1P8_CS  
IRX0_1  
AD19  
AG19  
AF20  
AE19  
AD20  
AG21  
AF22  
AE21  
AD22  
AG22  
AF23  
AE22  
AD23  
CSI0_RXN3  
CSI0_RXN3  
CSI0_RXP0  
CSI0_RXP1  
CSI0_RXP2  
CSI0_RXP3  
CSI1_RXN0  
CSI1_RXN1  
CSI1_RXN2  
CSI1_RXN3  
CSI1_RXP0  
CSI1_RXP1  
CSI1_RXP2  
CSI1_RXP3  
I
I
I
I
I
I
I
I
I
I
I
I
I
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
D-PHY  
D-PHY  
D-PHY  
D-PHY  
D-PHY  
D-PHY  
D-PHY  
D-PHY  
D-PHY  
D-PHY  
D-PHY  
D-PHY  
D-PHY  
VDDA_0P8_CS  
IRX0_1 /  
VDDA_1P8_CS  
IRX0_1  
CSI0_RXP0  
VDDA_0P8_CS  
IRX0_1 /  
VDDA_1P8_CS  
IRX0_1  
CSI0_RXP1  
CSI0_RXP2  
CSI0_RXP3  
CSI1_RXN0  
CSI1_RXN1  
CSI1_RXN2  
CSI1_RXN3  
CSI1_RXP0  
CSI1_RXP1  
CSI1_RXP2  
CSI1_RXP3  
VDDA_0P8_CS  
IRX0_1 /  
VDDA_1P8_CS  
IRX0_1  
VDDA_0P8_CS  
IRX0_1 /  
VDDA_1P8_CS  
IRX0_1  
VDDA_0P8_CS  
IRX0_1 /  
VDDA_1P8_CS  
IRX0_1  
VDDA_0P8_CS  
IRX0_1 /  
VDDA_1P8_CS  
IRX0_1  
VDDA_0P8_CS  
IRX0_1 /  
VDDA_1P8_CS  
IRX0_1  
VDDA_0P8_CS  
IRX0_1 /  
VDDA_1P8_CS  
IRX0_1  
VDDA_0P8_CS  
IRX0_1 /  
VDDA_1P8_CS  
IRX0_1  
VDDA_0P8_CS  
IRX0_1 /  
VDDA_1P8_CS  
IRX0_1  
VDDA_0P8_CS  
IRX0_1 /  
VDDA_1P8_CS  
IRX0_1  
VDDA_0P8_CS  
IRX0_1 /  
VDDA_1P8_CS  
IRX0_1  
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
English Data Sheet: SPRSP62  
 
 
 
 
 
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
VDDS_DDR /  
VDDS_DDR_C  
0
R1  
P1  
DDR0_CKN  
DDR0_CKN  
DDR0_CKP  
DDR0_RESETn  
DDR0_RET  
DDR1_CKN  
DDR1_CKP  
DDR1_RESETn  
DDR1_RET  
DDR0_CA0  
DDR0_CA1  
DDR0_CA2  
DDR0_CA3  
DDR0_CA4  
DDR0_CA5  
DDR0_CAL0  
DDR0_CKE0  
IO  
IO  
IO  
I
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
VDDS_DDR /  
VDDS_DDR_C  
0
DDR0_CKP  
DDR0_RESETn  
DDR0_RET  
DDR1_CKN  
DDR1_CKP  
DDR1_RESETn  
DDR1_RET  
DDR0_CA0  
DDR0_CA1  
DDR0_CA2  
DDR0_CA3  
DDR0_CA4  
DDR0_CA5  
DDR0_CAL0  
DDR0_CKE0  
VDDS_DDR /  
VDDS_DDR_C  
0
R5  
T8  
VDDS_DDR /  
VDDS_DDR_C  
0
VDDS_DDR /  
VDDS_DDR_C  
1
A9  
IO  
IO  
IO  
I
VDDS_DDR /  
VDDS_DDR_C  
1
A10  
F12  
J10  
P3  
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
0
IO  
IO  
IO  
IO  
IO  
IO  
A
VDDS_DDR /  
VDDS_DDR_C  
0
P5  
VDDS_DDR /  
VDDS_DDR_C  
0
N5  
P2  
VDDS_DDR /  
VDDS_DDR_C  
0
VDDS_DDR /  
VDDS_DDR_C  
0
P4  
VDDS_DDR /  
VDDS_DDR_C  
0
R3  
R8  
R2  
VDDS_DDR /  
VDDS_DDR_C  
0
VDDS_DDR /  
VDDS_DDR_C  
0
IO  
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English Data Sheet: SPRSP62  
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TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
VDDS_DDR /  
VDDS_DDR_C  
0
R4  
V5  
W5  
T5  
DDR0_CKE1  
DDR0_CKE1  
DDR0_CSn0_0  
DDR0_CSn0_1  
DDR0_CSn1_0  
DDR0_CSn1_1  
DDR0_DM0  
DDR0_DM1  
DDR0_DM2  
DDR0_DM3  
DDR0_DQ0  
DDR0_DQ1  
DDR0_DQ2  
DDR0_DQ3  
DDR0_DQ4  
DDR0_DQ5  
DDR0_DQ6  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
VDDS_DDR /  
VDDS_DDR_C  
0
DDR0_CSn0_0  
VDDS_DDR /  
VDDS_DDR_C  
0
DDR0_CSn0_1  
DDR0_CSn1_0  
DDR0_CSn1_1  
DDR0_DM0  
DDR0_DM1  
DDR0_DM2  
DDR0_DM3  
DDR0_DQ0  
DDR0_DQ1  
DDR0_DQ2  
DDR0_DQ3  
DDR0_DQ4  
DDR0_DQ5  
DDR0_DQ6  
VDDS_DDR /  
VDDS_DDR_C  
0
VDDS_DDR /  
VDDS_DDR_C  
0
U6  
H5  
M3  
U4  
AD1  
F3  
VDDS_DDR /  
VDDS_DDR_C  
0
VDDS_DDR /  
VDDS_DDR_C  
0
VDDS_DDR /  
VDDS_DDR_C  
0
VDDS_DDR /  
VDDS_DDR_C  
0
VDDS_DDR /  
VDDS_DDR_C  
0
VDDS_DDR /  
VDDS_DDR_C  
0
G4  
F5  
VDDS_DDR /  
VDDS_DDR_C  
0
VDDS_DDR /  
VDDS_DDR_C  
0
F1  
VDDS_DDR /  
VDDS_DDR_C  
0
J4  
VDDS_DDR /  
VDDS_DDR_C  
0
H3  
J2  
VDDS_DDR /  
VDDS_DDR_C  
0
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
English Data Sheet: SPRSP62  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
VDDS_DDR /  
VDDS_DDR_C  
0
G2  
K5  
M5  
K3  
K1  
N4  
N2  
L4  
DDR0_DQ7  
DDR0_DQ7  
DDR0_DQ8  
DDR0_DQ9  
DDR0_DQ10  
DDR0_DQ11  
DDR0_DQ12  
DDR0_DQ13  
DDR0_DQ14  
DDR0_DQ15  
DDR0_DQ16  
DDR0_DQ17  
DDR0_DQ18  
DDR0_DQ19  
DDR0_DQ20  
DDR0_DQ21  
DDR0_DQ22  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
VDDS_DDR /  
VDDS_DDR_C  
0
DDR0_DQ8  
DDR0_DQ9  
DDR0_DQ10  
DDR0_DQ11  
DDR0_DQ12  
DDR0_DQ13  
DDR0_DQ14  
DDR0_DQ15  
DDR0_DQ16  
DDR0_DQ17  
DDR0_DQ18  
DDR0_DQ19  
DDR0_DQ20  
DDR0_DQ21  
DDR0_DQ22  
VDDS_DDR /  
VDDS_DDR_C  
0
VDDS_DDR /  
VDDS_DDR_C  
0
VDDS_DDR /  
VDDS_DDR_C  
0
VDDS_DDR /  
VDDS_DDR_C  
0
VDDS_DDR /  
VDDS_DDR_C  
0
VDDS_DDR /  
VDDS_DDR_C  
0
VDDS_DDR /  
VDDS_DDR_C  
0
L2  
VDDS_DDR /  
VDDS_DDR_C  
0
T1  
T3  
V3  
U2  
W2  
W4  
Y1  
VDDS_DDR /  
VDDS_DDR_C  
0
VDDS_DDR /  
VDDS_DDR_C  
0
VDDS_DDR /  
VDDS_DDR_C  
0
VDDS_DDR /  
VDDS_DDR_C  
0
VDDS_DDR /  
VDDS_DDR_C  
0
VDDS_DDR /  
VDDS_DDR_C  
0
Copyright © 2023 Texas Instruments Incorporated  
English Data Sheet: SPRSP62  
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
VDDS_DDR /  
VDDS_DDR_C  
0
Y3  
AB3  
AA2  
AA4  
Y5  
DDR0_DQ23  
DDR0_DQ23  
DDR0_DQ24  
DDR0_DQ25  
DDR0_DQ26  
DDR0_DQ27  
DDR0_DQ28  
DDR0_DQ29  
DDR0_DQ30  
DDR0_DQ31  
DDR0_DQS0N  
DDR0_DQS0P  
DDR0_DQS1N  
DDR0_DQS1P  
DDR0_DQS2N  
DDR0_DQS2P  
DDR0_DQS3N  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
VDDS_DDR /  
VDDS_DDR_C  
0
DDR0_DQ24  
VDDS_DDR /  
VDDS_DDR_C  
0
DDR0_DQ25  
DDR0_DQ26  
DDR0_DQ27  
DDR0_DQ28  
DDR0_DQ29  
DDR0_DQ30  
DDR0_DQ31  
DDR0_DQS0N  
DDR0_DQS0P  
DDR0_DQS1N  
DDR0_DQS1P  
DDR0_DQS2N  
DDR0_DQS2P  
DDR0_DQS3N  
VDDS_DDR /  
VDDS_DDR_C  
0
VDDS_DDR /  
VDDS_DDR_C  
0
VDDS_DDR /  
VDDS_DDR_C  
0
AC2  
AB5  
AD2  
AC4  
H1  
VDDS_DDR /  
VDDS_DDR_C  
0
VDDS_DDR /  
VDDS_DDR_C  
0
VDDS_DDR /  
VDDS_DDR_C  
0
VDDS_DDR /  
VDDS_DDR_C  
0
VDDS_DDR /  
VDDS_DDR_C  
0
G1  
VDDS_DDR /  
VDDS_DDR_C  
0
M1  
VDDS_DDR /  
VDDS_DDR_C  
0
L1  
VDDS_DDR /  
VDDS_DDR_C  
0
U1  
VDDS_DDR /  
VDDS_DDR_C  
0
V1  
VDDS_DDR /  
VDDS_DDR_C  
0
AC1  
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Submit Document Feedback  
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
English Data Sheet: SPRSP62  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
VDDS_DDR /  
VDDS_DDR_C  
0
AB1  
C10  
E10  
E9  
DDR0_DQS3P  
DDR0_DQS3P  
DDR1_CA0  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
A
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
VDDS_DDR /  
VDDS_DDR_C  
1
DDR1_CA0  
VDDS_DDR /  
VDDS_DDR_C  
1
DDR1_CA1  
DDR1_CA1  
VDDS_DDR /  
VDDS_DDR_C  
1
DDR1_CA2  
DDR1_CA2  
VDDS_DDR /  
VDDS_DDR_C  
1
B10  
D10  
C9  
DDR1_CA3  
DDR1_CA3  
VDDS_DDR /  
VDDS_DDR_C  
1
DDR1_CA4  
DDR1_CA4  
VDDS_DDR /  
VDDS_DDR_C  
1
DDR1_CA5  
DDR1_CA5  
VDDS_DDR /  
VDDS_DDR_C  
1
E8  
DDR1_CAL0  
DDR1_CKE0  
DDR1_CKE1  
DDR1_CSn0_0  
DDR1_CSn0_1  
DDR1_CSn1_0  
DDR1_CSn1_1  
DDR1_DM0  
DDR1_DM1  
DDR1_CAL0  
DDR1_CKE0  
DDR1_CKE1  
DDR1_CSn0_0  
DDR1_CSn0_1  
DDR1_CSn1_0  
DDR1_CSn1_1  
DDR1_DM0  
DDR1_DM1  
VDDS_DDR /  
VDDS_DDR_C  
1
B9  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
VDDS_DDR /  
VDDS_DDR_C  
1
D9  
VDDS_DDR /  
VDDS_DDR_C  
1
F9  
VDDS_DDR /  
VDDS_DDR_C  
1
F8  
VDDS_DDR /  
VDDS_DDR_C  
1
F11  
F10  
D16  
E13  
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
Copyright © 2023 Texas Instruments Incorporated  
English Data Sheet: SPRSP62  
16  
Submit Document Feedback  
Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
VDDS_DDR /  
VDDS_DDR_C  
1
F7  
DDR1_DM2  
DDR1_DM2  
DDR1_DM3  
DDR1_DQ0  
DDR1_DQ1  
DDR1_DQ2  
DDR1_DQ3  
DDR1_DQ4  
DDR1_DQ5  
DDR1_DQ6  
DDR1_DQ7  
DDR1_DQ8  
DDR1_DQ9  
DDR1_DQ10  
DDR1_DQ11  
DDR1_DQ12  
DDR1_DQ13  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
VDDS_DDR /  
VDDS_DDR_C  
1
B3  
DDR1_DM3  
VDDS_DDR /  
VDDS_DDR_C  
1
B18  
E17  
D18  
A17  
E15  
B16  
C15  
C17  
B14  
D14  
C13  
C11  
E11  
A11  
DDR1_DQ0  
DDR1_DQ1  
DDR1_DQ2  
DDR1_DQ3  
DDR1_DQ4  
DDR1_DQ5  
DDR1_DQ6  
DDR1_DQ7  
DDR1_DQ8  
DDR1_DQ9  
DDR1_DQ10  
DDR1_DQ11  
DDR1_DQ12  
DDR1_DQ13  
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
Copyright © 2023 Texas Instruments Incorporated  
Submit Document Feedback  
17  
Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
English Data Sheet: SPRSP62  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
VDDS_DDR /  
VDDS_DDR_C  
1
B12  
D12  
B7  
D7  
C8  
A8  
C6  
E6  
B5  
D5  
B1  
A4  
C4  
E4  
D1  
D3  
DDR1_DQ14  
DDR1_DQ14  
DDR1_DQ15  
DDR1_DQ16  
DDR1_DQ17  
DDR1_DQ18  
DDR1_DQ19  
DDR1_DQ20  
DDR1_DQ21  
DDR1_DQ22  
DDR1_DQ23  
DDR1_DQ24  
DDR1_DQ25  
DDR1_DQ26  
DDR1_DQ27  
DDR1_DQ28  
DDR1_DQ29  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
VDDS_DDR /  
VDDS_DDR_C  
1
DDR1_DQ15  
DDR1_DQ16  
DDR1_DQ17  
DDR1_DQ18  
DDR1_DQ19  
DDR1_DQ20  
DDR1_DQ21  
DDR1_DQ22  
DDR1_DQ23  
DDR1_DQ24  
DDR1_DQ25  
DDR1_DQ26  
DDR1_DQ27  
DDR1_DQ28  
DDR1_DQ29  
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
Copyright © 2023 Texas Instruments Incorporated  
English Data Sheet: SPRSP62  
18  
Submit Document Feedback  
Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
VDDS_DDR /  
VDDS_DDR_C  
1
C2  
E2  
DDR1_DQ30  
DDR1_DQ30  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
1.1 V  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
VDDS_DDR /  
VDDS_DDR_C  
1
DDR1_DQ31  
DDR1_DQ31  
VDDS_DDR /  
VDDS_DDR_C  
1
A15  
A16  
A12  
A13  
A7  
DDR1_DQS0N  
DDR1_DQS0P  
DDR1_DQS1N  
DDR1_DQS1P  
DDR1_DQS2N  
DDR1_DQS2P  
DDR1_DQS3N  
DDR1_DQS3P  
DDR1_DQS0N  
DDR1_DQS0P  
DDR1_DQS1N  
DDR1_DQS1P  
DDR1_DQS2N  
DDR1_DQS2P  
DDR1_DQS3N  
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
VDDS_DDR /  
VDDS_DDR_C  
1
A6  
VDDS_DDR /  
VDDS_DDR_C  
1
A2  
VDDS_DDR /  
VDDS_DDR_C  
1
A3  
DDR1_DQS3P  
DP0_AUXN  
IO  
IO  
VDDA_1P8_SE  
RDES2_4  
AG11  
AF11  
DP0_AUXN  
DP0_AUXP  
1.8 V  
1.8 V  
AUX-PHY  
AUX-PHY  
VDDA_1P8_SE  
RDES2_4  
DP0_AUXP  
IO  
O
DSI0_TXCLKN  
0
1
0
1
VDDA_0P8_DS  
ITX /  
VDDA_0P8_DS  
ITX_C /  
VDDA_1P8_DS  
ITX  
AH13  
AH14  
DSI0_TXCLKN  
DSI0_TXCLKP  
1.8 V  
1.8 V  
D-PHY  
D-PHY  
CSI0_TXCLKN  
DSI0_TXCLKP  
CSI0_TXCLKP  
O
O
O
VDDA_0P8_DS  
ITX /  
VDDA_0P8_DS  
ITX_C /  
VDDA_1P8_DS  
ITX  
Copyright © 2023 Texas Instruments Incorporated  
Submit Document Feedback  
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
English Data Sheet: SPRSP62  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
VDDA_0P8_DS  
ITX /  
VDDA_0P8_DS  
ITX_C /  
VDDA_1P8_DS  
ITX  
AC13  
AH16  
AH17  
AC15  
AG12  
AF13  
AE12  
AD13  
AG13  
DSI0_TXRCALIB  
DSI0_TXRCALIB  
A
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
D-PHY  
D-PHY  
D-PHY  
D-PHY  
D-PHY  
D-PHY  
D-PHY  
D-PHY  
D-PHY  
DSI1_TXCLKN  
CSI1_TXCLKN  
DSI1_TXCLKP  
CSI1_TXCLKP  
0
1
0
1
O
O
O
O
VDDA_0P8_DS  
ITX /  
VDDA_0P8_DS  
ITX_C /  
VDDA_1P8_DS  
ITX  
DSI1_TXCLKN  
DSI1_TXCLKP  
DSI1_TXRCALIB  
DSI0_TXN0  
VDDA_0P8_DS  
ITX /  
VDDA_0P8_DS  
ITX_C /  
VDDA_1P8_DS  
ITX  
VDDA_0P8_DS  
ITX /  
VDDA_0P8_DS  
ITX_C /  
VDDA_1P8_DS  
ITX  
DSI1_TXRCALIB  
A
DSI0_TXN0  
CSI0_TXN0  
DSI0_TXN1  
CSI0_TXN1  
DSI0_TXN2  
CSI0_TXN2  
DSI0_TXN3  
CSI0_TXN3  
DSI0_TXP0  
CSI0_TXP0  
0
1
0
1
0
1
0
1
0
1
IO  
O
O
O
O
O
O
O
IO  
O
VDDA_0P8_DS  
ITX /  
VDDA_0P8_DS  
ITX_C /  
VDDA_1P8_DS  
ITX  
VDDA_0P8_DS  
ITX /  
VDDA_0P8_DS  
ITX_C /  
VDDA_1P8_DS  
ITX  
DSI0_TXN1  
VDDA_0P8_DS  
ITX /  
VDDA_0P8_DS  
ITX_C /  
VDDA_1P8_DS  
ITX  
DSI0_TXN2  
VDDA_0P8_DS  
ITX /  
VDDA_0P8_DS  
ITX_C /  
VDDA_1P8_DS  
ITX  
DSI0_TXN3  
VDDA_0P8_DS  
ITX /  
VDDA_0P8_DS  
ITX_C /  
VDDA_1P8_DS  
ITX  
DSI0_TXP0  
Copyright © 2023 Texas Instruments Incorporated  
English Data Sheet: SPRSP62  
20  
Submit Document Feedback  
Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
 
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
DSI0_TXP1  
CSI0_TXP1  
DSI0_TXP2  
CSI0_TXP2  
DSI0_TXP3  
CSI0_TXP3  
DSI1_TXN0  
CSI1_TXN0  
DSI1_TXN1  
CSI1_TXN1  
DSI1_TXN2  
CSI1_TXN2  
DSI1_TXN3  
CSI1_TXN3  
DSI1_TXP0  
CSI1_TXP0  
DSI1_TXP1  
CSI1_TXP1  
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
O
O
O
O
O
O
IO  
O
O
O
O
O
O
O
IO  
O
O
O
VDDA_0P8_DS  
ITX /  
VDDA_0P8_DS  
ITX_C /  
VDDA_1P8_DS  
ITX  
AF14  
AE13  
AD14  
AG15  
AF16  
AE15  
AD16  
AG16  
AF17  
DSI0_TXP1  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
D-PHY  
D-PHY  
D-PHY  
D-PHY  
D-PHY  
D-PHY  
D-PHY  
D-PHY  
D-PHY  
VDDA_0P8_DS  
ITX /  
VDDA_0P8_DS  
ITX_C /  
VDDA_1P8_DS  
ITX  
DSI0_TXP2  
VDDA_0P8_DS  
ITX /  
VDDA_0P8_DS  
ITX_C /  
VDDA_1P8_DS  
ITX  
DSI0_TXP3  
DSI1_TXN0  
DSI1_TXN1  
DSI1_TXN2  
DSI1_TXN3  
DSI1_TXP0  
DSI1_TXP1  
VDDA_0P8_DS  
ITX /  
VDDA_0P8_DS  
ITX_C /  
VDDA_1P8_DS  
ITX  
VDDA_0P8_DS  
ITX /  
VDDA_0P8_DS  
ITX_C /  
VDDA_1P8_DS  
ITX  
VDDA_0P8_DS  
ITX /  
VDDA_0P8_DS  
ITX_C /  
VDDA_1P8_DS  
ITX  
VDDA_0P8_DS  
ITX /  
VDDA_0P8_DS  
ITX_C /  
VDDA_1P8_DS  
ITX  
VDDA_0P8_DS  
ITX /  
VDDA_0P8_DS  
ITX_C /  
VDDA_1P8_DS  
ITX  
VDDA_0P8_DS  
ITX /  
VDDA_0P8_DS  
ITX_C /  
VDDA_1P8_DS  
ITX  
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
English Data Sheet: SPRSP62  
 
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
DSI1_TXP2  
CSI1_TXP2  
DSI1_TXP3  
CSI1_TXP3  
0
1
0
1
O
O
O
O
VDDA_0P8_DS  
ITX /  
VDDA_0P8_DS  
ITX_C /  
VDDA_1P8_DS  
ITX  
AE16  
AD17  
DSI1_TXP2  
1.8 V  
1.8 V  
D-PHY  
D-PHY  
VDDA_0P8_DS  
ITX /  
VDDA_0P8_DS  
ITX_C /  
VDDA_1P8_DS  
ITX  
DSI1_TXP3  
ECAP0_IN_APWM_OUT  
MCASP4_AXR2  
CPTS0_RFT_CLK  
HYP1_TXFLCLK  
MCAN12_TX  
0
1
IO  
IO  
I
2
3
I
4
O
O
IO  
IO  
IO  
O
O
I
VOUT0_DATA23  
GPMC0_AD5  
5
ECAP0_IN_APWM_OUT  
6
PADCFG:  
PADCONFIG_49  
0x4301C0C4  
AB26  
GPIO0_49  
7
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
SPI6_D0  
8
SYNC0_OUT  
9
TRC_DATA1  
10  
11  
12  
13  
14  
UART2_CTSn  
CPTS0_HW1TSPUSH  
I2C1_SCL  
I
IOD  
I
UART3_RXD  
EMU0  
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_75  
0x4301C12C  
A27  
C26  
EMU0  
0
IO  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
On / Off / Up  
On / Off / Up  
Off / Off / Off  
On / Off / Up  
On / Off / Up  
Off / SS / Off  
0
0
7
LVCMOS  
LVCMOS  
No  
No  
No  
EMU1  
EMU1  
0
15  
0
IO  
O
I
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_76  
0x4301C130  
MCU_OBSCLK0  
EXTINTn  
EXTINTn  
I2C OPEN  
DRAIN  
PADCFG:  
PADCONFIG_0  
0x4301C000  
AG24  
VDDSHV0  
GPIO0_0  
7
IO  
Copyright © 2023 Texas Instruments Incorporated  
English Data Sheet: SPRSP62  
22  
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
EXT_REFCLK1  
MCASP4_ACLKX  
VOUT0_DATA16  
HYP1_TXFLDAT  
MCAN1_RX  
0
1
I
IO  
O
I
2
3
4
I
EXT_REFCLK1  
GPMC0_AD6  
GPIO0_50  
6
IO  
IO  
O
O
O
I
PADCFG:  
PADCONFIG_50  
0x4301C0C8  
AD28  
7
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
SYNC1_OUT  
TRC_CLK  
9
10  
11  
12  
13  
14  
0
UART2_RTSn  
CPTS0_HW2TSPUSH  
I2C1_SDA  
IOD  
O
O
O
OZ  
IO  
IO  
O
O
I
UART3_TXD  
MCAN17_TX  
VOUT0_DATA18  
GPMC0_A14  
GPIO0_11  
2
6
GPIO0_11  
7
PADCFG:  
PADCONFIG_11  
0x4301C02C  
V23  
SPI7_CS3  
8
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
TRC_DATA25  
GPMC0_CSn2  
UART7_RXD  
USB0_DRVVBUS  
MCAN12_RX  
VOUT0_DATA17  
HYP1_RXFLDAT  
VOUT0_DATA22  
GPMC0_AD4  
GPIO0_12  
10  
12  
13  
14  
0
O
I
2
O
O
O
IO  
IO  
IO  
IO  
O
I
3
5
GPIO0_12  
6
PADCFG:  
PADCONFIG_12  
0x4301C030  
T26  
7
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
SPI6_CLK  
8
EQEP1_I  
9
TRC_DATA2  
UART9_CTSn  
UART6_RXD  
I2C0_SCL  
10  
11  
12  
0
I
I2C0_SCL  
IOD  
I2C OPEN  
DRAIN  
PADCFG:  
PADCONFIG_56  
0x4301C0E0  
AH25  
1.8 V/3.3 V  
Off / Off / Off  
On / SS / Off  
7
VDDSHV0  
No  
GPIO0_56  
7
IO  
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
English Data Sheet: SPRSP62  
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
I2C0_SDA  
PADCFG:  
PADCONFIG_57  
0x4301C0E4  
I2C0_SDA  
GPIO0_57  
0
7
IOD  
IO  
I2C OPEN  
DRAIN  
AE24  
1.8 V/3.3 V  
Off / Off / Off  
On / SS / Off  
7
VDDSHV0  
No  
MCAN0_RX  
0
1
I
IO  
O
MCASP4_AXR1  
VOUT0_DATA3  
GPMC0_AD15  
GPIO0_26  
2
6
IO  
IO  
IO  
IO  
O
MCAN0_RX  
7
PADCFG:  
PADCONFIG_26  
0x4301C068  
U28  
SPI5_CS0  
8
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
EHRPWM0_A  
TRC_DATA16  
UART2_TXD  
UART6_RTSn  
SPI7_D0  
9
10  
11  
12  
13  
0
O
O
IO  
O
MCAN0_TX  
MCASP2_AXR2  
VOUT0_DATA4  
GPMC0_AD14  
GPIO0_25  
1
IO  
O
2
6
IO  
IO  
IO  
IO  
O
MCAN0_TX  
7
PADCFG:  
PADCONFIG_25  
0x4301C064  
W28  
SPI5_CS1  
8
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
EHRPWM0_B  
TRC_DATA11  
UART2_RXD  
UART6_CTSn  
I2C3_SCL  
9
10  
11  
12  
13  
0
I
I
IOD  
I
MCAN1_RX  
MCASP4_AXR3  
VOUT0_DATA1  
VOUT0_DATA19  
1
IO  
O
2
5
O
MCAN1_RX  
GPMC0_BE0n_CLE  
GPIO0_28  
6
O
PADCFG:  
PADCONFIG_28  
0x4301C070  
R27  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
7
IO  
IO  
I
SPI5_D0  
8
EHRPWM0_SYNCI  
TRC_DATA5  
9
10  
11  
O
UART3_RTSn  
O
Copyright © 2023 Texas Instruments Incorporated  
English Data Sheet: SPRSP62  
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Submit Document Feedback  
Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
MCAN1_TX  
0
1
O
IO  
I
MCASP4_AFSX  
VOUT0_EXTPCLKIN  
HYP1_TXPMCLK  
DSS_FSYNC0  
GPMC0_AD7  
GPIO0_27  
2
3
O
MCAN1_TX  
4
O
PADCFG:  
PADCONFIG_27  
0x4301C06C  
V26  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
6
IO  
IO  
I
7
EHRPWM_TZn_IN5  
TRC_CTL  
9
10  
11  
0
O
UART6_TXD  
MCAN2_RX  
O
I
AUDIO_EXT_REFCLK1  
VOUT0_PCLK  
GPMC0_CSn1  
GPIO0_30  
1
IO  
O
2
6
O
MCAN2_RX  
7
IO  
IO  
IO  
O
PADCFG:  
PADCONFIG_30  
0x4301C078  
Y25  
SPI6_CS1  
8
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
EHRPWM4_B  
TRC_DATA17  
UART3_TXD  
GPMC0_DIR  
I2C5_SDA  
9
10  
11  
12  
13  
0
O
O
IOD  
O
MCAN2_TX  
MCASP2_AXR3  
VOUT0_DATA0  
VOUT0_DATA18  
GPMC0_WAIT0  
GPIO0_29  
1
IO  
O
2
5
O
6
I
MCAN2_TX  
7
IO  
IO  
IO  
O
PADCFG:  
PADCONFIG_29  
0x4301C074  
R28  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
SPI6_D1  
8
EHRPWM1_B  
TRC_DATA3  
UART3_RXD  
GPMC0_DIR  
I2C5_SCL  
9
10  
11  
12  
13  
I
O
IOD  
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Submit Document Feedback  
25  
Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
English Data Sheet: SPRSP62  
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
MCAN12_RX  
UART0_DCDn  
DSS_FSYNC1  
GPMC0_A23  
GPIO0_2  
0
1
I
I
3
O
MCAN12_RX  
6
OZ  
IO  
O
PADCFG:  
PADCONFIG_2  
0x4301C008  
AC24  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
VDDSHV2  
LVCMOS  
LVCMOS  
LVCMOS  
Yes  
Yes  
Yes  
7
TRC_CTL  
10  
11  
12  
0
UART5_RXD  
GPMC0_CSn3  
MCAN12_TX  
DSS_FSYNC0  
GPMC0_A24  
GPIO0_1  
I
O
O
3
O
MCAN12_TX  
6
OZ  
IO  
O
PADCFG:  
PADCONFIG_1  
0x4301C004  
W25  
7
VDDSHV2  
TRC_CLK  
10  
11  
12  
0
UART5_TXD  
GPMC0_CLK  
MCAN13_RX  
UART0_DTRn  
DSS_FSYNC3  
GPMC0_A21  
GPIO0_4  
O
IO  
I
1
O
3
O
MCAN13_RX  
6
OZ  
IO  
IOD  
O
PADCFG:  
PADCONFIG_4  
0x4301C010  
AF28  
VDDSHV2  
7
I2C4_SDA  
8
TRC_DATA1  
UART6_TXD  
MCAN13_TX  
UART0_DSRn  
DSS_FSYNC2  
GPMC0_A22  
GPIO0_3  
10  
11  
0
O
O
1
I
3
O
MCAN13_TX  
6
OZ  
IO  
O
PADCFG:  
PADCONFIG_3  
0x4301C00C  
AE28  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
7
TRC_DATA0  
UART4_TXD  
GPMC0_WAIT2  
10  
11  
12  
O
I
Copyright © 2023 Texas Instruments Incorporated  
English Data Sheet: SPRSP62  
26  
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
MCAN14_RX  
VOUT0_DATA23  
GPMC0_A19  
GPIO0_6  
0
2
I
O
MCAN14_RX  
6
OZ  
IO  
IOD  
O
PADCFG:  
PADCONFIG_6  
0x4301C018  
W23  
AD25  
AA23  
Y24  
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
VDDSHV2  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
Yes  
Yes  
Yes  
Yes  
Yes  
I2C5_SDA  
8
TRC_DATA3  
UART9_TXD  
MCAN14_TX  
UART0_RIn  
GPMC0_A20  
GPIO0_5  
10  
11  
0
O
O
1
I
MCAN14_TX  
6
OZ  
IO  
IOD  
O
PADCFG:  
PADCONFIG_5  
0x4301C014  
7
VDDSHV2  
VDDSHV2  
VDDSHV2  
VDDSHV2  
I2C4_SCL  
8
TRC_DATA2  
UART6_RXD  
MCAN15_RX  
VOUT0_DATA21  
GPMC0_A17  
GPIO0_8  
10  
11  
0
I
I
2
O
MCAN15_RX  
6
OZ  
IO  
IO  
O
PADCFG:  
PADCONFIG_8  
0x4301C020  
7
SPI0_CS2  
8
TRC_DATA22  
I2C1_SCL  
10  
12  
0
IOD  
O
MCAN15_TX  
VOUT0_DATA22  
GPMC0_A18  
GPIO0_7  
2
O
MCAN15_TX  
6
OZ  
IO  
IOD  
O
PADCFG:  
PADCONFIG_7  
0x4301C01C  
7
I2C5_SCL  
8
TRC_DATA21  
UART9_RXD  
MCAN16_RX  
VOUT0_DATA19  
GPMC0_A15  
GPIO0_10  
10  
11  
0
I
I
2
O
MCAN16_RX  
6
OZ  
IO  
IO  
O
PADCFG:  
PADCONFIG_10  
0x4301C028  
AB24  
7
SPI0_CS3  
8
TRC_DATA24  
GPMC0_WAIT1  
10  
12  
I
Copyright © 2023 Texas Instruments Incorporated  
Submit Document Feedback  
27  
Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
English Data Sheet: SPRSP62  
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
MCAN16_TX  
VOUT0_DATA20  
GPMC0_A16  
GPIO0_9  
0
2
O
O
MCAN16_TX  
6
OZ  
IO  
IO  
O
PADCFG:  
PADCONFIG_9  
0x4301C024  
Y28  
7
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
SPI1_CS3  
8
TRC_DATA23  
I2C1_SDA  
10  
12  
0
IOD  
O
MCAN5_TX  
MCASP0_ACLKX  
VOUT0_DATA15  
HYP0_RXFLCLK  
GPMC0_AD0  
GPIO0_14  
1
IO  
O
2
MCASP0_ACLKX  
3
O
PADCFG:  
PADCONFIG_14  
0x4301C038  
AB28  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
6
IO  
IO  
I
7
EHRPWM_TZn_IN2  
UART8_RXD  
MCAN5_RX  
9
11  
0
I
I
MCASP0_AFSX  
VOUT0_DATA14  
HYP0_RXFLDAT  
GPMC0_AD1  
GPIO0_15  
1
IO  
O
2
MCASP0_AFSX  
3
O
PADCFG:  
PADCONFIG_15  
0x4301C03C  
U27  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
6
IO  
IO  
IO  
O
7
EHRPWM2_B  
UART8_TXD  
MCAN10_RX  
MCASP1_ACLKX  
DP0_HPD  
9
11  
0
I
1
IO  
I
3
GPMC0_A11  
RGMII1_RD0  
GPIO0_46  
5
OZ  
I
MCASP1_ACLKX  
6
PADCFG:  
PADCONFIG_46  
0x4301C0B8  
AA24  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
7
IO  
IO  
O
EQEP0_S  
9
UART4_RTSn  
SPI3_CS3  
11  
12  
13  
IO  
O
UART9_RTSn  
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English Data Sheet: SPRSP62  
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TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
MCAN11_TX  
MCASP1_AFSX  
GPMC0_A12  
MDIO0_MDIO  
GPIO0_47  
0
1
O
IO  
OZ  
IO  
IO  
IO  
IO  
I
5
MCASP1_AFSX  
6
PADCFG:  
PADCONFIG_47  
0x4301C0BC  
V28  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
7
SPI3_CS0  
8
EQEP0_I  
9
UART0_RXD  
MCAN8_RX  
MCASP2_ACLKX  
VOUT0_DATA8  
HYP0_TXPMCLK  
VOUT0_DATA20  
GPMC0_AD10  
GPIO0_21  
11  
0
I
1
IO  
O
2
3
O
5
O
MCASP2_ACLKX  
6
IO  
IO  
IO  
IO  
O
PADCFG:  
PADCONFIG_21  
0x4301C054  
Y27  
7
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
SPI5_CS2  
8
EQEP2_S  
9
TRC_DATA4  
UART1_RXD  
SPI7_CS1  
10  
11  
13  
14  
0
I
IO  
O
SYNC3_OUT  
MCAN9_TX  
O
MCASP2_AFSX  
VOUT0_DATA7  
HYP0_TXPMDAT  
GPMC0_AD11  
GPIO0_22  
1
IO  
O
2
3
O
MCASP2_AFSX  
6
IO  
IO  
IO  
O
PADCFG:  
PADCONFIG_22  
0x4301C058  
AA27  
7
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
SPI5_CS3  
8
EHRPWM_SOCA  
TRC_DATA9  
UART1_TXD  
SPI7_CS2  
9
10  
11  
13  
O
O
IO  
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
English Data Sheet: SPRSP62  
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
MCAN6_TX  
0
1
O
IO  
O
I
MCASP0_AXR0  
VOUT0_DATA13  
HYP0_TXFLCLK  
GPMC0_AD2  
GPIO0_16  
2
3
6
IO  
IO  
IO  
IO  
O
I
MCASP0_AXR0  
7
PADCFG:  
PADCONFIG_16  
0x4301C040  
AC28  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
SPI2_CS2  
8
EHRPWM2_A  
TRC_DATA14  
UART4_RXD  
SPI7_CLK  
9
10  
11  
13  
14  
0
IO  
I
UART8_CTSn  
MCAN6_RX  
I
MCASP0_AXR1  
VOUT0_DATA12  
HYP0_TXFLDAT  
OBSCLK1  
1
IO  
O
I
2
3
4
O
IO  
IO  
IO  
O
O
O
IO  
O
O
IO  
O
O
O
IO  
I
MCASP0_AXR1  
GPMC0_AD3  
GPIO0_17  
6
PADCFG:  
PADCONFIG_17  
0x4301C044  
Y26  
7
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
SPI2_CS3  
8
EHRPWM0_SYNCO  
TRC_DATA12  
UART4_TXD  
9
10  
11  
13  
14  
0
SPI7_CS0  
UART8_RTSn  
MCAN7_TX  
MCASP0_AXR2  
VOUT0_DATA11  
HYP1_RXFLCLK  
GPMC0_ADVn_ALE  
GPIO0_18  
1
2
3
MCASP0_AXR2  
6
PADCFG:  
PADCONFIG_18  
0x4301C048  
AB27  
7
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
EQEP2_A  
9
TRC_DATA10  
UART4_CTSn  
GPMC0_WPn  
UART9_CTSn  
10  
11  
12  
13  
O
I
O
I
Copyright © 2023 Texas Instruments Incorporated  
English Data Sheet: SPRSP62  
30  
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
MCAN3_TX  
0
1
O
IO  
O
MCASP0_AXR3  
VOUT0_DATA2  
GPMC0_BE1n  
GPIO0_31  
2
6
O
MCASP0_AXR3  
7
IO  
IO  
I
PADCFG:  
PADCONFIG_31  
0x4301C07C  
T27  
SPI5_CLK  
8
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
EHRPWM_TZn_IN0  
TRC_DATA7  
9
10  
11  
12  
13  
0
O
UART3_CTSn  
SPI3_CS1  
I
IO  
IO  
I
SPI7_D1  
MCAN3_RX  
MCASP0_AXR4  
VOUT0_HSYNC  
HYP1_TXPMDAT  
VOUT0_VP0_HSYNC  
VOUT0_VP2_HSYNC  
GPMC0_OEn_REn  
GPIO0_32  
1
IO  
O
2
3
O
4
O
MCASP0_AXR4  
5
O
PADCFG:  
PADCONFIG_32  
0x4301C080  
U26  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
6
O
7
IO  
IO  
IO  
O
SPI6_CS2  
8
EHRPWM5_B  
TRC_DATA18  
I2C4_SDA  
9
10  
13  
0
IOD  
O
MCAN4_TX  
MCASP0_AXR5  
VOUT0_DE  
1
IO  
O
2
MCASP1_ACLKR  
VOUT0_VP0_DE  
VOUT0_VP2_DE  
GPMC0_CSn0  
GPIO0_33  
3
IO  
O
4
MCASP0_AXR5  
5
O
PADCFG:  
PADCONFIG_33  
0x4301C084  
AA28  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
6
O
7
IO  
IO  
IO  
O
SPI6_CS3  
8
EHRPWM5_A  
TRC_DATA19  
I2C4_SCL  
9
10  
13  
IOD  
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
English Data Sheet: SPRSP62  
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
MCAN4_RX  
0
1
I
IO  
O
MCASP0_AXR6  
VOUT0_VSYNC  
MCASP1_AFSR  
2
3
IO  
O
VOUT0_VP0_VSYNC  
VOUT0_VP2_VSYNC  
GPMC0_CLKOUT  
GPIO0_34  
4
MCASP0_AXR6  
5
O
PADCFG:  
PADCONFIG_34  
0x4301C088  
AD27  
6
O
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
7
IO  
IO  
I
SPI3_CS2  
8
EHRPWM_TZn_IN4  
TRC_DATA20  
SPI5_D1  
9
10  
11  
12  
0
O
IO  
O
GPMC0_FCLK_MUX  
MCAN5_TX  
O
MCASP0_AXR7  
MCASP4_ACLKR  
GPMC0_A0  
1
IO  
IO  
OZ  
O
3
5
MCASP0_AXR7  
RGMII1_TD0  
6
PADCFG:  
PADCONFIG_35  
0x4301C08C  
T25  
GPIO0_35  
7
IO  
OZ  
IO  
I
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
GPMC0_A14  
8
EHRPWM3_A  
UART4_RXD  
9
11  
12  
14  
0
GPMC0_CSn2  
USB0_DRVVBUS  
MCAN5_RX  
O
O
I
MCASP0_AXR8  
MCASP4_AFSR  
GPMC0_A1  
1
IO  
IO  
OZ  
O
3
MCASP0_AXR8  
5
PADCFG:  
PADCONFIG_36  
0x4301C090  
W24  
RGMII1_TD1  
6
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
GPIO0_36  
7
IO  
I
RMII1_RXD0  
8
EHRPWM_TZn_IN3  
UART4_TXD  
9
I
11  
O
Copyright © 2023 Texas Instruments Incorporated  
English Data Sheet: SPRSP62  
32  
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
MCAN6_TX  
0
1
O
IO  
IO  
OZ  
O
IO  
I
MCASP0_AXR9  
MCASP4_AXR4  
GPMC0_A2  
2
MCASP0_AXR9  
5
PADCFG:  
PADCONFIG_37  
0x4301C094  
AA25  
RGMII1_TD2  
GPIO0_37  
6
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
VDDSHV2  
LVCMOS  
LVCMOS  
LVCMOS  
Yes  
Yes  
Yes  
7
RMII1_RXD1  
8
EHRPWM3_SYNCO  
UART4_CTSn  
MCAN6_RX  
9
O
I
11  
0
I
MCASP0_AXR10  
GPMC0_A3  
1
IO  
OZ  
O
IO  
I
5
MCASP0_AXR10  
RGMII1_TD3  
GPIO0_38  
6
PADCFG:  
PADCONFIG_38  
0x4301C098  
V25  
VDDSHV2  
7
RMII1_CRS_DV  
EHRPWM3_SYNCI  
UART4_RTSn  
MCAN7_TX  
8
9
I
11  
0
O
O
IO  
OZ  
O
IO  
I
MCASP0_AXR11  
GPMC0_A4  
1
5
MCASP0_AXR11  
RGMII1_TX_CTL  
GPIO0_39  
6
PADCFG:  
PADCONFIG_39  
0x4301C09C  
T24  
7
VDDSHV2  
RMII1_RX_ER  
EHRPWM3_B  
SPI2_CS1  
8
9
IO  
IO  
I
10  
11  
0
UART5_RXD  
MCAN7_RX  
I
MCASP0_AXR12  
MCASP2_ACLKR  
GPMC0_A5  
1
IO  
IO  
OZ  
I
3
5
MCASP0_AXR12  
RGMII1_RD1  
GPIO0_40  
6
PADCFG:  
PADCONFIG_40  
0x4301C0A0  
AB25  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
7
IO  
O
O
IO  
O
RMII1_TXD0  
EHRPWM_SOCB  
SPI2_CLK  
8
9
10  
11  
UART5_TXD  
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Submit Document Feedback  
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
English Data Sheet: SPRSP62  
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
MCAN8_TX  
0
1
O
IO  
IO  
OZ  
I
MCASP0_AXR13  
MCASP2_AFSR  
GPMC0_A6  
3
5
MCASP0_AXR13  
RGMII1_RD2  
GPIO0_41  
6
PADCFG:  
PADCONFIG_41  
0x4301C0A4  
T23  
7
IO  
I
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
VDDSHV2  
LVCMOS  
LVCMOS  
LVCMOS  
Yes  
Yes  
Yes  
RMII_REF_CLK  
EHRPWM4_A  
SPI2_CS0  
8
9
IO  
IO  
I
10  
11  
13  
0
UART5_CTSn  
UART7_RXD  
MCAN8_RX  
MCASP0_AXR14  
MCASP2_AXR4  
MCASP0_ACLKR  
GPMC0_A7  
I
I
1
IO  
IO  
IO  
OZ  
I
2
3
5
MCASP0_AXR14  
RGMII1_RD3  
GPIO0_42  
6
PADCFG:  
PADCONFIG_42  
0x4301C0A8  
U24  
VDDSHV2  
7
IO  
IO  
I
CLKOUT  
8
EQEP0_A  
9
SPI2_D0  
10  
11  
13  
0
IO  
O
O
O
IO  
IO  
OZ  
I
UART5_RTSn  
UART7_TXD  
MCAN9_TX  
MCASP0_AXR15  
MCASP0_AFSR  
GPMC0_A8  
1
3
5
MCASP0_AXR15  
RGMII1_RX_CTL  
GPIO0_43  
6
PADCFG:  
PADCONFIG_43  
0x4301C0AC  
AC25  
7
IO  
O
I
VDDSHV2  
RMII1_TX_EN  
EQEP0_B  
8
9
SPI2_D1  
10  
11  
13  
IO  
I
UART8_RXD  
I2C1_SCL  
IOD  
Copyright © 2023 Texas Instruments Incorporated  
English Data Sheet: SPRSP62  
34  
Submit Document Feedback  
Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
MCAN11_RX  
MCASP1_AXR0  
GPMC0_A13  
MDIO0_MDC  
GPIO0_48  
0
1
I
IO  
OZ  
O
IO  
IO  
IO  
O
I
5
6
MCASP1_AXR0  
7
PADCFG:  
PADCONFIG_48  
0x4301C0C0  
T28  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
SPI3_CLK  
8
EQEP1_S  
9
UART0_TXD  
GPMC0_WAIT3  
SYNC2_OUT  
MCAN7_RX  
MCASP1_AXR1  
VOUT0_DATA10  
HYP1_RXPMCLK  
GPMC0_AD8  
GPIO0_19  
11  
12  
14  
0
O
I
1
IO  
O
I
2
3
6
IO  
IO  
IO  
I
MCASP1_AXR1  
7
PADCFG:  
PADCONFIG_19  
0x4301C04C  
V27  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
SPI3_D0  
8
EHRPWM_TZn_IN1  
TRC_DATA8  
UART0_CTSn  
UART9_RXD  
I2C2_SCL  
9
10  
11  
12  
13  
0
O
I
I
IOD  
O
IO  
O
I
MCAN8_TX  
MCASP1_AXR2  
VOUT0_DATA9  
HYP1_RXPMDAT  
VOUT0_DATA21  
GPMC0_AD9  
GPIO0_20  
1
2
3
5
O
IO  
IO  
IO  
I
MCASP1_AXR2  
6
PADCFG:  
PADCONFIG_20  
0x4301C050  
W27  
7
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
SPI3_D1  
8
EQEP2_B  
9
TRC_DATA6  
UART0_RTSn  
UART9_TXD  
I2C2_SDA  
10  
11  
12  
13  
O
O
O
IOD  
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Submit Document Feedback  
35  
Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
English Data Sheet: SPRSP62  
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
MCAN9_RX  
MCASP1_AXR3  
GPMC0_A9  
0
1
I
IO  
OZ  
I
5
MCASP1_AXR3  
RGMII1_RXC  
GPIO0_44  
6
PADCFG:  
PADCONFIG_44  
0x4301C0B0  
AD26  
7
IO  
O
I
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
RMII1_TXD1  
EQEP1_A  
8
9
UART8_TXD  
I2C1_SDA  
11  
13  
0
O
IOD  
O
IO  
OZ  
O
IO  
I
MCAN10_TX  
MCASP1_AXR4  
GPMC0_A10  
RGMII1_TXC  
GPIO0_45  
1
MCASP1_AXR4  
5
PADCFG:  
PADCONFIG_45  
0x4301C0B4  
U25  
6
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
7
EQEP1_B  
9
UART4_RXD  
MCAN9_RX  
MCASP2_AXR0  
VOUT0_DATA6  
HYP0_RXPMCLK  
GPMC0_AD12  
GPIO0_23  
11  
0
I
I
1
IO  
O
I
2
3
MCASP2_AXR0  
6
IO  
IO  
IO  
O
I
PADCFG:  
PADCONFIG_23  
0x4301C05C  
AA26  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
7
EQEP2_I  
9
TRC_DATA15  
UART1_CTSn  
UART6_RXD  
MCAN17_RX  
MCASP2_AXR1  
VOUT0_DATA5  
HYP0_RXPMDAT  
GPMC0_AD13  
GPIO0_24  
10  
11  
12  
0
I
I
1
IO  
O
I
2
3
MCASP2_AXR1  
6
IO  
IO  
IO  
O
O
O
IOD  
PADCFG:  
PADCONFIG_24  
0x4301C060  
AC27  
7
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
Yes  
EHRPWM1_A  
TRC_DATA13  
UART1_RTSn  
UART6_TXD  
I2C3_SDA  
9
10  
11  
12  
13  
Copyright © 2023 Texas Instruments Incorporated  
English Data Sheet: SPRSP62  
36  
Submit Document Feedback  
Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
MCU_ADC0_AIN0  
MCU_ADC0_AIN0  
WKUP_GPIO0_71  
MCU_ADC0_AIN1  
WKUP_GPIO0_72  
MCU_ADC0_AIN2  
WKUP_GPIO0_73  
MCU_ADC0_AIN3  
WKUP_GPIO0_74  
MCU_ADC0_AIN4  
WKUP_GPIO0_75  
MCU_ADC0_AIN5  
WKUP_GPIO0_76  
MCU_ADC0_AIN6  
WKUP_GPIO0_77  
MCU_ADC0_AIN7  
WKUP_GPIO0_78  
MCU_ADC1_AIN0  
WKUP_GPIO0_79  
MCU_ADC1_AIN1  
WKUP_GPIO0_80  
MCU_ADC1_AIN2  
WKUP_GPIO0_81  
0
7
0
7
0
7
0
7
0
7
0
7
0
7
0
7
0
7
0
7
0
7
A
I
PADCFG:  
WKUP_PADCONFIG_77  
0x4301C134  
L25  
K25  
M24  
L24  
L27  
K24  
M27  
M26  
P25  
R25  
P28  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
0
VDDA_ADC0  
ADC12B  
ADC12B  
ADC12B  
ADC12B  
ADC12B  
ADC12B  
ADC12B  
ADC12B  
ADC12B  
ADC12B  
ADC12B  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
MCU_ADC0_AIN1  
A
I
PADCFG:  
WKUP_PADCONFIG_78  
0x4301C138  
0
0
0
0
0
0
0
0
0
0
VDDA_ADC0  
VDDA_ADC0  
VDDA_ADC0  
VDDA_ADC0  
VDDA_ADC0  
VDDA_ADC0  
VDDA_ADC0  
VDDA_ADC1  
VDDA_ADC1  
VDDA_ADC1  
MCU_ADC0_AIN2  
A
I
PADCFG:  
WKUP_PADCONFIG_79  
0x4301C13C  
MCU_ADC0_AIN3  
A
I
PADCFG:  
WKUP_PADCONFIG_80  
0x4301C140  
MCU_ADC0_AIN4  
A
I
PADCFG:  
WKUP_PADCONFIG_81  
0x4301C144  
MCU_ADC0_AIN5  
A
I
PADCFG:  
WKUP_PADCONFIG_82  
0x4301C148  
MCU_ADC0_AIN6  
A
I
PADCFG:  
WKUP_PADCONFIG_83  
0x4301C14C  
MCU_ADC0_AIN7  
A
I
PADCFG:  
WKUP_PADCONFIG_84  
0x4301C150  
MCU_ADC1_AIN0  
A
I
PADCFG:  
WKUP_PADCONFIG_85  
0x4301C154  
MCU_ADC1_AIN1  
A
I
PADCFG:  
WKUP_PADCONFIG_86  
0x4301C158  
MCU_ADC1_AIN2  
A
I
PADCFG:  
WKUP_PADCONFIG_87  
0x4301C15C  
Copyright © 2023 Texas Instruments Incorporated  
Submit Document Feedback  
37  
Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
English Data Sheet: SPRSP62  
 
 
 
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
MCU_ADC1_AIN3  
MCU_ADC1_AIN3  
WKUP_GPIO0_82  
MCU_ADC1_AIN4  
WKUP_GPIO0_83  
MCU_ADC1_AIN5  
WKUP_GPIO0_84  
MCU_ADC1_AIN6  
WKUP_GPIO0_85  
MCU_ADC1_AIN7  
WKUP_GPIO0_86  
MCU_I2C0_SCL  
WKUP_GPIO0_65  
MCU_I2C0_SDA  
WKUP_GPIO0_87  
MCU_MCAN0_RX  
WKUP_GPIO0_61  
MCU_MCAN0_TX  
WKUP_GPIO0_60  
0
7
0
7
0
7
0
7
0
7
0
7
0
7
0
7
0
7
0
7
0
7
A
I
PADCFG:  
WKUP_PADCONFIG_88  
0x4301C160  
P27  
N25  
P26  
N26  
N27  
G24  
J25  
1.8 V  
1.8 V  
0
VDDA_ADC1  
ADC12B  
ADC12B  
ADC12B  
ADC12B  
ADC12B  
No  
No  
MCU_ADC1_AIN4  
A
PADCFG:  
WKUP_PADCONFIG_89  
0x4301C164  
0
0
0
0
VDDA_ADC1  
VDDA_ADC1  
VDDA_ADC1  
VDDA_ADC1  
I
MCU_ADC1_AIN5  
A
PADCFG:  
WKUP_PADCONFIG_90  
0x4301C168  
1.8 V  
No  
I
MCU_ADC1_AIN6  
A
PADCFG:  
WKUP_PADCONFIG_91  
0x4301C16C  
1.8 V  
No  
I
MCU_ADC1_AIN7  
A
PADCFG:  
WKUP_PADCONFIG_92  
0x4301C170  
1.8 V  
No  
I
MCU_I2C0_SCL  
IOD  
IO  
IOD  
IO  
I
VDDSHV0_MC  
U
I2C OPEN  
DRAIN  
PADCFG:  
WKUP_PADCONFIG_66  
0x4301C108  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
On / SS / Off  
On / SS / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
0
0
7
7
7
7
Yes  
Yes  
Yes  
Yes  
No  
MCU_I2C0_SDA  
VDDSHV0_MC  
U
I2C OPEN  
DRAIN  
PADCFG:  
WKUP_PADCONFIG_67  
0x4301C10C  
MCU_MCAN0_RX  
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_47  
0x4301C0BC  
E28  
E27  
A21  
A22  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
IO  
O
IO  
O
IO  
IO  
IO  
MCU_MCAN0_TX  
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_46  
0x4301C0B8  
MCU_MDIO0_MDC  
MCU_MDIO0_MDC  
WKUP_GPIO0_53  
MCU_MDIO0_MDIO  
WKUP_GPIO0_52  
VDDSHV2_MC  
U
PADCFG:  
WKUP_PADCONFIG_39  
0x4301C09C  
MCU_MDIO0_MDIO  
VDDSHV2_MC  
U
PADCFG:  
WKUP_PADCONFIG_38  
0x4301C098  
No  
Copyright © 2023 Texas Instruments Incorporated  
English Data Sheet: SPRSP62  
38  
Submit Document Feedback  
Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
 
 
 
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
MCU_OSPI0_CLK  
MCU_OSPI0_CLK  
0
1
O
O
VDDSHV1_MC  
U
PADCFG:  
WKUP_PADCONFIG_0  
0x4301C000  
MCU_HYPERBUS0_CK  
WKUP_GPIO0_16  
D19  
E18  
E20  
A19  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
On / Off / Off  
Off / Off / Off  
7
7
7
7
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
No  
No  
No  
No  
7
IO  
MCU_OSPI0_DQS  
MCU_OSPI0_DQS  
0
1
I
VDDSHV1_MC  
U
PADCFG:  
WKUP_PADCONFIG_2  
0x4301C008  
MCU_HYPERBUS0_RWDS  
IO  
WKUP_GPIO0_18  
7
IO  
MCU_OSPI0_LBCLKO  
MCU_OSPI0_LBCLKO  
0
1
IO  
O
VDDSHV1_MC  
U
PADCFG:  
WKUP_PADCONFIG_1  
0x4301C004  
MCU_HYPERBUS0_CKn  
WKUP_GPIO0_17  
MCU_OSPI1_CLK  
7
0
IO  
O
MCU_OSPI1_CLK  
VDDSHV1_MC  
U
PADCFG:  
WKUP_PADCONFIG_16  
0x4301C040  
WKUP_GPIO0_31  
7
IO  
MCU_OSPI1_DQS  
0
1
2
6
7
0
1
2
6
7
0
1
I
O
I
MCU_OSPI1_DQS  
MCU_OSPI0_CSn3  
VDDSHV1_MC  
U
PADCFG:  
WKUP_PADCONFIG_18  
0x4301C048  
B19  
B20  
MCU_HYPERBUS0_INTn  
MCU_OSPI0_ECC_FAIL  
WKUP_GPIO0_33  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
7
LVCMOS  
LVCMOS  
No  
No  
I
IO  
IO  
O
I
MCU_OSPI1_LBCLKO  
MCU_OSPI0_CSn2  
MCU_OSPI1_LBCLKO  
VDDSHV1_MC  
U
PADCFG:  
WKUP_PADCONFIG_17  
0x4301C044  
MCU_HYPERBUS0_RESETOn  
MCU_OSPI0_RESET_OUT0  
WKUP_GPIO0_32  
1.8 V/3.3 V  
Off / Off / Off  
On / Off / Off  
O
IO  
O
O
MCU_OSPI0_CSn0  
MCU_OSPI0_CSn0  
VDDSHV1_MC  
U
PADCFG:  
WKUP_PADCONFIG_11  
0x4301C02C  
MCU_HYPERBUS0_CSn0  
F15  
G17  
1.8 V/3.3 V  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
LVCMOS  
LVCMOS  
No  
No  
WKUP_GPIO0_27  
7
IO  
MCU_OSPI0_CSn1  
MCU_OSPI0_CSn1  
0
1
O
O
VDDSHV1_MC  
U
PADCFG:  
WKUP_PADCONFIG_12  
0x4301C030  
MCU_HYPERBUS0_RESETn  
WKUP_GPIO0_28  
7
IO  
MCU_OSPI0_CSn2  
0
1
2
3
4
6
7
O
O
I
MCU_OSPI0_CSn2  
MCU_OSPI0_CSn2  
MCU_HYPERBUS0_RESETOn  
MCU_HYPERBUS0_WPn  
MCU_HYPERBUS0_CSn1  
MCU_OSPI0_RESET_OUT0  
WKUP_GPIO0_29  
VDDSHV1_MC  
U
PADCFG:  
WKUP_PADCONFIG_14  
0x4301C038  
F14  
O
O
O
IO  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
LVCMOS  
No  
Copyright © 2023 Texas Instruments Incorporated  
Submit Document Feedback  
39  
Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
English Data Sheet: SPRSP62  
 
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
MCU_OSPI0_CSn3  
0
1
2
3
5
6
7
0
1
7
O
O
I
MCU_OSPI0_CSn3  
MCU_OSPI0_CSn3  
MCU_HYPERBUS0_INTn  
MCU_HYPERBUS0_WPn  
MCU_OSPI0_RESET_OUT1  
MCU_OSPI0_ECC_FAIL  
WKUP_GPIO0_30  
VDDSHV1_MC  
U
PADCFG:  
WKUP_PADCONFIG_15  
0x4301C03C  
F17  
O
O
I
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
LVCMOS  
No  
IO  
IO  
IO  
IO  
MCU_OSPI0_D0  
MCU_OSPI0_D0  
MCU_HYPERBUS0_DQ0  
WKUP_GPIO0_19  
VDDSHV1_MC  
U
PADCFG:  
WKUP_PADCONFIG_3  
0x4301C00C  
C19  
F16  
1.8 V/3.3 V  
On / Off / Off  
On / Off / Off  
7
7
LVCMOS  
LVCMOS  
No  
No  
BOOTST  
RAP  
BOOTMODE00  
I
MCU_OSPI0_D1  
0
1
7
IO  
IO  
IO  
MCU_OSPI0_D1  
MCU_HYPERBUS0_DQ1  
WKUP_GPIO0_20  
VDDSHV1_MC  
U
PADCFG:  
WKUP_PADCONFIG_4  
0x4301C010  
1.8 V/3.3 V  
On / Off / Off  
On / Off / Off  
BOOTST  
RAP  
BOOTMODE01  
I
MCU_OSPI0_D2  
MCU_OSPI0_D2  
0
1
IO  
IO  
VDDSHV1_MC  
U
PADCFG:  
MCU_HYPERBUS0_DQ2  
G15  
F18  
1.8 V/3.3 V  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
LVCMOS  
LVCMOS  
No  
No  
WKUP_PADCONFIG_5  
0x4301C014  
WKUP_GPIO0_21  
7
IO  
MCU_OSPI0_D3  
MCU_OSPI0_D3  
0
1
IO  
IO  
VDDSHV1_MC  
U
PADCFG:  
WKUP_PADCONFIG_6  
0x4301C018  
MCU_HYPERBUS0_DQ3  
WKUP_GPIO0_22  
7
IO  
MCU_OSPI0_D4  
0
1
7
IO  
IO  
IO  
MCU_OSPI0_D4  
MCU_HYPERBUS0_DQ4  
WKUP_GPIO0_23  
VDDSHV1_MC  
U
PADCFG:  
WKUP_PADCONFIG_7  
0x4301C01C  
E19  
1.8 V/3.3 V  
On / Off / Off  
On / Off / Off  
7
LVCMOS  
No  
BOOTST  
RAP  
BOOTMODE02  
I
MCU_OSPI0_D5  
0
1
7
IO  
IO  
IO  
MCU_OSPI0_D5  
MCU_HYPERBUS0_DQ5  
WKUP_GPIO0_24  
VDDSHV1_MC  
U
PADCFG:  
WKUP_PADCONFIG_8  
0x4301C020  
G19  
F19  
1.8 V/3.3 V  
1.8 V/3.3 V  
On / Off / Off  
Off / Off / Off  
On / Off / Off  
Off / Off / Off  
7
7
LVCMOS  
LVCMOS  
No  
No  
BOOTST  
RAP  
BOOTMODE03  
I
MCU_OSPI0_D6  
MCU_OSPI0_D6  
0
1
IO  
IO  
VDDSHV1_MC  
U
PADCFG:  
WKUP_PADCONFIG_9  
0x4301C024  
MCU_HYPERBUS0_DQ6  
WKUP_GPIO0_25  
7
IO  
Copyright © 2023 Texas Instruments Incorporated  
English Data Sheet: SPRSP62  
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
MCU_OSPI0_D7  
MCU_OSPI0_D7  
0
1
IO  
IO  
VDDSHV1_MC  
U
PADCFG:  
WKUP_PADCONFIG_10  
0x4301C028  
MCU_HYPERBUS0_DQ7  
WKUP_GPIO0_26  
F20  
D20  
1.8 V/3.3 V  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
LVCMOS  
LVCMOS  
No  
No  
7
0
IO  
O
MCU_OSPI1_CSn0  
MCU_OSPI1_CSn0  
VDDSHV1_MC  
U
PADCFG:  
WKUP_PADCONFIG_23  
0x4301C05C  
WKUP_GPIO0_38  
7
IO  
MCU_OSPI1_CSn1  
MCU_HYPERBUS0_WPn  
MCU_TIMER_IO0  
0
1
2
3
4
5
6
7
0
O
O
IO  
O
MCU_OSPI1_CSn1  
MCU_HYPERBUS0_CSn1  
MCU_UART0_RTSn  
MCU_SPI0_CS2  
VDDSHV1_MC  
U
PADCFG:  
WKUP_PADCONFIG_24  
0x4301C060  
C21  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
LVCMOS  
No  
O
IO  
O
MCU_OSPI0_RESET_OUT1  
WKUP_GPIO0_39  
IO  
IO  
MCU_OSPI1_D0  
MCU_OSPI1_D0  
VDDSHV1_MC  
U
PADCFG:  
WKUP_PADCONFIG_19  
0x4301C04C  
D21  
G20  
1.8 V/3.3 V  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
LVCMOS  
LVCMOS  
No  
No  
WKUP_GPIO0_34  
7
IO  
MCU_OSPI1_D1  
MCU_UART0_RXD  
MCU_SPI1_CS1  
WKUP_GPIO0_35  
MCU_OSPI1_D2  
MCU_UART0_TXD  
MCU_SPI1_CS2  
WKUP_GPIO0_36  
MCU_OSPI1_D3  
MCU_UART0_CTSn  
MCU_SPI0_CS1  
WKUP_GPIO0_37  
MCU_PORz  
0
4
5
7
0
4
5
7
0
4
5
7
IO  
I
MCU_OSPI1_D1  
VDDSHV1_MC  
U
PADCFG:  
WKUP_PADCONFIG_20  
0x4301C050  
IO  
IO  
IO  
O
IO  
IO  
IO  
I
MCU_OSPI1_D2  
VDDSHV1_MC  
U
PADCFG:  
WKUP_PADCONFIG_21  
0x4301C054  
C20  
A20  
1.8 V/3.3 V  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
LVCMOS  
LVCMOS  
No  
No  
MCU_OSPI1_D3  
VDDSHV1_MC  
U
PADCFG:  
WKUP_PADCONFIG_22  
0x4301C058  
IO  
IO  
I
G23  
A23  
MCU_PORz  
1.8 V  
VDDA_WKUP  
FS_RESET  
LVCMOS  
No  
No  
MCU_RESETSTATz  
MCU_RESETSTATz  
0
7
O
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_71  
0x4301C11C  
1.8 V/3.3 V  
Off / Low / Off  
On / NA / Up  
Off / SS / Off  
On / Off / Up  
0
0
WKUP_GPIO0_68  
MCU_RESETz  
IO  
I
MCU_RESETz  
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_70  
0x4301C118  
A26  
0
1.8 V/3.3 V  
LVCMOS  
No  
Copyright © 2023 Texas Instruments Incorporated  
Submit Document Feedback  
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
English Data Sheet: SPRSP62  
 
 
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
MCU_RGMII1_RXC  
MCU_RGMII1_RXC  
0
1
I
I
VDDSHV2_MC  
U
PADCFG:  
WKUP_PADCONFIG_33  
0x4301C084  
MCU_RMII1_REF_CLK  
WKUP_GPIO0_47  
D22  
E23  
F21  
F22  
B22  
B21  
C22  
D23  
F23  
G22  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
7
IO  
MCU_RGMII1_RX_CTL  
MCU_RGMII1_RX_CTL  
MCU_RMII1_RX_ER  
0
1
I
I
VDDSHV2_MC  
U
PADCFG:  
WKUP_PADCONFIG_27  
0x4301C06C  
WKUP_GPIO0_41  
7
IO  
MCU_RGMII1_TXC  
MCU_RGMII1_TXC  
MCU_RMII1_TX_EN  
0
1
O
O
VDDSHV2_MC  
U
PADCFG:  
WKUP_PADCONFIG_32  
0x4301C080  
WKUP_GPIO0_46  
7
IO  
MCU_RGMII1_TX_CTL  
MCU_RGMII1_TX_CTL  
MCU_RMII1_CRS_DV  
0
1
O
I
VDDSHV2_MC  
U
PADCFG:  
WKUP_PADCONFIG_26  
0x4301C068  
WKUP_GPIO0_40  
7
IO  
MCU_RGMII1_RD0  
MCU_RGMII1_RD0  
MCU_RMII1_RXD0  
0
1
I
I
VDDSHV2_MC  
U
PADCFG:  
WKUP_PADCONFIG_37  
0x4301C094  
WKUP_GPIO0_51  
7
IO  
MCU_RGMII1_RD1  
MCU_RGMII1_RD1  
MCU_RMII1_RXD1  
0
1
I
I
VDDSHV2_MC  
U
PADCFG:  
WKUP_PADCONFIG_36  
0x4301C090  
WKUP_GPIO0_50  
7
IO  
MCU_RGMII1_RD2  
MCU_RGMII1_RD2  
MCU_TIMER_IO5  
0
1
I
VDDSHV2_MC  
U
PADCFG:  
WKUP_PADCONFIG_35  
0x4301C08C  
IO  
WKUP_GPIO0_62  
7
IO  
MCU_RGMII1_RD3  
MCU_RGMII1_RD3  
MCU_TIMER_IO4  
0
1
I
VDDSHV2_MC  
U
PADCFG:  
WKUP_PADCONFIG_34  
0x4301C088  
IO  
WKUP_GPIO0_48  
7
IO  
MCU_RGMII1_TD0  
MCU_RGMII1_TD0  
MCU_RMII1_TXD0  
0
1
O
O
VDDSHV2_MC  
U
PADCFG:  
WKUP_PADCONFIG_31  
0x4301C07C  
WKUP_GPIO0_45  
7
IO  
MCU_RGMII1_TD1  
MCU_RGMII1_TD1  
MCU_RMII1_TXD1  
0
1
O
O
VDDSHV2_MC  
U
PADCFG:  
WKUP_PADCONFIG_30  
0x4301C078  
WKUP_GPIO0_44  
7
IO  
MCU_RGMII1_TD2  
MCU_TIMER_IO3  
0
1
3
7
O
IO  
I
MCU_RGMII1_TD2  
VDDSHV2_MC  
U
PADCFG:  
WKUP_PADCONFIG_29  
0x4301C074  
E21  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
LVCMOS  
No  
MCU_ADC_EXT_TRIGGER1  
WKUP_GPIO0_43  
IO  
Copyright © 2023 Texas Instruments Incorporated  
English Data Sheet: SPRSP62  
42  
Submit Document Feedback  
Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
 
 
 
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
MCU_RGMII1_TD3  
0
1
3
7
O
IO  
I
MCU_RGMII1_TD3  
MCU_TIMER_IO2  
VDDSHV2_MC  
U
PADCFG:  
WKUP_PADCONFIG_28  
0x4301C070  
E22  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
LVCMOS  
No  
MCU_ADC_EXT_TRIGGER0  
WKUP_GPIO0_42  
IO  
MCU_SAFETY_ERRORn  
PADCFG:  
WKUP_PADCONFIG_69  
0x4301C114  
J23  
B27  
B26  
D24  
MCU_SAFETY_ERRORn  
0
IO  
1.8 V  
Off / Off / Down  
On / Off / Off  
Off / Off / Off  
On / Off / Off  
On / SS / Down  
On / Off / Off  
Off / Off / Off  
On / Off / Off  
0
7
7
7
VDDA_WKUP  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
No  
Yes  
Yes  
Yes  
MCU_SPI0_CLK  
0
7
IO  
IO  
MCU_SPI0_CLK  
WKUP_GPIO0_54  
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_40  
0x4301C0A0  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
BOOTST  
RAP  
MCU_BOOTMODE00  
I
MCU_SPI0_CS0  
MCU_SPI0_CS0  
MCU_TIMER_IO1  
0
4
IO  
IO  
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_43  
0x4301C0AC  
WKUP_GPIO0_70  
7
IO  
MCU_SPI0_D0  
0
7
IO  
IO  
MCU_SPI0_D0  
WKUP_GPIO0_55  
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_41  
0x4301C0A4  
BOOTST  
RAP  
MCU_BOOTMODE01  
I
MCU_SPI0_D1  
0
4
7
IO  
IO  
IO  
MCU_SPI0_D1  
MCU_TIMER_IO0  
WKUP_GPIO0_69  
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_42  
0x4301C0A8  
B25  
1.8 V/3.3 V  
On / Off / Off  
On / Off / Off  
7
LVCMOS  
Yes  
BOOTST  
RAP  
MCU_BOOTMODE02  
I
AF1  
AC6  
AF2  
AE3  
MMC0_CALPAD  
MMC0_CLK  
MMC0_CMD  
MMC0_DS  
MMC0_CALPAD  
MMC0_CLK  
MMC0_CMD  
MMC0_DS  
A
O
1.8 V  
1.8 V  
1.8 V  
1.8 V  
VDDS_MMC0  
VDDS_MMC0  
VDDS_MMC0  
VDDS_MMC0  
eMMCPHY  
eMMCPHY  
eMMCPHY  
eMMCPHY  
No  
No  
No  
No  
IO  
IO  
IO  
I
MMC1_CLK  
UART8_RXD  
TIMER_IO6  
EHRPWM2_B  
UART4_CTSn  
EHRPWM5_A  
GPIO0_64  
0
1
3
IO  
IO  
I
4
MMC1_CLK  
5
PADCFG:  
PADCONFIG_65  
0x4301C104  
P23  
6
IO  
IO  
IO  
O
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV5  
SDIO  
No  
7
SPI1_CLK  
8
UART0_RTSn  
I2C6_SDA  
9
10  
11  
IOD  
O
MCAN15_TX  
Copyright © 2023 Texas Instruments Incorporated  
Submit Document Feedback  
43  
Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
English Data Sheet: SPRSP62  
 
 
 
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
MMC1_CMD  
UART8_TXD  
TIMER_IO7  
EHRPWM2_A  
UART4_RTSn  
GPIO0_65  
0
1
IO  
O
3
IO  
IO  
O
MMC1_CMD  
4
PADCFG:  
PADCONFIG_66  
0x4301C108  
N24  
5
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV5  
SDIO  
No  
7
IO  
IO  
IOD  
I
SPI1_D1  
8
I2C6_SCL  
10  
11  
MCAN15_RX  
MMC0_DAT0  
MMC0_DAT1  
MMC0_DAT2  
MMC0_DAT3  
MMC0_DAT4  
MMC0_DAT5  
MMC0_DAT6  
MMC0_DAT7  
MMC1_DAT0  
UART7_RTSn  
AF4  
AD3  
AD4  
AF3  
AE2  
AG3  
AE1  
AG1  
MMC0_DAT0  
MMC0_DAT1  
MMC0_DAT2  
MMC0_DAT3  
MMC0_DAT4  
MMC0_DAT5  
MMC0_DAT6  
MMC0_DAT7  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
O
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
VDDS_MMC0  
VDDS_MMC0  
VDDS_MMC0  
VDDS_MMC0  
VDDS_MMC0  
VDDS_MMC0  
VDDS_MMC0  
VDDS_MMC0  
eMMCPHY  
eMMCPHY  
eMMCPHY  
eMMCPHY  
eMMCPHY  
eMMCPHY  
eMMCPHY  
eMMCPHY  
No  
No  
No  
No  
No  
No  
No  
No  
0
1
ECAP1_IN_APWM_OUT  
TIMER_IO5  
2
IO  
IO  
IO  
O
3
MMC1_DAT0  
EHRPWM1_A  
UART4_TXD  
GPIO0_63  
4
PADCFG:  
PADCONFIG_63  
0x4301C0FC  
M23  
5
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV5  
SDIO  
No  
7
IO  
IO  
O
SPI1_D0  
8
UART5_RTSn  
I2C4_SCL  
9
10  
11  
IOD  
O
UART2_TXD  
Copyright © 2023 Texas Instruments Incorporated  
English Data Sheet: SPRSP62  
44  
Submit Document Feedback  
Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
 
 
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
MMC1_DAT1  
UART7_CTSn  
0
1
IO  
I
ECAP0_IN_APWM_OUT  
TIMER_IO4  
2
IO  
IO  
IO  
I
3
EHRPWM1_B  
UART4_RXD  
EHRPWM4_A  
GPIO0_62  
4
MMC1_DAT1  
5
PADCFG:  
PADCONFIG_62  
0x4301C0F8  
P24  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV5  
SDIO  
No  
6
IO  
IO  
IO  
I
7
SPI1_CS2  
8
UART5_CTSn  
I2C4_SDA  
9
10  
11  
0
IOD  
I
UART2_RXD  
MMC1_DAT2  
UART7_TXD  
TIMER_IO3  
IO  
O
1
3
IO  
IO  
IO  
IO  
O
MMC1_DAT2  
EHRPWM0_A  
GPIO0_61  
4
PADCFG:  
PADCONFIG_61  
0x4301C0F4  
R24  
7
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV5  
SDIO  
No  
SPI1_CS1  
8
CPTS0_TS_SYNC  
I2C3_SDA  
9
10  
11  
0
IOD  
O
UART5_TXD  
MMC1_DAT3  
UART7_RXD  
PCIE1_CLKREQn  
TIMER_IO2  
IO  
I
1
2
IO  
IO  
IO  
IO  
IO  
IO  
I
3
MMC1_DAT3  
EHRPWM0_B  
EHRPWM3_A  
GPIO0_60  
4
PADCFG:  
PADCONFIG_60  
0x4301C0F0  
R22  
6
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV5  
SDIO  
No  
7
SPI1_CS0  
8
UART0_CTSn  
I2C3_SCL  
9
10  
11  
IOD  
I
UART5_RXD  
OSC1_XI  
M28  
L28  
OSC1_XI  
I
1.8 V  
1.8 V  
VDDA_OSC1  
VDDA_OSC1  
HFXOSC  
HFXOSC  
OSC1_XO  
OSC1_XO  
O
Copyright © 2023 Texas Instruments Incorporated  
Submit Document Feedback  
45  
Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
English Data Sheet: SPRSP62  
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
VDDA_0P8_SE  
RDES0_1 /  
VDDA_0P8_SE  
RDES_C0_1 /  
VDDA_1P8_SE  
RDES0_1  
AH10  
PCIE_REFCLK1_N_OUT  
PCIE_REFCLK1_N_OUT  
O
O
1.8 V  
4L_PHY  
VDDA_0P8_SE  
RDES0_1 /  
VDDA_0P8_SE  
RDES_C0_1 /  
VDDA_1P8_SE  
RDES0_1  
AH11  
G26  
PCIE_REFCLK1_P_OUT  
PMIC_POWER_EN1  
PCIE_REFCLK1_P_OUT  
1.8 V  
4L_PHY  
PMIC_POWER_EN1  
0
5
O
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_68  
0x4301C110  
MCU_I3C0_SDAPULLEN  
OD  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
LVCMOS  
Yes  
WKUP_GPIO0_88  
7
IO  
PMIC_WAKE0n  
MCASP4_AXR0  
DSS_FSYNC1  
MCAN17_RX  
GPMC0_WEn  
GPIO0_13  
0
1
OD  
IO  
O
4
5
I
PMIC_WAKE0n  
6
O
PADCFG:  
PADCONFIG_13  
0x4301C034  
AD24  
7
IO  
IO  
O
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV2  
LVCMOS  
No  
SPI6_CS0  
8
TRC_DATA0  
10  
11  
13  
14  
UART9_RTSn  
UART7_TXD  
O
O
AUDIO_EXT_REFCLK0  
IO  
PORz  
PADCFG:  
WKUP_PADCONFIG_94  
0x4301C178  
K23  
AF27  
A24  
PORz  
0
0
0
I
O
I
1.8 V  
0
0
0
VDDA_WKUP  
VDDSHV0  
FS_RESET  
LVCMOS  
LVCMOS  
No  
No  
No  
RESETSTATz  
PADCFG:  
PADCONFIG_67  
0x4301C10C  
RESETSTATz  
RESET_REQz  
1.8 V/3.3 V  
1.8 V/3.3 V  
Off / Low / Off  
On / Off / Up  
Off / SS / Off  
On / Off / Up  
RESET_REQz  
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_93  
0x4301C174  
VDDA_0P8_SE  
RDES0_1 /  
VDDA_0P8_SE  
RDES_C0_1 /  
VDDA_1P8_SE  
RDES0_1  
AH4  
SERDES0_REFCLK_N  
SERDES0_REFCLK_N  
0
IO  
1.8 V  
4L_PHY  
Copyright © 2023 Texas Instruments Incorporated  
English Data Sheet: SPRSP62  
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
VDDA_0P8_SE  
RDES0_1 /  
VDDA_0P8_SE  
RDES_C0_1 /  
VDDA_1P8_SE  
RDES0_1  
AH5  
AC10  
AF9  
SERDES0_REFCLK_P  
SERDES0_REFCLK_P  
0
IO  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
4L_PHY  
4L_PHY  
4L_PHY  
4L_PHY  
4L_PHY  
4L_PHY  
4L_PHY  
4L_PHY  
4L_PHY  
VDDA_0P8_SE  
RDES0_1 /  
VDDA_0P8_SE  
RDES_C0_1 /  
VDDA_1P8_SE  
RDES0_1  
SERDES0_REXT  
SERDES0_REXT  
I
PCIE1_RXN0  
1
2
I
I
VDDA_0P8_SE  
RDES0_1 /  
VDDA_0P8_SE  
RDES_C0_1 /  
VDDA_1P8_SE  
RDES0_1  
USB0_SSRX1N  
SERDES0_RX0_N  
SERDES0_RX0_P  
SERDES0_RX1_N  
SERDES0_RX1_P  
SERDES0_RX2_N  
SERDES0_RX2_P  
SERDES0_RX3_N  
HYP_RXN0  
4
I
PCIE1_RXP0  
1
2
I
I
VDDA_0P8_SE  
RDES0_1 /  
VDDA_0P8_SE  
RDES_C0_1 /  
VDDA_1P8_SE  
RDES0_1  
USB0_SSRX1P  
AF10  
AE8  
AE9  
AF6  
HYP_RXP0  
4
I
PCIE1_RXN1  
1
2
I
I
VDDA_0P8_SE  
RDES0_1 /  
VDDA_0P8_SE  
RDES_C0_1 /  
VDDA_1P8_SE  
RDES0_1  
USB0_SSRX2N  
HYP_RXN1  
4
I
PCIE1_RXP1  
1
2
I
I
VDDA_0P8_SE  
RDES0_1 /  
VDDA_0P8_SE  
RDES_C0_1 /  
VDDA_1P8_SE  
RDES0_1  
USB0_SSRX2P  
HYP_RXP1  
4
I
PCIE1_RXN2  
1
2
I
I
VDDA_0P8_SE  
RDES0_1 /  
VDDA_0P8_SE  
RDES_C0_1 /  
VDDA_1P8_SE  
RDES0_1  
USB0_SSRX1N  
HYP_RXN2  
4
I
PCIE1_RXP2  
1
2
I
I
VDDA_0P8_SE  
RDES0_1 /  
VDDA_0P8_SE  
RDES_C0_1 /  
VDDA_1P8_SE  
RDES0_1  
USB0_SSRX1P  
AF7  
HYP_RXP2  
4
I
PCIE1_RXN3  
1
2
I
I
VDDA_0P8_SE  
RDES0_1 /  
VDDA_0P8_SE  
RDES_C0_1 /  
VDDA_1P8_SE  
RDES0_1  
USB0_SSRX2N  
AE5  
HYP_RXN3  
4
I
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
English Data Sheet: SPRSP62  
 
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
PCIE1_RXP3  
1
2
I
I
VDDA_0P8_SE  
RDES0_1 /  
VDDA_0P8_SE  
RDES_C0_1 /  
VDDA_1P8_SE  
RDES0_1  
USB0_SSRX2P  
AE6  
AH7  
AH8  
AG8  
AG9  
SERDES0_RX3_P  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
4L_PHY  
4L_PHY  
4L_PHY  
4L_PHY  
4L_PHY  
HYP_RXP3  
4
I
DP0_TXN0  
0
1
2
4
0
1
2
4
0
1
2
4
0
1
2
4
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
VDDA_0P8_SE  
RDES0_1 /  
VDDA_0P8_SE  
RDES_C0_1 /  
VDDA_1P8_SE  
RDES0_1  
PCIE1_TXN0  
USB0_SSTX1N  
HYP_TXN0  
SERDES0_TX0_N  
SERDES0_TX0_P  
SERDES0_TX1_N  
SERDES0_TX1_P  
DP0_TXP0  
VDDA_0P8_SE  
RDES0_1 /  
VDDA_0P8_SE  
RDES_C0_1 /  
VDDA_1P8_SE  
RDES0_1  
PCIE1_TXP0  
USB0_SSTX1P  
HYP_TXP0  
DP0_TXN1  
VDDA_0P8_SE  
RDES0_1 /  
VDDA_0P8_SE  
RDES_C0_1 /  
VDDA_1P8_SE  
RDES0_1  
PCIE1_TXN1  
USB0_SSTX2N  
HYP_TXN1  
DP0_TXP1  
VDDA_0P8_SE  
RDES0_1 /  
VDDA_0P8_SE  
RDES_C0_1 /  
VDDA_1P8_SE  
RDES0_1  
PCIE1_TXP1  
USB0_SSTX2P  
HYP_TXP1  
DP0_TXN2  
VDDA_0P8_SE  
RDES0_1 /  
VDDA_0P8_SE  
RDES_C0_1 /  
VDDA_1P8_SE  
RDES0_1  
PCIE1_TXN2  
USB0_SSTX1N  
DP0_TXN0  
AG5  
AG6  
AD7  
SERDES0_TX2_N  
SERDES0_TX2_P  
SERDES0_TX3_N  
1.8 V  
1.8 V  
1.8 V  
4L_PHY  
4L_PHY  
4L_PHY  
HYP_TXN2  
DP0_TXP2  
VDDA_0P8_SE  
RDES0_1 /  
VDDA_0P8_SE  
RDES_C0_1 /  
VDDA_1P8_SE  
RDES0_1  
PCIE1_TXP2  
USB0_SSTX1P  
DP0_TXP0  
HYP_TXP2  
DP0_TXN3  
VDDA_0P8_SE  
RDES0_1 /  
VDDA_0P8_SE  
RDES_C0_1 /  
VDDA_1P8_SE  
RDES0_1  
PCIE1_TXN3  
USB0_SSTX2N  
DP0_TXN1  
HYP_TXN3  
Copyright © 2023 Texas Instruments Incorporated  
English Data Sheet: SPRSP62  
48  
Submit Document Feedback  
Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
DP0_TXP3  
0
1
2
3
4
O
O
O
O
O
VDDA_0P8_SE  
RDES0_1 /  
VDDA_0P8_SE  
RDES_C0_1 /  
VDDA_1P8_SE  
RDES0_1  
PCIE1_TXP3  
USB0_SSTX2P  
DP0_TXP1  
AD8  
SERDES0_TX3_P  
1.8 V  
4L_PHY  
HYP_TXP3  
SOC_SAFETY_ERRORn  
PADCFG:  
PADCONFIG_68  
0x4301C110  
AF25  
SOC_SAFETY_ERRORn  
0
IO  
1.8 V/3.3 V  
Off / Off / Down  
On / SS / Down  
0
VDDSHV0  
LVCMOS  
No  
SPI0_CLK  
0
1
IO  
I
UART1_CTSn  
I2C2_SCL  
2
IOD  
IO  
IO  
IO  
O
SPI0_CLK  
MCASP3_AXR0  
EHRPWM2_A  
GPIO0_53  
3
PADCFG:  
PADCONFIG_53  
0x4301C0D4  
AH27  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV0  
LVCMOS  
No  
5
7
UART8_TXD  
VPU0_UART_TXD  
SPI0_CS0  
11  
14  
0
O
IO  
IO  
IO  
IO  
IO  
O
MCASP3_ACLKX  
MCASP3_ACLKR  
EHRPWM0_A  
GPIO0_51  
3
SPI0_CS0  
4
PADCFG:  
PADCONFIG_51  
0x4301C0CC  
AE27  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV0  
LVCMOS  
No  
5
7
MCAN14_TX  
SPI0_CS1  
9
0
IO  
O
CPTS0_TS_COMP  
UART0_RTSn  
MCASP3_AFSX  
MCASP3_AFSR  
EHRPWM1_A  
GPIO0_52  
1
2
O
3
IO  
IO  
IO  
IO  
I
SPI0_CS1  
4
PADCFG:  
PADCONFIG_52  
0x4301C0D0  
AF26  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV0  
LVCMOS  
No  
5
7
MCAN14_RX  
UART8_RXD  
VPU0_UART_RXD  
9
11  
14  
I
I
Copyright © 2023 Texas Instruments Incorporated  
Submit Document Feedback  
49  
Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
English Data Sheet: SPRSP62  
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
SPI0_D0  
0
1
IO  
O
UART1_RTSn  
I2C2_SDA  
SPI0_D0  
PADCFG:  
PADCONFIG_54  
0x4301C0D8  
2
IOD  
IO  
IO  
IO  
I
AG26  
MCASP3_AXR1  
EHRPWM3_A  
GPIO0_54  
3
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV0  
LVCMOS  
No  
5
7
UART2_RXD  
SPI0_D1  
11  
0
IO  
IO  
IO  
IO  
O
SPI0_D1  
MCASP3_AXR2  
EHRPWM4_A  
GPIO0_55  
3
PADCFG:  
PADCONFIG_55  
0x4301C0DC  
AH26  
5
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV0  
LVCMOS  
No  
7
UART2_TXD  
11  
TCK  
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_73  
0x4301C124  
A25  
TCK  
TDI  
0
0
0
I
I
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
On / NA / Up  
On / Off / Up  
Off / Off / Up  
On / Off / Up  
On / Off / Up  
Off / SS / Up  
0
0
0
LVCMOS  
LVCMOS  
LVCMOS  
No  
No  
No  
TDI  
PADCFG:  
PADCONFIG_69  
0x4301C114  
AG28  
AE26  
VDDSHV0  
VDDSHV0  
TDO  
PADCFG:  
PADCONFIG_70  
0x4301C118  
TDO  
OZ  
TIMER_IO0  
0
1
IO  
IO  
O
ECAP1_IN_APWM_OUT  
SYSCLKOUT0  
UART3_RXD  
2
TIMER_IO0  
5
I
PADCFG:  
PADCONFIG_58  
0x4301C0E8  
AE25  
PCIE1_CLKREQn  
GPIO0_58  
6
IO  
IO  
I
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV0  
LVCMOS  
No  
7
MMC1_SDCD  
MCAN13_TX  
8
9
O
I2C6_SDA  
13  
IOD  
Copyright © 2023 Texas Instruments Incorporated  
English Data Sheet: SPRSP62  
50  
Submit Document Feedback  
Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
TIMER_IO1  
0
1
IO  
IO  
O
ECAP2_IN_APWM_OUT  
OBSCLK0  
2
UART3_TXD  
USB0_DRVVBUS  
GPIO0_59  
5
O
TIMER_IO1  
6
O
PADCFG:  
PADCONFIG_59  
0x4301C0EC  
AG25  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
VDDSHV0  
LVCMOS  
No  
7
IO  
I
MMC1_SDWP  
MCAN13_RX  
I2C6_SCL  
8
9
I
13  
15  
IOD  
O
OBSCLK0  
TMS  
PADCFG:  
PADCONFIG_71  
0x4301C11C  
AG27  
B28  
TMS  
0
0
I
I
1.8 V/3.3 V  
1.8 V/3.3 V  
On / Off / Up  
On / Off / Up  
0
0
VDDSHV0  
LVCMOS  
LVCMOS  
No  
No  
TRSTn  
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_74  
0x4301C128  
TRSTn  
On / NA / Down  
On / Off / Down  
VDDA_0P8_US  
B /  
VDDA_1P8_US  
AG2  
AH2  
AC9  
AA6  
AA8  
USB0_DM  
USB0_DM  
IO  
IO  
A
3.3 V  
3.3 V  
3.3 V  
3.3 V  
5.0 V  
USB2PHY  
USB2PHY  
USB2PHY  
USB2PHY  
DDR  
B /  
VDDA_3P3_US  
B
VDDA_0P8_US  
B /  
VDDA_1P8_US  
USB0_DP  
USB0_DP  
B /  
VDDA_3P3_US  
B
VDDA_0P8_US  
B /  
VDDA_1P8_US  
USB0_ID  
USB0_ID  
B /  
VDDA_3P3_US  
B
VDDA_0P8_US  
B /  
VDDA_1P8_US  
USB0_RCALIB  
USB0_VBUS  
USB0_RCALIB  
USB0_VBUS  
A
B /  
VDDA_3P3_US  
B
VDDA_0P8_US  
B /  
VDDA_1P8_US  
A
B /  
VDDA_3P3_US  
B
Copyright © 2023 Texas Instruments Incorporated  
Submit Document Feedback  
51  
Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
English Data Sheet: SPRSP62  
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
N17, V11,  
V16, Y20  
VDDAR_CORE  
VDDAR_CORE  
PWR  
PWR  
H9, K14, P11,  
P14, V13  
VDDAR_CPU  
VDDAR_CPU  
VDDAR_MCU  
K17, K19  
AB14  
VDDAR_MCU  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
VDDA_0P8_DSITX  
VDDA_0P8_DSITX_C  
VDDA_0P8_USB  
VDDA_0P8_DSITX  
VDDA_0P8_DSITX_C  
VDDA_0P8_USB  
AB15  
AB8  
AB17, AB18 VDDA_0P8_CSIRX0_1  
VDDA_0P8_CSIRX0_1  
VDDA_0P8_DLL_MMC0  
VDDA_0P8_PLL_DDR0  
VDDA_0P8_PLL_DDR1  
VDDA_0P8_SERDES0_1  
VDDA_0P8_SERDES_C0_1  
VDDA_1P8_DSITX  
VDDA_1P8_USB  
W7  
P10  
J14  
VDDA_0P8_DLL_MMC0  
VDDA_0P8_PLL_DDR0  
VDDA_0P8_PLL_DDR1  
AB10, AB11 VDDA_0P8_SERDES0_1  
AA10, AA11 VDDA_0P8_SERDES_C0_1  
AA14, AA15 VDDA_1P8_DSITX  
AB7  
VDDA_1P8_USB  
AA17, AA19 VDDA_1P8_CSIRX0_1  
VDDA_1P8_CSIRX0_1  
VDDA_1P8_SERDES0_1  
VDDA_1P8_SERDES2_4  
VDDA_3P3_USB  
AA12  
AB13  
AB9  
J21  
VDDA_1P8_SERDES0_1  
VDDA_1P8_SERDES2_4  
VDDA_3P3_USB  
VDDA_ADC0  
VDDA_ADC0  
K21  
K22  
J17  
VDDA_ADC1  
VDDA_ADC1  
VDDA_MCU_PLLGRP0  
VDDA_MCU_TEMP  
VDDA_OSC1  
VDDA_MCU_PLLGRP0  
VDDA_MCU_TEMP  
VDDA_OSC1  
L21  
U18  
V19  
Y11  
N14  
R12  
R11  
K12  
T18  
Y16  
Y18  
V12  
L20  
U19  
VDDA_PLLGRP0  
VDDA_PLLGRP1  
VDDA_PLLGRP2  
VDDA_PLLGRP5  
VDDA_PLLGRP6  
VDDA_PLLGRP7  
VDDA_PLLGRP8  
VDDA_PLLGRP9  
VDDA_PLLGRP10  
VDDA_PLLGRP12  
VDDA_PLLGRP13  
VDDA_POR_WKUP  
VDDA_TEMP0  
VDDA_PLLGRP0  
VDDA_PLLGRP1  
VDDA_PLLGRP2  
VDDA_PLLGRP5  
VDDA_PLLGRP6  
VDDA_PLLGRP7  
VDDA_PLLGRP8  
VDDA_PLLGRP9  
VDDA_PLLGRP10  
VDDA_PLLGRP12  
VDDA_PLLGRP13  
VDDA_POR_WKUP  
VDDA_TEMP0  
Copyright © 2023 Texas Instruments Incorporated  
English Data Sheet: SPRSP62  
52  
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
K10  
T16  
U10  
Y14  
J22  
VDDA_TEMP1  
VDDA_TEMP2  
VDDA_TEMP1  
VDDA_TEMP2  
VDDA_TEMP3  
VDDA_TEMP4  
VDDA_WKUP  
PWR  
PWR  
PWR  
PWR  
PWR  
VDDA_TEMP3  
VDDA_TEMP4  
VDDA_WKUP  
R21, U21,  
U22  
VDDSHV0  
VDDSHV0  
PWR  
H19, H20  
H16, J16  
M20, R20  
G18, H18  
M21, N22  
VDDSHV0_MCU  
VDDSHV1_MCU  
VDDSHV2  
VDDSHV0_MCU  
VDDSHV1_MCU  
VDDSHV2  
PWR  
PWR  
PWR  
PWR  
PWR  
VDDSHV2_MCU  
VDDSHV5  
VDDSHV2_MCU  
VDDSHV5  
A1, A18, AA1,  
G10, G12,  
G14, G6,  
H11, H13,  
VDDS_DDR  
VDDS_DDR  
PWR  
H15, J6, L6,  
N6, N9, P7,  
P8, R6, U9  
R9  
J12  
VDDS_DDR_C0  
VDDS_DDR_C1  
VDDS_MMC0  
VDDS_DDR_C0  
VDDS_DDR_C1  
VDDS_MMC0  
PWR  
PWR  
PWR  
Y7, Y8  
AA21, AB20,  
J13, J15,  
M16, M19,  
N10, P18,  
R17, R19,  
T10, T20,  
U15, U17,  
U8, V14, V18,  
V20, V7, V9,  
W10, W13,  
W15, W17,  
W19, W21,  
W8, Y12,  
VDD_CORE  
VDD_CORE  
PWR  
Y22, Y9  
G8, H7, J8,  
K11, K13, K7,  
K9, L8, M14,  
M7, M9, N11,  
N15, P16,  
R13, R15,  
T12, T14,  
U11, U13  
VDD_CPU  
VDD_MCU  
VDD_CPU  
VDD_MCU  
PWR  
PWR  
K16, K18,  
L15, L17, L19  
J19  
VDD_MCU_WAKE1  
VDD_WAKE0  
VDD_MCU_WAKE1  
VDD_WAKE0  
PWR  
PWR  
P20  
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
English Data Sheet: SPRSP62  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
H23  
M18  
L22  
N19  
N20  
L18  
V22  
H22  
VMON1_ER_VSYS  
VMON1_ER_VSYS  
A
A
VMON2_IR_VCPU  
VMON3_IR_VEXT1P8  
VMON4_IR_VEXT1P8  
VMON5_IR_VEXT3P3  
VMON6_IR_VEXT0P8  
VPP_CORE  
VMON2_IR_VCPU  
VMON3_IR_VEXT1P8  
VMON4_IR_VEXT1P8  
VMON5_IR_VEXT3P3  
VMON6_IR_VEXT0P8  
VPP_CORE  
A
A
A
A
PWR  
PWR  
VPP_MCU  
VPP_MCU  
Copyright © 2023 Texas Instruments Incorporated  
English Data Sheet: SPRSP62  
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
A14, A5,  
AA13, AA16,  
AA18, AA20,  
AA22, AA3,  
AA5, AA7,  
AA9, AB12,  
AB16, AB19,  
AB2, AB21,  
AB23, AB4,  
AB6, AC11,  
AC22, AC26,  
AC3, AC5,  
AC7, AC8,  
AD15, AD18,  
AD21, AD6,  
AD9, AE10,  
AE14, AE17,  
AE20, AE23,  
AE4, AE7,  
AF12, AF15,  
AF18, AF21,  
AF24, AF5,  
AF8, AG10,  
AG14, AG17,  
AG20, AG23,  
AG4, AG7,  
AH1, AH12,  
AH15, AH18,  
AH21, AH24,  
AH3, AH6,  
AH9, B11,  
VSS  
VSS  
GND  
B13, B15,  
B17, B2, B23,  
B4, B6, B8,  
C1, C12,  
C14, C16,  
C18, C3, C5,  
C7, D11, D13,  
D15, D17,  
D2, D4, D6,  
D8, E1, E12,  
E14, E16,  
E26, E3, E5,  
E7, F2, F4,  
F6, G13,  
G28, G3, G5,  
G7, G9, H10,  
H12, H14,  
H2, H21, H4,  
H6, H8, J1,  
J11, J18, J24,  
J3, J5, J7, J9,  
K15, K2, K20,  
K27, K4, K6,  
K8, L14, L16,  
L3, L5, L7,  
L9, M15,  
M17, M2,  
M25, M4, M6,  
Copyright © 2023 Texas Instruments Incorporated  
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
English Data Sheet: SPRSP62  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
M8, N1, N16,  
N18, N21,  
N23, N3, N7,  
P15, P17,  
P19, P22, P6,  
P9, R10, R14,  
R16, R18,  
R23, R26,  
R7, T11, T13,  
T15, T17,  
T19, T2, T22,  
T4, T6, T9,  
U12, U14,  
U16, U20,  
U23, U3, U5,  
U7, V10, V15,  
V17, V2, V21,  
V24, V4, V6,  
V8, W1, W11,  
W12, W14,  
W16, W18,  
W20, W22,  
W26, W3,  
W6, W9, Y10,  
Y13, Y15,  
Y17, Y19, Y2,  
Y21, Y23, Y4,  
Y6  
MCU_SPI1_CLK  
MCU_SPI1_CLK  
WKUP_GPIO0_0  
0
1
7
IO  
IO  
IO  
WKUP_GPIO0_0  
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_48  
0x4301C0C0  
D26  
E24  
1.8 V/3.3 V  
On / Off / Off  
On / Off / Off  
7
7
LVCMOS  
LVCMOS  
Yes  
Yes  
BOOTST  
RAP  
MCU_BOOTMODE03  
I
MCU_SPI1_D0  
MCU_SPI1_D0  
WKUP_GPIO0_1  
0
1
7
IO  
IO  
IO  
WKUP_GPIO0_1  
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_49  
0x4301C0C4  
1.8 V/3.3 V  
On / Off / Off  
On / Off / Off  
BOOTST  
RAP  
MCU_BOOTMODE04  
I
MCU_SPI1_D1  
MCU_SPI1_D1  
WKUP_GPIO0_2  
0
1
7
IO  
IO  
IO  
WKUP_GPIO0_2  
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_50  
0x4301C0C8  
C28  
C27  
1.8 V/3.3 V  
1.8 V/3.3 V  
On / Off / Off  
Off / Off / Off  
On / Off / Off  
Off / Off / Off  
7
7
LVCMOS  
LVCMOS  
Yes  
Yes  
BOOTST  
RAP  
MCU_BOOTMODE05  
I
WKUP_GPIO0_3  
MCU_SPI1_CS0  
MCU_SPI1_CS0  
0
1
IO  
IO  
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_51  
0x4301C0CC  
WKUP_GPIO0_3  
7
IO  
Copyright © 2023 Texas Instruments Incorporated  
English Data Sheet: SPRSP62  
56  
Submit Document Feedback  
Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
MCU_MCAN1_TX  
MCU_MCAN1_TX  
MCU_SPI0_CS3  
0
1
2
3
7
0
1
2
3
7
0
1
2
3
7
0
1
2
3
7
0
1
2
3
4
7
0
1
2
3
4
7
O
O
WKUP_GPIO0_4  
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_52  
0x4301C0D0  
C23  
F26  
E25  
F28  
IO  
I
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
7
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
Yes  
Yes  
Yes  
Yes  
MCU_ADC_EXT_TRIGGER0  
WKUP_GPIO0_4  
IO  
I
MCU_MCAN1_RX  
MCU_MCAN1_RX  
MCU_SPI1_CS3  
WKUP_GPIO0_5  
I
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_53  
0x4301C0D4  
IO  
I
MCU_ADC_EXT_TRIGGER1  
WKUP_GPIO0_5  
IO  
I
WKUP_UART0_CTSn  
WKUP_UART0_CTSn  
MCU_CPTS0_HW1TSPUSH  
MCU_I2C1_SCL  
WKUP_GPIO0_6  
I
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_54  
0x4301C0D8  
I
IOD  
IO  
O
WKUP_GPIO0_6  
WKUP_UART0_RTSn  
WKUP_UART0_RTSn  
MCU_CPTS0_HW2TSPUSH  
MCU_I2C1_SDA  
WKUP_GPIO0_7  
O
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_55  
0x4301C0DC  
I
IOD  
IO  
IOD  
IOD  
O
WKUP_GPIO0_7  
MCU_I2C1_SCL  
MCU_I2C1_SCL  
WKUP_GPIO0_8  
MCU_CPTS0_TS_SYNC  
MCU_I3C0_SCL  
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_56  
0x4301C0E0  
F24  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
LVCMOS  
Yes  
IO  
IO  
IO  
IOD  
IOD  
O
MCU_TIMER_IO6  
WKUP_GPIO0_8  
MCU_I2C1_SDA  
MCU_I2C1_SDA  
WKUP_GPIO0_9  
MCU_CPTS0_TS_COMP  
MCU_I3C0_SDA  
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_57  
0x4301C0E4  
H26  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
LVCMOS  
Yes  
IO  
IO  
IO  
MCU_TIMER_IO7  
WKUP_GPIO0_9  
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Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1  
English Data Sheet: SPRSP62  
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
MCU_EXT_REFCLK0  
0
1
2
3
4
5
7
0
1
2
3
4
5
6
7
0
1
7
I
I
MCU_EXT_REFCLK0  
MCU_UART0_TXD  
MCU_ADC_EXT_TRIGGER0  
MCU_CPTS0_RFT_CLK  
MCU_SYSCLKOUT0  
WKUP_GPIO0_10  
WKUP_GPIO0_10  
O
I
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_58  
0x4301C0E8  
F27  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
LVCMOS  
Yes  
I
O
IO  
O
O
I
MCU_OBSCLK0  
MCU_OBSCLK0  
MCU_UART0_RXD  
MCU_ADC_EXT_TRIGGER1  
MCU_TIMER_IO1  
WKUP_GPIO0_11  
I
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_59  
0x4301C0EC  
F25  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
7
LVCMOS  
Yes  
IO  
OD  
OZ  
IO  
O
IO  
IO  
MCU_I3C0_SDAPULLEN  
MCU_CLKOUT0  
WKUP_GPIO0_11  
MCU_UART0_TXD  
MCU_SPI0_CS1  
WKUP_GPIO0_12  
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_60  
0x4301C0F0  
C25  
C24  
1.8 V/3.3 V  
On / Off / Off  
On / Off / Off  
7
7
LVCMOS  
LVCMOS  
Yes  
Yes  
WKUP_GPIO0_12  
BOOTST  
RAP  
MCU_BOOTMODE08  
I
MCU_UART0_RXD  
MCU_SPI1_CS1  
WKUP_GPIO0_13  
0
1
7
I
WKUP_GPIO0_13  
IO  
IO  
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_61  
0x4301C0F4  
1.8 V/3.3 V  
On / Off / Off  
On / Off / Off  
BOOTST  
RAP  
MCU_BOOTMODE09  
I
MCU_UART0_CTSn  
MCU_SPI0_CS2  
0
1
4
7
I
IO  
IO  
IO  
WKUP_GPIO0_14  
MCU_TIMER_IO8  
WKUP_GPIO0_14  
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_62  
0x4301C0F8  
B24  
1.8 V/3.3 V  
On / Off / Off  
On / Off / Off  
7
LVCMOS  
Yes  
BOOTST  
RAP  
MCU_BOOTMODE06  
I
MCU_UART0_RTSn  
MCU_SPI1_CS2  
0
1
4
7
O
IO  
IO  
IO  
WKUP_GPIO0_15  
MCU_TIMER_IO9  
WKUP_GPIO0_15  
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_63  
0x4301C0FC  
D25  
1.8 V/3.3 V  
On / Off / Off  
On / Off / Off  
7
LVCMOS  
Yes  
BOOTST  
RAP  
MCU_BOOTMODE07  
I
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表6-2. Pin Attributes (ALZ Package) (continued)  
Ball  
Name [2]  
PADCFG Register [13]  
PADCFG Address [14]  
Ball State  
Ball State  
AFTER  
Reset  
Mux  
Mode  
AFTER  
Voltage  
Buffer  
Type [11]  
Ball  
Num [1]  
Signal  
Name [3]  
Mux  
Mode [4]  
Signal  
Type [5]  
I/O  
Voltage [6]  
DURING  
Reset  
IO  
RET [12]  
Power [10]  
(RX/TX/PULL) [7] (RX/TX/PULL) [8] Reset [9]  
PMIC_WAKE1n  
0
1
2
7
4
7
O
I
WKUP_GPIO0_49  
MCU_EXT_REFCLK0  
MCU_CPTS0_RFT_CLK  
WKUP_GPIO0_49  
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_100  
0x4301C190  
K26  
G27  
1.8 V/3.3 V  
1.8 V/3.3 V  
Off / Off / Off  
On / Off / Off  
Off / Off / Off  
On / Off / Off  
7
7
LVCMOS  
LVCMOS  
No  
No  
I
IO  
IO  
IO  
MCU_TIMER_IO6  
WKUP_GPIO0_56  
WKUP_GPIO0_56  
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_72  
0x4301C120  
BOOTST  
RAP  
BOOTMODE04  
I
MCU_TIMER_IO7  
WKUP_GPIO0_57  
4
7
IO  
IO  
WKUP_GPIO0_57  
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_95  
0x4301C17C  
J26  
G25  
J27  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
On / Off / Off  
On / Off / Off  
On / Off / Off  
On / Off / Off  
On / Off / Off  
On / Off / Off  
7
7
7
LVCMOS  
LVCMOS  
LVCMOS  
No  
Yes  
Yes  
BOOTST  
RAP  
BOOTMODE05  
I
WKUP_GPIO0_66  
WKUP_GPIO0_66  
7
IO  
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_96  
0x4301C180  
BOOTST  
RAP  
BOOTMODE06  
I
WKUP_LF_CLKIN  
WKUP_GPIO0_67  
1
7
I
WKUP_GPIO0_67  
IO  
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_97  
0x4301C184  
BOOTST  
RAP  
BOOTMODE07  
I
WKUP_I2C0_SCL  
WKUP_I2C0_SCL  
0
7
0
7
IOD  
VDDSHV0_MC  
U
I2C OPEN  
DRAIN  
PADCFG:  
WKUP_PADCONFIG_64  
0x4301C100  
H24  
H27  
1.8 V/3.3 V  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
On / SS / Off  
On / SS / Off  
0
0
Yes  
Yes  
WKUP_GPIO0_63  
WKUP_I2C0_SDA  
WKUP_GPIO0_64  
IO  
IOD  
IO  
WKUP_I2C0_SDA  
VDDSHV0_MC  
U
I2C OPEN  
DRAIN  
PADCFG:  
WKUP_PADCONFIG_65  
0x4301C104  
H28  
J28  
WKUP_OSC0_XI  
WKUP_OSC0_XO  
WKUP_UART0_RXD  
WKUP_OSC0_XI  
WKUP_OSC0_XO  
WKUP_UART0_RXD  
I
O
I
1.8 V  
1.8 V  
VDDA_WKUP  
VDDA_WKUP  
HFXOSC  
HFXOSC  
No  
No  
0
7
0
7
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_44  
0x4301C0B0  
D28  
D27  
1.8 V/3.3 V  
1.8 V/3.3 V  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
LVCMOS  
LVCMOS  
Yes  
Yes  
WKUP_GPIO0_58  
WKUP_UART0_TXD  
WKUP_GPIO0_59  
IO  
O
WKUP_UART0_TXD  
VDDSHV0_MC  
U
PADCFG:  
WKUP_PADCONFIG_45  
0x4301C0B4  
IO  
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English Data Sheet: SPRSP62  
 
 
 
 
 
 
 
 
 
 
 
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ZHCSRF7 –DECEMBER 2022  
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6.3 Signal Descriptions  
6.3.1 ADC  
6.3.1.1 MCU Domain  
表6-3. MCU_ADC Signal Descriptions  
SIGNAL NAME  
MCU_ADC_EXT_TRIGGER0  
MCU_ADC_EXT_TRIGGER1  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
I
I
ADC Trigger Input  
ADC Trigger Input  
C23, E22, F27  
E21, F25, F26  
表6-4. MCU_ADC0 Signal Descriptions  
SIGNAL NAME  
MCU_ADC0_AIN0  
MCU_ADC0_AIN1  
MCU_ADC0_AIN2  
MCU_ADC0_AIN3  
MCU_ADC0_AIN4  
MCU_ADC0_AIN5  
MCU_ADC0_AIN6  
MCU_ADC0_AIN7  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
L25  
A
A
A
A
A
A
A
A
ADC Input 0  
ADC Input 1  
ADC Input 2  
ADC Input 3  
ADC Input 4  
ADC Input 5  
ADC Input 6  
ADC Input 7  
K25  
M24  
L24  
L27  
K24  
M27  
M26  
表6-5. MCU_ADC1 Signal Descriptions  
SIGNAL NAME  
MCU_ADC1_AIN0  
MCU_ADC1_AIN1  
MCU_ADC1_AIN2  
MCU_ADC1_AIN3  
MCU_ADC1_AIN4  
MCU_ADC1_AIN5  
MCU_ADC1_AIN6  
MCU_ADC1_AIN7  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
P25  
A
A
A
A
A
A
A
A
ADC Input 0  
ADC Input 1  
ADC Input 2  
ADC Input 3  
ADC Input 4  
ADC Input 5  
ADC Input 6  
ADC Input 7  
R25  
P28  
P27  
N25  
P26  
N26  
N27  
6.3.2 DDRSS  
6.3.2.1 MAIN Domain  
表6-6. DDRSS0 Signal Descriptions  
SIGNAL NAME  
DDR0_CKN  
PIN TYPE  
DESCRIPTION  
DDRSS Differential Clock (negative)  
DDRSS Differential Clock (positive)  
DDRSS Reset  
ALZ PIN  
R1  
IO  
IO  
IO  
I
DDR0_CKP  
P1  
DDR0_RESETn  
DDR0_RET  
R5  
DDR Retention Enable  
T8  
DDR0_CA0  
IO  
IO  
IO  
IO  
IO  
IO  
A
DDRSS Command Address  
DDRSS Command Address  
DDRSS Command Address  
DDRSS Command Address  
DDRSS Command Address  
DDRSS Command Address  
IO Pad Calibration Resistor  
DDRSS Clock Enable  
P3  
DDR0_CA1  
P5  
DDR0_CA2  
N5  
DDR0_CA3  
P2  
DDR0_CA4  
P4  
DDR0_CA5  
R3  
DDR0_CAL0(1)  
R8  
DDR0_CKE0  
IO  
R2  
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TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
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ZHCSRF7 –DECEMBER 2022  
表6-6. DDRSS0 Signal Descriptions (continued)  
SIGNAL NAME  
PIN TYPE  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
DESCRIPTION  
ALZ PIN  
R4  
DDR0_CKE1  
DDR0_CSn0_0  
DDR0_CSn0_1  
DDR0_CSn1_0  
DDR0_CSn1_1  
DDR0_DM0  
DDR0_DM1  
DDR0_DM2  
DDR0_DM3  
DDR0_DQ0  
DDRSS Clock Enable  
DDRSS Chip Select  
DDRSS Chip Select  
DDRSS Chip Select  
DDRSS Chip Select  
DDRSS Data Mask  
DDRSS Data Mask  
DDRSS Data Mask  
DDRSS Data Mask  
DDRSS Data  
V5  
W5  
T5  
U6  
H5  
M3  
U4  
AD1  
F3  
DDR0_DQ1  
DDRSS Data  
G4  
F5  
DDR0_DQ2  
DDRSS Data  
DDR0_DQ3  
DDRSS Data  
F1  
DDR0_DQ4  
DDRSS Data  
J4  
DDR0_DQ5  
DDRSS Data  
H3  
DDR0_DQ6  
DDRSS Data  
J2  
DDR0_DQ7  
DDRSS Data  
G2  
K5  
DDR0_DQ8  
DDRSS Data  
DDR0_DQ9  
DDRSS Data  
M5  
K3  
DDR0_DQ10  
DDR0_DQ11  
DDR0_DQ12  
DDR0_DQ13  
DDR0_DQ14  
DDR0_DQ15  
DDR0_DQ16  
DDR0_DQ17  
DDR0_DQ18  
DDR0_DQ19  
DDR0_DQ20  
DDR0_DQ21  
DDR0_DQ22  
DDR0_DQ23  
DDR0_DQ24  
DDR0_DQ25  
DDR0_DQ26  
DDR0_DQ27  
DDR0_DQ28  
DDR0_DQ29  
DDR0_DQ30  
DDR0_DQ31  
DDR0_DQS0N  
DDR0_DQS0P  
DDR0_DQS1N  
DDR0_DQS1P  
DDRSS Data  
DDRSS Data  
K1  
DDRSS Data  
N4  
DDRSS Data  
N2  
DDRSS Data  
L4  
DDRSS Data  
L2  
DDRSS Data  
T1  
DDRSS Data  
T3  
DDRSS Data  
V3  
DDRSS Data  
U2  
DDRSS Data  
W2  
W4  
Y1  
DDRSS Data  
DDRSS Data  
DDRSS Data  
Y3  
DDRSS Data  
AB3  
AA2  
AA4  
Y5  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
AC2  
AB5  
AD2  
AC4  
H1  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Complimentary Data Strobe  
DDRSS Data Strobe  
DDRSS Complimentary Data Strobe  
DDRSS Data Strobe  
G1  
M1  
L1  
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TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
表6-6. DDRSS0 Signal Descriptions (continued)  
SIGNAL NAME  
DDR0_DQS2N  
PIN TYPE  
DESCRIPTION  
DDRSS Complimentary Data Strobe  
DDRSS Data Strobe  
ALZ PIN  
IO  
IO  
IO  
IO  
U1  
V1  
DDR0_DQS2P  
DDR0_DQS3N  
DDR0_DQS3P  
DDRSS Complimentary Data Strobe  
DDRSS Data Strobe  
AC1  
AB1  
(1) An external 240 Ω ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.  
表6-7. DDRSS1 Signal Descriptions  
SIGNAL NAME  
DDR1_CKN  
PIN TYPE  
IO  
IO  
IO  
I
DESCRIPTION  
DDRSS Differential Clock (negative)  
DDRSS Differential Clock (positive)  
DDRSS Reset  
ALZ PIN  
A9  
DDR1_CKP  
DDR1_RESETn  
DDR1_RET  
DDR1_CA0  
DDR1_CA1  
DDR1_CA2  
DDR1_CA3  
DDR1_CA4  
DDR1_CA5  
DDR1_CAL0(1)  
DDR1_CKE0  
DDR1_CKE1  
DDR1_CSn0_0  
DDR1_CSn0_1  
DDR1_CSn1_0  
DDR1_CSn1_1  
DDR1_DM0  
DDR1_DM1  
DDR1_DM2  
DDR1_DM3  
DDR1_DQ0  
DDR1_DQ1  
DDR1_DQ2  
DDR1_DQ3  
DDR1_DQ4  
DDR1_DQ5  
DDR1_DQ6  
DDR1_DQ7  
DDR1_DQ8  
DDR1_DQ9  
DDR1_DQ10  
DDR1_DQ11  
DDR1_DQ12  
DDR1_DQ13  
DDR1_DQ14  
DDR1_DQ15  
A10  
F12  
J10  
C10  
E10  
E9  
DDR Retention Enable  
DDRSS Command Address  
DDRSS Command Address  
DDRSS Command Address  
DDRSS Command Address  
DDRSS Command Address  
DDRSS Command Address  
IO Pad Calibration Resistor  
DDRSS Clock Enable  
DDRSS Clock Enable  
DDRSS Chip Select  
DDRSS Chip Select  
DDRSS Chip Select  
DDRSS Chip Select  
DDRSS Data Mask  
DDRSS Data Mask  
DDRSS Data Mask  
DDRSS Data Mask  
DDRSS Data  
IO  
IO  
IO  
IO  
IO  
IO  
A
B10  
D10  
C9  
E8  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
B9  
D9  
F9  
F8  
F11  
F10  
D16  
E13  
F7  
B3  
B18  
E17  
D18  
A17  
E15  
B16  
C15  
C17  
B14  
D14  
C13  
C11  
E11  
A11  
B12  
D12  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
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TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
表6-7. DDRSS1 Signal Descriptions (continued)  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
B7  
DDR1_DQ16  
DDR1_DQ17  
DDR1_DQ18  
DDR1_DQ19  
DDR1_DQ20  
DDR1_DQ21  
DDR1_DQ22  
DDR1_DQ23  
DDR1_DQ24  
DDR1_DQ25  
DDR1_DQ26  
DDR1_DQ27  
DDR1_DQ28  
DDR1_DQ29  
DDR1_DQ30  
DDR1_DQ31  
DDR1_DQS0N  
DDR1_DQS0P  
DDR1_DQS1N  
DDR1_DQS1P  
DDR1_DQS2N  
DDR1_DQS2P  
DDR1_DQS3N  
DDR1_DQS3P  
IO  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
IO  
D7  
IO  
C8  
IO  
A8  
IO  
C6  
IO  
E6  
IO  
B5  
IO  
D5  
IO  
B1  
IO  
A4  
IO  
C4  
IO  
E4  
IO  
D1  
IO  
D3  
IO  
C2  
IO  
E2  
IO  
DDRSS Complimentary Data Strobe  
DDRSS Data Strobe  
A15  
A16  
A12  
A13  
A7  
IO  
IO  
DDRSS Complimentary Data Strobe  
DDRSS Data Strobe  
IO  
IO  
DDRSS Complimentary Data Strobe  
DDRSS Data Strobe  
IO  
A6  
IO  
DDRSS Complimentary Data Strobe  
DDRSS Data Strobe  
A2  
IO  
A3  
(1) An external 240 Ω ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.  
6.3.3 GPIO  
6.3.3.1 MAIN Domain  
表6-8. GPIO0 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
AG24  
W25  
GPIO0_0  
GPIO0_1  
GPIO0_2  
GPIO0_3  
GPIO0_4  
GPIO0_5  
GPIO0_6  
GPIO0_7  
GPIO0_8  
GPIO0_9  
GPIO0_10  
GPIO0_11  
GPIO0_12  
GPIO0_13  
GPIO0_14  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
AC24  
AE28  
AF28  
AD25  
W23  
Y24  
AA23  
Y28  
AB24  
V23  
T26  
AD24  
AB28  
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TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
表6-8. GPIO0 Signal Descriptions (continued)  
SIGNAL NAME  
PIN TYPE  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
DESCRIPTION  
ALZ PIN  
GPIO0_15  
GPIO0_16  
GPIO0_17  
GPIO0_18  
GPIO0_19  
GPIO0_20  
GPIO0_21  
GPIO0_22  
GPIO0_23  
GPIO0_24  
GPIO0_25  
GPIO0_26  
GPIO0_27  
GPIO0_28  
GPIO0_29  
GPIO0_30  
GPIO0_31  
GPIO0_32  
GPIO0_33  
GPIO0_34  
GPIO0_35  
GPIO0_36  
GPIO0_37  
GPIO0_38  
GPIO0_39  
GPIO0_40  
GPIO0_41  
GPIO0_42  
GPIO0_43  
GPIO0_44  
GPIO0_45  
GPIO0_46  
GPIO0_47  
GPIO0_48  
GPIO0_49  
GPIO0_50  
GPIO0_51  
GPIO0_52  
GPIO0_53  
GPIO0_54  
GPIO0_55  
GPIO0_56  
GPIO0_57  
GPIO0_58  
GPIO0_59  
General Purpose Input/Output  
U27  
AC28  
Y26  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
AB27  
V27  
W27  
Y27  
AA27  
AA26  
AC27  
W28  
U28  
V26  
R27  
R28  
Y25  
T27  
U26  
AA28  
AD27  
T25  
W24  
AA25  
V25  
T24  
AB25  
T23  
U24  
AC25  
AD26  
U25  
AA24  
V28  
T28  
AB26  
AD28  
AE27  
AF26  
AH27  
AG26  
AH26  
AH25  
AE24  
AE25  
AG25  
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TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
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ZHCSRF7 –DECEMBER 2022  
表6-8. GPIO0 Signal Descriptions (continued)  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
R22  
GPIO0_60  
GPIO0_61  
GPIO0_62  
GPIO0_63  
GPIO0_64  
GPIO0_65  
IO  
IO  
IO  
IO  
IO  
IO  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
R24  
P24  
M23  
P23  
N24  
6.3.3.2 WKUP Domain  
表6-9. WKUP_GPIO0 Signal Descriptions  
SIGNAL NAME  
WKUP_GPIO0_0  
WKUP_GPIO0_1  
WKUP_GPIO0_2  
WKUP_GPIO0_3  
WKUP_GPIO0_4  
WKUP_GPIO0_5  
WKUP_GPIO0_6  
WKUP_GPIO0_7  
WKUP_GPIO0_8  
WKUP_GPIO0_9  
WKUP_GPIO0_10  
WKUP_GPIO0_11  
WKUP_GPIO0_12  
WKUP_GPIO0_13  
WKUP_GPIO0_14  
WKUP_GPIO0_15  
WKUP_GPIO0_16  
WKUP_GPIO0_17  
WKUP_GPIO0_18  
WKUP_GPIO0_19  
WKUP_GPIO0_20  
WKUP_GPIO0_21  
WKUP_GPIO0_22  
WKUP_GPIO0_23  
WKUP_GPIO0_24  
WKUP_GPIO0_25  
WKUP_GPIO0_26  
WKUP_GPIO0_27  
WKUP_GPIO0_28  
WKUP_GPIO0_29  
WKUP_GPIO0_30  
WKUP_GPIO0_31  
WKUP_GPIO0_32  
WKUP_GPIO0_33  
WKUP_GPIO0_34  
PIN TYPE  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
DESCRIPTION  
ALZ PIN  
D26  
E24  
C28  
C27  
C23  
F26  
E25  
F28  
F24  
H26  
F27  
F25  
C25  
C24  
B24  
D25  
D19  
E20  
E18  
C19  
F16  
G15  
F18  
E19  
G19  
F19  
F20  
F15  
G17  
F14  
F17  
A19  
B20  
B19  
D21  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
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TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
www.ti.com.cn  
表6-9. WKUP_GPIO0 Signal Descriptions (continued)  
SIGNAL NAME  
WKUP_GPIO0_35  
PIN TYPE  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
I
DESCRIPTION  
ALZ PIN  
General Purpose Input/Output  
G20  
C20  
A20  
D20  
C21  
F22  
E23  
E22  
E21  
G22  
F23  
F21  
D22  
D23  
K26  
B21  
B22  
A22  
A21  
B27  
D24  
G27  
J26  
WKUP_GPIO0_36  
WKUP_GPIO0_37  
WKUP_GPIO0_38  
WKUP_GPIO0_39  
WKUP_GPIO0_40  
WKUP_GPIO0_41  
WKUP_GPIO0_42  
WKUP_GPIO0_43  
WKUP_GPIO0_44  
WKUP_GPIO0_45  
WKUP_GPIO0_46  
WKUP_GPIO0_47  
WKUP_GPIO0_48  
WKUP_GPIO0_49  
WKUP_GPIO0_50  
WKUP_GPIO0_51  
WKUP_GPIO0_52  
WKUP_GPIO0_53  
WKUP_GPIO0_54  
WKUP_GPIO0_55  
WKUP_GPIO0_56  
WKUP_GPIO0_57  
WKUP_GPIO0_58  
WKUP_GPIO0_59  
WKUP_GPIO0_60  
WKUP_GPIO0_61  
WKUP_GPIO0_62  
WKUP_GPIO0_63  
WKUP_GPIO0_64  
WKUP_GPIO0_65  
WKUP_GPIO0_66  
WKUP_GPIO0_67  
WKUP_GPIO0_68  
WKUP_GPIO0_69  
WKUP_GPIO0_70  
WKUP_GPIO0_71  
WKUP_GPIO0_72  
WKUP_GPIO0_73  
WKUP_GPIO0_74  
WKUP_GPIO0_75  
WKUP_GPIO0_76  
WKUP_GPIO0_77  
WKUP_GPIO0_78  
WKUP_GPIO0_79  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
D28  
D27  
E27  
E28  
C22  
H24  
H27  
G24  
G25  
J27  
A23  
B25  
B26  
L25  
K25  
M24  
L24  
L27  
K24  
M27  
M26  
P25  
I
I
I
I
I
I
I
I
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TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
表6-9. WKUP_GPIO0 Signal Descriptions (continued)  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
R25  
P28  
WKUP_GPIO0_80  
WKUP_GPIO0_81  
WKUP_GPIO0_82  
WKUP_GPIO0_83  
WKUP_GPIO0_84  
WKUP_GPIO0_85  
WKUP_GPIO0_86  
WKUP_GPIO0_87  
WKUP_GPIO0_88  
I
General Purpose Input/Output  
I
I
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
P27  
I
N25  
P26  
I
I
N26  
N27  
J25  
I
IO  
IO  
G26  
6.3.4 I2C  
6.3.4.1 MAIN Domain  
表6-10. I2C0 Signal Descriptions  
SIGNAL NAME  
I2C0_SCL  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
AH25  
IOD  
IOD  
I2C Clock  
I2C Data  
I2C0_SDA  
AE24  
表6-11. I2C1 Signal Descriptions  
SIGNAL NAME  
I2C1_SCL  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
IOD  
IOD  
I2C Clock  
I2C Data  
AA23, AB26, AC25  
AD26, AD28, Y28  
I2C1_SDA  
表6-12. I2C2 Signal Descriptions  
SIGNAL NAME  
I2C2_SCL  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
AH27, V27  
AG26, W27  
IOD  
IOD  
I2C Clock  
I2C Data  
I2C2_SDA  
表6-13. I2C3 Signal Descriptions  
SIGNAL NAME  
I2C3_SCL  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
R22, W28  
AC27, R24  
IOD  
IOD  
I2C Clock  
I2C Data  
I2C3_SDA  
表6-14. I2C4 Signal Descriptions  
SIGNAL NAME  
I2C4_SCL  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
IOD  
IOD  
I2C Clock  
I2C Data  
AA28, AD25, M23  
AF28, P24, U26  
I2C4_SDA  
表6-15. I2C5 Signal Descriptions  
SIGNAL NAME  
I2C5_SCL  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
R28, Y24  
W23, Y25  
IOD  
IOD  
I2C Clock  
I2C Data  
I2C5_SDA  
表6-16. I2C6 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
I2C6_SCL  
IOD  
I2C Clock  
AG25, N24  
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ZHCSRF7 –DECEMBER 2022  
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表6-16. I2C6 Signal Descriptions (continued)  
SIGNAL NAME  
I2C6_SDA  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
IOD  
I2C Data  
AE25, P23  
6.3.4.2 MCU Domain  
表6-17. MCU_I2C0 Signal Descriptions  
SIGNAL NAME  
MCU_I2C0_SCL  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
G24  
IOD  
IOD  
I2C Clock  
I2C Data  
MCU_I2C0_SDA  
J25  
表6-18. MCU_I2C1 Signal Descriptions  
SIGNAL NAME  
MCU_I2C1_SCL  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
E25, F24  
F28, H26  
IOD  
IOD  
I2C Clock  
I2C Data  
MCU_I2C1_SDA  
6.3.4.3 WKUP Domain  
表6-19. WKUP_I2C0 Signal Descriptions  
SIGNAL NAME  
WKUP_I2C0_SCL  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
H24  
IOD  
I2C Clock  
I2C Data  
WKUP_I2C0_SDA  
IOD  
H27  
6.3.5 I3C  
6.3.5.1 MCU Domain  
表6-20. MCU_I3C0 Signal Descriptions  
SIGNAL NAME  
MCU_I3C0_SCL  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
F24  
IO  
IO  
I3C Clock  
I3C Data  
MCU_I3C0_SDA  
H26  
MCU_I3C0_SDAPULLEN  
OD  
I3C Data Pull Enable  
F25, G26  
6.3.6 MCAN  
6.3.6.1 MAIN Domain  
表6-21. MCAN0 Signal Descriptions  
SIGNAL NAME  
MCAN0_RX  
PIN TYPE  
DESCRIPTION  
MCAN Receive Data  
MCAN Transmit Data  
ALZ PIN  
U28  
I
MCAN0_TX  
O
W28  
表6-22. MCAN1 Signal Descriptions  
SIGNAL NAME  
MCAN1_RX  
PIN TYPE  
DESCRIPTION  
MCAN Receive Data  
MCAN Transmit Data  
ALZ PIN  
AD28, R27  
V26  
I
MCAN1_TX  
O
表6-23. MCAN2 Signal Descriptions  
SIGNAL NAME  
MCAN2_RX  
PIN TYPE  
DESCRIPTION  
MCAN Receive Data  
MCAN Transmit Data  
ALZ PIN  
Y25  
I
MCAN2_TX  
O
R28  
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www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
表6-24. MCAN3 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
MCAN Receive Data  
MCAN Transmit Data  
ALZ PIN  
U26  
MCAN3_RX  
MCAN3_TX  
I
O
T27  
表6-25. MCAN4 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
MCAN Receive Data  
MCAN Transmit Data  
ALZ PIN  
AD27  
MCAN4_RX  
MCAN4_TX  
I
O
AA28  
表6-26. MCAN5 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
MCAN Receive Data  
MCAN Transmit Data  
ALZ PIN  
U27, W24  
AB28, T25  
MCAN5_RX  
MCAN5_TX  
I
O
表6-27. MCAN6 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
MCAN Receive Data  
MCAN Transmit Data  
ALZ PIN  
V25, Y26  
MCAN6_RX  
MCAN6_TX  
I
O
AA25, AC28  
表6-28. MCAN7 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
MCAN Receive Data  
MCAN Transmit Data  
ALZ PIN  
AB25, V27  
AB27, T24  
MCAN7_RX  
MCAN7_TX  
I
O
表6-29. MCAN8 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
MCAN Receive Data  
MCAN Transmit Data  
ALZ PIN  
U24, Y27  
T23, W27  
MCAN8_RX  
MCAN8_TX  
I
O
表6-30. MCAN9 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
MCAN Receive Data  
MCAN Transmit Data  
ALZ PIN  
MCAN9_RX  
MCAN9_TX  
I
AA26, AD26  
AA27, AC25  
O
表6-31. MCAN10 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
MCAN Receive Data  
MCAN Transmit Data  
ALZ PIN  
AA24  
MCAN10_RX  
MCAN10_TX  
I
O
U25  
表6-32. MCAN11 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
MCAN Receive Data  
MCAN Transmit Data  
ALZ PIN  
T28  
MCAN11_RX  
MCAN11_TX  
I
O
V28  
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ZHCSRF7 –DECEMBER 2022  
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表6-33. MCAN12 Signal Descriptions  
SIGNAL NAME  
MCAN12_RX  
MCAN12_TX  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
I
MCAN Receive Data  
MCAN Transmit Data  
AC24, T26  
AB26, W25  
O
表6-34. MCAN13 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
MCAN Receive Data  
MCAN Transmit Data  
ALZ PIN  
MCAN13_RX  
MCAN13_TX  
I
AF28, AG25  
AE25, AE28  
O
表6-35. MCAN14 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
MCAN Receive Data  
MCAN Transmit Data  
ALZ PIN  
AF26, W23  
AD25, AE27  
MCAN14_RX  
MCAN14_TX  
I
O
表6-36. MCAN15 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
MCAN Receive Data  
MCAN Transmit Data  
ALZ PIN  
AA23, N24  
P23, Y24  
MCAN15_RX  
MCAN15_TX  
I
O
表6-37. MCAN16 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
MCAN Receive Data  
MCAN Transmit Data  
ALZ PIN  
AB24  
MCAN16_RX  
MCAN16_TX  
I
O
Y28  
表6-38. MCAN17 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
MCAN Receive Data  
MCAN Transmit Data  
ALZ PIN  
AC27, AD24  
V23  
MCAN17_RX  
MCAN17_TX  
I
O
6.3.6.2 MCU Domain  
表6-39. MCU_MCAN0 Signal Descriptions  
SIGNAL NAME  
MCU_MCAN0_RX  
PIN TYPE  
DESCRIPTION  
MCAN Receive Data  
MCAN Transmit Data  
ALZ PIN  
E28  
I
MCU_MCAN0_TX  
O
E27  
表6-40. MCU_MCAN1 Signal Descriptions  
SIGNAL NAME  
MCU_MCAN1_RX  
PIN TYPE  
DESCRIPTION  
MCAN Receive Data  
MCAN Transmit Data  
ALZ PIN  
F26  
I
MCU_MCAN1_TX  
O
C23  
6.3.7 MCSPI  
6.3.7.1 MAIN Domain  
表6-41. MCSPI0 Signal Descriptions  
SIGNAL NAME  
SPI0_CLK  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
AH27  
IO  
IO  
SPI Clock  
SPI0_CS0  
SPI Chip Select 0  
AE27  
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TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
www.ti.com.cn  
ZHCSRF7 –DECEMBER 2022  
表6-41. MCSPI0 Signal Descriptions (continued)  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
AF26  
SPI0_CS1  
SPI0_CS2  
SPI0_CS3  
SPI0_D0  
SPI0_D1  
IO  
IO  
IO  
IO  
IO  
SPI Chip Select 1  
SPI Chip Select 2  
SPI Chip Select 3  
SPI Data 0  
AA23  
AB24  
AG26  
AH26  
SPI Data 1  
表6-42. MCSPI1 Signal Descriptions  
SIGNAL NAME  
SIGNAL NAME  
SIGNAL NAME  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
P23  
SPI1_CLK  
SPI1_CS0  
SPI1_CS1  
SPI1_CS2  
SPI1_CS3  
SPI1_D0  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
SPI Clock  
SPI Chip Select 0  
SPI Chip Select 1  
SPI Chip Select 2  
SPI Chip Select 3  
SPI Data 0  
R22  
R24  
P24  
Y28  
M23  
N24  
SPI1_D1  
SPI Data 1  
表6-43. MCSPI2 Signal Descriptions  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
AB25  
T23  
SPI2_CLK  
SPI2_CS0  
SPI2_CS1  
SPI2_CS2  
SPI2_CS3  
SPI2_D0  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
SPI Clock  
SPI Chip Select 0  
SPI Chip Select 1  
SPI Chip Select 2  
SPI Chip Select 3  
SPI Data 0  
T24  
AC28  
Y26  
U24  
SPI2_D1  
SPI Data 1  
AC25  
表6-44. MCSPI3 Signal Descriptions  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
T28  
SPI3_CLK  
SPI3_CS0  
SPI3_CS1  
SPI3_CS2  
SPI3_CS3  
SPI3_D0  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
SPI Clock  
SPI Chip Select 0  
SPI Chip Select 1  
SPI Chip Select 2  
SPI Chip Select 3  
SPI Data 0  
V28  
T27  
AD27  
AA24  
V27  
SPI3_D1  
SPI Data 1  
W27  
表6-45. MCSPI5 Signal Descriptions  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
T27  
SPI5_CLK  
SPI5_CS0  
SPI5_CS1  
SPI5_CS2  
SPI5_CS3  
SPI5_D0  
IO  
IO  
IO  
IO  
IO  
IO  
SPI Clock  
SPI Chip Select 0  
SPI Chip Select 1  
SPI Chip Select 2  
SPI Chip Select 3  
SPI Data 0  
U28  
W28  
Y27  
AA27  
R27  
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TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
ZHCSRF7 –DECEMBER 2022  
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表6-45. MCSPI5 Signal Descriptions (continued)  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
SPI5_D1  
IO  
SPI Data 1  
AD27  
表6-46. MCSPI6 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
T26  
SPI6_CLK  
SPI6_CS0  
SPI6_CS1  
SPI6_CS2  
SPI6_CS3  
SPI6_D0  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
SPI Clock  
SPI Chip Select 0  
SPI Chip Select 1  
SPI Chip Select 2  
SPI Chip Select 3  
SPI Data 0  
AD24  
Y25  
U26  
AA28  
AB26  
R28  
SPI6_D1  
SPI Data 1  
表6-47. MCSPI7 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
AC28  
Y26  
SPI7_CLK  
SPI7_CS0  
SPI7_CS1  
SPI7_CS2  
SPI7_CS3  
SPI7_D0  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
SPI Clock  
SPI Chip Select 0  
SPI Chip Select 1  
SPI Chip Select 2  
SPI Chip Select 3  
SPI Data 0  
Y27  
AA27  
V23  
U28  
SPI7_D1  
SPI Data 1  
T27  
6.3.7.2 MCU Domain  
表6-48. MCU_MCSPI0 Signal Descriptions  
SIGNAL NAME  
MCU_SPI0_CLK  
MCU_SPI0_CS0  
MCU_SPI0_CS1  
MCU_SPI0_CS2  
MCU_SPI0_CS3  
MCU_SPI0_D0  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
B27  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
SPI Clock  
SPI Chip Select 0  
SPI Chip Select 1  
SPI Chip Select 2  
SPI Chip Select 3  
SPI Data 0  
B26  
A20, C25  
B24, C21  
C23  
D24  
MCU_SPI0_D1  
SPI Data 1  
B25  
表6-49. MCU_MCSPI1 Signal Descriptions  
SIGNAL NAME  
MCU_SPI1_CLK  
MCU_SPI1_CS0  
MCU_SPI1_CS1  
MCU_SPI1_CS2  
MCU_SPI1_CS3  
MCU_SPI1_D0  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
D26  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
SPI Clock  
SPI Chip Select 0  
SPI Chip Select 1  
SPI Chip Select 2  
SPI Chip Select 3  
SPI Data 0  
C27  
C24, G20  
C20, D25  
F26  
E24  
MCU_SPI1_D1  
SPI Data 1  
C28  
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6.3.8 UART  
6.3.8.1 MAIN Domain  
表6-50. UART0 Signal Descriptions  
SIGNAL NAME  
UART0_CTSn  
UART0_DCDn  
UART0_DSRn  
UART0_DTRn  
UART0_RIn  
PIN TYPE  
DESCRIPTION  
UART Clear to Send (active low)  
UART Data Carrier Detect (active low)  
UART Data Set Ready (active low)  
UART Data Terminal Ready (active low)  
UART Ring Indicator  
ALZ PIN  
R22, V27  
AC24  
I
I
I
AE28  
O
I
AF28  
AD25  
UART0_RTSn  
UART0_RXD  
O
I
UART Request to Send (active low)  
UART Receive Data  
AF26, P23, W27  
V28  
UART0_TXD  
O
UART Transmit Data  
T28  
表6-51. UART1 Signal Descriptions  
SIGNAL NAME  
UART1_CTSn  
PIN TYPE  
DESCRIPTION  
UART Clear to Send (active low)  
UART Request to Send (active low)  
UART Receive Data  
ALZ PIN  
AA26, AH27  
AC27, AG26  
Y27  
I
UART1_RTSn  
O
I
UART1_RXD  
UART1_TXD  
O
UART Transmit Data  
AA27  
表6-52. UART2 Signal Descriptions  
SIGNAL NAME  
UART2_CTSn  
PIN TYPE  
DESCRIPTION  
UART Clear to Send (active low)  
UART Request to Send (active low)  
UART Receive Data  
ALZ PIN  
AB26  
I
UART2_RTSn  
O
I
AD28  
UART2_RXD  
AG26, P24, W28  
AH26, M23, U28  
UART2_TXD  
O
UART Transmit Data  
表6-53. UART3 Signal Descriptions  
SIGNAL NAME  
UART3_CTSn  
PIN TYPE  
DESCRIPTION  
UART Clear to Send (active low)  
UART Request to Send (active low)  
UART Receive Data  
ALZ PIN  
T27  
I
UART3_RTSn  
O
I
R27  
UART3_RXD  
AB26, AE25, R28  
AD28, AG25, Y25  
UART3_TXD  
O
UART Transmit Data  
表6-54. UART4 Signal Descriptions  
SIGNAL NAME  
UART4_CTSn  
PIN TYPE  
DESCRIPTION  
UART Clear to Send (active low)  
UART Request to Send (active low)  
UART Receive Data  
ALZ PIN  
I
AA25, AB27, P23  
AA24, N24, V25  
UART4_RTSn  
O
I
UART4_RXD  
AC28, P24, T25, U25  
AE28, M23, W24, Y26  
UART4_TXD  
O
UART Transmit Data  
表6-55. UART5 Signal Descriptions  
SIGNAL NAME  
UART5_CTSn  
PIN TYPE  
DESCRIPTION  
UART Clear to Send (active low)  
UART Request to Send (active low)  
UART Receive Data  
ALZ PIN  
P24, T23  
I
O
I
UART5_RTSn  
M23, U24  
UART5_RXD  
AC24, R22, T24  
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表6-55. UART5 Signal Descriptions (continued)  
SIGNAL NAME  
UART5_TXD  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
O
UART Transmit Data  
AB25, R24, W25  
表6-56. UART6 Signal Descriptions  
SIGNAL NAME  
UART6_CTSn  
PIN TYPE  
DESCRIPTION  
UART Clear to Send (active low)  
UART Request to Send (active low)  
UART Receive Data  
ALZ PIN  
W28  
I
UART6_RTSn  
UART6_RXD  
UART6_TXD  
O
I
U28  
AA26, AD25, T26  
AC27, AF28, V26  
O
UART Transmit Data  
表6-57. UART7 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
UART Clear to Send (active low)  
UART Request to Send (active low)  
UART Receive Data  
ALZ PIN  
P24  
UART7_CTSn  
UART7_RTSn  
UART7_RXD  
UART7_TXD  
I
O
I
M23  
R22, T23, V23  
AD24, R24, U24  
O
UART Transmit Data  
表6-58. UART8 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
UART Clear to Send (active low)  
UART Request to Send (active low)  
UART Receive Data  
ALZ PIN  
AC28  
UART8_CTSn  
UART8_RTSn  
UART8_RXD  
UART8_TXD  
I
O
I
Y26  
AB28, AC25, AF26, P23  
AD26, AH27, N24, U27  
O
UART Transmit Data  
表6-59. UART9 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
UART Clear to Send (active low)  
UART Request to Send (active low)  
UART Receive Data  
ALZ PIN  
AB27, T26  
AA24, AD24  
V27, Y24  
UART9_CTSn  
UART9_RTSn  
UART9_RXD  
UART9_TXD  
I
O
I
O
UART Transmit Data  
W23, W27  
表6-60. VPU0_UART Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
UART Receive Data  
UART Transmit Data  
ALZ PIN  
AF26  
VPU0_UART_RXD  
VPU0_UART_TXD  
I
O
AH27  
6.3.8.2 MCU Domain  
表6-61. MCU_UART0 Signal Descriptions  
SIGNAL NAME  
MCU_UART0_CTSn  
MCU_UART0_RTSn  
MCU_UART0_RXD  
MCU_UART0_TXD  
PIN TYPE  
DESCRIPTION  
UART Clear to Send (active low)  
UART Request to Send (active low)  
UART Receive Data  
ALZ PIN  
A20, B24  
I
O
I
C21, D25  
C24, F25, G20  
C20, C25, F27  
O
UART Transmit Data  
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6.3.8.3 WKUP Domain  
表6-62. WKUP_UART0 Signal Descriptions  
SIGNAL NAME  
WKUP_UART0_CTSn  
WKUP_UART0_RTSn  
WKUP_UART0_RXD  
WKUP_UART0_TXD  
PIN TYPE  
DESCRIPTION  
UART Clear to Send (active low)  
UART Request to Send (active low)  
UART Receive Data  
ALZ PIN  
E25  
I
O
I
F28  
D28  
O
UART Transmit Data  
D27  
6.3.9 MDIO  
6.3.9.1 MAIN Domain  
表6-63. MDIO0 Signal Descriptions  
SIGNAL NAME  
MDIO0_MDC  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
T28  
O
MDIO Clock  
MDIO Data  
MDIO0_MDIO  
IO  
V28  
6.3.9.2 MCU Domain  
表6-64. MCU_MDIO0 Signal Descriptions  
SIGNAL NAME  
MCU_MDIO0_MDC  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
A21  
O
MDIO Clock  
MDIO Data  
MCU_MDIO0_MDIO  
IO  
A22  
6.3.10 CPSW2G  
6.3.10.1 MAIN Domain  
表6-65. CPSW2G0 Signal Descriptions  
SIGNAL NAME  
CLKOUT  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
U24  
IO  
I
RMII Clock Output  
RGMII1_RXC  
RGMII1_RX_CTL  
RGMII1_TXC  
RGMII1_TX_CTL  
RGMII1_RD0  
RGMII1_RD1  
RGMII1_RD2  
RGMII1_RD3  
RGMII1_TD0  
RGMII1_TD1  
RGMII1_TD2  
RGMII1_TD3  
RMII1_CRS_DV  
RMII1_RX_ER  
RMII1_TX_EN  
RMII1_RXD0  
RMII1_RXD1  
RMII1_TXD0  
RGMII Receive Clock  
RGMII Receive Control  
RGMII Transmit Clock  
RGMII Transmit Control  
RGMII Receive Data 0  
RGMII Receive Data 1  
RGMII Receive Data 2  
RGMII Receive Data 3  
RGMII Transmit Data 0  
RGMII Transmit Data 1  
RGMII Transmit Data 2  
RGMII Transmit Data 3  
RMII Carrier Sense / Data Valid  
RMII Receive Data Error  
RMII Transmit Enable  
RMII Receive Data 0  
AD26  
AC25  
U25  
I
O
O
I
T24  
AA24  
AB25  
T23  
I
I
I
U24  
O
O
O
O
I
T25  
W24  
AA25  
V25  
V25  
I
T24  
O
I
AC25  
W24  
AA25  
AB25  
AD26  
I
RMII Receive Data 1  
O
O
RMII Transmit Data 0  
RMII Transmit Data 1  
RMII1_TXD1  
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表6-65. CPSW2G0 Signal Descriptions (continued)  
SIGNAL NAME  
RMII_REF_CLK  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
I
RMII Reference Clock  
T23  
6.3.10.2 MCU Domain  
表6-66. MCU_CPSW2G0 Signal Descriptions  
SIGNAL NAME  
MCU_RGMII1_RXC  
MCU_RGMII1_RX_CTL  
MCU_RGMII1_TXC  
MCU_RGMII1_TX_CTL  
MCU_RGMII1_RD0  
MCU_RGMII1_RD1  
MCU_RGMII1_RD2  
MCU_RGMII1_RD3  
MCU_RGMII1_TD0  
MCU_RGMII1_TD1  
MCU_RGMII1_TD2  
MCU_RGMII1_TD3  
MCU_RMII1_CRS_DV  
MCU_RMII1_REF_CLK  
MCU_RMII1_RX_ER  
MCU_RMII1_TX_EN  
MCU_RMII1_RXD0  
MCU_RMII1_RXD1  
MCU_RMII1_TXD0  
MCU_RMII1_TXD1  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
D22  
E23  
F21  
F22  
B22  
B21  
C22  
D23  
F23  
G22  
E21  
E22  
F22  
D22  
E23  
F21  
B22  
B21  
F23  
G22  
I
I
RGMII Receive Clock  
RGMII Receive Control  
RGMII Transmit Clock  
RGMII Transmit Control  
RGMII Receive Data 0  
RGMII Receive Data 1  
RGMII Receive Data 2  
RGMII Receive Data 3  
RGMII Transmit Data 0  
RGMII Transmit Data 1  
RGMII Transmit Data 2  
RGMII Transmit Data 3  
RMII Carrier Sense / Data Valid  
RMII Reference Clock  
RMII Receive Data Error  
RMII Transmit Enable  
RMII Receive Data 0  
O
O
I
I
I
I
O
O
O
O
I
I
I
O
I
I
RMII Receive Data 1  
O
O
RMII Transmit Data 0  
RMII Transmit Data 1  
6.3.11 ECAP  
6.3.11.1 MAIN Domain  
表6-67. ECAP0 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
Enhanced Capture (ECAP) Input or Auxiliary PWM  
(APWM) Ouput  
ECAP0_IN_APWM_OUT  
IO  
AB26, P24  
表6-68. ECAP1 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
Enhanced Capture (ECAP) Input or Auxiliary PWM  
(APWM) Ouput  
ECAP1_IN_APWM_OUT  
IO  
AE25, M23  
表6-69. ECAP2 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
Enhanced Capture (ECAP) Input or Auxiliary PWM  
(APWM) Ouput  
ECAP2_IN_APWM_OUT  
IO  
AG25  
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6.3.12 EQEP  
6.3.12.1 MAIN Domain  
表6-70. EQEP0 Signal Descriptions  
SIGNAL NAME  
EQEP0_A  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
U24  
I
EQEP Quadrature Input A  
EQEP0_B  
I
EQEP Quadrature Input B  
EQEP Index  
AC25  
V28  
EQEP0_I  
IO  
IO  
EQEP0_S  
EQEP Strobe  
AA24  
表6-71. EQEP1 Signal Descriptions  
SIGNAL NAME  
EQEP1_A  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
AD26  
U25  
I
EQEP Quadrature Input A  
EQEP1_B  
I
EQEP Quadrature Input B  
EQEP Index  
EQEP1_I  
IO  
IO  
T26  
EQEP1_S  
EQEP Strobe  
T28  
表6-72. EQEP2 Signal Descriptions  
SIGNAL NAME  
EQEP2_A  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
AB27  
W27  
I
EQEP Quadrature Input A  
EQEP2_B  
I
EQEP Quadrature Input B  
EQEP Index  
EQEP2_I  
IO  
IO  
AA26  
Y27  
EQEP2_S  
EQEP Strobe  
6.3.13 EPWM  
6.3.13.1 MAIN Domain  
表6-73. EPWM Signal Descriptions  
SIGNAL NAME  
EHRPWM_SOCA  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
AA27  
AB25  
T27  
O
O
I
EHRPWM Start of Conversion A  
EHRPWM_SOCB  
EHRPWM Start of Conversion B  
EHRPWM_TZn_IN0  
EHRPWM_TZn_IN1  
EHRPWM_TZn_IN2  
EHRPWM_TZn_IN3  
EHRPWM_TZn_IN4  
EHRPWM_TZn_IN5  
EHRPWM Trip Zone Input 0 (active low)  
EHRPWM Trip Zone Input 1 (active low)  
EHRPWM Trip Zone Input 2 (active low)  
EHRPWM Trip Zone Input 3 (active low)  
EHRPWM Trip Zone Input 4 (active low)  
EHRPWM Trip Zone Input 5 (active low)  
I
V27  
I
AB28  
W24  
I
I
AD27  
V26  
I
表6-74. EPWM0 Signal Descriptions  
SIGNAL NAME  
EHRPWM0_A  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
AE27, R24, U28  
R22, W28  
IO  
IO  
I
EHRPWM Output A  
EHRPWM Output B  
EHRPWM0_B  
EHRPWM0_SYNCI  
EHRPWM0_SYNCO  
Sync Input to EHRPWM module from an external pin  
Sync Output to EHRPWM module to an external pin  
R27  
Y26  
O
表6-75. EPWM1 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
EHRPWM1_A  
IO  
EHRPWM Output A  
AC27, AF26, M23  
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表6-75. EPWM1 Signal Descriptions (continued)  
SIGNAL NAME  
EHRPWM1_B  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
IO  
EHRPWM Output B  
P24, R28  
表6-76. EPWM2 Signal Descriptions  
SIGNAL NAME  
EHRPWM2_A  
EHRPWM2_B  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
AC28, AH27, N24  
P23, U27  
IO  
IO  
EHRPWM Output A  
EHRPWM Output B  
表6-77. EPWM3 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
AG26, R22, T25  
T24  
EHRPWM3_A  
IO  
IO  
I
EHRPWM Output A  
EHRPWM Output B  
EHRPWM3_B  
EHRPWM3_SYNCI  
EHRPWM3_SYNCO  
Sync Input to EHRPWM module from an external pin  
Sync Output to EHRPWM module to an external pin  
V25  
O
AA25  
表6-78. EPWM4 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
AH26, P24, T23  
Y25  
EHRPWM4_A  
EHRPWM4_B  
IO  
IO  
EHRPWM Output A  
EHRPWM Output B  
表6-79. EPWM5 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
AA28, P23  
U26  
EHRPWM5_A  
EHRPWM5_B  
IO  
IO  
EHRPWM Output A  
EHRPWM Output B  
6.3.14 USB  
6.3.14.1 MAIN Domain  
表6-80. USB0 Signal Descriptions  
SIGNAL NAME  
USB0_DM  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
AG2  
IO  
IO  
O
A
A
A
I
USB 2.0 Differential Data (negative)  
USB0_DP  
USB 2.0 Differential Data (positive)  
AH2  
USB0_DRVVBUS  
USB0_ID  
USB VBUS Control Output (active high)  
AG25, T25, V23  
AC9  
USB 2.0 Dual-Role Device Role Select  
USB0_RCALIB(1)  
USB0_VBUS(2)  
USB0_SSRX1N  
USB0_SSRX1P  
USB0_SSRX2N  
USB0_SSRX2P  
USB0_SSTX1N  
USB0_SSTX1P  
USB0_SSTX2N  
USB0_SSTX2P  
Pin to connect to calibration resistor  
AA6  
USB Level-shifted VBUS Detector  
AA8  
SERDES_USB Differential Receive Data (negative)  
SERDES_USB Differential Receive Data (positive)  
SERDES_USB Differential Receive Data (negative)  
SERDES_USB Differential Receive Data (positive)  
SERDES_USB Differential Transmit Data (negative)  
SERDES_USB Differential Transmit Data (positive)  
SERDES_USB Differential Transmit Data (negative)  
SERDES_USB Differential Transmit Data (positive)  
AF6, AF9  
AF10, AF7  
AE5, AE8  
AE6, AE9  
AG5, AH7  
AG6, AH8  
AD7, AG8  
AD8, AG9  
I
I
I
O
O
O
O
(1) An external 500 Ω ±1% resistor must be connected between this pin and VSS, even when the pin is unused.  
(2) An external resistor divider is required to limit the voltage applied to the device pin. For more information, see USB VBUS Design  
Guidelines.  
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6.3.15 Display Port  
6.3.15.1 MAIN Domain  
表6-81. DP0 Signal Descriptions  
SIGNAL NAME  
DP0_AUXN  
DP0_AUXP  
DP0_HPD  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
IO  
IO  
I
Display Port Differential Auxiliary Data (negative)  
Display Port Differential Auxiliary Data (positive)  
Display Port Hot Plug Detection  
AG11  
AF11  
AA24  
DP0_TXN0  
O
O
O
O
O
O
O
O
Display Port Differential Transmit (negative)  
Display Port Differential Transmit (negative)  
Display Port Differential Transmit (negative)  
Display Port Differential Transmit (negative)  
Display Port Differential Transmit (positive)  
Display Port Differential Transmit (positive)  
Display Port Differential Transmit (positive)  
Display Port Differential Transmit (positive)  
AG5, AH7  
AD7, AG8  
AG5  
DP0_TXN1  
DP0_TXN2  
DP0_TXN3  
AD7  
DP0_TXP0  
AG6, AH8  
AD8, AG9  
AG6  
DP0_TXP1  
DP0_TXP2  
DP0_TXP3  
AD8  
6.3.16 Hyperlink  
备注  
This SoC does not support Hyperlink. A customer design should not use signals HYP_*, HYP0_*,  
HYP1_*.  
6.3.16.1 MAIN Domain  
表6-82. Hyperlink Signal Descriptions  
SIGNAL NAME  
HYP_RXN0  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
AF9  
I
I
Hyperlink RX (negative)  
HYP_RXN1  
HYP_RXN2  
HYP_RXN3  
HYP_RXP0  
HYP_RXP1  
HYP_RXP2  
HYP_RXP3  
HYP_TXN0  
HYP_TXN1  
HYP_TXN2  
HYP_TXN3  
HYP_TXP0  
HYP_TXP1  
HYP_TXP2  
HYP_TXP3  
Hyperlink RX (negative)  
Hyperlink RX (negative)  
Hyperlink RX (negative)  
Hyperlink RX (positive)  
Hyperlink RX (positive)  
Hyperlink RX (positive)  
Hyperlink RX (positive)  
Hyperlink TX0 (negative)  
Hyperlink TX0 (negative)  
Hyperlink TX0 (negative)  
Hyperlink TX0 (negative)  
Hyperlink TX0 (positive)  
Hyperlink TX0 (positive)  
Hyperlink TX0 (positive)  
Hyperlink TX0 (positive)  
AE8  
AF6  
I
I
AE5  
AF10  
AE9  
AF7  
I
I
I
I
AE6  
AH7  
AG8  
AG5  
AD7  
AH8  
AG9  
AG6  
AD8  
O
O
O
O
O
O
O
O
表6-83. Hyperlink0 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
AB28  
U27  
HYP0_RXFLCLK  
HYP0_RXFLDAT  
HYP0_RXPMCLK  
O
O
I
Hyperlink Flow Management Receive Clock  
Hyperlink Flow Management Receive Data  
Hyperlink Power Management Receive Clock  
AA26  
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表6-83. Hyperlink0 Signal Descriptions (continued)  
SIGNAL NAME  
HYP0_RXPMDAT  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
I
I
Hyperlink Power Management Receive Data  
Hyperlink Flow Management Transmit Clock  
Hyperlink Flow Management Transmit Data  
Hyperlink Power Management Transmit Clock  
Hyperlink Power Management Transmit Data  
AC27  
AC28  
Y26  
HYP0_TXFLCLK  
HYP0_TXFLDAT  
HYP0_TXPMCLK  
HYP0_TXPMDAT  
I
O
O
Y27  
AA27  
表6-84. Hyperlink1 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
AB27  
T26  
HYP1_RXFLCLK  
HYP1_RXFLDAT  
HYP1_RXPMCLK  
HYP1_RXPMDAT  
HYP1_TXFLCLK  
HYP1_TXFLDAT  
HYP1_TXPMCLK  
HYP1_TXPMDAT  
O
O
I
Hyperlink Flow Management Receive Clock  
Hyperlink Flow Management Receive Data  
Hyperlink Power Management Receive Clock  
Hyperlink Power Management Receive Data  
Hyperlink Flow Management Transmit Clock  
Hyperlink Flow Management Transmit Data  
Hyperlink Power Management Transmit Clock  
Hyperlink Power Management Transmit Data  
V27  
I
W27  
I
AB26  
AD28  
V26  
I
O
O
U26  
6.3.17 PCIE  
6.3.17.1 MAIN Domain  
表6-85. PCIE Signal Descriptions  
SIGNAL NAME  
PCIE1_CLKREQn  
PCIE1_RXN0  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
AE25, R22  
AF9  
IO  
I
PCIE Clock Request Signal  
SERDES_PCIE Differential Receive Data (negative)  
SERDES_PCIE Differential Receive Data (negative)  
SERDES_PCIE Differential Receive Data (negative)  
SERDES_PCIE Differential Receive Data (negative)  
SERDES_PCIE Differential Receive Data (positive)  
SERDES_PCIE Differential Receive Data (positive)  
SERDES_PCIE Differential Receive Data (positive)  
SERDES_PCIE Differential Receive Data (positive)  
SERDES_PCIE Differential Transmit Data (negative)  
SERDES_PCIE Differential Transmit Data (negative)  
SERDES_PCIE Differential Transmit Data (negative)  
SERDES_PCIE Differential Transmit Data (negative)  
SERDES_PCIE Differential Transmit Data (positive)  
SERDES_PCIE Differential Transmit Data (positive)  
SERDES_PCIE Differential Transmit Data (positive)  
SERDES_PCIE Differential Transmit Data (positive)  
SERDES_PCIE Reference Clock Out Negative  
SERDES_PCIE Reference Clock Out Positive  
PCIE1_RXN1  
I
AE8  
PCIE1_RXN2  
I
AF6  
PCIE1_RXN3  
I
AE5  
PCIE1_RXP0  
I
AF10  
AE9  
PCIE1_RXP1  
I
PCIE1_RXP2  
I
AF7  
PCIE1_RXP3  
I
AE6  
PCIE1_TXN0  
O
O
O
O
O
O
O
O
O
O
AH7  
PCIE1_TXN1  
AG8  
PCIE1_TXN2  
AG5  
PCIE1_TXN3  
AD7  
PCIE1_TXP0  
AH8  
PCIE1_TXP1  
AG9  
PCIE1_TXP2  
AG6  
PCIE1_TXP3  
AD8  
PCIE_REFCLK1_N_OUT  
PCIE_REFCLK1_P_OUT  
AH10  
AH11  
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6.3.18 SERDES  
6.3.18.1 MAIN Domain  
表6-86. SERDES0 Signal Descriptions  
SIGNAL NAME  
SERDES0_REFCLK_N  
SERDES0_REFCLK_P  
SERDES0_REXT(1)  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
IO  
IO  
I
Serdes Reference Clock Input/Output (negative)  
Serdes Reference Clock Input/Output (positive)  
External Calibration Resistor  
AH4  
AH5  
AC10  
(1) An external 3.01 kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.  
6.3.19 DSI  
6.3.19.1 MAIN Domain  
表6-87. DSI0 Signal Descriptions  
SIGNAL NAME  
DSI0_TXCLKN  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
AH13  
AH14  
AC13  
AG12  
AF13  
AE12  
AD13  
AG13  
AF14  
AE13  
AD14  
O
O
A
DSI Transmit clock (negative)  
DSI0_TXCLKP  
DSI0_TXRCALIB(1)  
DSI0_TXN0  
DSI0_TXN1  
DSI0_TXN2  
DSI0_TXN3  
DSI0_TXP0  
DSI0_TXP1  
DSI0_TXP2  
DSI0_TXP3  
DSI Transmit clock (positive)  
DSI Transmit Calibration Resistor  
DSI Transmit (negative)  
DSI Transmit (negative)  
DSI Transmit (negative)  
DSI Transmit (negative)  
DSI Transmit (positive)  
DSI Transmit (positive)  
DSI Transmit (positive)  
DSI Transmit (positive)  
IO  
O
O
O
IO  
O
O
O
(1) An external 500 Ω ±1% resistor must be connected between this pin and VSS, even when the pin is unused.  
表6-88. DSI1 Signal Descriptions  
SIGNAL NAME  
DSI1_TXCLKN  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
AH16  
AH17  
AC15  
AG15  
AF16  
AE15  
AD16  
AG16  
AF17  
AE16  
AD17  
O
O
A
DSI Transmit clock (negative)  
DSI1_TXCLKP  
DSI1_TXRCALIB(1)  
DSI1_TXN0  
DSI1_TXN1  
DSI1_TXN2  
DSI1_TXN3  
DSI1_TXP0  
DSI1_TXP1  
DSI1_TXP2  
DSI1_TXP3  
DSI Transmit clock (positive)  
DSI Transmit Calibration Resistor  
DSI Transmit (negative)  
DSI Transmit (negative)  
DSI Transmit (negative)  
DSI Transmit (negative)  
DSI Transmit (positive)  
DSI Transmit (positive)  
DSI Transmit (positive)  
DSI Transmit (positive)  
IO  
O
O
O
IO  
O
O
O
(1) An external 500 Ω ±1% resistor must be connected between this pin and VSS, even when the pin is unused.  
6.3.20 CSI  
6.3.20.1 MAIN Domain  
表6-89. CSI0 Signal Descriptions  
SIGNAL NAME  
CSI0_RXCLKN  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
I
CSI Differential Receive Clock Input (negative)  
AH19  
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表6-89. CSI0 Signal Descriptions (continued)  
SIGNAL NAME  
CSI0_RXCLKP  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
I
CSI Differential Receive Clock Input (positive)  
AH20  
AC18  
CSI Pin connected to external resistor for on-chip  
resistor calibration  
CSI0_RXRCALIB(1)  
A
CSI0_TXCLKN  
CSI0_TXCLKP  
CSI0_RXN0  
CSI0_RXN1  
CSI0_RXN2  
CSI0_RXN3  
CSI0_RXP0  
CSI0_RXP1  
CSI0_RXP2  
CSI0_RXP3  
CSI0_TXN0  
CSI0_TXN1  
CSI0_TXN2  
CSI0_TXN3  
CSI0_TXP0  
CSI0_TXP1  
CSI0_TXP2  
CSI0_TXP3  
O
O
I
CSI Differential Transmit Clock Output (negative)  
CSI Differential Transmit Clock Output (positive)  
CSI Differential Receive Input (negative)  
CSI Differential Receive Input (negative)  
CSI Differential Receive Input (negative)  
CSI Differential Receive Input (negative)  
CSI Differential Receive Input (positive)  
CSI Differential Receive Input (positive)  
CSI Differential Receive Input (positive)  
CSI Differential Receive Input (positive)  
CSI Differential Transmit Output (negative)  
CSI Differential Transmit Output (negative)  
CSI Differential Transmit Output (negative)  
CSI Differential Transmit Output (negative)  
CSI Differential Transmit Output (positive)  
CSI Differential Transmit Output (positive)  
CSI Differential Transmit Output (positive)  
CSI Differential Transmit Output (positive)  
AH13  
AH14  
AG18  
AF19  
AE18  
AD19  
AG19  
AF20  
AE19  
AD20  
AG12  
AF13  
AE12  
AD13  
AG13  
AF14  
AE13  
AD14  
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
(1) An external 500 Ω ±1% resistor must be connected between this pin and VSS, even when the pin is unused.  
表6-90. CSI1 Signal Descriptions  
SIGNAL NAME  
CSI1_RXCLKN  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
AH22  
I
I
CSI Differential Receive Clock Input (negative)  
CSI Differential Receive Clock Input (positive)  
CSI1_RXCLKP  
AH23  
CSI pin connected to external resistor for on-chip  
resistor calibration  
CSI1_RXRCALIB(1)  
A
AC21  
CSI1_TXCLKN  
CSI1_TXCLKP  
CSI1_RXN0  
CSI1_RXN1  
CSI1_RXN2  
CSI1_RXN3  
CSI1_RXP0  
CSI1_RXP1  
CSI1_RXP2  
CSI1_RXP3  
CSI1_TXN0  
CSI1_TXN1  
CSI1_TXN2  
CSI1_TXN3  
CSI1_TXP0  
CSI1_TXP1  
CSI1_TXP2  
O
O
I
CSI Differential Transmit Clock Output (negative)  
CSI Differential Transmit Clock Output (positive)  
CSI Differential Receive Input (negative)  
CSI Differential Receive Input (negative)  
CSI Differential Receive Input (negative)  
CSI Differential Receive Input (negative)  
CSI Differential Receive Input (positive)  
CSI Differential Receive Input (positive)  
CSI Differential Receive Input (positive)  
CSI Differential Receive Input (positive)  
CSI Differential Transmit Output (negative)  
CSI Differential Transmit Output (negative)  
CSI Differential Transmit Output (negative)  
CSI Differential Transmit Output (negative)  
CSI Differential Transmit Output (positive)  
CSI Differential Transmit Output (positive)  
CSI Differential Transmit Output (positive)  
AH16  
AH17  
AG21  
AF22  
AE21  
AD22  
AG22  
AF23  
AE22  
AD23  
AG15  
AF16  
AE15  
AD16  
AG16  
AF17  
AE16  
I
I
I
I
I
I
I
O
O
O
O
O
O
O
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TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
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表6-90. CSI1 Signal Descriptions (continued)  
SIGNAL NAME  
CSI1_TXP3  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
O
CSI Differential Transmit Output (positive)  
AD17  
(1) An external 500 Ω ±1% resistor must be connected between this pin and VSS, even when the pin is unused.  
6.3.21 MCASP  
6.3.21.1 MAIN Domain  
表6-91. MCASP0 Signal Descriptions  
SIGNAL NAME  
MCASP0_ACLKR  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
U24  
IO  
MCASP Receive Bit Clock  
MCASP0_ACLKX  
MCASP0_AFSR  
MCASP0_AFSX  
MCASP0_AXR0  
MCASP0_AXR1  
MCASP0_AXR2  
MCASP0_AXR3  
MCASP0_AXR4  
MCASP0_AXR5  
MCASP0_AXR6  
MCASP0_AXR7  
MCASP0_AXR8  
MCASP0_AXR9  
MCASP0_AXR10  
MCASP0_AXR11  
MCASP0_AXR12  
MCASP0_AXR13  
MCASP0_AXR14  
MCASP0_AXR15  
IO  
MCASP Transmit Bit Clock  
AB28  
AC25  
U27  
IO  
MCASP Receive Frame Sync  
IO  
MCASP Transmit Frame Sync  
IO  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
AC28  
Y26  
IO  
IO  
AB27  
T27  
IO  
IO  
U26  
IO  
AA28  
AD27  
T25  
IO  
IO  
IO  
W24  
AA25  
V25  
IO  
IO  
IO  
T24  
IO  
AB25  
T23  
IO  
IO  
U24  
IO  
AC25  
表6-92. MCASP1 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
AA28  
AA24  
AD27  
V28  
MCASP1_ACLKR  
MCASP1_ACLKX  
MCASP1_AFSR  
MCASP1_AFSX  
MCASP1_AXR0  
MCASP1_AXR1  
MCASP1_AXR2  
MCASP1_AXR3  
MCASP1_AXR4  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
MCASP Receive Bit Clock  
MCASP Transmit Bit Clock  
MCASP Receive Frame Sync  
MCASP Transmit Frame Sync  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
T28  
V27  
W27  
AD26  
U25  
表6-93. MCASP2 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
AB25  
Y27  
MCASP2_ACLKR  
MCASP2_ACLKX  
MCASP2_AFSR  
IO  
IO  
IO  
MCASP Receive Bit Clock  
MCASP Transmit Bit Clock  
MCASP Receive Frame Sync  
T23  
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表6-93. MCASP2 Signal Descriptions (continued)  
SIGNAL NAME  
MCASP2_AFSX  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
IO  
IO  
IO  
IO  
IO  
IO  
MCASP Transmit Frame Sync  
AA27  
AA26  
AC27  
W28  
R28  
MCASP2_AXR0  
MCASP2_AXR1  
MCASP2_AXR2  
MCASP2_AXR3  
MCASP2_AXR4  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
U24  
表6-94. MCASP3 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
AE27  
AE27  
AF26  
MCASP3_ACLKR  
MCASP3_ACLKX  
MCASP3_AFSR  
MCASP3_AFSX  
MCASP3_AXR0  
MCASP3_AXR1  
MCASP3_AXR2  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
MCASP Receive Bit Clock  
MCASP Transmit Bit Clock  
MCASP Receive Frame Sync  
MCASP Transmit Frame Sync  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
AF26  
AH27  
AG26  
AH26  
表6-95. MCASP4 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
T25  
MCASP4_ACLKR  
MCASP4_ACLKX  
MCASP4_AFSR  
MCASP4_AFSX  
MCASP4_AXR0  
MCASP4_AXR1  
MCASP4_AXR2  
MCASP4_AXR3  
MCASP4_AXR4  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
MCASP Receive Bit Clock  
MCASP Transmit Bit Clock  
AD28  
W24  
MCASP Receive Frame Sync  
MCASP Transmit Frame Sync  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASPI Serial Data (Input/Output)  
V26  
AD24  
U28  
AB26  
R27  
AA25  
6.3.22 DMTIMER  
6.3.22.1 MAIN Domain  
表6-96. DMTIMER Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
Timer Inputs and Outputs (Can be used with any MAIN  
domain timer instance)  
TIMER_IO0  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
AE25  
Timer Inputs and Outputs (Can be used with any MAIN  
domain timer instance)  
TIMER_IO1  
TIMER_IO2  
TIMER_IO3  
TIMER_IO4  
TIMER_IO5  
TIMER_IO6  
AG25  
R22  
R24  
P24  
M23  
P23  
Timer Inputs and Outputs (Can be used with any MAIN  
domain timer instance)  
Timer Inputs and Outputs (Can be used with any MAIN  
domain timer instance)  
Timer Inputs and Outputs (Can be used with any MAIN  
domain timer instance)  
Timer Inputs and Outputs (Can be used with any MAIN  
domain timer instance)  
Timer Inputs and Outputs (Can be used with any MAIN  
domain timer instance)  
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表6-96. DMTIMER Signal Descriptions (continued)  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
Timer Inputs and Outputs (Can be used with any MAIN  
domain timer instance)  
TIMER_IO7  
IO  
N24  
6.3.22.2 MCU Domain  
表6-97. MCU_DMTIMER Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
Timer Inputs and Outputs (Can be used with any MCU  
domain timer instance.)  
MCU_TIMER_IO0  
IO  
B25, C21  
Timer Inputs and Outputs (Can be used with any MCU  
domain timer instance.)  
MCU_TIMER_IO1  
MCU_TIMER_IO2  
MCU_TIMER_IO3  
MCU_TIMER_IO4  
MCU_TIMER_IO5  
MCU_TIMER_IO6  
MCU_TIMER_IO7  
MCU_TIMER_IO8  
MCU_TIMER_IO9  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
B26, F25  
E22  
Timer Inputs and Outputs (Can be used with any MCU  
domain timer instance.)  
Timer Inputs and Outputs (Can be used with any MCU  
domain timer instance.)  
E21  
Timer Inputs and Outputs (Can be used with any MCU  
domain timer instance.)  
D23  
Timer Inputs and Outputs (Can be used with any MCU  
domain timer instance.)  
C22  
Timer Inputs and Outputs (Can be used with any MCU  
domain timer instance.)  
F24, G27  
H26, J26  
B24  
Timer Inputs and Outputs (Can be used with any MCU  
domain timer instance.)  
Timer Inputs and Outputs (Can be used with any MCU  
domain timer instance.)  
Timer Inputs and Outputs (Can be used with any MCU  
domain timer instance.)  
D25  
6.3.23 CPTS  
6.3.23.1 MAIN Domain  
表6-98. CPTS0 Signal Descriptions  
SIGNAL NAME  
CPTS0_RFT_CLK  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
AB26  
AF26  
R24  
I
O
O
I
CPTS Reference Clock  
CPTS0_TS_COMP  
CPTS Time Stamp Counter Compare  
CPTS Time Stamp Counter Bit  
CPTS0_TS_SYNC  
CPTS0_HW1TSPUSH  
CPTS0_HW2TSPUSH  
CPTS Hardware Time Stamp Push 1  
CPTS Hardware Time Stamp Push 2  
AB26  
AD28  
I
6.3.23.2 MCU Domain  
表6-99. MCU_CPTS0 Signal Descriptions  
SIGNAL NAME  
MCU_CPTS0_RFT_CLK  
MCU_CPTS0_TS_COMP  
MCU_CPTS0_TS_SYNC  
MCU_CPTS0_HW1TSPUSH  
MCU_CPTS0_HW2TSPUSH  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
F27, K26  
H26  
I
O
O
I
CPTS Reference Clock  
CPTS Time Stamp Counter Compare  
CPTS Time Stamp Counter Bit  
F24  
CPTS Hardware Time Stamp Push 1  
CPTS Hardware Time Stamp Push 2  
E25  
I
F28  
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6.3.24 DSS  
6.3.24.1 MAIN Domain  
表6-100. DSS0 Signal Descriptions  
SIGNAL NAME  
DSS_FSYNC0  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
O
Video Output Frame Sync  
Video Output Frame Sync  
Video Output Frame Sync  
Video Output Frame Sync  
Video Output Data Enable  
Video Output External Pixel Clock Input  
Video Output Horizontal Sync  
Video Output Pixel Clock Output  
Video Output Vertical Sync  
Video Output Data 0  
V26, W25  
AC24, AD24  
AE28  
AF28  
DSS_FSYNC1  
O
O
O
O
I
DSS_FSYNC2  
DSS_FSYNC3  
VOUT0_DE  
AA28  
V26  
VOUT0_EXTPCLKIN  
VOUT0_HSYNC  
VOUT0_PCLK  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
U26  
Y25  
VOUT0_VSYNC  
VOUT0_DATA0  
VOUT0_DATA1  
VOUT0_DATA2  
VOUT0_DATA3  
VOUT0_DATA4  
VOUT0_DATA5  
VOUT0_DATA6  
VOUT0_DATA7  
VOUT0_DATA8  
VOUT0_DATA9  
VOUT0_DATA10  
VOUT0_DATA11  
VOUT0_DATA12  
VOUT0_DATA13  
VOUT0_DATA14  
VOUT0_DATA15  
VOUT0_DATA16  
VOUT0_DATA17  
VOUT0_DATA18  
VOUT0_DATA19  
VOUT0_DATA20  
VOUT0_DATA21  
VOUT0_DATA22  
VOUT0_DATA23  
VOUT0_VP0_DE  
VOUT0_VP0_HSYNC  
VOUT0_VP0_VSYNC  
VOUT0_VP2_DE  
VOUT0_VP2_HSYNC  
VOUT0_VP2_VSYNC  
AD27  
R28  
Video Output Data 1  
R27  
Video Output Data 2  
T27  
Video Output Data 3  
U28  
Video Output Data 4  
W28  
Video Output Data 5  
AC27  
AA26  
AA27  
Y27  
Video Output Data 6  
Video Output Data 7  
Video Output Data 8  
Video Output Data 9  
W27  
Video Output Data 10  
V27  
Video Output Data 11  
AB27  
Y26  
Video Output Data 12  
Video Output Data 13  
AC28  
U27  
Video Output Data 14  
Video Output Data 15  
AB28  
AD28  
T26  
Video Output Data 16  
Video Output Data 17  
Video Output Data 18  
R28, V23  
AB24, R27  
Y27, Y28  
AA23, W27  
T26, Y24  
AB26, W23  
AA28  
U26  
Video Output Data 19  
Video Output Data 20  
Video Output Data 21  
Video Output Data 22  
Video Output Data 23  
Alternative Output Data Enable  
Alternative Output Horizontal Sync  
Alternative Output Vertical Sync  
Alternative Output Data Enable  
Alternative Output Horizontal Sync  
Alternative Output Vertical Sync  
AD27  
AA28  
U26  
AD27  
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6.3.25 GPMC  
6.3.25.1 MAIN Domain  
表6-101. GPMC0 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
GPMC Address Valid (active low) or Address Latch  
Enable  
GPMC0_ADVn_ALE  
O
AB27  
GPMC0_CLK  
IO  
O
GPMC clock  
W25  
AD27  
GPMC0_CLKOUT  
GPMC0_DIR  
GPMC clock generated for external synchronization  
GPMC Data Bus Signal Direction Control  
O
R28, Y25  
GPMC Output Enable (active low) or Read Enable  
(active low)  
GPMC0_OEn_REn  
O
U26  
GPMC0_WEn  
GPMC0_WPn  
O
O
GPMC Write Enable (active low)  
AD24  
AB27  
GPMC Flash Write Protect (active low)  
GPMC Address 0 Output. Only used to effectively  
address 8-bit data non-multiplexed memories  
GPMC0_A0  
GPMC0_A1  
GPMC0_A2  
GPMC0_A3  
GPMC0_A4  
GPMC0_A5  
GPMC0_A6  
GPMC0_A7  
GPMC0_A8  
GPMC0_A9  
GPMC0_A10  
GPMC0_A11  
GPMC0_A12  
GPMC0_A13  
GPMC0_A14  
GPMC0_A15  
GPMC0_A16  
GPMC0_A17  
GPMC0_A18  
GPMC0_A19  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
T25  
W24  
AA25  
V25  
GPMC Address 1 Output in A/D non-multiplexed mode  
and Address 17 in A/D multiplexed mode  
GPMC Address 2 Output in A/D non-multiplexed mode  
and Address 18 in A/D multiplexed mode  
GPMC Address 3 Output in A/D non-multiplexed mode  
and Address 19 in A/D multiplexed mode  
GPMC Address 4 Output in A/D non-multiplexed mode  
and Address 20 in A/D multiplexed mode  
T24  
GPMC Address 5 Output in A/D non-multiplexed mode  
and Address 21 in A/D multiplexed mode  
AB25  
T23  
GPMC Address 6 Output in A/D non-multiplexed mode  
and Address 22 in A/D multiplexed mode  
GPMC Address 7 Output in A/D non-multiplexed mode  
and Address 23 in A/D multiplexed mode  
U24  
GPMC Address 8 Output in A/D non-multiplexed mode  
and Address 24 in A/D multiplexed mode  
AC25  
AD26  
U25  
GPMC Address 9 Output in A/D non-multiplexed mode  
and Address 25 in A/D multiplexed mode  
GPMC Address 10 Output in A/D non-multiplexed  
mode and Address 26 in A/D multiplexed mode  
GPMC Address 11 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
AA24  
V28  
GPMC Address 12 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
GPMC Address 13 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
T28  
GPMC Address 14 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
T25, V23  
AB24  
Y28  
GPMC Address 15 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
GPMC Address 16 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
GPMC Address 17 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
AA23  
Y24  
GPMC Address 18 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
GPMC Address 19 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
W23  
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表6-101. GPMC0 Signal Descriptions (continued)  
SIGNAL NAME  
GPMC0_A20  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
GPMC Address 20 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
OZ  
AD25  
AF28  
AE28  
AC24  
W25  
GPMC Address 21 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
GPMC0_A21  
GPMC0_A22  
GPMC0_A23  
GPMC0_A24  
OZ  
OZ  
OZ  
OZ  
GPMC Address 22 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
GPMC Address 23 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
GPMC Address 24 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
GPMC Data 0 Input/Output in A/D non-multiplexed  
mode and additionally Address 1 Output in A/D  
multiplexed mode  
GPMC0_AD0  
GPMC0_AD1  
GPMC0_AD2  
GPMC0_AD3  
GPMC0_AD4  
GPMC0_AD5  
GPMC0_AD6  
GPMC0_AD7  
GPMC0_AD8  
GPMC0_AD9  
GPMC0_AD10  
GPMC0_AD11  
GPMC0_AD12  
GPMC0_AD13  
GPMC0_AD14  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
AB28  
U27  
GPMC Data 1 Input/Output in A/D non-multiplexed  
mode and additionally Address 2 Output in A/D  
multiplexed mode  
GPMC Data 2 Input/Output in A/D non-multiplexed  
mode and additionally Address 3 Output in A/D  
multiplexed mode  
AC28  
Y26  
GPMC Data 3 Input/Output in A/D non-multiplexed  
mode and additionally Address 4 Output in A/D  
multiplexed mode  
GPMC Data 4 Input/Output in A/D non-multiplexed  
mode and additionally Address 5 Output in A/D  
multiplexed mode  
T26  
GPMC Data 5 Input/Output in A/D non-multiplexed  
mode and additionally Address 6 Output in A/D  
multiplexed mode  
AB26  
AD28  
V26  
GPMC Data 6 Input/Output in A/D non-multiplexed  
mode and additionally Address 7 Output in A/D  
multiplexed mode  
GPMC Data 7 Input/Output in A/D non-multiplexed  
mode and additionally Address 8 Output in A/D  
multiplexed mode  
GPMC Data 8 Input/Output in A/D non-multiplexed  
mode and additionally Address 9 Output in A/D  
multiplexed mode  
V27  
GPMC Data 9 Input/Output in A/D non-multiplexed  
mode and additionally Address 10 Output in A/D  
multiplexed mode  
W27  
Y27  
GPMC Data 10 Input/Output in A/D non-multiplexed  
mode and additionally Address 11 Output in A/D  
multiplexed mode  
GPMC Data 11 Input/Output in A/D non-multiplexed  
mode and additionally Address 12 Output in A/D  
multiplexed mode  
AA27  
AA26  
AC27  
W28  
GPMC Data 12 Input/Output in A/D non-multiplexed  
mode and additionally Address 13 Output in A/D  
multiplexed mode  
GPMC Data 13 Input/Output in A/D non-multiplexed  
mode and additionally Address 14 Output in A/D  
multiplexed mode  
GPMC Data 14 Input/Output in A/D non-multiplexed  
mode and additionally Address 15 Output in A/D  
multiplexed mode  
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表6-101. GPMC0 Signal Descriptions (continued)  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
GPMC Data 15 Input/Output in A/D non-multiplexed  
mode and additionally Address 16 Output in A/D  
multiplexed mode  
GPMC0_AD15  
IO  
U28  
GPMC Lower-Byte Enable (active low) or Command  
Latch Enable  
GPMC0_BE0n_CLE  
O
R27  
GPMC0_BE1n  
GPMC0_CSn0  
GPMC0_CSn1  
GPMC0_CSn2  
GPMC0_CSn3  
GPMC0_WAIT0  
GPMC0_WAIT1  
GPMC0_WAIT2  
GPMC0_WAIT3  
O
O
O
O
O
I
GPMC Upper-Byte Enable (active low)  
GPMC Chip Select 0 (active low)  
GPMC Chip Select 1 (active low)  
GPMC Chip Select 2 (active low)  
GPMC Chip Select 3 (active low)  
GPMC External Indication of Wait  
GPMC External Indication of Wait  
GPMC External Indication of Wait  
GPMC External Indication of Wait  
T27  
AA28  
Y25  
T25, V23  
AC24  
R28  
I
AB24  
AE28  
T28  
I
I
6.3.26 MMC  
6.3.26.1 MAIN Domain  
表6-102. MMC0 Signal Descriptions  
SIGNAL NAME  
MMC0_CALPAD(1)  
MMC0_CLK  
PIN TYPE  
DESCRIPTION  
MMC/SD/SDIO Calibration Resistor  
MMC/SD/SDIO Clock  
MMC/SD/SDIO Command  
MMC Data Strobe  
ALZ PIN  
AF1  
A
O
AC6  
AF2  
MMC0_CMD(2)  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
MMC0_DS  
AE3  
AF4  
MMC0_DAT0(2)  
MMC0_DAT1(2)  
MMC0_DAT2(2)  
MMC0_DAT3(2)  
MMC0_DAT4(2)  
MMC0_DAT5(2)  
MMC0_DAT6(2)  
MMC0_DAT7(2)  
MMC/SD/SDIO Data  
MMC/SD/SDIO Data  
AD3  
AD4  
AF3  
MMC/SD/SDIO Data  
MMC/SD/SDIO Data  
MMC/SD/SDIO Data  
AE2  
AG3  
AE1  
AG1  
MMC/SD/SDIO Data  
MMC/SD/SDIO Data  
MMC/SD/SDIO Data  
(1) An external 10 kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.  
(2) An external pull-up of 10 kΩ ~ 50 kΩ ±1% resistor, as specified in the specification, must be connected to this ball to ensure proper  
operation.  
表6-103. MMC1 Signal Descriptions  
SIGNAL NAME  
MMC1_CLK(1)  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
P23  
IO  
IO  
I
MMC/SD/SDIO Clock  
MMC1_CMD  
MMC1_SDCD(2)  
MMC1_SDWP  
MMC1_DAT0  
MMC1_DAT1  
MMC1_DAT2  
MMC1_DAT3  
MMC/SD/SDIO Command  
SD Card Detect  
N24  
AE25  
AG25  
M23  
I
SD Write Protect  
IO  
IO  
IO  
IO  
MMC/SD/SDIO Data  
MMC/SD/SDIO Data  
MMC/SD/SDIO Data  
MMC/SD/SDIO Data  
P24  
R24  
R22  
(1) For MMC1_CLK signal to work properly, the RXACTIVE bit of the CTRLMMR_PADCONFIG171 register should be set to 0x1 because  
of retiming purposes.  
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(2) For ROM boot from MMC1 interface to work properly, the MMC1_SDCD pin should be pulled low externally with a resistor to indicated  
an SD Card/Memory device is present.  
6.3.27 OSPI  
6.3.27.1 MCU Domain  
表6-104. MCU_OSPI0 Signal Descriptions  
SIGNAL NAME  
MCU_OSPI0_CLK  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
D19  
O
I
OSPI Clock  
MCU_OSPI0_DQS  
MCU_OSPI0_ECC_FAIL  
MCU_OSPI0_LBCLKO  
MCU_OSPI0_CSn0  
MCU_OSPI0_CSn1  
MCU_OSPI0_CSn2  
MCU_OSPI0_CSn3  
MCU_OSPI0_D0  
OSPI Data Strobe (DQS) or Loopback Clock Input  
OSPI ECC Status  
E18  
I
B19, F17  
E20  
IO  
O
OSPI Loopback Clock Output  
OSPI Chip Select 0 (active low)  
OSPI Chip Select 1 (active low)  
OSPI Chip Select 2 (active low)  
OSPI Chip Select 3 (active low)  
OSPI Data 0  
F15  
O
G17  
O
B20, F14  
B19, F17  
C19  
O
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
O
MCU_OSPI0_D1  
OSPI Data 1  
F16  
MCU_OSPI0_D2  
OSPI Data 2  
G15  
MCU_OSPI0_D3  
OSPI Data 3  
F18  
MCU_OSPI0_D4  
OSPI Data 4  
E19  
MCU_OSPI0_D5  
OSPI Data 5  
G19  
MCU_OSPI0_D6  
OSPI Data 6  
F19  
MCU_OSPI0_D7  
OSPI Data 7  
F20  
MCU_OSPI0_RESET_OUT0  
MCU_OSPI0_RESET_OUT1  
OSPI Reset  
B20, F14  
C21, F17  
O
OSPI Reset  
表6-105. MCU_OSPI1 Signal Descriptions  
SIGNAL NAME  
MCU_OSPI1_CLK  
MCU_OSPI1_DQS  
MCU_OSPI1_LBCLKO  
MCU_OSPI1_CSn0  
MCU_OSPI1_CSn1  
MCU_OSPI1_D0  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
A19  
O
I
OSPI Clock  
OSPI Data Strobe (DQS) or Loopback Clock Input  
OSPI Loopback Clock Output  
OSPI Chip Select 0 (active low)  
OSPI Chip Select 1 (active low)  
OSPI Data 0  
B19  
IO  
O
B20  
D20  
O
C21  
IO  
IO  
IO  
IO  
D21  
MCU_OSPI1_D1  
OSPI Data 1  
G20  
C20  
MCU_OSPI1_D2  
OSPI Data 2  
MCU_OSPI1_D3  
OSPI Data 3  
A20  
6.3.28 Hyperbus  
6.3.28.1 MCU Domain  
表6-106. MCU_HYPERBUS0 Signal Descriptions  
SIGNAL NAME  
MCU_HYPERBUS0_CK  
MCU_HYPERBUS0_CKn  
MCU_HYPERBUS0_INTn  
MCU_HYPERBUS0_RESETn  
PIN TYPE  
DESCRIPTION  
Hyperbus Differential Clock (positive)  
Hyperbus Differential Clock (negative)  
Hyperbus Interrupt (active low)  
ALZ PIN  
D19  
O
O
I
E20  
B19, F17  
G17  
O
Hyperbus Reset (active low) Output  
Hyperbus Reset Status Indicator (active low) from  
Hyperbus Memory  
MCU_HYPERBUS0_RESETOn  
I
B20, F14  
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表6-106. MCU_HYPERBUS0 Signal Descriptions (continued)  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
Hyperbus Read-Write Data Strobe  
Hyperbus Write Protect (Not in use)  
Hyperbus Chip Select 0  
Hyperbus Chip Select 1  
Hyperbus Data 0  
ALZ PIN  
E18  
MCU_HYPERBUS0_RWDS  
MCU_HYPERBUS0_WPn  
MCU_HYPERBUS0_CSn0  
MCU_HYPERBUS0_CSn1  
MCU_HYPERBUS0_DQ0  
MCU_HYPERBUS0_DQ1  
MCU_HYPERBUS0_DQ2  
MCU_HYPERBUS0_DQ3  
MCU_HYPERBUS0_DQ4  
MCU_HYPERBUS0_DQ5  
MCU_HYPERBUS0_DQ6  
MCU_HYPERBUS0_DQ7  
IO  
O
C21, F14, F17  
F15  
O
O
C21, F14  
C19  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
Hyperbus Data 1  
F16  
Hyperbus Data 2  
G15  
Hyperbus Data 3  
F18  
Hyperbus Data 4  
E19  
Hyperbus Data 5  
G19  
Hyperbus Data 6  
F19  
Hyperbus Data 7  
F20  
6.3.29 Emulation and Debug  
6.3.29.1 MAIN Domain  
表6-107. JTAG Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
A27  
EMU0  
EMU1  
TCK  
IO  
Emulation Control 0  
Emulation Control 1  
IO  
C26  
I
JTAG Test Clock Input  
JTAG Test Data Input  
JTAG Test Data Output  
JTAG Test Mode Select Input  
JTAG Reset  
A25  
TDI  
I
AG28  
AE26  
AG27  
B28  
TDO  
OZ  
TMS  
I
I
TRSTn  
表6-108. Trace Signal Descriptions  
SIGNAL NAME  
TRC_CLK  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
AD28, W25  
AC24, V26  
AD24, AE28  
AB26, AF28  
AD25, T26  
R28, W23  
Y27  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Trace Clock  
TRC_CTL  
Trace Control  
Trace Data 0  
Trace Data 1  
Trace Data 2  
Trace Data 3  
Trace Data 4  
Trace Data 5  
Trace Data 6  
Trace Data 7  
Trace Data 8  
Trace Data 9  
Trace Data 10  
Trace Data 11  
Trace Data 12  
Trace Data 13  
Trace Data 14  
Trace Data 15  
TRC_DATA0  
TRC_DATA1  
TRC_DATA2  
TRC_DATA3  
TRC_DATA4  
TRC_DATA5  
TRC_DATA6  
TRC_DATA7  
TRC_DATA8  
TRC_DATA9  
TRC_DATA10  
TRC_DATA11  
TRC_DATA12  
TRC_DATA13  
TRC_DATA14  
TRC_DATA15  
R27  
W27  
T27  
V27  
AA27  
AB27  
W28  
Y26  
AC27  
AC28  
AA26  
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English Data Sheet: SPRSP62  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1  
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表6-108. Trace Signal Descriptions (continued)  
SIGNAL NAME  
TRC_DATA16  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
O
O
O
O
O
O
O
O
O
O
Trace Data 16  
Trace Data 17  
Trace Data 18  
Trace Data 19  
Trace Data 20  
Trace Data 21  
Trace Data 22  
Trace Data 23  
Trace Data 24  
Trace Data 25  
U28  
Y25  
TRC_DATA17  
TRC_DATA18  
TRC_DATA19  
TRC_DATA20  
TRC_DATA21  
TRC_DATA22  
TRC_DATA23  
TRC_DATA24  
TRC_DATA25  
U26  
AA28  
AD27  
Y24  
AA23  
Y28  
AB24  
V23  
6.3.30 System and Miscellaneous  
6.3.30.1 Boot Mode configuration  
表6-109. Sysboot Signal Descriptions  
SIGNAL NAME  
BOOTMODE00  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
C19  
F16  
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Bootmode Pin 0  
BOOTMODE01  
Bootmode Pin 1  
BOOTMODE02  
Bootmode Pin 2  
E19  
G19  
G27  
J26  
BOOTMODE03  
Bootmode Pin 3  
BOOTMODE04  
Bootmode Pin 4  
BOOTMODE05  
Bootmode Pin 5  
BOOTMODE06  
Bootmode Pin 6  
G25  
J27  
BOOTMODE07  
Bootmode Pin 7  
MCU_BOOTMODE00  
MCU_BOOTMODE01  
MCU_BOOTMODE02  
MCU_BOOTMODE03  
MCU_BOOTMODE04  
MCU_BOOTMODE05  
MCU_BOOTMODE06  
MCU_BOOTMODE07  
MCU_BOOTMODE08  
MCU_BOOTMODE09  
MCU Bootmode Pin 0  
MCU Bootmode Pin 1  
MCU Bootmode Pin 2  
MCU Bootmode Pin 3  
MCU Bootmode Pin 4  
MCU Bootmode Pin 5  
MCU Bootmode Pin 6  
MCU Bootmode Pin 7  
MCU Bootmode Pin 8  
MCU Bootmode Pin 9  
B27  
D24  
B25  
D26  
E24  
C28  
B24  
D25  
C25  
C24  
6.3.30.2 Clock  
表6-110. Clock0 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
Low Frequency (32.768 KHz) Oscillator Input  
High Frequency Oscillator Input  
ALZ PIN  
J27  
WKUP_LF_CLKIN  
WKUP_OSC0_XI  
WKUP_OSC0_XO  
I
I
H28  
O
High Frequency Oscillator Output  
J28  
表6-111. Clock1 Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
OSC1_XI  
I
High Frequency Oscillator Input  
M28  
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表6-111. Clock1 Signal Descriptions (continued)  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
OSC1_XO  
O
High Frequency Oscillator Output  
L28  
6.3.30.3 System  
表6-112. MCU System Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
F25  
Reference clock output for Ethernet PHYs (50MHz or  
25MHz)  
MCU_CLKOUT0  
OZ  
I
MCU_EXT_REFCLK0  
MCU_OBSCLK0  
External system clock input  
F27, K26  
C26, F25  
Observation clock output for test and debug purposes  
only  
O
MCU_PORz  
I
O
I
MCU Domain Cold Reset  
G23  
A23  
A26  
J23  
MCU_RESETSTATz  
MCU_RESETz  
MCU Domain Warm Reset status output  
MCU Domain Warm Reset  
MCU_SAFETY_ERRORn  
IO  
Error signal output from MCU Domain ESM  
MCU Domain system clock output for test and debug  
purposes only  
MCU_SYSCLKOUT0  
O
F27  
表6-113. System Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
External clock routed to ATL or McASP as one of the  
selectable input clock sources, or as a output clock  
output for ATL or McASP  
AUDIO_EXT_REFCLK0  
IO  
AD24  
External clock routed to ATL or McASP as one of the  
selectable input clock sources, or as a output clock  
output for ATL or McASP  
AUDIO_EXT_REFCLK1  
EXTINTn  
IO  
I
Y25  
External Interrupt  
AG24  
External clock input to Main Domain, routed to Timer  
clock muxes as one of the selectable input clock  
sources for Timer/WDT modules, or as reference clock  
to MAIN_PLL2 (PER1 PLL)  
EXT_REFCLK1  
I
AD28  
GPMC functional clock output selected through a mux  
logic  
GPMC0_FCLK_MUX  
OBSCLK0  
O
O
O
AD27  
AG25  
Y26  
Observation clock output for test and debug purposes  
only  
Observation clock output for test and debug purposes  
only  
OBSCLK1  
PMIC_POWER_EN1  
PMIC_WAKE0n  
PMIC_WAKE1n  
PORz  
O
OD  
O
I
Power enable output for MAIN Domain supplies  
PMIC WakeUp  
G26  
AD24  
K26  
PMIC WakeUp  
SoC PORz Reset Signal  
K23  
RESETSTATz  
RESET_REQz  
SOC_SAFETY_ERRORn  
SYNC0_OUT  
O
I
Main Domain Warm Reset status output  
Main Domain external Warm Reset request input  
Error signal output from Main Domain ESM  
CPTS Time Stamp Generator Bit 0  
CPTS Time Stamp Generator Bit 1  
CPTS Time Stamp Generator Bit 2  
CPTS Time Stamp Generator Bit 3  
AF27  
A24  
IO  
O
O
O
O
AF25  
AB26  
AD28  
T28  
SYNC1_OUT  
SYNC2_OUT  
SYNC3_OUT  
Y27  
SYSCLK0 output from Main PLL controller (divided by  
6) for test and debug purposes only  
SYSCLKOUT0  
O
AE25  
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6.3.30.4 EFUSE  
表6-114. EFUSE Signal Descriptions  
SIGNAL NAME  
VPP_CORE  
PIN TYPE  
PWR  
PWR  
DESCRIPTION  
ALZ PIN  
Programming Voltage for MAIN Domain Efuses  
Programming Voltage for MCU Domain Efuses  
V22  
H22  
VPP_MCU  
6.3.30.5 VMON  
表6-115. VMON POK Signal Descriptions  
SIGNAL NAME  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
Voltage Monitor, fixed 0.45V (+/-3%) threshold. Use  
with external precision voltage divider to monitor a  
higher voltage rail such as the PMIC input supply.  
VMON1_ER_VSYS  
A
H23  
VMON2_IR_VCPU  
A
A
Must be externally connected directly to VDD_CPU  
M18  
L22  
General purpose voltage monitor for external supplies,  
1.8V threshold. With internal resistor divider.  
VMON3_IR_VEXT1P8  
General purpose voltage monitor for external supplies,  
1.8V threshold. With internal resistor divider.  
VMON4_IR_VEXT1P8  
VMON5_IR_VEXT3P3  
VMON6_IR_VEXT0P8  
A
A
A
N19  
N20  
L18  
General purpose voltage monitor for external supplies,  
3.3V threshold. With internal resistor divider.  
General purpose voltage monitor for external supplies,  
0.8V threshold. With internal resistor divider.  
6.3.31 Power  
表6-116. Power Supply Signal Descriptions  
SIGNAL NAME  
CAP_VDDS0(1)  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
CAP  
External Capacitor Connection  
T21  
CAP_VDDS0_MCU(1)  
CAP_VDDS1_MCU(1)  
CAP_VDDS2(1)  
CAP  
External Capacitor Connection  
External Capacitor Connection  
External Capacitor Connection  
External Capacitor Connection  
External Capacitor Connection  
Core RAM Supply  
J20  
CAP  
G16  
P21  
CAP  
CAP_VDDS2_MCU(1)  
CAP_VDDS5(1)  
CAP  
H17  
CAP  
M22  
VDDAR_CORE  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
N17, V11, V16, Y20  
H9, K14, P11, P14, V13  
K17, K19  
AB14  
VDDAR_CPU  
CPU RAM Supply  
VDDAR_MCU  
MCU RAM Supply  
VDDA_0P8_DSITX  
VDDA_0P8_DSITX_C  
VDDA_0P8_USB  
Analog Supply for DSITX  
DSITX Clock Supply  
AB15  
USB 0.8V Supply  
AB8  
VDDA_0P8_CSIRX0_1  
VDDA_0P8_DLL_MMC0  
VDDA_0P8_PLL_DDR0  
VDDA_0P8_PLL_DDR1  
VDDA_0P8_SERDES0_1  
VDDA_0P8_SERDES_C0_1  
VDDA_1P8_DSITX  
VDDA_1P8_USB  
Analog Supply for CSIRX  
MMC DLL Analog Supply  
DDR de-skew PLL Analog Supply  
DDR de-skew PLL Analog Supply  
SERDES 0.8V Supply  
AB17, AB18  
W7  
P10  
J14  
AB10, AB11  
AA10, AA11  
AA14, AA15  
AB7  
SERDES 0.8V Clock Supply  
Analog Supply for DSITX  
USB 1.8V Supply  
VDDA_1P8_CSIRX0_1  
VDDA_1P8_SERDES0_1  
VDDA_1P8_SERDES2_4  
Analog Supply for CSIRX  
SERDES 1.8V Supply  
AA17, AA19  
AA12  
SERDES 1.8V Supply  
AB13  
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表6-116. Power Supply Signal Descriptions (continued)  
SIGNAL NAME  
PIN TYPE  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
DESCRIPTION  
ALZ PIN  
AB9  
VDDA_3P3_USB  
VDDA_ADC0  
USB 3.3V Supply  
ADC0 Analog Supply  
J21  
VDDA_ADC1  
ADC1 Analog Supply  
K21  
VDDA_MCU_PLLGRP0  
VDDA_MCU_TEMP  
VDDA_OSC1  
Analog Supply for MCU PLL Group 0  
Analog Supply for MCU temperature sensor  
HFOSC1 Supply  
K22  
J17  
L21  
VDDA_PLLGRP0  
VDDA_PLLGRP1  
VDDA_PLLGRP2  
VDDA_PLLGRP5  
VDDA_PLLGRP6  
VDDA_PLLGRP7  
VDDA_PLLGRP8  
VDDA_PLLGRP9  
VDDA_PLLGRP10  
VDDA_PLLGRP12  
VDDA_PLLGRP13  
VDDA_POR_WKUP  
VDDA_TEMP0  
VDDA_TEMP1  
VDDA_TEMP2  
VDDA_TEMP3  
VDDA_TEMP4  
VDDA_WKUP  
Analog Supply for MAIN PLL Group 0  
Analog Supply for MAIN PLL Group 1  
Analog Supply for MAIN PLL Group 2  
Analog Supply for MAIN PLL Group 5  
Analog Supply for MAIN PLL Group 6  
Analog Supply for MAIN PLL Group 7  
Analog Supply for MAIN PLL Group 8  
Analog Supply for MAIN PLL Group 9  
Analog Supply for MAIN PLL Group 10  
Analog Supply for MAIN PLL Group 12  
Analog Supply for MAIN PLL Group 13  
WKUP domain Analog Supply  
Analog Supply for temperature sensor 0  
Analog Supply for temperature sensor 1  
Analog Supply for temperature sensor 2  
Analog Supply for temperature sensor 3  
Analog Supply for temperature sensor 4  
Oscillator Supply for WKUP domain  
IO Power Supply  
U18  
V19  
Y11  
N14  
R12  
R11  
K12  
T18  
Y16  
Y18  
V12  
L20  
U19  
K10  
T16  
U10  
Y14  
J22  
VDDSHV0  
R21, U21, U22  
H19, H20  
H16, J16  
M20, R20  
G18, H18  
M21, N22  
VDDSHV0_MCU  
VDDSHV1_MCU  
VDDSHV2  
IO Power Supply  
IO Power Supply  
IO Power Supply  
VDDSHV2_MCU  
VDDSHV5  
IO Power Supply  
IO Power Supply  
A1, A18, AA1, G10, G12,  
G14, G6, H11, H13, H15,  
J6, L6, N6, N9, P7, P8,  
R6, U9  
VDDS_DDR  
PWR  
DDR PHY IO Supply  
VDDS_DDR_C0  
VDDS_DDR_C1  
VDDS_MMC0  
PWR  
PWR  
PWR  
IO Power Supply for DDR Clock  
IO Power Supply for DDR Clock  
MMC0 PHY IO Supply  
R9  
J12  
Y7, Y8  
AA21, AB20, J13, J15,  
M16, M19, N10, P18, R17,  
R19, T10, T20, U15, U17,  
U8, V14, V18, V20, V7,  
V9, W10, W13, W15,  
W17, W19, W21, W8,  
Y12, Y22, Y9  
VDD_CORE  
PWR  
MAIN domain core Supply  
G8, H7, J8, K11, K13, K7,  
K9, L8, M14, M7, M9, N11,  
N15, P16, R13, R15, T12,  
T14, U11, U13  
VDD_CPU  
VDD_MCU  
PWR  
PWR  
CPU core Supply  
MCU core Supply  
K16, K18, L15, L17, L19  
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表6-116. Power Supply Signal Descriptions (continued)  
SIGNAL NAME  
VDD_MCU_WAKE1  
VDD_WAKE0  
PIN TYPE  
DESCRIPTION  
ALZ PIN  
PWR  
Core Supply for MCU daisy chain  
J19  
PWR  
Core Supply for MAIN domain daisy chain  
P20  
A14, A5, AA13, AA16,  
AA18, AA20, AA22, AA3,  
AA5, AA7, AA9, AB12,  
AB16, AB19, AB2, AB21,  
AB23, AB4, AB6, AC11,  
AC22, AC26, AC3, AC5,  
AC7, AC8, AD15, AD18,  
AD21, AD6, AD9, AE10,  
AE14, AE17, AE20, AE23,  
AE4, AE7, AF12, AF15,  
AF18, AF21, AF24, AF5,  
AF8, AG10, AG14, AG17,  
AG20, AG23, AG4, AG7,  
AH1, AH12, AH15, AH18,  
AH21, AH24, AH3, AH6,  
AH9, B11, B13, B15, B17,  
B2, B23, B4, B6, B8, C1,  
C12, C14, C16, C18, C3,  
C5, C7, D11, D13, D15,  
D17, D2, D4, D6, D8, E1,  
E12, E14, E16, E26, E3,  
E5, E7, F2, F4, F6, G13,  
G28, G3, G5, G7, G9,  
VSS  
GND  
Ground  
H10, H12, H14, H2, H21,  
H4, H6, H8, J1, J11, J18,  
J24, J3, J5, J7, J9, K15,  
K2, K20, K27, K4, K6, K8,  
L14, L16, L3, L5, L7, L9,  
M15, M17, M2, M25, M4,  
M6, M8, N1, N16, N18,  
N21, N23, N3, N7, P15,  
P17, P19, P22, P6, P9,  
R10, R14, R16, R18, R23,  
R26, R7, T11, T13, T15,  
T17, T19, T2, T22, T4, T6,  
T9, U12, U14, U16, U20,  
U23, U3, U5, U7, V10,  
V15, V17, V2, V21, V24,  
V4, V6, V8, W1, W11,  
W12, W14, W16, W18,  
W20, W22, W26, W3, W6,  
W9, Y10, Y13, Y15, Y17,  
Y19, Y2, Y21, Y23, Y4, Y6  
(1) This pin must always be connected via a 1-μF ±10% capacitor to VSS.  
6.4 Connection for Unused Pins  
This section describes connectivity requirements for package balls that have specific connectivity requirements  
and unused package balls.  
备注  
All power balls must be supplied with the voltages specified in the Recommended Operating  
Conditions section, unless otherwise specified in Signal Descriptions.  
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备注  
For additional clarification, "left unconnected" or "no connect" (NC) means no signal traces can be  
connected to these device ball number.  
表6-117 shows the connectivity requirements for specific signals by ball name and ball number.  
表6-117. Connectivity Requirements  
BALL  
NUMBER  
BALL NAME  
WKUP_OSC0_XI  
CONNECTION REQUIREMENT  
H28  
M28  
B28  
L25  
K25  
M24  
L24  
L27  
K24  
M27  
M26  
P25  
R25  
P28  
P27  
N25  
P26  
N26  
N27  
G1  
OSC1_XI  
TRSTN  
MCU_ADC0_AIN0  
MCU_ADC0_AIN1  
MCU_ADC0_AIN2  
MCU_ADC0_AIN3  
MCU_ADC0_AIN4  
MCU_ADC0_AIN5  
MCU_ADC0_AIN6  
MCU_ADC0_AIN7  
MCU_ADC1_AIN0  
MCU_ADC1_AIN1  
MCU_ADC1_AIN2  
MCU_ADC1_AIN3  
MCU_ADC1_AIN4  
MCU_ADC1_AIN5  
MCU_ADC1_AIN6  
MCU_ADC1_AIN7  
DDR0_DQS0P  
Each of these balls must be connected to VSS through a separate external pull  
resistor to ensure these balls are held to a valid logic low level, if unused.  
L1  
DDR0_DQS1P  
V1  
DDR0_DQS2P  
AB1  
A16  
A13  
A6  
DDR0_DQS3P  
DDR1_DQS0P  
DDR1_DQS1P  
DDR1_DQS2P  
A3  
DDR1_DQS3P  
T8  
DDR0_RET  
J10  
H23  
L18  
L22  
M18  
N19  
N20  
DDR1_RET  
VMON1_ER_VSYS  
VMON6_IR_VEXT0P8  
VMON3_IR_VEXT1P8  
VMON2_IR_VCPU  
VMON4_IR_VEXT1P8  
VMON5_IR_VEXT3P3  
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表6-117. Connectivity Requirements (continued)  
BALL  
NUMBER  
BALL NAME  
SERDES0_REXT  
CONNECTION REQUIREMENT  
AC10  
AC18  
AC21  
R8  
CSI0_RXRCALIB  
CSI1_RXRCALIB  
DDR0_CAL0  
DDR1_CAL0  
DSI0_TXRCALIB  
DSI1_TXRCALIB  
USB0_RCALIB  
MCU_RESETZ  
MCU_PORZ  
PORZ  
Each of these balls must be connected to VSS through a separate external pull  
resistor to ensure these balls are held to a valid logic low level, if unused. Refer to  
Signal Descriptions footnote for appropriate value of pull-resistor for each signal.  
E8  
AC13  
AC15  
AA6  
A26  
G23  
K23  
A24  
A25  
AG27  
G24  
H24  
H27  
J25  
RESET_REQZ  
TCK  
TMS  
MCU_I2C0_SCL  
WKUP_I2C0_SCL  
WKUP_I2C0_SDA  
MCU_I2C0_SDA  
I2C0_SDA  
AE24  
AH25  
AG24  
AG28  
AE26  
A27  
C26  
H1  
I2C0_SCL  
Each of these balls must be connected to the corresponding power supply  
through a separate external pull resistor to ensure these balls are held to a valid  
logic high level, if unused.  
EXTINTN  
TDI  
TDO  
EMU0  
EMU1  
DDR0_DQS0N  
DDR0_DQS1N  
DDR0_DQS2N  
DDR0_DQS3N  
DDR1_DQS0N  
DDR1_DQS1N  
DDR1_DQS2N  
DDR1_DQS3N  
VPP_MCU  
M1  
U1  
AC1  
A15  
A12  
A7  
A2  
H22  
V22  
AF1  
VPP_CORE  
MMC0_CALPAD  
Each of these balls must be left unconnected, if unused.  
表6-118 shows the specific connection requirements for the RESERVED ball numbers on the device.  
备注  
For additional clarification, "left unconnected" or "no connect" (NC) means no signal traces can be  
connected to these device ball numbers.  
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ZHCSRF7 –DECEMBER 2022  
表6-118. Reserved Balls Specific Connection Requirements  
BALL NUMBERS  
CONNECTION REQUIREMENTS  
AB22 / AC12 / AC14 / AC16 / AC17 / AC19 / AC20 / AC23 / AD10 / AD11 / AD12 /  
AD5 / AE11 / F13 / G11 / G21 / H25 / K28 / L23 / L26 / N28 / N8 / T7  
RESERVED.  
These balls must be left unconnected.  
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7 Specifications  
7.1 Absolute Maximum Ratings  
over operating free-air temperature range (unless otherwise noted) (1) (2)  
PARAMETER  
MIN  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
MAX  
UNIT  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VDD_CORE  
MAIN domain core supply  
MCUSS core supply  
1.05  
1.05  
1.05  
1.05  
1.05  
1.05  
1.05  
1.05  
1.05  
1.05  
1.05  
1.05  
1.05  
1.05  
1.05  
1.05  
1.05  
2.2  
VDD_MCU  
VDD_CPU  
CPU core supply  
VDD_MCU_WAKE1  
VDD_WAKE0  
Core supply for MCU WAKE function  
Core supply for MAIN domain WAKE function  
MMC0 DLL analog supply  
MAIN domain RAM supply  
MCUSS RAM supply  
VDDA_0P8_DLL_MMC0  
VDDAR_CORE  
VDDAR_MCU  
VDDAR_CPU  
CPU RAM supply  
VDDA_0P8_DSITX  
VDDA_0P8_DSITX_C  
VDDA_0P8_CSIRX0_1  
VDDA_0P8_SERDES0_1  
DSITX clock supply  
DSITX clock supply  
CSIRX analog supply low  
SERDES0-1 analog supply low  
VDDA_0P8_SERDES_C0_1 SERDES0-1 clock supply  
VDDA_0P8_USB  
VDDA_0P8_PLL_DDR0  
VDDA_0P8_PLL_DDR1  
VDDA_1P8_USB  
VDDA_1P8_DSITX  
VDDA_1P8_CSIRX0_1  
VDDA_1P8_SERDES0_1  
VDDA_1P8_SERDES2_4  
VDDA_3P3_USB  
VDDA_MCU_PLLGRP0  
VDDA_PLLGRP0  
VDDA_PLLGRP1  
VDDA_PLLGRP2  
VDDA_PLLGRP5  
VDDA_PLLGRP6  
VDDA_PLLGRP7  
VDDA_PLLGRP8  
VDDA_PLLGRP9  
VDDA_PLLGRP10  
VDDA_PLLGRP12  
VDDA_PLLGRP13  
VDDA_WKUP  
USB0-1 0.8 V analog supply  
DDR0 PLL analog supply  
DDR1 PLL analog supply  
USB0-1 1.8 V analog supply  
DSITX analog supply high  
2.2  
CSIRX analog supply high  
2.2  
SERDES0-1 analog supply high  
SERDES2-4 analog supply high  
USB0-1 3.3 V analog supply  
2.2  
2.2  
3.8  
Analog supply for MCU PLL Group 0  
Analog supply for Main PLL Group 0  
Analog supply for Main PLL Group 1  
Analog supply for Main PLL Group 2  
Analog supply for MAIN PLL Group 5 (DDR)  
Analog supply for MAIN PLL Group 6  
Analog supply for MAIN PLL Group 7  
Analog supply for MAIN PLL Group 8  
Analog supply for MAIN PLL Group 9  
Analog supply for MAIN PLL Group 10  
Analog supply for MAIN PLL Group 12  
Analog supply for MAIN PLL Group 13  
Oscillator supply for WKUP domain  
ADC analog supply  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
VDDA_ADC0  
2.2  
VDDA_ADC1  
ADC analog supply  
2.2  
VDDA_MCU_TEMP  
Analog supply for temperature sensor 0 in MCU domain  
2.2  
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7.1 Absolute Maximum Ratings (continued)  
over operating free-air temperature range (unless otherwise noted) (1) (2)  
PARAMETER  
MIN  
–0.3  
–0.3  
–0.3  
-0.3  
MAX  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
1.2  
1.2  
1.2  
2.2  
2.2  
3.8  
UNIT  
V
VDDA_POR_WKUP  
VDDA_TEMP_0  
VDDA_TEMP_1  
VDDA_TEMP_2  
VDDA_TEMP_3  
VDDA_TEMP_4  
VDDA_OSC1  
WKUP domain analog supply  
Analog supply for temperature sensor 0  
Analog supply for temperature sensor 1  
Analog supply for temperature sensor 2  
Analog supply for temperature sensor 3  
Analog supply for temperature sensor 4  
HFOSC1 supply  
V
V
V
V
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
V
V
VDDS_DDR  
DDR interface power supply  
V
VDDS_DDR_C0  
VDDS_DDR_C1  
VDDS_MMC0  
IO power for DDR0 Memory Clock Bit (MCB) macro  
IO power for DDR1 Memory Clock Bit (MCB) macro  
MMC0 IO supply  
V
V
V
VDDSHV0_MCU  
IO supply MCUSS general IO  
group, and MCU and MAIN  
domain warm reset pins  
1.8 V  
3.3 V  
V
VDDSHV0  
IO supply for MAIN domain  
general  
1.8 V  
3.3 V  
2.2  
3.8  
2.2  
3.8  
2.2  
3.8  
2.2  
3.8  
2.2  
3.8  
1.89  
1.89  
3.6  
3.8  
V
V
V
V
V
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
VDDSHV1_MCU  
VDDSHV2_MCU  
VDDSHV2  
IO supply for MCUSS IO group 1 1.8 V  
3.3 V  
IO supply for MCUSS IO group 2 1.8 V  
3.3 V  
IO supply for MAIN domain IO  
group 2  
1.8 V  
3.3 V  
1.8 V  
3.3 V  
VDDSHV5  
IO supply for MAIN domain IO  
group 5  
VPP_CORE  
VPP_MCU  
Supply voltage range for CORE EFUSE domain  
Supply voltage range for MCU EFUSE domain  
Voltage range for USB VBUS comparator input  
V
V
V
V
USB0_VBUS(8)  
Steady State Max. Voltage at all fail-safe IO pins  
I2C0_SCL,  
I2C0_SDA,  
WKUP_I2C0_SCL,  
WKUP_I2C0_SDA,  
MCU_I2C0_SCL,  
MCU_I2C0_SDA,  
EXTINTn  
MCU_PORz, PORz  
3.8  
2.2  
V
V
–0.3  
–0.3  
Steady State Max. Voltage at all other IO pins(3)  
VMON1_ER_VSYS,  
VMON3_IR_VEXT1P  
8,  
VMON4_IR_VEXT1P  
8,  
VMON2_IR_VCPU,  
VMON6_IR_VEXT0P  
8(7)  
1.05  
–0.3  
VMON5_IR_VEXT3P  
3(7)  
3.8  
–0.3  
–0.3  
All other IO pins  
IO supply voltage + 0.3  
V
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ZHCSRF7 –DECEMBER 2022  
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7.1 Absolute Maximum Ratings (continued)  
over operating free-air temperature range (unless otherwise noted) (1) (2)  
PARAMETER  
MIN  
MAX  
UNIT  
Transient Overshoot and Undershoot specification at IO pin  
20% of IO supply  
voltage for up to 20%  
of signal period  
(see 图7-1, IO  
Transient Voltage  
Ranges)  
0.2 × VDD(6)  
V
Latch-up Performance, Class II (125°C)(4)  
I-Test  
100  
mA  
V
–100  
Over-Voltage (OV)  
Test  
NA  
1.5 × VDD(6)  
(5)  
TSTG  
Storage temperature  
+150  
°C  
–55  
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply  
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If  
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully  
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.  
(2) All voltage values are with respect to their associated VSS or VSSA_x, unless otherwise noted.  
(3) This parameter applies to all IO pins which are not fail-safe and the requirement applies to all values of IO supply voltage. For  
example, if the voltage applied to a specific IO supply is 0 volts the valid input voltage range for any IO powered by that supply will be  
–0.3 to +0.3 volts. Special attention should be applied anytime peripheral devices are not powered from the same power sources  
used to power the respective IO supply. It is important the attached peripheral never sources a voltage outside the valid input voltage  
range, including power supply ramp-up and ramp-down sequences.  
(4) For current pulse injection:  
Pins stressed per JEDEC JESD78E (Class II) and passed with specified I/O pin injection current and clamp voltage of 1.5 times  
maximum recommended I/O voltage and negative 0.5 times maximum recommended I/O voltage.  
For overvoltage performance:  
Supplies stressed per JEDEC JESD78E (Class II) and passed specified voltage injection.  
(5) For tape and reel the storage temperature range is [–10°C; +50°C] with a maximum relative humidity of 70%. TI recommends  
returning to ambient room temperature before usage.  
(6) VDD is the voltage on the corresponding power-supply pin(s) for the IO.  
(7) The VMON pins provides a way to monitor the system power supply. For more information, see System Power Supply Monitor Design  
Guidelines using VMON/POK.  
(8) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see USB VBUS Design  
Guidelines.  
Fail-safe IO terminals are designed such they do not have dependencies on the respective IO power supply  
voltage. This allows external voltage sources to be connected to these IO terminals when the respective IO  
power supplies are turned off. The specific signals that are fail safe are highlighted in the parameter "Steady  
State Max. Voltage at all fail-safe IO pins". All other IO terminals are not fail-safe and the voltage applied to them  
should be limited to the value defined by the "Steady State Max. Voltage at all other IO pins" parameter in  
Absolute Maximum Ratings.  
Overshoot = 20% of nominal  
IO supply voltage  
Tovershoot  
Tperiod  
Tundershoot  
Undershoot = 20% of nominal  
IO supply voltage  
A. Tovershoot + Tundershoot < 20% of Tperiod  
图7-1. IO Transient Voltage Ranges  
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7.2 ESD Ratings  
VALUE  
±1000  
±250  
UNIT  
Human-body model (HBM), per AEC Q100-002(1)  
Charged-device model (CDM), per AEC Q100-011  
All pins  
V(ESD)  
Electrostatic discharge  
V
Corner pins (A1,  
AJ29)  
±750  
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.  
7.3 Recommended Operating Conditions  
over operating free-air temperature range (unless otherwise noted)  
SUPPLY NAME(2)  
DESCRIPTION  
MIN(1)  
0.76  
NOM  
0.8  
MAX(1)  
0.84  
UNIT  
VDD_CORE  
Boot/Active voltage for MAIN domain core supply  
Boot/Active voltage for MCUSS core supply  
V
V
V
VDD_MCU  
VDD_CPU  
0.76  
0.8  
0.89  
Boot voltage for CPU core supply, applied at cold  
power up event  
0.76  
0.8  
0.84  
Active voltage for CPU core supply, after AVS mode  
enabled in software  
AVS(5)-5%  
AVS(5) AVS(5)+5%  
V
VDD_CPU AVS Range  
VDD_MCU_WAKE1  
VDD_WAKE0  
AVS valid voltage range for VDD_CPU  
Core supply for MCU WAKE function  
Core suply for MAIN domain WAKE function  
MMC PLL analog supply  
0.6  
0.76  
0.76  
0.76  
0.81  
0.81  
0.81  
0.76  
0.76  
0.76  
0.76  
0.76  
0.76  
0.76  
0.76  
1.71  
1.71  
1.71  
1.71  
1.71  
3.14  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
0.9  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
0.8  
0.8  
0.8  
0.85  
0.85  
0.85  
0.8  
0.8  
0.8  
0.8  
0.8  
0.8  
0.8  
0.8  
1.8  
1.8  
1.8  
1.8  
1.8  
3.3  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
0.89  
0.89  
0.84  
0.89  
0.89  
0.89  
0.84  
0.84  
0.84  
0.84  
0.84  
0.84  
0.84  
0.84  
1.89  
1.89  
1.89  
1.89  
1.89  
3.46  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
VDDA_0P8_DLL_MMC0  
VDDAR_CORE  
Main domain RAM supply  
VDDAR_MCU  
MCUSS RAM supply  
VDDAR_CPU  
CPU RAM supply  
VDDA_0P8_DSITX  
VDDA_0P8_DSITX_C  
VDDA_0P8_CSIRX0_1  
VDDA_0P8_SERDES0_1  
VDDA_0P8_SERDES_C0_1  
VDDA_0P8_USB  
DSITX clock supply  
DSITX clock supply  
CSIRX analog supply low  
SERDES0-1 analog supply low  
SERDES0-1 clock supply  
USB0-1 0.8v analog supply  
VDDA_0P8_PLL_DDR0  
VDDA_0P8_PLL_DDR1  
VDDA_1P8_USB  
DDR0 PLL analog supply low  
DDR1 PLL analog supply low  
USB0-1 1.8v analog supply  
VDDA_1P8_DSITX  
VDDA_1P8_CSIRX0_1  
VDDA_1P8_SERDES0_1  
VDDA_1P8_SERDES2_4  
VDDA_3P3_USB  
DSITX analog supply high  
CSIRX analog supply high  
SERDES0-1 analog supply high  
SERDES2-4 analog supply high  
USB0-1 3.3v analog supply  
VDDA_MCU_PLLGRP0  
VDDA_PLLGRP0  
Analog supply for MCU PLL Group 0  
Analog supply for Main PLL Group 0  
Analog supply for MAIN PLL Group 1  
Analog supply for MAIN PLL Group 2  
Analog supply for MAIN PLL Group 5 (DDR)  
Analog supply for MAIN PLL Group 6  
Analog supply for MAIN PLL Group 7  
Analog supply for MAIN PLL Group 8  
Analog supply for MAIN PLL Group 9  
VDDA_PLLGRP1  
VDDA_PLLGRP2  
VDDA_PLLGRP5  
VDDA_PLLGRP6  
VDDA_PLLGRP7  
VDDA_PLLGRP8  
VDDA_PLLGRP9  
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7.3 Recommended Operating Conditions (continued)  
over operating free-air temperature range (unless otherwise noted)  
SUPPLY NAME(2)  
DESCRIPTION  
Analog supply for MAIN PLL Group 10  
Analog supply for MAIN PLL Group 12  
Analog supply for MAIN PLL Group 13  
Oscillator supply for wkup domain  
ADC analog supply  
MIN(1)  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
NOM  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
MAX(1)  
UNIT  
V
VDDA_PLLGRP10  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
VDDA_PLLGRP12  
VDDA_PLLGRP13  
VDDA_WKUP  
V
V
V
VDDA_ADC0  
V
VDDA_ADC1  
ADC analog supply  
V
VDDA_MCU_TEMP  
Analog supply for temperature sensor 0 in MCU  
domain  
V
VDDA_POR_WKUP  
VDDA_1P8_MLB  
VDDA_TEMP_0  
VDDA_TEMP_1  
VDDA_TEMP_2  
VDDA_TEMP_3  
VDDA_TEMP_4  
VDDA_OSC1  
WKUP domain analog supply  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
25  
V
V
MLB IO supply (6-pin interface)  
Analog supply for temperature sensor 0  
Analog supply for temperature sensor 1  
Analog supply for temperature sensor 2  
Analog supply for temperature sensor 3  
Analog supply for temperature sensor 4  
Analog supply for HFOSC1  
V
V
V
V
V
V
VDDA_*  
Peak to Peak Noise for all VDDA inputs  
DDR inteface power supply  
mV  
V
VDDS_DDR(3)  
VDDS_DDR_C0  
VDDS_DDR_C1  
VDDS_MMC0  
VDDSHV0  
1.06  
1.06  
1.06  
1.71  
1.71  
3.14  
1.71  
3.14  
1.1  
1.1  
1.1  
1.8  
1.8  
3.3  
1.8  
3.3  
1.15  
1.15  
1.15  
1.89  
1.89  
3.46  
1.89  
3.46  
IO power for DDR0 Memory Clock Bit (MCB) macro  
IO power for DDR1 Memory Clock Bit (MCB) macro  
MMC0 IO supply  
V
V
V
IO supply for main domain  
general  
1.8-V operation  
3.3-V operation  
1.8-V operation  
3.3-V operation  
V
V
VDDSHV0_MCU  
IO supply MCUSS general IO  
group, and MCU and Main  
domain warm reset pins  
V
V
VDDSHV1_MCU(6)  
VDDSHV2  
IO supply for MCUSS IO group 1 1.8-V operation  
3.3-V operation  
1.71  
3.14  
1.71  
3.14  
1.71  
3.14  
1.71  
3.14  
0
1.8  
3.3  
1.89  
3.46  
1.89  
3.46  
1.89  
3.46  
1.89  
3.46  
3.46  
V
V
IO supply for main domain IO  
group 2  
1.8-V operation  
3.3-V operation  
1.8  
V
3.3  
V
VDDSHV2_MCU  
VDDSHV5  
IO supply for MCUSS IO group 2 1.8-V operation  
3.3-V operation  
1.8  
V
3.3  
V
IO supply for main domain IO  
group 5  
1.8-V operation  
3.3-V operation  
1.8  
V
3.3  
V
USB0_VBUS  
USB0_ID  
VSS  
Voltage range for USB VBUS comparator input  
Voltage range for the USB ID input  
Ground  
See (7)  
See (4)  
0
V
V
V
TJ  
Operating junction temperature  
range  
Automotive  
Extended  
-40  
-40  
0
125  
105  
90  
°C  
°C  
°C  
Commercial  
(1) The voltage at the device ball must never be below the MIN voltage or above the MAX voltage for any amount of time. This  
requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, and so forth.  
(2) Refer to Power-On-Hour (POH) Limits for limitations.  
(3) VDDS_DDR is required to still be powered with LPDDR4 voltage ranges, even If DDR interface is unused.  
(4) This terminal is connected to analog circuits in the respective USB PHY. The circuit sources a known current while measuring the  
voltage to determine if the terminal is connected to VSS with a resistance less than 10 Ωor greater than 100 kΩ. The terminal should  
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be connected to ground for USB host operation or open-circuit for USB peripheral operation, and should never be connected to any  
external voltage source.  
(5) The AVS Voltages are device-dependent, voltage domain-dependent, and OPP-dependent. They must be read from the  
VTM_DEVINFO_VDn. For information about VTM_DEVINFO_VDn Registers address, please refer to Voltage and Thermal Manager  
section in the device TRM. The power supply should be adjustable over the ranges shown in the VDD_CPU AVS Range entry.  
(6) When DDR1 is used concurrently with either OSPI0 or Hyperbus, VDDSHV1_MCU is limited to 1.8V (3.3V mode not supported if  
DDR1 is used in the system.)  
(7) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see USB VBUS Design  
Guidelines.  
7.4 Power-On-Hour (POH) Limits  
IP(1) (2) (3)  
VOLTAGE (V)  
(MAX)  
FREQUENCY  
(MHz) (MAX)  
VOLTAGE DOMAIN  
Tj(°C)  
POH  
All  
All  
All  
100%  
100%  
100%  
All  
All  
All  
All Supported OPPs  
All Supported OPPs  
All Supported OPPs  
Automotive -40°C to 125°C(4)  
Extended -40°C to 105°C  
Commercial 0°C to 90°C  
20000  
100000  
100000  
(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard  
terms and conditions for TI semiconductor products.  
(2) Unless specified in the table above, all voltage domains and operating conditions are supported in the device at the noted  
temperatures.  
(3) POH is a function of voltage, temperature and time. Usage at higher voltages and temperatures will result in a reduction in POH.  
(4) Automotive profile is defined as 20000 power on hours with a junction temperature as follows: 5%@-40°C, 65%@70°C, 20%@110°C,  
and 10%@125°C.  
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7.5 Operating Performance Points  
This section describes the operating conditions of the device. This section also contains the description of each  
Operating Performance Point (OPP) for processor clocks and device core clocks.  
表7-1 describes the maximum supported frequency per speed grade for the device.  
表7-1. Speed Grade Maximum Frequency  
MAXIMUM FREQUENCY (MHz)  
DEVICE  
MCU_  
R5SS0  
A72SS0  
2000  
C71SS0/1 R5FSS0/1  
GPU  
800  
800  
800  
CBASS0  
500  
VPAC  
720(1)  
600 (1)  
600 (1)  
DMPAC VENCDEC  
DMSC  
333  
LPDDR4  
550  
520(1)  
4266 MT/  
s(2)  
T
N
H
1000  
750  
1000  
1000  
1000  
1000  
(480MP/s)  
275  
433 (1)  
3733 MT/s  
1600  
1000  
1000  
500  
333  
(2)  
(240MP/s)  
275 (240  
300 (1)  
3200 MT/s  
1200  
500  
500  
333  
(2)  
MP/s)  
(1) Max VPAC and DMPAC speeds not available concurrently due to PLL sharing (max combinations are 720/480 and 650/520 for VPAC/  
DMPAC, respectively.  
(2) Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation. TI  
strongly recommends all designs to follow the TI LPDDR4 EVM PCB layout exactly in every detail (routing, spacing, vias/backdrill,  
PCB material, etc.) in order to achieve the full specified clock frequency. Refer to the Jacinto 7 DDR Board Design and Layout  
Guidelines for details.  
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7.6 Electrical Characteristics  
备注  
The interfaces or signals described in 节7.6.1 through 节7.6.8 correspond to the interfaces or signals  
available in multiplexing mode 0 (Primary Function).  
All interfaces or signals multiplexed on the balls described in these tables have the same DC electrical  
characteristics, unless multiplexing involves a PHY and GPIO combination, in which case different DC  
electrical characteristics are specified for the different multiplexing modes (Functions).  
7.6.1 I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics  
Over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
1.8-V MODE  
VIL  
Input low-level threshold  
0.3 ×  
V
V
VDDSHV(1)  
VILSS  
VIH  
VIHSS  
VHYS  
Input low-level threshold steady state  
Input high-level threshold  
0.3 ×  
VDDSHV(1)  
0.7 ×  
V
VDDSHV(1)  
Input high-level threshold steady state  
Input Hysteresis Voltage  
0.7 ×  
V
VDDSHV(1)  
0.1 ×  
mV  
VDDSHV(1)  
IIN  
Input Leakage Current  
Output low-level voltage  
VI = 1.8 V or 0 V  
±10  
µA  
V
VOL  
0.2 ×  
VDDSHV(1)  
IOL  
Low Level Output Current  
VOL(MAX)  
6
mA  
3.3-V MODE  
VIL  
Input low-level threshold  
0.3 ×  
V
V
VDDSHV(1)  
VILSS  
VIH  
VIHSS  
VHYS  
Input low-level threshold steady state  
Input high-level threshold  
0.25 ×  
VDDSHV(1)  
0.7 ×  
V
VDDSHV(1)  
Input high-level threshold steady state  
Input Hysteresis Voltage  
0.7 ×  
V
VDDSHV(1)  
0.05 ×  
mV  
VDDSHV(1)  
IIN  
Input Leakage Current  
Output low-level voltage  
Low Level Output Current  
VI = 3.3 V or 0 V  
VOL(MAX)  
±10  
0.4  
µA  
V
VOL  
IOL  
6
mA  
(1) VDDSHV stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see the  
Pin Attributes, POWER column.  
7.6.2 Fail-Safe Reset (FS Reset) Electrical Characteristics  
Over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
VIL  
Input low-level threshold  
0.3 ×  
V
VDDSHV(1)  
VILSS  
Input low-level threshold steady state  
0.3 ×  
V
VDDSHV(1)  
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Over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
VIH  
Input high-level threshold  
0.7 ×  
V
VDDSHV(1)  
VIHSS  
Input high-level threshold steady state  
0.7 ×  
V
VDDSHV(1)  
VHYS  
IIN  
Input Hysteresis Voltage  
Input Leakage Current  
200  
mV  
µA  
VI = 1.8 V or 0 V  
±10  
(1) VDDSHV stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see the  
Pin Attributes, POWER column.  
7.6.3 HFOSC/LFOSC Electrical Characteristics  
Over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
HIGH FREQUENCY OSCILLATOR  
VIH  
Input high-level threshold  
Input low-level threshold  
Input Hysteresis Voltage  
0.65 ×  
V
V
VDDSHV(1)  
VIL  
0.35 ×  
VDDSHV(1)  
VHYS  
49  
mV  
LOW FREQUENCY OSCILLATOR  
VIH  
Input high-level threshold  
Input low-level threshold  
Input Hysteresis Voltage  
0.65 ×  
V
V
VDDA_WKUP  
(1)  
VIL  
0.35 ×  
VDDA_WKUP  
(1)  
VHYS  
Active Mode  
85  
mV  
mV  
Bypass Mode  
324  
(1) VDDSHV stands for corresponding power supply. For WKUP_OSC0, the corresponding power supply is VDDA_WKUP. For OSC1_XI,  
the corresponding power supply is VDDS_OSC1.  
7.6.4 eMMCPHY Electrical Characteristics  
Over operating free-air temperature range (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
NOM  
MAX  
UNIT  
VIL  
Input low-level threshold  
0.35 ×  
V
VDDSHV(1)  
VILSS  
VIH  
Input low-level threshold steady state  
Input high-level threshold  
0.20  
V
V
0.65 ×  
VDDSHV(1)  
VIHSS  
IIN  
Input high-level threshold steady state  
Input Leakage Current  
1.4  
V
µA  
µA  
kΩ  
kΩ  
V
VI = 1.8 V or 0 V  
VO = 1.8 V or 0 V  
±10  
±10  
25  
IOZ  
Tri-state Output Leakage Current  
Pull-up Resistor  
RPU  
RPD  
VOL  
VOH  
15  
15  
20  
20  
Pull-down Resistor  
25  
Output low-level voltage  
Output high-level voltage  
0.30  
VDDSHV -  
0.30(1)  
V
IOL  
IOH  
Low Level Output Current  
High Level Output Current  
VOL(MAX)  
VOH(MAX)  
2
2
mA  
mA  
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Over operating free-air temperature range (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
NOM  
MAX  
UNIT  
SRI  
Input Slew Rate  
5E +8  
V/s  
(1) VDDSHV stands for corresponding power supply (vddshv8). For more information on the power supply name and the corresponding  
ball, see the Pin Attributes, POWER column..  
7.6.5 SDIO Electrical Characteristics  
Over operating free-air temperature range (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
NOM  
MAX  
UNIT  
1.8-V MODE  
VIL  
Input low-level threshold  
Input low-level threshold steady state  
Input high-level threshold  
Input high-level threshold steady state  
Input Hysteresis Voltage  
Input Leakage Current  
0.58  
0.58  
V
V
VILSS  
VIH  
1.27  
1.7  
V
VIHSS  
VHYS  
IIN  
V
150  
mV  
µA  
kΩ  
kΩ  
V
VI = 1.8 V or 0 V  
±10  
60  
RPU  
Pull-up Resistor  
40  
40  
50  
50  
RPD  
Pull-down Resistor  
60  
VOL  
Output low-level voltage  
Output high-level voltage  
0.45  
VOH  
VDDSHV-  
0.45(1)  
V
IOL  
Low Level Output Current  
High Level Output Current  
VOL(MAX)  
VOH(MAX)  
4
4
mA  
mA  
IOH  
3.3-V Mode  
VIL  
Input low-level threshold  
0.25 ×  
V
V
V
V
VDDSHV(1)  
VILSS  
VIH  
Input low-level threshold steady state  
Input high-level threshold  
0.15 ×  
VDDSHV(1)  
0.625 ×  
VDDSHV(1)  
VIHSS  
Input high-level threshold steady state  
0.625 ×  
VDDSHV(1)  
VHYS  
IIN  
Input Hysteresis Voltage  
Input Leakage Current  
Pull-up Resistor  
150  
mV  
µA  
kΩ  
kΩ  
V
VI = 1.8 V or 0 V  
±10  
60  
RPU  
RPD  
VOL  
40  
40  
50  
50  
Pull-down Resistor  
60  
Output low-level voltage  
0.125 ×  
VDDSHV(1)  
VOH  
Output high-level voltage  
0.75 ×  
V
VDDSHV(1)  
IOL  
IOH  
Low Level Output Current  
High Level Output Current  
VOL(MAX)  
VOH(MAX)  
6
mA  
mA  
10  
(1) VDDSHV stands for corresponding power supply (vddshv8). For more information on the power supply name and the corresponding  
ball, see the Pin Attributes , POWER column.  
7.6.6 CSI2/DSI D-PHY Electrical Characteristics  
Over operating free-air temperature range (unless otherwise noted)  
PARAMETER  
Low-Power Receiver (LP-RX)  
VIH Input high-level threshold  
MIN  
NOM  
MAX  
UNIT  
740  
mV  
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Over operating free-air temperature range (unless otherwise noted)  
PARAMETER  
MIN  
25  
NOM  
MAX  
UNIT  
mV  
VIL  
Input low-level threshold  
Hysteresis  
550  
VHYS  
mV  
Ultra-Low Power Receiver (ULP-RX)  
VITH  
Input high-level threshold  
Input low-level threshold  
Hysteresis  
740  
25  
mV  
mV  
mV  
VITL-ULPM  
VHYS  
300  
High Speed Receiver (HS-RX)  
VIDTH  
Differential input high-level threshold  
40  
mV  
mV  
mV  
mV  
mV  
mV  
VIDTL  
Differential input low-level threshold  
Maximum differential input voltage  
Single-ended input low-level threshold  
Single-ended input high-level threshold  
Common-mode voltage  
-40  
-40  
70  
VIDMAX  
VILHS  
270  
VIHHS  
460  
330  
VCMRXDC  
7.6.7 ADC12B Electrical Characteristics  
Over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Analog Input  
VMCU_ADC Full-scale Input Range  
VSS  
-1  
VDDA_ADC0/  
1
V
0/1_AIN[7:0]  
DNL  
INL  
Differential Non-Linearity  
Integral Non-Linearity  
0.5  
±1  
±2  
4
LSB  
LSB  
LSB  
±4  
LSBGAIN- Gain Error  
ERROR  
LSBOFFSE Offset Error  
±2  
LSB  
T-ERROR  
CIN  
Input Sampling Capacitance  
5.5  
70  
pF  
dB  
SNR  
Signal-to-Noise Ratio  
Input Signal: 200  
kHz sine wave at  
-0.5 dB Full Scale  
THD  
Total Harmonic Distortion  
Spurious Free Dynamic Range  
Input Signal: 200  
kHz sine wave at  
-0.5 dB Full Scale  
73  
76  
69  
dB  
dB  
dB  
Ω
SFDR  
Input Signal: 200  
kHz sine wave at  
-0.5 dB Full Scale  
SNR(PLUS) Signal-to-Noise Plus Distortion  
Input Signal: 200  
kHz sine wave at  
-0.5 dB Full Scale  
RMCU_ADC Input Impedance of MCU_ADC0/1_AIN[7:0] f = input frequency  
[1/((65.97 ×  
10–-12) ×  
0/1_AIN[0:7]  
fSMPL_CLK)]  
IIN  
Input Leakage  
MCU_ADC0/1_AIN[7  
:0] = VSS  
-10  
24  
μA  
μA  
MCU_ADC0/1_AIN[7  
:0] = VDDA_ADC0/1  
Sampling Dynamics  
FSMPL_CLK SMPL_CLK Frequency  
60  
MHz  
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Over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
tC  
Conversion Time  
13  
ADC0/1  
SMPL_CL  
K Cycles  
tACQ  
Acquisition time  
2
257 ADC0/1  
SMPL_CL  
K Cycles  
TR  
Sampling Rate  
ADC0/1 SMPL_CLK  
= 60 MHz  
4
MSPS  
CCISO  
Channel to Channel Isolation  
100  
dB  
General Purpose Input Mode(1)  
VIL  
Input low-level threshold  
0.35 ×  
VDDA_ADC0/  
1
V
V
V
V
VILSS  
Input high-level threshold steady state  
Input high-level threshold  
0.35 ×  
VDDA_ADC0/  
1
VIH  
0.65 ×  
VDDA_ADC0/  
1
VIHSS  
Input high-level threshold steady state  
0.65 ×  
VDDA_ADC0/  
1
VHYS  
IIN  
Input Hysteresis Voltage  
Input Leakage Current  
200  
mV  
µA  
VI = 1.8 V or 0 V  
6
(1) MCU_ADC0/1 can be configured to operate in General Purpose Input mode, where all MCU_ADC0/1_AIN[7:0] inputs are globally  
enabled to operate as digital inputs via the ADC0/1_CTRL register (gpi_mode_en = 1).  
7.6.8 LVCMOS Electrical Characteristics  
Over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
1.8-V MODE  
VIL  
Input Low Voltage  
0.35 × VDD(1)  
V
V
VILSS  
VIH  
Input Low Voltage Steady State  
Input High Voltage  
0.3 × VDD(1)  
0.65 × VDD(1)  
0.85 × VDD(1)  
150  
V
VIHSS  
VHYS  
IIN  
Input High Voltage Steady State  
Input Hysteresis Voltage  
Input Leakage Current.  
Pull-up Resistor  
V
mV  
µA  
kΩ  
kΩ  
V
VI = 1.8 V or 0 V  
±10  
30  
RPU  
RPD  
VOL  
VOH  
IOL  
15  
15  
22  
22  
Pull-down Resistor  
30  
Output Low Voltage  
0.45  
Output High Voltage  
VDD(1) - 0.45  
V
Low Level Output Current  
High Level Output Current  
VOL(MAX)  
VOH(MIN)  
3
3
mA  
mA  
IOH  
3.3-V MODE  
VIL  
Input Low Voltage  
0.8  
0.6  
V
V
VILSS  
VIH  
Input Low Voltage Steady State  
Input High Voltage  
2.0  
2.0  
V
VIHSS  
VHYS  
Input High Voltage Steady State  
Input Hysteresis Voltage  
V
150  
mV  
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MAX UNIT  
Over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
IIN  
Input Leakage Current.  
VI = 3.3 V or 0 V  
±10  
30  
µA  
kΩ  
V
RPD  
VOL  
VOH  
IOL  
Pull-down Resistor  
15  
22  
Output Low Voltage  
0.4  
Output High Voltage  
Low Level Output Current  
High Level Output Current  
2.4  
5
V
VOL(MAX)  
VOH(MIN)  
mA  
mA  
IOH  
6
(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see the Pin  
Attributes, POWER column.  
7.6.9 USB2PHY Electrical Characteristics  
备注  
USB0 and USB1 Electrical Characteristics are compliant with Universal Serial Bus Revision 2.0  
Specification dated April 27, 2000 including ECNs and Errata as applicable.  
7.6.10 SerDes 2-L-PHY/4-L-PHY Electrical Characteristics  
备注  
The PCIe interfaces are compliant with the electrical parameters specified in PCI Express® Base  
Specification Revision 4.0, September 27, 2017.  
This Device imposes an additional limit on SERDES REFCLK when used in Input mode with internal  
termination enabled, as described by parameter VREFCLK_TERM in 表 7-2, 4-L-PHY SERDES REFCLK  
Electrical Characteristics. Internal termination is enabled by default and must be disabled before  
applying a reference clock signal that exceeds the limits defined by VREFCLK_TERM. External  
termination should always be enabled on the source side.  
表7-2. 4-L-PHY SERDES REFCLK Electrical Characteristics  
Only applies when internal termination is enabled. Over recommended operating conditions (unless otherwise noted)  
PARAMETER  
MIN  
TYP  
MAX  
UNIT  
VREFCLK_TER Single ended voltage threshold at the reference clock  
400  
mV  
pin when internal termination is enabled  
M
RTERM  
Internal termination  
40  
50  
62.5  
Ω
备注  
The SerDes USB interfaces are compliant with the USB3.1 SuperSpeed Transmitter and Receiver  
Normative Electrical Parameters as defined in the Universal Serial Bus 3.1 Specification, Revision  
1.0 , July 26, 2013.  
备注  
The SGMII interfaces electrical characteristics are compliant with 1000BASE-KX per IEEE802.3  
Clause 70.  
备注  
The SGMII 2.5G / XAUI interfaces electrical characteristics are compliant with IEEE802.3 Clause 47.  
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备注  
The QSGMII interface electrical characteristics are compliant with QSGMII Specification revision 1.2.  
备注  
The UFS interface electrical characteristics are compliant with MIPI M-PHY Specification v3.1,  
February 17, 2014.  
备注  
The DP interface electrical characteristics are compliant with the VESA DisplayPort (DP) Standard v  
1.4 February 23, 2016.  
备注  
The eDP interface electrical characteristics are compliant with the VESA Embedded DisplayPort  
(eDP) Standard v1.4b October 23, 2015.  
7.6.13 DDR0 Electrical Characteristics  
备注  
The DDR interface is compatible with JESD209-4B standard compliant LPDDR4 SDRAM devices.  
7.7 VPP Specifications for One-Time Programmable (OTP) eFuses  
This section specifies the operating conditions required for programming the OTP eFuses and is applicable only  
for High-Security Devices.  
7.7.1 Recommended Operating Conditions for OTP eFuse Programming  
over operating free-air temperature range (unless otherwise noted)  
PARAMETER  
DESCRIPTION  
MIN  
NOM  
MAX  
UNIT  
VDD_CORE  
Supply voltage range for the core domain  
during OTP operation; OPP NOM (BOOT)  
See Recommended Operating Conditions  
See Recommended Operating Conditions  
N/A(2)  
V
VDD_MCU  
Supply voltage range for the core domain  
during OTP operation; OPP NOM (BOOT)  
V
V
V
VPP_CORE  
Supply voltage range for the eFuse ROM  
domain during normal operation  
Supply voltage range for the eFuse ROM  
domain during OTP programming(1)  
1.71  
1.8  
1.89  
VPP_MCU  
Supply voltage range for the eFuse ROM  
domain during normal operation  
N/A(2)  
Supply voltage range for the eFuse ROM  
domain during OTP programming(1)  
1.71  
1.8  
1.89  
(1) Supply voltage range includes DC errors and peak-to-peak noise. TI power management solutions TLV70018-Q1 from the TLV707x  
family meet the supply voltage range needed for VPP_CORE and VPP_MCU.  
(2) N/A stands for Not Applicable.  
7.7.2 Hardware Requirements  
The following hardware requirements must be met when programming keys in the OTP eFuses:  
• The VPP_CORE and VPP_MCU power supplies must be disabled when not programming OTP registers.  
• The VPP_CORE and VPP_MCU power supplies must be ramped up after the proper device power-up  
sequence (for more details, see Power Supply Sequencing).  
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7.7.3 Programming Sequence  
Programming sequence for OTP eFuses:  
• Power on the board per the power-up sequencing. No voltage should be applied on the VPP_CORE and  
VPP_MCU terminals during power up and normal operation.  
• Load the OTP write software required to program the eFuse (contact your local TI representative for the OTP  
software package).  
• Apply the voltage on the VPP_CORE and VPP_MCU terminals according to the specification in 节7.7.1.  
• Run the software that programs the OTP registers.  
• After validating the content of the OTP registers, remove the voltage from the VPP_CORE and VPP_MCU  
terminals.  
7.7.4 Impact to Your Hardware Warranty  
You recognize and accept at your own risk that your use of eFuse permanently alters the TI device. You  
acknowledge that eFuse can fail due to incorrect operating conditions or programming sequence. Such a failure  
may render the TI device inoperable and TI will be unable to confirm the TI device conformed to TI device  
specifications prior to the attempted eFuse. CONSEQUENTLY, TI WILL HAVE NO LIABILITY FOR ANY TI  
DEVICES THAT HAVE BEEN eFUSED.  
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7.8 Thermal Resistance Characteristics  
This section provides the thermal resistance characteristics used on this device.  
For reliability and operability concerns, the maximum junction temperature of the device has to be at or below  
the TJ value identified in 节7.3, Recommended Operating Conditions.  
7.8.1 Thermal Resistance Characteristics for ALZ Package  
It is recommended to perform thermal simulations at the system level with the worst case device power consumption.  
ALZ PACKAGE  
NO.  
PARAMETER  
DESCRIPTION  
AIR FLOW  
(m/s)(2)  
°C/W(1)(3)  
T1  
0.3  
2.0  
N/A  
N/A  
0
Junction-to-case  
Junction-to-board  
Junction-to-free air  
RΘJC  
T2  
RΘJB  
T3  
10.4  
6.1  
T4  
1
RΘJA  
T5  
Junction-to-moving air  
5.3  
2
T6  
4.8  
3
T7  
0.16  
0.17  
0.17  
0.17  
1.8  
0
T8  
1
Junction-to-package top  
ΨJT  
T9  
2
T10  
T11  
T12  
T13  
T14  
3
0
1.5  
1
Junction-to-board  
ΨJB  
1.4  
2
1.4  
3
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a  
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/  
JEDEC standards:  
•
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)  
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages  
JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions - Forced Convection (Moving Air)  
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages  
JESD51-9, Test Boards for Area Array Surface Mount Packages  
(2) m/s = meters per second.  
(3) °C/W = degrees Celsius per watt.  
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7.9 Temperature Sensor Characteristics  
This section summarizes the Voltage and Temperature Module (VTM) on die temperature sensor characteristics.  
For reliability and operability concerns, the maximum junction temperature of the device has to be at or below  
the TJ value identified in the Recommended Operating Conditions.  
表7-3. VTM Die Temperature sensor Characteristics  
TEST  
PARAMETER  
MIN  
TYP  
MAX UNIT  
CONDITIONS  
–40 to 110 ℃  
110 to 125 ℃  
5
–5  
–2  
℃
Tacc  
VTM temperature sensor accuracy  
2
℃
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7.10 Timing and Switching Characteristics  
备注  
The timings presented in this section are valid when the DRV_STR (Drive Strength) control in the  
associated PADCONFIG registers are set to the default “0h –Nominal (recommended)”value.  
7.10.1 Timing Parameters and Information  
The timing parameter symbols used in 节 7.10 are created in accordance with JEDEC Standard 100. To shorten  
the symbols, some pin names and other related terminologies have been abbreviated in 表7-4:  
表7-4. Timing Parameters Subscripts  
SYMBOL  
PARAMETER  
Cycle time (period)  
Delay time  
c
d
dis  
en  
h
Disable time  
Enable time  
Hold time  
su  
START  
t
Setup time  
Start bit  
Transition time  
Valid time  
v
w
Pulse duration (width)  
Unknown, changing, or don't care level  
Fall time  
X
F
H
High  
L
Low  
R
Rise time  
V
Valid  
IV  
AE  
FE  
LE  
Z
Invalid  
Active Edge  
First Edge  
Last Edge  
High impedance  
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7.10.2 Power Supply Sequencing  
This section describes power supply sequencing required to ensure proper device operation. The device can be  
operated using either an isolated or combined MCU & Main power distribution network (PDN). Two different  
primary power sequences are recommended based upon isolated and combined MCU & Main PDNs. In  
addition, the device can be operated in either MCU Only or DDR Retention or GPIO Retentioon low power  
modes. Two different desired device power supply sequences for entry and exit of low power modes are shown.  
The power supply names used in this section are specific to this device and align to names given in the Signal  
Descriptions section. Common power supply names may be used across different devices within the Jacinto 7TM  
processor family. These common supply names will have very similar if not identical functions across devices.  
All power sequencing timing diagrams shown will use the following terminology:  
• Primary = Essential power sequences of all voltage domains between off and full active states.  
• VOPR MIN = Minimum operational voltage level that ensures functionality as specified in Recommended  
Operating Conditions  
• Ramp-up = start of a voltage supply transition time from off condition to Vopr min.  
• Ramp-down = start of a voltage supply transition time from Vopr to off condition  
• Supply_“n”= multiple instances of similar power supplies (i.e. VDDSHVn = VDDSHV0, VDDSHV1,  
VDDSHV2 …VDDSHV6)  
• Supply_“xxx”= multiple instances of similar power supplies used for different signal types (i.e.  
VDDA_1P8_xxx = VDDA_1P8_DSITX, VDDA_1P8_USB, VDDA_0P8_DSITX, VDDA_0P8_USB, etc.)  
• Time stamps = “T#”markers with descriptions and approximate elapsed times for general reference.  
Specific timing transitions are dependent upon PDN design (see PDN User Guide for details).  
7.10.2.1 Power Supply Slew Rate Requirement  
To maintain the safe operating range of the internal ESD protection devices, TI recommends limiting the  
maximum slew rate of supplies to be less than 100 mV/us, as shown in 图 7-2. For instance, a 1.8V supply  
should have a ramp time > 18 μs to ensure the slew rate < 100mV/us.  
图7-2 describes the Power Supply Slew Rate Requirement in the device.  
Supply value  
t
Slew Rate = ∆V / ∆T  
Max Slew Rate < 100 mV / µs or 0.1 V / 1E(-6)s = 1E(+5) V / s  
∆Tmin > ∆V / Max Slew Rate or 1.8 V / 1E(+5) V / s  
∆Tmin > 18 µs  
SPRSP08_ELCH_06  
图7-2. Power Supply Slew and Slew Rate  
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7.10.2.2 Combined MCU and Main Domains Power- Up Sequencing  
节 7.10.2.2 describes the primary power-up sequencing when similar MCU and Main voltage domains are  
combined into common power rails. Combining MCU and Main voltage domains simplifies PDN design by  
reducing total number of power rails and sources while making MCU and Main processor sub-systems  
operational dependent on common power rails.  
T0  
T1  
T2  
T3  
T4  
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU,  
VDDSHV0, VDDSHV2, VDDSHV5(D) (B), VDDA_3P3_USB(E)  
)
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU,  
VDDSHV0, VDDSHV2, VDDSHV5(D) (C),VDDS_MMC0  
)
(VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_ADC_MCU,  
VDDA_POR_WKUP, VDDA_WKUP, VDDA_OSC1,  
VDDA_PLLGRP8, VDDA_PLLGRP6,VDDA_PLLGRP4,  
VDDA_PLLGRP0, VDDA_TEMP0, VDDA_TEMP1)(F)  
(VDDA_1P8_SERDES, VDDA_1P8_USB)(G)  
VDD_CPU  
VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0(H)  
VDD_MCU(I), VDD_MCU_WAKE1, VDD_CORE,  
VDD_WAKE0, VDDA_0P8_SERDES,  
VDDA_0P8_SERDES_C, VDDA_0P8_USB,  
VDDAR_CORE, VDDAR_CPU, VDDAR_MCU(I)  
VDDS_DDR_BIAS, VDDS_DDR, VDDS_DDR_C,  
OSC1_XI, OSC1_XO  
(optional)  
WKUP_OSC0_XI, WKUP_OSC0_XO  
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO  
(optional)  
MCU_BOOTMODE[9:0], BOOTMODE[7:0](J)  
MCU_PORz(J)(K)  
Valid Configuration  
PORz(J)(K)  
J7VCL_ELCH_01  
A. Time stamp markers:  
•
•
•
•
•
T0 –3.3V voltages start ramp-up to VOPR MIN. (0 ms)  
T1 –1.8-V voltages start ramp-up to VOPR MIN. (2 ms)  
T2 –Low voltage core supplies start ramp-up to VOPR MIN. (3 ms)  
T3 –Low voltage RAM array voltages start ramp-up to VOPR MIN. (4 ms)  
T4 –OSC1 is stable and PORz/MCU_PORz are de-asserted to release processor from reset. (13 ms)  
B. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3V to support 3.3V digital interfaces. A  
few supplies could have varying start times between T0 to T1 due to PDN designs using different power resources with varying turn-on  
& ramp-up time delays.  
C. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8 V to support 1.8-V digital interfaces.  
When eMMC memories are used, Main 1.8-V supplies could have a ramp-up aligned to T3 due to PDN designs grouping supplies with  
VDD_MMC0.  
D. VDDSHV5 supports MMC1 signaling for SD memory cards. If compliant high-speed SD card operation is needed, then an independent,  
dual voltage (3.3 V/1.8 V) power source and rail are required. The start of ramp-up to 3.3 V will be same as other 3.3-V domains as  
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shown. If SD card is not needed or standard data rates with fixed 3.3 V operation is acceptable, then domain can be grouped with digital  
IO 3.3-V power rail. If a SD card is capable of operating with fixed 1.8 V, then domain can be grouped with digital IO 1.8-V power rail.  
E. VDDA_3P3_USB is 3.3-V analog domain used for USB 2.0 differential interface signaling. A low noise, analog supply is recommended  
to provide best signal integrity for USB data eye mask compliance. The start of ramp-up to 3.3 V will be same as other 3.3-V domains  
as shown. If USB interface is not needed or data bit errors can be tolerated, then domain can be grouped with 3.3-V digital IO power rail  
either directly or through a supply filter.  
F. VDDA_1P8_<clk/pll/ana> are 1.8-V analog domains supporting clock oscillator, PLL and analog circuitry needing a low noise supply for  
optimal performance. It is not recommended to combine digital VDDSHVn_MCU and VDDSHVn IO domains since high frequency  
switching noise could negatively impact jitter performance of clock, PLL and DLL signals. Combining analog VDDA_1p8_<phy>  
domains should be avoided but if grouped, then in-line ferrite bead supply filtering is required.  
G. VDDA_1P8_<phy> are 1.8-V analog domains supporting multiple serial PHY interfaces. A low noise, analog supply is recommended to  
provide best signal integrity, interface performance and spec compliance. If any of these interfaces are not needed, data bit errors or  
non-compliant operation can be tolerated, then domains can be grouped with digital IO 1.8-V power rail either directly or through an in-  
line supply filter is allowed.  
H. VDDA_0P8_<dll/pll> are 0.8-V analog domains supporting PLL and DLL circuitry needing a low noise supply for optimal performance. It  
is not recommended to combine these domains with any other 0.8-V domains since high frequency switching noise could negatively  
impact jitter performance of PLL and DLL signals.  
I.  
VDD_MCU is a digital voltage domain with a wide range enabling it to be grouped and ramped-up with either 0.8-V VDD_CORE or  
0.85-V RAM array (VDDAR_xxx) domains.  
J. Minimum set-up and hold times shown with respect to MCU_PORz and PORz asserting high to latch MCU_BOOTMODEn (referenced  
to MCU_VDDSHV0) and BOOTMODEn (reference to VDDSHV2) settings into registers during power up sequence.  
K. Minimum elapsed time from crystal oscillator circuitry being energized (VDDA_OSC1 at T1) until stable clock frequency is reached  
depends upon on crystal oscillator, capacitor parameters and PCB parasitic values. A conservative 10 ms elapsed time defined by (T4  
–T1) time stamps is shown. This could be reduced depending upon customer’s clock circuit (that is, crystal oscillator or clock  
generator) and PCB designs.  
图7-3. Combined MCU and Main Domains, Primary Power-Up Sequence  
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7.10.2.3 Combined MCU and Main Domains Power- Down Sequencing  
图7-4 describes the device power-down sequencing.  
T0  
T1  
T2  
T3  
T4  
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU,  
VDDSHV0, VDDSHV2, VDDSHV5(D) (B), VDDA_3P3_USB(E)  
)
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU,  
VDDSHV0, VDDSHV2, VDDSHV5(D) (C),VDDS_MMC0  
)
(VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_ADC_MCU,  
VDDA_POR_WKUP, VDDA_WKUP, VDDA_OSC1,  
VDDA_PLLGRP8, VDDA_PLLGRP6,VDDA_PLLGRP4,  
VDDA_PLLGRP0, VDDA_TEMP0, VDDA_TEMP1)(F)  
(VDDA_1P8_SERDES, VDDA_1P8_USB)(G)  
VDD_CPU  
VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0(H)  
VDD_MCU(I), VDD_MCU_WAKE1, VDD_CORE,  
VDD_WAKE0, VDDA_0P8_SERDES,  
VDDA_0P8_SERDES_C, VDDA_0P8_USB,  
VDDAR_CORE, VDDAR_CPU, VDDAR_MCU(I)  
VDDS_DDR_BIAS, VDDS_DDR, VDDS_DDR_C  
TΔ1  
OSC1_XI, OSC1_XO  
(optional)  
WKUP_OSC0_XI, WKUP_OSC0_XO  
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO  
(optional)  
MCU_BOOTMODE[9:0], BOOTMODE[7:0]  
MCU_PORz(J)  
Valid Configuration  
PORz(J)  
J7VCL_ELCH_02  
A. Time stamp markers:  
•
•
•
•
•
T0 –MCU_PORz & PORz assert low to put all processor resources in safe state. (0 ms)  
T1 –Main DDR, SRAM Core, and SRAM CPU power supplies start ramp-down. (0.5 ms)  
T2 –Low voltage core supplies start supply ramp-down. (2.5 ms)  
T3 - 1.8-V voltages start supply ramp-down. (3.0 ms)  
T4 –3.3V voltages start supply ramp-down. (3.5 ms)  
B. Any MCU or Main dual voltage IO domains (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3 V to support 3.3-V digital interfaces.  
C. Any MCU or Main dual voltage IO domains (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8 V to support 1.8-V digital interfaces.  
D. VDDSHV5 supports MMC1 signaling for SD memory cards. A dual voltage (3.3 V/1.8 V) power rail is required for compliant, high-speed  
SD card operations. If SD card is not needed or standard data rates with fixed 3.3-V operation is acceptable, then domain can be  
grouped with digital IO 3.3-V power rail. If a SD card is capable of operating with fixed 1.8 V, then domain can be grouped with digital IO  
1.8-V power rail.  
E. VDDA_3P3_USB is 3.3-V analog domain used for USB 2.0 differential interface signaling. A low noise, analog supply is recommended  
to provide best signal integrity for USB data eye mask compliance. If USB interface is not needed or data bit errors can be tolerated,  
then domain can be grouped with 3.3-V digital IO power rail either directly or through a supply filter.  
F. VDDA_1P8_<clk/pll/ana> are 1.8V analog domains supporting clock oscillator, PLL and analog circuitry needing a low noise supply for  
optimal performance. It is not recommended to combine digital VDDSHVn_MCU and VDDSHVn IO domains since high frequency  
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switching noise could negatively impact jitter performance of clock, PLL and DLL signals. Combining analog VDDA_1p8_<phy>  
domains should be avoided but if grouped, then in-line ferrite bead supply filtering is required .  
G. VDDA_1P8_<phy> are 1.8-V analog domains supporting multiple serial PHY interfaces. A low noise, analog supply is recommended to  
provide best signal integrity, interface performance and spec compliance. If any of these interfaces are not needed, data bit errors or  
non-compliant operation can be tolerated, then domains can be grouped with digital IO 1.8-V power rail either directly or through an in-  
line supply filter is allowed.  
H. VDDA_0P8_<dll/pll> are 0.8-V analog domains supporting PLL and DLL circuitry needing a low noise supply for optimal performance. It  
is not recommended to combine these domains with any other 0.8-V domains since high frequency switching noise could negatively  
impact jitter performance of PLL and DLL signals.  
I.  
VDD_MCU is a digital voltage domain with a wide range enabling it to be grouped and ramped-up with either 0.8-V VDD_CORE or  
0.85-V RAM array (VDDAR_xxx) domains.  
J. MCU_PORz and PORz must be asserted low for TΔ1 = 200 us MIN to ensure SoC resources enter into safe state before any voltage  
begins to ramp down.  
图7-4. Combined MCU and Main Domains, Primary Power-Down Sequence  
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7.10.2.4 Isolated MCU and Main Domains Power- Up Sequencing  
Isolated MCU and Main voltage domains enable an SoC’s MCU and Main processor sub-systems to operate  
independently. There are 2 reasons an SoC’s PDN design may need to support independent MCU and Main  
processor functionality. First is to provide flexibility to enable SoC low power modes that can significant reduce  
SoC power dissipation when processor operations are not needed. Second is to enable robustness to gain  
freedom from interference (FFI) of a single fault impacting both MCU and Main processor sub-systems which is  
especially beneficial if using the SoC’s MCU as the system safety monitoring processor. The number of  
additional PDN power rails needed is dependent upon number of different MCU IO signaling voltage levels. If  
only 1.8V IO signaling is used, then only 2 additional power rails could be required. If both 1.8 and 3.3V IO  
signaling is desired, then 4 additional power rails could be needed.  
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T1  
T2  
T3  
T4  
T0  
Note 1  
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU)(C)  
Note 1  
(VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,  
VDDSHV4, VDDSHV5(E), VDDSHV6)(C),VDDA_3P3_USB(F)  
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU)(D)  
(VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,  
VDDSHV4, VDDSHV5(E), VDDSHV6)(D), VDDS_MMC0  
(VDDA_MCU_PLLGRP0,  
VDDA_MCU_TEMP, VDDA_ADC_MCU,  
VDDA_POR_WKUP, VDDA_WKUP)(G)  
VDDA_OSC1, VDDA_PLLGRP8,  
VDDA_PLLGRP6, VDDA_PLLGRP4,  
VDDA_PLLGRP0, VDDA_TEMP1, VDDA_TEMP0,  
(VDDA_1P8_SERDES, VDDA_1P8_USB)(H)  
VDD_MCU(J),VDD_MCU_WAKE1, VDDAR_MCU  
VDD_CPU  
VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0(I)  
VDD_CORE, VDD_WAKE0, VDDA_0P8_SERDES,  
VDDA_0P8_SERDES_C, VDDA_0P8_USB  
VDDAR_CORE, VDDAR_CPU  
VDDS_DDR_BIAS, VDDS_DDR, VDDS_DDR_C  
OSC1_XI, OSC1_XO  
(optional)  
WKUP_OSC0_XI, WKUP_OSC0_XO  
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO  
(optional)  
MCU_BOOTMODE[9:0], BOOTMODE[7:0](K)  
MCU_PORz(K)(L)  
Valid Configuration  
PORz(K)(L)  
J7VCL_ELCH_03  
A. T1Time stamp markers:  
•
•
•
•
•
T0 –All 3.3-V voltages start supply ramp-up to VOPR MIN. (0 ms)  
T1 –All 1.8-V voltages start supply ramp-up to VOPR MIN. (2 ms)  
T2 –All core voltages start supply ramp-up to VOPR MIN. (3 ms)  
T3 –All RAM array voltages start supply ramp-up to VOPR MIN. (4 ms)  
T4 –OSC1 is stable and PORz/MCU_PORz are de-asserted to release processor from reset. (13 ms)  
B. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3 V to support 3.3-V digital interfaces.  
A few supplies could have varying start times between T0 to T1 due to PDN designs using different power resources with varying turn-  
on & ramp-up time delays.  
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C. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8 V to support 1.8-V digital interfaces.  
When eMMC memories are used, Main 1.8-V supplies could have delayed start times that aligns to T3 due to PDN designs grouping  
supplies with VDD_MMC0.  
D. VDDSHV5 supports MMC1 signaling for SD memory cards. If compliant UHS-I SD card operation is needed, then an independent, dual  
voltage (3.3 V/1.8 V) power source and rail are required. The start of ramp-up to 3.3 V will be same as other 3.3-V domains as shown. If  
SD card is not needed or standard data rates with fixed 3.3-V operation is acceptable, then supply can be grouped with digital IO 3.3-V  
power rail. If a SD card is capable of operating with fixed 1.8 V, then supply can be grouped with digital IO 1.8-V power rail.  
E. VDDA_3P3_USB is 3.3-V analog supply used for USB 2.0 differential interface signaling. A low noise, analog supply is recommended  
to provide best signal integrity for USB data eye mask compliance. The start of ramp-up to 3.3 V will be same as other 3.3-V domains  
as shown. If USB interface is not needed or data bit errors can be tolerated, then supply can be grouped with 3.3-V digital IO power rail  
either directly or through a supply filter.  
F. VDDA_1P8_<clk/pll/ana> are 1.8-V analog domains supporting clock oscillator, PLL and analog circuitry needing a low noise supply for  
optimal performance. It is not recommended to combine digital VDDSHVn_MCU and VDDSHVn IO domains since high frequency  
switching noise could negatively impact jitter performance of clock, PLL and DLL signals. Combining analog VDDA_1p8_<phy>  
domains should be avoided but if grouped, then in-line ferrite bead supply filtering is required.  
G. VDDA_1P8_<phy> are 1.8-V analog domains supporting multiple serial PHY interfaces. A low noise, analog supply is recommended to  
provide best signal integrity, interface performance and spec compliance. If any of these interfaces are not needed, data bit errors or  
non-compliant operation can be tolerated, then domains can be grouped with digital IO 1.8-V power rail either directly or through an in-  
line supply filter is allowed.  
H. VDDA_0P8_<dll/pll> are 0.8-V analog domains supporting PLL and DLL circuitry needing a low noise supply for optimal performance. It  
is not recommended to combine these domains with any other 0.8-V domains since high frequency switching noise could negatively  
impact jitter performance of PLL and DLL signals.  
I.  
VDD_MCU is a digital voltage supply with a wide operational voltage range and power sequencing flexibility, enabling it to be grouped  
and ramped-up with either 0.8-V VDD_CORE at time stamp T2 or 0.85-V RAM array domains (VDDAR_xxx) at time stamp T3.  
J. Minimum set-up and hold times shown with respect to MCU_PORz and PORz asserting high to latch MCU_BOOTMODEn (referenced  
to MCU_VDDSHV0) and BOOTMODEn (reference to VDDSHV2) settings into registers during power up sequence.  
K. Minimum elapsed time from crystal oscillator circuitry being energized (VDDA_OSC1 at T1) until stable clock frequency is reached  
depends upon on crystal oscillator, capacitor parameters and PCB parasitic values. A conservative 10 ms elapsed time defined by (T4  
–T1) time stamps is shown. This could be reduced depending upon customer’s clock circuit (that is, crystal oscillator or clock  
generator) and PCB designs.  
图7-5. Isolated MCU and Main Domains, Primary Power-Up Sequence  
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7.10.2.5 Isolated MCU and Main Domains Power- Down Sequencing  
图7-6 describes the device power-down sequencing.  
T4  
T0  
T1  
T2  
T3  
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU)(B)  
(VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,  
VDDSHV4, VDDSHV5(D), VDDSHV6)(B),VDDA_3P3_USB(E)  
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU)(C)  
(VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,  
VDDSHV4, VDDSHV5(D), VDDSHV6)(C), VDDS_MMC0  
(VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP,  
VDDA_ADC_MCU, VDDA_POR_WKUP, VDDA_WKUP)(F)  
VDDA_OSC1, VDDA_PLLGRP8,  
VDDA_PLLGRP6, VDDA_PLLGRP4,  
VDDA_PLLGRP0, VDDA_TEMP01, VDDA_TEMP0,  
(VDDA_1P8_SERDES, VDDA_1P8_USB)(G)  
VDD_MCU(8) VDD_MCU_WAKE1, VDDAR_MCU  
VDD_CPU  
(VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0)(H)  
VDD_CORE, VDD_WAKE0, VDDA_0P8_SERDES,  
VDDA_0P8_SERDES_C, VDDA_0P8_USB  
VDDAR_CORE, VDDAR_CPU  
VDDS_DDR_BIAS, VDDS_DDR, VDDS_DDR_C  
TΔ1  
OSC1_XI, OSC1_XO  
(optional)  
WKUP_OSC0_XI, WKUP_OSC0_XO  
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO  
(optional)  
MCU_BOOTMODE[9:0], BOOTMODE[7:0]  
MCU_PORz(J)  
Valid Configuration  
PORz(J)  
J7VCL_ELCH_04  
A. Time stamp markers:  
•
•
•
•
•
T0 –MCU_PORz and PORz assert low to put all processor resources in safe state. (0 ms)  
T1 –Main DDR, SRAM Core, and SRAM CPU power domains start ramp-down. (0.5 ms)  
T2 –All core voltages start supply ramp-down. (2.5 ms)  
T3 –All 1.8V voltages start supply ramp-down. (3.0 ms)  
T4 –All 3.3V voltages start supply ramp-down. (3.5 ms)  
B. Any MCU or Main dual voltage IO domains (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3 V to support 3.3-V digital interfaces.  
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C. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8 V to support 1.8-V digital interfaces.  
When eMMC memories are used, Main 1.8-V supplies could have a ramp-down aligned to T1 due to PDN designs grouping supplies  
with VDD_MMC0.  
D. VDDSHV5 supports MMC1 signaling for SD memory cards. A dual voltage (3.3 V/1.8 V) power rail is required for compliant, high-speed  
SD card operations. If compliant high-speed SD card operation is needed, then an independent, dual voltage (3.3 V/1.8 V) power  
source and rail are required. The start of ramp-down from 3.3 V/1.8 V will be same as other 3.3-V domains as shown. If SD card is not  
needed or standard data rates with fixed 3.3-V operation is acceptable, then domain can be grouped with digital IO 3.3-V power rail. If a  
SD card is capable of operating with fixed 1.8 V, then domain can be grouped with digital IO 1.8-V power rail.  
E. VDDA_3P3_USB is 3.3-V analog domain used for USB 2.0 differential interface signaling. A low noise, analog supply is recommended  
to provide best signal integrity for USB data eye mask compliance. The start of ramp-down from 3.3 V will be same as other 3.3-V  
domains as shown. If USB interface is not needed or data bit errors can be tolerated, then domain can be grouped with 3.3-V digital IO  
power rail either directly or through a supply filter.  
F. VDDA_1P8_<clk/pll/ana> are 1.8-V analog domains supporting clock oscillator, PLL and analog circuitry needing a low noise supply for  
optimal performance. It is not recommended to combine digital VDDSHVn_MCU and VDDSHVn IO domains since high frequency  
switching noise could negatively impact jitter performance of clock, PLL and DLL signals. Combining analog VDDA_1p8_<phy>  
domains should be avoided but if grouped, then in-line ferrite bead supply filtering is required.  
G. VDDA_1P8_<phy> are 1.8-V analog domains supporting multiple serial PHY interfaces. A low noise, analog supply is recommended to  
provide best signal integrity, interface performance and spec compliance. If any of these interfaces are not needed, data bit errors or  
non-compliant operation can be tolerated, then domains can be grouped with digital IO 1.8-V power rail either directly or through an in-  
line supply filter is allowed.  
H. VDDA_0P8_<dll/pll> are 0.8-V analog domains supporting PLL and DLL circuitry needing a low noise supply for optimal performance. It  
is not recommended to combine these domains with any other 0.8-V domains since high frequency switching noise could negatively  
impact jitter performance of PLL and DLL signals.  
I.  
VDD_MCU is a digital voltage domain with a wide range enabling it to be grouped and ramped-up with either 0.8-V VDD_CORE or  
0.85V RAM array (VDDAR_xxx) domains.  
J. MCU_PORz and PORz must be asserted low for TΔ1 = 200 us MIN to ensure SoC resources enter into safe state before any voltage  
begins to ramp down.  
图7-6. Isolated MCU and Main Domains, Primary Power- Down Sequencing  
7.10.2.6 Independent MCU and Main Domains, Entry and Exit of MCU Only Sequencing  
Entry into MCU Only state is accomplished by executing a power down sequence except for the 4 MCU domains  
that remain energized. Exit from MCU Only state is accomplished by executing a power up sequence with the 4  
MCU domains remaining energized throughout the seque.  
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Entry into MCU only  
Active  
MCU only  
Exit from MCU only  
Active  
T0  
T1  
T2  
T3  
T4  
T0  
T1  
T2  
T3  
T4  
VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU(2)  
(VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,  
VDDSHV4, VDDSHV5(4), VDDSHV6)(2),VDDA_3P3_USB(5)  
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU)(3)  
(VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,  
VDDSHV4, VDDSHV5, VDDSHV6)(3) VDDS_MMC0  
(VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_ADC_MCU,  
VDDA_POR_WKUP, VDDA_WKUP)(6)  
(VDDA_OSC1, VDDA_PLLGRP8,  
VDDA_PLLGRP6, VDDA_PLLGRP4,  
VDDA_PLLGRP0, VDDA_TEMP1, VDDA_TEMP0)(7)  
(VDDA_1P8_SERDES, VDDA_1P8_USB)(7)  
VDD_MCU(9), VDD_MCU_WAKE1, VDDAR_MCU  
VDD_CPU  
(VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0)(8)  
VDD_CORE, VDD_WAKE0, VDDA_0P8_SERDES,  
VDDA_0P8_SERDES_C, VDDA_0P8_USB  
VDDAR_CORE, VDDAR_CPU  
VDDS_DDR_BIAS, VDDS_DDR, VDDS_DDR_C  
TΔ1  
OSC1_XI, OSC1_XO  
WKUP_OSC0_XI, WKUP_OSC0_XO  
(optional)  
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO  
(optional)  
MCU_BOOTMODE[9:0], BOOTMODE[7:0](10)  
MCU_PORz(10)(11)  
Valid Configuration  
PORz(10)(11)  
J7VCL_ELCH_05  
图7-7. Independent MCU and Main Domains, Entry and Exit of MCU Only Sequencing  
7.10.2.7 Independent MCU and Main Domains, Entry and Exit of DDR Retention State  
Entry into DDR Retention state is accomplished by executing a power down sequence except for the 4 DDR  
domains that remain energized. Exit from DDR Retention state is accomplished by executing a power up  
sequence with the 3 DDR domains remaining energized throughout the sequence.  
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Entry into MCU only  
Active  
DDR Retention  
Exit from MCU only  
Active  
T0  
T1  
T2  
T3  
T4  
T0  
T1  
T2  
T3  
T4  
Note1  
Note1  
VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU(2)  
(VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,  
VDDSHV4, VDDSHV5(4), VDDSHV6)(2), VDDA_3P3_USB(5)  
(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU)(3)  
(VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3,  
VDDSHV4, VDDSHV54,VDDSHV6)(3), VDDS_MMC0  
(VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_ADC_MCU,  
VDDA_POR_WKUP, VDDA_WKUP)(6)  
VDDA_OSC1, VDDA_PLLGRP8,  
VDDA_PLLGRP6, VDDA_PLLGRP4,  
VDDA_PLLGRP0, VDDA_TEMP0, VDDA_TEMP1,  
(VDDA_1P8_SERDES, VDDA_1P8_USB)(7)  
VDD_MCU(9), VDD_MCU_WAKE1, VDDAR_MCU  
VDD_CPU  
(VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0)(9)  
VDD_CORE, VDD_WAKE0VDDA_0P8_SERDES,  
VDDA_0P8_SERDES_C, VDDA_0P8_USB  
VDDAR_CORE, VDDAR_CPU  
VDDS_DDR_BIAS, VDDS_DDR, VDDS_DDR_C  
TΔ1  
OSC1_XI, OSC1_XO  
WKUP_OSC0_XI, WKUP_OSC0_XO  
(optional)  
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO  
(optional)  
MCU_BOOTMODE[9:0], BOOTMODE[7:0](10)  
MCU_PORz(10)(11)  
Valid Configuration  
PORz(10)(11)  
J7VCL_ELCH_06  
图7-8. Independent MCU and Main Domains, Entry and Exit of DDR Retention State  
7.10.2.8 Independent MCU and Main Domains, Entry and Exit of GPIO Retention Sequencing  
Entry into GPIO Retention state is accomplished by executing a power down sequence except for the 2 or 4  
wake domains that remain energized. Exit from GPIO Retention state is accomplished by executing a power up  
sequence with the 2 or 4 wake DDR domains remaining energized throughout the sequence.  
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Entry into MCU only  
Active  
DDR Retention  
Exit from MCU only  
Active  
T0  
T1  
T2  
T3  
T4  
T0  
T1  
T2  
T3  
T4  
Note1  
Note1  
( VDDSHV1_MCU, VDDSHV2_MCU)(2)  
(VDDSHV0, VDDSHV1, VDDSHV3,  
VDDSHV4, VDDSHV5(4), VDDSHV6)(2), VDDA_3P3_USB(5)  
(VDDSHV1_MCU, VDDSHV2_MCU)(3)  
(VDDSHV0, VDDSHV1, VDDSHV3,  
VDDSHV4, VDDSHV54,VDDSHV6)(3), VDDS_MMC0  
VDDSHV0_MCU, VDDSHV2  
(VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_ADC_MCU,  
VDDA_POR_WKUP, VDDA_WKUP)(6)  
VDDA_OSC1, VDDA_PLLGRP8,  
VDDA_PLLGRP6, VDDA_PLLGRP4,  
VDDA_PLLGRP0, VDDA_TEMP0, VDDA_TEMP1,  
(VDDA_1P8_SERDES, VDDA_1P8_USB)(7)  
VDD_MCU(9), VDD_MCU_WAKE1, VDDAR_MCU  
VDD_CPU  
(VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0)(9)  
VDD_CORE, VDD_WAKE0VDDA_0P8_SERDES,  
VDDA_0P8_SERDES_C, VDDA_0P8_USB  
VDDSHV0_MCU, VDDSHV2(8)  
VDDAR_CORE, VDDAR_CPU  
VDDS_DDR_BIAS, VDDS_DDR, VDDS_DDR_C  
TΔ1  
OSC1_XI, OSC1_XO  
WKUP_OSC0_XI, WKUP_OSC0_XO  
(optional)  
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO  
(optional)  
MCU_BOOTMODE[9:0], BOOTMODE[7:0](10)  
MCU_PORz(10)(11)  
Valid Configuration  
PORz(10)(11)  
J7VCL_ELCH_07  
图7-9. Independent MCU and Main Domains, Entry and Exit of GPIO Retention Sequencing  
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7.10.3 System Timing  
For more details about features and additional description information on the subsystem multiplexing signals,  
see the corresponding sections within Signal Descriptions and Detailed Description.  
表7-5. System Timing Conditions  
PARAMETER  
MIN  
0.5  
3
MAX UNIT  
INPUT CONDITIONS  
SRI  
Input slew rate  
2
V/ns  
pF  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
30  
7.10.3.1 Reset Timing  
Tables and figures provided in this section define timing requirements and switching characteristics for reset  
related signals.  
表7-6. MCU_PORz Timing Requirements  
see 图7-10  
NO.  
MIN  
TYP  
MAX UNIT  
Hold time, MCU_PORz active (low) at Power-up  
after all MCU DOMAIN supplies valid (using  
external crystal)  
N +  
RST1  
9500000  
ns  
1200(2)  
th(MCUD_SUPPLIES_VALID - MCU_PORz)  
Hold time, MCU_PORz active (low) at Power-up  
after all MCU DOMAIN supplies(1) valid and  
external clock stable (using external LVCMOS  
oscillator)  
RST2  
1200  
1200  
ns  
ns  
Pulse Width minimum, MCU_PORz low after  
Power-up (without removal of Power or system  
reference clock MCU_OSC0_XI/XO)  
RST3 tw(MCU_PORzL)  
(1) For definition of the MCU DOMAIN supplies, see the 节7.10.2.2.  
(2) N = oscillator start-up time  
RST1  
RST2  
RST3  
MCU_PORz  
MCU DOMAIN  
SUPPLIES VALID  
MCU_OSC0_XI,  
MCU_OSC0_XO  
图7-10. MCU_PORz Timing Requirements  
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表7-7. PORz Timing Requirements  
see 图7-11  
NO.  
MIN  
1200  
1200  
MAX UNIT  
Hold time, PORz active (low) at Power-up after all MAIN  
DOMAIN supplies1 valid  
RST4 th(MAIND_SUPPLIES_VALID - PORz)  
RST5 tw(PORzL)  
ns  
ns  
Pulse Width minimum, PORz low after Power-up  
1. For definition of the MAIN DOMAIN supplies, see the 节7.10.2.2.  
RST4  
RST5  
PORz  
MAIN DOMAIN  
SUPPLIES VALID  
图7-11. PORz Timing Requirements  
表7-8. MCU_PORz initiates; MCU_PORz_OUT, PORz_OUT, MCU_RESETSTATz, and RESETSTATz  
Switching Characteristics  
see 图7-12  
NO.  
PARAMETER  
MODE  
MIN  
MAX UNIT  
Delay time, MCU_PORz active (low) to  
MCU_PORz_OUT active (low)  
RST6 td(MCU_PORzL-MCU_PORz_OUTL)  
0
ns  
Delay time, MCU_PORz inactive (high) to  
MCU_PORz_OUT inactive (high)  
RST7 td(MCU_PORzH-MCU_PORz_OUTH)  
RST8 td(MCU_PORzL-PORz_OUTL)  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Delay time, MCU_PORz active (low) to  
PORz_OUT active (low)  
0
1500  
Delay time, MCU_PORz inactive (high) to  
PORz_OUT inactive (high)  
RST9 td(MCU_PORzH-PORz_OUTH)  
RST10 td(MCU_PORzL-MCU_RESETSTATzL)  
RST11 td(MCU_PORzH-MCU_RESETSTATzH)  
RST12 td(MCU_PORzL-RESETSTATzL)  
RST13 td(MCU_PORzH-RESETSTATzH)  
Delay time, MCU_PORz active (low) to  
MCU_RESETSTATz active (low)  
0
Delay time, MCU_PORz inactive (high) to  
MCU_RESETSTATz inactive (high)  
POST  
bypass  
12000*S(1)  
0
Delay time, MCU_PORz active (low) to  
RESETSTATz active (low)  
Delay time, MCU_PORz inactive (high) to  
RESETSTATz inactive (high)  
14500*S(1)  
Pulse width minimum, MCU_PORz_OUT  
active (low)  
RST14 tw(MCU_PORz_OUTL)  
RST15 tw(PORz_OUTL)  
RST16 tw(MCU_RESETSTATzL)  
RST17 tw(RESETSTATzL)  
1200  
2550  
ns  
ns  
ns  
ns  
Pulse Width Minimum PORz_OUT low  
Pulse Width Minimum MCU_RESETSTATz  
low  
3900*S(1)  
2650*S(1)  
Pulse Width Minimum RESETSTATz low  
(1) S = MCU_OSC0_XI/XO clock period.  
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RST12  
RST6  
RST13  
RST7  
MCU_PORz  
RST14  
MCU_PORz_OUT  
RST10  
RST11  
RST16  
MCU_RESETSTATz  
RST8  
RST9  
RST15  
PORz_OUT  
RST17  
RESETSTATz  
图7-12. MCU_PORz initiates; MCU_PORz_OUT, PORz_OUT, MCU_RESETSTATz, and RESETSTATz  
Switching Characteristics  
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MAX UNIT  
表7-9. PORz Initiates; PORz_OUT and RESETSTATz Switching Characteristics  
see 图7-13  
NO.  
PARAMETER  
MODE  
MIN  
software control of  
POR_RST_ISO_DONE_Z  
T(1)  
Delay time, PORz active (low) toPORz_OUT  
active (low)  
RST18 td(PORzL-PORz_OUTL)  
CTRLMMR_WKUP_POR_RST  
_CTRL[0].POR_RST_ISO_  
DONE_Z = 0  
0
ns  
ns  
Delay time, PORz active (high) toPORz_OUT  
active (high)  
RST19 td(PORzH-PORz_OUTH)  
1300  
T(1)  
td(PORzL-  
RST20  
Delay time, PORz active (low) to RESETSTATz  
active (low)  
CTRLMMR_WKUP_POR_RST  
_CTRL[0].POR_RST_ISO_  
DONE_Z = 0  
RESETSTATzL)  
0
ns  
ns  
td(PORzH-  
RST21  
Delay time, PORz active (high) to RESETSTATz  
active (high)  
14500*S  
(2)  
RESETSTATzH)  
(1) T = Reset Isolation Time (Software Dependent).  
(2) S = MCU_OSC0_XI/XO clock period.  
RST18  
RST19  
PORz  
PORz_OUT  
RST20  
RST21  
RESETSTATz  
图7-13. PORz initiates; PORz_OUT and RESETSTATz Switching Characteristics  
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表7-10. MCU_RESETz Timing Requirements  
see 图7-14  
NO.  
MIN  
MAX UNIT  
(1)  
RST22 tw(MCU_RESETzL)  
Pulse Width minimum, MCU_RESETz active (low)  
1200  
ns  
(1) Timing for MCU_RESETz is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.  
表7-11. MCU_RESETz initiates; MCU_RESETSTATz, and RESETSTATz Switching Characteristics  
see 图7-14  
NO.  
PARAMETER  
MIN  
MAX UNIT  
Delay time, MCU_RESETz active (low) to  
MCU_RESETSTATz active (low)  
RST23 td(MCU_RESETzL-MCU_RESETSTATzL)  
800  
ns  
Delay time, MCU_RESETz inactive (high) to  
MCU_RESETSTATz inactive (high)  
RST24 td(MCU_RESETzH-MCU_RESETSTATzH)  
RST25 td(MCU_RESETzL-RESETSTATzL)  
RST26 td(MCU_RESETzH-RESETSTATzH)  
(1) S = MCU_OSC0_XI/XO clock period.  
3900*S(1)  
800  
ns  
ns  
ns  
Delay time, MCU_RESETz active (low) to RESETSTATz  
active (low)  
Delay time, MCU_RESETz inactive (high) to  
RESETSTATz inactive (high)  
3900*S(1)  
RST23  
RST24  
MCU_RESETz  
RST22  
MCU_RESETSTATz  
RESETSTATz  
RST25  
RST26  
图7-14. MCU_RESETz initiates; MCU_RESETSTATz, and RESETSTATz Timing Requirements and  
Switching Characteristics  
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表7-12. RESET_REQz Timing Requirements  
see 图7-15  
NO.  
MIN  
MAX UNIT  
(1)  
RST27 tw(RESET_REQzL)  
Pulse Width minimum, RESET_REQz active (low)  
1200  
ns  
(1) Timing for RESET_REQz is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.  
表7-13. RESET_REQz initiates; RESETSTATz Switching Characteristics  
see 图7-15  
NO.  
PARAMETER  
MODE  
MIN  
MAX UNIT  
software control of  
SOC_WARMRST_ISO_DONE  
_Z  
T(1)  
Delay time, RESET_REQz active (low)  
to RESETSTATz active (low)  
RST28 td(RESET_REQzL-RESETSTATzL)  
CTRLMMR_WKUP_MAIN_WA  
RM  
740  
ns  
ns  
_RST_CTRL[0].SOC_  
WARMRST_ISO_DONE_Z = 0  
Delay time, RESET_REQz inactive  
(high) to RESETSTATz inactive (high)  
2650*S  
RST29 td(RESET_REQzH-RESETSTATzH)  
(2)  
(1) T = Reset Isolation Time (Software Dependent).  
(2) S = MCU_OSC0_XI/XO clock period.  
RST27  
RST28  
RESET_REQz  
RST29  
RESETSTATz  
图7-15. RESET_REQz initiates; RESETSTATz Timing Requirements and Switching Characteristics  
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表7-14. EMUx Timing Requirements  
see 图7-16  
NO.  
MIN  
3*S(1)  
10  
MAX UNIT  
RST30 tsu(EMUx-MCU_PORz)  
RST31 th(MCU_PORz - EMUx)  
Setup time, EMU[1:0] before MCU_PORz inactive (high)  
Hold time, EMU[1:0] after MCU_PORz inactive (high)  
ns  
ns  
(1) S = MCU_OSC0_XI/XO clock period.  
RST30  
MCU_PORz  
EMU[1:0]  
RST31  
图7-16. EMUx Timing Requirements  
表7-15. MCU_BOOTMODE Timing Requirements  
see 图7-17  
NO.  
MIN  
MAX UNIT  
Setup time, MCU_BOOTMODE[09:00] before  
MCU_PORz_OUT high  
RST32 tsu(MCU_BOOTMODE-MCU_PORz_OUT)  
RST33 th(MCU_PORz_OUT - MCU_BOOTMODE)  
(1) S = MCU_OSC0_XI/XO clock period.  
3*S(1)  
ns  
Hold time, MCU_BOOTMODE[09:00] after MCU_  
PORz_OUT high  
0
ns  
RST32  
MCU_PORz_OUT  
MCU_BOOTMODE[09:00]  
RST33  
图7-17. MCU_BOOTMODE Timing Requirements  
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表7-16. BOOTMODE Timing Requirements  
see 图7-18  
NO.  
MIN  
3*S(1)  
0
MAX UNIT  
RST34 tsu(BOOTMODE-PORz_OUT)  
RST35 th(PORz_OUT - BOOTMODE)  
Setup time, BOOTMODE[7:0] before PORz_OUT high  
Hold time, BOOTMODE[7:0] after PORz_OUT high  
ns  
ns  
(1) S = MCU_OSC0_XI/XO clock period.  
RST34  
PORz_OUT  
BOOTMODE[7:0]  
RST35  
图7-18. BOOTMODE Timing Requirements  
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7.10.3.2 Safety Signal Timing  
Tables and figures provided in this section define switching characteristics for MCU_SAFETY_ERRORn and  
SOC_SAFETY_ERRORn.  
表7-17. MCU_SAFETY_ERRORn Switching Characteristics  
see 图7-19  
NO.  
PARAMETER  
MIN  
MAX UNIT  
Pulse width minimum, MCU_SAFETY_ERRORn active  
(PWM mode disabled)  
SFTY1 tw(MCU_SAFETY_ERRORn)  
P*R(1) (2)  
ns  
Delay time, ERROR CONDITION to  
SFTY2 td (ERROR_CONDITION-MCU_SAFETY_ERRORnL) MCU_SAFETY_ERRORn  
active  
50*P(1)  
ns  
(1) P = ESM functional clock (MCU_SYSCLK0 /6).  
(2) R = Error Pin Counter Pre-Load Register count value.  
Internal Error Condition  
(Active High)  
SFTY1  
SFTY2  
MCU_SAFETY_ERRORn  
(PWM Mode Disabled)  
图7-19. MCU_SAFETY_ERRORn Switching Characteristics  
表7-18. SOC_SAFETY_ERRORn Switching Characteristics  
see 图7-20  
NO.  
PARAMETER  
MIN  
MAX UNIT  
Pulse width minimum,SOC_SAFETY_ERRORn active  
(PWM mode disabled)  
SFTY3 tw(SOC_SAFETY_ERRORn)  
P*R(1) (2)  
ns  
Delay time, ERROR CONDITION to  
SFTY4 td (ERROR_CONDITION-SOC_SAFETY_ERRORnL) SOC_SAFETY_ERRORn  
active  
50*P(1)  
ns  
Internal Error Condition  
(Active High)  
SFTY3  
SFTY4  
SOC_SAFETY_ERRORn  
(PWM Mode Disabled)  
图7-20. SOC_SAFETY_ERRORn Switching Characteristics  
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7.10.3.3 Clock Timing  
Tables and figures provided in this section define timing requirements and switching characteristics for clock  
signals.  
表7-19. Clock Timng Requiements  
see 图7-21  
NO.  
MIN  
10  
MAX UNIT  
CLK1 tc(EXT_REFCLK1)  
CLK2 tw(EXT_REFCLK1H)  
CLK3 tw(EXT_REFCLK1L)  
Cycle time minimum, EXT_REFCLK1  
ns  
Pulse Duration minimum, EXT_REFCLK1 high  
Pulse Duration minimum, EXT_REFCLK1 low  
E*0.45(1)  
E*0.45(1)  
E*0.55(1)  
E*0.55(1)  
ns  
ns  
(1) E = EXT_REFCLK1 cycle time.  
图7-21. Clock Timing Requirements  
表7-20. Clock Switching Characteristics  
see 图7-22  
NO.  
PARAMETER  
MIN  
8
MAX UNIT  
CLK4 tc(SYSCLKOUT0)  
CLK5 tw(SYSCLKOUT0H)  
CLK6 tw(SYSCLKOUT0L)  
CLK7 tc(OBSCLK0)  
Cycle time minimum,SYSCLKOUT0  
Pulse Duration minimum, SYSCLKOUT0 high  
Pulse Duration minimum, SYSCLKOUT0 low  
Cycle time minimum, OBSCLK0  
ns  
A*0.4(1)  
A*0.4(1)  
5
A*0.6(1)  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
A*0.6(1)  
CLK8 tw(OBSCLK0H)  
CLK9 tw(OBSCLK0L)  
CLK10 tc(CLKOUT0)  
Pulse Duration minimum, OBSCLK0 high  
Pulse Duration minimum,OBSCLK0 low  
Cycle time minimum, CLKOUT0  
B*0.4(2)  
B*0.4(2)  
20  
B*0.6(2)  
B*0.6(2)  
CLK11 tw(CLKOUT0H)  
CLK12 tw(CLKOUT0L)  
Pulse Duration minimum, CLKOUT0 high  
Pulse Duration minimum,CLKOUT0 low  
C*0.4(3)  
C*0.4(3)  
C*0.6(3)  
C*0.6(3)  
(1) A = SYSCLKOUT0 cycle time.  
(2) B = OBSCLK0 cycle time.  
(3) C = CLKOUT0 cycle time.  
图7-22. Clock Switching Characteristics  
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7.10.4 Clock Specifications  
7.10.4.1 Input and Output Clocks / Oscillators  
Various external clock inputs/outputs are needed to drive the device. Summary of these input clock signals is as  
follows:  
• High frequency oscillators inputs  
– OSC1_XO/OSC1_XI —external main crystal interface pins connected to internal oscillator which sources  
reference clock. Provides reference clock to PLLs within MCU domain and MAIN domain. This high-  
frequency oscillator is used to provide audio clock frequencies to MCASPs.  
– WKUP_OSC0_XO/WKUP_OSC0_XI —external main crystal interface pins connected to internal  
oscillator which sources reference clock. Provides reference clock to PLLs within WKUP and MAIN  
domain.  
• Low frequency digital input  
– WKUP_LF_CLKIN - Low Frequency 32k digital clock input, optionally sourced from an external PMIC or  
other clock source. This SoC does not support a LFOSC crystal input.  
• General purpose clock inputs  
– MCU_EXT_REFCLK0 - optional external System clock input (MCU domain).  
– EXT_REFCLK1 —optional external System clock input (MAIN domain).  
• Peripheral clocks - refer to the Signal Descriptions for peripheral specific clocks  
•
For more information about Input clock interfaces, see Clocking section in Device Configuration chapter in the  
device TRM.  
7.10.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source  
图 7-23 shows the recommended crystal circuit. All discrete components used to implement the oscillator circuit  
should be placed as close as possible to the WKUP_OSC0_XI and WKUP_OSC0_XO pins.  
Device  
WKUP_OSC0_XO  
WKUP_OSC0_XI  
Rd  
(Optional)  
Crystal  
(Optional)  
Rbias  
Cf2  
Cf1  
PCB Ground  
J7ES_WKUP_OSC_INT_02  
图7-23. WKUP_OSC0 Crystal Implementation  
The crystal must be in the fundamental mode of operation and parallel resonant. 表 7-21 summarizes the  
required electrical constraints.  
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MAX UNIT  
表7-21. WKUP_OSC0 Crystal Electrical Characteristics  
PARAMETER  
Fxtal  
MIN  
TYP  
Crystal Parallel Resonance Frequency  
Crystal Frequency Stability and Tolerance  
19.2, 20, 24, 25, 26, 27  
MHz  
ppm  
Fxtal  
Ethernet RGMII and RMII  
not used  
±100  
Ethernet RGMII and RMII  
using derived clock  
±50  
CL1+PCBXI  
CL2+PCBXO  
CL  
Capacitance of CL1 + CPCBXI  
Capacitance of CL2 + CPCBXO  
Crystal Load Capacitance  
12  
12  
6
24  
24  
12  
pF  
pF  
pF  
pF  
Cshunt  
Crystal Circuit Shunt Capacitance  
19.2 MHz, 20 MHz,  
24 MHz, 25 MHz, 26 MHz,  
27 MHz  
ESRxtal = 30 Ω  
ESRxtal = 40 Ω  
ESRxtal = 50 Ω  
7
5
5
19.2 MHz, 20 MHz,  
24 MHz, 25 MHz, 26 MHz,  
27 MHz  
pF  
pF  
19.2 MHz, 20 MHz,  
24 MHz, 25 MHz, 26 MHz,  
27 MHz  
19.2 MHz, 20 MHz, 24 MHz  
19.2 MHz, 20 MHz  
25 MHz  
pF  
pF  
pF  
pF  
5
5
ESRxtal = 60 Ω  
ESRxtal = 80 Ω  
3
19.2 MHz, 20 MHz  
3
ESRxtal = 100 Ω  
ESRxtal  
Crystal Effective Series Resistance  
100  
Ω
When selecting a crystal, the system design must consider the temperature and aging characteristics of a based  
on the worst case environment and expected life expectancy of the system.  
表7-22 details the switching characteristics of the oscillator and the requirements of the input clock.  
表7-22. WKUP_OSC0 Switching Characteristics –Crystal Mode  
PARAMETER  
MIN  
TYP  
MAX UNIT  
CXI  
XI Capacitance  
1.55  
pF  
pF  
fF  
CXO  
CXIXO  
ts  
XO Capacitance  
1.35  
XI to XO Mutual Capacitance  
Maximum Start-up Time  
0.9  
9.5(1)  
ms  
(1) TI strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. The  
vendors are equipped to determine what load capacitors will best tune their resonator/crystal to the microcontroller device  
for optimum startup and operation over temperature/voltage extremes.  
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VDD_WKUP (min.)  
VSS  
VDD_WKUP  
VDDA_WKUP (min.)  
VDDA_WKUP  
WKUP_OSC0_XO  
tsX  
VSS  
Time  
J7ES_WKUP_OSC_STARTUP_04  
图7-24. WKUP_OSC0 Start-up Time  
7.10.4.1.1.1 Load Capacitance  
The crystal circuit must be designed such that it applies the appropriate capacitive load to the crystal, as defined  
by the crystal manufacturer. The capacitive load, CL, of this circuit is a combination of discrete capacitors CL1,  
CL2, and several parasitic contributions. PCB signal traces which connect crystal circuit components to  
WKUP_OSC0_XI and WKUP_OSC0_XO have parasitic capacitance to ground, CPCBXI and CPCBXO, where the  
PCB designer should be able to extract parasitic capacitance for each signal trace. The WKUP_OSC0 circuits  
and device package have combined parasitic capacitance to ground, CPCBXI and CPCBXO, where these parasitic  
capacitance values are defined in 表7-22.  
Device  
Crystal Circuit  
Components  
PCB  
Signal Traces  
WKUP_OSC0_XI  
CL1  
CPCBXI  
CXI  
CL2  
CPCBXO  
CXO  
WKUP_OSC0_XO  
J7ES_WKUP_OSC_CC_05  
图7-25. Load Capacitance  
Load capacitors, CL1 and CL2 in 图 7-23, should be chosen such that the below equation is satisfied. CL in the  
equation is the load specified by the crystal manufacturer.  
CL = [(CL1 + CPCBXI + CXI) × (CL2 + CPCBXO + CXO)] / [(CL1 + CPCBXI + CXI) + (CL2 + CPCBXO + CXO)]  
To determine the value of CL1 and CL2, multiply the capacitive load value CL by 2. Using this result, subtract the  
combined values of CPCBXI + CXI to determine the value of CL1 and the combined values of CPCBXO + CXO to  
determine the value of CL2. For example, if CL = 10 pF, CPCBXI = 2.9 pF, CXI = 0.5 pF, CPCBXO = 3.7 pF, CXO = 0.5  
pF, the value of CL1 = [(2CL) - (CPCBXI + CXI)] = [(2 × 10 pF) - 2.9 pF - 0.5 pF)] = 16.6 pF and CL2 = [(2CL) -  
(CPCBXO + CXO)] = [(2 × 10 pF) - 3.7 pF - 0.5 pF)] = 15.8 pF  
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7.10.4.1.1.2 Shunt Capacitance  
The crystal circuit must also be designed such that it does not exceed the maximum shunt capacitance for  
WKUP_OSC0 operating conditions defined in 表 7-21. Shunt capacitance, Cshunt, of the crystal circuit is a  
combination of crystal shunt capacitance and parasitic contributions. PCB signal traces which connect crystal  
circuit components to WKUP_OSC0 have mutual parasitic capacitance to each other, CPCBXIXO, where the PCB  
designer should be able to extract mutual parasitic capacitance between these signal traces. The device  
package also has mutual parasitic capacitance, CXIXO, where this mutual parasitic capacitance value is defined  
in 表7-22.  
PCB routing should be designed to minimize mutual capacitance between XI and XO signal traces. This is  
typically done by keeping signal traces short and not routing them in close proximity. Mutual capacitance can  
also be minimized by placing a ground trace between these signals when the layout requires them to be routed  
in close proximity. It is important to minimize the mutual capacitance on the PCB to provide as much margin as  
possible when selecting a crystal.  
Device  
Crystal Circuit  
Components  
PCB  
Signal Traces  
WKUP_OSC0_XI  
CPCBXIXO  
CXIXO  
CO  
WKUP_OSC0_XO  
J7ES_WKUP_OSC_SC_06  
图7-26. Shunt Capacitance  
A crystal should be chosen such that the below equation is satisfied. CO in the equation is the maximum shunt  
capacitance specified by the crystal manufacturer.  
C
shunt ≥CO + CPCBXIXO + CXIXO  
For example, the equation would be satisfied when the crystal being used is 25 MHz with an ESR = 30 Ω,  
CPCBXIXO = 0.04 pF, CXIXO = 0.01 pF, and shunt capacitance of the crystal is less than or equal to 6.95 pF.  
7.10.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source  
图 7-27 shows the recommended oscillator connections when WKUP_OSC0_XI is connected to a 1.8-V  
LVCMOS square-wave digital clock source.  
备注  
A DC steady-state condition is not allowed on WKUP_OSC0_XI when the oscillator is powered up.  
This is not allowed because WKUP_OSC0_XI is internally AC coupled to a comparator that may enter  
a unknown state when DC is applied to the input. Therefore, application software should power down  
WKUP_OSC0 any time WKUP_OSC0_XI is not toggling between logic states.  
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Device  
WKUP_OSC0_XO  
WKUP_OSC0_XI  
PCB Ground  
J7ES_WKUP_OSC_EXT_CLK_05  
图7-27. 1.8-V LVCMOS-Compatible Clock Input  
7.10.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source  
图 7-28 shows the recommended crystal circuit. All discrete components used to implement the oscillator circuit  
should be placed as close as possible to the OSC1_XI and OSC1_XO pins.  
Device  
OSC1_XO  
OSC1_XI  
Rd  
(Optional)  
Crystal  
(Optional)  
Rbias  
Cf2  
Cf1  
PCB Ground  
J7ES_AUX_OSC_INT_07  
图7-28. OSC1 Crystal Implementation  
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The crystal must be in the fundamental mode of operation and parallel resonant. 表 7-23 summarizes the  
required electrical constraints.  
表7-23. OSC1 Crystal Electrical Characteristics  
PARAMETER  
MIN  
TYP  
MAX UNIT  
Fxtal  
Fxtal  
Crystal Parallel Resonance Frequency  
19.2  
27  
MHz  
ppm  
Crystal Frequency Stability and Tolerance  
Ethernet RGMII and RMII  
not used  
±100  
Ethernet RGMII and RMII  
using derived clock  
±50  
CL1+PCBXI  
CL2+PCBXO  
CL  
Capacitance of CL1 + CPCBXI  
Capacitance of CL2 + CPCBXO  
Crystal Load Capacitance  
12  
12  
6
24  
24  
12  
7
pF  
pF  
pF  
pF  
Cshunt  
Crystal Circuit Shunt Capacitance  
19.2 MHz, 20 MHz,  
24 MHz, 25 MHz, 26 MHz,  
27 MHz  
ESRxtal = 30 Ω  
ESRxtal = 40 Ω  
ESRxtal = 50 Ω  
19.2 MHz, 20 MHz,  
24 MHz, 25 MHz, 26 MHz,  
27 MHz  
5
5
pF  
pF  
19.2 MHz, 20 MHz,  
24 MHz, 25 MHz, 26 MHz,  
27 MHz  
19.2 MHz, 20 MHz, 24 MHz  
19.2 MHz, 20 MHz  
25 MHz  
5
5
pF  
pF  
pF  
pF  
ESRxtal = 60 Ω  
ESRxtal = 80 Ω  
3
19.2 MHz, 20 MHz  
3
ESRxtal = 100 Ω  
ESRxtal  
Crystal Effective Series Resistance  
100  
Ω
When selecting a crystal, the system design must consider the temperature and aging characteristics of a based  
on the worst case environment and expected life expectancy of the system.  
表7-24 details the switching characteristics of the oscillator and the requirements of the input clock.  
表7-24. OSC1 Switching Characteristics –Crystal Mode  
PARAMETER  
MIN  
TYP  
MAX  
1.55  
1.35  
0.9  
UNIT  
pF  
CXI  
XI Capacitance  
XO Capacitance  
CXO  
CXIXO  
ts  
pF  
XI to XO Mutual Capacitance  
Maximum Start-up Time  
fF  
9.5(1)  
ms  
(1) TI strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. The  
vendors are equipped to determine what load capacitors will best tune their resonator/crystal to the microcontroller device  
for optimum startup and operation over temperature/voltage extremes.  
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VDD_CORE (min.)  
VSS  
VDD_CORE  
VDDS_OSC1  
VDDS_OSC1 (min.)  
OSC1_XO  
tsX  
VSS  
Time  
J7ES_AUX_OSC_STARTUP_08  
图7-29. OSC1 Start-up Time  
7.10.4.1.3.1 Load Capacitance  
The crystal circuit must be designed such that it applies the appropriate capacitive load to the crystal, as defined  
by the crystal manufacturer. The capacitive load, CL, of this circuit is a combination of discrete capacitors CL1,  
CL2, and several parasitic contributions. PCB signal traces which connect crystal circuit components to OSC1_XI  
and OSC1_XO have parasitic capacitance to ground, CPCBXI and CPCBXO, where the PCB designer should be  
able to extract parasitic capacitance for each signal trace. The OSC1 circuits and device package have  
combined parasitic capacitance to ground, CPCBXI and CPCBXO, where these parasitic capacitance values are  
defined in 表7-24.  
Device  
Crystal Circuit  
Components  
PCB  
Signal Traces  
OSC1_XI  
CL1  
CPCBXI  
CXI  
CL2  
CPCBXO  
CXO  
OSC1_XO  
J7ES_AUX_OSC_CC_05  
图7-30. Load Capacitance  
Load capacitors, CL1 and CL2 in 图 7-28, should be chosen such that the below equation is satisfied. CL in the  
equation is the load specified by the crystal manufacturer.  
CL = [(CL1 + CPCBXI + CXI) × (CL2 + CPCBXO + CXO)] / [(CL1 + CPCBXI + CXI) + (CL2 + CPCBXO + CXO)]  
To determine the value of CL1 and CL2, multiply the capacitive load value CL by 2. Using this result, subtract the  
combined values of CPCBXI + CXI to determine the value of CL1 and the combined values of CPCBXO + CXO to  
determine the value of CL2. For example, if CL = 10 pF, CPCBXI = 2.9 pF, CXI = 0.5 pF, CPCBXO = 3.7 pF, CXO = 0.5  
pF, the value of CL1 = [(2CL) - (CPCBXI + CXI)] = [(2 × 10 pF) - 2.9 pF - 0.5 pF)] = 16.6 pF and CL2 = [(2CL) -  
(CPCBXO + CXO)] = [(2 × 10 pF) - 3.7 pF - 0.5 pF)] = 15.8 pF  
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7.10.4.1.3.2 Shunt Capacitance  
The crystal circuit must also be designed such that it does not exceed the maximum shunt capacitance for OSC1  
operating conditions defined in 表 7-23. Shunt capacitance, Cshunt, of the crystal circuit is a combination of  
crystal shunt capacitance and parasitic contributions. PCB signal traces which connect crystal circuit  
components to OSC1 have mutual parasitic capacitance to each other, CPCBXIXO, where the PCB designer  
should be able to extract mutual parasitic capacitance between these signal traces. The device package also  
has mutual parasitic capacitance, CXIXO, where this mutual parasitic capacitance value is defined in 表7-24.  
PCB routing should be designed to minimize mutual capacitance between XI and XO signal traces. This is  
typically done by keeping signal traces short and not routing them in close proximity. Mutual capacitance can  
also be minimized by placing a ground trace between these signals when the layout requires them to be routed  
in close proximity. It is important to minimize the mutual capacitance on the PCB to provide as much margin as  
possible when selecting a crystal.  
Device  
Crystal Circuit  
Components  
PCB  
Signal Traces  
OSC1_XI  
CPCBXIXO  
CXIXO  
CO  
OSC1_XO  
J7ES_AUX_OSC_SC_06  
图7-31. Shunt Capacitance  
A crystal should be chosen such that the below equation is satisfied. CO in the equation is the maximum shunt  
capacitance specified by the crystal manufacturer.  
C
shunt ≥CO + CPCBXIXO + CXIXO  
For example, the equation would be satisfied when the crystal being used is 25 MHz with an ESR = 30 Ω,  
CPCBXIXO = 0.04 pF, CXIXO = 0.01 pF, and shunt capacitance of the crystal is less than or equal to 6.95 pF.  
7.10.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source  
图 7-32 shows the recommended oscillator connections when OSC1 is connected to a 1.8-V LVCMOS square-  
wave digital clock source.  
备注  
A DC steady-state condition is not allowed on OSC1_XI when the oscillator is powered up. This is not  
allowed because OSC1_XI is internally AC coupled to a comparator that may enter a unknown state  
when DC is applied to the input. Therefore, application software should power down OSC1 any time  
OSC1_XI is not toggling between logic states.  
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Device  
OSC1_XO  
OSC1_XI  
PCB Ground  
J7ES_AUX_OSC_EXT_09  
图7-32. 1.8-V LVCMOS-Compatible Clock Input  
7.10.4.1.5 Auxiliary OSC1 Not Used  
图 7-33 shows the recommended oscillator connections when OSC1 is not used. OSC1_XI must be connected  
to VSS through an external pull resistor (Rpd) to ensure this input is held to a valid low level when unused since  
the internal pull-down resistor is disabled by default.  
Device  
OSC1_XO  
OSC1_XI  
Rpd  
NC  
PCB Ground  
J7ES_AUX_OSC_NOT_USED_11  
图7-33. OSC1 Not Used  
7.10.4.2 Output Clocks  
The device provides several system clock outputs. Summary of these output clocks are as follows:  
• MCU_CLKOUT0  
– Reference clock output for Ethernet PHYs (50 MHz or 25 MHz)  
• MCU_SYSCLKOUT0  
– MCU_SYSCLK0 is divided by 4 and then sent out of the device as a LVCMOS clock signal  
(MCU_SYSCLKOUT0). This signal can be used to test if the main chip clock is functioning or not. This  
signal should not be used as a clock source for external devices on a board.  
• MCU_OBSCLK0  
– On the clock output MCU_OBSCLK0, oscillators and PLLs clocks can be observed for tests and debug.  
This signal should not be used as a clock source for external devices on a board.  
• SYSCLKOUT0  
– SYSCLK0 is divided by 4 and then sent out of the device as a LVCMOS clock signal (SYSCLKOUT0).  
This signal can be used to test if the main chip clock is functioning or not. This signal should not be used  
as a clock source for external devices on a board.  
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• CLKOUT  
– Reference clock output for Ethernet PHYs (50 MHz)  
• OBSCLK[1:0]  
– On the clock output OBSCLK0/1, oscillators and PLLs clocks can be observed for tests and debug.  
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7.10.4.3 PLLs  
Power is supplied to the Phase-Locked Loop circuitries (PLLs) by internal regulators that derive power from the  
off-chip power-supply.  
There are total of three PLLs in the device in WKUP and MCU domains:  
• MCU_PLL0 (MCU R5FSS PLL) with WKUP_PLLCTRL0  
• MCU_PLL1 (MCU PERIPHERAL PLL)  
• MCU_PLL2 (MCU CPSW PLL)  
There are total of twenty PLLs in the device in MAIN domain:  
• PLL0 (MAIN PLL) with PLLCTRL0  
• PLL1 (PER0 PLL)  
• PLL2 (PER1 PLL)  
• PLL3 (CPSW9G PLL)  
• PLL4 (AUDIO0 PLL)  
• PLL5 (VIDEO PLL)  
• PLL6 (GPU PLL)  
• PLL7 (C7x PLL)  
• PLL8 (ARM0 PLL)  
• PLL12 (DDR PLL)  
• PLL13 (C66 PLL)  
• PLL14 (R5F PLL)  
• PLL15 (AUDIO1 PLL)  
• PLL16 (DSS PLL0)  
• PLL17 (DSS PLL1)  
• PLL18 (DSS PLL2)  
• PLL19 (DSS PLL3)  
• PLL23 (DSS PLL7)  
• PLL24 (MLB PLL)  
• PLL25 (VISION PLL)  
备注  
For more information, see:  
• Device Configuration / Clocking / PLLs section in the device TRM.  
• Peripherals / Display Subsystem Overview section in the device TRM.  
备注  
The input reference clock (OSC1_XI/OSC1_XO) is specified and the lock time is ensured by the PLL  
controller, as documented in the Device Configuration chapter in the device TRM.  
7.10.4.4 Module and Peripheral Clocks Frequencies  
节 7.10.5, Peripherals section documents the maximum frequency associated with the peripheral clocks of the  
device.  
For more details on the clocking structure of each module, reference Device Configurations chapter in the device  
TRM.  
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7.10.5 Peripherals  
7.10.5.1 ATL  
The device contains ATL module that can be used for asynchronous sample rate conversion of audio. The ATL  
calculates the error between two time bases, such as audio syncs, and optionally generates an averaged clock  
using cycle stealing via software.  
备注  
For more information about ATL, see Audio Tracking Logic (ATL) section in Peripherals chapter in the  
device TRM.  
表7-25 represents ATL timing conditions.  
表7-25. ATL Timing Conditions  
PARAMETER  
MODE  
MIN  
0.5  
1
MAX  
5
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
External reference CLK  
Internal reference CLK  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
10  
节 7.10.5.1.1, 节 7.10.5.1.2, 节 7.10.5.1.3, and 节 7.10.5.1.4 present timing requirements and switching  
characteristics for ATL.  
7.10.5.1.1 ATL_PCLK Timing Requirements  
NO.  
PARAMETER  
MODE  
MIN  
MAX UNIT  
External reference  
CLK  
D1 tc(pclk)  
Cycle time, ATL_PCLK  
5
ns  
External reference  
CLK  
D2 tw(pclkL)  
Pulse Duration, ATL_PCLK low  
Pulse Duration, ATL_PCLK high  
0.45 × M(1) + 2.5  
0.45 × M(1) + 2.5  
ns  
ns  
External reference  
CLK  
D3 tw(pclkH)  
(1) M = ATL_CLK[x] period  
7.10.5.1.2 ATL_AWS[x] Timing Requirements  
NO.  
MODE  
MIN  
MAX UNIT  
External reference  
CLK  
D4 tc(aws)  
D5 tw(awsL)  
D6 tw(awsH)  
Cycle Time, ATL_AWS[x](3)  
2 × M(1)  
ns  
External reference  
CLK  
Pulse Duration, ATL_AWS[x](3) low  
Pulse Duration, ATL_AWS[x](3) high  
0.45 × A(2) + 2.5  
0.45 × A(2) + 2.5  
ns  
ns  
External reference  
CLK  
(1) M = ATL_CLK[x] period  
(2) A = ATL_AWS[x] period  
(3) x = 0 to 3  
7.10.5.1.3 ATL_BWS[x] Timing Requirements  
NO.  
MODE  
MIN  
MAX UNIT  
External reference  
clock  
D7 tc(bws)  
Cycle Time, ATL_BWS[x](3)  
2 × M(1)  
ns  
External reference  
clock  
D8 tw(bwsL)  
Pulse Duration, ATL_BWS[x] low(3)  
0.45 × B(2) + 2.5  
ns  
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MODE  
MIN  
MAX UNIT  
External reference  
clock  
D9 tw(bwsH)  
Pulse Duration, ATL_BWS[x] high(3)  
0.45 × B(2) + 2.5  
ns  
(1) M = ATL_CLK[x] period  
(2) B = ATL_BWS[x] period  
(3) x = 0 to 3  
7.10.5.1.4 ATCLK[x] Switching Characteristics  
NO.  
PARAMETER  
MODE  
MIN  
MAX UNIT  
Internal reference  
CLK  
D10 tc(atclk)  
Cycle time, ATCLK[x](3)  
20  
ns  
Internal reference  
CLK  
D11 tw(atclkL)  
D12 tw(atclkH)  
Pulse Duration, ATCLK[x] low(3)  
Pulse Duration, ATCLK[x] high(3)  
0.45 × P(2) - M(1) - 0.3  
0.45 × P(2) - M(1) - 0.3  
ns  
ns  
Internal reference  
CLK  
(1) M = ATL_CLK[x] period  
(2) P = ATCLK[x] period  
(3) x = 0 to 3  
D10  
D12  
ATCLK[x]  
D11  
atl_01  
图7-34. ATCLK[x] Timing  
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7.10.5.2 CPSW2G  
For more details about features and additional description information on the device Gigabit Ethernet MAC, see  
the corresponding sections within Signal Descriptions and Detailed Description.  
7.10.5.2.1 CPSW2G MDIO Interface Timings  
表7-26 represents CPSW2G timing conditions.  
表7-26. CPSW2G MDIO Timing Conditions  
PARAMETER  
INPUT CONDITIONS  
SRI  
DESCRIPTION  
MIN  
0.9  
10  
MAX  
3.6  
UNIT  
V/ns  
pF  
Input signal slew rate  
OUTPUT CONDITIONS  
CL Output load capacitance  
470  
表7-27, 表7-28, and 图7-35 present timing requirements for MDIO.  
表7-27. CPSW2G MDIO Timing Requirements  
NO.  
MIN  
MAX  
UNIT  
ns  
MDIO1 tsu(mdioV-mdcH)  
MDIO2 th(mdcH-mdioV)  
Setup time, MDIO[x]_MDIO valid before MDIO[x]_MDC high  
Hold time, MDIO[x]_MDIO valid after MDIO[x]_MDC high  
90  
0
ns  
表7-28. CPSW2G MDIO Switching Characteristics  
NO.  
PARAMETER  
MIN  
400  
MAX  
UNIT  
ns  
MDIO3 tc(mdc)  
MDIO4 tw(mdcH)  
MDIO5 tw(mdcL)  
MDIO7 td(mdcL-mdioV)  
Cycle time, MDIO[x]_MDC  
Pulse Duration, MDIO[x]_MDC high  
160  
ns  
Pulse Duration, MDIO[x]_MDC low  
160  
ns  
Delay time, MDIO[x]_MDC low to MDIO[x]_MDIO valid  
150  
ns  
–150  
MDIO3  
MDIO4  
MDIO5  
MDIO[x]_MDC  
MDIO1  
MDIO2  
MDIO[x]_MDIO  
(input)  
MDIO7  
MDIO[x]_MDIO  
(output)  
CPSW2G_MDIO_TIMING_01  
图7-35. CPSW2G MDIO Timing Requirements and Switching Characteristics  
备注  
x = 0 in MCU domain  
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7.10.5.2.2 CPSW2G RMII Timings  
表 7-29, 节 7.10.5.2.2.1, 节 7.10.5.2.2.2, and 节 7.10.5.2.2.3 present timing conditions, requirements, and  
switching characteristics for CPSW2G RMII.  
表7-29. CPSW2G RMII Timing Conditions  
PARAMETER  
MIN  
MAX  
UNIT  
INPUT CONDITIONS  
SRI Input signal slew rate  
VDD(1) = 1.8 V  
VDD(1) = 3.3 V  
0.108  
0.4  
0.54  
1.2  
V/ns  
V/ns  
OUTPUT CONDITIONS  
CL Output load capacitance  
3
25  
pF  
(1) VDD stands for corresponding power supply. For more information on the power supply name and  
the corresponding ball(s), see POWER column of the Pin Attributes  
7.10.5.2.2.1 CPSW2G RMII[x]_REF_CLK Timing Requirements –RMII Mode  
see 图7-36  
NO.  
MIN  
MAX  
20  
UNIT  
ns  
RMII1  
RMII2  
RMII3  
tc(ref_clk)  
Cycle time, RMII[x]_REF_CLK  
19.999  
tw(ref_clkH)  
tw(ref_clkL)  
Pulse Duration, RMII[x]_REF_CLK high  
Pulse Duration, RMII[x]_REF_CLK low  
7
7
13  
ns  
13  
ns  
RMII1  
RMII2  
RMII[x]_REF_CLK  
RMII3  
A. x = 1 in MCU domain.  
图7-36. CPSW2G RMII[x]_REFCLK Timing Requirements –RMII Mode  
7.10.5.2.2.2 CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements –RMII Mode  
NO.  
MIN  
MAX  
UNIT  
Setup time, RMII[x]_RXD[1:0] valid before RMII[x]_REF_CLK rising  
edge  
tsu(rxdV-ref_clkH)  
tsu(crs_dvV-ref_clkH)  
tsu(rx_erV-ref_clkH)  
th(ref_clkH-rxdV)  
4
ns  
Setup time, RMII[x]_CRS_DV valid before RMII[x]_REF_CLK rising  
edge  
RMII4  
4
4
2
ns  
ns  
ns  
Setup time, RMII[x]_RX_ER valid before RMII[x]_REF_CLK rising  
edge  
Hold time, RMII[x]_RXD[1:0] valid after RMII[x]_REF_CLK rising  
edge  
RMII5  
Hold time, RMII[x]_CRS_DV valid after RMII[x]_REF_CLK rising  
edge  
th(ref_clkH-crs_dvV)  
th(ref_clkH-rx_erV)  
2
2
ns  
ns  
Hold time, RMII[x]_RX_ER valid after RMII[x]_REF_CLK rising edge  
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RMII4  
RMII5  
RMII[x]_REF_CLK  
RMII[x]_RXD[1:0], RMII[x]_CRS_DV,  
RMII[x]_RX_ER  
图7-37. CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RX_ER Timing Requirements –RMII Mode  
节7.10.5.2.2.3, and 图7-38 present switching characteristics for CPSW2G RMII Transmit.  
7.10.5.2.2.3 CPSW2G RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics –RMII Mode  
see 图7-38  
NO.  
PARAMETER  
MIN  
MAX UNIT  
td(ref_clkH-txdV)  
Delay time, RMII[x]_REF_CLK rising edge to RMII[x]_TXD[1:0] valid  
2
10  
10  
ns  
ns  
RMII6  
td(ref_clkH-tx_enV) Delay time, RMII[x]_REF_CLK rising edge to RMII[x]_TX_EN valid  
2
RMII6  
RMII[x]_REF_CLK  
RMII[x]_TXD[1:0], RMII[x]_TX_EN  
图7-38. RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics –RMII Mode  
7.10.5.2.3 CPSW2G RGMII Timings  
节7.10.5.2.3.1, 节7.10.5.2.3.2, and 图7-40 present timing requirements for receive RGMII operation.  
For more information, see Gigabit Ethernet MAC (MCU_CPSW0) section in Peripherals chapter in the device  
TRM.  
表7-30. CPSW2G RGMII Timing Conditions  
PARAMETER  
MIN  
MAX UNIT  
INPUT CONDITIONS  
VDD(1) = 1.8 V  
VDD(1) = 3.3 V  
1.44  
2.64  
5
5
V/ns  
V/ns  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
2
20  
pF  
PCB CONNECTIVITY REQUIREMENTS  
RGMII[x]_RXC,  
RGMII[x]_RD[3:0],  
RGMII[x]_RX_CTL  
50  
50  
ps  
ps  
td(Trace Mismatch  
Propagation delay mismatch across all traces  
Delay)  
RGMII[x]_TXC,  
RGMII[x]_TD[3:0],  
RGMII[x]_TX_CTL  
(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see  
POWER column of the Pin Attributes.  
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7.10.5.2.3.1 RGMII[x]_RXC Timing Requirements –RGMII Mode  
see 图7-39  
NO.  
MODE  
10Mbps  
MIN  
360  
36  
MAX UNIT  
440  
44  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RGMII1 tc(rxc)  
RGMII2 tw(rxcH)  
RGMII3 tw(rxcL)  
Cycle time, RGMII[x]_RXC  
100Mbps  
1000Mbps  
10Mbps  
7.2  
160  
16  
8.8  
240  
24  
Pulse duration, RGMII[x]_RXC high  
Pulse duration, RGMII[x]_RXC low  
100Mbps  
1000Mbps  
10Mbps  
3.6  
160  
16  
4.4  
240  
24  
100Mbps  
1000Mbps  
3.6  
4.4  
7.10.5.2.3.2 CPSW2G Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL –RGMII Mode  
see 图7-39  
NO.  
MODE  
MIN  
MAX UNIT  
10Mbps  
1
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Setup time, RGMII[x]_RD[3:0] valid before RGMII[x]_RXC  
transition  
tsu(rdV-rxcV)  
tsu(rx_ctlV-rxcV)  
th(rxcV-rdV)  
100Mbps  
1000Mbps  
10Mbps  
1
1
RGMII4  
1
Setup time, RGMII[x]_RX_CTL valid before RGMII[x]_RXC  
transition  
100Mbps  
1000Mbps  
10Mbps  
1
1
1
Hold time, RGMII[x]_RD[3:0] valid after RGMII[x]_RXC  
transition  
100Mbps  
1000Mbps  
10Mbps  
1
1
RGMII5  
1
Hold time, RGMII[x]_RX_CTL valid after RGMII[x]_RXC  
transition  
th(rxcV-rx_ctlV)  
100Mbps  
1000Mbps  
1
1
RGMII1  
RGMII2  
RGMII3  
RGMII[x]_RXC(A)  
RGMII4  
RGMII5  
RGMII[x]_RD[3:0](B)  
RGMII[x]_RX_CTL(B)  
1st Half-byte  
RXDV  
2nd Half-byte  
RXERR  
A. RGMII_RXC must be externally delayed relative to the data and control pins.  
B. Data and control information is received using both edges of the clocks. RGMII_RXD[3:0] carries data bits 3-0 on the rising edge of  
RGMII_RXC and data bits 7-4 on the falling edge of RGMII_RXC. Similarly, RGMII_RXCTL carries RXDV on rising edge of RGMII_RXC  
and RXERR on falling edge of RGMII_RXC.  
图7-39. CPSW2G Receive Interface Timing, RGMII Operation  
节 7.10.5.2.3.3, 节 7.10.5.2.3.4 present switching characteristics for transmit - RGMII for 10 Mbps, 100 Mbps,  
and 1000 Mbps.  
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MAX UNIT  
7.10.5.2.3.3 CPSW2G RGMII[x]_TXC Switching Characteristics –RGMII Mode  
NO.  
PARAMETER  
MODE  
10Mbps  
MIN  
360  
36  
tc(txc)  
Cycle time, RGMII[x]_TXC  
440  
44  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RGMII6  
100Mbps  
1000Mbps  
10Mbps  
7.2  
160  
16  
8.8  
240  
24  
tw(txcH)  
Pulse duration, RGMII[x]_TXC high  
Pulse duration, RGMII[x]_TXC low  
RGMII7  
RGMII8  
100Mbps  
1000Mbps  
10Mbps  
3.6  
160  
16  
4.4  
240  
24  
tw(txcL)  
100Mbps  
1000Mbps  
3.6  
4.4  
7.10.5.2.3.4 RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics –RGMII Mode  
see 图7-40  
NO.  
PARAMETER  
MODE  
MIN  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
MAX UNIT  
10Mbps  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Output setup time, RGMII[x]_TD[3:0] valid to RGMII[x]_TXC  
transition  
tosu(tdV-txcV)  
tosu(tx_ctlV-txcV)  
toh(tdV-txcV)  
100Mbps  
1000Mbps  
10Mbps  
RGMII9  
Output setup time, RGMII[x]_TX_CTL valid to RGMII[x]_TXC  
transition  
100Mbps  
1000Mbps  
10Mbps  
Output hold time, RGMII[x]_TD[3:0] valid after RGMII[x]_TXC  
transition  
100Mbps  
1000Mbps  
10Mbps  
RGMII10  
Output hold time, RGMII[x]_TX_CTL valid after  
RGMII[x]_TXC transition  
toh(tx_ctlV-txcV)  
100Mbps  
1000Mbps  
RGMII6  
RGMII7  
RGMII8  
RGMII[x]_TXC(A)  
RGMII9  
RGMII[x]_TD[3:0](B)  
RGMII[x]_TX_CTL(B)  
1st Half-byte  
TXEN  
2nd Half-byte  
TXERR  
RGMII10  
A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled.  
B. Data and control information is received using both edges of the clocks. RGMII_TD[3:0] carries data bits 3-0 on the rising edge of  
RGMII_TXC and data bits 7-4 on the falling edge of RGMII_TXC. Similarly, RGMII_TX_CTL carries TXDV on rising edge of RGMII_TXC  
and RTXERR on falling edge of RGMII_TXC.  
图7-40. CPSW2G Transmit Interface Timing RGMII Mode  
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7.10.5.3 CSI-2  
备注  
For more information, see the Camera Streaming Interface Receiver (CSI_RX_IF) chapter in the  
device TRM.  
The CSI_RX_IF deals with the processing of the pixel data coming from an external image sensor and data from  
memory. It is a key component for the following multimedia applications: camera viewfinder, video record, and  
still image capture.  
The CSI_RX_IF has a primary serial interface (CSI-2 port) compliant with the MIPI D-PHY RX specification v1.2  
and the MIPI CSI-2 specification v1.3, with 4 differential data lanes plus 1 differential clock lane in synchronous  
mode, double data rate. Refer to the specification for timing details.  
• 2.5 Gbps (1.25 GHz) for each lane.  
7.10.5.4 DDRSS  
For more details about features and additional description information on the device LPDDR4 Memory  
Interfaces, see the corresponding sections within Signal Descriptions and Detailed Description.  
The device has dedicated interface to LPDDR4. It supports JEDEC JESD209-4B standard compliant LPDDR4  
SDRAM devices with the following features:  
• 32-bit data path to external SDRAM memory  
• Memory device capacity: Up to 8GB address space available over two chip selects (4GB per rank)  
• No support for byte mode LPDDR4 memories, or memories with more than 17 row address bits  
表7-31 and 图7-41 present switching characteristics for DDRSS.  
表7-31. Switching Characteristics for DDRSS  
NO.  
PARAMETER  
DDR TYPE  
MIN  
MAX UNIT  
3.003 ns  
1
tc(DDR_CKP/DDR_CKN)  
Cycle time, DDR0_CKP and DDR0_CKN  
LPDDR4  
0.4681  
1. Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and  
by PCB implementation. TI strongly recommends all designs to follow the TI LPDDR4 EVM PCB layout  
exactly in every detail (routing, spacing, vias/backdrill, PCB material, etc.) in order to achieve the full  
specified clock frequency. Refer to the Jacinto 7 DDR Board Design and Layout Guidelines for details.  
1
DDR0_CKP  
DDR0_CKN  
图7-41. DDRSS Memory Interface Clock Timing  
For more information, see DDR Subsystem (DDRSS) section in Memory Controllers chapter in the device TRM.  
7.10.5.5 DSS  
For more details about features and additional description information on the device Display Subsystem –Video  
Output Ports, see the corresponding sections within Signal Descriptions and Detailed Description.  
表7-32 represents DPI timing conditions.  
表7-32. DPI Timing Conditions  
PARAMETER  
MIN  
MAX  
UNIT  
INPUT CONDITIONS  
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表7-32. DPI Timing Conditions (continued)  
PARAMETER  
MIN  
MAX  
UNIT  
SRI  
Input slew rate  
1.44  
26.4  
V/ns  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
1.5  
5
pF  
ps  
PCB CONNECTIVITY REQUIREMENTS  
Propagation delay mismatch  
across all traces  
td(Trace Mismatch Delay)  
100  
表 7-33, 表 7-34, 图 7-42 and 图 7-43 assume testing over the recommended operating conditions and electrical  
characteristic conditions.  
表7-33. DPI Video Output Switching Characteristics  
NO.(2)  
D1  
PARAMETER  
MIN  
6.06  
MAX UNIT  
tc(pclk)  
Cycle time, VOUT(x)_PCLK  
ns  
ns  
ns  
D2  
tw(pclkL)  
Pulse duration, VOUT(x)_PCLK low  
Pulse duration, VOUT(x)_PCLK high  
0.475×P(1)  
0.475×P(1)  
-0.68  
D3  
tw(pclkH)  
td(pclkV-dataV)  
D4  
Delay time, VOUT(x)_PCLK transition to VOUT(x)_DATA[23:0]  
transition  
1.78  
1.78  
ns  
D5  
td(pclkV-ctrlL)  
Delay time, VOUT(x)_PCLK transition to control signals  
-0.68  
ns  
VOUT(x)_VSYNC, VOUT(x)_HSYNC, VOUT(x)_DE falling edge  
(1) P = output VOUT(x)_PCLK period in ns.  
(2) x in VOUT(x) = 1 or 2  
D2  
D3  
D1  
Falling-edge Clock Reference  
Rising-edge Clock Reference  
VOUT(x)_PCLK  
VOUT(x)_PCLK  
D5  
VOUT(x)_VSYNC  
D5  
VOUT(x)_HSYNC  
D4  
VOUT(x)_DATA[23:0]  
VOUT(x)_DE  
data_1 data_2  
D5  
data_n  
DPI_TIMING_01  
A. The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock.  
B. The polarity and the pulse width of VOUT(x)_HSYNC and VOUT(x)_VSYNC are programmable, refer to Display Subsystem (DSS)  
section in Peripherals chapter in the device TRM.  
C. The VOUT(x)_PCLK frequency can be configured, refer to Display Subsystem section in Peripherals chapter in the device TRM.  
D. x in VOUT(x) = 1 or 2.  
图7-42. DPI Video Output  
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表7-34. DPI External Pixel Clock Timing Requirements  
MIN  
6.06  
MAX  
UNIT  
ns  
D6  
D7  
D8  
tc(extpclkin)  
tw(extpclkinL)  
tw(extpclkinH)  
Cycle time, VOUT(x)_EXTPCLKIN  
Pulse duration, VOUT(x)_EXTPCLKIN low  
Pulse duration, VOUT(x)_EXTPCLKIN high  
0.45×P(1)  
0.45×P(1)  
ns  
ns  
(1) P = output VOUT(x)_PCLK period in ns.  
(2) x in VOUT(x) = 1 or 2  
D7  
D8  
D6  
Falling-edge Clock Reference  
Rising-edge Clock Reference  
VOUT(x)_EXTPCLKIN  
VOUT(x)_EXTPCLKIN  
DPI_TIMING_02  
图7-43. DPI External Pixel Clock Input  
For more information, see Display Subsystem (DSS) and Peripherals section in Peripherals chapter in the device  
TRM.  
7.10.5.6 eCAP  
The supported features by the device ECAP are:  
• 32-bit time base counter  
• 4-event time-stamp registers (each 32 bits)  
• Independent edge polarity selection for up to four sequenced time-stamp capture events  
• Interrupt capabilities on any of the four capture events  
• Input capture signal pre-scaling (from 1 to 16)  
• Support of different capture modes (single shot capture, continuous mode capture, absolute timestamp  
capture or difference mode time-stamp capture)  
表7-35 represents ECAP timing conditions.  
表7-35. ECAP Timing Conditions  
PARAMETER  
MIN  
1
MAX  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
4
7
OUTPUT CONDITIONS  
CL  
Output load capacitance  
2
节7.10.5.6.1 and 节7.10.5.6.2 present timing and switching characteristics for eCAP (see 图7-44 and 图7-45).  
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7.10.5.6.1 Timing Requirements for eCAP  
NO.  
PARAMETER  
DESCRIPTION  
Pulse duration, CAP (asynchronous)  
MIN  
MAX  
UNIT  
CAP1 tw(cap)  
2 + 2P(1)  
ns  
(1) P = sysclk  
CAP1  
CAP  
EPERIPHERALS_TIMNG_01  
图7-44. eCAP Input Timings  
7.10.5.6.2 Switching Characteristics for eCAP  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
–2 + 2P(1)  
CAP2 tw(apwm)  
Pulse duration, APWM  
ns  
(1) P = sysclk  
CAP2  
APWM  
EPERIPHERALS_TIMNG_02  
图7-45. eCAP Output Timings  
For more information, see Enhanced Capture (ECAP) Module section in Peripherals chapter in the device TRM.  
7.10.5.7 EPWM  
The supported features by the device EPWM are:  
• Dedicated 16-bit time-base counter with period and frequency control  
• Two independent PWM outputs which can be used in different configurations (with single-edge operation,  
with dual-edge symmetric operation or one independent PWM output with dual-edge asymmetric operation)  
• Asynchronous override control of PWM signals during fault conditions  
• Programmable phase-control support for lag or lead operation relative to other EPWM modules  
• Dead-band generation with independent rising and falling edge delay control  
• Programmable trip zone allocation of both latched and un-latched fault conditions  
• Events enabling to trigger both CPU interrupts and start of ADC conversions  
表7-36 represents EPWM timing conditions.  
表7-36. EPWM Timing Conditions  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
1
4
7
OUTPUT CONDITIONS  
CL  
Output load capacitance  
2
节7.10.5.7.2, 节7.10.5.7.1 and present timing and switching characteristics for eHRPWM (see 图7-47, 图7-48,  
图7-49, and 图7-46).  
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7.10.5.7.1 Timing Requirements for eHRPWM  
NO.  
PARAMETER  
DESCRIPTION  
Pulse duration, EHRPWM_SYNCI  
MIN  
2 + 2P(1)  
2 + 3P(1)  
MAX  
UNIT  
ns  
PWM6 tw(synci)  
PWM7 tw(tz)  
Pulse duration, EHRPWM_TZn_IN low  
ns  
(1) P = sysclk  
PWM6  
EHRPWM_SYNCI  
PWM7  
EHRPWM_TZn_IN  
EPERIPHERALS_TIMNG_07  
图7-46. ePWM_SYNCI and ePWM_TZn_IN Output Timings  
For more information, see Camera Subsystem section in Peripherals chapter in the device TRM.  
7.10.5.7.2 Switching Characteristics for eHRPWM  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
P-3(1)  
P-3(1)  
MAX  
UNIT  
PWM1 tw(pwm)  
Pulse duration, EHRPWM_A/B, high or low  
ns  
ns  
ns  
ns  
PWM2 tw(syncout)  
PWM3 td(tzL-pwmV)  
PWM4 td(tzL-pwmZ)  
Pulse duration, EHRPWM_SYNCO  
Delay time, EHRPWM_TZn_IN falling edge to EHRPWM_A/B valid  
Delay time, EHRPWM_TZn_IN falling edge to EHRPWM_A/B Hi-Z  
11  
11  
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NO.  
PARAMETER  
DESCRIPTION  
Pulse duration, EHRPWM_SOCA/B  
MIN  
MAX  
UNIT  
PWM5 tw(soc)  
P-3(1)  
ns  
(1) P = sysclk  
PWM1  
EHRPWM_A/B  
PWM1  
PWM2  
EHRPWM_SYNCO  
PWM5  
EHRPWM_SOCA/B  
EPERIPHERALS_TIMNG_04  
图7-47. EPWM_A/B_out, ePWM_SYNCO, and ePWM_SOCA/B Input Timings  
PWM3  
EPWM_A/B  
EPQM_TZn_IN  
EPERIPHERALS_TIMING_05  
图7-48. EPWM_A/B and ePWM_TZn_IN Forced High/Low Input Timings  
PWM4  
EPWM_A/B  
EPQM_TZn_IN  
EPERIPHERALS_TIMING_06  
图7-49. EPWM_A/B and ePWM_TZn_IN Hi–Z Input Timings  
7.10.5.8 eQEP  
The supported features by the device eQEP are:  
• Input Synchronization  
• Three Stage/Six Stage Digital Noise Filter  
• Quadrature Decoder Unit  
• Position Counter and Control unit for position measurement  
• Quadrature Edge Capture unit for low speed measurement  
• Unit Time base for speed/frequency measurement  
• Watchdog Timer for detecting stalls  
表7-37 represents EQEP timing conditions.  
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表7-37. EQEP Timing Conditions  
PARAMETER  
MIN  
1
MAX  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
4
7
OUTPUT CONDITIONS  
CL  
Output load capacitance  
2
节 7.10.5.8.1 and 节 7.10.5.8.2 present timing requirements and switching characteristics for eQEP (see 图  
7-50).  
7.10.5.8.1 Timing Requirements for eQEP  
NO.  
MIN  
2 + 2P(1)  
2 + 2P(1)  
2 + 2P(1)  
2 + 2P(1)  
2 + 2P(1)  
MAX UNIT  
QEP1  
QEP2  
QEP3  
QEP4  
QEP5  
tw(qep)  
Pulse duration, QEP_A/B  
Pulse duration, QEP_I high  
Pulse duration, QEP_I low  
Pulse duration, QEP_S high  
Pulse duration, QEP_S low  
ns  
ns  
ns  
ns  
ns  
tw(qepiH)  
tw(qepiL)  
tw(qepsH)  
tw(qepsL)  
(1) P = sysclk  
QEP1  
QEP_A/B  
QEP2  
QEP_I  
QEP3  
QEP4  
QEP_S  
QEP5  
EPERIPHERALS_TIMNG_03  
图7-50. eQEP Input Timings  
7.10.5.8.2 Switching Characteristics for eQEP  
NO.  
PARAMETER  
Delay time, external clock to counter increment  
MIN  
MAX UNIT  
QEP6  
td(QEP-CNTR)  
24  
ns  
For more information, see Enhanced Quadrature Encoder Pulse (EQEP) Module section in Peripherals chapter  
in the device TRM.  
7.10.5.9 GPIO  
The device has ten instances of GPIO modules. The GPIO modules are integrated in three groups.  
• Group one: WKUP_GPIO0 and WKUP_GPIO1  
• Group two: GPIO0, GPIO2, GPIO4, and GPIO6  
• Group three: GPIO1, GPIO3, GPIO5, and GPIO7  
Within each group, exactly one module is selected to control the corresponding I/O pins and pin interrupts.  
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The GPIO pins are grouped into banks (16 pins per bank), which means that each GPIO module provides up to  
144 dedicated general-purpose pins with input and output capabilities; thus, the general-purpose interface  
supports up to 432 (3 instances × (9 banks × 16 pins)) pins. Since WKUP_GPIOu_[84:143] (u = 0, 1),  
GPIOn_[128:143] (n = 0, 2, 4, 6), and GPIOm_[36:143] (m = 1, 3, 5 ,7) are reserved in this device, general  
purpose interface supports up to 248 I/O pins.  
For more details about features and additional description information on the device General-Purpose Interface,  
see the corresponding sections within Signal Descriptions and Detailed Description.  
备注  
The general-purpose input/output i (i = 0 to 1) is also referred to as GPIOi.  
表 7-38, 节 7.10.5.9.1, and 节 7.10.5.9.2 present timing conditions, requirements, and switching characteristics  
for GPIO.  
表7-38. GPIO Timing Conditions  
PARAMETER  
BUFFER TYPE  
MIN  
MAX UNIT  
INPUT CONDITIONS  
LVCMOS  
0.2  
0.2  
6.6 V/ns  
0.8 V/ns  
SRI  
Input slew rate  
I2C OD FS  
OUTPUT CONDITIONS  
LVCMOS  
3
3
10  
pF  
pF  
CL  
Output load capacitance  
I2C OD FS  
100  
7.10.5.9.1 GPIO Timing Requirements  
NO.  
BUFFER TYPE  
MIN  
MAX UNIT  
1.8 V  
3.3 V  
2P + 2.6(1)  
2P + 3.4(1)  
ns  
ns  
GPIO1 tw(gpio_in)  
Pulse width, GPIOn_x  
(1) P = functional clock period in ns.  
7.10.5.9.2 GPIO Switching Characteristics  
NO.  
PARAMETER  
BUFFER TYPE  
LVCMOS  
MIN  
MAX UNIT  
–3.6 + 0.975P(1)  
GPIO3 tw(GPIO_OUT)  
GPIO4 tw(GPIO_OUT)  
GPIO5 tw(GPIO_OUT)  
Minimum Output Pulse Width  
Minimum Output Pulse Width Low  
Minimum Output Pulse Width High  
ns  
ns  
ns  
I2C Open Drain  
I2C Open Drain  
160  
60  
(1) P = functional clock period in ns.  
For more information, see General-Purpose Interface (GPIO) section in Peripherals chapter in the device TRM.  
7.10.5.10 GPMC  
For more details about features and additional description information on the device General-Purpose Memory  
Controller, see the corresponding sections within Signal Descriptions and Detailed Description.  
表7-39 represents GPMC timing conditions.  
备注  
The IO timings provided in this section are applicable for all combinations of signals for GPMC0.  
However, the timings are only valid for GPMC0 if signals within a single IOSET are used. The IOSETs  
are defined in the GPMC0_IOSET, GPMC0_IOSET table.  
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表7-39. GPMC Timing Conditions  
PARAMETER  
Input Conditions  
SRI  
DESCRIPTION  
MIN  
MAX  
4
UNIT  
V/ns  
pF  
Input slew rate  
1.65  
5
Output Conditions  
CL  
Output load capacitance  
20  
PCB Connectivity Requirements  
td(Trace Delay)  
Propagation delay of each trace 133 MHz  
140  
140  
360  
ps  
Synchronous Mode  
All other modes  
720  
200  
td(Trace Mismatch Delay)  
Propagation mismatch across all traces  
ps  
7.10.5.10.1 GPMC and NOR Flash —Synchronous Mode  
节 7.10.5.10.1.1 and 节 7.10.5.10.1.2 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see 图7-51 through 图7-55).  
7.10.5.10.1.1 GPMC and NOR Flash Timing Requirements —Synchronous Mode  
MIN  
MAX  
MIN  
MAX  
NO.  
PARAMETER  
DESCRIPTION(2)  
MODE(3)  
UNIT  
100 MHz(4)  
133 MHz(4)  
F12 tsu(dV-clkH)  
F13 th(clkH-dV)  
F21 tsu(waitV-clkH)  
F22 th(clkH-waitV)  
Setup time, input data  
GPMC_AD[15:0] valid before  
output clock GPMC_CLK high  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
1.81  
1.11  
ns  
not_div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
1.06  
1.78  
1.78  
1.81  
1.06  
1.78  
1.78  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Hold time, input data  
GPMC_AD[15:0] valid after  
output clock GPMC_CLK high  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
2.28  
1.11  
2.28  
not_div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
Setup time, input wait  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
GPMC_WAIT[j] valid before  
output clock GPMC_CLK high(1)  
not_div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
Hold time, input wait  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
GPMC_WAIT[j] valid after output  
clock GPMC_CLK high(1)  
not_div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
(1) In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.  
(2) Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see General-  
Purpose Memory Controller (GPMC) section in the device TRM.  
(3) For div_by_1_mode:  
•
•
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:  
– GPMC_CLK frequency = GPMC_FCLK frequency  
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h:  
– GPMC_CLK frequency = GPMC_FCLK frequency / (2 to 4)  
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100 MHz  
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•
For TIMEPARAGRANULARITY_X1:  
– GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/  
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,  
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND,  
TIMEOUTSTARTVALUE, WRDATAONADMUXBUS)  
(4) For 100 MHz:  
•
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = MAIN_PLL2_HSDIV1_CLKOUT / 3  
For 133 MHz:  
•
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = MAIN_PLL0_HSDIV3_CLKOUT  
7.10.5.10.1.2 GPMC and NOR Flash Switching Characteristics –Synchronous Mode  
MIN  
MAX  
MIN  
MAX  
UNI  
T
NO.(2) PARAMETER  
DESCRIPTION  
MODE(19)  
100 MHz(20)  
133 MHz(20)  
F0 tc(clk)  
Period, output clock GPMC_CLK(18)  
div_by_1_mode;  
; GPMC_FCLK_MUX;  
TIMEPARAGRANULA  
RITY_X1  
10  
7.52  
ns  
ns  
ns  
ns  
F1 tw(clkH)  
Typical pulse duration, output clock  
GPMC_CLK high  
div_by_1_mode  
0.475*P  
0.475*P  
; GPMC_FCLK_MUX; (15)- 0.3  
TIMEPARAGRANULA  
RITY_X1  
(15)- 0.3  
F1 tw(clkL)  
Typical pulse duration, output clock  
GPMC_CLK low  
div_by_1_mode  
0.475*P  
0.475*P  
(15)- 0.3  
; GPMC_FCLK_MUX; (15)- 0.3  
TIMEPARAGRANULA  
RITY_X1  
F2 td(clkH-csnV)  
Delay time, output clock GPMC_CLK rising  
edge to output chip select GPMC_CSn[i]  
transition(14)  
div_by_1_mode  
; GPMC_FCLK_MUX;  
TIMEPARAGRANULA  
RITY_X1  
F(6)- 2.2 F+3.75 F(6)- 2.2  
F(6)  
3.75  
+
no extra_delay  
F3 td(clkH-CSn[i]V)  
Delay time, output clock GPMC_CLK rising  
edge to output chip select GPMC_CSn[i]  
invalid(14)  
div_by_1_mode  
; GPMC_FCLK_MUX;  
TIMEPARAGRANULA  
RITY_X1  
E(5)- 2.2  
E(5)  
3.75  
+
E(5)- 2.2  
E(5)  
3.75  
+
ns  
no extra_delay  
F4 td(aV-clk)  
Delay time, output address GPMC_A[27:1]  
div_by_1_mode  
B(2)-2.3 B(2)+4.5 B(2)-2.3 B(2)+4.5 ns  
valid to output clock GPMC_CLK first edge ; GPMC_FCLK_MUX;  
TIMEPARAGRANULA  
RITY_X1  
F5 td(clkH-aIV)  
Delay time, output clock GPMC_CLK rising  
edge to output address GPMC_A[27:1]  
invalid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULA  
RITY_X1  
4.5  
4.5 ns  
–2.3  
–2.3  
F6 td(be[x]nV-clk)  
Delay time, output lower byte enable and  
div_by_1_mode  
B(2)-2.3 B(2)+1.9 B(2)-2.3 B(2)+1.9 ns  
command latch enable GPMC_BE0n_CLE, ; GPMC_FCLK_MUX;  
output upper byte enable GPMC_BE1n  
valid to output clock GPMC_CLK first edge  
TIMEPARAGRANULA  
RITY_X1  
F7 td(clkH-be[x]nIV) Delay time, output clock GPMC_CLK rising  
edge to output lower byte enable and  
div_by_1_mode  
; GPMC_FCLK_MUX;  
D(4)-2.3 D(4)+1.9 D(4)-2.3 D(4)+1.9 ns  
command latch enable GPMC_BE0n_CLE, TIMEPARAGRANULA  
output upper byte enable GPMC_BE1n  
RITY_X1  
invalid(11)  
F7 td(clkL-be[x]nIV)  
Delay time, GPMC_CLK falling edge to  
GPMC_BE0n_CLE, GPMC_BE1n  
invalid(12)  
div_by_1_mode  
; GPMC_FCLK_MUX;  
TIMEPARAGRANULA  
RITY_X1  
D(4)-2.3 D(4)+1.9 D(4)-2.3 D(4)+1.9 ns  
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MIN  
MAX  
MIN  
MAX  
UNI  
T
NO.(2) PARAMETER  
DESCRIPTION  
MODE(19)  
100 MHz(20)  
133 MHz(20)  
F7 td(clkL-be[x]nIV). Delay time, GPMC_CLK falling edge to  
GPMC_BE0n_CLE, GPMC_BE1n  
invalid(13)  
div_by_1_mode  
; GPMC_FCLK_MUX;  
TIMEPARAGRANULA  
RITY_X1  
D(4)-2.3 D(4)+1.9 D(4)-2.3 D(4)+1.9 ns  
F8 td(clkH-advn)  
F9 td(clkH-advnIV)  
F10 td(clkH-oen)  
F11 td(clkH-oenIV)  
F14 td(clkH-wen)  
Delay time, output clock GPMC_CLK rising  
edge to output address valid and address  
latch enable GPMC_ADVn_ALE transition TIMEPARAGRANULA  
div_by_1_mode  
; GPMC_FCLK_MUX;  
G(7)-2.3 G(7)+4.5 G(7)-2.3 G(7)+4.5 ns  
RITY_X1  
no extra_delay  
Delay time, output clock GPMC_CLK rising  
edge to output address valid and address  
latch enable GPMC_ADVn_ALE invalid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULA  
RITY_X1  
D(4)-2.3 D(4)+4.5 D(4)-2.3 D(4)+4.5 ns  
H(8)-2.3 H(8)+3.5 H(8)-2.3 H(8)+3.5 ns  
E(8)-2.3 E(8)+3.5 E(8)-2.3 E(8)+ 3.5 ns  
I(9)- 2.3 I(9)+4.5 I(9)- 2.3 I(9)+4.5 ns  
no extra_delay  
Delay time, output clock GPMC_CLK rising  
edge to output enable GPMC_OEn_REn  
transition  
div_by_1_mode  
; GPMC_FCLK_MUX;  
TIMEPARAGRANULA  
RITY_X1  
no extra_delay  
Delay time, output clock GPMC_CLK rising  
edge to output enable GPMC_OEn_REn  
invalid  
div_by_1_mode  
; GPMC_FCLK_MUX;  
TIMEPARAGRANULA  
RITY_X1  
no extra_delay  
Delay time, output clock GPMC_CLK rising  
edge to output write enable GPMC_WEn  
transition  
div_by_1_mode  
; GPMC_FCLK_MUX;  
TIMEPARAGRANULA  
RITY_X1  
no extra_delay  
F15 td(clkH-do)  
Delay time, output clock GPMC_CLK rising  
edge to output data GPMC_AD[15:0]  
transition(11)  
div_by_1_mode  
; GPMC_FCLK_MUX;  
TIMEPARAGRANULA  
RITY_X1  
J(10)-2.3 J(10)+2.7 J(10)-2.3 J(10)+2.7 ns  
J(10)-2.3 J(10)+2.7 J(10)-2.3 J(10)+2.7 ns  
J(10)-2.3 J(10)+2.7 J(10)-2.3 J(10)+2.7 ns  
J(10)-2.3 J(10)+1.9 J(10)-2.3 J(10)+1.9 ns  
J(10)-2.3 J(10)+1.9 J(10)-2.3 J(10)+1.9 ns  
J(10)-2.3 J(10)+1.9 J(10)-2.3 J(10)+1.9 ns  
F15 td(clkL-do)  
Delay time, GPMC_CLK falling edge to  
GPMC_AD[15:0] data bus transition(12)  
div_by_1_mode  
; GPMC_FCLK_MUX;  
TIMEPARAGRANULA  
RITY_X1  
F15 td(clkL-do).  
F17 td(clkH-be[x]n)  
F17 td(clkL-be[x]n)  
F17 td(clkL-be[x]n).  
Delay time, GPMC_CLK falling edge to  
GPMC_AD[15:0] data bus transition(13)  
div_by_1_mode  
; GPMC_FCLK_MUX;  
TIMEPARAGRANULA  
RITY_X1  
Delay time, output clock GPMC_CLK rising  
edge to output lower byte enable and  
div_by_1_mode  
; GPMC_FCLK_MUX;  
command latch enable GPMC_BE0n_CLE TIMEPARAGRANULA  
transition(11)  
RITY_X1  
Delay time, GPMC_CLK falling edge to  
GPMC_BE0n_CLE, GPMC_BE1n  
transition(12)  
div_by_1_mode  
; GPMC_FCLK_MUX;  
TIMEPARAGRANULA  
RITY_X1  
Delay time, GPMC_CLK falling edge to  
GPMC_BE0n_CLE, GPMC_BE1n  
transition(13)  
div_by_1_mode  
; GPMC_FCLK_MUX;  
TIMEPARAGRANULA  
RITY_X1  
F18 tw(csnV)  
Pulse duration, output chip select  
GPMC_CSn[i] low(14)  
Read  
Write  
Read  
Write  
A(1)  
A(1)  
C(3)  
C(3)  
A(1)  
A(1)  
C(3)  
C(3)  
ns  
ns  
ns  
ns  
F19 tw(be[x]nV)  
Pulse duration, output lower byte enable  
and command latch enable  
GPMC_BE0n_CLE, output upper byte  
enable GPMC_BE1n low  
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MIN  
MAX  
MIN  
MAX  
UNI  
T
NO.(2) PARAMETER  
DESCRIPTION  
MODE(19)  
100 MHz(20)  
K(16)  
133 MHz(20)  
K(16)  
F20 tw(advnV)  
Pulse duration, output address valid and  
address latch enable GPMC_ADVn_ALE  
low  
Read  
Write  
ns  
ns  
K(16)  
K(16)  
(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)  
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)  
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)  
With n being the page burst access number.  
(2) B = ClkActivationTime × GPMC_FCLK(17)  
(3) For single read: C = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(17)  
For burst read: C = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)  
For burst write: C = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)  
With n being the page burst access number.  
(4) For single read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)  
For burst read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)  
For burst write: D = (WrCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)  
(5) For single read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)  
For burst read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)  
For burst write: E = (CSWrOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)  
(6) For csn falling edge (CS activated):  
•
Case GPMCFCLKDIVIDER = 0:  
– F = 0.5 × CSExtraDelay × GPMC_FCLK(17)  
•
Case GPMCFCLKDIVIDER = 1:  
– F = 0.5 × CSExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and  
CSOnTime are even)  
– F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) otherwise  
Case GPMCFCLKDIVIDER = 2:  
•
– F = 0.5 × CSExtraDelay × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime) is a multiple of 3)  
– F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)  
– F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)  
(7) For ADV falling edge (ADV activated):  
•
Case GPMCFCLKDIVIDER = 0:  
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)  
•
Case GPMCFCLKDIVIDER = 1:  
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and  
ADVOnTime are even)  
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise  
Case GPMCFCLKDIVIDER = 2:  
•
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime) is a multiple of 3)  
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3)  
– G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3)  
For ADV rising edge (ADV deactivated) in Reading mode:  
•
Case GPMCFCLKDIVIDER = 0:  
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)  
•
Case GPMCFCLKDIVIDER = 1:  
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and  
ADVRdOffTime are even)  
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise  
Case GPMCFCLKDIVIDER = 2:  
•
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)  
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3)  
– G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3)  
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For ADV rising edge (ADV deactivated) in Writing mode:  
ZHCSRF7 –DECEMBER 2022  
•
Case GPMCFCLKDIVIDER = 0:  
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)  
•
Case GPMCFCLKDIVIDER = 1:  
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and  
ADVWrOffTime are even)  
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise  
Case GPMCFCLKDIVIDER = 2:  
•
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3)  
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3)  
– G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3)  
(8) For OE falling edge (OE activated) and IO DIR rising edge (Data Bus input direction):  
•
Case GPMCFCLKDIVIDER = 0:  
– H = 0.5 × OEExtraDelay × GPMC_FCLK(17)  
•
Case GPMCFCLKDIVIDER = 1:  
– H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and  
OEOnTime are even)  
– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise  
Case GPMCFCLKDIVIDER = 2:  
•
– H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime) is a multiple of 3)  
– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)  
– H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)  
For OE rising edge (OE deactivated):  
•
Case GPMCFCLKDIVIDER = 0:  
– H = 0.5 × OEExtraDelay × GPMC_FCLK(17)  
•
Case GPMCFCLKDIVIDER = 1:  
– H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and  
OEOffTime are even)  
– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise  
Case GPMCFCLKDIVIDER = 2:  
•
– H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime) is a multiple of 3)  
– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)  
– H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)  
(9) For WE falling edge (WE activated):  
•
Case GPMCFCLKDIVIDER = 0:  
– I = 0.5 × WEExtraDelay × GPMC_FCLK(17)  
•
Case GPMCFCLKDIVIDER = 1:  
– I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and  
WEOnTime are even)  
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise  
Case GPMCFCLKDIVIDER = 2:  
•
– I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime) is a multiple of 3)  
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)  
– I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)  
For WE rising edge (WE deactivated):  
•
Case GPMCFCLKDIVIDER = 0:  
– I = 0.5 × WEExtraDelay × GPMC_FCLK (17)  
•
Case GPMCFCLKDIVIDER = 1:  
– I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and  
WEOffTime are even)  
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– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise  
•
Case GPMCFCLKDIVIDER = 2:  
– I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime) is a multiple of 3)  
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)  
– I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)  
(10) J = GPMC_FCLK(17)  
(11) First transfer only for CLK DIV 1 mode.  
(12) Half cycle; for all data after initial transfer for CLK DIV 1 mode.  
(13) Half cycle of GPMC_CLKOUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLKOUT divide down from GPMC_FCLK.  
(14) In GPMC_CSn[i], i is equal to 0, 1, 2, or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.  
(15) P = GPMC_CLK period in ns  
(16) For read: K = (ADVRdOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)  
For write: K = (ADVWrOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)  
(17) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.  
(18) Related to the GPMC_CLK output clock maximum and minimum frequencies programmable in the GPMC module by setting the  
GPMC_CONFIG1_i configuration register bit field GPMCFCLKDIVIDER.  
(19) For div_by_1_mode:  
•
GPMC_CONFIG1_i register: GPMCFCLKDIVIDER = 0h:  
– GPMC_CLK frequency = GPMC_FCLK frequency  
•
•
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100 MHz  
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/  
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,  
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,  
WRDATAONADMUXBUS)  
For no extra_delay:  
•
•
•
•
GPMC_CONFIG2_i Register: CSEXTRADELAY = 0h = CSn Timing control signal is not delayed  
GPMC_CONFIG4_i Register: WEEXTRADELAY = 0h = nWE timing control signal is not delayed  
GPMC_CONFIG4_i Register: OEEXTRADELAY = 0h = nOE timing control signal is not delayed  
GPMC_CONFIG3_i Register: ADVEXTRADELAY = 0h = nADV timing control signal is not delayed  
(20) For 100 MHz:  
•
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = MAIN_PLL2_HSDIV1_CLKOUT / 3  
For 133 MHz:  
•
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = MAIN_PLL0_HSDIV3_CLKOUT  
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F1  
F0  
F1  
GPMC_CLK  
F2  
F3  
F18  
GPMC_CSn[i]  
F4  
F6  
GPMC_A[MSB:1]  
Valid Address  
F19  
F7  
GPMC_BE0n_CLE  
GPMC_BE1n  
F19  
F6  
F8  
F8  
F20  
F9  
GPMC_ADVn_ALE  
GPMC_OEn_REn  
F10  
F11  
F13  
F12  
D 0  
GPMC_AD[15:0]  
GPMC_WAIT[j]  
GPMC_01  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.  
B. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.  
图7-51. GPMC and NOR Flash —Synchronous Single Read (GPMCFCLKDIVIDER = 0)  
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F1  
F0  
F1  
GPMC_CLK  
F2  
F3  
GPMC_CSn[i]  
F4  
GPMCA[MSB:1]  
Valid Address  
F6  
F7  
F7  
GPMC_BE0n_CLE  
GPMC_BE1n  
F6  
F8  
F8  
F9  
GPMC_ADVn_ALE  
GPMC_OEn_REn  
F10  
F11  
F13  
F13  
F12  
F12  
D 0  
GPMC_AD[15:0]  
D 1  
D 2  
D 3  
F21  
F21  
F22  
F22  
GPMC_WAIT[j]  
GPMC_02  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.  
B. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.  
图7-52. GPMC and NOR Flash —Synchronous Burst Read —4x16–bit (GPMCFCLKDIVIDER = 0)  
F1  
F1  
F0  
GPMC_CLK  
GPMC_CSn[i]  
F2  
F3  
F4  
F6  
Valid Address  
GPMC_A[MSB:1]  
F17  
F17  
F17  
F17  
F17  
F17  
GPMC_BE0n_CLE  
GPMC_BE1n  
F6  
F8  
F8  
F9  
GPMC_ADVn_ALE  
GPMC_WEn  
F14  
F14  
F15  
D 1  
F15  
D 2  
F15  
GPMC_AD[15:0]  
GPMC_WAIT[j]  
D 0  
D 3  
GPMC_03  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.  
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B. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.  
图7-53. GPMC and NOR Flash—Synchronous Burst Write (GPMCFCLKDIVIDER = 0)  
F1  
F0  
F1  
GPMC_CLK  
F2  
F3  
GPMC_CSn[i]  
F6  
F7  
GMPC_BE0n_CLE  
Valid  
F6  
F7  
Valid  
GPMC_BE1n  
F4  
GPMC_A[27:17]  
Address (MSB)  
F5  
F12  
F13  
F4  
Address (LSB)  
F12  
GPMC_AD[15:0]  
D0  
D1  
D2  
D3  
F8  
F8  
F9  
GPMC_ADVn_ALE  
F10  
F11  
GPMC_OEn_REn  
GPMC_WAIT[j]  
GPMC_04  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.  
B. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.  
图7-54. GPMC and Multiplexed NOR Flash —Synchronous Burst Read  
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F1  
F1  
F0  
GPMC_CLK  
F2  
F3  
F18  
GPMC_CSn[i]  
F4  
GPMC_A[27:17]  
Address (MSB)  
F17  
F17  
F6  
F17  
F17  
F17  
F17  
GPMC_BE1n  
F6  
BPMC_BE0n_CLE  
F8  
F8  
F20  
F9  
GPMC_ADVn_ALE  
GPMC_WEn  
F14  
F14  
F15  
D 1  
F15  
D 2  
F15  
GPMC_AD[15:0]  
GPMC_WAIT[j]  
Address (LSB)  
D 0  
F22  
D 3  
F21  
F22  
F21  
GPMC_05  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.  
B. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.  
图7-55. GPMC and Multiplexed NOR Flash —Synchronous Burst Write  
7.10.5.10.2 GPMC and NOR Flash —Asynchronous Mode  
节 7.10.5.10.2.1 and 节 7.10.5.10.2.2 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see 图7-56 through 图7-61).  
7.10.5.10.2.1 GPMC and NOR Flash Timing Requirements –Asynchronous Mode  
NO.  
MODE(7)  
MIN  
MAX UNIT  
FA5(1) tacc(d)  
Data access time  
div_by_1_mode  
; GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X  
1
H(5) ns  
FA20(2) tacc1-pgmode(d)  
Page mode successive data access time  
Page mode first data access time  
div_by_1_mode  
; GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X  
1
P(4) ns  
FA21(3) tacc2-pgmode(d)  
div_by_1_mode  
; GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X  
1
H(5) ns  
(1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC  
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active  
functional clock edge. FA5 value must be stored inside the AccessTime register bit field.  
(2) The FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of  
GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional  
clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.  
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(3) The FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC  
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by  
active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.  
(4) P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(6)  
(5) H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(6)  
(6) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.  
(7) For div_by_1_mode:  
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:  
– GPMC_CLK frequency = GPMC_FCLK frequency  
•
•
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz  
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/  
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,  
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,  
WRDATAONADMUXBUS)  
7.10.5.10.2.2 GPMC and NOR Flash Switching Characteristics –Asynchronous Mode  
MIN  
MAX  
NO. PARAMETER  
DESCRIPTION  
MODE(15)  
UNIT  
133 MHz(16)  
FA0 tw(be[x]nV)  
Pulse duration, output lower-byte enable and  
command latch enable GPMC_BE0n_CLE, output  
upper-byte enable GPMC_BE1n valid time  
Read  
Write  
N(12) ns  
N(12)  
FA1 tw(csnV)  
Pulse duration, output chip select GPMC_CSn[i](13)  
low  
Read  
Write  
Read  
Write  
A(1) ns  
A(1)  
FA3 td(csnV-advnIV)  
Delay time, output chip select GPMC_CSn[i](13)  
valid to output address valid and address latch  
enable GPMC_ADVn_ALE invalid  
B(2)- 2.55 B(2)+ 2.65 ns  
B(2)- 2.55 B(2)+ 2.65  
FA4 td(csnV-oenIV)  
Delay time, output chip select GPMC_CSn[i](13)  
valid to output enable GPMC_OEn_REn invalid  
(Single read)  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_  
X1  
ns  
C(3)- 2.55 C(3)+ 2.65  
FA9 td(aV-csnV)  
Delay time, output address GPMC_A[27:1] valid to  
output chip select GPMC_CSn[i](13) valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_  
X1  
ns  
J(9)- 2.55 J(9)+ 2.65  
FA10 td(be[x]nV-csnV)  
FA12 td(csnV-advnV)  
FA13 td(csnV-oenV)  
FA16 tw(aIV)  
Delay time, output lower-byte enable and  
command latch enable GPMC_BE0n_CLE, output  
upper-byte enable GPMC_BE1n valid to output  
chip select GPMC_CSn[i](13) valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_  
X1  
ns  
J(9)- 2.55 J(9)+ 2.65  
Delay time, output chip select GPMC_CSn[i](13)  
valid to output address valid and address latch  
enable GPMC_ADVn_ALE valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_  
X1  
ns  
K(10)  
2.65  
+
K(10)- 2.55  
L(11)- 2.55  
G(7)  
Delay time, output chip select GPMC_CSn[i](13)  
valid to output enable GPMC_OEn_REn valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_  
X1  
ns  
ns  
ns  
L(11)  
+
2.65  
Pulse duration output address GPMC_A[26:1]  
invalid between 2 successive read and write  
accesses  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_  
X1  
FA18 td(csnV-oenIV)  
Delay time, output chip select GPMC_CSn[i](13)  
valid to output enable GPMC_OEn_REn invalid  
(Burst read)  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_  
X1  
I(8)- 2.55 I(8)+ 2.65  
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MIN  
MAX  
UNIT  
NO. PARAMETER  
DESCRIPTION  
MODE(15)  
133 MHz(16)  
FA20 tw(aV)  
Pulse duration, output address GPMC_A[27:1]  
valid - 2nd, 3rd, and 4th accesses  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_  
X1  
ns  
D(4)  
FA25 td(csnV-wenV)  
FA27 td(csnV-wenIV)  
FA28 td(wenV-dV)  
FA29 td(dV-csnV)  
FA37 td(oenV-aIV)  
Delay time, output chip select GPMC_CSn[i](13)  
valid to output write enable GPMC_WEn valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_  
X1  
ns  
E(5)- 2.55 E(5)+ 2.65  
F(6)- 2.55 F(6)+ 2.65  
2.65  
Delay time, output chip select GPMC_CSn[i](13)  
valid to output write enable GPMC_WEn invalid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_  
X1  
ns  
ns  
ns  
ns  
Delay time, output write enable GPMC_WEn valid  
to output data GPMC_AD[15:0] valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_  
X1  
Delay time, output data GPMC_AD[15:0] valid to  
output chip select GPMC_CSn[i](13) valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_  
X1  
J(9)- 2.55 J(9)+ 2.65  
Delay time, output enable GPMC_OEn_REn valid  
to output address GPMC_AD[15:0] phase end  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_  
X1  
2.65  
(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
For single write: A = (CSWrOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
with n being the page burst access number  
(2) For reading: B = ((ADVRdOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×  
GPMC_FCLK(14)  
For writing: B = ((ADVWrOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×  
GPMC_FCLK(14)  
(3) C = ((OEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)  
(4) D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
(5) E = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)  
(6) F = ((WEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)  
(7) G = Cycle2CycleDelay × GPMC_FCLK(14)  
(8) I = ((OEOffTime + (n - 1) × PageBurstAccessTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay))  
× GPMC_FCLK(14)  
(9) J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK(14)  
(10) K = ((ADVOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)  
(11) L = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)  
(12) For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
For burst read: N = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
For burst write: N = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
(13) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.  
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.  
(15) For div_by_1_mode:  
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:  
– GPMC_CLK frequency = GPMC_FCLK frequency  
•
•
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz  
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/  
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,  
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,  
WRDATAONADMUXBUS)  
(16) For 133 MHz:  
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•
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = MAIN_PLL0_HSDIV3_CLKOUT  
GPMC_FCLK  
GPMC_CLK  
FA5  
FA1  
GPMC_CSn[i]  
FA9  
GPMC_A[MSB:1]  
Valid Address  
FA0  
FA10  
Valid  
FA0  
GPMC_BE0n_CLE  
GPMC_BE1n  
Valid  
FA10  
FA3  
FA12  
GPMC_ADVn_ALE  
FA4  
FA13  
GPMC_OEn_REn  
GPMC_AD[15:0]  
Data IN 0  
Data IN 0  
GPMC_WAIT[j]  
GPMC_06  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.  
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock  
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock  
edge. FA5 value must be stored inside AccessTime register bits field.  
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
图7-56. GPMC and NOR Flash —Asynchronous Read —Single Word  
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GPMC_FCLK  
GPMC_CLK  
FA5  
FA5  
FA1  
FA1  
GPMC_CSn[i]  
FA16  
FA9  
FA9  
Address 0  
FA0  
Address 1  
FA0  
GPMC_A[MSB:1]  
FA10  
FA10  
Valid  
FA0  
Valid  
FA0  
GPMC_BE0n_CLE  
GPMC_BE1n  
Valid  
Valid  
FA10  
FA10  
FA3  
FA3  
FA12  
FA12  
GPMC_ADCn_ALE  
FA4  
FA4  
FA13  
FA13  
GPMC_OEn_REn  
GPMC_AD[15:0]  
Data Upper  
GPMC_WAIT[j]  
GPMC_07  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.  
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock  
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock  
edge. FA5 value must be stored inside AccessTime register bits field.  
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
图7-57. GPMC and NOR Flash —Asynchronous Read —32–Bit  
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GPMC_FCLK  
GPMC_CLK  
FA20  
FA20  
FA20  
Add1  
FA21  
FA1  
GPMC_CSn[i]  
FA9  
Add0  
Add2  
Add3  
Add4  
GPMC_A[MSB:1]  
FA0  
FA10  
FA10  
GPMC_BE0n_CLE  
FA0  
GPMC_BE1n  
FA12  
GPMC_ADVn_ALE  
FA18  
FA13  
GPMC_OEn_REn  
GPMC_AD[15:0]  
D3  
D0  
D1  
D2  
D3  
GPMC_WAIT[j]  
GPMC_08  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.  
B. FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC  
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data will be internally sampled by  
active functional clock edge. FA21 calculation must be stored inside AccessTime register bits field.  
C. FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC  
functional clock cycles. After each access to input page data, next input page data will be internally sampled by active functional clock  
edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first  
input page data). FA20 value must be stored in PageBurstAccessTime register bits field.  
D. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
图7-58. GPMC and NOR Flash —Asynchronous Read —Page Mode 4x16–Bit  
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GPMC_FCLK  
GPMC_CLK  
FA1  
GPMC_CSn[i]  
FA9  
GPMC_A[MSB:1]  
Valid Address  
FA0  
FA10  
GPMC_BE0n_CLE  
FA0  
FA10  
GPMC_BE1n  
FA3  
FA12  
GPMC_ADVn_ALE  
FA27  
FA25  
GPMC_WEn  
FA29  
GPMC_AD[15:0]  
GPMC_WAIT[j]  
Data OUT  
GPMC_09  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.  
图7-59. GPMC and NOR Flash —Asynchronous Write —Single Word  
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GPMC_FCLK  
GPMC_CLK  
FA1  
FA5  
GPMC_CSn[i]  
FA9  
Address (MSB)  
FA0  
GPMC_A[27:17]  
FA10  
FA10  
GPMC_BE0n_CLE  
GPMC_BE1n  
Valid  
FA0  
Valid  
FA3  
FA12  
GPMC_ADVn_ALE  
GPMC_OEn_REn  
FA4  
FA13  
FA29  
FA37  
Data IN  
Data IN  
Address (LSB)  
GPMC_AD[15:0]  
GPMC_WAIT[j]  
GPMC_10  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.  
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock  
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock  
edge. FA5 value must be stored inside AccessTime register bits field.  
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
图7-60. GPMC and Multiplexed NOR Flash —Asynchronous Read —Single Word  
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GPMC_FCLK  
GPMC_CLK  
FA1  
GPMC_CSn[i]  
FA9  
GPMC_A[27:17]  
Address (MSB)  
FA0  
FA10  
GPMC_BE0n_CLE  
FA0  
FA10  
GPMC_BE1n  
FA3  
FA12  
GPMC_ADVn_ALE  
FA27  
FA25  
GPMC_WEn  
FA29  
Valid Address (LSB)  
FA28  
GPMC_AD[15:0]  
Data OUT  
GPMC_WAIT[j]  
GPMC_11  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.  
图7-61. GPMC and Multiplexed NOR Flash —Asynchronous Write —Single Word  
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7.10.5.10.3 GPMC and NAND Flash —Asynchronous Mode  
节 7.10.5.10.3.1 and 节 7.10.5.10.3.2 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see 图7-62 through 图7-65).  
7.10.5.10.3.1 GPMC and NAND Flash Timing Requirements –Asynchronous Mode  
MIN  
MAX  
NO.  
MODE(4)  
UNIT  
133 MHz(5)  
div_by_1_mode;  
Access time, input data GPMC_AD[15:0](3) GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
GNF12(1)  
tacc(d)  
J(2)  
ns  
(1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC  
functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the  
active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.  
(2) J = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(3)  
(3) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.  
(4) For div_by_1_mode:  
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:  
– GPMC_CLK frequency = GPMC_FCLK frequency  
•
•
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz  
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/  
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,  
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,  
WRDATAONADMUXBUS)  
(5) For 133 MHz:  
•
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = MAIN_PLL0_HSDIV3_CLKOUT  
7.10.5.10.3.2 GPMC and NAND Flash Switching Characteristics –Asynchronous Mode  
MIN  
MAX  
NO.  
PARAMETER  
MODE(15)  
UNIT  
133 MHz(16)  
A(1)  
GNF0 tw(wenV)  
Pulse duration, output write enable GPMC_WEn  
valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_  
X1  
ns  
GNF1 td(csnV-wenV)  
GNF2 tw(cleH-wenV)  
GNF3 tw(wenV-dV)  
GNF4 tw(wenIV-dIV)  
GNF5 tw(wenIV-cleIV)  
Delay time, output chip select GPMC_CSn[i](13)  
valid to output write enable GPMC_WEn valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_  
X1  
B(2) - 2.55  
B(2)  
2.65  
+
ns  
ns  
ns  
ns  
Delay time, output lower-byte enable and  
command latch enable GPMC_BE0n_CLE high to  
output write enable GPMC_WEn valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_  
X1  
C(3) - 2.55  
D(4) - 2.55  
E(5) - 2.55  
C(3)  
2.65  
+
Delay time, output data GPMC_AD[15:0] valid to  
output write enable GPMC_WEn valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_  
X1  
D(4)  
2.65  
+
Delay time, output write enable GPMC_WEn  
invalid to output data GPMC_AD[15:0] invalid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_  
X1  
E(5)  
2.65  
+
Delay time, output write enable GPMC_WEn  
invalid to output lower-byte enable and command  
latch enable GPMC_BE0n_CLE invalid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_  
X1  
F(6) - 2.55 F(6)+ 2.65 ns  
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MIN  
133 MHz(16)  
G(7) - 2.55  
MAX  
UNIT  
NO.  
PARAMETER  
MODE(15)  
GNF6 tw(wenIV-CSn[i]V) Delay time, output write enable GPMC_WEn  
invalid to output chip select GPMC_CSn[i](13)  
invalid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_  
X1  
G(7)  
2.65  
+
ns  
GNF7 tw(aleH-wenV)  
GNF8 tw(wenIV-aleIV)  
GNF9 tc(wen)  
Delay time, output address valid and address latch  
enable GPMC_ADVn_ALE high to output write  
enable GPMC_WEn valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_  
X1  
C(3) - 2.55  
C(3)  
2.65  
+
ns  
Delay time, output write enable GPMC_WEn  
invalid to output address valid and address latch  
enable GPMC_ADVn_ALE invalid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_  
X1  
F(6) - 2.55 F(6)+ 2.65 ns  
Cycle time, write  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_  
X1  
H(8) ns  
GNF10 td(csnV-oenV)  
Delay time, output chip select GPMC_CSn[i](13)  
valid to output enable GPMC_OEn_REn valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_  
X1  
I(9) - 2.55 I(9)+ 2.65 ns  
GNF13 tw(oenV)  
Pulse duration, output enable GPMC_OEn_REn  
valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_  
X1  
K(10) ns  
GNF14 tc(oen)  
Cycle time, read  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_  
X1  
L(11)  
ns  
ns  
GNF15 tw(oenIV-CSn[i]V) Delay time, output enable GPMC_OEn_REn  
invalid to output chip select GPMC_CSn[i](13)  
invalid  
div_by_1_mode;  
M(12) - 2.55  
M(12)  
2.65  
+
(1) A = (WEOffTime - WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
(2) B = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)  
(3) C = ((WEOnTime - ADVOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - ADVExtraDelay)) × GPMC_FCLK(14)  
(4) D = (WEOnTime × (TimeParaGranularity + 1) + 0.5 × WEExtraDelay) × GPMC_FCLK(14)  
(5) E = ((WrCycleTime - WEOffTime) × (TimeParaGranularity + 1) - 0.5 × WEExtraDelay) × GPMC_FCLK(14)  
(6) F = ((ADVWrOffTime - WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - WEExtraDelay)) × GPMC_FCLK(14)  
(7) G = ((CSWrOffTime - WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay - WEExtraDelay)) × GPMC_FCLK(14)  
(8) H = WrCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK(14)  
(9) I = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)  
(10) K = (OEOffTime - OEOnTime) × (1 + TimeParaGranularity) × GPMC_FCLK(14)  
(11) L = RdCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK(14)  
(12) M = ((CSRdOffTime - OEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay - OEExtraDelay)) × GPMC_FCLK(14)  
(13) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.  
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.  
(15) For div_by_1_mode:  
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:  
– GPMC_CLK frequency = GPMC_FCLK frequency  
For GPMC_FCLK_MUX:  
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz  
For TIMEPARAGRANULARITY_X1:  
•
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/  
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,  
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,  
WRDATAONADMUXBUS)  
(16) For 133 MHz:  
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•
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = MAIN_PLL0_HSDIV3_CLKOUT  
GPMC_FCLK  
GNF1  
GNF2  
GNF6  
GNF5  
GPMC_CSn[i]  
GPMC_BE0n_CLE  
GPMC_ADCn_ALE  
GPMC_OEn_REn  
GPMC_WEn  
GNF0  
GNF3  
GNF4  
GPMC_AD[15:0]  
Command  
GPMC_12  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.  
图7-62. GPMC and NAND Flash —Command Latch Cycle  
GPMC_FCLK  
GPMC_CSn[i]  
GNF1  
GNF6  
GPMC_BE0n_CLE  
GPMC_ADVn_ALE  
GNF7  
GNF8  
GPMC_OEn_REn  
GPMC_WEn  
GNF9  
GNF0  
GNF3  
GNF4  
Address  
GPMC_AD[15:0]  
GPMC_13  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.  
图7-63. GPMC and NAND Flash —Address Latch Cycle  
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GPMC_FCLK  
GNF12  
GNF10  
GNF15  
GPMC_CSn[i]  
GPMC_BE0n_CLE  
GPMC_ADVn_ALE  
GNF14  
GNF13  
GPMC_OEn_REn  
GPMC_AD[15:0]  
GPMC_WAIT[j]  
DATA  
GPMC_14  
A. GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional  
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional  
clock edge. GNF12 value must be stored inside AccessTime register bits field.  
B. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
C. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.  
图7-64. GPMC and NAND Flash —Data Read Cycle  
GPMC_FCLK  
GNF1  
GNF6  
GPMC_CSn[i]  
GPMC_BE0n_CLE  
GPMC_ADVn_ALE  
GPMC_OEn_REn  
GNF9  
GNF0  
GPMC_WEn  
GNF3  
GNF4  
GPMC_AD[15:0]  
DATA  
GPMC_15  
A. `In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.  
图7-65. GPMC and NAND Flash —Data Write Cycle  
For more information, see Enhanced Pulse Width Modulation (EPWM) Module section in Peripherals chapter in  
the device TRM.  
7.10.5.10.4 GPMC0 IOSET  
表7-40 present the specific groupings of signals (IOSET) for use with GPMC0.  
表7-40. GPMC0 IOSET  
Signals  
IOSET1  
IOSET2  
BALL NAME  
MUX  
BALL NAME  
MDIO0_MDC  
RGMII6_RD1  
MUX  
GPMC0_WAIT2  
GPMC0_BE1n  
MDIO0_MDC  
8
8
8
8
PRG1_PRU0_GPO0  
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表7-40. GPMC0 IOSET (continued)  
Signals  
IOSET1  
IOSET2  
BALL NAME  
MUX  
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
BALL NAME  
MUX  
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
GPMC0_WAIT0  
GPMC0_WAIT1  
GPMC0_DIR  
GPMC0_CSn2  
GPMC0_WEn  
GPMC0_CSn3  
GPMC0_OEn_REn  
GPMC0_ADVn_ALE  
GPMC0_BE0n_CLE  
GPMC0_WPn  
GPMC0_CSn1  
GPMC0_CSn0  
GPMC0_CLKOUT  
GPMC0_AD0  
GPMC0_AD1  
GPMC0_AD2  
GPMC0_AD3  
GPMC0_AD4  
GPMC0_AD5  
GPMC0_AD6  
GPMC0_AD7  
GPMC0_AD8  
GPMC0_AD9  
GPMC0_AD10  
GPMC0_AD11  
GPMC0_AD12  
GPMC0_AD13  
GPMC0_AD14  
GPMC0_AD15  
GPMC0_A0  
PRG1_PRU0_GPO1  
PRG1_PRU0_GPO2  
PRG1_PRU0_GPO3  
PRG1_PRU0_GPO4  
PRG1_PRU0_GPO5  
PRG1_PRU0_GPO6  
PRG1_PRU0_GPO8  
PRG1_PRU0_GPO9  
PRG1_PRU0_GPO10  
PRG1_PRU1_GPO5  
PRG1_PRU1_GPO8  
PRG1_PRU1_GPO9  
PRG1_PRU1_GPO10  
PRG0_PRU0_GPO5  
PRG0_PRU0_GPO7  
PRG0_PRU0_GPO8  
PRG0_PRU0_GPO9  
PRG0_PRU0_GPO10  
PRG0_PRU0_GPO17  
PRG0_PRU0_GPO18  
PRG0_PRU0_GPO19  
PRG0_PRU1_GPO5  
PRG0_PRU1_GPO7  
PRG0_PRU1_GPO8  
PRG0_PRU1_GPO9  
PRG0_PRU1_GPO10  
PRG0_PRU1_GPO17  
PRG0_PRU1_GPO18  
PRG0_PRU1_GPO19  
PRG0_MDIO0_MDC  
RGMII5_TX_CTL  
PRG1_PRU0_GPO1  
PRG1_PRU0_GPO2  
PRG1_PRU0_GPO3  
PRG1_PRU0_GPO4  
PRG1_PRU0_GPO5  
PRG1_PRU0_GPO6  
PRG1_PRU0_GPO8  
PRG1_PRU0_GPO9  
PRG1_PRU0_GPO10  
PRG1_PRU1_GPO5  
PRG1_PRU1_GPO8  
PRG1_PRU1_GPO9  
PRG1_PRU1_GPO10  
PRG0_PRU0_GPO5  
PRG0_PRU0_GPO7  
PRG0_PRU0_GPO8  
PRG0_PRU0_GPO9  
PRG0_PRU0_GPO10  
PRG0_PRU0_GPO17  
PRG0_PRU0_GPO18  
PRG0_PRU0_GPO19  
PRG0_PRU1_GPO5  
PRG0_PRU1_GPO7  
PRG0_PRU1_GPO8  
PRG0_PRU1_GPO9  
PRG0_PRU1_GPO10  
PRG0_PRU1_GPO17  
PRG0_PRU1_GPO18  
PRG0_PRU1_GPO19  
PRG0_MDIO0_MDC  
RGMII5_TX_CTL  
GPMC0_A1  
GPMC0_A2  
RGMII5_RX_CTL  
RGMII5_TD3  
RGMII5_RX_CTL  
RGMII5_TD3  
GPMC0_A3  
GPMC0_A4  
RGMII5_TD2  
RGMII5_TD2  
GPMC0_A5  
RGMII5_TD1  
RGMII5_TD1  
GPMC0_A6  
RGMII5_TD0  
RGMII5_TD0  
GPMC0_A7  
RGMII5_TXC  
RGMII5_TXC  
GPMC0_A8  
RGMII5_RXC  
RGMII5_RXC  
GPMC0_A9  
RGMII5_RD3  
RGMII5_RD3  
GPMC0_A10  
GPMC0_A11  
GPMC0_A12  
GPMC0_A13  
GPMC0_A14  
RGMII5_RD2  
RGMII5_RD2  
RGMII5_RD1  
RGMII5_RD1  
RGMII5_RD0  
RGMII5_RD0  
RGMII6_TX_CTL  
RGMII6_TX_CTL  
RGMII6_RX_CTL  
RGMII6_RX_CTL  
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表7-40. GPMC0 IOSET (continued)  
Signals  
IOSET1  
IOSET2  
BALL NAME  
RGMII6_TD3  
MUX  
8
BALL NAME  
MUX  
GPMC0_A15  
GPMC0_A16  
GPMC0_A17  
GPMC0_A18  
GPMC0_A19  
GPMC0_A20  
GPMC0_A21  
GPMC0_A22  
GPMC0_A23  
GPMC0_A24  
GPMC0_A25  
GPMC0_A26  
GPMC0_A27  
GPMC0_WAIT3  
RGMII6_TD3  
RGMII6_TD2  
RGMII6_TD1  
RGMII6_TD0  
RGMII6_TXC  
RGMII6_RXC  
RGMII6_RD3  
RGMII6_RD2  
8
8
8
8
8
8
8
8
8
8
8
8
8
8
RGMII6_TD2  
RGMII6_TD1  
8
8
RGMII6_TD0  
8
RGMII6_TXC  
8
RGMII6_RXC  
8
RGMII6_RD3  
8
RGMII6_RD2  
8
PRG0_PRU1_GPO2  
PRG0_PRU1_GPO4  
PRG0_PRU1_GPO6  
PRG0_PRU1_GPO11  
PRG0_MDIO0_MDIO  
MDIO0_MDIO  
8
PRG0_PRU1_GPO2  
PRG0_PRU1_GPO4  
PRG0_PRU1_GPO6  
PRG0_PRU1_GPO11  
PRG0_MDIO0_MDIO  
MDIO0_MDIO  
8
8
8
8
8
7.10.5.11 HyperBus  
For more details about features and additional description information on the device HyperBus, see the  
corresponding sections within Signal Descriptions and Detailed Description.  
节 7.10.5.11, 节 7.10.5.11.2, and 节 7.10.5.11.3 assume testing over the recommended operating conditions and  
electrical characteristic conditions (see 图7-66, 图7-67, and 图7-68).  
表7-41 represents HyperBus timing conditions.  
表7-41. HyperBus Timing Conditions  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
INPUT CONDITIONS  
SRI  
Input slew rate  
2
5
V/ns  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
7.10.5.11.1 Timing Requirements for HyperBus  
NO.  
D1  
D2  
D3  
D4  
PARAMETER  
tw(RESETn)  
DESCRIPTION  
MIN  
MAX  
UNIT  
Pulse width, RESETn  
200  
1000  
ns  
ns  
ns  
ns  
tw(csL)  
Pulse width, Chip Select  
td(RESETnH-csL)  
td(csL-RWDSL)  
Delay time, RESETn inactive to CSn active  
Delay time, CSn active to RWDS falling  
200.34  
115  
7.10.5.11.2 HyperBus 166 MHz Switching Characteristics  
NO.  
D5  
PARAMETER  
tskn(rwdsX-dV)  
DESCRIPTION  
Input skew, RWDS transitioning to D0:D7 valid  
CLK period, CLK/CLKn  
MIN  
-0.46  
6
MAX  
UNIT  
ns  
0.46  
D6  
tc(clk/clkn)  
tw(clk/clkn)  
tw(csIV)  
ns  
D7  
Pulse width, CLK/CLKn  
2.7  
6
ns  
D8  
Pulse width, CS0 invalid between operations  
Delay time, CS0 active to CLK rising/ CLKn falling  
Delay time, last falling CLK/ rising CLKn edge to CS0 inactive  
ns  
D9  
td(clkH-csL)  
td(clkL[LE]-csH)  
-3.34  
ns  
D10  
0.41  
ns  
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PARAMETER  
DESCRIPTION  
Delay time, CLK transition to RWDS valid  
Delay time, CLK transitioning to D0:D7 valid  
MIN  
1.01  
0.84  
MAX  
2.08  
2.17  
UNIT  
ns  
D11  
D12  
td(clkX-rwdsV)  
td(clkX-d[0:7]V)  
ns  
7.10.5.11.3 HyperBus 100 MHz Switching Characteristics  
NO.  
PARAMETER  
tskn(rwdsX-dV)  
DESCRIPTION  
Input skew, RWDS transitioning to D0:D7 valid  
CLK period, CLK  
MIN  
-0.81  
10  
MAX  
UNIT  
ns  
LFD5  
LFD6  
LFD7  
LFD8  
LFD9  
0.81  
tc(clk)  
ns  
tw(clk)  
Pulse width, CLK  
4.75  
10  
ns  
tw(csIV)  
td(clkH-csL)  
Pulse width, CS0 invalid between operations  
Delay time, CS0 active to CLK rising  
Delay time, last falling CLK edge to CS0 inactive  
Delay time, CLK transition to RWDS valid  
Delay time, CLK transitioning to D0:D7 valid  
ns  
-3.51  
ns  
LFD10 td(clkL[LE]-csH)  
LFD11 td(clkX-rwdsV)  
LFD12 td(clkX-d[0:7]V)  
0.51  
1.51  
1.34  
ns  
3.49  
3.66  
ns  
ns  
D8/LFD8  
D2  
CSn  
D9/LFD9  
D10/LFD10  
CK, CKn  
D7/LFD7  
D6/LFD6  
D4  
D11/LFD11  
RWDS  
D12/LFD12  
Dn Dn+1 Dn+1  
D12/LFD12  
Dn  
A
39:32 31:24 23:16  
7:0  
47:40  
15:8  
DQ[7:0]  
B
A
B
CK and Data are center aligned  
Command-Address  
Host drives DQ[7:0] and Memory drives RWDS  
Host drives DQ[7:0] and RWDS  
HYPERBUS_TIMING_01  
图7-66. HyperBus Timing Diagrams –Transmitter Mode  
D8/LFD8  
D2  
CSn  
D9/LFD9  
D10/LFD10  
CK, CKn  
D7/LFD7  
D4  
D6/LFD6  
RWDS  
D5/LFD5  
D12/LFD12  
D5/LFD5  
Dn+1 Dn+1  
Dn  
A
Dn  
B
39:32 31:24 23:16  
7:0  
47:40  
15:8  
DQ[7:0]  
A
B
CK and Data are center aligned  
Command-Address  
Host drives DQ[7:0] and Memory drives RWDS  
Host drives DQ[7:0] and RWDS  
HYPERBUS_TIMING_02  
图7-67. HyperBus Timing Diagrams –Receiver Mode  
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D1  
RESETn  
CSn  
D3  
HYPERBUS_TIMING_03  
图7-68. HyperBus Timing Diagrams –Reset  
For more information, see HyperBus Interface section in Peripherals chapter in the device TRM.  
7.10.5.12 I2C  
The device contains several multicontroller Inter-Integrated Circuit (I2C) controllers. Each I2C controller was  
designed to be compliant to the Philips I2C-bus™ specification version 2.1. However, the device IO Buffers are  
not fully compliant to the I2C electrical specification. Some I2C instances use the LVCMOS Buffer Type, while  
other instances use the I2S OD FS Buffer type. See the Pin Attributes table to determine the IO Buffer  
Type used for each I2C instance on this device. The I2C speeds supported and exceptions are described per  
IO Buffer Type below:  
• I2C instances that use the LVCMOS buffer type  
– Speeds:  
• Standard-mode (up to 100 Kbits/s)  
– 1.8 V  
– 3.3 V  
• Fast-mode (up to 400 Kbits/s)  
– 1.8 V  
– 3.3 V  
– Exceptions:  
• The IOs associated with these ports are not compliant to the fall time requirements defined in the I2C  
specification because they are implemented with higher performance LVCMOS push-pull IOs that were  
designed to support other signal functions that could not be implemented with I2C compatible IOs. The  
LVCMOS IOs being used on these ports are connected such they emulate open-drain outputs. This  
emulation is achieved by forcing a constant low output and disabling the output buffer to enter the Hi-Z  
state.  
• The I2C specification defines a maximum input voltage VIH of (VDD + 0.5 V), which exceeds the  
absolute maximum ratings for the device IOs. The system must bemdaex signed to ensure the I2C signals  
never exceed the limits defined in the Absolute Maximum Ratings section of this data sheet.  
• I2C instances that use the I2C OD FS buffer type  
– Speeds:  
• Standard-mode (up to 100 Kbits/s)  
– 1.8 V  
– 3.3 V  
• Fast-mode (up to 400 Kbits/s)  
– 1.8 V  
– 3.3 V  
• Hs-mode (up to 3.4 Mbit/s)  
– 1.8 V  
– Exceptions:  
• The IOs associated with these ports were not design to support Hs-mode while operating at 3.3 V. So  
Hs-mode is limited to 1.8-V operation.  
• The rise and fall times of the I2C signals connected to these ports must not exceed a slew rate of 0.8  
V/ns (or 8E+7 V/s). This limit is more restrictive than the minimum fall time limits defined in the I2C  
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specification. Therefore, it may be necessary to add additional capacitance to the I2C signals to slow  
the rise and fall times such that they do not exceed a slew rate of 0.8 V/ns.  
• The I2C specification defines a maximum input voltage VIH of (VDD + 0.5 V), which exceeds the  
absolute maximum ratings for the device IOs. The system must bemdaex signed to ensure the I2C signals  
never exceed the limits defined in the Absolute Maximum Ratings section of this data sheet.  
Refer to the Philips I2C-bus specification version 2.1 for timing details.  
For more details about features and additional description information on the device Inter-Integrated Circuit, see  
the corresponding subsections within 节6.3 and Detailed Description.  
7.10.5.13 I3C  
For more details about features and additional description information on the device Inter-Integrated Circuit, see  
the corresponding sections within Signal Descriptions, Signal Descriptions and Detailed Description.  
表 7-42, 表 7-43, 图 7-69, 表 7-44, and 图 7-70 assume testing over the recommended operating conditions and  
electrical characteristic conditions.  
表7-42. I3C Open Drain Timing Conditions  
PARAMETER  
MIN  
MAX  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
0.2276  
5
OUTPUT CONDITIONS  
CL  
Output load capacitance  
50  
表7-43. I3C Open Drain Timing Parameters  
NO.  
PARAMETER  
tLOW_OD  
DESCRIPTION  
MODE  
MIN  
MAX UNIT  
D1  
Low Period of SCL Clock  
Controller  
200  
ns  
ns  
tDIG_OD_L  
tLOW_OD  
+
MIN  
tFDA_OD  
MIN  
D2  
tHIGH  
High Period of SCL Clock  
Controller  
41  
tHIGH + tCF  
12  
ns  
ns  
ns  
ns  
ns  
tDIG_H  
tfDA_OD  
tSU_OD  
tCAS  
D3  
D4  
D5  
Fall Time of SDA Signal  
Controller, Target  
Controller, Target  
tCF  
3
SDA Data Setup Time During Open Drain Mode  
Clock After START (S) Condition  
Controller,  
ENTAS0  
38.4  
1000  
100000  
Controller,  
ENTAS1  
38.4  
38.4  
ns  
ns  
ns  
ns  
ns  
Controller,  
ENTAS2  
2000000  
Controller,  
ENTAS3  
38.4 50000000  
D6  
D7  
tCBP  
Clock Before STOP (P) Condition  
Controller  
tCAS MIN  
/
2
tMMOVERLAP  
Current Controller to Secondary Controller Overlap  
time during handoff  
Controller  
tDIG_OD_L  
min  
D8  
D9  
tAVAL  
Bus Available Condition  
Bus Idle Condition  
Controller  
Controller  
Controller  
1000  
1000000  
tAVALmin  
ns  
ns  
ns  
tIDLE  
D10  
tMMLOCK  
Time Internal Where New Controller Not Driving SDA  
Low  
1. This is approximately equal to tLOWmin + tDS_ODmin + trDA_ODtyp + tSU_Odmin  
.
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2. The Controller may use a shorter Low period if the Controller knows that this is safe, when SDA is already  
above VIH.  
3. Based on tSPIKE, rise and fall times, and interconnect.  
4. This maximum High period may be exceeded when the signals can be safely seen by Legacy I2C Devices,  
and/or in consideration of the interconnect (for example: a short Bus).  
5. On a Legacy Bus where I2C Devices need to see Start, the tCAS Min value is further constrained.  
6. Targets that do not support the optional ENTASx CCCs shall use the tCAS Max value shown for ENTAS3.  
7. On a Mixed Bus with Fm Legacy I2C Devices, tAVAL is 300ns shorter than the Fm Bus Free Condition time  
(tBUF).  
D4  
D3  
0.7xVDD  
0.3xVDD  
SDA  
D5  
D6  
D1  
0.7xVDD  
0.3xVDD  
SCL  
D2  
Stop  
Start  
Repeated  
Start  
Stop  
- Open drain with weak pull-up  
- Open drain with weak pull-up  
I3C_TIMING_01  
图7-69. I3C Open Drain Timing  
表7-44. I3C Push-Pull Timing Parameters for SDR and HDR-DDR Modes  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
MIN  
MAX UNIT  
D1  
D2  
fSCL  
SCL Clock Period  
Controller  
Controller  
80 100000  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tLOW  
SCL Clock Low Period  
24  
32  
24  
32  
24  
32  
12  
tDIG_L  
D3  
D4  
tHIGH_MIXED  
tDIG_H_MIXED  
tHIGH  
SCL Clock High Period of Mixed Bus (Mixed Bus Topology  
Not Supported)  
Controller  
Controller  
Target  
45  
SCL Clock High Period  
tDIG_H  
D5  
D6  
tSCO  
Clock in to Data Out for Target  
SCL Clock Rise Time  
tCR  
Controller 150 × 1 /  
fSCL  
60  
60  
D7  
D8  
tCF  
SCL Clock Fall Time  
Controller 150 × 1 /  
fSCL  
ns  
ns  
tHD_PP  
SDA Signal Data Hold in Push Pull Mode  
Controller  
tCR + 3  
and tCF  
+
3
Target  
0
3
ns  
ns  
D9  
tSU_PP  
SDA Signal Data Setup In Push-Pull Mode  
Controller,  
Target  
D10  
D11  
tCASr  
tCBSr  
Clock After Repeated START (Sr)  
Clock Before Repeated START (Sr)  
Controller  
tCAS MIN  
ns  
ns  
Controller tCAS MIN  
/
2
1. FSCL = 1 / (tDIG_L + tDIG_H  
)
2. tDIG_L and tDIG_H are the clock Low and High periods as seen at the receiver end of the I3C Bus using VIL  
and VIH.  
3. When communicating with an I3C Device on a mixed Bus, the tDIG_H_MIXED period must be constrained to  
make sure that I2C Devices do not interpret I3C signaling as valid I2C signaling.  
4. As both edges are used, the hold time needs to be satisfied for the respective edges; tCF + 3 for falling edge  
clocks, and tCR + 3 for rising edge clocks.  
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5. Clock Frequency Minimum 0.01 MHz, Maximum 12.5 MHz  
0.7xVDD  
0.3xVDD  
SDA  
D5  
D11  
D10  
D1  
D5  
D2  
D8  
D9  
D9  
0.7xVDD  
SCL  
0.3xVDD  
D4  
D7  
D6  
Stop  
Start  
Repeated  
Start  
Stop  
- Open drain with weak pull-up  
- Open drain with weak pull-up  
I3C_TIMING_02  
图7-70. I3C Push-Pull Timing (SDR and HDR-DDR Modes)  
7.10.5.14 MCAN  
For more details about features and additional description information on the device Controller Area Network  
Interface, see the corresponding sections within Signal Descriptions and Detailed Description.  
备注  
The device has multiple MCAN modules. MCANn is a generic prefix applied to MCAN signal names,  
where n represents the specific MCAN module.  
表7-45. MCAN Timing Conditions  
PARAMETER  
MIN  
2
MAX  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
15  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
5
20  
表7-46. MCAN Switching Characteristics  
PARAMETER  
NO.  
MIN  
MAX  
10  
UNIT  
MCAN1 td(MCAN_TX)  
MCAN2 td(MCAN_RX)  
Delay time, transmit shift register to MCANn_TX pin(1)  
Delay time, MCANn_RX pin to receive shift register(1)  
ns  
ns  
10  
(1) n is [0:13] in MCANn_* or [0:1] in MCU_MCANn_*  
For more information, see Controller Area Network (MCAN) section in Peripherals chapter in the device TRM.  
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7.10.5.15 MCASP  
For more details about features and additional description information on the device Multichannel Audio Serial  
Port, see the corresponding sections within Signal Descriptions and Detailed Description.  
表7-48 and 图7-71 present timing requirements for MCASP0 to MCASP11.  
表7-47 represents MCASP timing conditions.  
表7-47. MCASP Timing Conditions  
PARAMETER  
MIN  
0.7  
1
MAX  
5
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
10  
PCB CONNECTIVITY REQUIREMENTS  
td(Trace Delay)  
Propagation delay of each trace  
100  
1100  
100  
ps  
ps  
td(Trace Mismatch Delay)  
Propagation delay mismatch across all traces  
表7-48. MCASP Timing Requirements  
NO.  
MODE(1)  
MIN  
15.26  
0.5P(2)  
MAX UNIT  
ASP1 tc(AHCLKRX)  
Cycle time, MCASP[x]_AHCLKR/X  
ns  
ns  
-
ASP2 tw(AHCLKRX)  
ASP3 tc(ACLKRX)  
ASP4 tw(ACLKRX)  
Pulse duration, MCASP[x]_AHCLKR/X high or low  
Cycle time, MCASP[x]_ACLKR/X  
1.53  
15.26  
ns  
ns  
0.5R(3)  
-
Pulse duration, MCASP[x]_ACLKR/X high or low  
1.53  
12.3  
4
ACLKR/X int  
ns  
ns  
ns  
ns  
Setup time, MCASP[x]_AFSR/X input valid before  
MCASP[x]_ACLKR/X  
ASP5 tsu(AFSRX-ACLKRX)  
ASP6 th(ACLKRX-AFSRX)  
ASP7 tsu(AXR-ACLKRX)  
ASP8 th(ACLKRX-AXR)  
ACLKR/X ext in/out  
ACLKR/X int  
–1  
1.6  
12.3  
4
Hold time, MCASP[x]_AFSR/X input valid after  
MCASP[x]_ACLKR/X  
ACLKR/X ext in/out  
ACLKR/X int  
Setup time, MCASP[x]_AXR input valid before  
MCASP[x]_ACLKR/X  
ACLKR/X ext in/out  
ACLKR/X int  
-1  
Hold time, MCASP[x]_AXR input valid after  
MCASP[x]_ACLKR/X  
ACLKR/X ext in/out  
1.6  
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1  
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0  
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1  
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1  
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0  
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1  
(2) P = AHCLKR/X period in ns.  
(3) R = ACLKR/X period in ns.  
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ASP2  
ASP2  
ASP1  
MCASP[x]_ACLKR/X (Falling Edge Polarity)  
MCASP[x]_AHCLKR/X (Rising Edge Polarity)  
ASP4  
ASP4  
ASP3  
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 0)(A)  
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 1)(B)  
ASP6  
ASP5  
MCASP[x]_AFSR/X (Bit Width, 0 Bit Delay)  
MCASP[x]_AFSR/X (Bit Width, 1 Bit Delay)  
MCASP[x]_AFSR/X (Bit Width, 2 Bit Delay)  
MCASP[x]_AFSR/X (Slot Width, 0 Bit Delay)  
MCASP[x]_AFSR/X (Slot Width, 1 Bit Delay)  
MCASP[x]_AFSR/X (Slot Width, 2 Bit Delay)  
ASP8  
ASP7  
MCASP[x]_AXR[x] (Data In/Receive)  
A0 A1  
A30 A31 B0 B1  
B30 B31 C0 C1 C2 C3  
C31  
A. For CLKRP = CLKXP = 0, the MCASP transmitter is configured for rising edge (to shift data out) and the MCASP receiver is configured  
for falling edge (to shift data in).  
B. For CLKRP = CLKXP = 1, the MCASP transmitter is configured for falling edge (to shift data out) and the MCASP receiver is configured  
for rising edge (to shift data in).  
图7-71. MCASP Input Timing  
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表 7-49 and 图 7-72 present switching characteristics over recommended operating conditions for MCASP0 to  
MCASP11.  
表7-49. MCASP Switching Characteristics  
NO.  
PARAMETER  
DESCRIPTION  
MODE(1)  
MIN  
MAX UNIT  
ASP9 tc(AHCLKRX)  
ASP10 tw(AHCLKRX)  
ASP11 tc(ACLKRX)  
ASP12 tw(ACLKRX)  
Cycle time, MCASP[x]_AHCLKR/X  
20  
0.5P(2) - 2  
20  
ns  
ns  
ns  
ns  
Pulse duration, MCASP[x]_AHCLKR/X high or low  
Cycle time, MCASP[x]_ACLKR/X  
Pulse duration, MCASP[x]_ACLKR/X high or low  
0.5R(3) - 2  
ASP13 td(ACLKRX-AFSRX) Delay time, MCASP[x]_ACLKR/X transmit edge to  
MCASP[x]_AFSR/X output valid  
ACLKR/X int  
0
7.25  
12.84  
7.25  
12.84  
7.25  
14  
ns  
ns  
ns  
ACLKR/X ext in/out  
ACLKR/X int  
–15.28  
0
ASP14 td(ACLKX-AXR)  
Delay time, MCASP[x]_ACLKX transmit edge to  
MCASP[x]_AXR output valid  
ACLKR/X ext in/out  
ACLKR/X int  
–15.28  
0
ASP15 tdis(ACLKX-AXR)  
Disable time, MCASP[x]_ACLKX transmit edge to  
MCASP[x]_AXR output high impedance  
ACLKR/X ext in/out  
–14.9  
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1  
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0  
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1  
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1  
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0  
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1  
(2) P = AHCLKR/X period in ns.  
(3) R = ACLKR/X period in ns.  
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ASP10  
ASP10  
ASP9  
MCASP[x]_ACLKR/X (Falling Edge Polarity)  
MCASP[x]_AHCLKR/X (Rising Edge Polarity)  
ASP12  
ASP12  
ASP11  
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 1)(A)  
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 0)(B)  
ASP13  
ASP13  
ASP13  
ASP13  
MCASP[x]_AFSR/X (Bit Width, 0 Bit Delay)  
MCASP[x]_AFSR/X (Bit Width, 1 Bit Delay)  
MCASP[x]_AFSR/X (Bit Width, 2 Bit Delay)  
MCASP[x]_AFSR/X (Slot Width, 0 Bit Delay)  
MCASP[x]_AFSR/X (Slot Width, 1 Bit Delay)  
MCASP[x]_AFSR/X (Slot Width, 2 Bit Delay)  
ASP13  
ASP13  
ASP13  
MCASP[x]_AXR[x] (Data Out/Transmit)  
ASP14  
ASP15  
A0 A1  
A30 A31 B0 B1  
B30 B31 C0 C1 C2 C3  
C31  
A. For CLKRP = CLKXP = 1, the MCASP transmitter is configured for falling edge (to shift data out) and the MCASP receiver is configured  
for rising edge (to shift data in).  
B. For CLKRP = CLKXP = 0, the MCASP transmitter is configured for rising edge (to shift data out) and the MCASP receiver is configured  
for falling edge (to shift data in).  
图7-72. MCASP Output Timing  
For more information, see Multichannel Audio Serial Port (MCASP) section in Peripherals chapter in the device  
TRM.  
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7.10.5.16 MCSPI  
For more details about features and additional description information on the device Serial Port Interface, see  
the corresponding sections within Signal Descriptions and Detailed Description.  
For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the  
device TRM.  
表7-50 represents MCSPI timing conditions.  
备注  
The IO timings provided in this section are applicable for all combinations of signals for MCU_SPI0  
and MCU_SPI1. However, the timings are only valid for MCU_SPI0 and MCU_SPI1 if signals within a  
single IOSET are used. The IOSETs are defined in the 表7-55 and 表7-56 tables.  
表7-50. MCSPI Timing Conditions  
PARAMETER  
MIN  
MAX  
UNIT  
INPUT CONDITIONS  
SRI  
Input slew rate  
2
8.5 V/ns  
OUTPUT CONDITIONS  
CLK  
6
6
24  
12  
pF  
pF  
CL  
Output load capacitance  
D[x], CSi  
7.10.5.16.1 MCSPI —Controller Mode  
表 7-51, 图 7-73, 表 7-52, and 图 7-74 present timing requirements and switching characteristics for MCSPI –  
Controller Mode.  
表7-51. MCSPI Timing Requirements - Controller Mode  
see 图7-73  
NO.  
MIN  
MAX  
UNIT  
tsu(misoV-  
SM4  
Setup time, SPI_D[x] valid before SPI_CLK active edge  
Hold time, SPI_D[x] valid after SPI_CLK active edge  
2.9  
ns  
spiclkV)  
th(spiclkV-  
SM5  
2
ns  
misoV)  
表7-52. MCSPI Switching Characteristics - Controller Mode  
see 图7-74  
NO.  
PARAMETER  
Cycle time, SPI_CLK  
MODE  
MIN  
MAX UNIT  
SM1 tc(spiclk)  
SM2 tw(spiclkL)  
20.8  
ns  
0.5P -  
1(1)  
Pulse duration, SPI_CLK low  
Pulse duration, SPI_CLK high  
ns  
ns  
0.5P -  
1(1)  
SM3 tw(spiclkH)  
Delay time, SPI_CLK active edge to SPI_D[x]  
transition  
SM6 td(spiclkV-simoV)  
SM7 td(csV-simoV)  
SM8 td(csV-spiclk)  
2
ns  
–2  
Delay time, SPI_CSi active edge to SPI_D[x] transition  
5
B - 4(3)  
A - 4(4)  
A - 4(4)  
B - 4(3)  
ns  
ns  
ns  
ns  
ns  
PHA = 0(2)  
PHA = 1 (2)  
PHA = 0(2)  
PHA = 1(2)  
Delay time, SPI_CSi active to SPI_CLK first edge  
SM9 td(spiclkV-csV)  
Delay time, SPI_CLK last edge to SPI_CSi inactive  
(1) P = SPI_CLK period in ns  
(2) SPI_CLK phase is programmable with the PHA bit of the MCSPI_CHCONF_0/1/2/3 register  
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(3) B = (TCS + .5) * TSPICLKREF, where TCSns a bit field of the MCSPI_CHCONF_0/1/2/3 register and Fratio = Even >= 2.  
(4) When P = 20.8 ns, A = (TCS + 1) * TSPICLKREF, where TCSns a bit field of the MCSPI_CHCONF_0/1/2/3 register.  
When P > 20.8 ns, A = (TCS + 0.5) * Fratio * TSPICLKREF, where TCSns a bit field of the MCSPI_CHCONF_0/1/2/3 register.  
PHA=0  
EPOL=1  
SPI_CS[i] (OUT)  
SM1  
SM3  
SM8  
SM2  
SM9  
POL=0  
POL=1  
SPI_SCLK (OUT)  
SM1  
SM3  
SM2  
SPI_SCLK (OUT)  
SM5  
SM5  
SM4  
SM4  
Bit n-1  
Bit n-2  
Bit n-3  
Bit n-4  
Bit 0  
SPI_D[x] (IN)  
PHA=1  
EPOL=1  
SPI_CS[i] (OUT)  
SPI_SCLK (OUT)  
SM2  
SM1  
SM8  
SM3  
SM2  
SM9  
POL=0  
POL=1  
SM1  
SM3  
SPI_SCLK (OUT)  
SM5  
SM4  
SM5  
Bit n-2  
SM4  
Bit n-1  
Bit n-3  
Bit 1  
Bit 0  
SPI_D[x] (IN)  
SPRSP08_TIMING_McSPI_02  
图7-73. SPI Controller Mode Receive Timing  
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PHA=0  
EPOL=1  
SPI_CS[i] (OUT)  
SM1  
SM3  
SM8  
SM2  
SM9  
POL=0  
SPI_SCLK (OUT)  
SM1  
SM3  
SM2  
POL=1  
SPI_SCLK (OUT)  
SM7  
Bit n-1  
SM6  
Bit n-2  
SM6  
Bit n-3  
Bit n-4  
Bit 0  
SPI_D[x] (OUT)  
PHA=1  
EPOL=1  
SPI_CS[i] (OUT)  
SM1  
SM2  
SM8  
SM3  
SM2  
SM9  
POL=0  
SPI_SCLK (OUT)  
SM1  
SM3  
POL=1  
SPI_SCLK (OUT)  
SM6  
Bit n-1  
SM6  
Bit n-2  
SM6  
Bit n-3  
SM6  
Bit 1  
Bit0  
SPI_D[x] (OUT)  
SPRSP08_TIMING_McSPI_01  
图7-74. MCSPI Controller Mode Transmit Timing  
7.10.5.16.2 MCSPI —Peripheral Mode  
表 7-53, 表 7-54, 图 7-75, and 图 7-76 present timing requirements and switching characteristics for MCSPI –  
Peripheral Mode.  
表7-53. MCSPI Timing Requirements - Peripheral Mode  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
MIN  
MAX UNIT  
SS1 tc(spiclk)  
Cycle time, SPI_CLK  
20.8  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
SS2 tw(spiclkL)  
Pulse duration, SPI_CLK low  
0.45P(1)  
SS3 tw(spiclkH)  
Pulse duration, SPI_CLK high  
0.45P(1)  
SS4 tsu(simoV-spiclkV)  
SS5 th(spiclkV-simoV)  
SS8 tsu(csV-spiclkV)  
SS9 th(spiclkV-csV)  
Setup time, SPI_D[x] valid before SPI_CLK active edge  
Hold time, SPI_D[x] valid after SPI_CLK active edge  
Setup time, SPI_CSi valid before SPI_CLK first edge  
Hold time, SPI_CSi valid after SPI_CLK last edge  
5
5
5
5
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表7-54. MCSPI Switching Characteristics - Peripheral Mode  
PARAMET  
NO.  
SS6  
SS7  
DESCRIPTION  
MIN  
MAX  
UNIT  
ER  
td(spiclkV-  
Delay time, SPI_CLK active edge to SPI_D[x] transition  
2
17.12  
ns  
ns  
somiV)  
tsk(csV-somiV) Delay time, SPI_CSi active edge to SPI_D[x] transition  
20.95  
(1) P = SPI_CLK period in ns.  
PHA=0  
EPOL=1  
SPI_CS[i] (IN)  
SS1  
SS2  
SS8  
SS3  
SS3  
SS9  
POL=0  
SPI_SCLK (IN)  
SS1  
SS2  
POL=1  
SPI_SCLK (IN)  
SS5  
SS4  
SS5  
Bit n-2  
SS4  
Bit n-1  
Bit n-3  
Bit n-4  
Bit 0  
SPI_D[x] (IN)  
PHA=1  
EPOL=1  
SPI_CS[i] (IN)  
SS1  
SS2  
SS8  
SS3  
SS2  
SS9  
POL=0  
SPI_SCLK (IN)  
SS1  
SS3  
POL=1  
SPI_SCLK (IN)  
SS4  
SS5  
SS4  
SS5  
Bit n-1  
Bit n-2  
Bit n-3  
Bit 1  
Bit 0  
SPI_D[x] (IN)  
SPRSP08_TIMING_McSPI_04  
图7-75. SPI Peripheral Mode Receive Timing  
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PHA=0  
EPOL=1  
SPI_CS[i] (IN)  
SS1  
SS2  
SS8  
SS3  
SS3  
SS9  
POL=0  
SPI_SCLK (IN)  
SS1  
SS2  
POL=1  
SPI_SCLK (IN)  
SS7  
Bit n-1  
SS6  
Bit n-2  
SS6  
Bit n-3  
Bit n-4  
Bit 0  
SPI_D[x] (OUT)  
PHA=1  
EPOL=1  
SPI_CS[i] (IN)  
SS1  
SS2  
SS8  
SS3  
SS2  
SS9  
POL=0  
SPI_SCLK (IN)  
SS1  
SS3  
POL=1  
SPI_SCLK (IN)  
SS6  
Bit n-1  
SS6  
Bit n-2  
SS6  
Bit n-3  
SS6  
Bit 1  
Bit 0  
SPI_D[x] (OUT)  
SPRSP08_TIMING_McSPI_03  
图7-76. MCSPI Peripheral Mode Transmit Timing  
表7-55 and 表7-56 present the specific groupings of signals (IOSET) for use with MCU_SPI0 and MCU_SPI1.  
表7-55. MCU_SPI0 IOSETs  
Signals  
IOSET1  
IOSET2  
BALL NAME  
MUX  
BALL NAME  
MUX  
MCU_SPI0_CLK  
MCU_SPI0_D0  
MCU_SPI0_D1  
MCU_SPI0_CS0  
MCU_SPI0_CS1  
MCU_SPI0_CS2  
MCU_SPI0_CLK  
MCU_SPI0_D0  
0
0
0
0
5
5
MCU_SPI0_CLK  
MCU_SPI0_D0  
0
0
0
0
1
1
MCU_SPI0_D1  
MCU_SPI0_D1  
MCU_SPI0_CS0  
MCU_OSPI1_D3  
MCU_OSPI1_CSn1  
MCU_SPI0_CS0  
WKUP_GPIO0_12  
WKUP_GPIO0_14  
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表7-56. MCU_SPI1 IOSET  
Signals  
IOSET1  
IOSET2  
BALL NAME  
MCU_SPI1_CLK  
MCU_SPI1_D0  
MCU_SPI1_D1  
MCU_SPI1_CS0  
MCU_OSPI1_D1  
MCU_OSPI1_D2  
MUX  
BALL NAME  
MUX  
MCU_SPI1_CLK  
MCU_SPI1_D0  
MCU_SPI1_D1  
MCU_SPI1_CS0  
MCU_SPI1_CS1  
MCU_SPI1_CS2  
0
0
0
0
5
5
MCU_SPI1_CLK  
MCU_SPI1_D0  
0
0
0
0
1
1
MCU_SPI1_D1  
MCU_SPI1_CS0  
WKUP_GPIO0_13  
WKUP_GPIO0_15  
For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the  
device TRM.  
7.10.5.17 MMCSD  
The MMCSD Host Controller provides an interface to embedded Multi-Media Card (MMC), Secure Digital (SD),  
and Secure Digital IO (SDIO) devices. The MMCSD Host Controller deals with MMC/SD/SDIO protocol at  
transmission level, data packing, adding cyclic redundancy checks (CRCs), start/end bit insertion, and checking  
for syntactical correctness.  
For more details about MMCSD interfaces, see the corresponding MMC0, MMC1, and MMC2 sections within  
Signal Descriptions and Detailed Description.  
备注  
Some operating modes require software configuration of the MMC DLL delay settings, as shown in 表  
7-57 and 表7-67.  
For more information, see Multi-Media Card/Secure Digital (MMCSD) Interface section in Peripherals chapter in  
the device TRM.  
7.10.5.17.1 MMC0 - eMMC Interface  
MMC0 interface is compliant with the JEDEC eMMC electrical standard v5.1 (JESD84-B51) and it supports the  
following eMMC applications:  
• Legacy speed  
• High speed SDR  
• High speed DDR  
• High Speed HS200  
• High Speed HS400  
表7-57 presents the required DLL software configuration settings for MMC0 timing modes.  
表7-57. MMC0 DLL Delay Mapping for All Timing Modes  
REGISTER NAME  
BIT FIELD  
MMCSD0_SS_PHY_CTRL_4_REG  
[15:12]  
MMCSD0_SS_PHY_CTRL_5_REG  
[31:24]  
[20]  
[8]  
[4:0]  
[17:16]  
[10:8]  
[2:0]  
SELDLYTXCLK  
SELDLYRXCLK  
BIT FIELD NAME  
STRBSEL  
OTAPDLYENA  
OTAPDLYSEL  
ITAPDLYENA  
ITAPDLYSEL  
FRQSEL  
CLKBUFSEL  
OUTPUT  
DELAY  
ENABLE  
OUTPUT  
DELAY  
VALUE  
INPUT  
DELAY  
ENABLE  
INPUT  
DELAY  
VALUE  
DLL/  
DELAY CHAIN  
SELECT  
DELAY  
BUFFER  
DURATION  
STROBE  
DELAY  
DLL REF  
FREQUENCY  
MODE DESCRIPTION  
8-bit PHY  
Legacy  
operating 1.8 V,  
SDR  
0x0  
0x0  
0x0  
0x0  
NA  
NA  
0x1  
0x1  
0x10  
0xA  
0x1  
0x1  
0x0  
0x0  
0x7  
0x7  
25 MHz  
High  
Speed operating 1.8 V,  
SDR 50 MHz  
8-bit PHY  
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表7-57. MMC0 DLL Delay Mapping for All Timing Modes (continued)  
REGISTER NAME  
BIT FIELD  
MMCSD0_SS_PHY_CTRL_4_REG  
MMCSD0_SS_PHY_CTRL_5_REG  
[31:24]  
[20]  
[15:12]  
[8]  
[4:0]  
[17:16]  
[10:8]  
[2:0]  
SELDLYTXCLK  
SELDLYRXCLK  
BIT FIELD NAME  
STRBSEL  
OTAPDLYENA  
OTAPDLYSEL  
ITAPDLYENA  
ITAPDLYSEL  
FRQSEL  
CLKBUFSEL  
OUTPUT  
DELAY  
ENABLE  
OUTPUT  
DELAY  
VALUE  
INPUT  
DELAY  
ENABLE  
INPUT  
DELAY  
VALUE  
DLL/  
DELAY CHAIN  
SELECT  
DELAY  
BUFFER  
DURATION  
STROBE  
DELAY  
DLL REF  
FREQUENCY  
MODE DESCRIPTION  
High  
8-bit PHY  
Speed operating 1.8 V,  
0x0  
0x0  
0x1  
0x1  
0x1  
0x6  
0x8  
0x5  
0x1  
0x1  
0x1  
Tuning  
Tuning  
Tuning  
0x0  
0x0  
0x0  
0x4  
0x0  
0x0  
0x7  
0x7  
0x7  
DDR  
50 MHz  
8-bit PHY  
HS200 operating 1.8 V,  
200 MHz  
8-bit PHY  
HS400 operating 1.8 V,  
200 MHz  
0x66  
表7-58 presents timing conditions for MMC0.  
表7-58. MMC0 Timing Conditions  
PARAMETER  
MIN  
MAX UNIT  
INPUT CONDITIONS  
Legacy SDR  
0.14  
0.3  
1.44 V/ns  
0.90 V/ns  
0.90 V/ns  
0.90 V/ns  
High Speed SDR  
SRI  
Input slew rate  
High Speed DDR (CMD)  
High Speed DDR (DAT[7:0])  
0.3  
0.45  
OUTPUT CONDITIONS  
HS200, HS400  
All other modes  
1
1
6
pF  
pF  
CL  
Output load capacitance  
12  
PCB CONNECTIVITY REQUIREMENTS  
td(Trace Delay)  
Propagation delay of each trace  
All modes  
134  
756  
100  
8
ps  
ps  
ps  
Legacy SDR, High Speed SDR,  
High Speed DDR  
td(Trace Mismatch  
Propagation delay mismatch across all  
traces  
Delay)  
HS200, HS400  
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7.10.5.17.1.1 Legacy SDR Mode  
表 7-59, 图 7-77, 表 7-60, and 图 7-78 present timing requirements and switching characteristics for MMC0 –  
Legacy SDR Mode.  
表7-59. MMC0 Timing Requirements –Legacy SDR Mode  
see 图7-77  
NO.  
MIN  
2.5  
6.5  
2.5  
6.5  
MAX  
UNIT  
ns  
LSDR1 tsu(cmdV-clkH)  
LSDR2 th(clkH-cmdV)  
LSDR3 tsu(dV-clkH)  
LSDR4 th(clkH-dV)  
Setup time, MMC0_CMD valid before MMC0_CLK rising edge  
Hold time, MMC0_CMD valid after MMC0_CLK rising edge  
Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge  
Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge  
ns  
ns  
ns  
图7-77. MMC0 –Legacy SDR –Receive Mode  
表7-60. MMC0 Switching Characteristics –Legacy SDR Mode  
see 图7-78  
NO.  
PARAMETER  
Operating frequency, MMC0_CLK  
Cycle time, MMC0_CLK  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
25  
LSDR5  
LSDR6  
LSDR7  
LSDR8  
LSDR9  
tc(clk)  
40  
18.7  
tw(clkH)  
Pulse duration, MMC0_CLK high  
Pulse duration, MMC0_CLK low  
ns  
tw(clkL)  
18.7  
ns  
td(clkL-cmdV)  
td(clkL-dV)  
Delay time, MMC0_CLK falling edge to MMC0_CMD transition  
Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition  
3.8  
3.8  
ns  
–3.2  
–3.2  
ns  
图7-78. MMC0 –Legacy SDR –Transmit Mode  
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7.10.5.17.1.2 High Speed SDR Mode  
表 7-61, 图 7-79, 表 7-62, and 图 7-80 present timing requirements and switching characteristics for MMC0 –  
High Speed SDR Mode.  
表7-61. MMC0 Timing Requirements –High Speed SDR Mode  
see 图7-79  
NO.  
MIN  
2.99  
2.67  
2.99  
2.67  
MAX  
UNIT  
ns  
HSSDR1 tsu(cmdV-clkH)  
HSSDR2 th(clkH-cmdV)  
HSSDR3 tsu(dV-clkH)  
HSSDR4 th(clkH-dV)  
Setup time, MMC0_CMD valid before MMC0_CLK rising edge  
Hold time, MMC0_CMD valid after MMC0_CLK rising edge  
Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge  
Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge  
ns  
ns  
ns  
图7-79. MMC0 –High Speed SDR Mode –Receive Mode  
表7-62. MMC0 Switching Characteristics –High Speed SDR Mode  
see 图7-80  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
HSSDR5 tc(clk)  
Operating frequency, MMC0_CLK  
50  
Cycle time, MMC0_CLK  
20  
9.2  
HSSDR6 tw(clkH)  
HSSDR7 tw(clkL)  
HSSDR8 td(clkL-cmdV)  
HSSDR9 td(clkL-dV)  
Pulse duration, MMC0_CLK high  
ns  
Pulse duration, MMC0_CLK low  
9.2  
ns  
Delay time, MMC0_CLK falling edge to MMC0_CMD transition  
Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition  
3.8  
3.8  
ns  
–3.2  
–3.2  
ns  
图7-80. MMC0 –High Speed SDR Mode –Transmit Mode  
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ZHCSRF7 –DECEMBER 2022  
7.10.5.17.1.3 High Speed DDR Mode  
表 7-63, 图 7-81, 表 7-64, and 图 7-82 present timing requirements and switching characteristics for MMC0 –  
High Speed DDR Mode.  
表7-63. MMC0 Timing Requirements –High Speed DDR Mode  
see 图7-81  
NO.  
MIN  
3.79  
2.67  
0.74  
1.67  
MAX  
UNIT  
ns  
HSDDR1 tsu(cmdV-clkH)  
HSDDR2 th(clkH-cmdV)  
HSDDR3 tsu(dV-clkV)  
HSDDR4 th(clkV-dV)  
Setup time, MMC0_CMD valid before MMC0_CLK rising edge  
Hold time, MMC0_CMD valid after MMC0_CLK rising edge  
Setup time, MMC0_DAT[7:0] valid before MMC0_CLK transition  
Hold time, MMC0_DAT[7:0] valid after MMC0_CLK transition  
ns  
ns  
ns  
图7-81. MMC0 –High Speed DDR Mode –Receive Mode  
表7-64. MMC0 Switching Characteristics –High Speed DDR Mode  
see 图7-82  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
HSDDR5 tc(clk)  
Operating frequency, MMC0_CLK  
50  
Cycle time, MMC0_CLK  
20  
9.2  
9.2  
3.4  
2.9  
HSDDR6 tw(clkH)  
HSDDR7 tw(clkL)  
HSDDR8 td(clkH-cmdV)  
HSDDR9 td(clkV-dV)  
Pulse duration, MMC0_CLK high  
ns  
Pulse duration, MMC0_CLK low  
ns  
Delay time, MMC0_CLK rising edge to MMC0_CMD transition  
Delay time, MMC0_CLK transition to MMC0_DAT[7:0] transition  
9.8  
ns  
6.85  
ns  
图7-82. MMC0 –High Speed DDR Mode –Transmit Mode  
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7.10.5.17.1.4 HS200 Mode  
表7-65 and 图7-83 present switching characteristics for MMC0 –HS200 Mode.  
表7-65. MMC0 Switching Characteristics –HS200 Mode  
see 图7-83  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
Operating frequency, MMC0_CLK  
200  
HS2005  
HS2006  
HS2007  
HS2008  
HS2009  
tc(clk)  
Cycle time, MMC0_CLK  
5
2.08  
2.08  
0.99  
0.99  
tw(clkH)  
Pulse duration, MMC0_CLK high  
ns  
tw(clkL)  
Pulse duration, MMC0_CLK low  
ns  
td(clkL-cmdV)  
td(clkL-dV)  
Delay time, MMC0_CLK rising edge to MMC0_CMD transition  
Delay time, MMC0_CLK rising edge to MMC0_DAT[7:0] transition  
3.16  
3.16  
ns  
ns  
图7-83. MMC0 –HS200 Mode –Transmit Mode  
7.10.5.17.1.5 HS400 Mode  
表7-66 and 图7-84 present switching characteristics for MMC0 –HS400 Mode.  
表7-66. MMC0 Switching Characteristics –HS400 Mode  
see 图7-84  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
Operating frequency, MMC0_CLK  
200  
HS4005  
HS4006  
HS4007  
HS4008  
tc(clk)  
Cycle time, MMC0_CLK  
5
2.08  
2.08  
0.99  
tw(clkH)  
Pulse duration, MMC0_CLK high  
Pulse duration, MMC0_CLK low  
ns  
tw(clkL)  
ns  
td(clkH-cmdV)  
Delay time, MMC0_CLK rising clock edge to MMC0_CMD  
transition  
3.28  
1.84  
ns  
HS4009  
td(clkV-dV)  
Delay time, MMC0_CLK transition to MMC0_DAT[7:0] transition  
0.59  
ns  
HS4005  
HS4006  
HS4007  
MMC0_CLK  
HS4008  
HS4008  
MMC0_CMD  
HS4009  
HS4009  
MMC0_DAT[7:0]  
图7-84. eMMC in –HS400 Mode –Transmitter Mode  
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7.10.5.17.2 MMC1/2 - SD/SDIO Interface  
MMC1 interface is compliant with the SD Host Controller Standard Specification 4.10 and SD Physical Layer  
Specification v3.01 as well as SDIO Specification v3.00 and they support the following SD Card applications:  
• Default speed  
• High speed  
• UHS–I SDR12  
• UHS–I SDR25  
• UHS–I SDR50  
• UHS–I SDR104  
• UHS–I DDR50  
表7-67 presents the required DLL software configuration settings for MMC1 timing modes.  
表7-67. MMC1 DLL Delay Mapping for All Timing Modes  
REGISTER NAME  
BIT FIELD  
MMCSD12_SS_PHY_CTRL_4_REG  
[15:12] [8]  
OTAPDLYENA OTAPDLYSEL ITAPDLYENA ITAPDLYSEL  
MMCSD12_SS_PHY_CTRL_5_REG  
[20]  
[4:0]  
[2:0]  
BIT FIELD NAME  
CLKBUFSEL  
INPUT  
DELAY  
ENABLE  
INPUT  
DELAY  
VALUE  
DELAY  
BUFFER  
DURATION  
DELAY  
ENABLE  
DELAY  
VALUE  
MODE  
DESCRIPTION  
Default  
Speed  
4-bit PHY operating  
3.3 V, 25 MHz  
0x0  
0x0  
0x1  
0x1  
0x1  
0x1  
0x1  
0x0  
0x0  
0xF  
0xF  
0xC  
0xC  
0x5  
0x0  
0x0  
0x0  
0x0  
0x1  
0x1  
0x1  
0x0  
0x0  
0x7  
0x7  
0x7  
0x7  
0x7  
0x7  
0x7  
High  
Speed  
4-bit PHY operating  
3.3 V, 50 MHz  
UHS-I  
SDR12  
4-bit PHY operating  
1.8 V, 25 MHz  
0x0  
UHS-I  
SDR25  
4-bit PHY operating  
1.8 V, 50 MHz  
0x0  
UHS-I  
SDR50  
4-bit PHY operating  
1.8 V, 100 MHz  
Tuning  
0x2  
UHS-I  
DR50  
4-bit PHY operating  
1.8 V, 50 MHz  
UHS-I  
SDR104  
4-bit PHY operating  
1.8, V 200 MHz  
Tuning  
表7-68 presents timing conditions for MMC1.  
表7-68. MMC1 Timing Conditions  
PARAMETER  
MIN  
MAX UNIT  
INPUT CONDITIONS  
Default Speed, High Speed  
UHS–I SDR12, UHS–I SDR25  
USH-1 DDR50  
0.69  
0.34  
1.00  
2.06 V/ns  
1.34 V/ns  
2.00 V/ns  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
All modes  
1
10  
pF  
PCB CONNECTIVITY REQUIREMENTS  
240.03  
126  
1134  
1386  
20  
ps  
ps  
ps  
ps  
ps  
UHS–I DDR50  
All other modes  
UHS–I DDR50  
UHS–I SDR104  
All other modes  
td(Trace Delay)  
Propagation delay of each trace  
td(Trace Mismatch  
Propagation delay mismatch across all  
traces  
8
Delay)  
100  
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7.10.5.17.2.1 Default Speed Mode  
表 7-69, 图 7-85, 表 7-70, and 图 7-86 present timing requirements and switching characteristics for MMC1/2 –  
Default Speed Mode.  
表7-69. MMC1/2 Timing Requirements –Default Speed Mode  
see 图7-85  
NO.  
DS1  
DS2  
DS3  
DS4  
MIN  
2.15  
4.56  
2.15  
4.56  
MAX  
UNIT  
ns  
tsu(cmdV-clkH)  
th(clkH-cmdV)  
tsu(dV-clkH)  
th(clkH-dV)  
Setup time, MMC[x]_CMD valid before MMC[x]_CLK rising edge  
Hold time, MMC[x]_CMD valid after MMC[x]_CLK rising edge  
Setup time, MMC[x]_DAT[3:0] valid before MMC[x]_CLK rising edge  
Hold time, MMC[x]_DAT[3:0] valid after MMC[x]_CLK rising edge  
ns  
ns  
ns  
A. x = 1, 2 for MMC1 and MMC2  
B. x = 1, 2 for MMC1 and MMC2  
MMC[x]_CLK  
MMC[x]_CMD  
DS2  
DS4  
DS1  
DS3  
MMC[x]_DAT[3:0]  
图7-85. MMC1/2 –Default Speed –Receive Mode  
表7-70. MMC1/2 Switching Characteristics –Default Speed Mode  
see 图7-86  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
Operating frequency, MMC[x]_CLK  
25  
DS5  
DS6  
DS7  
DS8  
DS9  
tc(clk)  
Cycle time, MMC[x]_CLK  
40  
18.7  
tw(clkH)  
Pulse duration, MMC[x]_CLK high  
ns  
tw(clkL)  
Pulse duration, MMC[x]_CLK low  
18.7  
ns  
td(clkL-cmdV)  
td(clkL-dV)  
Delay time, MMC[x]_CLK falling edge to MMC[x]_CMD transition  
Delay time, MMC[x]_CLK falling edge to MMC[x]_DAT[3:0] transition  
3.53  
3.53  
ns  
–3.53  
–3.53  
ns  
DS5  
DS6  
DS7  
MMC[x]_CLK  
MMC[x]_CMD  
DS8  
DS9  
MMC[x]_DAT[3:0]  
图7-86. MMC1/2 –Default Speed –Transmit Mode  
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7.10.5.17.2.2 High Speed Mode  
表 7-71, 图 7-87, 表 7-72, and 图 7-88 present timing requirements and switching characteristics for MMC1/2 –  
High Speed Mode.  
表7-71. MMC1/2 Timing Requirements –High Speed Mode  
see 图7-87  
NO.  
HS1  
HS2  
HS3  
HS4  
MIN  
2.15  
2.26  
2.15  
2.26  
MAX  
UNIT  
ns  
tsu(cmdV-clkH)  
th(clkH-cmdV)  
tsu(dV-clkH)  
th(clkH-dV)  
Setup time, MMC[x]_CMD valid before MMC[x]_CLK rising edge  
Hold time, MMC[x]_CMD valid after MMC[x]_CLK rising edge  
Setup time, MMC[x]_DAT[3:0] valid before MMC[x]_CLK rising edge  
Hold time, MMC[x]_DAT[3:0] valid after MMC[x]_CLK rising edge  
ns  
ns  
ns  
A. x = 1, 2 for MMC1 and MMC2  
B. x = 1, 2 for MMC1 and MMC2  
MMC[x]_CLK  
MMC[x]_CMD  
HS1  
HS3  
HS2  
HS4  
MMC[x]_DAT[3:0]  
图7-87. MMC1 /2–High Speed –Receive Mode  
表7-72. MMC1/2 Switching Characteristics –High Speed Mode  
see 图7-88  
NO.  
PARAMETER  
Operating frequency, MMC[x]_CLK  
Cycle time. MMC[x]_CLK  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
50  
HS5  
HS6  
HS7  
HS8  
HS9  
tc(clk)  
20  
9.2  
tw(clkH)  
Pulse duration, MMC[x]_CLK high  
Pulse duration, MMC[x]_CLK low  
ns  
tw(clkL)  
9.2  
ns  
td(clkL-cmdV)  
td(clkL-dV)  
Delay time, MMC[x]_CLK falling edge to MMC[x]_CMD transition  
2.07  
2.07  
ns  
–2.07  
–2.07  
Delay time, MMC[x]_CLK falling edge to MMC[x]_DAT[3:0]  
transition  
ns  
HS5  
HS6  
HS7  
MMC[x]_CLK  
HS8  
HS9  
MMC[x]_CMD  
MMC[x]_DAT[3:0]  
图7-88. MMC1/2 –High Speed –Transmit Mode  
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7.10.5.17.2.3 UHS–I SDR12 Mode  
表 7-73, 图 7-89, 表 7-74, and 图 7-90 present timing requirements and switching characteristics for MMC1/2 –  
UHS-I SDR12 Mode.  
表7-73. MMC1/2 Timing Requirements –UHS-I SDR12 Mode  
see 图7-89  
NO.  
MIN  
5.46  
1.67  
5.46  
1.67  
MAX  
UNIT  
ns  
SDR121 tsu(cmdV-clkH)  
SDR122 th(clkH-cmdV)  
SDR123 tsu(dV-clkH)  
SDR124 th(clkH-dV)  
Setup time, MMC[x]_CMD valid before MMC[x]_CLK rising edge  
Hold time, MMC[x]_CMD valid after MMC[x]_CLK rising edge  
Setup time, MMC[x]_DAT[3:0] valid before MMC[x]_CLK rising edge  
Hold time, MMC[x]_DAT[3:0] valid after MMC[x]_CLK rising edge  
ns  
ns  
ns  
A. x = 1, 2 for MMC1 and MMC2  
B. x = 1, 2 for MMC1 and MMC2  
MMC[x]_CLK  
MMC[x]_CMD  
SDR122  
SDR124  
SDR121  
SDR123  
MMC[x]_DAT[3:0]  
图7-89. MMC1/2 –UHS-I SDR12 –Receive Mode  
表7-74. MMC1/2 Switching Characteristics –UHS-I SDR12 Mode  
see 图7-90  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
Operating frequency, MMC[x]_CLK  
25  
SDR125 tc(clk)  
Cycle time, MMC[x]_CLK  
40  
18.7  
18.7  
1.2  
SDR126 tw(clkH)  
SDR127 tw(clkL)  
SDR128 td(clkH-cmdV)  
SDR129 td(clkH-dV)  
Pulse duration, MMC[x]_CLK high  
ns  
Pulse duration, MMC[x]_CLK low  
ns  
Delay time, MMC[x]_CLK rising edge to MMC[x]_CMD transition  
Delay time, MMC[x]_CLK rising edge to MMC[x]_DAT[3:0] transition  
13.55  
13.55  
ns  
1.2  
ns  
SDR125  
SDR126  
SDR127  
MMC[x]_CLK  
SDR128  
SDR128  
MMC[x]_CMD  
SDR129  
SDR129  
MMC[x]_DAT[3:0]  
图7-90. MMC1/2 –UHS-I SDR12 –Transmit Mode  
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ZHCSRF7 –DECEMBER 2022  
7.10.5.17.2.4 UHS–I SDR25 Mode  
表 7-75, 图 7-91, 表 7-76, and 图 7-92 present timing requirements and switching characteristics for MMC1/2 –  
UHS-I SDR25 Mode.  
表7-75. MMC1/2 Timing Requirements –UHS-I SDR25 Mode  
see 图7-91  
NO.  
MIN  
2.1  
MAX  
UNIT  
ns  
SDR251 tsu(cmdV-clkH)  
SDR252 th(clkH-cmdV)  
SDR253 tsu(dV-clkH)  
SDR254 th(clkH-dV)  
Setup time, MMC[x]_CMD valid before MMC[x]_CLK rising edge  
Hold time, MMC[x]_CMD valid after MMC[x]_CLK rising edge  
Setup time, MMC[x]_DAT[3:0] valid before MMC[x]_CLK rising edge  
Hold time, MMC[x]_DAT[3:0] valid after MMC[x]_CLK rising edge  
1.67  
2.1  
ns  
ns  
1.67  
ns  
A. x = 1, 2 for MMC1 and MMC2  
B. x = 1, 2 for MMC1 and MMC2  
MMC[x]_CLK  
MMC[x]_CMD  
SDR252  
SDR254  
SDR251  
SDR253  
MMC[x]_DAT[3:0]  
图7-91. MMC1/2 –UHS-I SDR25 –Receive Mode  
表7-76. MMC1/2 Switching Characteristics –UHS-I SDR25 Mode  
see 图7-92  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
Operating frequency, MMC[x]_CLK  
50  
SDR255 tc(clk)  
Cycle time, MMC[x]_CLK  
20  
9.2  
9.2  
2.4  
2.4  
SDR256 tw(clkH)  
SDR257 tw(clkL)  
SDR258 td(clkH-cmdV)  
SDR259 td(clkH-dV)  
Pulse duration, MMC[x]_CLK high  
ns  
Pulse duration, MMC[x]_CLK low  
ns  
Delay time, MMC[x]_CLK rising edge to MMC[x]_CMD transition  
Delay time, MMC[x]_CLK rising edge to MMC[x]_DAT[3:0] transition  
9.37  
9.37  
ns  
ns  
SDR255  
SDR256  
SDR257  
MMC[x]_CLK  
SDR258  
SDR258  
MMC[x]_CMD  
SDR259  
SDR259  
MMC[x]_DAT[3:0]  
图7-92. MMC1/2 –UHS-I SDR25 –Transmit Mode  
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7.10.5.17.2.5 UHS–I SDR50 Mode  
表7-77, and 图7-93 presents switching characteristics for MMC1/2 –UHS-I SDR50 Mode.  
表7-77. MMC1/2 Switching Characteristics –UHS-I SDR50 Mode  
see 图7-93  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
Operating frequency, MMC[x]_CLK  
100  
SDR505 tc(clk)  
Cycle time, MMC[x]_CLK  
10  
4.45  
4.45  
1.2  
SDR506 tw(clkH)  
SDR507 tw(clkL)  
SDR508 td(clkH-cmdV)  
SDR509 td(clkH-dV)  
Pulse duration, MMC[x]_CLK high  
ns  
Pulse duration, MMC[x]_CLK low  
ns  
Delay time, MMC[x]_CLK rising edge to MMC[x]_CMD transition  
Delay time, MMC[x]_CLK rising edge to MMC[x]_DAT[3:0] transition  
6.35  
6.35  
ns  
1.2  
ns  
A. x = 1, 2 for MMC1 and MMC2  
SDR505  
SDR506  
SDR507  
MMC[x]_CLK  
MMC[x]_CMD  
SDR508  
SDR508  
SDR509  
SDR509  
MMC[x]_DAT[3:0]  
图7-93. MMC1/2 –UHS-I SDR50 –Transmit Mode  
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7.10.5.17.2.6 UHS–I DDR50 Mode  
表7-78 and 图7-94 present switching characteristics for MMC1/2 –UHS-I DDR50 Mode.  
表7-78. MMC1/2 Switching Characteristics –UHS-I DDR50 Mode  
see 图7-94  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
Operating frequency, MMC[x]_CLK  
40  
DDR505  
DDR506  
DDR507  
DDR508  
DDR509  
tc(clk)  
Cycle time, MMC[x]_CLK  
25  
9.2  
tw(clkH)  
tw(clkL)  
td(clkH-cmdV)  
td(clk-dV)  
Pulse duration, MMC[x]_CLK high  
ns  
Pulse duration, MMC[x]_CLK low  
9.2  
ns  
Delay time, MMC[x]_CLK rising edge to MMC[x]_CMD transition  
Delay time, MMC[x]_CLK transition to MMC[x]_DAT[3:0] transition  
1.12  
1.12  
3.46  
6.12  
ns  
ns  
A. x = 1, 2 for MMC1 and MMC2  
DDR505  
DDR506  
DDR507  
MMC[x]_CLK  
MMC[x]_CMD  
DDR508  
DDR509  
DDR509  
MMC[x]_DAT[3:0]  
图7-94. MMC1/2 –UHS-I DDR50 –Transmit Mode  
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7.10.5.17.2.7 UHS–I SDR104 Mode  
表7-79, and 图7-95 present switching characteristics for MMC1/2 –UHS-I SDR104 Mode.  
表7-79. MMC1/2 Switching Characteristics –UHS-I SDR104 Mode  
see 图7-95  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
Operating frequency, MMC[x]_CLK  
200  
SDR1045 tc(clk)  
Cycle time, MMC[x]_CLK  
5
2.12  
2.12  
1.07  
1.07  
SDR1046 tw(clkH)  
SDR1047 tw(clkL)  
SDR1048 td(clkH-cmdV)  
SDR1049 td(clkH-dV)  
Pulse duration, MMC[x]_CLK high  
ns  
Pulse duration, MMC[x]_CLK low  
ns  
Delay time, MMC[x]_CLK rising edge to MMC[x]_CMD transition  
Delay time, MMC[x]_CLK rising edge to MMC[x]_DAT[3:0] transition  
3.21  
3.21  
ns  
ns  
A. x = 1, 2 for MMC1 and MMC2  
SDR1045  
SDR1046  
SDR1047  
MMC[x]_CLK  
MMC[x]_CMD  
SDR1048  
SDR1048  
SDR1049  
SDR1049  
MMC[x]_DAT[3:0]  
图7-95. MMC1/2 –UHS-I SDR104 –Transmit Mode  
7.10.5.18 CPTS  
表7-80 represents CPTS timing conditions.  
表7-80. CPTS Timing Conditions  
PARAMETER  
DESCRIPTION  
MIN  
0.5  
2
MAX  
5
UNIT  
INPUT CONDITIONS  
SRI  
Input slew rate  
V/ns  
pF  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
10  
节 7.10.5.18.1, 节 7.10.5.18.2, 图 7-96, and 图 7-97 present timing requirements and switching characteristics of  
the CPTS interface.  
7.10.5.18.1 CPTS Timing Requirements  
see 图7-96  
NO.  
T1  
T2  
T3  
T4  
T5  
MIN  
12P + 2(1)  
12P + 2(1)  
5
MAX UNIT  
tw(HWnTSPUSHH)  
tw(HWnTSPUSHL)  
tc(RFT_CLK)  
Pulse duration, HWnTSPUSH(2) high  
Pulse duration, HWnTSPUSH(2) low  
Cycle time, RFT_CLK  
ns  
ns  
8
ns  
ns  
ns  
tw(RFT_CLKH)  
tw(RFT_CLKL)  
Pulse duration, RFT_CLK high  
Pulse duration, RFT_CLK low  
0.45 * T(3)  
0.45 * T(3)  
(1) P = functional clock period in ns.  
(2) In HWnTSPUSH, n = 1 to 2.  
(3) T = RFT_CLK period in ns.  
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T1  
T2  
HWn_TSPUSH  
T3  
T4  
T5  
RFT_CLK  
图7-96. CPTS Timing Requirements  
7.10.5.18.2 CPTS Switching Characteristics  
see 图7-97  
NO.  
PARAMETER  
SOURCE  
MIN  
36P - 2(1)  
36P - 2(1)  
36P - 2(1)  
36P - 2(1)  
36P - 2(1)  
5P - 2(1)  
MAX UNIT  
T6  
tw(TS_COMPH)  
tw(TS_COMPL)  
tw(TS_SYNCH)  
tw(TS_SYNCL)  
Pulse duration, TS_COMP high  
Pulse duration, TS_COMP low  
Pulse duration, TS_SYNC high  
Pulse duration, TS_SYNC low  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
T7  
T8  
T9  
TS_SYNC  
T10  
T11  
tw(SYNC_OUTH)  
Pulse duration, SYNCn_OUT(2) high  
Pulse duration, SYNCn_OUT(2) low  
TS_GENF  
TS_SYNC  
TS_GENF  
36P - 2(1)  
5P - 2(1)  
tw(SYNC_OUTL)  
(1) P = functional clock period in ns.  
(2) n = 0 to 3 in SYNCn_OUT  
T6  
T7  
TS_COMP  
T8  
T9  
TS_SYNC  
T10  
T11  
SYNCn_OUT  
图7-97. CPTS Switching Characteristics  
For more information, see Navigator Subsystem (NAVSS) section in Data Movement Architecture (DMA) chapter  
in the device TRM.  
7.10.5.19 OSPI  
For more details about features and additional description information on the device Octal Serial Peripheral  
Interface, see the corresponding sections within Signal Descriptions and Detailed Description.  
表7-81 represents OSPI timing conditions.  
表7-81. OSPI Timing Conditions  
PARAMETER  
INPUT CONDITIONS  
SRI  
MIN  
MAX  
UNIT  
Input slew rate  
3.3 V  
2
1
6
6
V/ns  
V/ns  
All other modes  
OUTPUT CONDITIONS  
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表7-81. OSPI Timing Conditions (continued)  
PARAMETER  
MIN  
MAX  
UNIT  
CL  
Output load capacitance  
All modes  
3
10  
pF  
PCB CONNECTIVITY REQUIREMENTS  
td(Trace Delay)  
Propagation delay  
OSPI_CLK trace  
No Loopback;  
Internal Pad  
Loopback  
ps  
450  
Propagation delay  
OSPI_LBCLKO trace  
External Board  
Loopback  
ps  
ps  
ps  
2*L-30(2)  
L-30(2)  
2*L+30(2)  
L+30(2)  
Propagation delay  
OSPI_DQS trace  
DQS  
td(Trace Mismatch Delay)  
Propagation delay mismatch  
OSPI_D[i:0](1), OSPI_CSn  
relative to OSPI_CLK  
All modes  
60  
(1) i in D[i:0] = 0 to 7 for OSPI0; i in [i:0] = 3 for OSPI1  
(2) L = Propagation delay of OSPI_CLK trace  
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7.10.5.19.1 OSPI0 PHY Mode  
7.10.5.19.1.1 OSPI With Data Training  
备注  
I/O timing requirements and switching characteristics are not applicable when OSPI is used with data  
training. Follow the OSPI and QSPI Board Design and Layout Guidelines section to ensure proper  
operation.  
7.10.5.19.1.1.1 OSPI Switching Characteristics –Data Training  
PARAMETER  
DESCRIPTION  
MODE  
MIN  
6
MAX  
UNIT  
ns  
tc(CLK)  
Cycle time, CLK  
Cycle time, CLK  
DDR, 1.8V  
DDR, 3.3V  
SDR, 1.8V  
SDR, 3.3V  
7.5  
6
ns  
tc(CLK)  
ns  
7.5  
ns  
7.10.5.19.1.2 OSPI Without Data Training  
备注  
The I/O Timings provided in this section are only applicable when data training is not implemented.  
Additionally, the I/O Timings are valid only for some OSPI usage modes when the corresponding DLL  
Delays are configured as described in 表7-82 found in this section.  
节 7.10.5.19.1.2.4, 节 7.10.5.19.1.2.2, 节 7.10.5.19.1.2, and 节 7.10.5.19.1.2 present switching characteristics  
for OSPI DDR and SDR Mode.  
7.10.5.19.1.2.1 OSPI Timing Requirements –SDR Mode  
表7-82. OSPI DLL Delay Mapping - SDR Timing Modes  
MODE  
OSPI_PHY_CONFIGURATION_REG BIT FIELD  
PHY_CONFIG_TX_DLL_DELAY_FLD  
PHY_CONFIG_RX_DLL_DELAY_FLD  
DELAY VALUE  
All modes  
0x0  
0x0  
表7-83. OSPI Timing Requirements –SDR Mode  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
MIN  
0.6  
0.9  
1.7  
2
MAX  
UNIT  
ns  
O21 tsu(D-LBCLK)  
Setup time, D[i:0] valid before active LBCLK  
input (DQS) edge(1)  
1.8V, External Board Loopback  
3.3V, External Board Loopback  
1.8V, External Board Loopback  
3.3V, External Board Loopback  
ns  
O22 th(LBCLK-D)  
Hold time, D[i:0] valid after active LBCLK  
input (DQS) edge(1)  
ns  
ns  
(1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1  
OSPI_DQS  
O21  
O22  
OSPI_D[i:0]  
OSPI_TIMING_06  
图7-98. OSPI Timing Requirements –SDR, External Loopback Clock  
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7.10.5.19.1.2.2 OSPI Switching Characteristics –SDR Mode  
NO. PARAMETER  
DESCRIPTION  
MODE  
1.8V  
MIN  
7
MAX  
UNIT  
ns  
O7 tc(CLK)  
Cycle time, CLK  
3.3V  
7.5  
ns  
O8 tw(CLKL)  
Pulse duration, CLK low  
Pulse duration, CLK high  
ns  
–
0.3+0.475*P  
(2)  
O9  
ns  
–
0.3+0.475*P  
(2)  
O10 ttd(CSn-CLK)  
Delay time, CSn[3:0] active edge to CLK rising  
edge  
1.8V  
3.3V  
1.8V  
3.3V  
0.475 * P +  
0.525 * P +  
ns  
ns  
ns  
ns  
0.975 * M * R 1.025 * M * R  
- 7 (2) (3) (5)  
+ 1 (2) (3) (5)  
0.475 * P +  
0.525 * P +  
0.975 * M * R 1.025 * M * R  
- 7(2) (3) (5)  
+ 1 (2) (3) (5)  
O11 td(CLK-CSn)  
Delay time, CLK rising edge to CSn inactive  
edge  
0.475 * P +  
0.525 * P +  
0.975 * N * R 1.025 * N * R  
- 1 (2) (4) (5)  
+ 1 (2) (4) (5)  
0.475 * P +  
0.525 * P +  
0.975 * N * R 1.025 * N * R  
- 1 (2) (4) (5)  
+ 1(2) (4) (5)  
O12 td(CLK-D)  
Delay time, CLK active edge to D[i:0]  
transition(1)  
1.8V  
3.3V  
1.25  
ns  
ns  
–1.16  
1.51  
–1.33  
(1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1  
(2) P = CLK cycle time = SCLK period  
(3) M = OSPI_DEV_DELAY_REG[D_INIT_FLD]  
(4) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]  
(5) R = refclk  
OSPI_CSn  
O11  
O10  
O7  
O9  
O8  
OSPI_CLK  
OSPI_D[i:0]  
O12  
OSPI_TIMING_02  
图7-99. OSPI Switching Characteristics –SDR  
节 7.10.5.19.1.2.3, 节 7.10.5.19.1.2.1, 节 7.10.5.19.1.2.2, 节 7.10.5.19.1.2.2, and 图 7-98 presents timing  
requirements for OSPI DDR and SDR Mode.  
7.10.5.19.1.2.3 OSPI Timing Requirements –DDR Mode  
表7-84. OSPI DLL Delay Mapping - DDR Timing Modes  
OSPI0  
OSPI1  
OSPI_PHY_CONFIGURATION_REG  
BIT FIELD  
MODE  
DELAY VALUE  
TRANSMIT  
1.8V  
PHY_CONFIG_TX_DLL_DELAY_FLD  
0x54  
0x54  
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表7-84. OSPI DLL Delay Mapping - DDR Timing Modes (continued)  
OSPI0  
OSPI1  
OSPI_PHY_CONFIGURATION_REG  
BIT FIELD  
MODE  
DELAY VALUE  
3.3V  
PHY_CONFIG_TX_DLL_DELAY_FLD  
0x55  
0x5C  
RECEIVE  
1.8V, DQS  
3.3V, DQS  
All other modes  
PHY_CONFIG_RX_DLL_DELAY_FLD  
PHY_CONFIG_RX_DLL_DELAY_FLD  
PHY_CONFIG_RX_DLL_DELAY_FLD  
0x23  
0x47  
0x0  
0x29  
0x42  
0x0  
表7-85. OSPI Timing Requirements –DDR Mode  
NO. PARAMETER  
DESCRIPTION  
MODE  
MIN  
MAX  
UNIT  
ns  
O15 tsu(D-LBCLK)  
Setup time, D[i:0] valid before active LBCLK (DQS) 1.8V, External Board Loopback  
0.52  
1.97  
edge(1)  
3.3V, External Board Loopback  
ns  
O16 th(LBCLK-D)  
Hold time, D[i:0] valid after active LBCLK (DQS)  
edge(1)  
1.8V, External Board Loopback 1.24 (2)  
ns  
3.3V, External Board Loopback 1.44 (2)  
ns  
O17 tsu(D-DQS)  
Setup time, DQS edge to D[i:0] transition(1)  
1.8V, DQS  
ns  
–0.46  
3.3V, DQS  
1.8V, DQS  
3.3V, DQS  
ns  
–0.66  
3.59  
O18 th(DQS-D)  
Hold time, DQS edge to D[i:0] transition(1)  
ns  
8.89  
ns  
(1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1  
(2) This Hold time requirement is larger than the Hold time provided by a typical flash device. Therefore, the trace length between the SoC  
and flash device must be sufficiently long enough to ensure that the Hold time is met at the SoC. Refer to OSPI and QSPI Board  
Design and Layout Guidelines for more details.  
OSPI_DQS  
O15 O16  
OSPI_D[i:0]  
OSPI_TIMING_04  
图7-100. OSPI Timing Requirements –DDR, External Loopback Clock and DQS  
7.10.5.19.1.2.4 OSPI Switching Characteristics –DDR Mode  
NO. PARAMETER  
DESCRIPTION  
MODE  
1.8V  
MIN  
19  
MAX  
UNIT  
ns  
O1 tc(CLK)  
Cycle time, CLK  
3.3V  
19  
ns  
O2 tw(CLKL)  
O3 tw(CLKH)  
O4 td(CLK-CSn)  
Pulse duration, CLK low  
0.475*P - 0.3  
ns  
(2)  
Pulse duration, CLK high  
0.475*P - 0.3  
ns  
ns  
(2)  
Delay time, CSn active edge to CLK rising edge  
1.8V  
3.3V  
0.475 * P +  
0.525 * P +  
0.975 * M * R 1.025 * M * R  
- 7 (2) (3) (5)  
+ 1(2) (3) (5)  
0.475 * P +  
0.525 * P +  
ns  
0.975 * M * R 1.025 * M * R  
- 7(2) (3) (5) + 1(2) (3) (5)  
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UNIT  
NO. PARAMETER  
DESCRIPTION  
MODE  
MIN  
MAX  
0.525 * P +  
O5 td(CLK-CSn)  
Delay time, CLK rising edge to CSn inactive  
edge  
1.8V  
0.475 * P +  
ns  
0.975 * N * R 1.025 * N * R  
- 7(2) (4) (5)  
+ 1 (2) (4) (5)  
3.3V, OSPI0 DDR TX; 0.475 * P +  
0.525 * P +  
ns  
3.3V, OSPI1 DDR TX 0.975 * N * R 1.025 * N * R  
- 7(2) (4) (5)  
+ 1 (2) (4) (5)  
O6 td(CLK-D)  
Delay time, CLK active edge to D[i:0]  
transition(1)  
1.8V, OSPI0 DDR TX;  
1.8V, OSPI1 DDR TX  
ns  
ns  
–7.71  
–1.56  
3.3V, OSPI0 DDR TX;  
3.3V, OSPI1 DDR TX  
–7.71  
–1.56  
(1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1  
(2) P = CLK cycle time = SCLK period  
(3) N = OSPI_DEV_DELAY_REG[D_INIT_FLD]  
(4) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]  
(5) R = refclk  
OSPI_CSn  
O4  
O3  
O5  
OSPI_CLK  
O2  
O1  
O6  
O6  
OSPI_D[i:0]  
OSPI_TIMING_01  
图7-101. OSPI Switching Characteristics –DDR  
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7.10.5.19.2 OSPI0 Tap Mode  
7.10.5.19.2.1 OSPI0 Tap SDR Timing  
表 7-86, 图 7-102, 表 7-87, and 图 7-103 present timing requirements and switching characteristics for OSPI0  
Tap SDR Mode.  
表7-86. OSPI0/1 Timing Requirements –Tap SDR Mode  
see 图7-102  
NO.  
MODE  
MIN  
MAX UNIT  
Setup time, OSPI0/1_D[7:0] valid before  
active OSPI0/1_CLK edge  
(10.4 -  
O19 tsu(D-CLK)  
No Loopback  
ns  
(0.975T(1)R(2)))  
Hold time, OSPI0/1_D[7:0] valid after  
active OSPI0/1_CLK edge  
(–0.2 +  
O20 th(CLK-D)  
No Loopback  
ns  
(0.975T(1)R(2)))  
(1) T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD]  
(2) R = refclk cycle time in ns  
OSPI_CLK  
O19  
O20  
OSPI_D[i:0]  
OSPI_TIMING_05  
图7-102. OSPI0/1 Timing Requirements –Tap SDR, No Loopback  
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表7-87. OSPI0/1 Switching Characteristics –Tap SDR Mode  
see 图7-103  
NO.  
PARAMETER  
MODE  
MIN  
20  
MAX UNIT  
O7  
O8  
O9  
tc(CLK)  
tw(CLKL)  
tw(CLKH)  
Cycle time, OSPI0/1_CLK  
ns  
ns  
ns  
Pulse duration, OSPI0/1_CLK low  
Pulse duration, OSPI0/1_CLK high  
((0.475P(1)) - 0.3)  
((0.475P(1)) - 0.3)  
Delay time, OSPI0/1_CSn[3:0] active edge  
to OSPI0/1_CLK rising edge  
((0.475P(1)) +  
((0.525P(1)) +  
O10 td(CSn-CLK)  
O11 td(CLK-CSn)  
O12 td(CLK-D)  
ns  
ns  
ns  
(0.975M(2)R(4)) - 1) (1.025M(2)R(4)) + 1)  
Delay time, OSPI0/1_CLK rising edge to  
OSPI0/1_CSn[3:0] inactive edge  
((0.475P(1)) +  
((0.525P(1)) +  
(0.975N(3)R(4)) - 1) (1.025N(3)R(4)) + 1)  
Delay time, OSPI0/1_CLK active edge to  
OSPI0/1_D[7:0] transition  
2
–2  
(1) P = CLK cycle time = SCLK period in ns  
(2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD]  
(3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]  
(4) R = refclk cycle time in ns  
OSPI_CSn  
O11  
O10  
O7  
O9  
O8  
OSPI_CLK  
OSPI_D[i:0]  
O12  
OSPI_TIMING_02  
图7-103. OSPI0/1 Switching Characteristics –Tap SDR, No Loopback  
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7.10.5.19.2.2 OSPI0 Tap DDR Timing  
表 7-88, 图 7-104, 表 7-89, and 图 7-105 present timing requirements and switching characteristics for OSPI0  
Tap DDR Mode.  
表7-88. OSPI0/1 Timing Requirements –Tap DDR Mode  
see 图7-104  
NO.  
MODE  
MIN  
MAX UNIT  
Setup time, OSPI0/1_D[7:0] valid before  
active OSPI0/1_CLK edge  
(12.04 -  
O13 tsu(D-CLK)  
No Loopback  
ns  
(0.975T(1)R(2)))  
Hold time, OSPI0/1_D[7:0] valid after  
active OSPI0/1_CLK edge  
(1.84 +  
O14 th(CLK-D)  
No Loopback  
ns  
(0.975T(1)R(2)))  
(1) T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD]  
(2) R = refclk cycle time in ns  
OSPI_CLK  
O13 O14 O13 O14  
OSPI_D[i:0]  
OSPI_TIMING_03  
图7-104. OSPI0/1 Timing Requirements –Tap DDR, No Loopback  
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表7-89. OSPI0/1 Switching Characteristics –Tap DDR Mode  
see 图7-105  
NO.  
PARAMETER  
MODE  
MIN  
40  
MAX UNIT  
O1  
O2  
O3  
tc(CLK)  
tw(CLKL)  
tw(CLKH)  
Cycle time, OSPI0/1_CLK  
ns  
ns  
ns  
Pulse duration, OSPI0/1_CLK low  
Pulse duration, OSPI0/1_CLK high  
((0.475P(1)) - 0.3)  
((0.475P(1)) - 0.3)  
Delay time, OSPI0/1_CSn[3:0] active edge  
to OSPI0/1_CLK rising edge  
((0.475P(1)) +  
((0.525P(1)) +  
O4  
O5  
O6  
td(CSn-CLK)  
td(CLK-CSn)  
td(CLK-D)  
ns  
ns  
ns  
((0.975M(2)R(4)) - 1) (1.025M(2)R(4)) + 1)  
Delay time, OSPI0/1_CLK rising edge to  
OSPI0/1_CSn[3:0] inactive edge  
((0.475P(1)) +  
((0.525P(1)) +  
(0.975N(3)R(4)) - 1) (1.025N(3)R(4)) + 1)  
Delay time, OSPI0/1_CLK active edge to  
OSPI0/1_D[7:0] transition  
(–17.94 +  
(–1.56 +  
(0.975T(5)R(4)))  
(1.025T(5)R(4)))  
(1) P = CLK cycle time = SCLK period in ns  
(2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD]  
(3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]  
(4) R = refclk cycle time in ns  
(5) T = OSPI_RD_DATA_CAPTURE_REG[DDR_READ_DELAY_FLD]  
OSPI_CSn  
O4  
O3  
O5  
OSPI_CLK  
O2  
O6  
O6  
O1  
OSPI_D[i:0]  
OSPI_TIMING_01  
图7-105. OSPI0/1 Switching Characteristics –Tap DDR, No Loopback  
7.10.5.20 OLDI  
7.10.5.20.1 OLDI Switching Characteristics  
NO.  
O1  
O2  
O3  
O4  
O5  
O6  
O7  
O8  
PARAMETER  
MODE  
IOSET1  
IOSET1  
IOSET1  
IOSET1  
IOSET1  
IOSET1  
IOSET1  
IOSET1  
MIN  
0.18  
0.18  
1
MAX  
0.5  
UNIT  
ns  
LVDS Low-to-High Transition Time max  
LVDS high-to-low Transition Time max  
Transmitter Output Bit Width min  
0.5  
ns  
1
UI  
0.25  
-0.06  
0.75  
0.06  
110  
0.035  
0.25  
ns  
Transmitter Pulse Positions –Normalized  
Variation in transmitter pulse position across Bit 7:0 pulse positions  
TxOut Channel to Channel Skew  
ns  
ns  
Transmitter Jitter Cycle-to-Cycle  
0.028  
ns  
Input Total Jitter Tolerance (Includes data to clock skew, pulse position  
variation.)  
ns  
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T
OLDI_CLK  
bit 0  
bit 1  
bit 0  
3UI  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
1UI  
OLDI_DATA[3:0]  
tTPP1  
tTPP2  
tTPP3  
tTPP4  
tTPP5  
tTPP6  
tTPP7  
2UI  
ΔtTPP  
4UI  
5UI  
6UI  
7UI  
图7-106. OLDI Transmitter Pulse Positions  
Ideal Data  
Bit Beginning  
Ideal Data  
Bit End  
Sampling  
Window  
VTH  
OLDI_DATA[3:0]  
0 V  
VTL  
DATA_TOL  
Right  
DATA_TOL  
Left  
Ideal Center Position (tBIT/2)  
tBIT (1UI)  
图7-107. OLDI Data Output Jitter  
+VOD  
80%  
80%  
VSS=2|VOD|  
OLDI_CLK  
0 V  
20%  
20%  
LLHT  
-VOD  
LLHT  
图7-108. LVDS Output Transition Times  
For more information, see Display Subsystem (DSS) and Peripherals section in Peripherals chapter in the device  
TRM.  
7.10.5.21 PCIE  
The PCI-Express Subsystem is compliant with the PCIe® Base Specification, Revision 4.0. Refer to the  
specification for timing details.  
For more details about features and additional description information on the device Peripheral Component  
Interconnect Express, see the corresponding sections within Signal Descriptions and Detailed Description.  
For more information, see Peripheral Component Interconnect Express (PCIe) Subsystem section in Peripherals  
chapter in the device TRM.  
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7.10.5.22 Timers  
For more details about features and additional description information on the device Timers, see the  
corresponding sections within Signal Descriptions and Detailed Description.  
表7-90 represents Timers timing conditions.  
表7-90. Timers Timing Conditions  
PARAMETER  
DESCRIPTION  
MODE  
CAPTURE  
PWM  
MIN  
0.5  
2
MAX  
5
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
10  
节7.10.5.22.1, 节7.10.5.22.2 and 图7-109 present timings and switching characteristics of the Timers.  
7.10.5.22.1 Timing Requirements for Timers  
NO.  
PARAMETER  
tw(TINPH)  
DESCRIPTION  
MODE  
MIN  
MAX UNIT  
T1  
Pulse duration, high  
Pulse duration, low  
CAPTURE  
2.5 +  
4P(1)  
ns  
T2  
tw(TINPL)  
CAPTURE  
2.5 +  
4P(1)  
ns  
(1) P = functional clock period in ns.  
7.10.5.22.2 Switching Characteristics for Timers  
NO.  
PARAMETER  
tw(TOUTH)  
DESCRIPTION  
MODE  
MIN  
MAX  
UNIT  
T3  
Pulse duration, high  
Pulse duration, low  
PWM  
-2.5 +  
4P(1)  
ns  
T4  
tw(TOUTL)  
PWM  
-2.5 +  
4P(1)  
ns  
(1) P = functional clock period in ns.  
T1  
T2  
TIMER_IOx (inputs)  
T3  
T4  
TIMER_IOx (outputs)  
TIMER_01  
图7-109. Timer Timing  
For more information, see Timers section in Peripherals chapter in the device TRM.  
7.10.5.23 UART  
For more details about features and additional description information on the device Universal Asynchronous  
Receiver Transmitter, see the corresponding sections within , Signal Descriptions and Detailed Description.  
表7-91 represents UART timing conditions.  
表7-91. UART Timing Conditions  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
INPUT CONDITIONS  
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表7-91. UART Timing Conditions (continued)  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
SRI  
Input slew rate  
0.5  
5
V/ns  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
1
30(1)  
pF  
(1) This value represents an absolute maximum load capacitance. As the UART baud rate increases, it may be necessary to reduce the  
load capacitance to a value less than this maximum limit to provide enough timing margin for the attached device. The output rise/fall  
times increase as capacitive load increases, which decreases the time data is valid for the receiver of the attached devices. Therefore,  
it is important to understand the minimum data valid time required by the attached device at the operating baud rate. Then use the  
device IBIS models to verify the actual load capacitance on the UART signals does not increase the rise/fall times beyond the point  
where the minimum data valid time of the attached device is violated.  
节 7.10.5.23.1, 节 7.10.5.23.2, and 图 7-110 present timing requirements and switching characteristics for UART  
interface.  
7.10.5.23.1 Timing Requirements for UART  
NO.  
PARAMETER  
tw(rxd)  
DESCRIPTION  
MODE  
MIN  
MAX  
UNIT  
4
Pulse width, receive data bit, high or low  
0.95U(1) 1.05U(1)  
ns  
(2)  
(2)  
5
tw(rxdS)  
Pulse width, receive start bit, low  
0.95U(1)  
ns  
(2)  
(1) U = UART baud time = 1/Programmed baud rate  
(2) This value defines the data valid time, where the input voltage is required to be above VIH or below VIL.  
7.10.5.23.2 UART Switching Characteristics  
NO.  
PARAMETER  
f(baud)  
DESCRIPTION  
Maximum programmable baud rate  
MIN  
MAX  
UNIT  
Mbps  
ns  
12  
2
3
tw(TX)  
Pulse width, transmit data bit, high or low  
Pulse width, transmit start bit, high or low  
U - 2(1)  
U - 2(1)  
U + 2(1)  
tw(RTS)  
ns  
(1) U = UART baud time = 1/Programmed baud rate  
2
1
Start  
Bit  
VIH  
VIL  
UARTi_RXD  
Data Bits  
4
3
Start  
Bit  
UARTi_TXD  
Data Bits  
UART_TIMING_01_RCVRVIHVIL  
图7-110. UART Timing  
For more information, see Universal Asynchronous Receiver/Transmitter (UART) section in Peripherals chapter  
in the device TRM.  
7.10.5.24 USB  
The USB 2.0 subsystem is compliant with the Universal Serial Bus (USB) Specification, revision 2.0. Refer to the  
specification for timing details.  
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The USB 3.1 GEN1 Dual-Role Device Subsystem is compliant with the Universal Serial Bus (USB) 3.1  
Specification, revision 1.0. Refer to the specification for timing details.  
For more details about features and additional description information on the device Universal Serial Bus  
Subsystem (USB), see the corresponding sections within Signal Descriptions and Detailed Description.  
7.10.6 Emulation and Debug  
7.10.6.1 Trace  
表7-92. Trace Timing Conditions  
PARAMETER  
MIN  
MAX  
UNIT  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
2
5
pF  
PCB CONNECTIVITY REQUIREMENTS  
Propagation delay mismatch across  
all traces  
td(Trace Mismatch)  
200  
ps  
表 7-93 and 图 7-111 assume testing over the recommended operating conditions and electrical characteristic  
conditions.  
表7-93. Trace Switching Characteristics  
NO.  
PARAMETER  
MIN  
MAX UNIT  
1.8 V Mode  
DBTR1 tc(TRC_CLK)  
Cycle time, TRC_CLK  
6.50  
2.50  
2.50  
0.81  
0.81  
0.81  
0.81  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
DBTR2 tw(TRC_CLKH)  
DBTR3 tw(TRC_CLKL)  
Pulse width, TRC_CLK high  
Pulse width, TRC_CLK low  
DBTR4 tosu(TRC_DATAV-TRC_CLK)  
DBTR5 toh(TRC_CLK-TRC_DATAI)  
DBTR6 tosu(TRC_CTLV-TRC_CLK)  
DBTR7 toh(TRC_CLK-TRC_CTLI)  
3.3 V Mode  
Output setup time, TRC_DATA valid to TRC_CLK edge  
Output hold time, TRC_CLK edge to TRC_DATA invalid  
Output setup time, TRC_CTL valid to TRC_CLK edge  
Output hold time, TRC_CLK edge to TRC_CTL invalid  
DBTR1 tc(TRC_CLK)  
Cycle time, TRC_CLK  
9.75  
4.13  
4.13  
1.22  
1.22  
1.22  
1.22  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
DBTR2 tw(TRC_CLKH)  
DBTR3 tw(TRC_CLKL)  
Pulse width, TRC_CLK high  
Pulse width, TRC_CLK low  
DBTR4 tosu(TRC_DATAV-TRC_CLK)  
DBTR5 toh(TRC_CLK-TRC_DATAI)  
DBTR6 tosu(TRC_CTLV-TRC_CLK)  
DBTR7 toh(TRC_CLK-TRC_CTLI)  
Output setup time, TRC_DATA valid to TRC_CLK edge  
Output hold time, TRC_CLK edge to TRC_DATA invalid  
Output setup time, TRC_CTL valid to TRC_CLK edge  
Output hold time, TRC_CLK edge to TRC_CTL invalid  
DBTR1  
DBTR2  
DBTR3  
TRC_CLK  
(Worst Case 1)  
(Ideal)  
(Worst Case 2)  
DBTR4  
DBTR6  
DBTR5  
DBTR7  
DBTR4  
DBTR6  
DBTR5  
DBTR7  
TRC_DATA  
TRC_CTL  
SPRSP08_Debug_01  
图7-111. Trace Switching Characteristics  
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7.10.6.2 JTAG  
For more details about features and additional description information on the device IEEE 1149.1 Standard–  
Test–Access Port, see the corresponding sections within Signal Descriptions and Detailed Description.  
备注  
The JTAG signals are split across two IO power domains on the device. Timings parameters defined  
in this section only apply when the two IO power domains are operating at the same voltage and level-  
shifters are not inserted into the signal path. Values for the following timing parameters are not defined  
when operating the two IO power domains at different voltages since propagation delay through the  
device IO buffers differ when some are operating at 1.8 V while others are operating at 3.3 V. This  
effectively reduces timing margin beyond the values defined in this section. The JTAG interface is still  
expected to function when the two IO power domains are operated at different voltages, assuming the  
system designer has implemented appropriate level-shifters and the operating frequency is reduced to  
accommodate additional delay inserted by the level-shifters and IO buffers operating at different  
voltages.  
表7-94. JTAG Timing Conditions  
PARAMETER  
MIN  
0.50  
5
MAX  
2.00  
15  
UNIT  
V/ns  
pF  
Input Conditions  
SRI  
Input slew rate  
Output Conditions  
CL  
Output load capacitance  
PCB CONNECTIVITY REQUIREMENTS  
td(Trace Delay)  
Propagation delay of each trace  
Propagation delay mismatch across all traces  
83.5  
1000(1)  
100  
ps  
ps  
td(Trace Mismatch Delay)  
(1) Maximum propagation delay associated with the JTAG signal traces has a significant impact on maximum TCK operating frequency. It  
may be possible to increase the trace delay beyond this value, but the operating frequency of TCK must be reduced to account for the  
additional trace delay.  
7.10.6.2.1 JTAG Electrical Data and Timing  
节 7.10.6.2.1.1, 节 7.10.6.2.1.2, and 图 7-112 assume testing over the recommended operating conditions and  
electrical characteristic conditions.  
7.10.6.2.1.1 JTAG Timing Requirements  
See 图7-112  
NO.  
MIN  
46.5(1)  
18.6(2)  
18.6(2)  
4.5  
MAX UNIT  
J1  
tc(TCK)  
Cycle time minimum, TCK  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
J2  
tw(TCKH)  
Pulse width minimum, TCK high  
J3  
tw(TCKL)  
Pulse width minimum, TCK low  
tsu(TDI-TCK)  
tsu(TMS-TCK)  
th(TCK-TDI)  
th(TCK-TMS)  
Input setup time minimum, TDI valid to TCK high  
Input setup time minimum, TMS valid to TCK high  
Input hold time minimum, TDI valid from TCK high  
Input hold time minimum, TMS valid from TCK high  
J4  
J5  
4.5  
2
2
(1) The maximum TCK operating frequency assumes the following timing requirements and switching characteristics for the attached  
debugger. The operating frequency of TCK must be reduced to provide appropriate timing margin if the debugger exceeds any of these  
assumptions.  
•
•
Minimum TDO setup time of 4.6 ns relative to the rising edge of TCK  
TDI and TMS output delay in the range of –16.5 ns to 14.0 ns relative to the falling edge of TCK  
(2) P = TCK cycle time in ns  
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7.10.6.2.1.2 JTAG Switching Characteristics  
See 图7-112  
NO.  
PARAMETER  
MIN  
MAX UNIT  
J6  
J7  
td(TCKL-TDOI)  
td(TCKL-TDOV)  
Delay time minimum, TCK low to TDO invalid  
Delay time maximum, TCK low to TDO valid  
0
ns  
12  
ns  
1. The JTAG signals are split across two IO power domains on the device. Timings parameters defined in this  
table only apply when the two IO power domains are operating at the same voltage. Values for these timing  
parameters are not defined when operating the two IO power domains at different voltages since  
propagation delay through the device IO buffers differ when some are operating at 1.8V while others are  
operating at 3.3V. This effectively reduces timing margin beyond the values defined in this table. The JTAG  
interface is still expected to function when the two IO power domains are operated at different voltages,  
assuming the system designer has implemented appropriate level shifters and the operating frequency is  
reduced to accommodate additional delay inserted by the level-shifters and IO buffers operating at different  
voltages.  
J1  
J2  
J3  
TCK  
TDI / TMS  
TDO  
J4  
J5  
J4  
J5  
J7  
J6  
图7-112. JTAG Timing Requirements and Switching Characteristics  
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8 Applications, Implementation, and Layout  
备注  
Information in the following applications sections is not part of the TI component specification, and TI  
does not warrant its accuracy or completeness. TI’s customers are responsible for determining  
suitability of components for their purposes. Customers should validate and test design  
implementation to confirm system functionality.  
8.1 Device Connection and Layout Fundamentals  
8.1.1 Power Supply Decoupling and Bulk Capacitors  
8.1.1.1 Power Distribution Network Implementation Guidance  
The Sitara Processor Power Distribution Networks: Implementation and Analysis provides guidance for  
successful implementation of the power distribution network. This includes PCB stackup guidance as well as  
guidance for optimizing the selection and placement of the decoupling capacitors. TI supports only designs that  
follow the board design guidelines contained in the application report.  
8.1.2 External Oscillator  
For more information about External Oscillators, see Clock Specifications.  
8.1.3 JTAG and EMU  
Texas Instruments supports a variety of eXtended Development System (XDS) JTAG controllers with various  
debug capabilities beyond only JTAG support. A summary of this information is available in the XDS Target  
Connection Guide.  
For more recommendations on EMU routing, see Emulation and Trace Headers Technical Reference Manual  
8.1.4 Reset  
The device incorporates four external reset pins (MCU_PORz, MCU_RESETz, PORz, and RESET_REQz) and  
two reset status pins (MCU_RESETSTATz and RESETSTATz). These pins can be driven by an external power  
good circuitry or Power Management IC (PMIC). MCU_PORz and Main PORz pins should be held active low  
during the entire power-up phase, and until all power supplies as well as the HFOSC0 clock are stable.  
All MCU domain resets act as master resets to the whole device, whereas Main domain resets only reset Main  
domain (MCU domain is reset isolated from all Main domain resets).  
8.1.5 Unused Pins  
For more information about Unused Pins, see 节6.4  
8.1.6 Hardware Design Guide for JacintoTM 7 Devices  
The Hardware Design Guide for JacintoTM 7 Devices document describes hardware system design  
considerations for the JacintoTM 7 family of processors.This design guide is intended to be used as an aid during  
the development of application hardware.  
8.2 Peripheral- and Interface-Specific Design Information  
8.2.1 LPDDR4 Board Design and Layout Guidelines  
The goal of the Jacinto 7 DDR Board Design and Layout Guidelines is to make the LPDDR4 system  
implementation straightforward for all designers. Requirements have been distilled down to a set of layout and  
routing rules that allow designers to successfully implement a robust design for the topologies that TI supports.  
TI only supports board designs using LPDDR4 memories that follow the guidelines in this document.  
8.2.2 OSPI and QSPI Board Design and Layout Guidelines  
The following section details the routing guidelines that must be observed when routing the OSPI and QSPI  
interfaces.  
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8.2.2.1 No Loopback and Internal Pad Loopback  
• The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device  
• The signal propagation delay from the MCU_OSPI[x]_CLK signal to the flash device must be < 450 ps (~7cm  
as stripline or ~8cm as microstrip)  
• 50 ΩPCB routing is recommended along with series terminations, as shown in 图8-1  
• Propagation delays and matching:  
– A to B < 450 ps  
– Matching skew: < 60 ps  
A
B
R1  
0 Ω*  
OSPI/QSPI/SPI  
Device Clock Input  
MCU_OSPI[x]_CLK  
MCU_OSPI[x]_LBCLKO  
OSPI Device DQS  
MCU_OSPI[x]_DQS  
E
F
MCU_OSPI[x]_D[y],  
MCU_OSPI[x]_CSn[z]  
OSPI/QSPI/SPI  
Device IO[y], CS#  
MCU_OSPI_Board_01  
* 0 Ωresistor (R1), located as close as possible to the MCU_OSPI[x]_CLK pin, is placeholder for fine tuning, if needed.  
图8-1. OSPI Interface High Level Schematic  
8.2.2.2 External Board Loopback  
• The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device  
• The MCU_OSPI[x]_LBCLKO output signal must be looped back into the MCU_OSPI[x]_DQS input  
• The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B)  
should be approximately equal to half of the signal propagation delay from the MCU_OPSI[x]_LBCLKO pin to  
the MCU_OSPI[x]_DQS pin ((C to D)/2). See the note below.  
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• The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B) must  
be approximately equal to the signal propagation delay of the control and data signals between the flash  
device and the SoC device (E to F, or F to E)  
• 50 ΩPCB routing is recommended along with series terminations, as shown in 图8-2  
• Propagation delays and matching:  
– A to B = E to F = (C to D) / 2  
– Matching skew: < 60 ps  
备注  
The OSPI Board Loopback Hold time requirement (described in OSPI) is larger than the Hold time  
provided by a typical flash device. Therefore, the length of MCU_OPSI[x]_LBCLKO pin to the  
MCU_OSPI[x]_DQS pin (C to D) can be shortened to compensate.  
A
B
R1  
0 Ω*  
OSPI/QSPI/SPI  
Device Clock Input  
MCU_OSPI[x]_CLK  
C
R1  
0 Ω*  
MCU_OSPI[x]_LBCLKO  
D
OSPI Device DQS  
MCU_OSPI[x]_DQS  
E
F
MCU_OSPI[x]_D[y],  
MCU_OSPI[x]_CSn[z]  
OSPI/QSPI/SPI  
Device IO[y], CS#  
MCU_OSPI_Board_02  
* 0 Ωresistor (R1), located as close as possible to the MCU_OSPI[x]_CLK and MCU_OSPI[x]_LBCLKO pins, is a placeholder for fine  
tuning, if needed.  
图8-2. OSPI Interface High Level Schematic  
8.2.2.3 DQS (only available in Octal Flash devices)  
• The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device  
• The DQS pin of the flash devices must be connected to MCU_OSPI[x]_DQS signal  
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• The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B)  
should be approximately equal to the signal propagation delay from the MCU_OSPI[x]_DQS pin to the DQS  
output pin (C to D)  
• 50 ΩPCB routing is recommended along with series terminations, as shown in 图8-3  
• Propagation delays and matching:  
– A to B = C to D  
– Matching skew: < 60 ps  
A
B
R1  
0 Ω*  
OSPI/QSPI/SPI  
device clock input  
MCU_OSPI[x]_CLK  
C
D
OSPI device DQS  
MCU_OSPI[x]_DQS  
E
F
MCU_OSPI[x]_D[y],  
MCU_OSPI[x]_CSn[z]  
OSPI/QSPI/SPI  
device IOy, CS#  
J7ES_OSPI_Board_03  
* 0 Ωresistor (R1), located as close as possible to the MCU_OSPI[x]_CLK pin, is a placeholder for fine tuning, if needed.  
图8-3. OSPI Interface High Level Schematic  
8.2.3 USB VBUS Design Guidelines  
The USB 3.1 specification allows the VBUS voltage to be as high as 5.5 V for normal operation, and as high as  
20 V when the Power Delivery addendum is supported. Some automotive applications require a max voltage to  
be 30 V.  
The device requires the VBUS signal voltage be scaled down using an external resistor divider (as shown in the  
图 8-4), which limits the voltage applied to the actual device pin (USB0_VBUS). The tolerance of these external  
resistors should be equal to or less than 1%, and the leakage current of zener diode at 5 V should be less than  
100 nA.(1)  
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Device  
USBn_VBUS  
16.5 kΩ  
1%  
3.5 kΩ  
1%  
VBUS signal  
10 kΩ  
1%  
6.8V  
(BZX84C6V8 or equivalent)  
VSS  
VSS  
J7ES_USB_VBUS_01  
图8-4. USB VBUS Detect Voltage Divider / Clamp Circuit  
The USB0_VBUS pin can be considered to be fail-safe because the external circuit in 图 8-4 limits the input  
current to the actual device pin in a case where VBUS is applied while the device is powered off.  
8.2.4 System Power Supply Monitor Design Guidelines using VMON/POK  
The VMON1_ER_VSYS pin provides a way to monitor a system power supply. This system power supply is  
typically a single pre-regulated power source for the entire system. This supply is monitored by comparing the  
output of an external voltage divider circuit sourced by this supply with an internal voltage reference, with a  
power fail event being triggered when the voltage applied to VMON1_ER_VSYS drops below the internal  
reference voltage. The actual system power supply voltage trip point is determined by the system designer when  
selecting component values used to implement the external resistor voltage divider circuit. When designing the  
resistor divider circuit it is important to understand various factors which contribute to variability in the system  
power supply monitor trip point. The first thing to consider is the initial accuracy of the VMON1_ER_VSYS input  
threshold which has a nominal value of 0.45 V, with a variation of ±3%. Precision 1% resistors with similar  
thermal coefficient are recommended for implementing the resistor voltage divider. This minimizes variability  
contributed by resistor value tolerances. Input leakage current associated with VMON1_ER_VSYS must also be  
considered since any current flowing into the pin creates a loading error on the voltage divider output. The  
VMON1_ER_VSYS input leakage current may be in the range of 10 nA to 2.5 μA when applying 0.45 V.  
备注  
The resistor voltage divider shall be designed such that its output voltage never exceeds the  
maximum value defined in Recommended Operating Conditions during normal operating conditions.  
图8-5 presents an example, where the system power supply is nominally 5 V and the maximum trigger threshold  
is 5 V - 10%, or 4.5 V.  
For this example, it is important to understand which variables effect the maximum trigger threshold when  
selecting resistor values. It is obvious a device which has a VMON1_ER_VSYS input threshold of 0.45 V + 3%  
needs to be considered when trying to design a voltage divider that doesn’t trip until the system supply drops  
10%. The effect of resistor tolerance and input leakage also needs to be considered, but how these contributions  
effect the maximum trigger point may not be obvious. When selecting component values which produce a  
maximum trigger voltage, the system designer must consider a condition where the value of R1 is 1% low and  
the value of R2 is 1% high combined with a condition where input leakage current for the VMON1_ER_VSYS pin  
is 2.5 μA. When implementing a resistor divider where R1 = 4.81 KΩ and R2 = 40.2 KΩ, the result is a  
maximum trigger threshold of 4.523 V.  
Once component values have been selected to satisfy the maximum trigger voltage as described above, the  
system designer can determine the minimum trigger voltage by calculating the applied voltage that produces an  
output voltage of 0.45 V - 3% when the value of R1 is 1% high and the value of R2 is 1% low, and the input  
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leakage current is 10 nA, or zero. Using an input leakage of zero with the resistor values given above, the result  
is a minimum trigger threshold of 4.008 V.  
This example demonstrates a system power supply voltage trip point that ranges from 4.008 V to 4.523 V.  
Approximately 250 mV of this range is introduced by VMON1_ER_VSYS input threshold accuracy of ±3%,  
approximately 150 mV of this range is introduced by resistor tolerance of ±1%, and approximately 100 mV of this  
range is introduced by loading error when VMON1_ER_VSYS input leakage current is 2.5 μA.  
The resistor values selected in this example produces approximately 100 μA of bias current through the resistor  
divider when the system supply is 4.5 V. The 100 mV of loading error mentioned above could be reduced to  
about 10 mV by increasing the bias current through the resistor divider to approximately 1 mA. So resistor  
divider bias current vs loading error is something the system designer needs to consider when selecting  
component values.  
The system designer should also consider implementing a noise filter on the voltage divider output since  
VMON1_ER_VSYS has minimum hysteresis and a high-bandwidth response to transients. This could be done  
by installing a capacitor across R1 as shown in 图 8-5. However, the system designer must determine the  
response time of this filter based on system supply noise and expected response to transient events.  
图 8-5 presents an example, when the system power supply voltage is nominally 5 V and the desired trigger  
threshold is -10% or 4.5 V.  
Device  
VMON_VSYS  
R2  
VSYS  
40.2 kΩ 1%  
C1  
Value = Determined by system designer  
(System Power Supply)  
4.81 kΩ  
1%  
R1  
VSS  
SPRSP56_VMON_ER_MON_01  
图8-5. System Supply Monitor Voltage Divider Circuit  
The VMON2_IR_VCPU pin provides a way to monitor VDD_CPU power supply. Must be externally connected as  
close as possible to VDD_CPU pin on the board. SoCs that have a VMON6_IR_VEXT0P8 can optionally monitor  
other domains such as VDD_CORE or VDD_MCU. Similarly, those signals should be as close as possible to  
VDD_CORE or VDD_MCU pin on the board.  
The VMON3_IR_VEXT1P8 and VMON4_IR_VEXT1P8 pins provide a way to monitor an external 1.8-V power  
supply. The VMON5_IR_VEXT3P3 pin provides a way to monitor an external 3.3-V power supply. An internal  
resistor divider with software control is implemented inside the SoC. Software can program the internal resistor  
divider to create appropriate under voltage and over voltage interrupts. These pins should not be sourced from  
an external resistor divider. If the monitored voltage requires adjustment, be sure to buffer the divided voltage  
prior connecting to monitor pin.  
8.2.5 High Speed Differential Signal Routing Guidance  
The High Speed Interface Layout Guidelines provides guidance for successful routing of the high speed  
differential signals. This includes PCB stackup and materials guidance as well as routing skew, length and  
spacing limits. TI supports only designs that follow the board design guidelines contained in the application  
report.  
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8.2.6 Thermal Solution Guidance  
The Thermal Design Guide for DSP and ARM Application Processors provides guidance for successful  
implementation of a thermal solution for system designs containing this device. This document provides  
background information on common terms and methods related to thermal solutions. TI only supports designs  
that follow system design guidelines contained in the application report.  
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9 Device and Documentation Support  
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,  
generate code, and develop solutions are listed below.  
9.1 Device Nomenclature  
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all  
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix). Texas  
Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These  
prefixes represent evolutionary stages of product development from engineering prototypes (TMDX) through fully  
qualified production devices and tools (TMDS).  
Device development evolutionary flow:  
X
P
Experimental device that is not necessarily representative of the final device's electrical specifications and  
may not use production assembly flow.  
Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical  
specifications.  
null Production version of the silicon die that is fully qualified.  
Support tool development evolutionary flow:  
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.  
TMDS Fully-qualified development-support product.  
X and P devices and TMDX development-support tools are shipped against the following disclaimer:  
"Developmental product is intended for internal evaluation purposes."  
Production devices and TMDS development-support tools have been characterized fully, and the quality and  
reliability of the device have been demonstrated fully. TI's standard warranty applies.  
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production  
devices. Texas Instruments recommends that these devices not be used in any production system because their  
expected end-use failure rate still is undefined. Only qualified production devices are to be used.  
For orderable part numbers, see the Package Option Addendum of this document, the TI website (ti.com), or  
contact your TI sales representative.  
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9.1.1 Standard Package Symbolization  
备注  
Some devices may have a cosmetic circular marking visible on the top of the device package which  
results from the production test process. In addition, some devices may also show a color variation in  
the package substrate which results from the substrate manufacturer. These differences are cosmetic  
only with no reliability impact.  
xBBBBBBBBzYrPPPcQ1  
PIN ONE INDICATOR  
XXXXXXX  
G1  
ZZZ  
YYY  
O
J7ES_SPRSP35_PACK_01  
图9-1. Printed Device Reference  
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9.1.2 Device Naming Convention  
备注  
BLANK in the symbol or part number is collapsed so there are no gaps between characters.  
表9-1. Nomenclature Description  
FIELD  
PARAMETER  
FIELD  
DESCRIPTION  
VALUES  
DESCRIPTION  
MARKING ORDERABLE  
x
Device evolution stage(1)  
X
Prototype  
P
Preproduction (production test flow, no reliability data)  
Production  
BLANK  
BBBBBBB(2) Base production part  
number  
J721S2(2)  
Preproduction superset device  
See 节5, Device Comparison  
TDA4VE88  
TDA4AL88  
TDA4VL21  
z
Device Speed  
Device type  
T
See 表7-1, Speed Grade Maximum Frequency.  
N
H
OTHER  
Alternate speed grade  
Y
G
C
0
General purpose  
General purpose, R5F Lockstep capable  
High Security(3) capable  
5
High Security(3) capable, R5F Lockstep capable  
High Security Prime(3) capable, R5F Lockstep capable  
R
High Security(3) capable, R5F Lockstep capable,  
Customer Dev Keys. Only available on preproduction  
J721S2 devices.  
D
P
High Security Prime(3) capable, R5F Lockstep capable,  
Customer Dev Keys. Only available on preproduction  
J721S2 devices.  
r
PPP  
c
Device revision  
A or BLANK  
ALZ  
SR 1.0  
Package designator  
Carrier designator  
ALZ FCBGA-N770 (23 mm x 23 mm) Package  
N/A  
N/A  
BLANK  
Tray  
R
Tape and Reel  
Q1  
Automotive Designator  
Not automotive qualified.  
Supports TJ = –40°C to 105°C  
BLANK  
Q1  
Meets AEC-Q100 qualification requirements, with  
exceptions as specified in this data sheet.  
Supports TJ = –40°C to 125°C  
XXXXXXX  
YYY  
ZZZ  
Lot Trace Code  
Production Code  
Production Code  
Pin One  
As Marked  
As Marked  
As Marked  
As Marked  
As Marked  
N/A  
N/A  
N/A  
N/A  
N/A  
Lot Trace Code (LTC)  
Production Code, for TI use only  
Production Code, for TI use only  
Pin one designator  
O
G1  
ECAT  
ECAT—Green package designator  
(1) To designate the stages in the product development cycle, TI assigns prefixes to the part numbers. These prefixes represent  
evolutionary stages of product development from engineering prototypes through fully qualified production devices.  
Prototype devices are shipped against the following disclaimer:  
“This product is still in development and is intended for internal evaluation purposes.”  
Notwithstanding any provision to the contrary, TI makes no warranty expressed, implied, or statutory, including any implied warranty of  
merchantability of fitness for a specific purpose, of this device.  
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(2) J721S2 is the base part number for the preproduction superset device. Software should constrain the features used to match the  
intended production device.  
(3) For HS device support, TI recommends the 0, 5, or D device types. The R and P (HS “prime”) device types are not recommended  
for most applications, as they require extra steps in the manufacturing process and have a higher cost.  
9.2 Tools and Software  
The following products support development for TDA4VM platforms:  
Development Tools  
Code Composer Studio™ Integrated Development Environment Code Composer Studio (CCS) Integrated  
Development Environment (IDE) is a development environment that supports TI's Microcontroller and Embedded  
Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded  
applications. It includes an optimizing C/C++ compiler, source code editor, project build environment, debugger,  
profiler, and many other features. The intuitive IDE provides a single user interface taking you through each step  
of the application development flow. Familiar tools and interfaces allow users to get started faster than ever  
before. Code Composer Studio combines the advantages of the Eclipse software framework with advanced  
embedded debug capabilities from TI resulting in a compelling feature-rich development environment for  
embedded developers.  
SYSCONFIG Tool System Configuration Tool To help simplify configuration challenges and accelerate software  
development, TI created SysConfig, an intuitive and comprehensive collection of graphical utilities for configuring  
pins, peripherals, radios, subsystems, and other components. SysConfig helps you manage, expose, and  
resolve conflicts visually so that you have more time to create differentiated applications. The SysConfig tool is  
integrated in Code Composer Studio™ (CCS) IDE, as a standalone installer, or can be used via the dev.ti.com  
cloud tools portal.  
For a complete listing of development-support tools for the processor platform, visit the Texas Instruments  
website at ti.com. For information on pricing and availability, contact the nearest TI field sales office or authorized  
distributor.  
9.3 Documentation Support  
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on  
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For  
change details, review the revision history included in any revised document.  
The following documents describe the TDA4x devices.  
Technical Reference Manual  
TDA4AL, TDA4VL, TDA4VE Technical Reference Manual Details the integration, the environment, the  
functional description, and the programming models for each peripheral and subsystem in the TDA4VM family of  
devices.  
Errata  
J721S2, TDA4VE, TDA4AL, TDA4VL Processor Silicon Revision 1.0, Silicon Errata Describes the known  
exceptions to the functional specifications for the device.  
9.4 Trademarks  
eMMC™ is a trademark of MultiMediaCard Association.  
Jacinto™ and Code Composer Studio™ are trademarks of TI.  
TI E2E™ is a trademark of Texas Instruments.  
Arm® and Cortex® are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.  
PCI-Express® is a registered trademark of PCI-SIG.  
Secure Digital® is a registered trademark of SD Card Association.  
所有商标均为其各自所有者的财产。  
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9.5 支持资源  
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解  
答或提出自己的问题可获得所需的快速设计帮助。  
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅  
TI 的《使用条款》。  
9.6 静电放电警告  
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理  
和安装程序，可能会损坏集成电路。  
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参  
数更改都可能会导致器件与其发布的规格不相符。  
9.7 术语表  
TI 术语表  
本术语表列出并解释了术语、首字母缩略词和定义。  
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10 Mechanical, Packaging, and Orderable Information  
10.1 Packaging Information  
The following pages include mechanical, packaging, and orderable information. This information is the most  
current data available for the designated devices. This data is subject to change without notice and revision of  
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.  
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PACKAGE OPTION ADDENDUM  
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23-Jan-2023  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
-40 to 125  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
TDA4AL88TGAALZRQ1  
TDA4VE88TGAALZRQ1  
TDA4VL21HGAALZRQ1  
ACTIVE  
FCBGA  
FCBGA  
FCBGA  
ALZ  
770  
770  
770  
250  
RoHS & Green  
RoHS & Green  
RoHS & Green  
Call TI  
Level-3-260C-168 HR  
Level-3-260C-168 HR  
Level-3-260C-168 HR  
TDA4AL88  
TGAALZQ1  
206  
Samples  
Samples  
Samples  
ACTIVE  
ACTIVE  
ALZ  
ALZ  
250  
250  
Call TI  
Call TI  
-40 to 125  
TDA4VE88  
TGAALZQ1  
206  
-40 to 125  
TDA4VL21  
HGAALZQ1  
206  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
23-Jan-2023  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
8-Jul-2023  
TAPE AND REEL INFORMATION  
REEL DIMENSIONS  
TAPE DIMENSIONS  
K0  
P1  
W
B0  
Reel  
Diameter  
Cavity  
A0  
A0 Dimension designed to accommodate the component width  
B0 Dimension designed to accommodate the component length  
K0 Dimension designed to accommodate the component thickness  
Overall width of the carrier tape  
W
P1 Pitch between successive cavity centers  
Reel Width (W1)  
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE  
Sprocket Holes  
Q1 Q2  
Q3 Q4  
Q1 Q2  
Q3 Q4  
User Direction of Feed  
Pocket Quadrants  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TDA4AL88TGAALZRQ1 FCBGA  
TDA4VE88TGAALZRQ1 FCBGA  
TDA4VL21HGAALZRQ1 FCBGA  
ALZ  
ALZ  
ALZ  
770  
770  
770  
250  
250  
250  
330.0  
330.0  
330.0  
44.4  
44.4  
44.4  
23.4  
23.4  
23.4  
23.4  
23.4  
23.4  
4.25  
4.25  
4.25  
32.0  
32.0  
32.0  
44.0  
44.0  
44.0  
Q1  
Q1  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
8-Jul-2023  
TAPE AND REEL BOX DIMENSIONS  
Width (mm)  
H
W
L
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
TDA4AL88TGAALZRQ1  
TDA4VE88TGAALZRQ1  
TDA4VL21HGAALZRQ1  
FCBGA  
FCBGA  
FCBGA  
ALZ  
ALZ  
ALZ  
770  
770  
770  
250  
250  
250  
336.6  
336.6  
336.6  
336.6  
336.6  
336.6  
53.2  
53.2  
53.2  
Pack Materials-Page 2  
PACKAGE OUTLINE  
FCBGA - 2.57 mm max height  
BALL GRID ARRAY  
ALZ0770A  
23.1  
22.9  
A
B
BALL A1 CORNER  
PIN 1 ID  
(OPTIONAL)  
23.1  
22.9  
(
18.60)  
0.2 C  
(
18.60)  
22.60)  
(
(1.4)  
2.57  
2.37  
0.2 C  
C
SEATING PLANE  
(0.67)  
0.5  
0.15 C  
TYP  
0.3  
21.6 TYP  
SYMM  
0.8 TYP  
AH  
AG  
AF  
AE  
AD  
AC  
AB  
AA  
Y
W
V
U
SYMM  
T
21.6  
TYP  
R
P
N
M
L
K
J
0.55  
0.45  
770 X Ø  
H
G
F
E
D
C
B
A
0.25  
0.10  
C A B  
C
(0.7) TYP  
(0.7) TYP  
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28  
0.8 TYP  
4226636/A 03/2021  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
FCBGA - 2.57 mm max height  
BALL GRID ARRAY  
ALZ0770A  
770X (Ø 0.4)  
(0.8) TYP  
(0.8) TYP  
28  
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27  
1
2 3  
A
B
C
D
E
F
G
H
J
K
L
M
N
SYMM  
P
R
T
U
V
W
Y
AA  
AB  
AC  
AD  
AE  
AF  
AG  
AH  
SYMM  
LAND PATTERN EXAMPLE  
EXPOSED METAL SHOWN  
SCALE: 0.225X  
0.07 MAX  
0.07 MAX  
Ø 0.4  
(METAL)  
(Ø 0.4)  
SOLDER MASK  
OPENING  
EXPOSED METAL  
EXPOSED METAL  
SOLDER MASK  
OPENING  
METAL UNDER  
SOLDERMASK  
NON-SOLDER MASK  
DEFINED  
SOLDER MASK  
DEFINED  
(PREFERRED)  
SOLDER MASK DETAILS  
NOT TO SCALE  
4226636/A 03/2021  
NOTES: (continued)  
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature  
number SLUA271 (www.ti.com/lit/slua271)  
.
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown  
on this view. It is recommended that vias under paste be filled, plugged or tented.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
FCBGA - 2.57 mm max height  
BALL GRID ARRAY  
ALZ0770A  
770X (Ø 0.4)  
(0.8) TYP  
28  
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27  
1
2 3  
A
(0.8) TYP  
B
C
D
E
F
G
H
J
K
L
M
N
SYMM  
P
R
T
U
V
W
Y
AA  
AB  
AC  
AD  
AE  
AF  
AG  
AH  
SYMM  
SOLDER PASTE EXAMPLE  
BASED ON 0.15 mm THICK STENCIL  
SCALE: 0.225X  
4226636/A 03/2021  
NOTES: (continued)  
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
www.ti.com  
重要声明和免责声明  
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，  
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验  
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。  
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。  
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2023，德州仪器 (TI) 公司  

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