TDC1011 [TI]
TDC1011 Single Channel Ultrasonic Sensing Analog Front End (AFE) for Level Sensing,Concentration Sensing Applications;
| 型号： | TDC1011 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TDC1011 Single Channel Ultrasonic Sensing Analog Front End (AFE) for Level Sensing,Concentration Sensing Applications |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TDC1011
SNAS662 –JULY 2015
TDC1011 Single Channel Ultrasonic Sensing Analog Front End (AFE) for Level Sensing,
Concentration Sensing Applications
1 Features
3 Description
The TDC1011 is a fully integrated analog front-end
(AFE) for ultrasonic sensing measurements of liquid
level, fluid identification/concentration, and proximity/
distance applications common in automotive,
industrial, medical, and consumer markets. When
paired with an MSP430/C2000 MCU, power, wireless,
and source code, TI provides the complete ultrasonic
sensing solution.
1
•
•
•
Measurement Range: Up to 8 ms
Operating Current: 1.8 µA (2 SPS)
Transmitter Channel TX
–
–
Supports Single Transducer Applications
Programmable Excitation: 31.25 kHz to 4 MHz,
Up to 31 Pulses
•
Receiver Channel RX
TI's Ultrasonic AFE offers programmability and
flexibility to accommodate
–
–
–
STOP Cycle-to-Cycle Jitter: 50 psRMS
a
wide-range of
Low-Noise and Programmable Gain Amplifiers
applications and end equipment. The TDC1011 can
be configured for multiple transmit pulses and
frequencies, gain, and signal thresholds for use with
a wide-range of transducer frequencies (31.25kHz to
4MHz) and Q-factors. Similarly, the programmability
of the receive path allows ultrasonic waves to be
detected over a wider range of distances/tank sizes
and through various mediums.
Access to Signal Chain for External Filter
Design
–
–
Programmable Threshold Comparator for Echo
Qualification
Programmable Low Power Mode for Long TOF
Measurements
•
•
Temperature Measurement
Selecting different modes of operation, the TDC1011
can be optimized for low power consumption, making
it ideal for battery powered applications. The low
noise amplifiers and comparators provide extremely
low jitter, enabling picosecond resolution and
accuracy.
–
–
Interface to Two PT1000/500 RTDs
RTD-to-RTD Matching Accuracy 0.02°CRMS
Operating Temperature Range: -40°C to 125°C
2 Applications
Device Information(1)
•
Measurements Through Tanks of Varying
Materials:
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TDC1011
TSSOP (PW-28)
9.70 mm × 4.40 mm
–
–
Fluid Level
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Fluid Identification / Concentration
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TDC1011
SNAS662 –JULY 2015
www.ti.com
Table of Contents
8.3 Feature Description................................................. 12
8.4 Device Function Description ................................... 19
8.5 Programming .......................................................... 28
8.6 Register Maps......................................................... 30
Application and Implementation ........................ 36
9.1 Application Information............................................ 36
9.2 Typical Applications ................................................ 36
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 7
6.7 Switching Characteristics.......................................... 7
6.8 Typical Characteristics.............................................. 8
Parameter Measurement Information ................ 10
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
9
10 Power Supply Recommendations ..................... 41
11 Layout................................................................... 42
11.1 Layout Guidelines ................................................. 42
11.2 Layout Example .................................................... 42
12 Device and Documentation Support ................. 43
12.1 Device Support...................................................... 43
12.2 Community Resources.......................................... 43
12.3 Trademarks........................................................... 43
12.4 Electrostatic Discharge Caution............................ 43
12.5 Glossary................................................................ 43
7
8
13 Mechanical, Packaging, and Orderable
Information ........................................................... 43
4 Revision History
DATE
REVISION
NOTES
July 2015
*
Initial release.
2
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5 Pin Configuration and Functions
TSSOP
(PW) 28 Pin
Top View
NC
TX
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RX
VCOM
LNAOUT
PGAIN
PGAOUT
COMPIN
RTD1
NC
GND
CLKIN
VDD
VDD
VIO
3
4
5
6
7
SDO
SDI
8
RTD2
9
RREF
CSB
10
11
12
13
14
RES
SCLK
RESET
TRIGGER
EN
ERRB
START
STOP
Pin Functions
PIN
NAME
TYPE(1)
DESCRIPTION
NO.
1
NC
RX
No Connect (leave floating)
Receive input
2
I
P
O
I
VCOM
LNAOUT
PGAIN
PGAOUT
COMPIN
RTD1
3
Output common mode voltage bias
4
Low noise amplifier output (for ac decoupling capacitor)
Programmable gain amplifier input
Programmable gain amplifier output
Echo qualification and zero-crossing detector input
Resistance temperature detector channel 1
Resistance temperature detector channel 2
Reference resistor for temperature measurement
Reserved (connect to GND)
5
6
O
I
7
8
O
O
O
I
RTD2
9
RREF
RES
10
11
12
13
14
15
16
17
18
19
20
21
22
23, 24
ERRB
START
STOP
EN
O
O
O
I
Error flag (open drain)
Start pulse output
Stop pulse output
Enable (active high; when low the TDC1011 is in SLEEP mode)
Trigger input
TRIGGER
RESET
SCLK
CSB
I
I
Reset (active high)
I
Serial clock for the SPI interface
Chip select for the SPI interface (active low)
Serial data input for the SPI interface
Serial data output for the SPI interface
Positive I/O supply
I
SDI
I
SDO
O
P
P
VIO
VDD
Positive supply; all VDD supply pins must be connected to the supply. Place a 100-nF bypass capacitor
to ground in close proximity to the pin.
CLKIN
GND
NC
25
26
27
28
I
Clock input
G
Negative supply
No Connect (leave floating)
Transmit output
TX
O
(1) G = Ground, I = Input, O = Output, P = Power
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)
(1)(2)
MIN
–0.3
–0.3
–0.3
–0.3
MAX
6.0
UNIT
V
VDD
VIO
VI
Analog supply voltage, VDD pins
I/O supply voltage (VIO must always be lower than or equal to VDD supply)
Voltage on any analog input pin(3)
Voltage on any digital input pin(3)
6.0
V
VDD + 0.3
VIO + 0.3
5
V
VI
V
II
Input current at any pin
mA
°C
°C
TJ
Operating junction temperature
–40
–65
125
Tstg
Storage temperature range
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground, unless otherwise specified.
(3) When the input voltage at a pin exceeds the power supplies, the current at that pin must not exceed 5 mA and the voltage (VI) at that
pin must not exceed 6.0 V.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC A100-002(1)
All pins
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC
Q100-011
Corner pins (1, 14, 15
and 28)
±750
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
5.5
UNIT
V
VDD
VIO
VI
Analog supply voltage, VDD pins
2.7
1.8
Digital supply voltage, (VIO must always be lower than or equal to VDD supply)
Voltage on any analog input pin
VDD
VDD
VIO
V
GND
GND
0.06
–40
V
VI
Voltage on any digital input pin
V
ƒCLKIN
TJ
Operating frequency
16
MHz
°C
Operating junction temperature
125
6.4 Thermal Information(1)
TDC1011
TSSOP
THERMAL METRIC
UNIT
PW (28 PINS)
RθJA
Junction-to-ambient thermal resistance
83.5
29.9
40.8
2.4
RθJC(top) Junction-to-case (top) thermal resistance
RθJB
ψJT
Junction-to-board thermal resistance
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
ψJB
40.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These
specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life of
the product containing it. TA = 25°C, VDD = VIO = 3.7 V, VCOM = VCM = VDD / 2, CVCOM = 10 nF (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TRANSMITTER SIGNAL PATH (TX)
HIGH
LOW
VDD – 0.32
0.32
V
V
VOUT(TX)
Output voltage swing
ƒout = 1 MHz, RL = 75 Ω to VCM
ƒout = 1 MHz, RL = 75 Ω to VCM
IOUT(TX)
ƒOUT(TX)
Output drive current
Output TX frequency
22
mARMS
ƒCLKIN = 8 MHz, divide-by-2 (programmable;
4
MHz
see Transmitter Signal Path)
RECEIVER SIGNAL PATH (RX)
LNA capacitive feedback, GPGA = 6 dB, ƒIN = 1
MHz, VIN = 100 mVPP, CVCOM = 1 µF and
Figure 14
STOP cycle-to-cycle
jitter
ΔtSTOP
50
psRMS
LNA
Capacitive feedback, CIN = 300 pF, ƒIN = 1
MHz, RL = 100 kΩ to VCM, CVCOM = 1 µF
GLNA
LNA gain
20
2
dB
LNA input referred
noise density
Capacitive feedback, CIN = 300 pF, ƒ = 1 MHz,
VDD = 3.1 V, VIN = VCM, RL = ∞, CVCOM = 1 µF
enLNA
nV/√Hz
HIGH
LOW
HIGH
LOW
VCM + (VCM – 0.24) / (GLNA
VCM – (VCM – 0.24) / (GLNA
VDD – 0.24
)
V
V
V
V
Resistive feedback, RL = 1 kΩ to
VCM, CVCOM = 1 µF
VIN(LNA)
Input voltage range
Output voltage range
)
Resistive feedback, RL = 1 kΩ to
VCM, CVCOM = 1 µF
VOUT(LNA)
GND + 0.24
Resistive feedback, RL = 1 kΩ to VCM, 100mV
step, CVCOM = 1 µF
SRLNA
Slew rate(1)
9
5
V/μs
MHz
µV
Capacitive feedback, CIN = 300 pF, RL= 100 kΩ
to VCM, CVCOM = 1 µF
BWLNA
VOS(LNA)
–3-dB bandwidth
LNA input offset
voltage
Resistive mode, VIN = VCM, RL = ∞
±320
VCOM
VCOM
VCOM output voltage
VCOM output error
VCM
V
CVCOM = 1 µF
0.5%
PGA
HIGH
LOW
VCM + (VCM – 0.06) / (GPGA
)
V
RL = 100 kΩ to VCM, CL = 10 pF
to GND
VIN(PGA)
PGA input range
VCM – (VCM – 0.06) / (GPGA
)
V
GPGAMIN
GPGAMAX
ΔGPGA
PGA min gain
0
21
3
dB
dB
dB
PGA max gain
PGA gain step size
PGA gain error
DC, RL = ∞, CL = 10 pF
GE(PGA)
DC, GPGA = 0 dB, RL = ∞, CL = 10 pF
DC, GPGA = 0 dB, RL = ∞, CL = 10 pF
5%
PGA gain temperature
coefficient
TCGPGA
enPGA
170
3.1
ppm/°C
PGA input referred
noise density
GPGA = 21 dB, ƒ = 1 MHz, VDD = 3.1V, VIN =
VCM, RL = ∞, CVCOM = 1 µF
nV/√Hz
HIGH
LOW
VDD – 0.06
60
V
RL = 100 kΩ to VCM, CL = 10 pF
to GND
VOUT(PGA)
Output range
mV
GPGA = 21 dB, RL = 100 kΩ to VCM, CL = 10
pF, CVCOM = 1 µF
BWPGA
SRPGA
–3-db bandwidth
Slew rate(1)
5
MHz
V/µs
GPGA = 21 dB, RL = 100 kΩ to VCM, CL = 10
pF, CVCOM = 1 µF
12.5
(1) The slew rate is measured from 10% to 90% and is represented by the average of the rising and falling slew rates.
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Electrical Characteristics (continued)
The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These
specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life of
the product containing it. TA = 25°C, VDD = VIO = 3.7 V, VCOM = VCM = VDD / 2, CVCOM = 10 nF (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ZERO CROSS COMPARATOR
VOS(COMP)
Input offset voltage(2)
Referred to VCOM
±115
5
µV
nV/√Hz
mV
Zero crossing
enCOMP
comparator input
1 MHz
referred noise(2)
(2)
HYSTCOMP
Hysteresis
Referred to VCOM
-10
THRESHOLD DETECTOR
ECHO_QUAL_THLD = 0h, VCOM referred
ECHO_QUAL_THLD = 7h, VCOM referred
–35
mV
V
VTHDET
Threshold level
–1.5
TEMPERATURE SENSOR INTERFACE(3)
RREF = 1 kΩ, PT1000 range: –40 to 125°C(4)
RREF = 1 kΩ, PT1000 range: –15°C to 85°C(4)
RREF = 1 kΩ, RRTD1 = RRTD2 = 1.1 kΩ
1
0.5
°C
°C
Temperature
TERROR
measurement accuracy
Relative accuracy
0.02
5.8
°CRMS
m°C/°C
TGE
Gain error
POWER SUPPLY
Sleep (EN = CLKIN = TRIGGER = low)
0.61
2.8
µA
Continuous receive mode, LNA and PGA
bypassed
3
mA
IDD
VDD supply current
Continuous receive mode, LNA and PGA active
Temp. measurement only (PT1000 mode)(5)
Temp. measurement (PT500 mode)(6)
6.2
370
500
7.5
400
540
mA
µA
µA
VIO supply sleep
current(2)
IIO
Sleep (EN = CLKIN = TRIGGER = low)
2
nA
DIGITAL INPUT/OUTPUT CHARACTERISTICS
Input logic low
threshold
VIL
0.2 × VIO
V
V
Input logic high
threshold
VIH
0.8 × VIO
SDO pin, 100-μA current
0.2
0.4
0.5
0.6
0.2
0.4
V
V
V
V
V
V
V
V
V
V
V
SDO pin, 1.85-mA current
START and STOP pins, 100-μA current
START and STOP pins, 1.85-mA current
ERRB pin, 100-μA current
Output logic low
threshold
VOL
ERRB pin, 1.85-mA current
SDO pin, 100-μA current
VIO – 0.2
VIO – 0.6
VIO – 0.5
VIO – 0.6
VIO – 0.2
SDO pin, 1.85-mA current
Output logic high
threshold
VOH
START and STOP pins, 100-μA current
START and STOP pins, 1.85-mA current
ERRB pin, 0-µA current
Maximum output
current for SDO,
START and STOP
IOMAX
1.85
mA
(2) Specified by design.
(3) With ideal external components. For more detail see Temp Sensor Measurement section.
(4) PT1000 RTD approximate resistance: 800 Ω ≡ –52°C, 931 Ω ≡ –18°C, 1.10 kΩ ≡ 26°C, 1.33 kΩ ≡ 86°C and 1.48 kΩ ≡ 125°C.
(5) Specified currents include 120μA which flows through the RTD sensor in PT1000 mode (TEMP_RTD_SEL = 0).
(6) Specified currents include 240μA which flows through the RTD sensor in PT500 mode (TEMP_RTD_SEL = 1).
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6.6 Timing Requirements
TA = 25°C, VDD = VIO = 3.7 V and ƒSCLK = 1 MHz (unless otherwise noted).
MIN
NOM
MAX
26
UNIT
MHz
ns
ƒSCLK
t1
Serial clock frequency
High period, SCLK
16
16
10
12
12
16
10
17
10
t2
Low period, SCLK
ns
t3
Set-up time, nCS to SCLK
Set-up time, SDI to SCLK
Hold time, SCLK to SDI
ns
t4
ns
t5
ns
t6
SCLK transition to SDO valid time
Hold time, SCLK transition to nCS rising edge
nCS inactive
ns
t7
ns
t8
ns
t9
Hold time, SCLK transition to nCS falling edge
Signal rise and fall times(1)
ns
tr / tf
1.8
ns
(1) The slew rate is measured from 10% to 90% and is represented by the average of the rising and falling slew rates.
SCLK
t
t
t
7
t
9
1
2
t
3
CSB
t
8
t
t
5
4
D0
D15
D14
t
6
90%
90%
Prior D15
Prior D1
Prior D0
10%
10%
t
r
t
f
Figure 1. SPI Timing Diagram
6.7 Switching Characteristics
TA = 25°C, VDD = VIO = 3.7 V, ƒCLKIN = 8 MHz.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
START, STOP, ENABLE, RESET, CLOCKIN, TRIGGER, ERR
TX_FREQ_DIV = 2h, NUM_TX = 1
1
2
3
μs
μs
μs
PWSTART Pulse width for START signal TX_FREQ_DIV = 2h, NUM_TX = 2
TX_FREQ_DIV = 2h, NUM_TX ≥ 3
tr / tf
START
Rise/fall time for START
signal
20% to 80%, 20-pF load
0.25
0.25
16
ns
ns
tr / tf STOP Rise/fall time for STOP signal 20% to 80%, 20-pF load
Maximum CLKIN input
frequency
ƒCLKIN
MHz
ns
tr / tf CLKIN CLKIN input rise/fall time(1)
20% to 80%
20% to 80%
10
TRIGGER input rise/fall
tr / tf TRIG
time(1)
10
ns
tEN_TRIG
Enable to trigger wait time(1)
50
ns
TX_FREQ_DIV = 2h (see TX/RX Measurement
Sequencing and Timing)
tRES_TRIG Reset to trigger wait time(1)
3.05
μs
(1) Specified by design.
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6.8 Typical Characteristics
At TA = 25°C, unless otherwise noted.
500
400
300
200
100
0
500
400
300
200
100
0
±100
±100
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
C001
C002
VDD = VIO = 3.7V
Capacitive
Feedback Mode
RL = 1kΩ
VDD = VIO = 3.7V
Gain of 21dB
RL = 1kΩ
Figure 2. LNA ZOUT vs Frequency
Figure 3. PGA ZOUT vs Frequency
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
0
0
5k
50k
Frequency (Hz)
500k
2M
5k
50k
Frequency (Hz)
500k
2M
C013
C014
VDD = VIO = 3.1V
Capacitive
RL = ∞
VDD = VIO = 3.7V
Gain of 21dB
RL = ∞
Feedback Mode
Figure 4. LNA Input-referred Noise vs Frequency
Figure 5. PGA Input-referred Noise vs Frequency
Time (1ꢀs/DIV)
Time (1ꢀs/DIV)
C005
C006
VDD = VIO = 3.7V
VIN = 100mV
Resistive Feedback
Mode
RL = 1kΩ
VDD = VIO = 3.7V
VIN = 100mV
Gain of 21dB
RL = 100kΩ
fIN = 100kHz
fIN = 100kHz
Figure 6. LNA Response
Figure 7. PGA Response
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Typical Characteristics (continued)
At TA = 25°C, unless otherwise noted.
30
30
20
20
10
10
0
0
±10
±20
±30
±10
±20
±30
10k
100k
1M
10M
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
C007
C008
VDD = VIO = 3.7V
CIN = 300 pF
Capacitive
Feedback Mode
RL = 100kΩ
VDD = VIO = 3.7V
Gain of 21dB
RL = 100kΩ
Figure 8. LNA Gain vs Frequency
Figure 9. PGA Gain vs Frequency
20
18
16
14
12
10
8
20
18
16
14
12
10
8
6
6
4
4
2
2
0
0
Time (ps)
Time (ps)
C009
C010
VDD = VIO = 5V
VIN = 100mV
LNA Capacitive
Feedback Mode
PGA Gain of 6dB
fIN = 1MHz
VDD = VIO = 3.7V
VIN = 100mV
TA = 25C°
LNA Capacitive
Feedback Mode
PGA Gain of 6dB
fIN = 1MHz
(See Figure 14)
Count >= 10000
(See Figure 14)
Count >= 10000
Figure 10. RX Jitter Histogram
Figure 11. RX Jitter Histogram
20
18
16
14
12
10
8
20
18
16
14
12
10
8
6
6
4
4
2
2
0
0
Time (ps)
Time (ps)
C011
C012
VDD = VIO = 3.7V
VIN = 100mV
TA = -40C°
LNA Capacitive
Feedback Mode
PGA Gain of 6dB
fIN = 1MHz
VDD = VIO = 3.7V
VIN = 100mV
TA = 125C°
LNA Capacitive
Feedback Mode
PGA Gain of 6dB
fIN = 1MHz
(See Figure 14)
Count >= 10000
(See Figure 14)
Count >= 10000
Figure 12. RX Jitter Histrogam
Figure 13. RX Jitter Histogram
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7 Parameter Measurement Information
CIN = 300 pF
INPUT
LNAIN
PGAIN
CF1 = 1 nF
LNAOUT
RF1 = 1 N
CF2 = 51 pF
PGAOUT
COMPIN
CF3 = 51 pF
RF2 = 5.1 Nꢀ
GND
VCOM
Figure 14. External Circuits for Jitter Measurement
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8 Detailed Description
8.1 Overview
The main functional blocks of TDC1011 are the Transmit (TX) and the Receive (RX) Channels. The transmitter
supports flexible settings for driving various ultrasonic transducers, and the receiver provides configurable blocks
with a wide range of settings for signal conditioning in various applications. The receive signal chain consists of
an LNA (Low Noise Amplifier), a PGA (Programmable Gain Amplifier), and two auto-zeroed comparators for
echo qualification and STOP pulse generation.
A measurement cycle is initiated with a trigger signal on the TRIGGER pin of the device. After a trigger signal is
asserted, an output pulse is generated on the START pin. This signal is used as the time reference to begin a
TOF measurement. The transmitter generates programmable TX pulses, synchronous to the rising edge of the
START pulse, to drive an ultrasonic transducer and generate an ultrasonic wave that is shot through an acoustic
medium. The receiver detects the ultrasound wave that traveled through the medium and generates STOP
signals. Whether the ultrasound wave is received directly or from a reflection will depend on the system
configuration. The STOP signals are used by an external Time-to-Digital Converter (TDC), which functions as a
very accurate stopwatch. The system must include a TDC to measure the TOF based on the interval between
the START and STOP pulses. In some applications with medium-range accuracy requirements (ns range), a
microcontroller can be used to measure the TOF duration. In applications with high-range accuracy requirements
(ps range), TI recommends using the TDC7200 time-to-digital converter to measure the TOF duration.
In each application, the TDC1011 has to be configured by a serial interface (SPI) for the various application-
specific parameters that are explained in the following sections.
8.2 Functional Block Diagram
TX
Serial
Interface
Clock
Divider
Tx
SM Control
Unit
Generator
START
STOP
enable
Event
Manager
DAC
±
LNA
+
PGA
RX
Threshold Detect
+
VCOM
±
20 dB
0 to 21 dB
VCOM
Analog Bias Temp. Sense
TDC1011
Zero-Cross Detect
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8.3 Feature Description
8.3.1 Transmitter Signal Path
The Transmitter (TX) path consists of a Clock Divider block and a TX Generator block. The clock divider allows
the TDC1011 to divide the clock source that is connected to the CLKIN pin down to the resonant frequency (ƒR)
of the transducer used. The clock divider allows division factors in powers of 2. The division factor of the clock
divider can be programmed with the TX_FREQ_DIV field in the CONFIG_0 register.
The TX Generator block can drive a transducer with a programmable number of TX pulses. The frequency of
these pulses is defined as ƒCLKIN/(2TX_FREQ_DIV+1), and should match the ƒR of the transducer. The number of
pulses is configured by programming the NUM_TX field in the CONFIG_0 register.
For example, for ƒCLKIN = 8 MHz and TX_FREQ_DIV = 2h (divide by 8), the divided clock frequency is 1 MHz.
In addition to the programmable number of pulses, the TX Generator also provides options to introduce a 180⁰
pulse shift at pulse position n or damping the last TX pulse. In some situations, damping can reduce the ringing
of the transducer for very short TOF measurements. These features are further described in the TRANSMIT
Operation section of the datasheet.
8.3.2 Receiver Signal Path
The RX signal path consists of an LNA, PGA, and a pair of comparators. The LNA and PGA provide the required
amplification of the receive signal. The amplified receive signal is fed into a set of comparators which generate
pulses on the STOP pin based on the programmed threshold levels. The block diagram for the receiver path can
be seen in Figure 15.
If the 20-dB to 41-dB of gain provided by the TDC1011 is insufficient, additional gain can be added prior to the
COMPIN pin. Likewise, with a strong received signal, if the gain from the LNA or PGA is not needed, they can be
bypassed and the transducer signal can be directly connected to the COMPIN pin.
A band-pass filter centered on the transducer’s response can be used between each stage of the receiver path
to reduce the noise; note that the inputs of the LNA, PGA, and comparators should be biased to the VCOM pin’s
potential. The comparators connected to the COMPIN pin are used for echo qualification and generation of
STOP pulses that correspond to the zero-crossings of the echo signal. The STOP pulses are used with a START
pulse to calculate the TOF of the echo in the medium.
enable
Event
Manager
DAC
±
LNA
+
PGA
STOP
Threshold Detect
+
VCOM
±
20dB
0 to 21 dB
VCOM
Analog Bias Temp. Sense
TDC1011
Zero-Cross Detect
Figure 15. TDC1011 Receiver Path
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Feature Description (continued)
8.3.3 Low Noise Amplifier (LNA)
The LNA in the TDC1011’s front-end limits the input-referred noise and ensures timing accuracy for the
generated STOP pulses. The LNA is an inverting amplifier designed for a closed-loop gain of 20 dB with the aid
of an external input capacitor or resistor, and it can be programmed for two feedback configurations. The band-
pass configuration, referred to as capacitive feedback mode, must be combined with an input capacitor. The low-
pass configuration, referred to as resistive feedback mode, must be combined with an input resistor. The
recommended values for the input components are 300 pF and 900 Ω respectively.
The LNA can be configured in capacitive feedback mode for transducers with resonant frequencies in the order
of a couple of MHz. This is done by clearing the LNA_FB bit in the TOF_1 register to 0. As shown in Figure 16,
the external capacitor, CIN, should be placed between the transducer and the input pin. This provides an in-band
gain of CIN/CF, where CF is the on-chip 30-pF feedback capacitor. Provided that CIN = 300 pF, the in-band gain of
the LNA circuit is:
CIN
300 pF
30 pF
Gaininꢀband
10
CF
(1)
CF
RF
30 pF
9 N
CIN
300 pF
RX
±
LNA
LNAOUT
+
VCOM
Figure 16. LNA Capacitive Feedback Configuration
The capacitive feedback configuration of the LNA has a band-pass frequency response. The high-pass corner
frequency is set by the internal feedback components RF (9 kΩ) and CF (30 pF), and is approximately 590 kHz.
The in-band gain is set by the capacitor ratio and the LNA’s 50-MHz gain-bandwidth product sets the low-pass
corner of the frequency response. For example, an in-band gain of 10 results in a bandpass response between
590 kHz and 5 MHz.
The LNA can be configured in resistive feedback mode for transducers with resonant frequencies in the order of
a couple of hundreds of kHz. This is done by setting the LNA_FB bit in the TOF_1 register to 1. In this
configuration, the internal feedback capacitor CF is disconnected (see Figure 17), and the DC gain of the LNA
circuit is determined by the ratio between the internal feedback resistor RF (9 kΩ) and an external resistor RIN.
For RIN = 900 Ω, the gain of the circuit is 10.
9 Nꢀ
RF
RIN
Transducer
RX
900 ꢀ
±
LNAOUT
LNA
+
VCOM
Figure 17. LNA Resistive Feedback Configuration
The LNA can be bypassed and disabled by writing a 1 to the LNA_CTRL bit in the TOF_1 register.
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Feature Description (continued)
8.3.4 Programmable Gain Amplifier (PGA)
The PGA, shown in Figure 18, is an inverting amplifier with an input resistance of RIN = 500 Ω and a
programmable feedback resistor RFB that can be programmed to set a 0-dB to 21-dB gain in 3-dB steps. This
can be done by programming the PGA_GAIN field in the TOF_1 register. The bandwidth of the PGA is scaled
based on its programmed gain. The typical bandwidth of the PGA with a 100-kΩ load to VCM and a 10-pF
capacitor to ground are listed in Table 1.
Table 1. Typical PGA Bandwidth
PGA_GAIN (Hex)
Gain (dB)
Bandwidth (MHz)
0h
1h
2h
3h
4h
5h
6h
7h
0
3
19.0
16.8
14.4
12.3
10.0
8.2
6
9
12
15
18
21
6.6
5.0
The PGA can be bypassed and disabled by writing a 1 to the PGA_CTRL bit in the TOF_1 register. The output of
the PGA should not be loaded directly with capacitances greater than 10 pF.
RFB
RIN
500 :
PGA_IN
PGA_OUT
PGA
VCOM
Figure 18. TDC1011 Programmable Gain Amplifier
8.3.5 Receiver Filters
It is recommended to place two filters in the RX path to minimize the receive path noise and obtain maximum
timing accuracy. As shown in Figure 19, one filter is placed between the LNAOUT and the PGAIN pins, and
another filter is placed between the PGAOUT and the COMPIN pins.
With an in-band gain of 10, the LNA has a bandwidth of 5 MHz. For most applications, a low-pass filter between
the LNAOUT and PGAIN pins is sufficient.
As shown in Figure 19, the second filter stage can use a cascade of a low-pass filter (RF1 and CF3) followed by a
high-pass filter (CF2 and RF2) referenced to VCOM. Design of the filter is straightforward. The RF1 and CF2 can be
chosen first. A reasonable set of values for RF1 and CF2 could be: RF1 = 1 kΩ ± 10% and CF2 = 50pF ± 10%.
Given the center frequency of interest to be ƒC and the filter bandwidth to be ƒB, the value of CF3 can be
calculated as:
1
CF3
2SRF1
fC ꢂ fB
(2)
RF2 and CF2 determine the high-pass corner of the filter. RF2 should be referenced to VCOM to maintain the DC
bias level at the comparator input during the echo receive time. For values of RF2 larger than RF1, there will be
limited loading effect from the high-pass filter to the low-pass filter resulting in more accurate corner frequencies.
The chosen values shown in the figure below result in a high-pass corner frequency of about 600 kHz and a low-
pass corner frequency of about 3 MHz.
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More complex filters can be used; external gain is acceptable if the signal amplitude is too low. If the pass-band
of the filter is wider than an octave, it is recommended to use a filter design which has linear group delay.
RF1 = 1 Nꢀ
CF2 = 50 pF
CF1 = 1 nF
LNAOUT
PGAIN
PGAOUT
COMPIN
CF3 = 53 pF
RF2 = 5 Nꢀ
GND
VCOM
Figure 19. Filter for a 1-MHz Operation
8.3.6 Comparators for STOP Pulse Generation
The STOP pulse generation block of the TDC1011 contains two auto-zeroed comparators (a zero-cross detect
and a threshold-detect comparator), a threshold setting DAC, and an event manager.
Comparator auto-zero periods occur at the beginning of every TOF receive cycle. During these periods, the
comparator’s input offset is stored in an internal 2.5-pF capacitor, and it is subtracted from the input signal during
the echo processing phase. The duration of auto-zero period is configured with the AUTOZERO_PERIOD field
located in the CLOCK_RATE register.
Zero Cross Detect
VCOM
±
COMPIN
+
STOP
Threshold
Detect
Event Manager
ECHO_QUAL_THLD
±
+
DAC
VTHLD
±
+
RECEIVE_MODE
NUM_RX
Figure 20. STOP Pulse Generation Circuit
8.3.6.1 Threshold Detector and DAC
The threshold detect comparator in Figure 20 compares the echo amplitude with a programmable threshold level
(VTHLD) controlled by a DAC. The DAC voltage is set by the ECHO_QUAL_THLD field in register CONFIG_3 and
provides 8 programmable threshold levels, VTHLD. The typical levels are summarized in Table 2:
Table 2. Echo Qualification Threshold Levels
ECHO_QUAL_THLD
Typical VTHLD (mV)
0h
1h
2h
3h
4h
5h
6h
7h
–35
–50
–75
–125
–220
–410
–775
–1500
8.3.6.2 Zero-cross Detect Comparator
The zero-cross detect comparator compares the amplified echo signal at COMPIN with its reference voltage,
which is VCOM. As shown in Figure 21, the comparator produces a low-to-high transition when the amplitude of
the echo signal rises above VCOM. The comparator produces a high-to-low transition when the echo amplitude
falls below VCOM – VHYST. The built-in negative-sided hysteresis of 10 mV in reference to VCOM ensures accurate
zero-cross time instances associated with the rising edges of the echo signal and immunity of the comparator
output to noise.
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Signal into
COMPIN
VCOM
VHYST = 10 mV
Zero Cross
Detect Output
Figure 21. Zero-Cross Detector Output Signal
The output of the zero-cross detect comparator is passed to the event manager, where depending on the
decision of the threshold-detect comparator.
8.3.6.3 Event Manager
The event manager is a digital state machine in the STOP pulse generation circuit of the TDC1011. The event
manager controls the maximum number of STOP pulses to generate on the STOP pin and the receive mode for
the STOP pulse generation. The number of STOP pulses is configured in the NUM_RX field in the CONFIG_1
register. The receive mode is selected in the RECEIVE_MODE bit of the CONFIG_4 register. See sections
Single Echo Receive Mode and Multiple Echo Receive Mode for details about the receiver modes of the
TDC1011.
An example for NUM_RX = 2h and RECEIVE_MODE = 0 is shown in Figure 22. When the echo signal amplitude
exceeds values smaller than VTHLD, the threshold detect comparator indicates to the event manager to qualify the
next zero-cross event as valid. When the qualified zero-cross is detected by the zero-cross detect comparator,
the event manager passes the pulse to the STOP pin until the number of receive events programmed in
NUM_RX is reached.
STOP
COMPIN
VCOM
VTHLD
GND
Passes VTHLD
Passes VTHLD
Qualified for
zero-cross
Qualified for
zero-cross
Figure 22. Signal Qualification, Zero-cross Detection and STOP Pulse Generation
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8.3.7 Common-mode Buffer (VCOM)
The output of the internal common-mode buffer is present at the VCOM pin. This pin should be bypassed to
ground with a low-leakage 10-nF capacitor and it should not be loaded with more than 20 µA. The common-
mode buffer can be disabled with the VCOM_SEL bit in the CONFIG_2 register. If disabled, an external
reference voltage must be applied to the VCOM pin.
During a time-of-flight measurement, the common-mode reference will take approximately 16 µs to settle if
starting from zero initial conditions. Using a larger capacitor will increase the settling time of the internal common-
mode reference. The implications of a larger VCOM capacitor are further explored in the Common-mode
Reference Settling Time section.
8.3.8 Temperature Sensor
MEAS_MODE
TDC1011
tof_start
MUX
START
MEAS_MODE
tof_stop
MUX
STOP
Temp
Sensor
RTD1
RTD1
(external)
RTD2
RTD2
(external)
Figure 23. Temperature Sensor Measurement
Accurate measurements of level, and concentration may require compensation for the temperature dependency
of the speed of sound in the medium. The TDC1011 provides two temperature sensor connections, allowing to
measure up to two locations with RTDs, as shown in Figure 23.
The temperature sensor block supports PT1000 or PT500 sensors. The type of RTD used must be selected in
the TEMP_RTD_SEL bit of the CONFIG_3 register. The system requires a temperature-stable external reference
resistor (RREF). If the RTD type is PT500, then RREF should be 500 Ω. If the RTD type is PT1000, then RREF
should be 1 kΩ. The reference resistor needs to have either a low temperature coefficient or be calibrated for
temperature shift.
The logic timing in a temperature measurement is controlled by the TEMP_CLK_DIV bit in the CONFIG_3
register. As shown in Figure 24, the external clock can be divided by 8 or by the value resulting from the
TX_FREQ_DIV field configuration in the CONFIG_0 register. It is recommended to operate the temperature
measurement block at frequencies of 1 MHz or less.
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0x03[4] ± TEMP_CLK_DIV
y 8
0
¦
TEMP
1
CLKIN
¦
TTEMP =
CLKIN
¦
TEMP
1
y 2TX_FREQ_DIV+1
0x00[7:5] ± TX_FREQ_DIV
Figure 24. Timing Source for the Temperature Measurement
See the TDC1011 Temperature Sensing Interface application note listed in the Temperature Measurement with
Multiple RTDs section for details about artifacts in the temperature measurement and how to manage them.
8.3.8.1 Temperature Measurement with Multiple RTDs
The temperature measurement mode is selected by setting the MEAS_MODE bit in the CONFIG_2 register to 1.
A temperature measurement is started by sending a trigger pulse. After the temperature measurement is
complete, the TDC1011 returns to SLEEP mode. To return to TOF measurement mode, reset the MEAS_MODE
bit to 0.
The temperature sensor measurement can be performed without the need of an external ADC. The temperature
sensor block operates by converting the resistance of a reference, RREF, and up to two RTDs into a series of
START and STOP pulses. The interval between the pulses is proportional to the measured resistance, and
therefore, the temperature. As shown in Figure 25, the TDC1011 performs three measurements per trigger event
and generates the corresponding pulses on the START and STOP pins.
Reference
RTD1
RTD2
TRIGGER
START
td1
td2
tREF
tRTD1
tRTD2
STOP
Figure 25. Temperature Measurement Output Timing
The resistance of RTD1 and RTD2 can be calculated from the time intervals in Figure 25 as follows:
tREF
RRTDx RREF
u
tRTDx
(3)
With a 1-kΩ reference resistor, the tREF interval is approximately 200 μs. The following intervals, tRTD1 and tRTD2
,
will depend on the resistance of the RTDs. The time delay between measurements, td1 and td2, can be
approximated as follows:
td1 = (51 × TTEMP) + ( tRTD1 × 0.55 )
td2 = (51 × TTEMP) + ( tRTD2 × 0.55 )
(4)
(5)
For example, two PT1000 sensors at 0°C will have an approximate resistance of 1 kΩ; the same as the
reference resistor in this example. Given an external 8-MHz clock and the default temperature clock divide-by-8
from the TEMP_CLK_DIV bit, the overall measurement time between the START pulse and the last STOP pulse
is approximately 922 µs.
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8.3.8.2 Temperature Measurement with a Single RTD
The temperature sensing block can be configured to measure a single RTD by setting the TEMP_MODE bit in
register CONFIG_3 to 1. When the temperature measurement runs in PT1000 mode (TEMP_RTD_SEL = 0), the
first interval corresponds to RREF, the second interval is a redundant measurement on RREF and should be
neglected, and the third interval corresponds to RTD1. This operation is represented in Figure 26.
Reference
Discard
RTD1
TRIGGER
START
td1
td2
tREF
½ tREF
tRTD1
STOP
Figure 26. Temperature Measurement with a Single PT1000
The resistance of RTD1 can be calculated using Equation 3. The time delay between measurements can be
approximated using Equation 4 and Equation 5, with the exception that in this case, td1 is a function of ½ tREF and
td2 is a function of tRTD1
.
If the temperature measurement runs in PT500 mode (TEMP_RTD_SEL = 1), the first interval is a redundant
measurement on RREF and should be neglected, the second interval corresponds to RREF, and the third interval
corresponds to RTD1. This operation is represented in Figure 27.
Discard
Reference
RTD1
TRIGGER
START
td1
td2
2 u tREF
tREF
tRTD1
STOP
Figure 27. Temperature Measurement with a Single PT500
The resistance of RTD1 can be calculated using Equation 3. The time delay between measurements can be
approximated using Equation 4 and Equation 5, with the exception that in this case, td1 is a function of tREF and
td2 is a function of tRTD1
.
8.4 Device Function Description
8.4.1 Time-of-Flight Measurement Mode
The TOF measurement mode is selected by setting the MEAS_MODE bit in the CONFIG_2 register to 0.
8.4.1.1 Liquid Level or Fluid Identification
The TDC1011 performs a single TOF measurement after receiving a trigger signal and returns to the SLEEP
mode when the measurement is complete.
8.4.2 State Machine
A state machine in the TDC1011 manages the operation of the various measurement modes (see Figure 28). At
power-on, the state machine is reset and most blocks are disabled. After the power-on sequence is complete, the
device goes into SLEEP mode if the EN pin is low or into READY mode if the EN pin is high. In the SLEEP or
READY state, the TDC1011 is able to receive SPI commands to set registers and configure the device for a
measurement mode.
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Device Function Description (continued)
NOTE
Although the SPI block is always active, it is not recommended to perform configuration
changes while the device is active. Configuration changes should be performed while the
device is in the SLEEP state or in the READY state.
If the EN pin is high and a trigger signal is received, the state machine will begin the execution of the configured
measurement. The state machine will return to the SLEEP state after the measurement is completed.
The device can be forced to exit a measurement by applying a logic high on the RESET pin high or a logic low
on the EN pin.
SW Reset
EN = Low
HW Reset
Timeout = 1
SLEEP state
EN = High
ERROR_FLAGS register (0x07):
xꢀ Writing 1 to bit [1] of the ERROR_FLAGS
register cancels any active measurement
and returns to sleep mode or ready mode
and sets Count to 0 and CH-flag to FALSE.
tNot
Ready
Trigger
pulse?
Yes
TX Burst
Output START
Pulse
RX Active
Output
STOP pulses
Mode?
Figure 28. Simplified TDC1011 State Machine Diagram
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Device Function Description (continued)
8.4.3 TRANSMIT Operation
8.4.3.1 Transmission Pulse Count
The number of TX pulses generated by the TDC1011 to drive an ultrasonic transducer is programmable using
the NUM_TX field located in the CONFIG_0 register.
8.4.3.2 TX 180° Pulse Shift
As shown in Figure 29, the transmitter block can add a 180° shift at a position in the TX signal. The position of
the pulse shift is set by the TX_PH_SHIFT_POS field in the CONFIG_4 register and allows generating a specific
signal pattern.
Generation of 180° burst
for Tx Signature
Figure 29. Transmitter Pulse Signature, 180° Burst
As shown in Figure 30, enabling the TX 180° pulse shift has the effect of decreasing the number of transmitted
pulses by 1.
Normal Operation:
NUM_TX = 0x07
TX_PH_SHIFT_POS = 0x1F
180| Shift:
NUM_TX = 0x07
TX_PH_SHIFT_POS = 0x03
Pos. 0
Pos. 1
Pos. 2
Pos. 3
Pos. 4
Pos. 5
Pos. 6
Figure 30. Transmitter Pulse Signature
In some cases, the 180° pulse shift may help improving the turn-off time of a transducer, and thus suppress the
transmit ringing.
The 180° pulse shift is disabled by setting TX_PH_SHIFT_POS to position 31. Setting the 180° pulse shift to
positions 0 or 1 is not recommended.
8.4.3.3 Transmitter Damping
The transmitter damping feature allows for improved control over the transducer signal generation. Damping
extends the duration of the last TX pulse to help dissipate ringing and improve the transducer's turn-off time (see
Figure 31 and Figure 32). The accuracy of measurements can be improved by having a faster transducer turn-off
time. Damping is controlled with the DAMPING bit in the CONFIG_2 register.
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Device Function Description (continued)
Damping extends the duration of
the last pulse to dissipate ringing
Figure 31. Transmitter Damping (5 Tx Pulses With a Damping Pulse)
8.0
Damping disabled
6.0
Damping enabled
4.0
2.0
0.0
-2.0
-4.0
-6.0
-8.0
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
20.0
7LPHꢀꢁꢀVꢂ
Figure 32. Transmitter Damped Echo
There are two invalid use combinations of the damping feature that may result in unexpected behavior. First,
damping should not be combined with the 180° pulse shift described in the previous section. Second, damping
should not be enabled if the number of TX pulses is set to 31.
8.4.4 RECEIVE Operation
8.4.4.1 Single Echo Receive Mode
Single Echo mode can be used for fluid identification measurements or level applications where transducer
carrier frequency information is required. The device can be configured for Single Echo mode by setting the
RECEIVE_MODE bit to 0 in the CONFIG_4 register. In Single Echo mode, the device will generate STOP pulses
for every zero-cross qualified by the threshold comparator, up to the number of expected STOP events
configured in the NUM_RX field in the CONFIG_1 register.
The threshold comparator qualifies the next zero-cross after an RX amplitude smaller than the programmed
threshold voltage is detected. The zero-cross detector will provide output pulses corresponding to the rising edge
of the received signal crossing the VCOM level, as shown in Figure 33. The threshold voltage can be set in the
ECHO_QUAL_THDL field in the CONFIG_3 register.
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Device Function Description (continued)
Zero-crossing detected after
threshold exceeded
COMPIN
VCOM
ECHO_QUAL_THLD
Threshold
Signal exceeds threshold
Output on
STOP pin
Maximum number of requested events (5 in this figure)
returned; subsequent events not reported
Figure 33. Single Echo Receive Mode (5 STOP Events)
If the number of expected pulses programmed in NUM_RX is not received or the time-of-flight operation times
out, the TDC1011 will indicate an error condition in the ERROR_FLAGS register and will set the ERRB pin low.
8.4.4.2 Multiple Echo Receive Mode
The Multiple Echo mode is intended for use in level sensing applications and distance/displacement
measurements in which multiple echoes (burst) are received. In this condition, each received echo group will be
treated as a single pulse on the STOP pin. Up to 7 STOP pulses can be generated based on the value of the
NUM_RX field in the CONFIG_1 register. Multi echo mode can be enabled by setting the RECEIVE_MODE bit to
1 in the CONFIG_4 register. A representation of multiple echo STOP pulse generation is shown in Figure 34.
COMPIN
VCOM
Programmed
threshold
Output on
STOP pin
No pulse on STOP
No pulse on STOP pin because
pin because signal did not
exceed threshold
maximum number of programmed events
(5 in this example) already produced.
Figure 34. Multiple Echo Receive Mode (5 STOP Events)
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Device Function Description (continued)
The rising edge of a STOP pulse is generated by a zero-crossing event. As in the Single Echo Receive Mode,
the threshold comparator qualifies the next zero-cross after an RX amplitude smaller than the programmed
threshold voltage is detected. The STOP pulse will extend until a zero-cross after the RX amplitude is no longer
smaller than the threshold voltage (see Figure 35).
Signal zero-crossing without
exceeding threshold
Zero-crossing detected
after threshold exceeded
COMPIN
VCOM
Programmed
threshold
Signal exceeds
threshold
Output on
STOP pin
Figure 35. Multiple Echo Receive Mode (Zoom-in)
If the number of expected pulses programmed in NUM_RX is not received or the time-of-flight operation times
out, the TDC1011 will indicate an error condition in the ERROR_FLAGS register and will set the ERRB pin low.
8.4.5 Timing
8.4.5.1 Timing Control and Frequency Scaling (CLKIN)
0x09[2] ± CLOCKIN_DIV
1
y 2CLOCKIN_DIV
¦
0
T0 = ꢀ
¦
0
CLKIN
¦
CLKIN
1
y 2TX_FREQ_DIV+1
¦
1
T1 = ꢀ
¦
1
0x00[7:5] ± TX_FREQ_DIV
Figure 36. External Clock Division Tree
All transmit and receive function sequencing is synchronous to the external clock applied to the CLKIN pin. The
external clock is divided to generate two internal clocks with corresponding time periods denoted as T0 and T1 in
Figure 36. The division factor used to generate T0 is controlled with the CLOCKIN_DIV bit in the CLOCK_RATE
register. The division factor used to generate T1 is controlled with the TX_FREQ_DIV field located in the
CONFIG_0 register.
The SPI block is synchronous with the clock applied to the SCLK pin, and it is independent of the clock applied
to CLKIN. See the Serial Peripheral Interface (SPI) section for a complete description of the SPI block.
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Device Function Description (continued)
8.4.5.2 TX/RX Measurement Sequencing and Timing
The TDC1011 automatically sequences the TX and RX functionality. After receiving a pulse edge on the
TRIGGER pin, the TDC1011 resynchronizes to the CLKIN signal, and sends a TX burst.
The trigger edge polarity is configured to rising edge by default, but it can be changed to falling edge by setting
the TRIG_EDGE_POLARITY bit in the CONFIG_4 register to 1.
After a device reset, the system must wait a determined time before sending the next trigger signal. The typical
reset to trigger wait time is 3 × T1 + 50 ns.
8.4.6 Time-of-Flight (TOF) Control
The possible configurations of the TX/RX sequencing during a time-of-flight measurement can be divided into
three cases: Short TOF Measurement, Standard TOF Measurement and Standard TOF Measurement with
Power Blanking. Overall, the cases differ in the order of sequencing, power saving and echo listening windows.
The behavior of each case is described in the sections to follow.
8.4.6.1 Short TOF Measurement
Analog OFF
Analog ON
(see Note A)
TRIG
Echo listen period
TX
(see Note B)
START
(see Note C)
RX
STOP
READY
COMMON-MODE
128 x T0
AUTOZERO
TRANSMIT
MASK
ECHO LISTEN
END READY
1 x T1
2AUTOZERO_PERIOD x 64 x T0
2SHORT_TOF_BLANK_PERIOD x 8 x T0
2TOF_TIMEOUT_CTRL x 128 x T0
NUM_TX x T1
A. Common-mode settling time.
B. If NUM_TX < 3, the width of the START pulse is equal to NUM_TX × T1. If NUM_TX ≥ 3, the width of the START
pulse is equal to 3 × T1.
Figure 37. Short TOF Measurement
In a short time of flight measurement, the RX path is activated before the TX burst, as shown in Figure 37.
The short TOF is the default measurement sequence selected at power-on. The short TOF measurement is
selected if the value of the TIMING_REG[9:0] field is less than 30, or if the FORCE_SHORT_TOF bit is set to 1.
The TIMING_REG[9:0] is a 10-bit wide field, with its 2 most significant bits located in the TOF_1 register, and the
8 least significant bits located in the TOF_0 register. The FORCE_SHORT_TOF bit is located in the TIMEOUT
register.
The comparator's input offset is stored in an internal capacitor during the auto-zero period. The length of the
auto-zero period is controlled by the AUTOZERO_PERIOD field in the CLOCK_RATE register.
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Device Function Description (continued)
The length of the window when the comparators are able to qualify and generate STOP pulses is configured by
the TOF_TIMEOUT_CTRL field. A timeout will occur if the number of expected pulses is not received during the
allocated time and an error condition is reported to the ERROR_FLAGS register and the ERRB pin. It is possible
to disable the echo timeout (see TOF Measurement Interval). The TOF_TIMEOUT_CTRL field is located in the
TIMEOUT register.
See the Timing Control and Frequency Scaling (CLKIN) section for the definition of the time periods T0 and T1.
8.4.6.2 Standard TOF Measurement
Analog OFF
Analog ON
TRIG
Echo listen period
TX
(see Note A)
START
(see Note B)
(see Note C)
RX
STOP
READY
TRANSMIT
COMMON-MODE
128 x T0
AUTOZERO
WAIT / ECHO LISTEN
ECHO LISTEN
END READY
1 x T1
2AUTOZERO_PERIOD x 64 x T0
2TOF_TIMEOUT_CTRL x 128 x T0
NUM_TX x T1
(TIMING_REG ± 30) x 8 x T0
A. Clock alignment.
B. If NUM_TX < 3, the width of the START pulse is equal to NUM_TX × T1. If NUM_TX ≥ 3, the width of the START
pulse is equal to 3 × T1.
C. Common-mode settling time.
Figure 38. Standard TOF Measurement
In a standard time of flight measurement, the RX path is activated after the TX burst is completed, as shown in
Figure 38.
The standard TOF measurement sequence is enabled if the value of the TIMING_REG field is greater than or
equal to 30, and only if the FORCE_SHORT_TOF bit is set to 0. The TIMING_REG is a 10-bit wide field, with its
2 most significant bits located in the TOF_1 register, and the 8 least significant bits located in the TOF_0 register.
The FORCE_SHORT_TOF bit is located in the TIMEOUT register.
The comparator's input offset is stored in an internal capacitor during the auto-zero period. The length of the
auto-zero period is controlled by the AUTOZERO_PERIOD field in the CLOCK_RATE register.
The length of the window when the comparators are able to qualify and generate STOP pulses is configured by a
combination of the TIMING_REG field and the TOF_TIMEOUT_CTRL field. With the addition of the
TIMING_REG in the calculation, the standard TOF measurement allows for a longer wait time and listening
window. A timeout will occur if the number of expected pulses is not received during the allocated time and an
error condition is reported to the ERROR_FLAGS register and the ERRB pin. It is possible to disable the echo
timeout (see TOF Measurement Interval). The TOF_TIMEOUT_CTRL field is located in the TIMEOUT register.
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Device Function Description (continued)
NOTE
If the FORCE_SHORT_TOF bit = 1, the measurement sequencing will behave as a Short
TOF Measurement, thus overriding the setting of the TIMING_REG field.
8.4.6.3 Standard TOF Measurement with Power Blanking
Analog OFF
Analog ON
TRIG
TX
Echo listen period
(see Note A)
START
RX
(see Note B)
(see Note C)
STOP
READY
TRANSMIT
NUM_TX x T1
WAIT
COMMON-MODE
128 x T0
AUTOZERO
ECHO LISTEN
END READY
1 x T1
2AUTOZERO_PERIOD x 64 x T0
2TOF_TIMEOUT_CTRL x 128 x T0
(TIMING_REG ± 30) x 8 x T0
A. Clock alignment.
B. If NUM_TX < 3, the width of the START pulse is equal to NUM_TX × T1. If NUM_TX ≥ 3, the width of the START
pulse is equal to 3 × T1.
C. Common-mode settling time.
Figure 39. Standard TOF Measurement with Blanking Enabled
The power blanking sequence is a variation to the standard TOF measurement sequence, and can be enabled
by setting the BLANKING bit to 1. In addition, all other conditions described in the Standard TOF Measurement
should be met. The BLANKING bit can be found in the CONFIG_3 register.
Power blanking allows the device to remain in a low-power state while the TX signals propagate to the RX
transducer in situations when the expected time-of-flight is long. Power blanking uses the TIMING_REG to
control a wait time between the transmit sequence and the receive sequence, during which, the complete RX
chain is disabled, as shown in Figure 39. The TIMING_REG is a 10-bit wide field, with its 2 most significant bits
located in the TOF_1 register, and the 7 least significant bits located in the TOF_0 register.
8.4.6.4 Common-mode Reference Settling Time
The duration of the common-mode settling time is defined by the VCOM capacitor. With a 10-nF VCOM
capacitor, the common-mode reference requires 16 µs to settle. On the other hand, the duration of the common-
mode settling window is defined as 128 × T0, where the time unit T0 is determined by the external clock
frequency and the value of the CLOCKIN_DIV bit, as explained in the Timing Control and Frequency Scaling
(CLKIN) section.
A frequency of 8 MHz will result in a settling window of 128 × 1 / 8 MHz, which equals to 16 µs. Increasing the
value of the VCOM capacitor will increase the common-mode settling time, but for the same 8-MHz frequency,
the duration of the common-mode settling window will remain at 16 µs. In such situation, the common-mode
reference will take multiple TOF cycles to reach its final value when starting from zero initial conditions.
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Device Function Description (continued)
8.4.6.5 TOF Measurement Interval
The comparators in the TDC1011's RX path can qualify and generate STOP pulses from a received echo within
an interval set by the TOF_TIMEOUT_CTRL field in the TIMEOUT register. The listening interval can be
extended in the standard TOF measurement (without blanking) by a period controlled with the TIMING_REG field
(see Standard TOF Measurement).
If the number of STOP events programmed in the NUM_RX field is not received within the listening interval, a
timeout event will occur and the device will return to the READY state. In addition, an error will be reported to the
ERROR_FLAGS register and the ERRB pin will be driven low.
The echo timeout can be disabled by setting the ECHO_TIMEOUT bit to 1 in the TIMEOUT register. If the echo
timeout is disabled, the device will not exit from the receive state until the expected number of STOP events set
in NUM_RX occur. If the number of events does not occur, the device can be forced out of the receive state by
writing a value of 0x03 to the ERROR_FLAGS register, or by de-asserting the EN pin, or asserting the RESET
pin.
NOTE
Writing a logic 1 to bit [1] of the ERROR_FLAGS register clears the state machine. Writing
a logic 1 to bit[0] clears the error flags.
NOTE
It is not recommended to hold the RX in an active state for intervals longer than 100ms, as
the comparator auto-zero may no longer be accurate.
8.4.7 Error Reporting
The TDC1011 will report an error when the receive signals do not match the expected configuration. The ERRB
pin will go low to indicate the presence of an error condition. Reading the ERROR_FLAGS register provides
information about the condition(s) that caused the error.
The ERR_SIG_WEAK bit indicates that the number of received and qualified zero-crossings was less than the
expected number set in the NUM_RX register field and a timeout occurred. This error is cleared when bit [0] is
written to 1.
The ERR_NO_SIG bit indicates that no signals were received and a timeout occurred. Writing a 1 to this bit
resets the state machine, halts active measurements and returns the device to SLEEP or READY mode. This
error is cleared when bit [0] is written to 1.
The ERR_SIG_HIGH bit indicates that the received echo amplitude exceeds the largest echo qualification
threshold at the input of the comparators. The ERR_SIG_HIGH error is only reported when the
ECHO_QUAL_THDL register field is set to 7h. Writing a 1 to this bit will reset all the error flags and reset the
ERRB pin to high.
NOTE
It is recommended to reset the state machine when the error flags are cleared. This can
be done simultaneously by writing a value of 0x03 to the ERROR_FLAGS register.
8.5 Programming
8.5.1 Serial Peripheral Interface (SPI)
The serial interface consists of serial data input (SDI), serial data output (SDO), serial interface clock (SCLK) and
chip select bar (CSB). The serial interface is used to configure the TDC1011 parameters available in various
configuration registers. All the registers are organized into individually addressable byte-long registers with a
unique address.
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Programming (continued)
The communication on the SPI bus normally supports write and read transactions. A write transaction consists of
a single write command byte, followed by single data byte. A read transaction consists of a single read command
byte followed by 8 SCLK cycles. The write and read command bytes consist of 1 reserved bit, a 1-bit instruction,
and a 6-bit register address. Figure 40 shows the SPI protocol for a transaction involving one byte of data (read
or write).
CSB
11
14
1
2
3
4
5
6
7
8
9
10
12
13
15
16
SCK
COMMAND FIELD
DATA FIELD
MSB
LSB
SDI
c0
d6
c7
c6
c5
c4
c3
c2
c1
d7
d5
d4
d3
d2
d1
d0
Address (6 bits)
resvd
R/W
Write Data (8-bits)
MSB
LSB
SDO
d6
d7
d5
d4
d3
d2
d1
d0
R/W = Instruction
0: Read
Read Data (8-bits)
1: Write
Note: Specifying any value other than zero in bit[7] of the command byte is prohibited.
Figure 40. SPI Protocol
8.5.1.1 Chip Select Bar (CSB)
CSB is an active-low signal and needs to be low throughout a transaction. That is, CSB should not pulse
between the command byte and the data byte of a single transaction.
De-asserting CSB always terminates an ongoing transaction, even if it is not yet complete. Re-asserting CSB will
always bring the device into a state ready for the next transaction, regardless of the termination status of a
previous transaction.
8.5.1.2 Serial Clock (SCLK)
SCLK can idle high or low. It is recommended to keep SCLK as clean as possible to prevent glitches from
corrupting the SPI frame.
8.5.1.3 Serial Data Input (SDI)
SDI is driven by the SPI master by sending the command and the data byte to configure the AFE.
8.5.1.4 Serial Data Output (SDO)
SDO is driven by the AFE when the SPI master initiates a read transaction.
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8.6 Register Maps
NOTE
•
•
•
Reserved bits must be written to 0 unless otherwise indicated.
Read-back value of reserved bits and registers is unspecified and should be discarded.
Recommended values must be programmed and forbidden values must not be
programmed where they are indicated to avoid unexpected results.
8.6.1 TDC1011 Registers
Table 3 list the memory-mapped registers for the TDC1011. All register addresses not listed in Table 3 should be
considered as reserved locations and the register contents should not be modified.
Table 3. TDC1011 REGISTERS
Address (Hex)
Acronym
Register Name
Config-0
Config-1
Config-2
Config-3
Config-4
TOF-1
Reset Value
Section
See here
See here
See here
See here
See here
See here
See here
See here
See here
See here
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
CONFIG_0
CONFIG_1
CONFIG_2
CONFIG_3
CONFIG_4
TOF_1
45h
40h
0h
3h
1Fh
0h
TOF_0
TOF-0
0h
ERROR_FLAGS
TIMEOUT
CLOCK_RATE
Error Flags
Timeout
0h
19h
0h
Clock Rate
8.6.1.1 CONFIG_0 Register (address = 0h) [reset = 45h] (map)
Figure 41. CONFIG_0 Register
(MSB) 7
6
5
4
3
2
1
0 (LSB)
TX_FREQ_DIV
R/W-2h
NUM_TX
R/W-5h
LEGEND: R/W = Read or write; R = Read only; R/W1C = Read or write 1 to clear
Table 4. CONFIG_0 Register Field Descriptions
Bit
Field
Type
Reset
Description
Frequency divider for TX clock and T1
0h: Divide by 2
1h: Divide by 4
2h: Divide by 8 (default)
3h: Divide by 16
[7:5]
TX_FREQ_DIV(1)
R/W
2h
4h: Divide by 32
5h: Divide by 64
6h: Divide by 128
7h: Divide by 256
Number of TX pulses in a burst, ranging from 0 to 31.
5h: 5 pulses (default)
[4:0]
NUM_TX
R/W
5h
(1) See Timing Control and Frequency Scaling (CLKIN) for the definition of the time period T1.
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8.6.1.2 CONFIG_1 Register (address = 1h) [reset = 40h] (map)
Figure 42. CONFIG_1 Register
(MSB) 7
RESERVED
R/W-1h
6
5
4
3
2
1
0 (LSB)
RESERVED
R/W-0h
NUM_RX
R/W-0h
LEGEND: R/W = Read or write; R = Read only; R/W1C = Read or write 1 to clear
Table 5. CONFIG_1 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
1h
Description
[7:6]
[5:3]
RESERVED
RESERVED
1h: Reserved (default)
0h
Must always be written 0h (default)
Number of expected receive events
0h: Do not count events (32 STOP pulses output) (default)
1h: 1 event (1 STOP pulse output)
2h: 2 events (2 STOP pulses output)
3h: 3 events (3 STOP pulses output)
4h: 4 events (4 STOP pulses output)
5h: 5 events (5 STOP pulses output)
6h: 6 events (6 STOP pulses output)
7h: 7 events (7 STOP pulses output)
[2:0]
NUM_RX
R/W
0h
8.6.1.3 CONFIG_2 Register (address = 2h) [reset = 0h] (map)
Figure 43. CONFIG_2 Register
(MSB) 7
VCOM_SEL
R/W-0h
6
5
4
3
2
1
0 (LSB)
MEAS_MODE
R/W-0h
DAMPING
R/W-0h
RESERVED
R/W-0h
LEGEND: R/W = Read or write; R = Read only; R/W1C = Read or write 1 to clear
Table 6. CONFIG_2 Register Field Descriptions
Bit
Field
Type
Reset
Description
Common-mode voltage reference control
0h: Internal (default)
[7]
VCOM_SEL
R/W
0h
1h: External
AFE measurement type
[6]
MEAS_MODE
R/W
0h
0h: Time-of-flight measurement (default)
1h: Temperature measurement
TX burst damping
[5]
DAMPING
R/W
R/W
0h
0h
0h: Disable damping (default)
1h: Enable damping
[4:0]
RESERVED
Must always be written 0h (default)
8.6.1.4 CONFIG_3 Register (address 3h) [reset = 3h] (map)
Figure 44. CONFIG_3 Register
(MSB) 7
RESERVED
R/W-0h
6
5
4
3
2
1
0 (LSB)
TEMP_MODE
R/W-0h
TEMP_RTD_SEL TEMP_CLK_DIV
R/W-0h R/W-0h
BLANKING
R/W-0h
ECHO_QUAL_THLD
R/W-3h
LEGEND: R/W = Read or write; R = Read only; R/W1C = Read or write 1 to clear
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Table 7. CONFIG_3 Register Field Descriptions
Bit
Field
Type
Reset
Description
[7]
RESERVED
R/W
0h
0h: Reserved (default)
Temperature measurement channels
0h: Measure REF, RTD1 and RTD2 (default)
1h: Measure REF and RTD1
[6]
[5]
[4]
TEMP_MODE
R/W
R/W
R/W
0h
0h
0h
RTD type
TEMP_RTD_SEL
TEMP_CLK_DIV
0h: PT1000 (default)
1h: PT500
Clock divider for temperature mode
0h: Divide by 8 (default)
1h: Use TX_FREQ_DIV
Power blanking in standard TOF measurements. The blanking
length is controlled with the TIMING_REG field (see Standard
TOF Measurement with Power Blanking).
[3]
BLANKING
R/W
0h
0h: Disable power blanking (default)
1h: Enable power blanking
Echo qualification DAC threshold level with respect to VCOM
0h: –35 mV
1h: –50 mV
2h: –75 mV
[2:0]
ECHO_QUAL_THLD
R/W
3h
3h: –125 mV (default)
4h: –220 mV
5h: –410 mV
6h: –775 mV
7h: –1500 mV
8.6.1.5 CONFIG_4 Register (address = 4h) [reset = 1Fh] (map)
Figure 45. CONFIG_4 Register
(MSB) 7
RESERVED
R/W-0h
6
5
4
3
2
1
0 (LSB)
RECEIVE_
MODE
TRIG_EDGE_
POLARITY
TX_PH_SHIFT_POS
R/W-1Fh
R/W-0h
R/W-0h
LEGEND: R/W = Read or write; R = Read only; R/W1C = Read or write 1 to clear
Table 8. CONFIG_4 Register Field Descriptions
Bit
Field
Type
Reset
Description
[7]
RESERVED
R/W
0h
0h: Reserved (default)
Receive echo mode
0h: Single echo (default)
1h: Multi echo
[6]
[5]
RECEIVE_MODE
R/W
R/W
R/W
0h
Trigger edge polarity
0h: Rising edge (default)
1h: Falling edge
TRIG_EDGE_POLARITY
TX_PH_SHIFT_POS
0h
TX 180° pulse shift position, ranging from 0 to 31.
1Fh: Position 31 (default)
[4:0]
1Fh
It is not recommended to set TX_PH_SHIFT_POS to 0 or 1.
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8.6.1.6 TOF_1 Register (address = 5h) [reset = 0h] (map)
Figure 46. TOF_1 Register
(MSB) 7
6
5
4
3
2
1
0 (LSB)
PGA_GAIN
R/W-0h
PGA_CTRL
R/W-0h
LNA_CTRL
R/W-0h
LNA_FB
R/W-0h
TIMING_REG[9:8]
R/W-0h
LEGEND: R/W = Read or write; R = Read only; R/W1C = Read or write 1 to clear
Table 9. TOF_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
PGA gain
0h: 0 dB (default)
1h: 3 dB
2h: 6 dB
[7:5]
PGA_GAIN
R/W
0h
3h: 9 dB
4h: 12 dB
5h: 15 dB
6h: 18 dB
7h: 21 dB
PGA control
[4]
[3]
[2]
PGA_CTRL
LNA_CTRL
LNA_FB
R/W
R/W
R/W
0h
0h
0h
0h: Active (default)
1h: Bypassed and powered off
LNA control
0h: Active (default)
1h: Bypassed and powered off
LNA feedback mode
0h: Capacitive feedback (default)
1h: Resistive feedback
TIMING_REG field's 2 most-significant bits (see Standard TOF
Measurement and Standard TOF Measurement with Power
Blanking)
[1:0]
TIMING_REG[9:8]
R/W
0h
0h: 0 (default)
8.6.1.7 TOF_0 Register (address = 6h) [reset = 0h] (map)
Figure 47. TOF_0 Register
(MSB) 7
6
5
4
3
2
1
0 (LSB)
TIMING_REG[7:0]
R/W-0h
LEGEND: R/W = Read or write; R = Read only; R/W1C = Read or write 1 to clear
Table 10. TOF_0 Register Field Descriptions
Bit
Field
Type
Reset
Description
TIMING_REG field's 8 least-significant bits (see Standard TOF
Measurement and Standard TOF Measurement with Power
Blanking)
[7:0]
TIMING_REG[7:0]
R/W
0h
0h: 0 (default)
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8.6.1.8 ERROR_FLAGS Register (address = 7h) [reset = 0h] (map)
Figure 48. ERROR_FLAGS Register
7 (MSB)
6
5
4
3
2
1
0 (LSB)
ERR_
SIG_WEAK
ERR_
SIG_HIGH
RESERVED
R-0h
ERR_NO_SIG
R/W1C-0
R-0h
R/W1C-0
LEGEND: R/W = Read or write; R = Read only; R/W1C = Read or write 1 to clear
Table 11. ERROR_FLAGS Register Field Descriptions(1)(2)
Bit
Field
Type
Reset
Description
[7:3]
RESERVED
R
0h
0h: Reserved (default)
1h: The number of received and qualified zero-crossings was
less than the expected number set in NUM_RX field and a
timeout occurred.
[2]
[1]
ERR_SIG_WEAK
ERR_NO_SIG
R
0h
0h
1h: No signals were received and timeout occurred.
Writing a 1 to this field resets the state machine, halts active
measurements and returns the device to the SLEEP or READY
mode.
R/W1C
1h: The received echo amplitude exceeds the largest echo
qualification threshold at the input of the comparators. The error
is only reported when ECHO_QUAL_THLD = 0x07.
[0]
ERR_SIG_HIGH
R/W1C
0h
Writing a 1 to this field will reset all the error flags and reset the
ERRB pin to high.
(1) It is recommended to read the error status register or the ERRB pin before initiating a new measurement.
(2) All error flags should be cleared before initiating a new measurement.
8.6.1.9 TIMEOUT Register (address = 8h) [reset = 19h] (map)
Figure 49. TIMEOUT Register
(MSB) 7
RESERVED
R/W-0h
6
5
4
3
2
1
0 (LSB)
FORCE_
SHORT_TOF
ECHO_
TIMEOUT
SHORT_TOF_BLANK_PERIOD
R/W-3h
TOF_TIMEOUT_CTRL
R/W-0h
R/W-0h
R/W-1h
LEGEND: R/W = Read or write; R = Read only; R/W1C = Read or write 1 to clear
Table 12. TIMEOUT Register Field Descriptions
Bit
Field
Type
Reset
Description
[7]
RESERVED
R/W
0h
0h: Reserved (default)
Short time-of-flight control
0h: Disabled (default)
[6]
FORCE_SHORT_TOF
R/W
0h
1h: Force a short time-of-flight measurement
Short time-of-flight blanking period (see Short TOF
Measurement)
0h: 8 × T0
1h: 16 × T0
2h: 32 × T0
[5:3]
SHORT_TOF_BLANK_PERIOD(1)
R/W
3h
3h: 64 × T0 (default)
4h: 128 × T0
5h: 256 × T0
6h: 512 × T0
7h: 1024 × T0
(1) See Timing Control and Frequency Scaling (CLKIN) for the definition of the time period T0.
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Table 12. TIMEOUT Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
Echo receive timeout control (see TOF Measurement Interval)
0h: Enable echo timeout (default)
[2]
ECHO_TIMEOUT
R/W
0h
1h: Disable timeout
Echo listening window timeout (see TOF Measurement Interval)
0h: 128 × T0
[1:0]
TOF_TIMEOUT_CTRL(1)
R/W
1h
1h: 256 × T0 (default)
2h: 512 × T0
3h: 1024 × T0
8.6.1.10 CLOCK_RATE Register (address = 9h) [reset = 0h] (map)
Figure 50. CLOCK_RATE Register
(MSB) 7
6
5
4
3
2
1
0 (LSB)
RESERVED
R/W-0h
CLOCKIN_DIV
R/W-0h
AUTOZERO_PERIOD
R/W-0h
LEGEND: R/W = Read or write; R = Read only; R/W1C = Read or write 1 to clear
Table 13. CLOCK_RATE Register Field Descriptions(1)
Bit
Field
Type
Reset
Description
[7:3]
RESERVED
R/W
0h
0h: Reserved (default)
CLKIN divider to generate T0
0h: Divide by 1 (default)
1h: Divide by 2
[2]
CLOCKIN_DIV(1)
R/W
R/W
0h
0h
Receiver auto-zero period
0h: 64 × T0 (default)
1h: 128 × T0
[1:0]
AUTOZERO_PERIOD(1)
2h: 256 × T0
3h: 512 × T0
(1) See Timing Control and Frequency Scaling (CLKIN) for the definition of the time period T0.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TDC1011 is an analog front-end for ultrasonic sensing applications. The device is typically used for the
driving and sensing of ultrasonic transducers to perform accurate time-of-flight measurements. Ultrasonic time-of-
flight sensing allows for fluid level, fluid identification or concentration measurements.
9.2 Typical Applications
9.2.1 Level and Fluid Identification Measurements
Concentration
RREF
Level
RTD
START
STOP
TX
OR Gate
TDC1011
RX
16-MHz CLK
OSC
TMS320F28035
C2000 MCU
Figure 51. Level or Concentration Measurement Application Diagram
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Typical Applications (continued)
9.2.1.1 Design Requirements
Table 14. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Fluid Level
Range
2 – 10 cm
Fluid Identification
Accuracy
0.5% concentration variation
5.08 cm
Distance
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Level Measurements
For level sensing applications, the total time-of-flight (TOF) of the sound wave in the fluid is measured. The
pulses transmitted by a bottom mounted transducer travel through the fluid, to the surface of the fluid. The
discontinuity between the fluid and air generates a reflected wave which returns back to the bottom mounted
transducer.
At the beginning of a measurement cycle, the transducer is connected to a transmit channel of the AFE, and the
transmit burst excites the transducer to generate an ultrasound wave. Synchronous to the TX burst, a START
pulse is generated by the TDC1011 to indicate the start of a measurement. After the transmission is completed,
and depending on the device configuration, the transducer is connected to a receive channel of the AFE.
When a valid echo is received, the TDC1011 generates a STOP pulse. Generation of multiple STOP pulses is
possible through register configuration of the device. The START and STOP signal times are compared to
determine the TOF.
The level of the fluid can be determined using the following equation:
61( × ?
@ =
2
where
•
•
•
d is the fluid level in meters (m)
TOF is the time-of-flight in seconds (s)
c is the speed of sound in the fluid in meters per second (m/s)
(6)
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Trigger
START
TX
Echo Pulse
received
RX
TOF
STOP
Figure 52. Relation Between Transmit and Receive Pulses in Level Measurements
Level measurements have 2 main criteria: resolution and range (maximum height). Resolution accuracies of 1-2
mm are achievable but are impractical due to any environmental disturbances, such as tank vibrations, creating
millimeter level surface waves. Ranges of up to 1 m are measurable utilizing VDD level excitation pulses, but
surface disturbances and signal loss over longer distances make the reliable echo reception an issue. Greater
level measurement reception can be achieved by mechanical means (level guide tube) and/or electronic means
(level shifting the TX pulses to greater voltages; see TIDA-00322).
9.2.1.2.2 Fluid Identification
The TDC1011 can be used to measure the time-of-flight for a known distance to calculate the speed of sound
(cmedium) in the fluid. This application utilizes the same circuitry as the level example but a transducer in a side
mounted configuration transmitting across the container or to a target at a known distance from the transducer.
The temperature can also be measured to compensate for the temperature variation of sound. With the known
distance, TOF and temperature, the speed of sound in the fluid can be determined and the identity of the
medium verified.
After measuring the time-of-flight for the fixed distance, the speed of sound can be calculated as follows:
2 × @
?
=
IA@EQI
61(
where
•
•
•
cmedium is the speed of sound in the fluid in meters per second (m/s)
d is the level in meters (m)
TOF is the time of flight in seconds (s)
(7)
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The measurement process is identical to the level example above. The speed of sound can be used to uniquely
identify a variety of fluids. In this example, the concentration of diesel exhaust fluid (DEF) is measured with a
desired accuracy resolution of 0.5% of concentration variation. For most fluids, the speed of sound varies over
temperature, so every application will be different. In this example, all samples were all at ambient temperature of
23°C.
9.2.1.3 Application Curves
The data used in the following level and fluid identification graphs was collected using an ultrasonic test cell. The
test cell is an acrylic plastic container with width of 2.54 cm and ultrasonic transducers attached to the outside
using cyanoacrylate glue. The transducers in this experiment were STEMiNC 1MHz piezo electric ceramic discs
(SMD10T2R111). Equivalent transducers with the following characteristics could be used:
•
•
•
Piezo material: SM111
Dimensions: 10mm diameter x 2mm thickness
Resonant frequency: 1050 kHz (thickness mode)
1650
1625
1600
1575
1550
1525
1500
1475
1450
1425
1400
150
135
120
105
90
75
60
45
30
r
r
2
3
4
5
6
7
8
9
10
e
Height (cm)
Wat
Tap Wate
Fluid Height in Tank
Full (10 cm)
Full – 1 (9 cm)
Full – 2 (8 cm)
3 cm
Time-of-Flight (µs)
DEF 10.0%DEF 20.0%DEF 30.0%DEF 31.5%DEF 32.0%DEF 32.5%
Distilled
145
131
118
50
Fluid
Speed of sound (m/s)
Distilled water
Tap water
1481.87
1483.13
1530.49
1576.42
1620.00
1627.37
1629.15
1630.00
DEF 10.0%
DEF 20.0%
DEF 30.0%
DEF 31.5%
DEF 32.0%
DEF 32.5%
2 cm
35
Figure 53. Time-of-Flight for Fluid Height in Tank
Figure 54. Speed of Sound for Various Fluids and Diesel
Exhaust Fluid (DEF) Concentration
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1483.5
1483.0
1482.5
1482.0
1481.5
1481.0
1632
1630
1628
1626
1624
1622
1620
1618
r
r
e
Wat
30.0%
31.5%
32.0%
32.5%
Tap Wate
DEF
DEF
DEF
DEF
Distilled
Fluid
Speed of sound (m/s)
1620.00
Fluid
Speed of sound (m/s)
1481.87
DEF 30.0%
DEF 31.5%
DEF 32.0%
DEF 32.5%
Distilled water
Tap water
1627.37
1483.13
1629.15
1630.00
Figure 55. Speed of Sound in Distilled Water and Tap
Water
Figure 56. Speed of Sound of Various Diesel Exhaust Fluid
(DEF) Concentrations
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10 Power Supply Recommendations
The analog circuitry of the TDC1011 is designed to operate from an input voltage supply range between 2.7V
and 5.5V. It is recommended to place a 100nF ceramic bypass capacitor to ground as close as possible to the
VDD pins. In addition, an electrolytic or tantalum capacitor with value greater than 1µF is recommended. The
bulk capacitor does not need to be in close vicinity with the TDC1011 and could be close to the voltage source
terminals or at the output of the voltage regulators powering the TDC1011.
The IO circuitry of the TDC1011 is designed to operate from an input voltage supply range between 1.8V and
5.5V. The IO voltage supply (VIO) can be lower than the analog voltage supply (VDD), but it should not exceed it.
It is also recommended to place a 100nF ceramic bypass capacitor to ground as close as possible to the VIO
pin. If a separate source or regulator is used for VIO, an additional electrolytic or tantalum capacitor with value
greater than 1µF is recommended.
In some cases an additional 10µF bypass capacitor may further reduce the supply noise.
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11 Layout
11.1 Layout Guidelines
•
In a 4-layer board design, the recommended layer stack order from top to bottom is: signal, ground, power
and signal.
•
•
Bypass capacitors should be placed in close proximity to the VDD and VIO pins.
The length of the START and STOP traces from the DUT to the stopwatch/MCU should be matched to
prevent uneven signal delays. Also, avoid unnecessary via-holes on these traces and keep the routing as
short/direct as possible to minimize parasitic capacitance on the PCB.
•
•
Match the length (or resistance) of the traces leading to the RTD sensors. PCB series resistance will be
added in series to the RTD sensors.
Route the SPI signal traces close together. Place a series resistor at the source of SDO (close to the DUT)
and series resistors at the sources of SDI, SCLK and CSB (close to the master MCU).
11.2 Layout Example
VIA to Ground Plane
VIA to Bottom or Internal Layer
Top Layer
Bottom Layer
GND
NC
RX
1
TX
NC
GND
System Clock
VCOM
GND
CLKIN
VDD
VDD
VIO
GND
LNAOUT
PGAIN
RTD1
PGAOUT
COMPIN
SDO
SDI
RTD1
RTD2
To RTDs: Match trace
length (resistance)
MCU
SPI Master
CSB
SCLK
RESET
RREF
RES
GND
ERRB
START
STOP
RTD2
MCU
I/Os
Trigger:stop
watch/MCU
TRIGGER
EN
GND
Matched
trace
length to
stopwatch
/MCU
MCU
I/Os
Figure 57. TDC1011 Board Layout (Capacitive Feedback Mode)
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.1.2 Development Support
For development support see the following:
•
Automotive Ultrasonic Fluid Level/Quality Measurement Reference Design, TIDA-00322
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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12-Jul-2015
PACKAGING INFORMATION
Orderable Device
TDC1011PW
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
TSSOP
TSSOP
PW
28
28
48
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
TDC1011PW
TDC1011PWR
ACTIVE
PW
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
TDC1011PW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jul-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TDC1011 :
Automotive: TDC1011-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jul-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TDC1011PWR
TSSOP
PW
28
2500
330.0
16.4
6.8
10.2
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jul-2015
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 28
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
TDC1011PWR
2500
Pack Materials-Page 2
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