TDP1204 [TI]
12Gbps DP++ 1.1 至 HDMI 2.1 源侧转接驱动器;
| 型号： | TDP1204 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12Gbps DP++ 1.1 至 HDMI 2.1 源侧转接驱动器 驱动 驱动器 |
| 文件： | 总77页 (文件大小：2771K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TDP1204
ZHCSQR9 –JULY 2022
TDP1204 12Gbps、直流/交流耦合转HDMI™ 2.1 电平转换器混合转接驱动器
1 特性
3 说明
• 支持高达12Gbps HDMI 2.1 数据速率的交流耦合或
直流耦合输入和输出
TDP1204 是一款 HDMI 2.1 转接驱动器，支持高达
12Gbps 的数据速率，向后兼容 HDMI 1.4b 和 HDMI
2.0b。高速差分输入和输出可以是交流耦合或直流耦
合，支持将TDP1204 用作DP++ 转HDMI 电平转换器
或 HDMI 转接驱动器。TDP1204 可支持 3、6、8、10
和12Gbps 的三通道和四通道HDMI 2.1 FRL。
– 向后兼容HDMI 1.4b 和HDMI 2.0b
– HDMI 2.1 固定速率链路(FRL) 为3、6、8、10
和12Gbps
– 支持HDMI 2.1 三通道和四通道FRL
• 已针对HDMI 源应用进行优化
• 6GHz 时高达12dB 的可编程接收器均衡器
• I2C 或引脚搭接可编程
• 集成的HPD 电平转换器同时支持1.8V 和3.3V
LVCMOS 电平
• 集成的DDC 缓冲器支持最低1.2V 电平
• 主通道上全通道交换
• 用于链路配置的数字显示控制(DDC) 监控功能
• 低功耗：
TDP1204 是一款混合转接驱动器，同时支持源端和接
收端应用。混合转接驱动器可用作线性转接驱动器，也
可用作限幅转接驱动器。配置为限幅转接驱动器时，
TDP1204 的差分输出电压电平独立于图形处理单元
(GPU) 的输出电平，从而确保插座的 HDMI 电平符合
要求。限幅转接驱动器模式推荐用于 HDMI 源端应
用。配置为线性转接驱动器时，TDP1204 的差分输出
电平是 GPU 输出电平的线性函数，从而支持将
TDP1204 用于透明呈现链路训练或用作通道缩短器。
建议将线性转接驱动器模式用于HDMI 接收端应用。
– 12G FRL 四通道有源限制：575mW
– 12G FRL 四通道有源线性：220mW
– 断电：0.6mW
TDP1204 有一个集成的 HPD 电平转换器，该转换器
可将 5V HPD 信号转换为 1.8V 或 3.3V。电平转换器
输出还可配置为推挽式或开漏式。另外，TDP1204 还
集成了一个数字显示控制 (DDC) 缓冲器。DDC 缓冲器
可提供电容隔离，电平转换器可将 5V DDC 电平转换
为 3.3V、1.8V 或 1.2V 电平。集成电平转换器后，无
需分立式解决方案，因此节省了系统成本。
• 可用于商业级和工业级温度范围
• 3.3V 单电源
• 40 引脚0.4mm 间距4mm × 6mm WQFN 封装
2 应用
• 笔记本电脑和台式机
• 电视
• 家庭影院和娱乐系统
• 游戏系统
• 扩展坞
TDP1204 支持 3.3V VCC 单电源轨，可用于商业级温
度范围(TDP1204) 和工业级温度范围(TDP1204I)。
器件信息(1)
• 专业音频、视频和标牌
封装尺寸（标称值）
器件型号
TDP1204
封装
WQFN (40)
1.14V to
4.00mm × 6.00mm
3.3V
3.6V
Optional
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
OUT_D2p
OUT_D2n
IN_D2p
IN_D2n
OUT_D1p
OUT_D1n
IN_D1p
IN_D1n
OUT_D0p
OUT_D0n
IN_D0p
IN_D0n
GPU
(DP++, HDMI)
OUT_CLKp
OUT_CLKn
IN_CLKp
IN_CLKn
HDMI_5V
LV_DDC_SDA HV_DDC_SDA
LV_DDC_SCL
HPD_OUT
HV_DDC_SCL
HPD_IN
简化版原理图
.
.
.
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSFI6
TDP1204
ZHCSQR9 –JULY 2022
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Table of Contents
8.5 Register Maps...........................................................47
9 Application and Implementation..................................60
9.1 Application Information............................................. 60
9.2 Typical Source-Side Application............................... 60
9.3 Typical Sink-Side Application....................................65
10 Power Supply Recommendations..............................69
10.1 Supply Decoupling..................................................69
11 Layout...........................................................................69
11.1 Layout Guidelines................................................... 69
11.2 Layout Example...................................................... 70
12 Device and Documentation Support..........................71
12.1 Documentation Support.......................................... 71
12.2 接收文档更新通知................................................... 71
12.3 支持资源..................................................................71
12.4 Trademarks.............................................................71
12.5 Electrostatic Discharge Caution..............................71
12.6 术语表..................................................................... 71
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................6
6.6 Timing Requirements................................................13
6.7 Switching Characteristics..........................................14
6.8 Typical Characteristics..............................................17
7 Parameter Measurement Information..........................18
8 Detailed Description......................................................24
8.1 Functional Block Diagram ........................................24
8.2 Feature Description...................................................25
8.3 Device Functional Modes..........................................37
8.4 Programming............................................................ 42
Information.................................................................... 71
4 Revision History
DATE
REVISION
NOTES
July 2022
*
Initial Release
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5 Pin Configuration and Functions
VCC
1
28
27
26
25
24
23
22
21
VCC
HPDOUT_SEL
2
3
HV_DDC_SCL
HV_DDC_SDA
LV_DDC_SDA
LV_DDC_SCL
AC_EN
TEST1
CTLEMAP_SEL
4
5
6
7
8
Thermal
Pad
LINEAR_EN
VCC
EN
SDA/CFG1
SCL/CFG0
EQ1
Not to scale
图5-1. RNQ Package 40-Pin WQFN (Top View)
表5-1. Pin Functions
DESCRIPTION
PIN
TYPE(1)
NAME
NO.
VCC
1
P
I
3.3-V power supply
HPDOUT_SEL. Selects whether HPD_OUT pin is push, pull, or open-drain. Open-drain is not
HPDOUT_SEL
TEST1
2
3
2-level (PD) supported in pin-strap mode. Therefore this pin should be left floating or pull-down to GND.
O
Test1. For TI internal use only. This pin can be left unconnected.
CTLE Map select. When TDP1204 is configured in pin-strap mode, this pin selects the CTLE
Map used. 表8-8 lists more details. Also in pin-strap this pin will control whether or not AEQ is
enabled. 表8-9 lists more details. In I2C mode, CTLE map and AEQ enable is determined by
registers.
I
CTLEMAP_SEL
4
4-level
(PU/PD)
I
In pin-strap mode, selects whether TDP1204 operates in linear or limited redriver mode. 表8-5
lists more details.
LINEAR_EN
VCC
5
6
4-level
(PU/PD)
P
3.3-V power supply
When low, TDP1204 will be held in reset. The IN_D[2:0], IN_CLK, OUT_D[2:0] and OUT_CLK
pins will be held in high impedance while EN is low. On rising edge of EN, the device will sample
2-level (PU) four-level inputs and function based on the sampled state of the pins. This pin has an internal
250-k pull-up to VIO.
I
EN
7
8
I
EQ1 pin setting when TDP1204 is configured for pin strap mode; works in conjunction with EQ0;
表8-6 lists the settings. In I2C mode, EQ settings are controlled through the registers.
EQ1
4-level
(PU/PD)
IN_D2p
IN_D2n
9
I
I
Channel 2 differential positive input
Channel 2 differential negative input
10
Hot plug detect output to source side. If not used, then this pin can be left floating. If used, then it
is recommended to have an external 220k resistor to GND on this pin.
HPD_OUT
11
O
IN_D1p
IN_D1n
12
13
I
I
Channel 1 differential positive input.
Channel 1 differential negative input.
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表5-1. Pin Functions (continued)
PIN
NAME
TYPE(1)
DESCRIPTION
NO.
14
VIO
P
I
Voltage supply for I/Os. 表8-2 lists more details.
Channel 0 differential positive input
IN_D0p
IN_D0n
15
16
I
Channel 0 differential negative input
I
MODE
17
4-level
(PU/PD)
Mode control pin. Selects between pin-strap and I2C mode. For more details, refer to 节8.3.1.
IN_CLKp
IN_CLKn
VCC
18
19
20
I
I
Clock differential positive input
Clock differential negative input
3.3-V power supply
P
I2C Clock/CFG0: when TDP1204 is configured for I2C mode, this pin will function as the I2C
clock. 表8-18 lists how this pin otherwise functions as CFG0.
SCL/CFG0
SDA/CFG1
21
22
I
I2C Data / CFG1: when TDP1204 is configured for I2C mode, this pin will function as the I2C
clock. 表8-19 lists how this pin will otherwise function as CFG1.
I/O
In pin-strap mode, the AC_EN pin selects whether high speed transmitters are externally AC or
DC-coupled.
2-level (PD) 0: DC-coupled
1: AC-coupled
I
AC_EN
23
LV_DDC_SCL
LV_DDC_SDA
HV_DDC_SDA
HV_DDC_SCL
VCC
24
25
26
27
28
I/O
I/O
I/O
I/O
P
Low voltage side bidirectional DDC clock line. Internally pulled-up to VIO.
Low voltage side bidirectional DDC data line. Internally pulled-up to VIO.
High voltage side bidirectional DDC data line. Pull-up externally to HDMI 5-V.
High voltage side bidirectional DDC clock line. Pull-up externally to HDMI 5-V.
3.3-V power supply
TX pre-emphasis control: in pin-strap mode with limited enabled, this pin controls TX EQ. In pin-
strap with linear and AEQ enabled, this pin will adjust the adapted value. 表8-15 lists the
available settings for the TXPRE when operating in pin strap mode. In I2C mode, Tx pre-
emphasis is controlled through the registers.
I
TXPRE
29
4-level
(PU/PD)
OUT_CLKn
OUT_CLKp
30
31
O
O
TMDS data clock differential negative output
TMDS data clock differential positive output
I
HPD_IN
32
Hot plug detect input from sink side. This pin has an internal pull-down resistor and is fail-safe.
2-level (PD)
OUT_D0n
OUT_D0p
33
34
O
O
TMDS data 0 differential negative output
TMDS data 0 differential positive output
Address bit for I2C programming when TDP1204 is configured for I2C mode. 表8-22 lists more
details.
EQ0 pin setting when TDP1204 is configured for pin strap mode; works in conjunction with EQ1;
表8-6 lists the EQ pin settings. In I2C mode, EQ settings are controlled through the registers.
I
ADDR/EQ0
35
4-level
(PU/PD)
OUT_D1n
OUT_D1p
36
37
O
O
TMDS data 1 differential negative output
TMDS data 1 differential positive output
I
TX output swing control: 4 settings. This pin is only used in pin strap mode. 表8-17 lists the
TXSWG
38
4-level
(PU/PD)
available TX swing settings. In I2C mode, Tx output swing is controlled through the registers.
OUT_D2n
OUT_D2p
Thermal Pad
39
40
O
O
TMDS data 2 differential negative output
TMDS data 2 differential positive output
Thermal pad. Connect to a solid ground plane.
—
(1) I = input, O = output, G = ground, and P = power.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
-0.5
MAX
UNIT
Supply Voltage VCC and VIO
4
4
4
4
V
V
V
V
Input Voltage
Differential Inputs (IN_D[2:0], IN_CLK)
-0.3
Output voltage HPD_OUT output
–0.3
–0.3
Output voltage Differential outputs (OUT_D[2:0], OUT_CLK)
LV_DDC_SDA, LV_DDC_SCL, SCL/CFG0, SDA/CFG1, MODE,
CLTEMAP_SEL, HPDOUT_SEL, TXSWG, TXPRE, EQ1, ADDR/
EQ0, EN, AC_EN, LINEAR_EN
4
V
–0.5
–0.5
Control pins
HPD_IN, HV_DDC_SCL, HV_DDC_SDA
TDP1204 Junction temperature
TDP1204I Junction temperature
Storage temperature
6
105
125
150
V
TJ
°C
°C
°C
TJ
Tstg
–65
(1) Operation outside the Absolute Maximum Rating may cause permanent damage to the device. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Condition.
If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±4000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per ANSI/ESDA/
JEDEC JS-002, all pins(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Supply voltage when high-speed RX pins (IN_D[2:0] and IN_CLK) is AC-
coupled to a DP++ TX
VCC
VCC
3.0
3.3
3.6
V
Supply voltage when high-speed RX pins (IN_D[2:0] and IN_CLK) is DC-
coupled to a HDMI TX
3.135
3.3
3.465
V
VIO
VIO supply when 1.2-V LVCMOS level used.
1.14
1.7
3
1.2
1.8
3.3
1.26
1.9
V
V
VIO
VIO supply when 1.8-V LVCMOS level used.
VIO
VIO supply when 3.3-V LVCMOS level used.
3.6
V
VPSN
Peak to peak Power supply noise on VCC pins (less than 4 MHz).
100
mV
DC input voltage for SCL/CFG0, SDA/CFG1, MODE, AC_EN, LINEAR_EN,
EN, CTLEMAP_SEL, TXSWG, TXPRE, EQ1, ADDR1/EQ0, LV_DDC_SCL,
LV_DDC_SDA, HPDOUT_SEL
VCTL3
3.6
V
–0.3
VCTL5
DC input voltage for HV_DDC_SCL, HV_DDC_SDA, HPD_IN pins
Optional external AC-coupling capacitor on IN_Dx and IN_CLK.
5.5
V
–0.3
CACRX
85
253
nF
External AC-coupling capacitor on OUT_Dx and OUT_CLK when AC_EN =
H.
CACTX
TA
85
0
253
70
nF
°C
TDP1204 Ambient temperature
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6.3 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
85
UNIT
TA
TDP1204I Ambient temperature
°C
–40
6.4 Thermal Information
TDP1204
THERMAL METRIC(1)
RNQ (WQFN)
40 PINS
30.9
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
21.2
11.7
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ΨJT
11.7
ΨJB
RθJC(bot)
3.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over recommended voltage and operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
190
215
840
575
220
MAX
265
UNIT
mW
mW
mW
mW
mW
POWER
Pin Strap mode; DR = 3.4 Gbps; HPD_IN
PACTIVE-
Power dissipation in HDMI 1.4 3.4 Gbps = H; No de-emphasis/pre-emphasis;
active operation
H14-LT-
Limited redriver mode; DC-coupled TX;
AC-coupled RX; 3 Gbps CTLE;
ARX-DTX
Pin Strap mode; DR = 6 Gbps; HPD_IN =
H; No de-emphasis/pre-emphasis;
Limited redriver mode; DC-coupled TX;
AC-coupled RX; 6 Gbps CTLE;
PACTIVE-
Power dissipation in HDMI 2.0 6 Gbps
active operation
305
H20-LT-
ARX-DTX
Pin Strap mode; DR = 12 Gbps; HPD_IN
= H; TXFFE0; Limited redriver mode; AC-
coupled TX; AC-coupled RX;12 Gbps
CTLE;
PACTIVE- Power dissipation in FRL 12 Gbps active
operation when TX is AC-coupled
(AC_EN = H)
1220
785
FRL-LT-
ARX-ATX
Pin Strap mode; DR = 12 Gbps; HPD_IN
= H; TXFFE0; Limited redriver mode; DC-
coupled TX; AC-coupled RX; 12 Gbps
CTLE;
PACTIVE- Power dissipation in FRL 12 Gbps active
operation when TX is DC-coupled
(AC_EN = L)
FRL-LT-
ARX-DTX
Pin Strap mode; DR = 12 Gbps; HPD_IN
= H; Highest linearity setting; Linear
redriver mode; DC-coupled TX; AC-
coupled RX; 12 Gbps CTLE;
PACTIVE- Power dissipation in FRL 12 Gbps active
operation when TX is DC-coupled
(AC_EN = L)
310
FRL-LR-
ARX-DTX
Pin Strap mode; DR = 12 Gbps; HPD_IN
= H; Highest linearity setting; Linear
redriver mode; AC-coupled TX; AC-
coupled RX; 12 Gbps CTLE
PACTIVE- Power dissipation in FRL 12 Gbps active
operation when TX is AC-coupled
660
0.6
1.0
990
2
mW
mW
mW
FRL-LR-
(AC_EN = H)
ARX-ATX
Pin Strap mode; HPD_IN = L; EN = L or
H; High-speed outputs are disconnected;
PPD
Power in power-down (HPD_IN = L)
Pin Strap mode; HPD_IN = H; No
incoming signal; EN = H; DC-coupled TX;
incoming signal with DDC Buffer disabled AC-coupled RX; Limited redriver mode;
High-speed outputs are connected;
Power in standby (HPD_IN = H) but no
PSD
1.85
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6.5 Electrical Characteristics (continued)
over recommended voltage and operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Pin Strap mode; HPD_IN = H; No
Power in standby (HPD_IN = H) but no
incoming signal with DDC buffer enabled. AC-coupled RX; Limited redriver mode;
High-speed outputs are connected;
incoming signal; EN = H; DC-coupled TX;
PSD
1.2
2.05
mW
HPD_IN = H;VCC = VIO = 3.6 V;
IVIOQ
IVIOA
VIO quiescent current
LV_DDC_SDA/SCL = H;
HV_DDC_SDA/SCL = H;
16
1
µA
VIO active instantaneous current
VCC = VIO = 3.6 V; HPD_IN = H;
mA
2-LEVEL CONTROL PINS (EN, SCL/CFG0, SDA/CFG1, AC_EN, HPDOUT_SEL)
VIO_TRSH Threshold for selecting between 1.2-V
1.5
2.5
V
V
V
V
V
V
V
V
V
V
LVCMOS / 1.8-V LVCMOS
D
VIO_TRSH Threshold for selecting between 1.8-V
LVCMOS / 3.3-V LVCMOS
D
Low-level input voltage for SCL/CFG0,
SDA/CFG1
VIL_1p2V
VIH_1p2V
VIL_1p8V
VIH_1p8V
VIL_3p3V
VIL_3p3V
VIH_3p3V
VIH_3p3V
VIO = 1.26 V; VCC = 3.0 V;
VIO = 1.14 V; VCC = 3.6 V;
VIO = 1.9 V; VCC = 3.0 V;
VIO = 1.7 V; VCC = 3.6 V;
VIO = 3.6 V; VCC = 3.0 V;
VIO = 3.6 V; VCC = 3.0 V;
VIO = 3.0 V; VCC = 3.6 V;
VIO = 3.0 V; VCC = 3.6 V;
-0.3
0.8
0.378
3.6
High-level input voltage for SCL/CFG0,
SDA/CFG1
Low-level input voltage for SCL/CFG0,
SDA/CFG1
-0.3
1.19
-0.3
-0.3
2.2
0.57
3.6
High-level input voltage for SCL/CFG0,
SDA/CFG1
Low-level input voltage for SCL/CFG0,
SDA/CFG1
0.8
Low-level input voltage for AC_EN,
HPDOUT_SEL
0.8
High-level input voltage for SCL/CFG0,
SDA/CFG1
3.6
High-level input voltage for AC_EN,
HPDOUT_SEL
2.2
3.6
0.3
VOL_1p2V Low-level output voltage SDA/CFG1
IOL_1p2V Low-level output current SDA/CFG1
VCC = 3.0 V; VIO = 1.2 V;
-0.3
2
V
mA
V
VCC = 3.0 V; VIO = 1.2 V;
VOL
IOL
Low-level output voltage SDA/CFG1
Low-level output current SDA/CFG1
VCC = 3.0 V; VIO = 1.8 V or 3.3 V;
VCC = 3.0 V; VIO = 1.8 V or 3.3 V;
-0.3
4
0.4
mA
Low-level input current SCL/CFG0, SDA/
CFG1
IIL_I2C
ILEAK
VIN = 0 V; VIO = 1.8 V or 3.3 V;
VIN = 3.6 V; VCC = 0 V;
1
µA
µA
–1
Fail-safe input current for SCL/CFG0,
SDA/CFG1
25
–25
VIL_EN
VIH_EN
Low-level input voltage for EN pin.
High-level input voltage for EN pin.
VIO = 1.14 V; VCC = 3.3 V;
VIO = 3.6 V; VCC = 3.3 V;
-0.3
0.8
0.4
3.6
V
V
VIN = 0 V; VIO = 1.8 V or 3.3 V; VCC =
3.6 V
IIL
Low-level input current EN
20
1
µA
µA
–20
–1
Low-level input current AC_EN,
HPDOUT_SEL
IIL
VIN = 0 V; VIO = 1.8 V or 3.3 V;
IIH_EN
High-level input current for EN
VIN = 3.6 V; VIO = 1.8 V or 3.3 V;
VIN = 3.6 V; VIO = 1.8 V or 3.3 V;
1
µA
µA
–1
IIH_ACEN High-level input current for AC_EN
IIH_HPDOU High-level input current for
24
–24
VIN = 3.6 V; VIO = 1.8 V or 3.3 V;
30
350
350
µA
kΩ
kΩ
–24
125
125
HPDOUT_SEL
TSEL
RPU_EN
Internal Pull-up resistance on EN.
250
250
RPD_ACE
Internal Pull-down resistance on AC_EN
N
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6.5 Electrical Characteristics (continued)
over recommended voltage and operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RPD_HPD Internal Pull-down resistance on
125
250
350
5
kΩ
HPDOUT_SEL
OUTSEL
Capacitance for SCL/CFG0 and SDA/
CI2C-PINS
CFG1
f = 100 kHz;
pF
pF
pF
Ω
C(I2C_FM+
I2C bus capacitance for FM+ (1 MHz)
150
150
910
2200
_BUS)
C(I2C_FM_
I2C bus capacitance for FM (400 kHz)
BUS)
R(EXT_I2C External resistors on both SDA and SCL
C(I2C_FM+_BUS) = 150 pF
C(I2C_FM_BUS) = 150 pF
620
620
820
when operating at FM+ (1 MHz)
_FM+)
R(EXT_I2C External resistors on both SDA and SCL
1500
Ω
when operating at FM (400 kHz)
_FM)
LV_DDC_SDA and LV_DDC_SCL (DDC Buffer Disabled)
VIL_1p2V Low-level input voltage
VIH_1p2V High-level input voltage
VIL_1p8V Low-level input voltage
VIH_1p8V High-level input voltage
VIL_3p3V Low-level input voltage
VIH_3p3V High-level input voltage
VCC = 3.0 V;
-0.3
0.8
0.378
3.6
V
V
V
V
V
V
VCC = 3.6 V;
VCC = 3.0 V;
VCC = 3.6 V;
VCC = 3.0 V;
VCC = 3.6 V;
-0.3
1.19
-0.3
2.2
0.57
3.6
0.8
3.6
DDC Buffer (LV_DDC_SCL, LV_DDC_SDA, HV_DDC_SCL, HV_DDC_SDA)
High-level input voltage for
HV_DDC_SCL and HV_DDC_SDA
VHV_IH
VHV_IL
VLV_IH
VLV_IH
VLV_IH
VLV_IL
VLV_IL
VLV_IL
IHV_IL_FS
IHV_IL
VIO = 3.3 V; VCC = 3.0 V
VIO = 3.3 V; VCC = 3.0 V
VIO = 1.14 V; VCC = 3.3 V
VIO = 1.7 V; VCC = 3.3 V
VIO = 3.0 V; VCC = 3.3 V
VIO = 1.26 V; VCC = 3.3 V
VIO = 1.9 V; VCC = 3.3 V
VIO = 3.6 V; VCC = 3.3 V
3.3
-0.3
0.8
5.3
1.6
3.6
3.6
3.6
V
V
Low-level input voltage for HV_DDC_SCL
and HV_DDC_SDA
High-level input voltage for LV_DDC_SCL
and LV_DDC_SDA for 1.2-V LVCMOS
V
High-level input voltage for LV_DDC_SCL
and LV_DDC_SDA for 1.8-V LVCMOS
1.15
2.1
V
High-level input voltage for LV_DDC_SCL
and LV_DDC_SDA for 3.3-V LVCMOS
V
Low-level input voltage for LV_DDC_SCL
and LV_DDC_SDA for 1.2-V LVCMOS
0.082 *
VIO
-0.3
-0.3
-0.3
-5
V
Low-level input voltage for LV_DDC_SCL
and LV_DDC_SDA for 1.8-V LVCMOS
0.10 *
VIO
V
Low-level input voltage for LV_DDC_SCL
and LV_DDC_SDA for 3.3-V LVCMOS
0.10 *
VIO
V
Failsafe Input leakage for HV_DDC_SCL
and HV_DDC_SDA
VIN = 5.3 V through 1.5 kΩ; VCC = 0 V;
VIO = 0 V;
5
5
µA
µA
µA
mA
V
Input leakage for HV_DDC_SCL and
HV_DDC_SDA
HV VIN = 5.3 V; LV VIN = VIO;
HV VIN = 5.3 V; LV VIN = VIO;
-5
Input leakage for LV_DDC_SCL and
LV_DDC_SDA
ILV_IL
-5.5
3.5
5.5
VHV_OL = 0.4 V; HDMI5V= 5.3 V; Pullup
with 1.4 kΩ; VCC = 3.0 V;
IHV_OL
VHV_OL
Low-level output current
Low-level output voltage for
HV_DDC_SCL and HV_DDC_SDA
HDMI5V= 5.3 V; Pullup with 1.4 kΩ; VCC
= 3.0 V;
0.4
0.3
Low-level output voltage for
LV_DDC_SCL and LV_DDC_SDA for 1.2- VCC = 3.0 V; VIO = 1.26 V
V LVCMOS
VLV_OL
0.2
V
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6.5 Electrical Characteristics (continued)
over recommended voltage and operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Low-level output voltage for
VLV_OL
LV_DDC_SCL and LV_DDC_SDA for 1.8- VCC = 3.0 V; VIO = 1.9 V
V LVCMOS
0.3
0.4
V
Low-level output voltage for
VLV_OL
LV_DDC_SCL and LV_DDC_SDA for 3.3- VCC = 3.0 V; VIO = 3.6 V
V LVCMOS
0.6
0.75
V
Δ
VLV_HYST Hysteresis on LV side for 3.3 V LVCMOS VIO = 3.3 V; VCC = 3.3 V
50
mV
_3p3V
RPULV
RPUHV
Internal pull-up resistor to VIO
7450
1500
10000
1800
13000
2000
Ω
Ω
External pull-up resistor to HDMI 5 V
Capacitance for HV_DDC_SCL and
HV_DDC_SDA
CIOHV
CIOLV
12
pF
Capacitance for LV_DDC_SCL and
LV_DDC_SDA
7
5.3
pF
V
VHDMI5V HDMI 5V
4.8
Bus capacitance for HV_DDC_SCL and
HV_DDC_SDA
CHV_BUS
750
pF
Bus capacitance for LV_DDC_SCL and
LV_DDC_SDA
CLV_BUS
50
pF
HPD_IN
VIL-HPDIN Low-level input voltage for HPD_IN
VIH-HPDIN High-level input voltage for HPD_IN
VCC = 3.6 V;
VCC = 3.6 V
-0.3
2.0
0.8
5.5
V
V
Device powered; VIH = 5.5 V; Includes
internal pull-down resistor
IH-HPDIN High-level input current for HPD_IN
-50
-1
50
1
µA
µA
kΩ
µA
Device powered; VIL = 0 V; Includes
internal pull-down resistor
IL-HPDIN
Low-level input current for HPD_IN
RPD-
Internal Pull-down resistance on HPD_IN VCC = 3.3 V; HPD_IN = 5.5 V
110
-50
150
210
50
HPDIN
ILEAK-
Fail-safe condition leakage current for
VCC = 0 V; HPD_IN = 5.5 V;
HPD_IN
HPDIN
HPD_OUT
High level output voltage when configured
VCC = 3.0 V;
VOH_3p3V
2.4
1.3
3.465
1.95
0.4
V
V
for 3.3 V LVCMOS push/pull.
High level output voltage when configured
VCC = 3.0 V;
VOH_1p8V
for 1.8 V LVCMOS push/pull.
Low level output voltage when configured
VCC = 3.0 V;
VOL_PP
-0.3
-0.3
V
for push/pull.
Low level output voltage when configured
VCC = 3.0 V; 0.5 kΩ to 3.6 V load;
for open drain.
VOL_OD
IOH_3p3V
IOL_3p3V
IOH_1p8V
IOL_1p8V
0.4
V
High level output current for 3.3-V
LVCMOS
HPD_IN = VIH-HPDIN
HPD_IN = VIL-HPDIN; I2C mode;
HPD_IN = VIH-HPDIN
HPD_IN = VIL-HPDIN; I2C mode;
;
-4
mA
mA
mA
mA
Low level output current for 3.3-V
LVCMOS
4
High level output current for 1.8-V
LVCMOS
;
-1.1
Low level output current for 1.8-V
LVCMOS
1.2
4-LEVEL CONTROL (MODE, LINEAR_EN, EQ1, ADDR/EQ0, TXSLEW, TXPRE, TXSWG)
VTH
VTH
Threshold "0" / "R"
Threshold "R" / "F"
VCC = 3.3 V
VCC = 3.3 V
0.55
1.65
V
V
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6.5 Electrical Characteristics (continued)
over recommended voltage and operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VTH
IIH
Threshold "F" / "1"
VCC = 3.3 V
2.7
High-level input current
Low-level input current
Internal pullup resistance
Internal pull-down resistance
VIH = 3.6 V; VCC = 3.6 V;
VIL = 0 V; VCC = 3.6 V;
20
60
µA
IIL
-40
µA
–100
R4PU
R4PD
48
98
kΩ
kΩ
HDMI HIGH SPEED INPUTS
DR_RX_DA
Data lanes data rate
0.25
0.25
12 Gbps
12 Gbps
TA
DR_RX_CL
Clock lane data rate
K
VID(DC)
DC differential input swing
At pins; LINEAR_EN = L;
At pins;
400
75
1200 mVpp
mVpp
VID(EYE) Differential input swing eye opening
VRX_ASSE
Signal detect assert level.
PRBS7 pattern; 12 Gbps;
180
mVpp
mVpp
RT
VRX_DEAS
Signal detect deassert level.
PRBS7 pattern; 12 Gbps;
At pins;
110
3.3
SERT
VICM-DC Input DC common mode voltage bias
2.5
VCC
V
At 6 GHz; 12 Gbps CTLE; EQ15; DC
Gain = 0 dB; Limited Mode; At output of
RX;
EEQ_12Gb
Maximum Fixed EQ gain (AC - DC)
12
1.0
dB
s_MAX_LT
EEQ_12Gb
At 6 GHz; 12 Gbps CTLE; EQ0; DC Gain
= 0 dB; Limited Mode; At output of RX;
Minimum Fixed EQ gain (AC - DC)
dB
dB
ps_MIN_LT
EEQ_12Gb
Maximum Fixed EQ Gain when EQ is
bypassed. (AC - DC)
At 6 GHz; 12 Gbps CTLE; DC Gain = 0
dB; Limited Mode; At output of RX;
-1.5
ps_BYPASS
_LT
EEQ_6Gbs
At 3 GHz; 6 Gbps CTLE; EQ15; DC Gain
= 0 dB; Limited Mode; At output of RX;
Maximum Fixed EQ gain (AC - DC)
12.0
0.6
dB
dB
_MAX_LT
EEQ_6Gbp
At 3 GHz; 6 Gbps CTLE; EQ0; DC Gain =
0 dB; Limited Mode; At output of RX;
Minimum Fixed EQ gain (AC - DC)
s_MIN_LT
At 1.5 GHz; 3 Gbps CTLE; EQ15; DC
Gain = 0 dB; Limited Mode; At output of
RX;
EEQ_3Gbs
Maximum Fixed EQ gain (AC - DC)
12
dB
_MAX_LT
EEQ_3Gbp
At 1.5 GHz; 3 Gbps CTLE; EQ0; DC Gain
= 0 dB; Limited Mode; At output of RX;
Minimum Fixed EQ gain (AC - DC)
0.8
100
100
dB
Ω
Ω
s_MIN_LT
Input differential impedance when
termination is enabled
RINT
90
85
110
115
At TTP2; HPD_IN = H; 0℃≤TA ≤70℃
Input differential impedance when
termination is enabled
At TTP2; HPD_IN = H; –20℃≤TA ≤
85℃
RINT
HDMI HIGH SPEED OUTPUTS (Limited Mode)
DR = 270 Mbps; HPD_IN = H; AC_EN =
L (DC-coupled); TXSWG = "F" (1000
mV); TXPRE = "F" (0dB); TX termination
open; VCC_EXT = 3.3 V; 25℃ ≤TA ≤
85℃;
Single-ended low-level output voltage for
VOL_open
2.7
2.6
2.9
2.9
V
V
DR ≤1.65 Gbps data rate
DR = 3.4 Gbps; HPD_IN = H; AC_EN = L
(DC-coupled); TXSWG = "F" (1000 mV);
TXPRE = "F" (0 dB); TX termination 300-
ohms; VCC_EXT = 3.3 V; 25℃ ≤TA ≤
85℃;
Single-ended low-level output voltage
VOL_300
1.65 Gbps < DR ≤3.4 Gbps.
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6.5 Electrical Characteristics (continued)
over recommended voltage and operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DR = 5.94 Gbps; HPD_IN = H; AC_EN =
L (DC-coupled); TXSWG = "F" (1000
mV); TXPRE = "F" (0 dB); VCC_EXT =
3.3 V; 25℃ ≤TA ≤85℃;
Data lane single-ended low-level output
voltage 3.4 Gbps < DR ≤6 Gbps.
VOL_DAT2
2.3
2.9
V
0
DR = 1.5 Gbps; HPD_IN = H; AC_EN = L
(DC-coupled); TXSWG = "F" (1000 mV);
TXPRE = "F" (0 dB); VCC_EXT = 3.3
V; 25℃ ≤TA ≤85℃;
VSWING_D Single-ended output voltage swing on
400
400
400
400
300
500
500
500
500
400
600
600
600
600
600
mV
mV
mV
mV
mV
data lanes with TX term set to open.
A_14
DR = 3.4 Gbps;HPD_IN = H; AC_EN = L
(DC-coupled); TXSWG = "F" (1000 mV);
TXPRE = "F" (0 dB); VCC_EXT = 3.3
V; 25℃ ≤TA ≤85℃;
VSWING_D Single-ended output voltage swing on
data lanes with TX term set to 300-ohms.
A_14
DR = 5.94 Gbps;HPD_IN = H; AC_EN = L
(DC-coupled); TXSWG = "F" (1000 mV);
TXPRE = "F" (0 dB); VCC_EXT = 3.3
V; 25℃ ≤TA ≤85℃;
VSWING_D Single-ended output voltage swing on
data lanes for HDMI2.0 operation.
A_20
HPD_IN = H; AC_EN = L (DC-coupled);
TXSWG = "F" (1000 mV); TXPRE = "F" (0
dB); VCC_EXT = 3.3 V; 25℃ ≤TA ≤
85℃; TERM set to open;
VSWING_C
Single-ended output voltage swing on
clock lane for DR ≤3.4 Gbps datarate
LK_14_OPE
N
HPD_IN = H; AC_EN = L (DC-coupled);
TXSWG = "F" (1000 mV); TXPRE = "F" (0
dB); VCC_EXT = 3.3 V; 25℃ ≤TA ≤
85℃;
VSWING_C Single-ended output voltage swing on
clock lane for HDMI 2.0
LK_20
At TTP4; AC_EN = L or H; LTP5, 6, 7 or
8; TXFFE0; 25℃ ≤TA ≤85℃;
VOCM-DC- FRL DC common mode voltage when
2.335
2.335
3.495
3.495
V
V
actively transmitting
ON
At TTP4; FRL 3 lane mode; AC_EN = L
or H; 25℃ ≤TA ≤85℃;
VOCM-DC- FRL DC common mode voltage when
lane 3 is disabled
OFF
At TTP4; 2.97 Gbps; HPD_IN = H;
AC_EN = L or H; TXSWG = "F" (1000
mV); TXPRE = "F" (0 dB); 25℃ ≤TA ≤
85℃;
VOD_3G
Data lanes Differential output swing
Data lanes Differential output swing
400
1560
mV
At TTP4_EQ; 5.94 Gbps; HPD_IN = H;
AC_EN = L or H; TXSWG = "F" (1000
mV); TXPRE = "F" (0 dB); 25℃ ≤TA ≤
85℃;
VOD_6G
150
100
1560
1560
mV
mV
At TTP4_EQ; 12 Gbps; HPD_IN = H;
AC_EN = L or H; TXSWG = "F" (1000
mV); TXFFE0; 25℃ ≤TA ≤85℃;
VOD_12G_ Data lanes Differential output swing at 12
G FRL.
FRL
VCC = 0 V; DC-coupled; TMDS output
pulled to 3.465 V with 50 Ω resistors
ILEAK
IOS
Failsafe condition leakage current
Short circuit current limit
35
70
µA
OUT_CLK, OUT_D[2:0] outputs P or N
shorted to GND
mA
TERM = 1h; AC_EN = L (DC-
coupled);HPD_IN=H; Active state; –20℃
≤TA ≤85℃;
Internal termination for DR ≤3.4 Gbps
when DC-coupled
RTERM14
RTERM14
RTERM2+
RTERM2+
235
235
85
295
295
100
100
375
375
115
115
Ω
Ω
Ω
Ω
TERM = 1h; AC_EN = H (AC-
coupled); HPD_IN=H; Active state; –
20℃≤TA ≤85℃;
Internal termination for DR ≤3.4 Gbps
when AC-coupled
TERM = 3h; AC_EN = L (DC-coupled);
HPD_IN=H; Active state; –20℃≤TA ≤
85℃;
Internal termination for DR > 3.4 Gbps
when DC-coupled.
TERM = 3h; AC_EN = H (AC-
coupled); HPD_IN=H; Active state; –
20℃≤TA ≤85℃;
Internal termination for DR > 3.4 Gbps
when AC-coupled.
85
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6.5 Electrical Characteristics (continued)
over recommended voltage and operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TERM = 3h; HPD_IN = H; TX_AC_EN =
0; CLK_TXFFE = 0h; CLK_VOD = 3h;
VTXPRE0- Transmitter FFE pre-emphasis ratio for 0 D0_TXFFE = 0h; D0_VOD = 3h;
0
dB
dB.
D1_TXFFE = 0h; D1_VOD = 3h;
RATIO
D2_TXFFE = 0h; D2_VOD = 3h; 20 * log
(Vp/Vn); 128 zeros followed by 128 ones;
At 5.94 Gbps HDMI 2.0; TERM = 3h;
HPD_IN = H; TX_AC_EN = 0;
CLK_TXFFE = 0h; CLK_VOD = 3h;
D0_TXFFE = 1h; D0_VOD = 3h;
D1_TXFFE = 1h; D1_VOD = 3h;
D2_TXFFE = 1h; D2_VOD = 3h; 20 * log
(Vp/Vn); 128 zeros followed by 128 ones;
VTXPRE1- Transmitter FFE pre-emphasis ratio for
4.0
6.5
dB
dB
dB
dB
dB
dB
3.5 dB for data lanes
RATIO
At 5.94 Gbps HDMI 2.0; TERM = 3h;
HPD_IN = H; TX_AC_EN = 0;
CLK_TXFFE = 0h; CLK_VOD = 3h;
D0_TXFFE = 2h; D0_VOD = 3h;
D1_TXFFE = 2h; D1_VOD = 3h;
D2_TXFFE = 2h; D2_VOD = 3h; 20 * log
(Vp/Vn); 128 zeros followed by 128 ones;
VTXPRE2- Transmitter FFE pre-emphasis ratio for 6
dB for data lanes
RATIO
At 12 Gbps FRL; TERM = 3h; HPD_IN =
H; TX_AC_EN = 0; CLK_TXFFE = 4h;
CLK_VOD = 3h; D0_TXFFE = 4h;
D0_VOD = 3h; D1_TXFFE = 4h; D1_VOD
= 3h; D2_TXFFE = 4h; D2_VOD = 3h; 20
* log (Vp/Vn); 128 zeros followed by 128
ones;
VTXFFE0- Transmitter FRL TXFFE0 de-emphasis
-2.5
-3.2
-3.5
-4.5
ratio
RATIO
At 12 Gbps FRL; TERM = 3h; HPD_IN =
H; TX_AC_EN = 0; CLK_TXFFE = 5h;
CLK_VOD = 3h; D0_TXFFE = 5h;
D0_VOD = 3h; D1_TXFFE = 5h; D1_VOD
= 3h; D2_TXFFE = 5h; D2_VOD = 3h; 20
* log (Vp/Vn); 128 zeros followed by 128
ones;
VTXFFE1- Transmitter FRL TXFFE1 de-emphasis
ratio
RATIO
At 12 Gbps FRL; TERM = 3h; HPD_IN =
H; TX_AC_EN = 0; CLK_TXFFE = 6h;
CLK_VOD = 3h; D0_TXFFE = 6h;
D0_VOD = 3h; D1_TXFFE = 6h; D1_VOD
= 3h; D2_TXFFE = 6h; D2_VOD = 3h; 20
* log (Vp/Vn); 128 zeros followed by 128
ones;
VTXFFE2- Transmitter FRL TXFFE2 de-emphasis
ratio.
RATIO
At 12 Gbps FRL; TERM = 3h; HPD_IN =
H; TX_AC_EN = 0; CLK_TXFFE = 7h;
CLK_VOD = 3h; D0_TXFFE = 7h;
D0_VOD = 3h; D1_TXFFE = 7h; D1_VOD
= 3h; D2_TXFFE = 7h; D2_VOD = 3h; 20
* log (Vp/Vn); 128 zeros followed by 128
ones;
VTXFFE3- Transmitter FRL TXFFE3 de-emphasis
ratio
RATIO
HDMI HIGH SPEED OUTPUTS (Linear Mode)
At 10 MHz; 200 mVpp < VID < 1200
mVpp; EQ0; DCGAIN = 0 dB; 12Gbps
CTLE; CTLEBYP_EN = 0; BERT TX 100
MHz clock starting at 200 mV to 1200
mV in 50 mV steps;TX DC coupled to
VCC_EXT;
CPLF-
Low-frequency 1-dB compression point
Dx_VOD = 0.
900
750
mVpp
mVpp
TXSWG-0
At 6 GHz; 200 mVpp < VID < 1200 mVpp;
EQ0; DCGAIN = 0 dB; 12 Gbps CTLE;
CTLEBYP_EN = 0; TX DC coupled to
VCC_EXT;
CPHF-
High-frequency 1-dB compression point
Dx_VOD = 0.
TXSWG-0
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6.5 Electrical Characteristics (continued)
over recommended voltage and operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
At 10 MHz; 200 mVpp < VID < 1200
mVpp; EQ0; DCGAIN = 0 dB; 12 Gbps
CTLE; CTLEBYP_EN = 0; BERT TX 100
MHz clock starting at 200 mV to 1200
mV in 50 mV steps; TX DC coupled to
VCC_EXT;
CPLF-
Low-frequency 1-dB compression point
Dx_VOD = 1.
1000
mVpp
TXSWG-R
At 6 GHz; 200 mVpp < VID < 1200 mVpp;
EQ0; DCGAIN = 0 dB; 12Gbps CTLE;
CTLEBYP_EN = 0;TX DC coupled to
VCC_EXT;
CPHF-
High-frequency 1-dB compression point
Dx_VOD = 1.
800
1100
875
mVpp
mVpp
mVpp
mVpp
mVpp
TXSWG-R
At 10 MHz; 200 mVpp < VID < 1200
mVpp; EQ0; DCGAIN = 0 dB; 12 Gbps
CTLE; CTLEBYP_EN = 0; BERT TX 100
MHz clock starting at 200 mV to 1200
mV in 50 mV steps; TX DC coupled to
VCC_EXT;
CPLF-
Low-frequency 1-dB compression point
Dx_VOD = 2.
TXSWG-F
At 6 GHz; 200 mVpp < VID < 1200 mVpp;
EQ0; DCGAIN = 0 dB; 12 Gbps CTLE;
CTLEBYP_EN = 0; TX DC coupled to
VCC_EXT;
CPHF-
High-frequency 1-dB compression point
Dx_VOD = 2.
TXSWG-F
At 10 MHz; 200 mVpp < VID < 1200
mVpp; EQ0; DCGAIN = 0 dB; 12 Gbps
CTLE; CTLEBYP_EN = 0; BERT TX 100
MHz clock starting at 200 mV to 1200
mV in 50 mV steps; TX DC coupled to
VCC_EXT;
CPLF-
Low-frequency 1-dB compression point
Dx_VOD = 3.
1200
950
TXSWG-1
At 6 GHz; 200 mVpp < VID < 1200 mVpp;
EQ0; DCGAIN = 0 dB; 12 Gbps CTLE;
CTLEBYP_EN = 0; TX DC coupled to
VCC_EXT;
CPHF-
High-frequency 1-dB compression point
Dx_VOD = 3.
TXSWG-1
6.6 Timing Requirements
MIN
NOM
MAX
UNIT
Local I2C (SCL/CFG0, SDA/CFG1). Refer to 图7-9.
fSCL
tBUF
I2C clock frequency
1
MHz
µs
Bus free time between START and STOP conditions
0.5
Hold time after repeated START condition. After this period, the first clock
pulse is generated
tHD_STA
0.26
µs
tLOW
Low period of the I2C clock
High period of the I2C clock
Setup time for a repeated START condition
Data hold time
0.5
0.26
0.26
0
µs
µs
tHIGH
tSU_STA
tHD_DAT
tSU_DAT
tR
µs
μs
ns
Data setup time
50
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Setup time for STOP condition
120
120
ns
tF
4
ns
tSU_STO
0.26
μs
DDC Snoop I2C Timings. Refer to 图7-9.
fSCL
tBUF
I2C DDC clock frequency
100
kHz
µs
Bus free time between START and STOP conditions
4.7
4
Hold time after repeated START condition. After this period, the first clock
pulse is generated
tHD_STA
tLOW
µs
µs
Low period of the I2C clock
4.7
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6.6 Timing Requirements (continued)
MIN
4
NOM
MAX
UNIT
µs
tHIGH
tSU_STA
tHD_DAT
tSUDAT
tR
High period of the I2C clock
Setup time for a repeated START condition
Data hold time
4.7
0
µs
μs
ns
Data setup time
250
Rise time of both SDA and SCL signals. Measured from 30% to 70%.
Fall time of both SDA and SCL signals Measured from 70% to 30%.
Setup time for STOP condition
1000
300
ns
tF
ns
tSU_STO
Cb_LV
4
μs
pF
Capacitive load for each bus line on LV side
50
Power-On. Refer to 图7-1.
tVCC_RAMP VCC supply ramp. Measured from 10% to 90%.
0.10
50
5
ms
ms
µs
µs
µs
tD_PG
Internal POR de-assertion delay
tVIO_SU
tCFG_SU
tCFG_HD
VIO supply stable before reset(2) high.
Configuration pins(1) setup before reset(2) high.
Configuration pins(1) hold after reset(2)high.
100
0
500
(1) Follow comprise the configuration pins: MODE, ADDR/EQ0, EQ1, TXSWG, TXSLEW, TXPRE, AC_EN, HPDOUT_SEL, DCGAIN
(2) Reset is the logical AND of internal POR and EN pin.
6.7 Switching Characteristics
over recommended voltage and operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Redriver
Maximum HDMI 1.4 clock frequency at
which TX termination is assured to be
open
HDMI1.4; 25 MHz ≤IN_CLK ≤340
MHz; TXTERM_AUTO_HDMI14 = 0h;
TERM = 2h; TX is DC-coupled;
fHDMI14_o
165
MHz
pen
Minimum HDMI 1.4 clock frequency at
which TX termination is assured to be
300-ohms
HDMI1.4; 25 MHz ≤IN_CLK ≤340
MHz; TXTERM_AUTO_HDMI14 = 0h;
TERM = 2h; TX is DC-coupled;
fHDMI14_3
250
0.7
MHz
ms
00
tAEQ_DON Time from start of FRL link training to
AEQ complete for 3 Gbps.
E
Time from start of FRL link training to
tAEQ_DON
AEQ complete for 6 Gbps, 8 Gbps, 10
0.5
220
ms
ps
UI
E
Gbps, and 12 Gbps
tPD
Propagation delay time
At TTP4;
90
At TTP4; With 0.15 UI skew at input; At
12 Gbps; LTP5, 6, 7, or 8; TXFFE0; TX
termination 100-Ω; Linear mode;
Data lane Intra-pair output skew with
worse case skew at inputs
tSK1(T)
0.15
At TTP4; No intra-pair skew at input; 6
Gbps with 150 MHz clock; TX termination
100-Ω; Limited mode;
Clock lane Intra-pair output skew with
zero intra-pair skew at inputs
tSK1(T)
0.10
0.15
0.11
UI
UI
At TTP4; No intra-pair skew at input; At
12 Gbps; LTP5, 6, 7, or 8; TXFFE0; TX
termination 100-Ω; Limited mode;
Data lane Intra-pair output skew with zero
intra-pair skew at inputs
tSK1(T)
0.053
At TTP4; At 12 Gbps; LTP5, 6, 7, or 8;
TXFFE0;
tSK2(T)
Inter-pair output skew
30
600
600
ps
ps
ps
Transition time (rise and fall time) for
clock lane when operating at HDMI1.4
At TTP4; 20% to 80%; Clock Frequency =
300 MHz;
tRF-CLK-14
75
75
Transition time (rise and fall time) for
clock lane when operating at HDMI 2.0
At TTP4; 20% to 80%; Clock Frequency =
150 MHz;
tRF-CLK-20
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6.7 Switching Characteristics (continued)
over recommended voltage and operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
At TTP4; 20% to 80%; DR = 3 Gbps;
SLEW_HDMI14 = default; PRBS7
pattern; Clock Frequency = 300 MHz;
Transition time (rise and fall time) for data
lanes when operating at HDMI 1.4
tRF_14
75
195
ps
At TTP4; 20% to 80%; DR = 6 Gbps;
SLEW_HDMI20 = default; PRBS7
pattern; Clock Frequency = 150 MHz;
Transition time (rise and fall time) for data
lanes when operating at HDMI 2.0
tRFDAT_20
42.5
115
ps
At TTP4; Slope at 50% level; All FRL DR
up to 12 Gbps; SLEW_HDMI21 = Default;
clock pattern of 128 zeros and 128 ones;
Single-ended TX slew rate for data lanes
when operating at HDMI 2.1 FRL
tSLEW_FRL
16 mV/ps
Transistion bit duration when de-
emphasis/pre-emphasis is enabled
At TTP4; DR = 3 Gbps; Clock pattern of
128 zeros followed by 128 ones;
tTRANS_3G
tTRANS_6G
tTRANS_8G
0.4
0.4
0.4
0.5
0.6
1
1
UI
UI
UI
UI
UI
Transistion bit duration when de-
emphasis/pre-emphasis is enabled
At TTP4; DR = 6 Gbps; Clock pattern of
128 zeros followed by 128 ones;
Transistion bit duration when de-
emphasis/pre-emphasis is enabled
At TTP4; DR = 8 Gbps; Clock pattern of
128 zeros followed by 128 ones;
1
tTRANS_10 Transistion bit duration when de-
At TTP4; DR = 10 Gbps; Clock pattern of
128 zeros followed by 128 ones;
1.1
1.3
emphasis/pre-emphasis is enabled
G
tTRANS_12 Transistion bit duration when de-
At TTP4; DR = 12 Gbps; Clock pattern of
128 zeros followed by 128 ones;
emphasis/pre-emphasis is enabled
G
HPD
tHPD_PD HPD_IN to HPD_OUT propagation delay
100
4
µs
Refer to 图7-7
Refer to 图7-7
HPD_IN debounce time before declaring
tHPD_PWR
Powerdown. Enter Powerdown if
HPD_IN is low after debounce time.
2
2
ms
DOWN
HPD_IN debounce time required for
tHPD_STAN exiting Powerdown to Standby. Exit
4
ms
Refer to 图7-8
Powerdown if HPD_IN is high after
DBY
debounce time.
Standby
tSTANDBY_ Detection of electrical idle to entry into
HPD_IN = H;
HPD_IN = H;
300
25
µs
µs
Standby.
ENTRY
Maximum differential signal glitch time
tSIGDET_D
rejected during debounce before
transitioning from standby to active
B
Maximum differential signal glitch time
tSIGDET_D
rejected during debounce before
HPD_IN = H;
50
ns
µs
B
transitioning from active to standby
tSTANDBY_ Detection of differential signal to exit from HPD_IN = H; Does not include AEQ time
200
Standby to Active state
if AEQ_TX_DELAY_EN = 1;
EXIT
DDC Buffer
fSCL
DDC buffer frequency
100
kHz
ns
Propagation delay time. Low-to-high-level LV to HV; CLV_BUS = CHV_BUS = 50 pF;
output. VIO set to 1.2 V LVCMOS levels. DDC_LV_DCC_EN = 1'b1;
1400
Propagation delay time. Low-to-high-level LV to HV; CLV_BUS = CHV_BUS = 50 pF;
output. VIO set to 1.8 V LVCMOS levels. DDC_LV_DCC_EN = 1'b1;
tPLH1
1400
1400
410
ns
ns
ns
ns
ns
Propagation delay time. Low-to-high-level LV to HV; CLV_BUS = CHV_BUS = 50 pF;
output. VIO set to 3.3 V LVCMOS levels. DDC_LV_DCC_EN = 1'b1;
Propagation delay time. Low-to-high-level HV to LV; CLV_BUS = CHV_BUS = 50 pF;
output. VIO set to 1.2 V LVCMOS levels. DDC_LV_DCC_EN = 1'b1;
Propagation delay time. Low-to-high-level HV to LV; CLV_BUS = CHV_BUS = 50 pF;
output. VIO set to 1.8 V LVCMOS levels. DDC_LV_DCC_EN = 1'b1;
tPLH2
410
Propagation delay time. Low-to-high-level HV to LV; CLV_BUS = CHV_BUS = 50 pF;
output. VIO set to 3.3 V LVCMOS levels. DDC_LV_DCC_EN = 1'b1;
410
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6.7 Switching Characteristics (continued)
over recommended voltage and operating free-air temperature range (unless otherwise noted)
PARAMETER
Propagation delay time. High to low-level LV to HV; CLV_BUS = CHV_BUS = 50 pF;
output. VIO set to 1.2 V LVCMOS. DDC_LV_DCC_EN = 1'b1;
Propagation delay time. High to low-level LV to HV; CLV_BUS = CHV_BUS = 50 pF;
output. VIO set to 1.8 V LVCMOS. DDC_LV_DCC_EN = 1'b1;
Propagation delay time. High to low-level LV to HV; CLV_BUS = CHV_BUS = 50 pF;
output. VIO set to 3.3 V LVCMOS. DDC_LV_DCC_EN = 1'b1;
Propagation delay time. High to low-level HV to LV; CLV_BUS = CHV_BUS = 50 pF;
output. VIO set to 1.2 V LVCMOS. DDC_LV_DCC_EN = 1'b1;
Propagation delay time. High to low-level HV to LV; CLV_BUS = CHV_BUS = 50 pF;
output. VIO set to 1.8 V LVCMOS. DDC_LV_DCC_EN = 1'b1;
Propagation delay time. High to low-level HV to LV; CLV_BUS = CHV_BUS = 50 pF;
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1200
1200
1200
535
ns
tPHL1
ns
ns
ns
ns
ns
tPHL2
535
535
output. VIO set to 3.3 V LVCMOS.
DDC_LV_DCC_EN = 1'b1;
LV side fall time for 1.2-V LVCMOS
70% to 30%; CLV_BUS = CHV_BUS = 50 pF;
70% to 30%; CLV_BUS = CHV_BUS = 50 pF;
70% to 30%; CLV_BUS = CHV_BUS = 50 pF;
70% to 30%; CLV_BUS = CHV_BUS = 50 pF;
30% to 70%; CLV_BUS = CHV_BUS = 50 pF;
75
75
75
75
260
260
260
260
ns
ns
ns
ns
tLV_FALL LV side fall time for 1.8-V LVCMOS
LV side fall time for 3.3-V LVCMOS
tHV_FALL HV side fall time
LV side rise time for 1.2-V LVCMOS
tLV_RISE LV side rise time for 1.8-V LVCMOS
LV side rise time for 3.3-V LVCMOS
300
300
300
670
670
670
ns
ns
ns
Pulled up to VIO using RPULV
30% to 70%; CLV_BUS = CHV_BUS = 50 pF;
Pulled up to VIO using RPULV
30% to 70%; CLV_BUS = CHV_BUS = 50 pF;
Pulled up to VIO using RPULV
;
;
;
30% to 70%; CLV_BUS = CHV_BUS = 50 pF;
VCC = 3.0 V; HDMI5V = 5.3V; Pulled up
tHV_RISE_
HV side rise time (50 pF load)
225
ns
ns
50pF
to HDMI5V using RPUHV
;
30% to 70%; CLV_BUS = 50 pF; CHV_BUS
750 pF; VCC = 3.0 V; HDMI5V = 5.3 V;
=
tHV_RISE_
HV side rise time (750 pF load)
1250
750pF
Pulled up to HDMI5V using RPUHV
;
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6.8 Typical Characteristics
图6-1. 3 Gbps CTLE EQ Curves with
图6-2. 6 Gbps CTLE EQ Curves with
GLOBAL_DCG = 0x2 in Limited Mode
GLOBAL_DCG = 0x2 in Limited Mode
图6-4. Input Differential Return Loss (SDD11)
图6-3. 12 Gbps CTLE EQ Curves with
GLOBAL_DCG =0x2 in Limited Mode
图6-5. Output Differential Return Loss (SDD22)
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7 Parameter Measurement Information
VIO(min)
VIO
tVIO_SU
2.8 V
tD_PG
VCC
Internal POR
tCFG_SU
Reset
(POR && EN pin)
VIH
EN pin
tCFG_HD
CFG pins
图7-1. Power-On Timing Requirements
VCC
3.3 V
50
50
50
50
0.5 pF
D+
D-
Y
Z
Receiver
Driver
VID
VD+
VY
VID = VD+ - VD-
VOD = VY - VZ
VD-
VZ
VICM = (VD+ + VD-)
2
VOCM = (VY + VZ)
2
图7-2. TMDS Main Link Test Circuit
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4.0 V
2.6 V
Vcc
VID+
VID
VID(pp)
0 V
VID-
tPHL
tPLH
80%
80%
VOD(pp)
VOD
0 V
20%
20%
tr
tf
图7-3. Input or Output Timing Measurements
VOD(SS)
PRE = L
图7-4. Output Differential Waveform
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TXPRE = —F“
TXPRE = —0“ or —1“
VOD(PP)
VOD(SS)
图7-5. Output Differential Waveform with De-Emphasis
Avcc(4)
RT
(5)
RT
SMA
SMA
SMA
REF
Cable
EQ
Coax
Coax
Coax
Coax
Data +
RX
+EQ
OUT
SMA
Data -
Parallel (6)
BERT
Jitter Test
Instrument (2,3)
FR4 PCB trace(1)
AC coupling Caps
&
Device
FR4 PCB trace
AVcc
RT
[No Pre-
emphasis]
RT
REF
Cable
EQ
SMA
SMA
SMA
SMA
Coax
Coax
Coax
Coax
Clk+
Clk-
RX
+EQ
OUT
Jitter Test
Instrument (2,3)
TTP4_EQ
Copyright © 2016, Texas Instruments Incorporated
TTP4
TTP1
TTP2
TTP3
TTP2_EQ
(1) The FR4 trace between TTP1 and TTP2 is designed to emulate 1-12”of FR4, AC-coupling cap, connector and another 2”of FR4.
Trace width –4 mils. 100 Ωdifferential impedance.
(2) All Jitter is measured at a BER of 109. HDMI 2.1 jitter measured at BER 10-10
.
(3) Residual jitter reflects the total jitter measured at TTP4 minus the jitter measured at TTP
(4) AVCC = 3.3 V.
(5) RT = 50 Ω.
(6) For HDMI 1.4 or 2.0, the input signal from parallel Bert does not have any pre-emphasis or de-emphasis. For HDMI 2.1 FRL, the
input signal from BERT will have 2.18 dB pre-shoot and -3.1 dB de-emphasis. Refer to Recommended Operating Conditions.
图7-6. HDMI Output Jitter Measurement
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HPD_IN
VIL
tHPD_PWRDOWN
tHPD_PD
HPD_OUT
VOL
Device Active or Standby
Power Down
图7-7. HPD Logic Shutdown and Propagation Timing
VIH
HPD_IN
tHPD_STANDBY
tHPD_PD
VOH
HPD_OUT
Standby
Device In Power Down
图7-8. HPD Logic Standby and Propagation Timing
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t
t
r
t
SU_DAT
f
70 %
70 %
30 %
SDA
30 %
cont.
t
t
HD_DAT
VD_DAT
t
f
t
HIGH
t
r
70 %
30 %
70 %
30 %
70 %
30 %
70 %
30 %
SCL
cont.
t
HD_STA
t
LOW
th
9
clock
1 / f
S
SCL
st
1
clock cycle
t
BUF
SDA
SCL
t
VD_ACK
t
t
t
t
SU_STO
SU_STA
HD_STA
SP
70 %
30 %
Sr
P
S
th
9
clock
图7-9. I2C SCL and SDA Timing
LV_DDC_SCL/SDA
INPUT
0.7 VIO
0.3 VIO
tPLH1
tPHL1
HV_DDC_SCL/SDA
OUTPUT
0.7 HDMI5V
0.3 HDMI5V
tf
tr
图7-10. DDC Propagation Delay –Source to Sink
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HV_DDC_SCL/SDA
INPUT
0.7 HDMI5V
0.3 HDMI5V
tPLH2
tPHL2
LV_DDC_SCL/SDA
OUTPUT
0.7 VIO
0.3 VIO
tf
tr
图7-11. DDC Propagation Delay –Sink to Source
VID(DC)
VID(EYE)
图7-12. VID(DC) and VID(EYE)
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8 Detailed Description
8.1 Functional Block Diagram
SigDet
OUT_D2p
OUT_D2n
IN_D2p
Driver
Driver
EQ
IN_D2n
OUT_D1p
OUT_D1n
IN_D1p
EQ
IN_D1n
OUT_D0p
IN_D0p
Driver
EQ
OUT_D0n
OUT_CLKp
IN_D0n
IN_CLKp
Driver
EQ
OUT_CLKn
IN_CLKn
SigDet
VIO
SCL/CFG0
SDA/CFG1
ADDR/EQ0
EN
I2C
Target
CTLEMAP_SEL
TXPRE
TXSWG
EQ1
TEST1
HPD_IN
MODE
AC_EN
HPD_OUT
DDC
Snoop
LINEAR_EN
HPDOUT_SEL
VIO
RPULV
DDC
Buffer
HV_DDC_SDA
HV_DDC_SCL
LV_DDC_SDA
LV_DDC_SCL
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8.2 Feature Description
8.2.1 4-Level Inputs
The TDP1204 has 4-level inputs pins that control the receiver equalization gain, transmitter voltage swing, and
pre-emphasis, and place TDP1204 into different modes of operation. These 4-level inputs utilize a resistor
divider to help set the 4 valid levels and provide a wider range of control settings. There are internal pull-up and
a pull-down resistors. These resistors are combined with the external resistor connection to achieve the desired
voltage level.
表8-1. 4-Level Control Pin Settings
LEVEL
SETTINGS
0
R
F
1
Tie 1-kΩ 5% to GND.
Tie 20-kΩ 5% to GND.
Float (leave pin open)
Tie 1-kΩ 5% to VCC
.
备注
图7-1 shows how all 4-level inputs are latched after the rising edge of the EN pin. After these pins are
sampled, the internal pull-up and pull-down resistors will be isolated to save power.
8.2.2 I/O Voltage Level Selection
The TDP1204 supports 1.2-V, 1.8-V, and 3.3-V LVCMOS levels. The VIO pin is used to select which voltage
level is used for the following 2-level control pins: LV_DDC_SDA, LV_DDC_SCL, SCL/CFG0, and SDA/CFG1.
The AC_EN pin threshold is fixed at 3.3-V LVCMOS levels. EN pin threshold is fixed at 1.2-V LVCMOS
threshold.
表8-2. Selection of LVCMOS Signaling Level
VIO pin
LVCMOS Signaling Level
VALUE < 1.5-V
1.2-V
1.8-V
3.3-V
1.5-V < VALUE < 2.5-V
VALUE > 2.5-V
8.2.3 HPD_OUT
The TDP1204 will level shift 5-V signaling level present on HPD_IN pin to a lower voltage such as 1.8-V or 3.3-V
levels on the HPD_OUT pin. The HPD_OUT supports both push-pull and open drain. The default operation is
push-pull. Selection between push-pull and open drain is done through the HPDOUT_SEL register.
表 8-2 lists how the VIO determines the output level of HPD_OUT when HPD_OUT is configured for push-pull
operation. Please note push-pull operation is not supported for VIO less than 1.7-V.
备注
Open-drain operation is only supported when TDP1204 is configured for I2C mode.
When EN pin is low, the HPD_OUT pin will be in a high impedance state. It is recommended to have a
weak pull-down resistor (such as 220k) on HPD_OUT.
8.2.4 Lane Control
The TDP1204 has various lane control features. Pin strapping globally controls features like receiver
equalization, VOD swing, slew rate, and pre-emphasis or de-emphasis. Through I2C receiver equalization,
transmitter swing, and pre-emphasis for each lane can be independently controlled.
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8.2.5 Swap
图8-1 shows how TDP1204 incorporates a swap function which can swap the lanes. The RX EQ, pre-emphasis,
termination, and slew configurations will follow the new mapping. This function is supported in pin strap mode as
well as when TDP1204 is configured for I2C mode. A register controls the swap function in I2C mode.
表8-3. Swap Functions
Normal Operation
CFG1 = H or LANE_SWAP Register is 1h
CFG1 pin = L or LANE_SWAP Register is 0h
IN_D2 →OUT_D2
IN_D1 →OUT_D1
IN_D0 →OUT_D0
IN_CLK →OUT_CLK
IN_CLK →OUT_CLK
IN_D0 →OUT_D0
IN_D1 →OUT_D1
IN_D2 →OUT_D2
IN_D2p
IN_D2n
IN_D2p
OUT_D2p
OUT_D2n
OUT_D2p
OUT_D2n
DATA LANE2
DATA LANE1
DATA LANE0
CLOCK LANE
IN_D2n
IN_D1p
IN_D1n
OUT_D1p
OUT_D1n
IN_D1p
IN_D1n
OUT_D1p
OUT_D1n
DATA LANE0
DATA LANE1
IN_D0p
IN_D0n
IN_D0p
IN_D0n
OUT_D0p
OUT_D0n
OUT_D0p
OUT_D0n
IN_CLKp
IN_CLKn
OUT_CLKp
OUT_CLKn
IN_CLKp
IN_CLKn
OUT_CLKp
OUT_CLKn
DATA LANE2
CLOCK LANE
In Normal Working
Lane Swap
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图8-1. TDP1204 Swap Function
8.2.6 Linear and Limited Redriver
The TDP1204 supports both linear and limited redriver. Selection between linear and limited can be done from
the LINEAR_EN pin in pin-strap mode or through GLOBAL_LINR_EN register in I2C mode.
The limited redriver mode will decouple TDP1204 transmitter's voltage swing, pre-emphasis or de-emphasis,
and slew rate from the GPUs transmitter. This allows the GPU to use a lower power TX setting and depends on
the TDP1204 transmitter to meet TX compliance requirements. For source applications, it is recommended to
configure TDP1204 as a limited redriver. It is not recommended to use limited redriver mode in sink applications.
Unlike limited redriver mode, in linear redriver mode the TDP1204 transmitter's output is not decoupled from the
GPU's transmitter. In linear redriver mode, the TDP1204 transmitter's output is a linear function of its input. The
linear redriver mode offers transparency to link training which makes it perfect for HDMI 2.1 applications. For
HDMI sink applications, it is recommended to configure TDP1204 as a linear redriver.
表 8-4 lists the requirements that the GPU transmitter must meet if linear redriver mode is used in an HDMI 2.1
source application. Linear redriver mode should only be used for HDMI 2.1 data rates. For HDMI 1.4 and 2.0, the
TDP1204 should be configured for limited mode (LINEAR_EN = "0" or "1").
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表8-4. Linear Redriver Mode: GPU TX Requirements for HDMI Source Applications
GPU TX Parameter
Min
Max
Units
Single-ended TX swing for HDMI
2.1
400
500
mV
TX rise/fall time for 3, 6, 8, 10,
and 12-Gbps FRL
16
mV/ps
The TDP1204 in pin-strap mode provides the option to dynamically switch between limited and linear based on
the HDMI mode of operation. The feature is enabled by setting LINEAR_EN pin = "1".
表8-5. Pin-Strap Mode LINEAR_EN Pin Function
LINEAR_EN Pin Level
HDMI 1.4, 2.0, or DP
HDMI 2.1 FRL
1
F
Limited Enabled
Linear Enabled
Linear Enabled
Recommended for DP and HDMI sink
application.
Linear Enabled
Recommended for DP and HDMI sink
application.
R
0
Reserved
Reserved
Limited Enabled.
Limited Enabled
Recommended for HDMI source application Recommended for HDMI source application
8.2.7 Main Link Inputs
Each main link input (IN_D[2:0] and IN_CLK) is internally biased to 3.3-V through approximately 100-Ω (50-Ω
single-ended). When using TDP1204 in DisplayPort++ applications, external AC-coupling capacitances should
be used. When using TDP1204 in an HDMI application such as in an HDMI monitor, the main link inputs can be
DC-coupled to a compliant HDMI transmitter. Each input data channel contains an equalizer to compensate for
cable or board losses.
8.2.8 Receiver Equalizer
The equalizer is used to clean up inter-symbol interference (ISI) jitter or loss from the bandwidth-limited board
traces or cables. TDP1204 supports fixed receiver equalizer by setting the EQ0 and EQ1 pins or through I2C
register. 表8-6 lists the pin strap settings and EQ values.
The TDP1204 has three sets of CTLE curves (3-Gbps CTLE, 6-Gbps CTLE, and 12-Gbps CTLE) with each
curve having 16 AC gain settings and 3 DC gain settings. 表 8-6 provides details about the 16 AC gain settings
with GLOBAL_DCG = 0x2.
The TDP1204 in pin-strap mode has three CTLE HDMI Datarate Maps: Map A, Map B, and Map C. 表 8-7
provides details about these maps. The expectation is Map A and C should be used if TDP1204 is used in a
source application and Map B for a sink application.
表 8-8 lists how the sampled state of the CTLEMAP_SEL pin determines the default CTLE HDMI Datarate map
when the TDP1204 is configured for pin-strap mode.
In I2C mode, the default CTLE (3-Gbps, 6-Gbps, or 12-Gbps) used for each HDMI mode can be controlled from
a register.
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EQ0 PIN
表8-6. Receiver EQ Settings When GLOBAL_DCG = 0x2
RX EQ Level for 3-
Gbps CTLE
(Gain at 1.5-GHz –
Gain at 10-MHz)
RX EQ Level for 6-
Gbps CTLE
(Gain at 3-GHz –Gain (Gain at 6-GHz –Gain
RX EQ Level for 12-
Gbps CTLE
EQ Setting(1)
EQ1 PIN
at 10-MHz)
at 10-MHz)
0(2)
1
1.0
2.0
0.5
0
0
0
0
R
F
1
1.0
0.8
2
3.2
2.4
1.8
0
3
4.2
3.3
2.7
0
4
5.3
4.4
3.7
F
F
F
F
R
R
R
R
1
0
5
6.0
5.2
4.4
R
F
1
6
7.0
6.0
5.0
7
7.7
6.8
5.8
8
9.0
7.5
6.5
0
9
9.5
8.2
7.5
R
F
1
10
11
12
13
14
15
10.0
10.5
11.0
11.5
12.0
12.3
8.8
8.3
9.3
9.1
10.0
10.5
11.0
11.8
9.8
0
10.3
11.0
11.6
1
R
F
1
1
1
(1) CLK_EQ, D0_EQ, D1_EQ, and D2_EQ registers determine the receiver EQ setting in I2C mode.
(2) When CTLEBYP_EN = 1 and DCGAIN = 0-dB, EQ settings 0 will be 0-dB due to the CTLE is bypassed.
表8-7. CTLE HDMI Datarate Map A, B, and C
HDMI Mode
1.4
Map A
Map B
Map C
12 Gbps CTLE
12 Gbps CTLE
12 Gbps CTLE
12 Gbps CTLE
12 Gbps CTLE
12 Gbps CTLE
12 Gbps CTLE
3 Gbps CTLE
6 Gbps CTLE
3 Gbps CTLE
6 Gbps CTLE
12 Gbps CTLE
12 Gbps CTLE
12 Gbps CTLE
6 Gbps CTLE
6 Gbps CTLE
6 Gbps CTLE
6 Gbps CTLE
12 Gbps CTLE
12 Gbps CTLE
12 Gbps CTLE
2.0
3 Gbps FRL
6 Gbps FRL
8 Gbps FRL
10 Gbps FRL
12 Gbps FRL
表8-8. Pin-strap Mode CTLE HDMI Datarate Mapping
Sampled State of CTLEMAP_SEL pin
"0"
"R"
"F"
"1"
CTLE HDMI Datarate Map
Map A
Map C
Map A
Map B
备注
The clock lane EQ when operating in HDMI 1.4 or 2.0 will use the 3-Gbps CTLE and will be set to the
zero EQ setting.
8.2.9 CTLE Bypass
The TDP1204 will operate as a buffer when CTLE bypass is enabled. In pin-strap mode, this feature is disabled.
In I2C mode, this feature is enabled when CTLEBYP_EN = 1h and GLOBAL_DCG = 2h. Any lane that has EQ
setting of 0h will operate in CTLE bypass.
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8.2.10 Adaptive Equalization in HDMI 2.1 FRL
The TDP1204 supports adaptive equalization (AEQ) for HDMI 2.1 FRL. It does not support AEQ for HDMI 1.4 or
2.0. In HDMI 1.4 and HDMI 2.0 modes, TDP1204 will use sampled state of EQ[1:0] pins or value programmed
into register. The AEQ is supported in some pin-strap modes as well as in I2C mode. In I2C mode, AEQ can be
enabled by setting the AEQ_EN register. The TDP1204 adaptation algorithm scans through available
equalization settings searching for a setting for which the incoming high-speed signal is not over equalized.
The TDP1204 will perform adaptive equalization when FRL link training begins. It will also readapt each time the
data rate changes. The adaption will only occur during the TXFFE0 portion of FRL link training when LTP5,
LTP6, LTP7, or LTP8 is being received. The TDP1204 adaption will complete within tAEQ_DONE from the time FRL
link training begins. If the sink requests additional TXFFE levels (TXFFE1, 2, or 3), then the TDP1204 will keep
its equalizer settings fixed at the value adapted during TXFFE0. If for some reason the FRL link training fails and
transitions to legacy mode (HDMI 1.4 or HDMI 2.0), then the EQ [1:0] pins sample the EQ settings that the
TDP1204 switches to if in pin-strap mode or programmed into the register (if in I2C mode).
The TDP1204 will keep OUT_D[2:0] and OUT_CLK disabled until after adaptation completes. After adaptation
completes, the appropriate lanes will be enabled. In I2C mode, this behavior can be overridden by clearing the
AEQ_TX_DELAY_EN field.
表8-9. Adaptive Equalization Enable and Disable
CTLEMAP_SEL pin level
MODE pin level
0
R
F
1
0
R
F
1
AEQ disabled
AEQ disabled
I2C register
AEQ disabled
AEQ disable
AEQ disabled
I2C register
AEQ disabled
AEQ disabled
AEQ enabled
I2C register
AEQ enabled
AEQ disabled
AEQ enabled
I2C register
AEQ enabled
备注
The AEQ operates only on IN_D1 pins (pins 12 and 13). The EQ value determined by AEQ will be
applied to the other FRL data lanes.
8.2.10.1 HDMI 2.1 TX Compliance Testing with AEQ Enabled
Care must be taken when performing HDMI 2.1 TX compliance testing with AEQ enabled. Because the
TDP1204 will only adapt to LTP5 through 8 during the TXFFE0 part of link training, it is important the test
equipment initiate a FRL link training before performing any TX measurements, especially TX eye and jitter
measurement. After completion of FRL link training, the test equipment can then switch the current pattern
(LTP5, LTP6, LTP7, or LTP8) to the desired test pattern (LTP1, LTP2, LTP3, or LTP4). If the test equipment
request LTP1, LTP2, LTP3, or LTP4 before initiating link training, the TDP1204 will use the sampled state of
EQ[1:0] pins.
The following HDMI 2.1 TX tests use LTP5, LTP6, LTP7, and LTP8 as the required pattern for the measurement:
HFR1-1, HFR1-2, HFR1-4, HFR1-7, and HFR1-8. If the TDP1204 AEQ adaption has not completed and instead
uses sampled state of EQ[1:0] pins, then it is possible these tests may fail or inaccurately represent system
performance.
8.2.11 HDMI 2.1 Link Training Compatible Rx EQ
This mode is recommended in source applications in which the GPU is unaware of the TDP1204 presence and
will adjust its transmitter levels (VOD, de-emphasis, and pre-shoot) during HDMI 2.1 FRL link training. This mode
is only supported if the TDP1204 is enabled for limited redriver. 表 8-10 lists the TXFFE levels that this mode
assumes the GPU is using.
This feature is supported in I2C mode and all pin-strap modes with the exception of MODE = "0".
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In HDMI 2.1 with AEQ disabled, the TDP1204 will initially set the RX EQ based on the EQ0 and EQ1 pins. The
pins determines what value will be used when the TXFFE0 is snooped during FRL link training. 表 8-11 lists how
TDP1204 uses the EQ setting for each increase in TXFFE level (TXFFE1, 2, or 3) from the sampled state of the
EQ [1:0] pins.
When HDMI 2.1 with AEQ is enabed, the TDP1204 will adapt during the TXFFE0 portion of FRL link training. 表
8-11 lists how TDP1204 uses the EQ setting for each increase in TXFFE level (TXFFE1, 2, or 3) from the
adapted EQ value.
表8-10. Recommended GPU FRL TXFFE Levels
GPU FRL TXFFE Levels
TXFFE0
Pre-Shoot (dB)
De-Emphasis (dB)
−3.10
2.18
2.50
2.92
3.52
TXFFE1
−4.43
TXFFE2
−6.02
TXFFE3
−7.96
表8-11. Link Training Compatible RX EQ Adjustments
Initial EQ Setting from sampled
state of EQ[1:0] pins or
adapted EQ value
EQ Setting Used for TXFFE1
EQ Setting Used for TXFFE2
EQ Setting Used for TXFFE3
0
1
0
0
0
0
0
0
1
1
1
1
2
3
4
5
6
7
8
9
0
0
0
0
0
0
0
0
1
1
1
1
2
3
4
5
2
1
3
1
4
2
5
2
6
3
7
3
8
4
9
5
10
11
12
13
14
15
6
7
8
9
10
11
8.2.12 Input Signal Detect
When standby is enabled and swap is disabled, the TDP1204 looks for a signal on either IN_CLK (if HDMI 1.4 or
2.0) or IN_D2 (if HDMI 2.1). When standby is enabled and swap is enabled, the TDP1204 looks for a signal on
either IN_CLK (if HDMI 2.1) or IN_D2 (if HDMI 1.4 or 2.0). The TDP1204 is fully functional when a signal is
detected. If no signal is detected, then the device reenters standby mode waiting for a signal again. In the
standby state, all of the TMDS outputs are in high-Z status. In both pin-strap mode and I2C mode, standby is
enabled by default. In I2C mode, standby can be disabled by setting the STANDBY_DISABLE register.
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8.2.13 Main Link Outputs
8.2.13.1 Transmitter Bias
The TDP1204 transmitter supports both external (DC-coupled) and internal bias (AC-coupled) to a receiver.
Selection between DC and AC-coupled is done through use of the AC_EN pin in pin-strap mode and TX_AC_EN
register in I2C mode. The AC_EN pin informs the TDP1204 whether or not an external AC-coupling capacitor is
present. When AC_EN is greater than VIH, then TDP1204 transmitters are internally biased to approximately
VCC. For DisplayPort, HDMI 2.1 FRL AC-coupled, or any other AC-coupled application, the AC_EN pin should
be connected to greater than VIH and an external AC-coupling capacitor should be placed on each of the
OUT_D[2:0] pins and the OUT_CLK pin. If the AC_EN pin is connected to less than VIL, then the AC_EN pin will
inform TDP1204 that AC_EN pin is DC-coupled (externally biased) to the far-end HDMI compliant receiver.
备注
图 8-3 shows that if using AC-coupled TX mode (AC_EN = high) in an HDMI source application, then
an external 499 Ω pull-down to GND must be placed on each OUT pin (OUT_D2:0p/n and
OUT_CLKp/n) between the AC-coupling capacitor and the HDMI receptacle. The purpose of the 499
Ωresistor is to set the common mode voltage to HDMI compliant levels.
OUT_D2p
OUT_D2n
OUT_D1p
OUT_D1n
OUT_D0p
OUT_D0n
OUT_CLKp
OUT_CLKn
图8-2. DC-Coupled TX in HDMI Source Application (AC_EN = Low). External ESD is Not Shown.
499
CACTX
OUT_D2p
OUT_D2n
OUT_D1p
OUT_D1n
OUT_D0p
OUT_D0n
OUT_CLKp
OUT_CLKn
System 3.3 V
图8-3. AC-Coupled TX in HDMI Source Application (AC_EN = High). External ESD is Not Shown.
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8.2.13.2 Transmitter Impedance Control
HDMI 2.0 standards require a source termination impedance approximately 100-Ω for data rates > 3.4-Gbps.
HDMI 1.4b requires no source termination but has a provision for termination for higher data rates greater than
1.65-Gbps. Enabling this termination is optional. 表 8-13 lists how the TDP1204 terminations are controlled
automatically when in pin strap mode. Depending on the MODE pin, the CFG0 pin can be used to select the
HDMI 1.4 termination between open and 300-Ω.
The TDP1204 supports automatic selection between open and 300-Ω termination when operating in HDMI 1.4.
In pin-strap mode with CTL0 low, the TDP1204 will enable open termination when HDMI clock frequency is less
than fHDMI14_open and will enable 300-Ω termination when HDMI clock frequency is greater than fHDMI14_300
.
TXTERM_AUTO_HDMI14 register controls this feature in I2C mode.
In I2C mode, termination is controlled through registers as described by 表8-12.
表8-12. Source Termination Control in I2C mode
TXTERM_AUTO_HDMI14
Register
TX_AC_EN Register
TERM Register
Source Termination
0
0
00
01
X
X
None
Parallel ≅ 300-Ωacross P and N
Automatic. HDMI 2.0 or HDM 2.1. parallel ≅ 100-Ω
0
0
0
10
10
10
X
1
0
across P and N
Automatic. HDMI 1.4. parallel ≅ 300-Ωacross P and N
Automatic. HDMI 1.4. No termination if HDMI clock
frequency is ≤fHDMI14_open
.
Automatic. HDMI 1.4. Parallel ≅ 300-Ωacross P and N
0
10
0
termination if HDMI clock frequency is ≥fHDMI14_300
Parallel ≈100-Ωacross P and N
.
0
1
1
11
00
01
X
X
X
≅ 150-Ωto supply (VCC) on both P and N
≅ 150-Ωto supply (VCC) on both P and N
Automatic. ≅ 150-Ωto supply (VCC) on both P and N
for HDMI 1.4. Otherwise ≅ 50-Ωto supply (VCC) on
both P and N.
1
1
10
11
X
X
≅ 50-Ωto supply (VCC) on both P and N
表8-13. Automatic Source Termination Control in Pin-Strap Mode
HDMI Mode
AC_EN pin
Source Termination
None or parallel ≅ 300-Ωacross P and N
depending on state of SCL/CFG0 pin
HDMI 1.4
0
HDMI 2.0
HDMI 1.4
HDMI 2.0
0
1
1
Parallel ≅ 100-Ωacross P and N
≅ 150-Ωto supply (VCC) on both P and N
≅ 50-Ωto supply (VCC) on both P and N
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8.2.13.3 TX Slew Rate Control
The TDP1204 has the ability to slow down the TMDS output edge rates. In pin-strap mode, the TX slew rate can
not be controlled. In I2C mode, both clock and data lanes slew rate can be controlled from a register. 表8-14 lists
the supported settings for each slew rate register based on HDMI data rate. The TDP1204 must be configured in
limited redriver mode to control the TX slew rate.
表8-14. I2C Mode TX Slew Register Supported Settings
SLEW_8G10G12G
HDMI Datarate
SLEW_CLK Register
SLEW_3G Register
SLEW_6G Register
Register
HDMI 1.4
3'b000 through 3'b011
3'b010 through 3'b101
N/A
N/A
HDMI 2.0
3'b000 through 3'b011
N/A
3'b011 through 3'b110
N/A
HDMI 2.1 3 Gbps FRL
HDMI 2.1 6 Gbps FRL
HDMI 2.1 8Gbps FRL
HDMI 2.1 10 Gbps FRL
HDMI 2.1 12 Gbps FRL
N/A
N/A
N/A
N/A
N/A
3'b010 through 3'b101
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3'b011 through 3'b110
N/A
N/A
N/A
3'b100 through 3'b111
3'b110 through 3'b111
3'b111
8.2.13.4 TX Pre-Emphasis and De-Emphasis Control
The TDP1204 provides pre-emphasis and de-emphasis on the data lanes allowing the output signal pre-
conditioning to offset interconnect losses between the TDP1204 outputs and a TMDS receiver. Pre-emphasis
and de-emphasis is not implemented on the clock lane unless the TDP1204 is in HDMI 2.1 FRL mode and at
which time the clock lane becomes a data lane. There are two methods to implement pre-emphasis, pin
strapping or through I2C programming. TX pre-emphasis and de-emphasis control is only supported in limited
mode.
When using pin strap mode, the TXPRE pin controls four different global pre-emphasis and de-emphasis values
for all data lanes when TDP1204 is operating in HDMI 1.4 or HDMI 2.0. 表8-15 lists these pre-emphasis and de-
emphasis values. In HDMI 2.1 FRL mode, the de-emphasis value used is based on the DDC TXFFE snooped
value. 表8-16 lists how the TDP1204 uses the de-emphasis level for each TX FFE level.
表8-15. Pin-Strap TXPRE Pin Function
LINEAR_EN pin = "F"
LINEAR_EN pin = "0"
LINEAR_EN pin = "R"
AEQ ADJUSTMENT
or "1"
HDMI 2.1 FRL
TXFF0 Level
TXPRE pin
HDMI 1.4 or HDMI 2.0
AEQ ADJUSTMENT
AEQ ADJUSTMENT
0
3.5 dB pre-emphasis
-2.5 dB de-emphasis
0
0
0
0
+1
+4
0
0
0
0
0
Refer to 表8-16.
Refer to 表8-16.
Refer to 表8-16.
Refer to 表8-16
R
F
1
0 dB
6.0 dB pre-emphasis
+2
表8-16. HDMI 2.1 FRL TX FFE Levels
De-Emphasis
(dB)
FRL TX FFE Snooped Level
TXFFE0
TXFFE1
TXFFE2
TXFFE3
-2.5
-3.5
-3.7
-4.6
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8.2.13.5 TX Swing Control
The TDP1204 transmitter swing level can be adjusted in both pin strap and I2C mode. In I2C mode, TX swing
settings are controlled independently for each lane (both clock and data) through registers.
In I2C mode, the TX swing used when operating in HDMI 1.4 and HDMI 2.0 can be indepedently controlled
through HDMI14_VOD and HDMI20_VOD registers.
表 8-17 lists how the TXSWG pin adjusts the default 1000 mV swing in pin strap mode with limited redeliver
mode enabled. In HDMI 1.4 the TXSWG controls the swing for both the data and clock lanes. In HDMI 2.0, the
TXSWG pin controls the data lanes while the clock lane will remain at the default value. In HDMI 2.1, the
TXSWG pin controls data and clock lanes.
In pin-strap mode with linear enabled, the linearity range is fixed at the highest level (1200 mVpp) and therefore
TXSWG pin is not used. In I2C mode, the linearity range can be adjusted from a register.
表8-17. Pin Strap TXSWG Control
TXSWG pin
Limited Mode for HDMI 1.4
Default (1000 mVpp)
Default − 5%
Limited Mode for HDMI 2.0
Default (1000 mVpp)
Default − 5%
Limited Mode for HDMI 2.1
Default + 10%
Linear Mode
1200 mVpp
1200 mVpp
1200 mVpp
1200 mVpp
0
R
F
1
Default − 5%
Default (1000 mVpp)
Default (1000 mVpp)
Default (1000 mVpp)
Default + 5%
Default (1000 mVpp)
Default + 5%
8.2.14 DDC Buffer
The TDP1204 has a DDC buffer for capacitance isolation and for shifting 5-V levels present on the HDMI
connector to as low as 1.2-V levels on the GPU source side. The HV_DDC_SDA and HV_DDC_SCL pins
support 5-V levels while the LV_DDC_SDA and LV_DDC_SCL pins support 1.2-V, 1.8-V, and 3.3-V levels. When
the DDC buffer is used in source application, the HV side must be pulled up using 1.5-kΩto 2-kΩresistors. It is
recommended to use 1.8-kΩ ±5% resistor. HV_DDC_SDA and HV_DDC_SCL pins will typically be pulled up to
HDMI 5-V. The LV_DDC_SDA and LV_DDC_SCL are internally pulled up to VIO.
The TDP1204 enables DDC translation from low voltage (system side) voltage levels to 5-V (HDMI cable side)
voltage levels without degradation of system performance. The TDP1204 contains 2 bidirectional, open-drain
buffers specifically designed to support up and down-translation between the low voltage (LV) side DDC-bus and
the high voltage (HV) 5-V DDC-bus. The HV I/Os (HV_DDC_SCL and HV_DDC_SDA) are overvoltage tolerant
to 5.5-V. After HPD_IN high, a LOW level on LV side (below VILC = 0.08 × VIO) turns the corresponding HV
driver (either SDA or SCL) on and drives HV side down to VHVOL. When LV side rises above approximately 0.10
× VIO, the HV pulldown driver is turned off and the internal pullup resistor pulls the pin HIGH. When HV side falls
first and goes below 1.6-V, a CMOS hysteresis input buffer detects the falling edge, turns on the LV driver, and
pulls LV down to approximately VLVOL = 0.16 × VIO. The LV side pulldown is not enabled unless the LV voltage
goes below VILC. If the LV side low voltage goes below VILC, the HV side pulldown driver is enabled until LV
side rises above (VILC + ΔVT-HYST), then HV side, if not externally driven LOW, continues to rise being pulled
up by the external pullup resistor.
VIO
RPULV
HDMI 5V
RPUHV
LV_DDC_SDA
LV_DDC_SCL
VIC
+
-
HV_DDC_SDA
HV_DDC_SCL
CHV_BUS
CLV_BUS
VLV_OL
图8-4. DDC Buffer Block Diagram
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图 8-5 shows the connection of the LV and HV DDC pins when using the DDC buffer. This connection is
supported in pin-strap mode when MODE pin is "0" or "1". In I2C mode, the DDCBUF_EN register must be set to
enable the DDC Buffer.
备注
The TDP1204 has integrated pullups to VIO on the DDC LV pins. Therefore, no external pull-ups shall
be present between the TDP1204's DDC LV pins and DDC host when using TDP1204's DDC buffer.
HDMI_5V
VIO (1.14 V to 3.6 V)
1.8-k
Redriver
LV_DDC_SDA
LV_DDC_SCL
HV_DDC_SDA
HV_DDC_SCL
DP++
Or HDMI
Source
图8-5. Source Application: DDC Buffer Enabled
图8-6 shows an example source application of snooping from the HV DDC pins. In this example, the DDC buffer
must be enabled and the LV DDC pins must be floating. This connection is supported in pin-strap mode when
MODE pin is "0" or "1". In I2C mode, the DDCBUF_EN register must be set to enable the DDC Buffer.
HDMI_5V
VIO (1.14 V to 3.6 V)
1.8-k
1.8-k
Redriver
HV_DDC_SDA
LV_DDC_SDA
LV_DDC_SCL
HV_DDC_SCL
I2C Voltage
DP++
Or HDMI
Source
Discrete
DDC
Level shi er
图8-6. Source Application: DDC Buffer Enabled and Snoop from HV DDC pins
图 8-7 shows an example source application of snooping from the LV DDC pins. In this example, the DDC buffer
must be disabled and the HV DDC pins must be floating. This connection is supported in pin-strap mode when
MODE pin is "R". In I2C mode, the DDCBUF_EN register must be cleared to disable the DDC Buffer.
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VIO (1.14 V to 3.6 V)
Redriver
HV_DDC_SDA
LV_DDC_SDA
LV_DDC_SCL
DP++
Or HDMI
Source
HV_DDC_SCL
HDMI_5V
1.8-k
Discrete
DDC
Level shi er
图8-7. Source Application: DDC Buffer Disabled and Snoop from LV DDC pins
图 8-8 shows the connection of the LV and HV DDC pins when using the DDC buffer in a sink application. This
connection is supported in pin-strap mode when MODE pin is "0" or "1". In I2C mode, the DDCBUF_EN register
must be set to enable the DDC Buffer.
HDMI_5V
VIO (1.14 V to 3.6 V)
47-k
Redriver
LV_DDC_SDA
LV_DDC_SCL
HV_DDC_SDA
HV_DDC_SCL
HDMI SINK
(scaler)
图8-8. Sink Application: DDC Buffer Enabled
图 8-9 shows an example sink application of snooping from the LV DDC pins. In this example, the DDC buffer
must be disabled and the HV DDC pins must be floating. This connection is supported in pin-strap mode when
MODE pin is "R". In I2C mode, the DDCBUF_EN register must be cleared to disable the DDC Buffer.
VIO (1.14 V to 3.6 V)
Redriver
HV_DDC_SDA
HV_DDC_SCL
LV_DDC_SDA
LV_DDC_SCL
HDMI_5V
47-k
HDMI SINK
(scaler)
Discrete
DDC
Level shiꢀer
图8-9. Sink Application: DDC Buffer Disabled and Snoop from LV DDC pins
图 8-10 shows an example sink application of snooping from the HV DDC pins. In this example, the DDC buffer
must be enabled and the LV DDC pins must be floating. This connection is supported in pin-strap mode when
MODE pin is "0" or "1". In I2C mode, the DDCBUF_EN register must be set to enable the DDC Buffer.
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HDMI_5V
47-k
VIO (1.14 V to 3.6 V)
Redriver
HV_DDC_SDA
HV_DDC_SCL
LV_DDC_SDA
LV_DDC_SCL
I2C Voltage
Discrete
DDC
Level shi er
HDMI SINK
(scaler)
图8-10. Sink Application: DDC Buffer Enable and Snoop from HV DDC pins
8.2.15 HDMI DDC Capacitance
The HDMI specification limits the DDC bus capacitance to ≤ 50-pF for both an HDMI source and sink.
Therefore, care must be taken to make sure the total capacitance of all components (TDP1204, FR4 trace, ESD,
source, and sink) is less than 50-pF.
The TDP1204s DDC Buffer offers capacitance isolation between the LV DDC pins and the HV DDC pin. The
total capacitance of components, including the FR4 trace, between the TDP1204 HV_DDC_SDA/SCL pins and
the HDMI receptacle must be ≤(50-pF –CIOHV).
If implementing a DDC level shifter using pass gates, then the total capacitance will include all components
between source or sink and the HDMI receptacle. These components include and are not limited to Source or
Sink, the FR4 trace, ESD components, and TDP1204.
备注
Trace capacitance can be in the range of 2 to 5-pF per inch. A general rule is a 50-Ω FR4 trace will be
around 3.3-pF per inch.
8.3 Device Functional Modes
8.3.1 MODE Control
The MODE pin provides four modes of operation. There are three pin-strap modes and one I2C mode. In all
three pin strap modes, DDC snooping feature is enabled. In I2C mode, DDC snoop feature is enabled by default
but can be disabled by a register.
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8.3.1.1 I2C Mode (MODE = "F")
In I2C mode, all settings of the TDP1204 can be controlled through the registers. The TDP1204 7-bit I2C
address is determined by the ADDR/EQ0 pin. All other 4-level and 2-level pins are not used in I2C mode since
the functions exist in a register. The SCL/CFG0 pin will function as the I2C clock and the SDA/CFG1 pin will
function as the I2C data.
The TDP1204 defaults to power down in I2C mode. Upon completion of initialization of the TDP1204, software
must clear the PD_EN field to exit the power down state. The HPD_OUT pin will be asserted low while the
PD_EN register is set.
The TDP1204 supports 1.2-V, 1.8-V, and 3.3-V I2C signaling levels. Selection of 1.2-V, 1.8-V, or 3.3-V is
determined by the VIO pin as described in 表8-2.
8.3.1.2 Pin Strap Modes
表 8-18 and 表 8-19 lists how the SCL/CFG0 and the SDA/CFG1 pins will be used to control the HDMI 1.4
termination, lane SWAP function, and the DisplayPort mode in pin-strap mode.
表8-18. SCL/CFG0 Pin in Pin-Strap Mode
SCL/CFG0 Pin
AC_EN Pin
TDP1204 Function
0
0
HDMI 1.4 termination is open if HDMI clock
frequency ≤fHDMI14_open
0
0
HDMI 1.4 termination is ≅300-Ω if HDMI
clock frequency ≥fHDMI14_300
1
0
0
1
HDMI 1.4 termination is ≅300-Ω
Normal HDMI. Function determined by
MODE pin.
DisplayPort mode. DDC snoop disabled. All
four lanes enabled when HPD_IN is high. 12
Gbps CTLE used.
1
1
表8-19. SDA/CFG1 Pin in Pin-Strap Mode
SDA/CFG1 Pin
TDP1204 Function
0
1
Normal Lane ordering
Lane Swap enabled
备注
The SCL/CFG0 is the only two-level pin that is continuously sampled in pin-strap mode. AC_EN,
HPDOUT_SEL, and SDA/CFG1 will not be continuously sampled in pin-strap mode unless indicated
otherwise.
The TDP1204 must be configured as a linear redriver when operating in DisplayPort mode.
8.3.1.2.1 Pin-Strap: HDMI 1.4 and HDMI 2.0 Functional Description
The TDP1204 will always use the sampled state of EQ[1:0] pins when operating in either HDMI 1.4 and HDMI
2.0. The amount of EQ applied is determined by the CTLE Map used (refer to Receiver EQ section).
If TDP1204 is configured for limited redriver mode, then the OUT_D[2:0] and OUT_CLKP/N levels will be fixed
based on the sampled state of TXSWG pin (refer to 表8-17) and TXPRE pin (refer to 表8-15).
If TDP1204 is configured for linear redriver mode, then OUT_D[2:0] and OUT_CLK will be a linear function of the
input signals.
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备注
In source application, it is recommended to use limited redriver mode for both HDMI 1.4 and HDMI
2.0.
8.3.1.2.2 Pin-Strap HDMI 2.1 Function (MODE = "0"): Fixed Rx EQ and DDC Buffer Enabled
This mode is recommended in a source applications in which the GPU is aware of the TDP1204 presence and
keeps its transmitter levels (VOD, de-emphasis and pre-shoot) fixed during HDMI 2.1 FRL link training. In this
mode, the TDP1204 will provide an HDMI compliant signal at the HDMI receptacle.
In this mode, the TDP1204 will operate with a fixed RX EQ based on the value set by EQ0 and EQ1 pins.
In HDMI 2.1 FRL with limited redriver enabled, OUT_D[2:0] and OUT_CLK outputs will change based on the
snooped value of TXFFE levels. 表8-16 lists the TXFFE level used for each snooped value.
In HDMI 2.1 FRL with linear redriver enabled, OUT_D[2:0] and OUT_CLK outputs will function as described in 节
8.2.6.
备注
Adaptive EQ is not supported in this mode. Link Training Compatible Rx EQ is not supported in this
mode.
8.3.1.2.3 Pin-Strap HDMI 2.1 Function (MODE = "1"): Flexible RX EQ and DDC Buffer Enabled
This mode is recommended in a source applications in which the GPU is unaware of the TDP1204 presence and
will adjust its transmitter levels (VOD, de-emphasis, and pre-shoot) during HDMI 2.1 FRL link training.
In this mode, the TDP1204 supports both 节8.2.10 and 节8.2.11.
If TDP1204 is configured for limited redriver mode, then the OUT_D[2:0] and OUT_CLKP/N VOD level will be
fixed based on the sampled state of TXSWG (refer to 表 8-17). In HDMI 2.1 FRL, these outputs will change
based on the snooped value of TXFFE levels. 表8-11 lists the TXFFE level used for each snooped value.
In this mode with limited redriver enabled, it is highly that the recommended GPU use TXFFE levels listed in 表
8-10.
8.3.1.2.4 Pin-Strap HDMI 2.1 Function (MODE = "R"): Flexible Rx EQ and DDC Buffer Disabled
This pin strap mode is the same as MODE ="1" with the exception the DDC buffer is disabled.
备注
This mode is intended to be used when external discrete DDC buffer or level shifter is used.
HV_DDC_SDA and HV_DDC_SCL pins can be left floating in this mode.
8.3.2 DDC Snoop Feature
As part of discovery the source reads the sink E-EDID information to understand the sink’s capabilities. Part of
this read is HDMI Forum Vendor Specific Data Block (HF-VSDB) located at target address 0xA8. From the
LV_DDC_SDA and LV_DDC_SCL pins, the TDP1204 DDC snoop function will monitor both reads and writes to
specific offsets of the Status and Control Data Channel Structure (SCDCS) located within the HF-VSDB. The
following SCDCS offsets are monitored: Update Flags at offset 10h, TMDS Configuration at offset 20h, Sink
Configuration at offset 31h, Source Test Configuration at offset 35h, and Status Flags located at offsets 41h and
42h. The DDC snoop function resides on the LV_DDC_SDA and LV_DDC_SCL pins.
The TDP1204 has similar SCDCS registers within its register space. Through TDP1204 local I2C interface,
external microprocessor can control TDP1204 to perform all the necessary functions required for each HDMI
type.
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8.3.2.1 HDMI Type
表 8-20 lists the TDP1204 monitors offsets 20h and 31h to determine HDMI type as either HDMI 1.4, HDMI 2.0,
or HDMI 2.1 FRL.
表8-20. HDMI Type Selection
TMDS_CLK_RATIO
SCDCS Offset 20h[1]
FRL_RATE
SCDCS Offset 31h[3:0]
HDMI Type
HDMI 1.4 (TMDS x10)
HDMI 2.0 (TMDS x40)
HDMI 2.1 FRL
0
1
0h
0h
X
Not 0h
备注
TDP1204 will default to HDMI 1.4 following a power-on reset or whenever it enters the powerdown
state. Upon exiting standby, the TDP1204 will hold data rate value (HDMI 1.4, 2.0, or 2.1) prior to
entering the standby.
8.3.2.2 HDMI 2.1 FRL Snoop
In HDMI 2.1 FRL mode, the TDP1204 monitors offset 31h, 35h, 41h, and 42h. Each offset contains information
that the TDP1204 uses during FRL link training or during TX compliance testing.
Offset 31h contains FRL lane count (3 or 4 lanes), data rate (3, 6, 8, 10, or 12 Gbps), and maximum TXFFE
levels supported. TDP1204 enables the appropriate number of lanes based on the lane count. The TDP1204
uses the data rate information to determine the duration of the TXFFE de-emphasis. The maximum number of
supported TXFFE levels sets the number of TXFFE levels TDP1204 uses during FRL link training. 表 8-16 lists
the TDP1204 does support all four possible TXFFE levels (TXFFE0 through TXFFE3).
Values snooped from offset 35h is used by TDP1204 during TX FFE compliance testing.
8.3.3 Low Power Modes
The TDP1204 has two low power modes: Power Down and Standby. 表 8-21 lists both lower power modes.
Power down is entered when HPD_IN is low for tHPD_PWRDOWN or in I2C if PD_EN bit is set. Power down is also
entered when the EN pin is low. The TDP1204 will exit power down to the standby state when HPD_IN is high
for tHPD_STANDBY
.
The TDP1204 implements a two stage standby power process when HPD_IN is high.
Stage 1: If there is no signal (electrical idle) on the IN_CLK lane if HDMI 1.4/2.0 or IN_D2 if HDMI 2.1, then the
TDP1204 will enter standby mode within tSTANDBY_ENTRY
Stage 2: If a signal is detected which last longer than tSIGDET_DB, then TDP1204 will declare a valid signal and
exit standby within tSTANDY_EXIT
.
.
• If a signal is detected, then the TDP1204 will go into normal active operation and signals present at IN_CLK
and IN_D[2:0] inputs will be passed through to the OUT_CLK and OUT_D[2:0] outputs.
• If it is determined that no signal is present, then the TDP1204 will reenter stage 1.
The TDP1204 will exit standby state and immediately enter active state if LTP1, LTP2, LTP3, or LTP4 is snooped
while monitoring status flags at SCDCS offset 41h or 42h.
The TDP1204 will exit normal operation and return to the standby state within tSTANDBY_ENTRY anytime electrical
idle is detected.
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表8-21. Power Modes
INPUTS
STATUS
HDMI
STANDBY_ HPD_PWRDW
1.4/2.0:
HPD_IN
pin
PD_EN
register
OUT_Dx
OUT_CLK
EN pin
DISABLE
register
N_DISABLE
register
IN_CLK pin HPD_OUT pin IN_Dx pins SDA/SCL
HDMI 2.1:
DDC
Mode
IN_D2 pins
Power
Down Mode
L
X
L
X
X
X
1
X
0
X
0
1
0
0
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
Disabled
Active
Active
Active
Active
High-Z
High-Z
Disabled
Disabled
Disabled
Active
Power
Down Mode
H
H
H
H
L
Power
Down Mode
X
H
X
X
X
1
L
HPD_IN
H
High-Z
All RX
Active
Normal
operation
TX Active
TX Active
All RX
Active
Normal
operation
1
Active
HDMI
1.4/2.0:
IN_CLK
Active
HDMI 2.1:
IN_D2
Standby
Mode
(Squelch
waiting)
H
H
H
H
H
H
X
X
0
0
0
0
X
X
1
1
0
0
0
0
No signal
HPD_IN
Active
Active
Active
Active
High-Z
TX Active
High-Z
Active
Active
Active
Active
Active
Valid signal
detected
All RX
Active
Normal
operation
HPD_IN
HDMI
1.4/2.0:
IN_CLK
Active
HDMI 2.1:
IN_D2
Standby
Mode
(Squelch
waiting)
No signal
H
H
Active
Valid signal
detected
All RX
Active
Normal
operation
TX Active
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8.4 Programming
8.4.1 Pseudocode Examples
These are examples of configuring TDP1204 when it is configured for I2C mode.
8.4.1.1 HDMI 2.1 Source Example with DDC Snoop and DDC Buffer Enabled
When using TDP1204's DDC buffer with snooping enabled, this example can be used. In this example, adaptive
EQ for HDMI 2.1 is disabled.
This example will initialize the following:
• Limited redriver mode with DC-coupled output
• TX slew rate for each data rate
• CTLE used for each data rate
• Receiver EQ setting for each lane (clock, D0, D1, and D2)
• TX voltage swing for each lane (clock, D0, D1, and D2)
• TX pre-emphasis or de-emphasis for HDMI 1.4 and 2.0
// (address, data)
// Initial power-on configuration.
(0x0A, 0x00), // Rate snoop and TXFFE snoop enabled.
(0x0B, 0x23), // 3G and 6G slew rate control
(0x0C, 0x70), // HDMI clock and 8G10G12G tx slew rate control
(0x0D, 0x22), // Limited mode, DC-coupled TX, 0 dB DCG, Auto Term, disable CTLE bypass
(0x0E, 0x97), // HDMI14, 2.0 and 2.1 CTLE selection
(0x10, 0x03), // Enabled DDC DCC correction and DDC buffer
(0x12, 0x03), // Clock lane VOD and TXFFE
(0x13, 0x00), // Clock lane EQ.
(0x14, 0x03), // D0 lane VOD and TXFFE.
(0x15, 0x0Y), // D0 lane EQ. Set "Y" to desired value.
(0x16, 0x03), // D1 lane VOD and TXFFE.
(0x17, 0x0Y), // D1 lane EQ. Set "Y" to desired value.
(0x18, 0x03), // D2 lane VOD and TXFFE.
(0x19, 0x0Y), // D2 lane EQ. Set "Y" to desired value.
(0x09, 0x00), // Take out of PD state. Should be done after initialization is complete.
8.4.1.2 HDMI 2.1 Source Example with DDC Snoop Disabled and DDC Buffer Disabled
When using an external discrete DDC buffer with snooping disabled, this example can be used. In this example,
adaptive EQ for HDMI 2.1 is disabled. Also, this example assumes the source only wants to support TXFFE0
level when operating in HDMI 2.1 FRL mode.
This example will initialize the following:
• Limited redriver mode with DC-coupled output
• TX slew rate for each data rate
• CTLE used for each data rate
// (address, data)
// Initial power-on configuration.
(0x0A, 0x05), // Rate snoop disabled and TXFFE controlled by 35h, 41h, and 42h
(0x0B, 0x23), // 3G and 6G tx slew rate control
(0x0C, 0x70), // HDMI clock and 8G10G12G TX slew rate control
(0x0E, 0x97), // HDMI 1.4, 2.0 and 2.1 CTLE selection
(0x11, 0x00), // Disable all four lanes.
(0x09, 0x00), // Take out of PD state. Should be done after initialization is complete.
// Selection between HDMI modes (1.4, 2.0, and 2.1)
switch (HDMI_MODE) {
case 'HDMI14_165' : // HDMI 1.4 configuration for less than 1.65 Gbps
(0x11, 0x00), // Disable all four lanes.
(0x0D, 0x20), // Limited mode, DC-coupled TX, 0dB DCG, Term open, disable CTLE bypass
(0x12, 0x03), // Clock lane VOD and TXFFE
(0x13, 0x00), // Clock lane EQ.
(0x14, 0x03), // D0 lane VOD and TXFFE.
(0x15, 0x0Y), // D0 lane EQ. Set "Y" to desired value.
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(0x16, 0x03), // D1 lane VOD and TXFFE.
(0x17, 0x0Y), // D1 lane EQ. Set "Y" to desired value.
(0x18, 0x03), // D2 lane VOD and TXFFE.
(0x19, 0x0Y), // D2 lane EQ. Set "Y" to desired value.
(0x20, 0x00), // Clear TMDS_CLK_RATIO
(0x31, 0x00), // Disable FRL
(0x11, 0x0F), // Enable all four lanes.
break;
case 'HDMI14_340' : // HDMI 1.4 configuration for greater than 1.65 Gbps
(0x11, 0x00), // Disable all four lanes.
(0x0D, 0x21), // Limited mode, DC-coupled TX, 0dB DCG, Term 300, disable CTLE bypass
(0x12, 0x03), // Clock lane VOD and TXFFE
(0x13, 0x00), // Clock lane EQ.
(0x14, 0x03), // D0 lane VOD and TXFFE.
(0x15, 0x0Y), // D0 lane EQ. Set "Y" to desired value.
(0x16, 0x03), // D1 lane VOD and TXFFE.
(0x17, 0x0Y), // D1 lane EQ. Set "Y" to desired value.
(0x18, 0x03), // D2 lane VOD and TXFFE.
(0x19, 0x0Y), // D2 lane EQ. Set "Y" to desired value.
(0x20, 0x00), // Clear TMDS_CLK_RATIO
(0x31, 0x00), // Disable FRL
(0x11, 0x0F), // Enable all four lanes.
break;
case 'HDMI20' : // HDMI 2.0 configuration
(0x11, 0x00), // Disable all four lanes.
(0x0D, 0x23), // Limited mode, DC-coupled TX, 0dB DCG, Term 100, disable CTLE bypass
(0x12, 0x03), // Clock lane VOD and TXFFE
(0x13, 0x00), // Clock lane EQ.
(0x14, 0x03), // D0 lane VOD and TXFFE.
(0x15, 0x0Y), // D0 lane EQ. Set "Y" to desired value.
(0x16, 0x03), // D1 lane VOD and TXFFE.
(0x17, 0x0Y), // D1 lane EQ. Set "Y" to desired value.
(0x18, 0x03), // D2 lane VOD and TXFFE.
(0x19, 0x0Y), // D2 lane EQ. Set "Y" to desired value.
(0x20, 0x02), // Set TMDS_CLK_RATIO
(0x31, 0x00), // Disable FRL
(0x11, 0x0F), // Enable all four lanes.
break;
case 'HDMI21_3G' : // HDMI 2.1 3 Gbps FRL
(0x11, 0x00), // Disable all four lanes.
(0x0D, 0x23), // Limited mode, DC-coupled TX, 0 dB DCG, Term 100, disable CTLE bypass
(0x12, 0x03), // Clock lane VOD and TXFFE
(0x13, 0x00), // Clock lane EQ.
(0x14, 0x03), // D0 lane VOD and TXFFE.
(0x15, 0x0Y), // D0 lane EQ. Set "Y" to desired value.
(0x16, 0x03), // D1 lane VOD and TXFFE.
(0x17, 0x0Y), // D1 lane EQ. Set "Y" to desired value.
(0x18, 0x03), // D2 lane VOD and TXFFE.
(0x19, 0x0Y), // D2 lane EQ. Set "Y" to desired value.
(0x20, 0x00), // Clear TMDS_CLK_RATIO
(0x31, 0x01), // Set to 3G FRL. Only TXFFE0 supported.
(0x11, 0x0F), // Enable all four lanes.
break;
case 'HDMI21_6G_3lane' : // HDMI 2.1 6 Gbps FRL 3 lanes
(0x11, 0x00), // Disable all four lanes.
(0x0D, 0x23), // Limited mode, DC-coupled TX, 0 dB DCG, Term 100, disable CTLE bypass
(0x12, 0x03), // Clock lane VOD and TXFFE
(0x13, 0x00), // Clock lane EQ.
(0x14, 0x03), // D0 lane VOD and TXFFE.
(0x15, 0x0Y), // D0 lane EQ. Set "Y" to desired value.
(0x16, 0x03), // D1 lane VOD and TXFFE.
(0x17, 0x0Y), // D1 lane EQ. Set "Y" to desired value.
(0x18, 0x03), // D2 lane VOD and TXFFE.
(0x19, 0x0Y), // D2 lane EQ. Set "Y" to desired value.
(0x20, 0x00), // Clear TMDS_CLK_RATIO
(0x31, 0x02), // Set to 6G FRL and 3 lanes. Only TXFFE0 supported.
(0x11, 0x0F), // Enable all four lanes.
break;
case 'HDMI21_6G_4lane' : // HDMI 2.1 6 Gbps FRL 4 lanes
(0x11, 0x00), // Disable all four lanes.
(0x0D, 0x23), // Limited mode, DC-coupled TX, 0 dB DCG, Term 100, disable CTLE bypass
(0x12, 0x03), // Clock lane VOD and TXFFE
(0x13, 0x0Y), // Clock lane EQ. Set to "Y" to desired value.
(0x14, 0x03), // D0 lane VOD and TXFFE.
(0x15, 0x0Y), // D0 lane EQ. Set "Y" to desired value.
(0x16, 0x03), // D1 lane VOD and TXFFE.
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(0x17, 0x0Y), // D1 lane EQ. Set "Y" to desired value.
(0x18, 0x03), // D2 lane VOD and TXFFE.
(0x19, 0x0Y), // D2 lane EQ. Set "Y" to desired value.
(0x20, 0x00), // Clear TMDS_CLK_RATIO
(0x31, 0x03), // Set to 6G FRL and 4 lanes. Only TXFFE0 supported.
(0x11, 0x0F), // Enable all four lanes.
break;
case 'HDMI21_8G' : //HDMI 2.1 8 Gbps FRL
(0x11, 0x00), // Disable all four lanes.
(0x0D, 0x23), // Limited mode, DC-coupled TX, 0 dB DCG, Term 100, disable CTLE bypass
(0x12, 0x03), // Clock lane VOD and TXFFE
(0x13, 0x0Y), // Clock lane EQ. Set "Y" to desired value.
(0x14, 0x03), // D0 lane VOD and TXFFE.
(0x15, 0x0Y), // D0 lane EQ. Set "Y" to desired value.
(0x16, 0x03), // D1 lane VOD and TXFFE.
(0x17, 0x0Y), // D1 lane EQ. Set "Y" to desired value.
(0x18, 0x03), // D2 lane VOD and TXFFE.
(0x19, 0x0Y), // D2 lane EQ. Set "Y" to desired value.
(0x20, 0x00), // Clear TMDS_CLK_RATIO
(0x31, 0x04), // Set to 8G FRL and 4 lanes. Only TXFFE0 supported.
(0x11, 0x0F), // Enable all four lanes.
break;
case 'HDMI21_10G' : //HDMI 2.1 10 Gbps FRL
(0x11, 0x00), // Disable all four lanes.
(0x0D, 0x23), // Limited mode, DC-coupled TX, 0 dB DCG, Term 100, disable CTLE bypass
(0x12, 0x03), // Clock lane VOD and TXFFE
(0x13, 0x0Y), // Clock lane EQ. Set "Y" to desired value.
(0x14, 0x03), // D0 lane VOD and TXFFE.
(0x15, 0x0Y), // D0 lane EQ. Set "Y" to desired value.
(0x16, 0x03), // D1 lane VOD and TXFFE.
(0x17, 0x0Y), // D1 lane EQ. Set "Y" to desired value.
(0x18, 0x03), // D2 lane VOD and TXFFE.
(0x19, 0x0Y), // D2 lane EQ. Set "Y" to desired value.
(0x20, 0x00), // Clear TMDS_CLK_RATIO
(0x31, 0x05), // Set to 10G FRL and 4 lanes. Only TXFFE0 supported.
(0x11, 0x0F), // Enable all four lanes.
break;
case 'HDMI21_12G' : //HDMI 2.1 12 Gbps FRL
(0x11, 0x00), // Disable all four lanes.
(0x0D, 0x23), // Limited mode, DC-coupled TX, 0 dB DCG, Term 100, disable CTLE bypass
(0x12, 0x03), // Clock lane VOD and TXFFE
(0x13, 0x0Y), // Clock lane EQ. Set "Y" to desired value.
(0x14, 0x03), // D0 lane VOD and TXFFE.
(0x15, 0x0Y), // D0 lane EQ. Set "Y" to desired value.
(0x16, 0x03), // D1 lane VOD and TXFFE.
(0x17, 0x0Y), // D1 lane EQ. Set "Y" to desired value.
(0x18, 0x03), // D2 lane VOD and TXFFE.
(0x19, 0x0Y), // D2 lane EQ. Set "Y" to desired value.
(0x20, 0x00), // Clear TMDS_CLK_RATIO
(0x31, 0x06), // Set to 12G FRL and 4 lanes. Only TXFFE0 supported.
(0x11, 0x0F), // Enable all four lanes.
break;
}
8.4.2 TDP1204 I2C Address Options
For further programmability, the TDP1204 can be controlled using I2C. The SCL/CFG0 and SDA/CFG1 terminals
are used for I2C clock and I2C data respectively.
表8-22. TDP1204 I2C Device Address Description
ADDR/EQ0 pin
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (W/R)
HEX
BC/BD
BA/BB
B8/B9
B6/B7
0
R
F
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
1
0
1
0
1
0/1
0/1
0/1
0/1
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8.4.3 I2C Target Behavior
Register O set
Target Address
Data wri en
P
S
A6
A5
A4
A3
A2
A1
A0
0
A
C7
C6
C5
C4
C3
C2
C1
C0
A
D7
D6
D5
D4
D3
D2
D1
D0
A
Start
Stop
Ack
Write
图8-11. I2C Write with Data
The following procedure should be followed to write data to TDP1204 I2C registers (refer to 图8-11):
1. The host initiates a write operation by generating a start condition (S), followed by the TDP1204 7-bit
address and a zero-value “W/R”bit to indicate a write cycle.
2. The TDP1204 acknowledges the address cycle.
3. The host presents the register offset within TDP1204 to be written, consisting of one byte of data, MSB-first.
4. The TDP1204 acknowledges the sub-address cycle.
5. The host presents the first byte of data to be written to the I2C register.
6. The TDP1204 acknowledges the byte transfer.
7. The host may continue presenting additional bytes of data to be written, with each byte transfer completing
with an acknowledge from the TDP1204.
8. The host terminates the write operation by generating a stop condition (P).
Data from o set 0x00
or
Target Address
last read address + 1
S
A6
A5
A4
A3
A2
A1
A0
1
A
D7
D6
D5
D4
D3
D2
D1
D0
A
P
Start
Stop
Ack
Read
图8-12. I2C Read Without Repeated Start
The following procedure should be followed to read the TDP1204 I2C registers without a repeated Start (refer to
图8-12).
1. The host initiates a read operation by generating a start condition (S), followed by the TDP1204 7-bit
address and a zero-value “W/R”bit to indicate a read cycle.
2. The TDP1204 acknowledges the 7-bit address cycle.
3. Following the acknowledge the host continues sending clock.
4. The TDP1204 transmit the contents of the memory registers MSB-first starting at register 00h or last read
register offset+1. If a write to the I2C register occurred prior to the read, then the TDP1204 shall start at the
register offset specified in the write.
5. The TDP1204 waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the host after each
byte transfer; the I2C host acknowledges reception of each data byte transfer.
6. If an ACK is received, then the TDP1204 transmits the next byte of data as long as host provides the clock. If
a NAK is received, then the TDP1204 stops providing data and waits for a stop condition (P).
7. The host terminates the write operation by generating a stop condition (P).
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Register O set Xh
Target Address
S
A6
A5
A4
A3
A2
A1
A0
0
A
C7
C6
C5
C4
C3
C2
C1
C0
A
Sr
Start
Ack
Write
Repeated Start
Data from Register Xh
Target Address
Data from Register Xh + 1
P
S
A6
A5
A4
A3
A2
A1
A0
1
A
D7
D6
D5
D4
D3
D2
D1
D0
A
D7
D6
D5
D4
D3
D2
D1
D0
A
Stop
Read
图8-13. I2C Read with Repeated Start
The following procedure should be followed to read the TDP1204 I2C registers with a repeated Start (refer to 图
8-13).
1. The host initiates a read operation by generating a start condition (S), followed by the TDP1204 7-bit
address and a zero-value “W/R”bit to indicate a write cycle.
2. The TDP1204 acknowledges the 7-bit address cycle.
3. The host presents the register offset within TDP1204 to be written, consisting of one byte of data, MSB-first.
4. The TDP1204 acknowledges the register offset cycle.
5. The host presents a repeated start condition (Sr).
6. The host initiates a read operation by generating a start condition (S), followed by the TDP1204 7-bit
address and a one-value “W/R”bit to indicate a read cycle.
7. The TDP1204 acknowledges the 7-bit address cycle.
8. The TDP1204 transmit the contents of the memory registers MSB-first starting at the register offset.
9. The TDP1204 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the host after
each byte transfer; the I2C host acknowledges reception of each data byte transfer.
10. If an ACK is received, then the TDP1204 transmits the next byte of data as long as host provides the clock. If
a NAK is received, then the TDP1204 stops providing data and waits for a stop condition (P).
11. The host terminates the read operation by generating a stop condition (P).
Register O set
Target Address
S
A6
A5
A4
A3
A2
A1
A0
0
A
C7
C6
C5
C4
C3
C2
C1
C0
A
P
Start
Ack
Write
Stop
图8-14. I2C Write Without Data
The following procedure should be followed for setting a starting sub-address for I2C reads (refer to 图8-14).
1. The host initiates a write operation by generating a start condition (S), followed by the TDP1204 7-bit
address and a zero-value “W/R”bit to indicate a write cycle.
2. The TDP1204 acknowledges the address cycle.
3. The host presents the register offset within TDP1204 to be written, consisting of one byte of data, MSB-first.
4. The TDP1204 acknowledges the register offset cycle.
5. The host terminates the write operation by generating a stop condition (P).
备注
图 8-12 that if no register offset is included for the read procedure after initial power-up, then reads
start at register offset 00h and continue byte by byte through the registers until the I2C host terminates
the read operation. During a read operation, the TDP1204 auto-increments the I2C internal register
address of the last byte transferred independent of whether or not an ACK was received from the I2C
host.
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8.5 Register Maps
8.5.1 TDP1204 Registers
表 8-23 lists the memory-mapped registers for the TDP1204 registers. All register offset addresses not listed in
表8-23 should be considered as reserved locations and the register contents should not be modified.
表8-23. TDP1204 Registers
Offset Acronym
Register Name
Section
节8.5.1.1
节8.5.1.2
节8.5.1.3
节8.5.1.4
8h
9h
Ah
Bh
REV_ID
Revision ID
PD_RST
Power Down and Reset control
Misc Control
MISC_CONTROL
GBL_SLEW_CTRL
Global TX Slew control for data lanes in
HDMI1.4 and 2.0
Ch
Dh
GBL_SLEW_CTRL2
GBL_CTRL1
Global TX Slew control for data and clock
Global control
节8.5.1.5
节8.5.1.6
Eh
GBL_CTLE_CTRL
DDC_CFG
Global CTLE control
节8.5.1.7
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Ch
1Dh
1Eh
20h
31h
35h
41h
42h
50h
51h
DDC Buffer controls
节8.5.1.8
LANE_ENABLE
CLK_CONFIG1
CLK_CONFIG2
D0_CONFIG1
Lane enables
节8.5.1.9
CLK lane TX swing and FFE control
CLK lane RX EQ control
D0 lane TX swing and FFE control
D0 lane RX EQ control
节8.5.1.10
节8.5.1.11
节8.5.1.12
节8.5.1.13
节8.5.1.14
节8.5.1.15
节8.5.1.16
节8.5.1.17
节8.5.1.18
节8.5.1.19
节8.5.1.20
节8.5.1.21
节8.5.1.22
节8.5.1.23
节8.5.1.24
节8.5.1.25
节8.5.1.26
节8.5.1.27
节8.5.1.28
D0_CONFIG2
D1_CONFIG1
D1 lane TX swing and FFE control
D1 lane RX EQ control
D1_CONFIG2
D2_CONFIG1
D2 lane TX swing and FFE control
D2 lane RX EQ control
D2_CONFIG2
SIGDET_TH_CFG
GBL_STATUS
SIGDET voltage threshold control
Global Powerdown and Standby Status
Adaptive EQ control1
AEQ_CONTROL1
AEQ_CONTROL2
SCDC_TMDS_CONFIG
SCDC_SINK_CONFIG
SCDC_SRC_TEST
SCDC_STATUS10
SCDC_STATUS32
AEQ_STATUS
Adaptive EQ control2
SCDC TMDS Clock Ratio
SCDC SNK FRL FFE and Rate
SCDC Test
Lanes 0 and 1 FRL Training Status
Lanes 2 and 3 FRL Training Status
Adaptive EQ Status
AEQ_STATUS2
Adaptive EQ Status
Complex bit access types are encoded to fit into small table cells. 表 8-24 shows the codes that are used for
access types in this section.
表8-24. TDP1204 Access Type Codes
Access Type
Code
Description
Read Type
H
H
R
Set or cleared by hardware
Read
R
RH
R
H
Read
Set or cleared by hardware
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表8-24. TDP1204 Access Type Codes (continued)
Access Type
Write Type
W
Code
Description
W
Write
W1S
W
Write
1S
1 to set
WtoP
W
Write
Reset or Default Value
-n
Value after reset or the default
value
8.5.1.1 REV_ID Register (Offset = 8h) [Reset = 03h]
REV_ID is shown in 表8-25.
Return to the 表8-23.
表8-25. REV_ID Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
REV_ID
RH
3h
Device revision.
8.5.1.2 PD_RST Register (Offset = 9h) [Reset = 01h]
PD_RST is shown in 表8-26.
Return to the 表8-23.
表8-26. PD_RST Register Field Descriptions
Bit
7
Field
Type
Reset
Description
SOFT_RST
SCDC_SOFT_RST
HWtoP
HWtoP
0h
Writing a 1 to this field resets all fields
6
0h
Writing a 1 to this field resets the fields in the SCDC registers 20h,
31h, 35h, 41h and 42h.
5
4
3
2
RESERVED
RESERVED
RESERVED
R
0h
0h
0h
0h
Reserved
Reserved
Reserved
R/W
R
HPD_PWRDWN_DISABL R/W
E
Mode to ignore HPD pin and always enter active state unless
PD_EN is high
0h = Automatically enter power down based on HPD_IN
1h = Always remain in active state or Standby
1
0
STANDBY_DISABLE
R/W
R/W
0h
1h
When high, standby mode is disabled and the device will
immediately enter active mode with all lanes enabled when not in
power down. When low, the device will enter standby mode when
exiting power down and wait for incoming data before entering active
mode.
0h = Standby mode enabled
1h = Standby mode disabled
PD_EN
I2C power down. Software should clear this field after it has
completed initialization. HPD_OUT will be asserted low when this
field is set.
0h = Normal operation
1h = Forced power down by I2C
8.5.1.3 MISC_CONTROL Register (Offset = Ah) [Reset = 08h]
MISC_CONTROL is shown in 表8-27.
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Return to the 表8-23.
表8-27. MISC_CONTROL Register Field Descriptions
Bit
Field
Type
Reset
Description
7
LANE_SWAP
R/W
0h
This field swaps the input and output lanes.
0h = No lanes swapped
1h = Both input and output lanes swapped
6
5
RESERVED
R/W
R/W
0h
0h
Reserved
RX_TERM_DISABLE
When set will disable Rx termination.
0h = Enabled when HPD_IN high.
1h = Disable
4
3
HPD_OUT_SEL
R/W
R/W
0h
1h
Selects whether HPD_OUT is push/pull or open-drain.
0h = Push Pull
1h = Open Drain
EQ_SNOOP_CTRL
Control whether Rx EQ is adjusted in response to snooped TXFFE
when TXFFE snooping is enabled through registers 41h and 42h.
0h = Rx EQ automatically adjusted for TXFFE
1h = Rx EQ is fixed
2
RATE_SNOOP_CTRL
TXFFE_SNOOP_CTRL
R/W
R/W
0h
0h
Control snooping of HDMI rates. When snooping is disabled, correct
HDMI rate must be written through I2C to registers 20h and 31h.
0h = Snooping enabled
1h = Snooping disabled
1-0
Control snooping of TXFFE
0h = DDC snooping through registers 35h, 41h and 42h
1h = DDC snooping disabled. TXFFE controlled through I2C writes to
35h, 41h and 42h
2h = DDC snooping disabled. TXFFE controlled through writes to
CLK_TXFFE, D0_TXFFE, D1_TXFFE, and D2_TXFFE
3h = DDC snooping disabled. TXFFE controlled through writes to
CLK_TXFFE, D0_TXFFE, D1_TXFFE, and D2_TXFFE
8.5.1.4 GBL_SLEW_CTRL Register (Offset = Bh) [Reset = 34h]
GBL_SLEW_CTRL is shown in 表8-28.
Return to the 表8-23.
表8-28. GBL_SLEW_CTRL Register Field Descriptions
Bit
7
Field
Type
Reset
Description
RESERVED
SLEW_3G
R
0h
Reserved
6-4
R/W
3h
Field controls slew rate for HDMI 1.4 data lane and HDMI 2.1 3 Gbps
FRL data lanes.
0h = slowest edge rate
7h = fastest edge rate
3
RESERVED
SLEW_6G
R
0h
4h
Reserved
2-0
R/W
Field controls slew rate for HDMI 2.0 data lanes and HDMI 2.1 6
Gbps FRL data lanes.
0h = slowest edge rate
7h = fastest edge rate
8.5.1.5 GBL_SLEW_CTRL2 Register (Offset = Ch) [Reset = 71h]
GBL_SLEW_CTRL2 is shown in 表8-29.
Return to the 表8-23.
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表8-29. GBL_SLEW_CTRL2 Register Field Descriptions
Bit
7
Field
Type
Reset
Description
RESERVED
SLEW_8G10G12G
R
0h
Reserved
6-4
R/W
7h
Field controls slew rate for data lanes for 8 Gbps, 10 Gbps and 12
Gbps FRL datarates
0h = slowest edge rate
7h = fastest edge rate
3
RESERVED
SLEW_CLK
R
0h
1h
Reserved
2-0
R/W
Field control slew rate of clock lane in HDMI 1.4b and HDMI 2.0
modes.
0h = slowest edge rate
7h = fastest edge rate
8.5.1.6 GBL_CTRL1 Register (Offset = Dh) [Reset = 22h]
GBL_CTRL1 is shown in 表8-30.
Return to the 表8-23.
表8-30. GBL_CTRL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
GLOBAL_LINR_EN
R/W
0h
Global control for selecting between linear redriver or limited redriver.
0h = Limited
1h = Linear
6
5-4
3
TX_AC_EN
R/W
R/W
0h
2h
0h
Controls selection of ac-coupled or dc-coupled TX termination. When
AC-coupled is enabled, 50 Ωtermination on both P and N to VCC
will be enabled.
0h = dc-coupled
1h = ac-coupled
GLOBAL_DCG
CTLE DCGain for all lane.
0h = −3 dB
1h = −3 dB
2h = 0 dB
3h = +1 dB
TXTERM_AUTO_HDMI14 R/W
Selects between no termination and 300 Ωs when TERM = 2h and
operating in HDMI1.4.
0h = No termination for clock less than or equal to 165 MHz and 300
Ωfor clock greater than 225 MHz
1h = 300 Ω
2
CTLEBYP_EN
TERM
R/W
R/W
0h
2h
Selects whether or not CTLE bypass is enabled or not when
GLOBAL_DCG is set to 2h and EQ set to 0h.
0h = CTLE bypass disabled
1h = CTLE bypass enabled
1-0
TX terminaion control
0h = No termination
1h = 300 Ω
2h = Automatic based HDMI mode
3h = 100 Ω
8.5.1.7 GBL_CTLE_CTRL Register (Offset = Eh) [Reset = 3Fh]
GBL_CTLE_CTRL is shown in 表8-31.
Return to the 表8-23.
表8-31. GBL_CTLE_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
GLOBAL_CTLEBW
R/W
0h
CTLE bandwidth control. 0 is lowest and 3h is highest.
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表8-31. GBL_CTLE_CTRL Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5-4
HDMI14_CTLE_SEL
HDMI20_CTLE_SEL
HDMI21_CTLE_SEL
R/W
3h
Selects the CTLE used when datarate is HDMI 1.4. Value
programmed into this field will apply to data lanes only. Clock lane
will always use 3 Gbps CTLE.
0h = 3 Gbps CTLE
1h = 6 Gbps CTLE
2h = Auto select based on snoop datarate
3h = 12 Gbps CTLE
3-2
1-0
R/W
R/W
3h
3h
Selects the CTLE used when datarate is HDMI 2.0. Value
programmed into this field will apply to data lanes only. Clock lane
will always use 3 Gbps CTLE.
0h = 3 Gbps CTLE
1h = 6 Gbps CTLE
2h = Auto select based on snoop datarate
3h = 12 Gbps CTLE
Selects the CTLE used when datarate is HDMI 2.1. Value
programmed into this field will apply to all four lanes.
0h = 3 Gbps CTLE
1h = 6 Gbps CTLE
2h = Auto select based on snoop datarate
3h = 12 Gbps CTLE
8.5.1.8 DDC_CFG Register (Offset = 10h) [Reset = 02h]
DDC_CFG is shown in 表8-32.
Return to the 表8-23.
表8-32. DDC_CFG Register Field Descriptions
Bit
7-2
1
Field
Type
Reset
Description
RESERVED
DDC_LV_DCC_EN
R
0h
Reserved
R/W
1h
Controls whether duty cycle correction is enabled for DDC LV side.
0h = DCC disabled
1h = DCC enabled
0
DDCBUF_EN
R/W
0h
Controls whether or not DDC buffer is enabled. Regardless of the
state of this field, the device will always disable the DDC buffer
anytime HPD_IN is low or when PD_EN field is 1.
0h = DDC Buffer Disabled
1h = DDC Buffer Enabled
8.5.1.9 LANE_ENABLE Register (Offset = 11h) [Reset = 5Fh]
LANE_ENABLE is shown in 表8-33.
Return to the 表8-23.
表8-33. LANE_ENABLE Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
HDMI20_VOD
R/W
1h
VOD control for limited redriver in HDMI 2.0
0h = Use values in CLK_VOD, D0_VOD, D1_VOD and D2_VOD
1h = Default (1000 mV)
2h = Default − 5%
3h = Default + 5%
5-4
HDMI14_VOD
R/W
1h
VOD control for limited redriver in HDMI 1.4
0h = Use values in CLK_VOD, D0_VOD, D1_VOD and D2_VOD
1h = Default (1000 mV)
2h = Default − 5%
3h = Default − 10%
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表8-33. LANE_ENABLE Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3
CLK_LANE_EN
R/W
1h
Enable for CLK lane
0h = Disabled
1h = Enabled
2
1
0
D0_LANE_EN
D1_LANE_EN
D2_LANE_EN
R/W
R/W
R/W
1h
1h
1h
Enable for D0 lane
0h = Disabled
1h = Enabled
Enable for D0 lane
0h = Disabled
1h = Enabled
Enable for D0 lane
0h = Disabled
1h = Enabled
8.5.1.10 CLK_CONFIG1 Register (Offset = 12h) [Reset = 03h]
CLK_CONFIG1 is shown in 表8-34.
Return to the 表8-23.
表8-34. CLK_CONFIG1 Register Field Descriptions
Bit
7
Field
Type
Reset
Description
RESERVED
CLK_TXFFE
R
0h
Reserved
6-4
R/W
0h
TXFFE control for CLK lane. This field is only honored in HDMI 2.1.
0h = 0.0 dB
1h = 3.5 dB
2h = 6.0 dB
3h = Reserved
4h = −1.5 dB
5h = −2.5 dB
6h = −3.5 dB
7h = −4.8 dB
3
RESERVED
CLK_VOD
R
0h
3h
Reserved
2-0
R/W
Differential Swing control for CLK lane.
0h = Limited −15% Linear 800 mV
1h = Limited −10% Linear 900 mV
2h = Limited − 5% Linear 1000 mV
3h = Limited 800 mV Linear 1200 mV
4h = Limited +5% Linear Reserved
5h = Limited +10% Linear Reserved
6h = Limited +15% Linear Reserved
7h = Limited +20% Linear Reserved
8.5.1.11 CLK_CONFIG2 Register (Offset = 13h) [Reset = 00h]
CLK_CONFIG2 is shown in 表8-35.
Return to the 表8-23.
表8-35. CLK_CONFIG2 Register Field Descriptions
Bit
7-4
3-0
Field
Type
Reset
Description
RESERVED
CLK_EQ
R
0h
Reserved
R/W
0h
EQ control for CLK lane. This field is only honored in HDMI 2.1.
0h = Min EQ
Fh = Max EQ
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8.5.1.12 D0_CONFIG1 Register (Offset = 14h) [Reset = 03h]
D0_CONFIG1 is shown in 表8-36.
Return to the 表8-23.
表8-36. D0_CONFIG1 Register Field Descriptions
Bit
7
Field
Type
Reset
Description
RESERVED
D0_TXFFE
R
0h
Reserved
6-4
R/W
0h
TXFFE control for D0 lane.
0h = 0.0 dB
1h = 3.5 dB
2h = 6.0 dB
3h = Reserved
4h = −1.5 dB
5h = −2.5 dB
6h = −3.5 dB
7h = −4.8 dB
3
RESERVED
D0_VOD
R
0h
3h
Reserved
2-0
R/W
Differential Swing control for D0 lane.
0h = Limited −15% Linear 800 mV
1h = Limited −10% Linear 900 mV
2h = Limited - 5% Linear 1000 mV
3h = Limited 1000 mV Linear 1200 mV
4h = Limited +5% Linear Reserved
5h = Limited +10% Linear Reserved
6h = Limited +15% Linear Reserved
7h = Limited +20% Linear Reserved
8.5.1.13 D0_CONFIG2 Register (Offset = 15h) [Reset = 00h]
D0_CONFIG2 is shown in 表8-37.
Return to the 表8-23.
表8-37. D0_CONFIG2 Register Field Descriptions
Bit
7-4
3-0
Field
Type
Reset
Description
RESERVED
D0_EQ
R
0h
Reserved
R/W
0h
EQ control for D0 lane.
0h = Min EQ
Fh = Max EQ
8.5.1.14 D1_CONFIG1 Register (Offset = 16h) [Reset = 03h]
D1_CONFIG1 is shown in 表8-38.
Return to the 表8-23.
表8-38. D1_CONFIG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R
0h
Reserved
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表8-38. D1_CONFIG1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
6-4
D1_TXFFE
R/W
0h
TXFFE control for D1 lane.
0h = 0.0 dB
1h = 3.5 dB
2h = 6.0 dB
3h = Reserved
4h = −1.5 dB
5h = −2.5 dB
6h = −3.5 dB
7h = −4.8 dB
3
RESERVED
D1_VOD
R
0h
3h
Reserved
2-0
R/W
Differential Swing control for D1 lane.
0h = Limited −15% Linear 800 mV
1h = Limited −10% Linear 900 mV
2h = Limited − 5% Linear 1000 mV
3h = Limited 1000 mV Linear 1200 mV
4h = Limited +5% Linear Reserved
5h = Limited +10% Linear Reserved
6h = Limited +15% Linear Reserved
7h = Limited +20% Linear Reserved
8.5.1.15 D1_CONFIG2 Register (Offset = 17h) [Reset = 00h]
D1_CONFIG2 is shown in 表8-39.
Return to the 表8-23.
表8-39. D1_CONFIG2 Register Field Descriptions
Bit
7-4
3-0
Field
Type
Reset
Description
RESERVED
D1_EQ
R
0h
Reserved
R/W
0h
EQ control for D1 lane
0h = Min EQ
Fh = Max EQ
8.5.1.16 D2_CONFIG1 Register (Offset = 18h) [Reset = 03h]
D2_CONFIG1 is shown in 表8-40.
Return to the 表8-23.
表8-40. D2_CONFIG1 Register Field Descriptions
Bit
7
Field
Type
Reset
Description
RESERVED
D2_TXFFE
R
0h
Reserved
6-4
R/W
0h
TXFFE control for D2 lane
0h = 0.0 dB
1h = 3.5 dB
2h = 6.0 dB
3h = Reserved
4h = −1.5 dB
5h = −2.5 dB
6h = −3.5 dB
7h = −4.8 dB
3
RESERVED
R
0h
Reserved
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表8-40. D2_CONFIG1 Register Field Descriptions (continued)
Bit
Field
D2_VOD
Type
Reset
Description
2-0
R/W
3h
Differential Swing control for D2 lane.
0h = Limited −15% Linear 800 mV
1h = Limited -10% Linear 900 mV
2h = Limited - 5% Linear 1000 mV
3h = Limited 1000 mV Linear 1200 mV
4h = Limited +5% Linear Reserved
5h = Limited +10% Linear Reserved
6h = Limited +15% Linear Reserved
7h = Limited +20% Linear Reserved
8.5.1.17 D2_CONFIG2 Register (Offset = 19h) [Reset = 00h]
D2_CONFIG2 is shown in 表8-41.
Return to the 表8-23.
表8-41. D2_CONFIG2 Register Field Descriptions
Bit
7-4
3-0
Field
Type
Reset
Description
RESERVED
D2_EQ
R
0h
Reserved
R/W
0h
EQ control for D2 lane.
0h = Min EQ
Fh = Max EQ
8.5.1.18 SIGDET_TH_CFG Register (Offset = 1Ah) [Reset = 44h]
SIGDET_TH_CFG is shown in 表8-42.
Return to the 表8-23.
表8-42. SIGDET_TH_CFG Register Field Descriptions
Bit
7
Field
Type
Reset
Description
RESERVED
CFG_SIGDET_HYST
R
0h
Reserved
6-4
R/W
4h
Controls the SIGDET hysteresis. Value programmed into this field
plus value programmed into CFG_SIGDET_VTH field defines the
SIGDET assert threshold.
0h = 0 mV
1h = 12 mV
2h = 25 mV
3h = 37 mV
4h = 55 mV
5h = 63 mV
6h = 75 mV
7h = 90 mV
3
RESERVED
R
0h
4h
Reserved
2-0
CFG_SIGDET_VTH
R/W
Controls the SIGDET de-assert voltage threshold.
0h = 58 mV
1h = 60 mV
2h = 72 mV
3h = 84 mV
4h = 95 mV
5h = 108 mV
6h = 120 mV
7h = 135 mV
8.5.1.19 GBL_STATUS Register (Offset = 1Ch) [Reset = 00h]
GBL_STATUS is shown in 表8-43.
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Return to the 表8-23.
表8-43. GBL_STATUS Register Field Descriptions
Bit
7
Field
Type
RH
RH
R
Reset
Description
PD_STATUS
STANDBY_STATUS
RESERVED
0h
Power Down status
Standby Status
Reserved
6
0h
5-0
0h
8.5.1.20 AEQ_CONTROL1 Register (Offset = 1Dh) [Reset = F3h]
AEQ_CONTROL1 is shown in 表8-44.
Return to the 表8-23.
表8-44. AEQ_CONTROL1 Register Field Descriptions
Bit
7-4
3-2
Field
Type
Reset
Description
FULLAEQ_UPPER_EQ
AEQ_PATTERN_CTRL
R/W
Fh
Maximum EQ value to check for full AEQ mode
R/W
0h
Control how link training pattern snooping for EQ adaptation
0h = Require a read of pattern register 41h/42h after a rate change.
Allow eq adaptation for patterns 0, 5, 6, 7, and 8.
1h = Require a read of pattern register 41h/42h after a rate change.
Allow eq adaptation for patterns 5, 6, 7, and 8.
2h = Allow eq adaptation for patterns 0, 5, 6, 7, and 8. No need for
read after rate change
3h = Allow eq adaptation for patterns 5, 6, 7, and 8. No need for read
after rate change.
1
0
AEQ_START_CTRL
AEQ_TX_DELAY_EN
R/W
R/W
1h
1h
Control whether starts based on signal detect or both signal detect
and FLT_UPDATE cleared
0h = Only require signal detect
1h = Require signal detect and clearing of FLT_UPDATE
Control whether TX remains disabled during EQ adaptation
0h = TX active during adaptation
1h = TX disabled during adaptation
8.5.1.21 AEQ_CONTROL2 Register (Offset = 1Eh) [Reset = 00h]
AEQ_CONTROL2 is shown in 表8-45.
Return to the 表8-23.
表8-45. AEQ_CONTROL2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
AEQ_MODE
R/W
0h
Selects between two Adaption modes
0h = AEQ with hits counted at mideye for every EQ.
1h = AEQ with hits counted at mideye only for EQ equal 0.
6
AEQ_EN
R/W
0h
Controls whether or not adaptive EQ is enabled.
0h = AEQ disabled
1h = AEQ enabled
5-4
3
RESERVED
R/W
R/W
0h
0h
Reserved
OVER_EQ_SIGN
Selects the sign for OVER_EQ_CTRL field.
0h = positive
1h = negative
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表8-45. AEQ_CONTROL2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2-0
OVER_EQ_CTRL
R/W
0h
This field will increase or decrease the AEQ by value programmed
into this field. For example, full AEQ value is 6 and this field is
programmed to 2 and OVER_EQ_SIGN = 0, then EQ value used will
be 8. This field is only used in Full AEQ mode.
0h = 0 or −8
1h = 1 or −7
2h = 2 or −6
3h = 3 or −5
4h = 4 or −4
5h = 5 or −3
6h = 6 or −2
7h = 7 or −1
8.5.1.22 SCDC_TMDS_CONFIG Register (Offset = 20h) [Reset = 00h]
SCDC_TMDS_CONFIG is shown in 表8-46.
Return to the 表8-23.
表8-46. SCDC_TMDS_CONFIG Register Field Descriptions
Bit
7-2
1
Field
Type
Reset
Description
RESERVED
TMDS_CLK_RATIO
R
0h
Reserved
RH/W
0h
TMDS Bit Period to TMDS Clock Period Ratio. Reads last value
snooped through DDC read/write or I2C write.
0h = 1/10 (HDMI 1.4b)
1h = 1/40 (HDMI 2.0)
0
RESERVED
R
0h
Reserved
8.5.1.23 SCDC_SINK_CONFIG Register (Offset = 31h) [Reset = 00h]
SCDC_SINK_CONFIG is shown in 表8-47.
Return to the 表8-23.
表8-47. SCDC_SINK_CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
FFE_LEVELS
RH/W
0h
Indicates the maximum TXFFE level supported for the current FRL
rate. Read last value snooped through DDC read/write or I2C write.
0h = Only TXFFE0 supported
1h = TXFFE0-1 supported
2h = TXFFE0-2 supported
3h = TXFFE0-3 supported
3-0
FRL_RATE
RH/W
0h
Selects FRL rate and lane count. Read last value snooped through
DDC read/write or I2C write.
0h = Disable FRL
1h = 3 Gbps on 3 lanes
2h = 6 Gbps on 3 lanes
3h = 6 Gbps on 4 lanes
4h = 8 Gbps on 4 lanes
5h = 10 Gbps on 4 lanes
6h = 12 Gbps on 4 lanes
8.5.1.24 SCDC_SRC_TEST Register (Offset = 35h) [Reset = 00h]
SCDC_SRC_TEST is shown in 表8-48.
Return to the 表8-23.
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表8-48. SCDC_SRC_TEST Register Field Descriptions
Bit
7-6
5
Field
Type
Reset
Description
RESERVED
FLT_NO_TIMEOUT
R
0h
Reserved
RH/W
0h
Set by sink test equipment to have source not time out during FRL
link training
0h = Normal operation
1h = Source does not timeout
4
3
RESERVED
TX_NO_FFE
R
0h
0h
Reserved
RH/W
Test mode to disable FFE. Read last value snooped through DDC
read/write or I2C write.
0h = Normal TXFFE
1h = TX sent with no FFE
2
1
0
TX_DEEMPH_ONLY
TX_PRESHOOT_ONLY
RESERVED
RH/W
RH/W
R
0h
0h
0h
Test mode to enable de-emphasis only. Read last value snooped
through DDC read/write or I2C write.
0h = Normal TXFFE
1h = TX sent de-emphasis only
Test mode to enable pre-shoot only. Read last value snooped
through DDC read/write or I2C write.
0h = Normal TXFFE
1h = TX sent with pre-shoot only
Reserved
8.5.1.25 SCDC_STATUS10 Register (Offset = 41h) [Reset = 00h]
SCDC_STATUS10 is shown in 表8-49.
Return to the 表8-23.
表8-49. SCDC_STATUS10 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
LN1_LTP_REQ
RH/W
0h
Link training pattern request for lane 1. Reads last value read
through DDC or written through I2C. A DDC read/I2C write of Eh
advances the current FFE level for this lane saturating at the value of
FFE_LEVELS. A DDC read/I2C write of Fh clears for FFE level for all
lanes to TXFFE0.
3-0
LN0_LTP_REQ
RH/W
0h
Link training pattern request for lane 0. Reads last value read
through DDC or written through I2C. A DDC read/I2C write of Eh
advances the current FFE level for this lane saturating at the value of
FFE_LEVELS. A DDC read/I2C write of Fh clears for FFE level for all
lanes to TXFFE0.
8.5.1.26 SCDC_STATUS32 Register (Offset = 42h) [Reset = 00h]
SCDC_STATUS32 is shown in 表8-50.
Return to the 表8-23.
表8-50. SCDC_STATUS32 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
LN3_LTP_REQ
RH/W
0h
Link training pattern request for lane 3. Reads last value read
through DDC or written through I2C. A DDC read/I2C write of Eh
advances the current FFE level for this lane saturating at the value of
FFE_LEVELS. A DDC read/I2C write of Fh clears for FFE level for all
lanes to TXFFE0.
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表8-50. SCDC_STATUS32 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3-0
LN2_LTP_REQ
RH/W
0h
Link training pattern request for lane 2. Reads last value read
through DDC or written through I2C. A DDC read/I2C write of Eh
advances the current FFE level for this lane saturating at the value of
FFE_LEVELS. A DDC read/I2C write of Fh clears for FFE level for all
lanes to TXFFE0.
8.5.1.27 AEQ_STATUS Register (Offset = 50h) [Reset = 80h]
AEQ_STATUS is shown in 表8-51.
Return to the 表8-23.
表8-51. AEQ_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7
AEQDONE_STAT
RH
1h
This field is low while AEQ is active and high when it is done. It is
valid when FRL training and AEQ_EN = 1 or when
FORCE_AEQ_EN = 1 and HW has reset FORCE_AEQ back to 0.
0h = AEQ is running
1h = AEQ is done
6
5
AEQ_HC_OVERFLOW
RESERVED
RH
R
0h
0h
0h
0h
13-bit AEQ hit counter overflow status
Reserved
4
RXD1_DONE_STAT
RXD1_AEQ_STAT
RH
RH
This flag is set after DAC wait timer expires.
3-0
Optimal EQ determined by FSM after the completion of Full AEQ.
This field will include the value programmed into OVER_EQ_CTRL
field.
8.5.1.28 AEQ_STATUS2 Register (Offset = 51h) [Reset = 00h]
AEQ_STATUS2 is shown in 表8-52.
Return to the 表8-23.
表8-52. AEQ_STATUS2 Register Field Descriptions
Bit
7
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
6-4
3-0
VOD_RANGE_STAT
AEQ_EYE_STAT
RH
RH
0h
0h
VOD range selected by the last AEQ run
EYE status from the last AEQ run. Relative to the maximum limit of
15.
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
TDP1204 is designed to accept AC or DC-coupled HDMI input signals. The device provides signal conditioning
and level shifting functions to drive a compliant HDMI source connector. The device can be used in an HDMI
sink application such as monitor or TV. The TDP1204 can also be used as an DP/HDMI redriver in an embedded
application. In many major PC or gaming systems APU/GPU will provide AC-coupled HDMI signals. TDP1204 is
suitable for such platforms.
9.1 Application Information
The TDP1204 is designed to work in source applications such as Blu-ray™ DVD player, gaming system,
desktops, notebooks, or audio video receivers (AVR) and in sink applications such as TV or monitors. The
following sections provide design considerations for various types of applications.
9.2 Typical Source-Side Application
图9-1 provides a schematic representation of what is considered a standard source implementation.
B
D
C
A
LCD
LAB
Op onal
CAC-RX
Op onal
Op onal
CAC-TX
RESD
IN_D2p
IN_D2n
OUT_D2p
OUT_D2n
OUT_D1p
OUT_D1n
IN_D1p
IN_D1n
OUT_D0p
OUT_D0n
Redriver
IN_D0p
IN_D0n
GPU
OUT_CLKp
OUT_CLKn
IN_CLKp
IN_CLKn
LCAP-RX
LCAP-TX
LR_ESD
LESD
图9-1. TDP1204 in Source Side Application
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9.2.1 Design Requirements
The TDP1204 can be designed into many different applications. In all the applications there are certain
requirements for the system to work properly. The EN pin must have a 0.1-µF capacitor to ground. The
processor can drive the EN pin, but the EN pin needs to change states (low to high) after the voltage rails have
stabilized. Using I2C is the best way to configure the device, but pin strapping is also provided as I2C and is not
available in all cases. As sources may have many different naming conventions, it is necessary to confirm that
the link between the source and the TDP1204 are correctly mapped. A Swap function is provided for the input
pins in case signaling is reversed between the source and receptacle. 表 9-1 lists information on expected
values to perform properly.
For this design example, the TDP1204 is assumed to be configured for pin-strap mode. If I2C mode is desired,
MODE pin should be set to "F" and software must configure TDP1204. For how to configure TDP1204, refer to
节8.4.1.
表9-1. Design Parameters
Design Parameter
VCC
Value
3.3-V
VIO (1.2-V, 1.8-V, or 3.3-V LVCMOS levels)
Maximum HDMI 2.1 FRL Datarate (3, 6, 8, 10, or 12-Gbps)
Pin-strap or I2C mode (if I2C, then MODE = "F").
Pin Strap Mode.(MODE = "0", "R" or "1").
1.8-V
12-Gbps
Pin-strap
Mode = "0" (Fixed EQ with DDC Buffer support)
DDC Snoop Feature. (Y/N). Required when in pin strap. Optional in
I2C mode.
Yes
SWAP function (Y / N). In pin strap mode controlled by SDA/CFG1
pin.
No. SDA/CFG1 pin = L.
DDC Level Shifter Support (Y / N)
HPD_IN to HPD_OUT Level Shifter Support (Y / N)
Pre-Channel Length (Refer to 表9-2 on length restrictions)
Post-Channel Length (Refer to 表9-2 on length restrictions)
Limited or linear redriver mode?
Yes
Yes, HPD_OUT is used. If no, then HPD_OUT can be left floating.
Length = 8 inches (≅ 7.2-dB at 6-GHz insertion loss)
Length = 2 inches (≅ 1.8-dB at 6-GHz insertion loss)
Limited redriver (LINEAR_EN pin = "0").
TX is DC or AC-coupled to HDMI receptacle?
DC-coupled. AC_EN pin = Low.
GPU Launch Voltage (500 mV to 1200 mV) if using limited redriver
mode. If using linear redriver mode, refer to 表8-4 for GPU
requirements.
500-mV
If MODE = "0" or "R", GPU's TX FFE pre-shoot and de-emphasis
levels shall be set to 0-dB for all four TXFFE levels
If MODE = "1", then GPU TXFFE pre-shoot and de-emphasis levels
shall meet 表8-4 requirements.
GPU HDMI 2.1 pre-shoot and de-emphasis levels used if using
redriver in limited mode
CTLE HDMI Datarate Map (Map A, Map B, or Map C)
Map C
EQ1 pin: "R"
ADDR/EQ0 pin: "R"
(7.5-dB)
RX EQ (16 possible values. Value chosen based on pre-channel
length).
TX Pre-emphasis. In pre-strap mode controlled by TXPRE pin.
TX Swing. In pre-strap mode controlled by TXSWG pin.
Default 0-dB of pre-emphasis. Float TXPRE pin.
Default TX swing level. Float TXSWG pin.
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表9-2. Source Layout and Component Placement Constraints
Symbol
Parameter
Condition
Min
Typ
Max
Units
External series resistor between ESD component and
TDP1204
RESD
0
2.5
Ω
(1) (2)
LAB
PCB trace length from GPU to TDP1204
At 12-Gbps
At 12-Gbps
1
10
5
inches
mil
LINTRA-AB Intra-pair skew from GPU to TDP1204
(1)
LCD
PCB trace length from TDP1204 to receptacle
0.75
2
inches
mil
LINTRA-CD Intra-pair skew from TDP1204 to receptacle
5
PCB trace length from TDP1204 to optional external
CAC-RX capacitor
LCAP-RX
0.3
0.3
inches
inches
PCB trace length from TDP1204 to optional external
CAC-TX capacitor
LCAP-TX
LESD
PCB trace length from ESD component to receptacle
PCB trace length from RESD to ESD component
0.5
0.25
1
inches
inches
inches
LR_ESD
LINTER-PAIR Inter-pair skew between all four channels (D0, D1, D2,
(3)
and CLK)
dB / inch /
GHz
ILPCB
PCB trace insertion loss
0.1
0.17
ZPCB_AB
ZPCB_CD
VIAAB
Differential impedance of LAB
75
90
110
110
2
Ω
Ω
Differential impedance of LCD
Number of vias between GPU and TDP1204
VIA
VIACD
Number of vias between HDMI connector and
TDP1204
1
VIA
Differential crosstalk between adjacent differential
pairs on PCB.
XTALK
dB
≦3 GHz
−24
(1) Maximum distance assumes PCB trace insertion loss meets ILPCB requirement. If PCB trace insertion loss exceeds the maximum limit,
then distance needs be reduced.
(2) Minimum distance assumes PCB trace insertion loss meets ILPCB requirement. If PCB trace insertion loss is less than the minimum
limit, then distance needs to be increased.
(3) Calculation of channel length is the sum of LAB and LCD
.
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9.2.2 Detailed Design Procedure
VCC (3.3 V)
VIO
10 µF
100 nF
100 nF
100 nF
100 nF
VCC (3.3 V)
Common mode
choke op onal
100 nF
GPU
CAC-RX
RESD
OUT_D2p
OUT_D2n
OUT_D1p
OUT_D1n
OUT_D0p
OUT_D0n
OUT_CLKp
OUT_CLKn
HPD_IN
D2+
IN_D2p
D2p
D2n
D2-
IN_D2n
D1+
D1-
IN_D1p
D1p
IN_D1n
D1n
D0+
D0-
IN_D0p
D0p
IN_D0n
D0n
CLK+
CLK-
HPD
SCL
IN_CLKp
IN_CLKn
HPD_OUT
LV_DDC_SCL
LV_DDC_SDA
CLKp
CLKn
HPD_OUT
HPD
HV_DDC_SCL
HV_DDC_SDA
DDC_SCL
DDC_SDA
SCL/GPIO
SDA/GPIO
GPIO
SDA
1.8-k
MODE
1.8-k
MODE
+5 V
TXPRE
TXPRE
+5 V
TXSWG
CTLEMAP_SEL
EQ1
TXSWG
CTLEMAP_SEL
EQ1
VCC (3.3 V)
DNI
VIO
AC_EN
AC_EN
LINEAR_EN
ADDR/EQ0
SCL/CFG0
SDA/CFG1
EN
DNI
SCL/CFG0
ADDR/EQ0
SCL/CFG0
SDA/CFG1
EN
LINEAR_EN
MODE
HPDOUT_SEL
HPDOUT_SEL
1-k
10-k
VCC (3.3 V)
DNI
VIO
100 nF
DNI
SDA/CFG1
redriver
HPD_OUT
220-k
TXPRE
DNI
10-k
VCC (3.3 V)
VCC (3.3 V)
DNI
VCC (3.3 V)
VCC (3.3 V)
DNI
VCC (3.3 V)
R1
VCC (3.3 V)
R3
VCC (3.3 V)
DNI
DNI
DNI
AC_EN
CTLEMAP_SEL
TXSWG
EQ1
ADDR/EQ0
HPDOUT_SEL
LINEAR_EN
DNI
1-k
DNI
R2
R4
DNI (Do Not Install)
图9-2. TDP1204 in Source Application Schematics
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9.2.2.1 Pre-Channel (LAB
)
The TDP1204 can support up to 12-dB at 6-GHz of insertion loss. The loss profile between the GPU and the
TDP1204 input (referred to the pre-channel as depicted in 图 9-1) should be less than the TDP1204 maximum
receiver equalization. 图9-3 shows the loss profile of FR4 trace at different lengths. The TDP1204 EQ0 and EQ1
pins should be configured to match the pre-channel insertion loss. 表 8-6 lists the EQ0 and EQ1 configuration
options.
The GPU transmitter differential output voltage swing must be large enough so that the TDP1204's VID(DC) and
VID(EYE) requirements are met. The VID(EYE) is the eye height after the contribution of ISI jitter only. Because a
redriver can only compensate for ISI jitter, all non-ISI sources of jitter (random, sinusoidal, and so forth) will be
passed through TDP1204. If the system designer requires the worse case channel length of 10 inches, then the
GPU transmitter differential voltage swing without de-emphasis should be at least 1000 mVpp to meet the
VID(DC) and VID(EYE) requirements of the TDP1204. A GPU transmitter, which incorporates de-emphasis, can
meet the requirement with less than 1000 mVpp.
9.2.2.2 Post-Channel (LCD
)
图 9-1 shows the post-channel, which should be 2 inches or less. If ESD devices are used, then it may be
necessary to overcome the insertion loss of the ESD device by increasing the TDP1204 transmitter voltage
swing. 表8-17 lists how this is done by configuring the TXSWG pin to the appropriate value.
If post-channel is greater than 2 inches, then transmitter pre-emphasis may need to be employed. 表 8-15 lists
how this is done by configuring the TDP1204 TXPRE pin to the appropriate setting. Adjusting the TDP1204
transmitter voltage swing may also be necessary.
9.2.2.3 Common Mode Choke
It may be necessary to incorporate a common mode choke (CMC) to reduce EMI. The purpose of a CMC is to
have a minimal impact to the differential signal while attentuating common mode noise thereby reducing radiated
emissions. The CMC should be placed between the TDP1204 and the ESD device.
表9-3. Recommended Common Mode Chokes
Manufacturer
Part Number
Murata
DLM0QSB120HY2
DLM0NSB120HY2
NFG0QHB542HS2
Murata
Murata
9.2.2.4 ESD Protection
It may be necessary to incorporate an ESD component to protect the TDP1204 from electrostatic discharge
(ESD). It is recommended that the ESD protection component has a breakdown voltage of ≥4.5 V and a clamp
voltage of ≤4.3 V. A clamp voltage greater than 4.3 V will require a RESD on each high-speed differential pin.
The ESD component should be placed near the HDMI connector.
表9-4. Recommended ESD Protection Component
Manufacturer
Part Number
NXP
PUSB3FR4
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9.2.3 Application Curves
图9-3. FR4 Trace Insertion Loss at 6 GHz
图9-4. Pre-Channel Insertion Loss at TTP2
图9-5. Post-Channel Insertion Loss at TTP4
图9-6. 12 Gbps Input Eye at TTP2 After Pre-
channel
图9-8. 12 Gbps Output Eye at TTP4_EQ After Pre
and Post Channels
图9-7. 12 Gbps Output Eye at TTP4 After Pre and
Post Channels
9.3 Typical Sink-Side Application
图9-9 provides a schematic representation of what is considered a standard sink implementation.
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A
B
C
D
LCD
LAB
RESD
Optional
CAC-TX
IN_CLKn
IN_CLKp
OUT_CLKn
OUT_CLKp
OUT_D0n
IN_D0n
IN_D0p
OUT_D0p
OUT_D1n
OUT_D1p
SINK
(Scaler)
IN_D1n
IN_D1p
Redriver
OUT_D2n
OUT_D2p
IN_D2n
IN_D2p
LR_ESD
LESD
LCAP-TX
图9-9. TDP1204 in Sink Side Application
9.3.1 Design Requirements
表9-5. Design Parameters
Design Parameter
Value
3.3-V (±5%)
1.8-V
VCC
VIO (1.2-V, 1.8-V, or 3.3-V LVCMOS levels)
Maximum HDMI 2.1 FRL Datarate (6, 8, 10, or 12-Gbps)
Pin-strap or I2C mode (if I2C, then MODE = "F").
Pin Strap Mode.(MODE = "0", "R" or "1").
12-Gbps
Pin-strap
Mode = "1" (Adaptive EQ with DDC Buffer support)
Yes
DDC Snoop Feature. (Y/N). Required when in pin strap. Optional in
I2C mode.
SWAP function (Y / N). In pin strap mode controlled by SDA/CFG1
pin.
Yes. SDA/CFG1 pin = H.
DDC Level Shifter Support (Y / N)
Yes
HPD_IN to HPD_OUT Level Shifter Support (Y / N)
Pre-Channel Length (Refer to 表9-6 on length restrictions)
Post-Channel Length (Refer to 表9-6 on length restrictions)
No, then HPD_OUT can be left floating.
Length = 1 inches; Width = 4 mil. (≅ 1-dB at 6-GHz insertion loss)
Length = 6 inches; Width = 4 mil (≅ 6-dB at 6-GHz insertion loss)
Linear redriver (LINEAR_EN pin = "F") recommended in sink
application
Limited or linear redriver mode?
TX is DC or AC-coupled to HDMI receptacle?
AC-coupled. AC_EN pin = High.
EQ1 pin: "0"
ADDR/EQ0 pin: "1"
(2.7-dB)
RX EQ (16 possible values. Value chosen based on pre-channel
length).
CTLE Map (Map A, Map B or Map C). In pre-strap controlled by
CTLEMAP_SEL pin.
For Sink application recommend Map B or C.
TX pre-emphasis. In pre-strap mode controlled by TXPRE pin. TX
pre-emphasis control not supported in linear redriver mode.
Float TXPRE pin.
TX Swing. In pre-strap mode controlled by TXSWG pin.
Default TX swing level. Float TXSWG pin.
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表9-6. Sink Layout and Component Placement Constraints
Symbol
Parameter
Condition
Min
Typ
Max
Units
External series resistor between ESD
component and TDP1204
RESD
0
2.5
Ω
PCB trace length from receptacle to
TDP1204
(1) (2)
LAB
0.75
1
2
inches
LINTRA-AB
Intra-pair skew from receptacle to TDP1204
PCB trace length from TDP1204 to sink
Intra-pair skew from TDP1204 to sink
2
6
2
mil
inches
mil
(1)
LCD
LINTRA-CD
LCAP-TX
PCB trace length from TDP1204 to external
CAC-TX capacitor
0.3
inches
inches
PCB trace length from ESD component to
receptacle
LESD
0.5
PCB trace length from RESD to ESD
component
LR_ESD
0.25
0.10
inches
inches
(3)
LINTER-PAIR
Inter-pair skew between all four channels
(D0, D1, D2, and CLK)
dB / inch /
GHz
ILPCB
PCB trace insertion loss
0.1
0.17
ZPCB_AB
ZPCB_CD
VIAAB
Differential impedance of LAB
Differential impedance of LCD
90
90
110
110
1
Ω
Ω
Number of vias between receptacle and
TDP1204
VIA
VIACD
Number of vias between sink and TDP1204
2
VIA
dB
Differential crosstalk between adjacent
differential pairs on PCB.
XTALK
≦3-GHz
−24
(1) Maximum distance assumes PCB trace insertion loss meets ILPCB requirement. If PCB trace insertion loss exceeds the maximum limit,
then distance needs to be reduced.
(2) Minimum distance assumes PCB trace insertion loss meets ILPCB requirement. If PCB trace insertion loss is less than the minimum
limit, then distance needs to be increased.
(3) Calculation of channel length is the sum of LAB and LCD
.
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9.3.2 Detailed Design Procedures
VCC (3.3 V)
VIO
VCC (3.3 V)
Op onal
100 nF
10 µF
100 nF
100 nF
100 nF
100 nF
HDMI SINK
(Scaler)
CAC-TX
RESD
D2+/FRL_D2p
D2-/FRL_D2n
D1+/FRL_D1p
D1-/FRL_D1n
D0+/FRL_D0p
D0-/FRL_D0n
CLK+/FRL_D3p
CLK-/FRL_D3p
DDC_SCL
OUT_D2p
OUT_D2n
OUT_D1p
OUT_D1n
OUT_D0p
OUT_D0n
OUT_CLKp
OUT_CLKn
D2+
D2-
IN_D2p
IN_D2n
ESD
D1+
D1-
IN_D1p
IN_D1n
D0+
D0-
IN_D0p
IN_D0n
ESD
CLK+
CLK-
SCL
IN_CLKp
IN_CLKn
HV_DDC_SCL
HV_DDC_SDA
HPD_IN
MODE
LV_DDC_SCL
LV_DDC_SDA
HPD_OUT
DDC_SDA
SDA
ESD
47-k
HPDOUT
GPIO
HPD
+5 V
1-k
SRC_PRNT
MODE
TXPRE
TXPRE
SRC_PRNT
TXSWG
TXSWG
CTLEMAP_SEL
EQ1
CTLEMAP_SEL
EQ1
VCC (3.3 V)
1-k
VIO
AC_EN
AC_EN
LINEAR_EN
ADDR/EQ0
SCL/CFG0
SDA/CFG1
EN
ADDR/EQ0
SCL/CFG0
SDA/CFG1
EN
DNI
SCL/CFG0
LINEAR_EN
HPDOUT_SEL
MODE
HPDOUT_SEL
DNI
10-k
VCC (3.3 V)
DNI
VIO
10-k
100 nF
TDP1204
TXPRE
SDA/CFG1
1-k
DNI
VCC (3.3 V)
VCC (3.3 V)
DNI
VCC (3.3 V)
VCC (3.3 V)
DNI
VCC (3.3 V)
R1
VCC (3.3 V)
VCC (3.3 V)
DNI
HPDOUT_SEL
10-k
AC_EN
DNI
R3
CTLEMAP_SEL
LINEAR_EN
TXSWG
EQ1
ADDR/EQ0
DNI
DNI
DNI
R2
R4
DNI (Do Not Install)
图9-10. TDP1204 in Sink Application Schematics
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10 Power Supply Recommendations
10.1 Supply Decoupling
Texas Instruments recommends a single bulk capacitor of 10-µF on the VCC supply. Along with the bulk
capacitor, Texas Instruments recommends a 0.1-µF decoupling capacitor on each TDP1204 VCC pin that is
placed as close to the VCC pin as possible. 图9-2 shows an example.
11 Layout
11.1 Layout Guidelines
For the TDP1204 on a high-K board, it is required to solder the PowerPAD™ onto the thermal land to ground. A
thermal land is the area of solder-tinned-copper underneath the PowerPAD package. On a high-K board, the
TDP1204 can operate over the full temperature range by soldering the PowerPAD onto the thermal land. For the
device to operate across the temperature range on a low-K board, a 1-oz Cu trace connecting the GND pins to
the thermal land must be used. A simulation shows RθJA = 30.9°C/W allowing 950-mW power dissipation at
70°C ambient temperature. A general PCB design guide for PowerPAD packages is provided in the PowerPAD
Thermally Enhanced Package application report. TI recommends using a four layer stack up at a minimum to
accomplish a low-EMI PCB design. TI recommends four layers as the TDP1204 is a single voltage rail device.
• Routing the high-speed TMDS traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects from the HDMI connectors to the Redriver inputs and
outputs. It is important to match the electrical length of these high speed traces to minimize both inter-pair
and intra-pair skew.
• Placing a solid ground plane next to the high-speed single layer establishes controlled impedance for
transmission link interconnects and provides an excellent low-inductance path for the return current flow.
• Placing a power plane next to the ground plane creates an additional high-frequency bypass capacitance.
• Routing slower seed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
• If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep symmetry. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high
frequency bypass capacitance significantly.
• To minimize crosstalk between adjacent differential pairs, the distance between the differential pairs should
be at least five times longer than the trace width (5W rule). For the clock differential pair, the distance should
be increased to 8W or 10W.
Layer 1: TMDS signal layer
Layer 1: TMDS signal layer
5 to 10
mils
Layer 2: Ground Plane
Layer 2: Ground Plane
Layer 3: VCC Power Plane
20 to 40
mils
Layer 4: VDD Power Plane
Layer 5: Ground Plane
Layer 3: Power Plane
5 to 10
mils
Layer 4: Control signal layer
Layer 6: Control signal layer
图11-1. Recommended 4 or 6-Layer PCB Stack
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11.2 Layout Example
GND
1
9
40
IN_D2p/n
OUT_D2p/n
HPD_OUT
TXSWG
IN_D1p/n
OUT_D1p/n
OUT_D0p/n
OUT_CLKp/n
VIO
ADDR/EQ0
HPD_IN
GND
IN_D0p/n
IN_CLKp/n
MODE
GND
TXPRE
20
29
VCC
GND
HV_DDC_SCL
HV_DDC_SDA
LV_DDC_SCL
LV_DDC_SDA
图11-2. Source Example Layout
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, PowerPAD Thermally Enhanced Package application report
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
HDMI™ is a trademark of HDMI Licensing Administrator, Inc..
Blu-ray™ is a trademark of Blu-ray Disc Association (BDA).
PowerPAD™ and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TDP1204IRNQR
TDP1204IRNQT
TDP1204RNQR
TDP1204RNQT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
WQFN
RNQ
RNQ
RNQ
RNQ
40
40
40
40
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
0 to 85
TDP04
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
TDP04
TDP04
TDP04
0 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Apr-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
RNQ0040A
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
B
A
PIN 1 INDEX AREA
4.1
3.9
C
0.8 MAX
SEATING PLANE
0.08
0.05
0.00
4.7±0.1
2X 4.4
(0.2) TYP
9
20
EXPOSED
THERMAL PAD
36X 0.4
8
21
2X
2.8
2.7±0.1
1
28
0.25
40X
0.15
29
40
PIN 1 ID
0.1
C A
B
0.5
0.3
(OPTIONAL)
40X
0.05
4222125/B 01/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RNQ0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(4.7)
2X (2.1)
6X (0.75)
40
29
40X (0.6)
1
28
40X (0.2)
SYMM
4X
(1.1)
(3.8)
(2.7)
36X (0.4)
8
21
(R0.05) TYP
9
20
SYMM
(5.8)
(
0.2) TYP
VIA
LAND PATTERN EXAMPLE
SCALE:15X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222125/B 01/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
RNQ0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
4X (1.5)
40
29
40X (0.6)
1
28
40X (0.2)
SYMM
6X
(0.695)
(3.8)
6X
(1.19)
36X (0.4)
8
21
(R0.05) TYP
METAL
TYP
9
20
6X (1.3)
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
73% PRINTED SOLDER COVERAGE BY AREA
SCALE:18X
4222125/B 01/2016
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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