TDP158_技术文档

TDP158

ZHCSFY1E –DECEMBER 2016 –REVISED JULY 2022

TDP158 6Gbps、交流耦合型TMDS^™或HDMI ^™电平转换器转接驱动器

1 特性

3 说明

• 交流耦合TMDS 或DisplayPort^™双模物理层输入

到HDMI2.0b TMDS 物理层输出，支持高达6Gbps

的数据速率，兼容HDMI2.0b 电气参数

• 支持DisplayPort 双模标准版本1.1

• 支持4k2k60p 和高达WUXGA 16 位色深或

1080p，刷新率更高

TDP158 器件是一款交流耦合型 HDMI 信号转最小化

传输差分信号 (TMDS) 转接驱动器，支持数字视频接

口 (DVI) 1.0 和高清多媒体接口 (HDMI) 1.4b 和 2.0b

输出信号。TDP158 支持四条 TMDS 通道和数字显示

控制 (DDC) 接口。TDP158 支持高达 6Gbps 的信号传

输速率，可实现高达4k2k60p 24 位/像素的分辨率以及

高达 WUXGA 16 位色深或 1080p，同时具有较高的刷

新率。TDP158 经配置可支持HDMI2.0 标准。

• 可编程固定接收器均衡器增益最高可达

15.5dB

• 全局或独立的高速通道控制、预加重和发送摆幅以

及转换率控制

TDP158 支持双电源轨

• I²C 或引脚搭接可编程

（V_DD为 1.1V，V_CC为 3.3V），有助于降低功耗。该

器件采用多种电源管理方法降低整体功耗。 TDP158

通过I²C 或引脚搭接支持固定接收器 EQ 增益，从而补

偿长度不同的输入电缆或电路板引线。

• 可通过I²C 配置为DisplayPort 转接驱动器

• 主通道上全通道交换

• 低功耗

器件信息⁽¹⁾

– 6Gbps 时的工作功耗为200mW，关断状态下的

功耗为8mW

• 采用40 引脚、0.4mm 间距、5mm x 5mm WQFN

封装，与SN75DP159RSB 重计时器引脚兼容

封装尺寸（标称值）

器件型号

TDP158

封装

WQFN (40)

5.00mm × 5.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

2 应用

• 笔记本电脑、台式机、一体机、平板电脑、游戏机

和工业PC

• 音频或视频设备

• Blu-ray^™DVD

• 游戏系统

• HDMI 适配器或软件狗

• 集线站

TDP158

IN_D2p/n

IN_D1p/n

IN_D0p/n

OUT_D2p/n

OUT_D1p/n

OUT_D0p/n

OUT_CLKp/n

DP++ TX

Or

AC Coupled

HDMI TX

8

5

1

TDP158

P

D

T

IN_CLKp/n

SCL_SRC

SDA_SRC

HDMI

Connector

5 V

GPU

显示

SCL_SNK

SDA_SNK

HPD_SNK

DDC

HPD

HPD_SRC

3.3 V

OE

SCL_CTL

SDA_CTL

VSADJ

I²C

简化版原理图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLLSEX2

TDP158

www.ti.com.cn

ZHCSFY1E –DECEMBER 2016 –REVISED JULY 2022

Table of Contents

8.1 Overview...................................................................19

8.2 Functional Block Diagram.........................................20

8.3 Feature Description...................................................20

8.4 Device Functional Modes..........................................27

8.5 Register Maps...........................................................28

9 Application and Implementation..................................40

9.1 Application Information............................................. 40

9.2 Typical Application.................................................... 40

10 Power Supply Recommendations..............................46

10.1 Power Management................................................46

10.2 Standby Power........................................................46

11 Layout...........................................................................47

11.1 Layout Guidelines................................................... 47

11.2 Layout Example...................................................... 48

12 Device and Documentation Support..........................49

12.1 Documentation Support.......................................... 49

12.2 接收文档更新通知................................................... 49

12.3 支持资源..................................................................49

12.4 Trademarks.............................................................49

12.5 Electrostatic Discharge Caution..............................49

12.6 术语表..................................................................... 49

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................4

6 Specifications.................................................................. 6

6.1 Absolute Maximum Ratings........................................ 6

6.2 ESD Ratings............................................................... 6

6.3 Recommended Operating Conditions.........................6

6.4 Thermal Information....................................................7

6.5 Electrical Characteristics, Power Supply.................... 8

6.6 Electrical Characteristics, Differential Input................ 9

6.7 Electrical Characteristics, TMDS Differential

Output............................................................................9

6.8 Electrical Characteristics, DDC, I2C, HPD, and

ARC...............................................................................9

6.9 Electrical Characteristics, TMDS Differential

Output in DP-Mode......................................................10

6.10 Switching Characteristics, TMDS............................10

6.11 Switching Characteristics, HPD.............................. 10

6.12 Switching Characteristics, DDC and I²C................. 11

6.13 Typical Characteristics............................................12

7 Parameter Measurement Information..........................13

8 Detailed Description......................................................19

Information.................................................................... 49

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision D (March 2020) to Revision E (July 2022)

Page

• 更新了整个文档中的表格、图和交叉引用的编号格式.........................................................................................1

• 在整个数据表中添加了包容性术语......................................................................................................................1

• Updated the TDP158 in Source Side Application figure with ESD between device and receptacle.................40

• Updated the TDP158 Source Side Application with DDC Snoop figure with ESD between device and

receptacle......................................................................................................................................................... 44

• Updated the TDP158 in Dual Role Source Side Application figure with ESD between device and receptacle....

45

Changes from Revision C (October 2019) to Revision D (March 2020)

Page

• 将HDMI 2.0a 更改为HDMI 2.0b........................................................................................................................1

Changes from Revision B (June 2017) to Revision C (October 2019)

Page

• 删除了特性：面向商业和工业应用的扩展温度器件选项..................................................................................... 1

• 更改了特性：从“与SN65DP159RSB 和SN75DP159RSB 重计时器引脚兼容”更改为“与SN75DP159RSB

重计时器引脚兼容”........................................................................................................................................... 1

• 从器件信息表中删除了TDP158I........................................................................................................................1

• Changed the T_JMIN value From: –40°C To: 0°C in the Recommended Operating Conditions table...............6

• Deleted T_Afor TDP158I in the Recommended Operating Conditions table....................................................... 6

• Changed the last sentence of the Overview section to remove the TDP158I device.......................................19

Changes from Revision A (January 2017) to Revision B (June 2017)

Page

• 将标题从“HDMI™ 转接驱动器”更改为“HDMI™ 电平转换器转接驱动器”...................................................1

2

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• 更改了特性列表..................................................................................................................................................1

• 更改了应用列表..................................................................................................................................................1

• Added text to pins 17, 23, 34, 16 in the Pin Functions table: "For pin control, Low = 1 kΩpulldown resistor to

GND, High = 1 kΩpullup resistor to VCC, NC = Floating" ................................................................................4

• Added text to pin NC in the Pin Functions table: "Optionally connect 0.1 μF to GND to reduce noise"............4

• V_SADJ: Added Note "Reducing resistor ..", and Changed values in the Recommended Operating Conditions

table....................................................................................................................................................................6

• Changed Rvsdj max value to 8 kΩin 图6-1 ...................................................................................................12

• Changed the paragraph in the Operation Timing section.................................................................................21

• Added column Pin Number to 表8-2, Changed IN_CLK →OUT_CLK To: IN_D2 →OUT_D2 in the last row of

the SWAP column.............................................................................................................................................22

• Changed Note 1 of 表8-3 ................................................................................................................................23

• Changed the last two sentences of the paragraph in the pre-emphasis section.............................................. 26

• Changed the title of 图8-6 From: 3.5 dB pre-emphasis in Normal Operation To: 6 dB pre-emphasis Setting in

Normal Operation............................................................................................................................................. 26

• Changed From: Reg0Ch[1:0] = 01 To: Reg0Ch[1:0] = 10 in 图8-7 .................................................................26

• Changed the Default setting in 表8-9 From: TBD To: 00000001..................................................................... 30

• Added paragraph to the Application and Implementation section: "TDP158 is designed ..."........................... 40

• Changed the Application Information paragraph.............................................................................................. 40

• Changed From: 0 Ωresistors To: 1 kΩresistors, and a noise filter (capacitor) for the no connect in 图9-1 ....

40

• Added text "1 kΩpulldown resistor " to the Connect values in 表9-1 ............................................................ 41

• Changed text in the second paragraph of the Source Side HDMI Application section From: "Control pins can

be tied directly to VCC, GND or left floating." To: "Control pins should be tied to 1 kΩpullup to VCC, 1 kΩ

pulldown to GND, or left floating.".....................................................................................................................44

• Changed From: 0 Ωresistors To: 1 kΩresistors, and a noise filter (capacitor) for the no connect in 图9-5 ....

44

• Changed From: 0 Ωresistors To: 1 kΩresistors, and a noise filter (capacitor) for the no connect in 图9-6 ....

45

• Changed From: 0 Ωresistors To: 1 kΩresistors, and a noise filter (capacitor) for the no connect in 图11-2 ...

48

Changes from Revision * (December 2016) to Revision A (January 2017)

Page

• 将“预览”更改为量产数据.................................................................................................................................1

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ZHCSFY1E –DECEMBER 2016 –REVISED JULY 2022

5 Pin Configuration and Functions

IN_D2p/n

HPD_SRC

IN_D1p/n

IN_D0p/n

I2C_EN

1

2

3

4

5

6

7

8

9

10

30

29

28

27

26

25

24

23

22

21

OUT_D2n/p

HPD_SNK

OUT_D1n/p

OUT_D0n/p

A1/EQ2

GND

IN_CLKp/n

OUT_CLKn/p

Not to scale

图5-1. RSB Package, 40-Pin WQFN (Top View)

表5-1. Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

SUPPLY AND GROUND PINS

3.3 V Power Supply

VCC

VDD

11, 37

P

12,20,31,40

1.1 V Power Supply

15, 35

Thermal Pad

GND

G

Ground

MAIN LINK INPUT PINS

Channel 2 Differential Input

Channel 1 Differential Input

Channel 0 Differential Input

Clock Differential Input

IN_D2p/n

IN_D1p/n

IN_D0p/n

IN_CLKp/n

1, 2

4, 5

I

6, 7

9, 10

MAIN LINK OUTPUT PINS (FAIL SAFE)

TMDS Data 2 Differential Output

TMDS Data 1 Differential Output

TMDS Data 0 Differential Output

TMDS Data Clock Differential Output

OUT_D2n/p

OUT_D1n/p

OUT_D0n/p

OUT_CLKn/p

29, 30

26, 27

24, 25

21, 22

O

4

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ZHCSFY1E –DECEMBER 2016 –REVISED JULY 2022

表5-1. Pin Functions (continued)

TYPE⁽¹⁾

DESCRIPTION

NO.

HOT PLUG DETECT AND DDC PINS

HPD_SRC

HPD_SNK

SDA_SNK

SCL_SNK

SDA_SRC

SCL_SRC

3

O

I

Hot Plug Detect Output to source side

Hot Plug Detect Input from sink side

Sink Side Bidirectional DDC Data Line

Sink Side Bidirectional DDC Clock Line

Source Side Bidirectional DDC Data Line

Source Side Bidirectional DDC Clock Line

CONTROL PINS

28

33

32

39

38

I/O

Operation Enable/Reset Pin

OE = L: Power Down Mode

OE = H: Normal Operation

Internal weak pullup: Resets device when transitions from H to L

OE

36

8

I

I2C_EN = High; Puts Device into I2C Control Mode

I2C_EN = Low; Puts Device into Pin Strap Mode

I2C_EN

I2C Data Signal: When I2C_EN = High;

Pre-emphasis: When I2C_EN = Low: See 节8.3.11

DE = L: None 0 dB

SDA_CTL/PRE

14

I/0

DE = H: 3.5 dB

I2C Clock Signal: When I2C_EN = High;

Lane SWAP: When I2C_EN = Low: See 节8.3.4 HDMI Mode Only

SWAP = L: Normal Operation

SCL_CTL/SWAP

VSADJ

13

18

17

I

SWAP = H: Lane Swap

TMDS Compliant Voltage Swing Control (Nominal 6 kΩ for HDMI and DP combination;

6.49 kΩ for HDMI only)

Address Bit 1 for I2C Programming when I2C_EN = High

I

EQ1 Pin Setting when I2C_EN = Low; Works in conjunction with A1/EQ2; See 节8.3.5

for settings. For pin control, Low = 1 kΩpulldown resistor to GND, High = 1 kΩpullup

resistor to VCC, NC = Floating.

A0/EQ1

3 Level

Address Bit 2 for I2C Programming when I2C_EN = High

I

EQ2 Pin Setting when I2C_EN = Low; Works in conjunction with A0/EQ1; See 节8.3.5

for settings. For pin control, Low = 1 kΩpulldown resistor to GND, High = 1 kΩpullup

resistor to VCC, NC = Floating.

A1/EQ2

SLEW

23

34

3 Level

Clock Slew Rate Control: See 节8.3.10

SLEW = L: Slowest ≅ 203 ps

SLEW = NC (Default): Mid-range 1 ≅ 180 ps

SLEW = H: Fastest ≅ 122 ps

I

3 Level

For pin control, L = 1 kΩpulldown resistor to GND, H = 1 kΩpullup resistor to VCC, NC

= Floating.

Source Termination Cotnrol: See 节8.3.8

TERM = H, 75 Ω ≅ 150 Ω

TERM = L, Transmit Termination impedance in 150 Ω ≅ 300 Ω

TERM = NC, No transmit Termination

I

TERM

NC

16

19

3 Level

Note: When TMDS_CLOCK_RATIO_STATUS bit = 1 the TDP158 sets source termination

to 75 Ω ≅ 150 Ω Automatically

For pin control, L = 1 kΩpulldown resistor to GND, H = 1 kΩpullup resistor to VCC, NC

= Floating.

NA

No Connect. Optionally connect 0.1 μF to GND to reduce noise.

(1) I= Input, O = Output, P = Power, G = Ground

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

–0.3

0

MAX

4

UNIT

VCC

V

Supply Voltage Range⁽³⁾

VDD

1.4

1.56

1.4

4

Main Link Input Differential Voltage (IN_Dx)

Main Link Input Single Ended on Pin

TMDS Output ( OUT_Dx)

–0.3

Voltage Range

HPD_SRC, VSADJ, SDA_CTL/PRE, OE, A1/

EQ2, A0/EQ1, TERM, I2C_EN, SLEW,

SCL_CTL/SWAP, SDA_SRC, SCL_SRC

4

V

–0.3

HDP_SNK, SDA_SNK, SCL_SNK

6

Continuous power dissipation

Storage temperature, T_stg

See 节6.4

150

°C

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) All voltage values, except differential voltages, are with respect to network ground terminal.

(3) Tested in accordance with JEDEC Standard 22, Test Method A114-B.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

3

NOM

MAX

3.6

UNIT

V

V_CC

Supply Voltage Nominal Value 3.3 V for DP mode

Supply Voltage Nominal Value 3.3 V for HDMI mode

Supply Voltage Nominal Value 1.1 V

3.13

1

3.47

1.27

105

85

V

V_DD

T_J

V

Junction temperature

0

°C

T_A

Operating free-air temperature (TDP158)

0

MAIN LINK DIFFERENTIAL PINS

V_ID(EYE)

1200

0.9

mV

V

75

200

0.5

Peak-to-peak input differential voltage See 图7-14

V_ID(DC)

V_IC

The input differential voltage Peak-to peak DC level, See 图7-14

Input Common Mode Voltage (Internally Biased)

Data rate

d_R

0.25

4.5

6

Gbps

V_SADJ

TMDS compliant swing voltage bias resistor (Nominal 6 kΩfor HDMI and

DP combination; 6.49 kΩfor HDMI only)⁽¹⁾

8

kΩ

DDC, I2C, HPD, AND CONTROL PINS

V_I(DC)

DC Input Voltage

HDP_SNK, SDA_SNK, SCL_SNK,

5.5

3.6

V

–0.3

SDA_SRC, SCL_SRC; All other Local I2C, and

control pins

6

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6.3 Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

0.3 x V_CC

0.8

UNIT

V_IL

Low-level input voltage at DDC

Low-level input voltage at HPD

V

Low-level input voltage at SDA_CTL/PRE, OE, A1/EQ2, A0/EQ1, TERM,

I2C_EN, SLEW, SCL_CTL/SWAP pins only

0.3

V_IM

V_IH

Mid-Level input voltage at A1/EQ2, A0/EQ1, TERM, SLEW pins only

1.2

1.6

V

High-level input voltage at OE, A1/EQ2, A0/EQ1, TERM, I2C_EN, SLEW

pins only

0.7 x V_CC

High-level input voltage at SDA_SRC, SCL_SRC, SDA_CTL/PRE,

SCL_CTL/SWAP

V

0.7 x V_CC

High-level input voltage at SDA_SNK, SCL_SNK

High-level input voltage at HPD

3.2

2

V

V_OL

Low-level output voltage

0.4

V

V_OH

High-level output voltage

2.4

V

f_SCL

SCL clock frequency fast I²C mode for local I2C control

Total capacitive load for each bus line supporting 400 kHz (DDC terminals)

Total capacitive load for each bus line (local I2C terminals)

DDC Data rate

400

100

400

30

kHz

pF

Kbps

µA

kΩ

C_(bus,DDC)

C_(bus,I2C)

d_R(DDC)

I_IH

High level input current

–30

–20

–10

I_IM

Mid level input current

20

I_IL

Low level input current

10

I_OZ

High impedance outpupt current

10

R_(OEPU)

Pull up resistance on OE pin

250

150

(1) Reducing resistor in V_SADJwill increase V_OD, care should be taking since resistors below ≅6 kΩmay lead to compliance failures.

6.4 Thermal Information

TDP158

THERMAL METRIC⁽¹⁾

RSB (WQFN)

UNIT

40 PINS

3.7

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

23.1

9.9

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.3

ψ_JT

3.8

ψ_JB

R_θJC(bot)

3.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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6.5 Electrical Characteristics, Power Supply

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP⁽²⁾

200

MAX⁽¹⁾

UNIT

mW

OE = H,_VCC= 3.3 V/3.6 V, V_DD= 1.1 V/1.27

V

P_D1

Device power Dissipation

IN_Dx: VID_PP = 1200 mV, 6 Gbps TMDS

pattern, V_I= 3.3 V, I2C_EN = L,

SDA_CTL/PRE = L, EQ1/EQ2 = H

350

680

OE = H, V_CC= 3.3 V/3.6 V, V_DD= 1.1 V/1.27

330

mW

V

Device power Dissipation in DP-

Mode

P_D2

IN_Dx: VID_PP = 400 mV, 5.4 Gbps DP

pattern, I2C_EN = H, V_OD= 400 mV PRE =

0 dB

OE = H, V_CC= 3.3 V/3.6 V, V_DD= 1.1 V/1.27

V , HPD = H, No input Signal: Stage 1 See

节10.2

34

60

mW

Stage 1: Standby Power

P_(STBY1)

OE = H, V_CC= 3.3 V/3.6 V, VDD = 1.1 V/

1.27 V , HPD = H, Noise on input Signal:

Stage 2 See 节10.2

Stage 2: Standby Power

OE = L, V_CC= 3.3 V/3.6 V, V_DD= 1.1 V/1.27

V

8

34

20

mW

mA

P_(SD1)

P_(SD2)

Device power in PowerDown

Device power in PowerDown in DP- OE = L, V_CC= 3.3 V/3.6 V, V_DD= 1.1 V/1.27

Mode

V

OE = H, V_CC= 3.3 V/3.6 V, V_DD= 1.1 V/1.27

V

IN_Dx: VID_PP = 1200 mV, 6 Gbps TMDS

pattern

I2C_EN = L, SDA_CTL/PRE = L, EQ1/EQ2

= H,

I_CC1

I_CC2

I_DD1

I_DD2

V_CCSupply current

OE = H, V_CC= 3.3 V/3.6 V, V_DD= 1.1 V/1.27

V

IN_Dx: VID_PP = 400 mV, 5.4 Gbps DP

pattern, I2C_EN = H, V_OD= 400 mV PRE =

0 dB

45

110

220

mA

V_CCSupply current in DP-Mode

OE = H, V_CC= 3.3 V/3.6 V, V_DD= 1.1 V/1.27

V

IN_Dx: VID_PP = 1200 mV, 6 Gbps TMDS

pattern

I2C_EN = L, SDA_CTL/PRE = L, EQ1/EQ2

= H

160

V_DDSupply current

OE = H, V_CC= 3.3 V/3.6 V, V_DD= 1.1 V/1.27

V

IN_Dx: VID_PP = 400 mV, 5.4 Gbps DP

pattern, I2C_EN = H, V_OD= 40 mV PRE =

dB

160

220

mA

V_DDSupply current DP-Mode

OE = H, V_CC= 3.3 V/3.6 V,

V_DD= 1.1 V/1.27 V , HPD =

H: No signal on IN_CLK

3.3 V Rail

1.1 V Rail

3.3 V Rail

7

mA

Stage 1: Standby current See 节

10.2

I_(STBY1)

OE = H, V_CC= 3.3 V/3.6 V,

V_DD= 1.1 V/1.27 V , HPD =

H: No valid signal on

IN_CLK

7

mA

Stage 2: Standby current See 节

10.2

27

1.1 V Rail

OE = L, V_CC= 3.3 V/3.6 V,

V_DD= 1.1 V/1.27 V , or OE =

H, HPD = L

3.3 V Rail

1.1 V Rail

1

4

7

mA

I_(SD11)

PowerDown current –HDMI Mode

3.3 V Rail

1.1 V Rail

1

4

7

mA

OE = L, V_CC= 3.3 V/3.6 V,

V_DD= 1.1 V/1.27 V

I_(SD2)

PowerDown current in DP-Mode

(1) The maximum rating is simulated at 3.6 V V_CCand 1.27 V V_DDand at 85°C temperature unless otherwise noted.

(2) The typical rating is simulated at 3.3 V V_CCand 1.1 V V_DDand at 27°C temperature unless otherwise noted.

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6.6 Electrical Characteristics, Differential Input

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

0.25

25

TYP⁽²⁾

MAX⁽¹⁾

6

UNIT

Gbps

Mhz

D_{R(RX_DATA)}

D_{R(RX_CLK)}

t_{RX_DUTY}

TMDS data lanes data rate

TMDS clock lanes clock rate

Input clock duty circle

340

60%

120

40%

80

50%

100

Input differential termination

impedance

Ω

R_(INT)

V_(TERM)

Input Common Mode Voltage

OE = H

0.7

V

(1) The maximum rating is simulated at 3.6 V V_CCand 1.27 V V_DDand at 85°C temperature unless otherwise noted.

(2) The typical rating is simulated at 3.3 V V_CCand 1.1 V V_DDand at 27°C temperature unless otherwise noted.

6.7 Electrical Characteristics, TMDS Differential Output

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP⁽²⁾

MAX⁽¹⁾

UNIT

600

1400

mV

Output differential voltage before pre-

emphasis; See 节8.3.11

V_SADJ= 6 kΩ; SDA_CTL/PRE = H:

See 图7-4

V_OD(PP)

350

720

mV

V_SADJ= 6 kΩ; SDA_CTL/PRE = H,

See 图7-4

Steady state output differential voltage

See 节8.3.11

V_OD(SS)

1000

V_SADJ= 5.5 kΩ; SDA_CTL/PRE = L,

See 图7-3

I_OS

Short circuit current limit

Main link output shorted to GND

50

mA

Source Termination resistance for HDMI

2.0

75

150

Ω

R_(TERM)

6.8 Electrical Characteristics, DDC, I2C, HPD, and ARC

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP⁽²⁾

MAX⁽¹⁾

UNIT

DDC and I2C

SCL/SDA_CTL, SCL/SDA_SRC low

level input voltage

0.3 x V_CC

V

V_IL

V_IH

SCL/SDA_CTL, input voltage

0.7 x V_CC

V_CC+ 0.5

0.4

V

I_O= 3 mA and V_CC> 2 V

SCL/SDA_CTL, SCL/SDA_SRC low

level output voltage

V_OL

0.2 x V_CC

HPD

V_IH

High-level input voltage

Low-level input voltage

High-level output voltage

Low-level output voltage

HPD_SNK

2.1

V

V_IL

HPD_SNK

0.8

3.6

0.4

40

2.4

0

V

V_OH

V_OL

_IOH= –500 µA; HPD_SRC,

I_OL= 500 µA; HPD_SRC,

V

V_CC= 0 V; V_DD= 0 V;

HPD_SNK = 5 V;

μA

I_LKG

Failsafe condition leakage current

Device powered; V_IH= 5 V; I_H(HPD)

includes R_(pdHPD)resistor current

40

30

μA

kΩ

I_H(HPD)

High level input current

Device powered; V_IL= 0.8 V; I_L(HPD)

includes R_(pdHPD)resistor current

150

190

220

R_(pdHPD)

HPD input termination to GND

V_CC= 0 V

(1) The maximum rating is simulated at 3.6 V V_CCand 1.27 V V_DDand at 85°C temperature unless otherwise noted.

(2) The typical rating is simulated at 3.3 V V_CCand 1.1 V V_DDand at 27°C temperature unless otherwise noted.

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6.9 Electrical Characteristics, TMDS Differential Output in DP-Mode

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX⁽¹⁾

UNIT

Differential peak-to-peak output

voltage level 0

Based on default state of

V0_P0_VOD register

415

V

V_{(TX_DIFFPP_LVL0)}

V_{(TX_DIFFPP_LVL1)}

V_{(TX_DIFFPP_LVL2)}

Differential peak-to-peak output

voltage level 1

Based on default state of

V1_P0_VOD register

660

880

V

Differential peak-to-peak output

voltage level 2

Based on default state of

V2_P0_VOD register

1

6

5

dB

ΔV_OD(L0L1)

ΔV_OD(L1L2)

ΔV_ODn= 20×log(V_ODL(n+1)/

V_ODL(n)) measured in compliance

with latest PHY CTS 1.2

Output peak-to-peak differential

voltage delta

V_{(TX_PRE_RATIO_0)}

V_{(TX_PRE_RATIO_1)}

V_{(TX_PRE_RATIO_2)}

ΔV_PRE(L1L0)

Pre-emphasis level 0

Pre-emphasis level 1

Pre-emphasis level 2

Pre-emphasis delta

RBR, HBR and HBR2

0

dB

2

5

4.2

7.2

Measured in compliance with

latest PHY CTS 1.2

2

1.6

ΔV_PRE(L2L1)

(1) Does not support Level 3 swing or pre-emphasis.

6.10 Switching Characteristics, TMDS

PARAMETER

TEST CONDITIONS

MIN

250

TYP⁽²⁾

MAX⁽¹⁾

UNIT

Mbps

ps

d_R

Data rate

6000

Reg0Ah[1:0] = 11 (default)

Reg0Ah[1:0] = 10

60

80

ps

t_T(DATA)

Transition time (rise and fall time);

measured at 20% and 80%.

SDA_CTL = L, OE = H, All Data

Rates

Note: Data lane control by I2C only:

See 节8.3.10

Reg0Ah[1:0] = 01

95

ps

Reg0Ah[1:0] = 00

110

122

150

180

203

ps

TERM = H; Reg0Bh[7:6] = 11

Reg0Bh[7:6] = 10

ps

t_T(CLOCK)

TERM = L; Reg0Bh[7:6] = 00

TERM = NC; Reg0Bh[7:6] = 01

ps

(1) The maximum rating is simulated at 3.6 V V_CCand 1.27 V V_DDand at 85°C temperature unless otherwise noted.

(2) The typical rating is simulated at 3.3 V V_CCand 1.1 V V_DDand at 27°C temperature unless otherwise noted.

6.11 Switching Characteristics, HPD

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP⁽²⁾

MAX⁽¹⁾

UNIT

ns

Propagation delay from HPD_SNK to

HPD_SRC; rising edge and falling

edge

see 图7-8; not valid during switching

time

t_PD(HPD)

t_T(HPD)

40

120

HPD logical disconnected timeout

2

ms

see 图7-9

(1) The Maximum rating is simulated at 3.6 V V_CCand 1.27 V V_DDand at 85°C temperature unless otherwise noted

(2) The Typical rating is simulated at 3.3 V V_CCand 1.1 V V_DDand at 27°C temperature unless otherwise noted

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6.12 Switching Characteristics, DDC and I²C

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t_r

t_f

Rise time of both SDA and SCL

signals

300

ns

V_CC= 3.3 V; See 图7-12

Fall time of both SDA and SCL

signals

300

ns

See 图7-12

t_HIGH

Pulse duration , SCL high

Pulse duration , SCL low

Setup time, SDA to SCL

Setup time, SCL to start condition

Hold time, start condition to SCL

Data Hold Time

0.6

1.3

100

0.6

0

See 图7-11

See 图7-10

μs

ns

t_LOW

t_SU1

t_{ST, STA}

t_HD,STA

t_HD,DAT

t_VD,DAT

t_VD,ACK

t_ST,STO

μs

ns

Data valid time

0.9

0.6

µs

Data valid acknowledge time

Setup time, SCL to stop condition

µs

See 图7-10

μs

Bus free time between stop and start

condition

t_(BUF)

1.3

μs

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6.13 Typical Characteristics

900

800

700

600

500

400

300

200

100

0

180

160

140

120

100

80

1.1 V (mA)

3.3 V (mA)

60

40

20

0

0.5

1

1.5

2

2.5

3

3.5

Date Rate (Gbps)

4

4.5

5

5.5

6

4

5

6

7

8

Rvsadj (kW)

D002

D001

图6-2. HDMI Current vs Data Rate

图6-1. V_ODSwing vs VASDJ Resistor Value

180

160

140

120

100

80

60

40

20

0

1.4

2

2.6

3.2 3.8

Data Rate (Gbps)

4.4

5

5.4

D003

图6-3. DisplayPort Current vs Data Rate

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7 Parameter Measurement Information

V_TERM

3.3 V

50 Ω

75-200 nF

50 Ω

0.5 pF

D+

D-

Y

Z

Receiver

Driver

V_ID

V_D+

V_Y

75-200 nF

V_ID= V_D+- V_D-

V_OD= V_Y- V_Z

V_D-

V_Z

V_ICM= (V_D++ V_D-

2

)

V_OC= (V_Y+ V_Z)

2

图7-1. TMDS Main Link Test Circuit

4.0 V

2.6 V

Vcc

V_ID+

V_ID

V_ID(pp)

0 V

V_ID-

t_PHL

t_PLH

80%

V_OD(pp)

V_OD

0 V

20%

t_r

t_f

图7-2. Input or Output Timing Measurements

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V_OD(SS)

PRE = L

图7-3. Output Differential Waveform

PRE = L

PRE = H

VOD(PP)

VOD(SS)

图7-4. Output Differential Waveform with De-Emphasis

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Avcc⁽⁴⁾

(5)

R_T

SMA

REF

Cable

EQ

Coax

Data +

RX

+EQ

OUT

Data -

Parallel ⁽⁶⁾

BERT

Jitter Test

Instrument ^(2,3)

FR4 PCB trace⁽¹⁾

AC coupling Caps

&

Device

FR4 PCB trace

AVcc

R_T

[No Pre-

emphasis]

R_T

REF

Cable

EQ

SMA

Coax

Clk+

Clk-

RX

+EQ

OUT

Jitter Test

Instrument ^(2,3)

TTP4_EQ

TTP4

TTP1

TTP2

TTP3

TTP2_EQ

A. The FR4 trace between TTP1 and TTP2 is designed to emulate 1-8”of FR4, AC coupling cap, connector and another 1-8”of FR4.

Trace width –4 mils. 100 Ωdifferential impedance.

B. All Jitter is measured at a BER of 10⁹

C. Residual jitter reflects the total jitter measured at TTP4 minus the jitter measured at TTP

D. AVCC = 3.3 V

E. R_T= 50 Ω

F. The input signal from parallel Bert does not have any pre-emphasis. Refer to Recommended Operating Conditions.

图7-5. HDMI Output Jitter Measurement

V

0

H

0

0.5

图7-6. Output Eye Mask at TTP4_EQ for HDMI 2.0

TMDS Data Rate (Gbps)

3.4 < DR < 3.712

H (Tbit)

V (mV)

0.6

335

–0.0332Rbit²+ 0.2312 R_bit+ 0.1998

–19.66Rbit²+ 106.74R_bit+ 209.58

3.712 < DR < 5.94

0.4

150

5.94 ≤DR ≤6.0

HPD Input

HPD Output

190 k

100 k

图7-7. HPD Test Circuit

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HPD_SNK

V_CC

50%

0 V

t_PD(HPD)

HPD_SRC

V_CC

50%

0 V

图7-8. HPD Timing Diagram No. 1

HPD_SNK

Vcc

50%

0V

HPD Logical disconnect

Timeout

tT(HPD)

HPD_SRC

Vcc

0V

Logically

Disconnected

Device Logically

Connected

图7-9. HPD Logic Disconnect Timeout

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t_HD,STA

t_f

t_r

SCL

t_ST,STO

SDA

t_(BUF)

START

STOP

图7-10. Start and Stop Condition Timing

tHIGH

tLOW

SCL

tST,STA

SDA

tSU1

图7-11. SCL and SDA Timing

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SDA_SRC/SCL_SRC

INPUT

½ V_CC

t_PLH1

t_PHL1

SDA_SNK/SCL_SNK

OUTPUT

80%

½ V_CC

20

%

tf

tr

图7-12. DDC Propagation Delay –Source to Sink

SDA_SNK/SCL_SNK

INPUT

½ Vcc

t_PHL2

t_PLH2

80%

SDA_SRC/SCL_SRC

OUTPUT

20%

½ Vcc

t_f

t_r

图7-13. DDC Propagation Delay –Sink to Source

V_ID(DC)

V_ID(EYE)

图7-14. V_ID(DC)and V_ID(EYE)

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8 Detailed Description

8.1 Overview

The TDP158 is an AC-coupled digital video interface (DVI) or high-definition multimedia interface (HDMI) signal

input to Transition Minimized Differential Signal (TMDS) level shifting Redriver. The TDP158 supports four TMDS

channels, Hot Plug Detect, and a Digital Display Control (DDC) interfaces. The TDP158 supports signaling rates

up to 6 Gbps to allow for the highest resolutions of 4k2k60p 24 bits per pixel and up to WUXGA 16-bit color

depth or 1080p with higher refresh rates. For passing compliance and reducing system level design issues,

several features have been included such as TMDS output amplitude adjust using an external resistor on the

VSADJ pin, source termination selection, pre-emphasis, and output slew rate control. Device operation and

configuration can be programmed by pin strapping or I²C. Four TDP158 devices can be used on one I²C bus

when I2C_EN is high with device address set by A0/A1.

To reduce active power the TDP158 supports dual power supply rails of 1.1 V on VDD and 3.3 V on VCC. There

are several methods of power management such as going into power down mode using three methods:

1. HPD is low

2. Writing a 1 to register 09h[3]

3. De-asserting OE

De-asserting OE clears the I²C registers, thus once re-asserted, the device must be reprogrammed if I²C was

used for device setup. The TDP158 requires the source to write a 1 to the TMDS_CLOCK_RATIO_STATUS

register for the TDP158 to resume 75 Ω to 150 Ω source termination upon return to normal active operation from

re-asserted, OE, or re-asserted HPD. If this bit is already set as a one during the source to sink read, then the

TDP158 automatically sets this bit to 1. The SIG_EN register enables the signal detect circuit that provides an

automatic power-management feature during normal operation. When no valid signal is present on the clock

input, the device enters Standby mode. DDC link supports the HDMI 2.0b SCDC communication, 100 Kbps data

rate default and 400 Kbps adjustable by software.

TDP158 supports fixed EQ gain control to compensate for different lengths of input cables or board traces. The

EQ gain can be software adjusted by I²C control or pin strapping EQ1 and EQ2 pins. Customers can use the

TERM to change to one of three source termination impedances for better output performance when working in

HDMI 1.4b or HDMI 2.0b. When the TMDS_CLOCK_RATIO_STATUS bit is set to 1, the TDP158 automatically

switches in 75 Ω to 150 Ω source termination. To assist in ease of implementation, the TDP158 supports lanes

swapping, see 节8.3.3. The device's available extended commercial temperature range is 0°C to 85°C.

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8.2 Functional Block Diagram

HPD_SRC

HPD_SNK

190 k

SIGNAL

DETECT

VBIAS

SIG_DET_

OUT

VSADJ

50

OUT_CLKp

OUT_CLKn

IN_CLKp

IN_CLKn

TMDS

EQ

VBIAS

50

IN_D[2:0]p

IN_D[2:0]n

OUT_D[2:0]p

OUT_D[2:0]n

EQ

TMDS

Enable

MODE_TERM

SLEW

Control Block, I2C Registers

EQ_CTL

EQ1

I2C_EN

A0/EQ1

A1/EQ2

DE

Enable

EQ2

A0

SIG_DET_OUT

A1

OE

Local

I2C

Control

SLEW

TERM

SDA

SDA_CTL/PRE

SCL

PRE

DDC Snoop Block

SCL_CTL/SWAP

SWAP

SDA_SRC

SCL_SRC

SDA_SNK

SCL_SNK

VDD

ACTIVE DDC BLOCK

1.1 V

3.3 V

VREG

VCC

GND

8.3 Feature Description

8.3.1 Reset Implementation

When OE is low, control signal inputs are ignored; the HDMI inputs and outputs are high impedance. It is critical

to transition the OE from a low level to high after the V_CCsupply has reached the minimum recommended

operating voltage. This is achieved by a control signal to the OE input, or by an external capacitor connected

between OE and GND. To ensure the TDP158 is properly reset, the OE pin must be de-asserted for at least 100

μs before being asserted. When OE is re-asserted the TDP158 must be reprogrammed if it was programmed by

I²C and not pin strapping. When implementing the external capacitor, the size of the external capacitor depends

on the power up ramp of the V_CCsupply, where a slower ramp-up results in a larger value external capacitor.

Refer to the latest reference schematic for TDP158; consider approximately 0.1 µF capacitor as a reasonable

first estimate for the size of the external capacitor. Both OE implementations are shown in 图8-1 and 图8-2.

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OE

R_RST= 200 k

C

图8-1. External Capacitor Controlled OE

GPO

OE

C

图8-2. OE Input from Active Controller

8.3.2 Operation Timing

TDP158 starts to operate after the OE signal is properly set after power up timing is complete. See 图8-3 and 表

8-1. Keeping OE low until V_DDand V_CCbecomes stable avoids any timing requirements as shown in 图8-3.

Control Signal

Td2

OE

Td1

Vdd

Vcc

图8-3. Power Up Timing for TDP158

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表8-1. Power Up and Operation Timing Requirements

PARAMETER

t_d1

DESCRIPTION

MIN

TYP

MAX

UNIT

µs

V_CCstable before V_DD

0

200

t_d1

V_DDand V_CCstable before OE de-assertion

V_DDsupply ramp up requirements

V_CCsupply ramp up requirements

100

0.2

µs

V_DD(ramp)

V_CC(ramp)

100

ms

8.3.3 Lane Control

The TDP158 has various lane control features. By default the high speed lanes are globally controlled. Pin

strapping can globally control features like receiver equalization, V_ODswing and pre-emphasis. I²C programming

performs the same global programming using default configurations. Through I2C a method to control receive

equalization, transmitter swing (V_OD) and pre-emphasis on each individual lane. Setting reg09h[5] = 1 puts the

device into independent lane configuration mode.

Reg31h[7:3] controls the clock lane, reg32h[7:3] controls lane D0, reg33h[7:3] controls lane D1 and reg34h[7:3]

controls lane D2 while Reg4E and Reg4F control the individual lane EQ control.

备注

If the swap function is enabled and individual lane control has been implemented, then it is

recommended to reprogram the lanes to make sure they match the expected results. Registers are

mapped to the pin name convention.

8.3.4 Swap

TDP158 incorporates a swap function which can swap the lanes, see 图 8-4. The EQ, Pre-emphasis,

termination, and slew setup will follow the new mapping. This function can be used with the SCL_CTL/SWAP pin

13 when I2C_EN pin 8 is low or can be implemented using control the register 0x09h bit 7 and is only valid for

HDMI mode.

表8-2. Swap Functions

Normal Operation

IN_D2 →OUT_D2

IN_D1 →OUT_D1

IN_D0 →OUT_D0

IN_CLK →OUT_CLK

Pin Numbers

[1, 2] →[30, 29]

[4, 5] →[27, 26]

[6, 7] →[25, 24]

[9, 10] →[22, 21]

SWAP = L or CSR 0x09h bit 7 is 1’b1

IN_CLK →OUT_CLK

IN_D0 →OUT_D0

IN_D1 →OUT_D1

IN_D2 →OUT_D2

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IN_D2p

IN_D2n

1

2

3

4

5

6

7

8

30

29

28

27

26

25

24

OUT_D2p

OUT_D2n

HPD_SNK

IN_D2p

IN_D2n

1

2

30

29

28

27

26

25

24

23

OUT_D2p

OUT_D2n

HPD_SNK

DATA LANE2

CLOCK LANE

HPD_SRC

3

IN_D1p

IN_D1n

OUT_D1p

IN_D1p

IN_D1n

4

DATA LANE1

DATA LANE0

OUT_D1p

DATA LANE0

DATA LANE1

OUT_D1n

OUT_D0p

5

OUT_D1n

OUT_D0p

IN_D0p

6

IN_D0n

I2C_EN

OUT_D0n

IN_D0n

I2C_EN

7

OUT_D0n

A1/EQ2

23

22

8

IN_CLKp

IN_CLKn

OUT_CLKp

OUT_CLKn

9

IN_CLKp

IN_CLKn

9

22

21

OUT_CLKp

OUT_CLKn

CLOCK LANE

DATA LANE2

10

21

10

In Normal Working

Lane Swap

图8-4. TDP158 Swap Function

8.3.5 Main Link Inputs

Standard Dual Mode DisplayPort terminations are integrated on all inputs with expected AC coupling capacitors

on board prior to input pins. External terminations are not required. Each input data channel contains an

equalizer to compensate for cable or board losses. The voltage at the input pins must be limited under the

absolute maximum ratings.

8.3.6 Receiver Equalizer

The equalizer is used to clean up inter-symbol interference (ISI) jitter/loss from the bandwidth-limited board

traces or cables. TDP158 supports fixed receiver equalizer by setting the A0/EQ1 and A1/EQ2 pins or through

I²C. 表8-3 shows the pin strap settings and EQ values.

表8-3. Receiver EQ Programming and Values

Global

Independent Lane Control

Pin Control ⁽¹⁾

{EQ2,EQ1}

I2C Control

I2C Control ⁽²⁾

RX EQ

(dB)

D2

D1

D3

CLK^{(2) (3)}

P0_Reg4F[7:4]

P0_Reg0D[6:3]

P0_Reg4E[3:0]

P0_Reg4E[7:4]

P0_Reg4F[3:0]

4’b0000

4’b0001

4’b0010

4’b0011

4’b0100

4’b0101

4’b0110

4’b0111

4’b1000

4’b1001

4’b1010

4’b1011

4’b1100

2

3

2’b00

2’b0Z

4’b0000

4’b0001

4’b0010

4’b0011

4’b0100

4’b0101

4’b0110

4’b0111

4’b1000

4’b1001

4’b1010

4’b1011

4’b1100

4’b0000

4’b0001

4’b0010

4’b0011

4’b0100

4’b0101

4’b0110

4’b0111

4’b1000

4’b1001

4’b1010

4’b1011

4’b1100

4’b0000

4’b0001

4’b0010

4’b0011

4’b0100

4’b0101

4’b0110

4’b0111

4’b1000

4’b1001

4’b1010

4’b1011

4’b1100

4’b0000

4’b0001

4’b0010

4’b0011

4’b0100

4’b0101

4’b0110

4’b0111

4’b1000

4’b1001

4’b1010

4’b1011

4’b1100

4

5

2’b01

2’bZ0

6.5

7.5

8.5

9

2’bZZ

10

11

12

13

14

2’bZ1

2’b10

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表8-3. Receiver EQ Programming and Values (continued)

Global

Independent Lane Control

Pin Control ⁽¹⁾

{EQ2,EQ1}

2’b1Z

I2C Control

I2C Control ⁽²⁾

RX EQ

(dB)

D2

D1

D3

CLK^{(2) (3)}

P0_Reg4F[7:4]

P0_Reg0D[6:3]

P0_Reg4E[3:0]

P0_Reg4E[7:4]

P0_Reg4F[3:0]

14.5

15

4’b1101

4’b1110

4’b1111

4’b1101

4’b1110

4’b1111

4’b1101

4’b1110

4’b1111

4’b1101

4’b1110

4’b1111

4’b1110

15.5

2’b11

4’b1111

(1) For Pin Control 0 = 1 kΩpulldown resistor to GND, 1 = 1 kΩpullup resistor to VCC, Z = Floating (No Connect)

(2) Individual Lane control is based upon the pin names with no swap

(3) The CLK EQ in HDMI mode is controlled by register P0_Reg0D[2:1]

8.3.7 Input Signal Detect Block

When SIG_EN is enabled through I²C the receiver looks for a valid HDMI clock signal input and is fully functional

when a valid signal is detected. If no valid HDMI clock signal is detected, then the device enters standby mode

waiting for a valid signal at the clock input. All of the TMDS outputs and IN_D[0:2] are in high-Z status. HDMI

signal detect circuit is default enabled. If there is a loss of signal, then reg20h[5] can be read to determine if the

TDP158 has detected a valid signal or not.

8.3.8 Transmitter Impedance Control

HDMI 2.0 standard requires a source termination impedance in the 75 Ω to 150 Ω range for data rates > 3.4

Gbps. HDMI 1.4b requires no source termination but has a provision for using 150 Ω to 300 Ω for higher data

rates. The TDP158 has three termination levels that are selectable using pin 16 when programming through pin

strapping or when using I²C programming through reg0Bh[4:3]. When the TMDS_CLOCK_RATIO_STATUS bit,

reg0Bh[1] = 1 the TDP158 automatically turns on the 75 Ω to 150 Ω source termination otherwise the termination

must be selected. See 表8-4.

表8-4. Source Termination Control Table

Pin 16

Reg0Bh[4:3]

Source Termination

TERM = L

TERM = NC

00

01

10

11

150 Ω≅ 300 Ω

None

Automatic set based upon TMDS_CLOCK_RATIO_STATUS bit

75 Ω≅ 150 Ω

TERM = H

备注

If the TMDS_CLOCK_RATIO_STATUS bit = 1, then the TDP158 automatically switches in 75 Ω ≅ 150

Ω termination.

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8.3.9 TMDS Outputs

A 1% precision resistor, connected from VSADJ pin to ground is recommended to allow the differential output

swing to comply with TMDS signal levels. The differential output driver provides a typical 10-mA current sink

capability, which provides a typical 500-mV voltage drop across a 50-Ωtermination resistor.

V_CC

A_VCC

TDP158

Zo = RT

图8-5. TMDS Driver and Termination Circuit

Referring to 图 8-5, if V_CC(TDP158 supply) and A_VCC(sink termination supply) are both powered, the TMDS

output signals are high impedance when OE = low. Both supplies being active is the normal operating condition.

A total of approximately 33-mW of power is consumed by the terminations independent of the OE logical

selection. When AVCC is powered on, normal operation (OE controls output impedance) is resumed. When the

power source of the device is off and the power source to termination is on, the I_O(off), output leakage current,

specification ensures the leakage current is limited 45-μA or less. The clock and data lanes V_ODcan be

changed through I²C reg0Ch[7:2], VSWING_DATA and VSWING_CLK.

8.3.10 Slew Rate Control

As the clock signal tends to be a primary source of EMI, the TDP158 provides the ability to slow down the TMDS

output edge rates. There are two ways of changing the slew rate, Pin strapping for clock lane and I²C for both

clock and data lanes. Refer to 节6.10

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8.3.11 Pre-Emphasis

The TDP158 provides pre-emphasis on the data lanes allowing the output signal pre-conditioning to offset

interconnect losses between the TDP158 outputs and a TMDS receiver. Pre-emphasis is not implemented on

the clock lane unless the TDP158 is in DP mode; at which time, it becomes a data lane. The default value for

pre-emphasis is 0 dB. There are two methods to implement pre-emphasis, pin strapping or through I²C

programming. When using pin strapping, the SDA_CTL/PRE pin controls global pre-emphasis values of 0 dB or

3.5 dB. Through I²C, reg0Ch[1:0] pre-emphasis values are 0 dB, 3.5 dB, and 6 dB. The 6 dB value has different

meanings when the device is in normal operational mode (reg09h[5] = 0) or when the TDP158 has been put into

DP-mode (reg09h[5] = 1). As 图 8-6 shows, the 6 dB pre-emphasis setting will result in an output of 3 dB of pre-

emphasis with 3 dB of de-emphasis when device is in normal HDMI operation. As 图 8-7 shows, the output will

be about 5 dB pre-emphasis with a 1 db de-emphasis when selecting 6 dB pre-emphasis setting for DP-mode.

V_OD(PP)value will not go above 1 V.

Reg0Ch[1:0] = 00

Reg0Ch[1:0] = 10

V_OD(PP)

V_OD(SS)

图8-6. 6 dB Pre-Emphasis Setting in Normal Operation

Reg0Ch[1:0] = 00

Reg0Ch[1:0] = 10

V_OD(PP)

V_OD(SS)

图8-7. 6 dB Pre-Emphasis in DP-Mode

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Mode

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表8-5. Swing and Pre-Emphasis Programming Based Upon 6 kΩVSADJ Resistor

Global Control

Independent Lane Control

Reg09h[6]

Lane CTL

Reg09[5]

Mode CTL

Reg09h[6]

Lane CTL

Reg09[5]

Mode CTL

P0_Reg0C[7:0]

HDMI

0

1

0

1

8’h00

8’h80

8’hC1

8’h42

8’hC0

8’hF1

8’h52

8’h20

8’h51

8’h00

8’h80

8’hC1

8’h42

8’hA0

8’h21

8’h62

8’h00

8’h61

DP SWG0, PRE0

DP SWG0, PRE1

DP SWG0, PRE2

DP SWG1, PRE0

DP SWG1, PRE1

DP SWG1, PRE2

DP SWG2, PRE0

DP SWG2, PRE1

8.3.12 DP-Mode Description

The TDP158 has the ability to perform as a DisplayPort redriver under the right conditions. The TDP158 is put

into this mode by setting reg09h[5] to 1. The device is now programmable through I²C only. As the transmitter is

a DC coupled transmitter supporting TMDS some external circuits are required to level shift the signal to an AC-

coupled DisplayPort signal, see 图 9-6. Note that the AUX lines bypass the TDP158. To set the device up

correctly during link training, the TDP158 must be programmed using I²C. When this bit is set, the TDP158 does

the following:

• Ignore SWAP function

• Ignore SIG_EN function

• Enable all four lanes and set to support 5.4 Gbps data rate

• Sets V_ODswing to the lowest level based on a 6 kΩ VSADJ resistor value

• Sets pre-emphasis to 0 dB

• Defaults to global lane control

• Can be set to independent lane control by setting P0_Reg09[6] to a 1. This should be done after

implementing DP mode. Individual Lane control starts on P0_Reg30 through P0_Reg34 and also P0_Reg4E

and 4F

For the system implementer to configure the TDP158 output to the properly requested levels during link training,

the following registers are used.

• Reg0Ch[7:5] is a global V_ODswing control for all four lanes, see 表8-5

• Reg0Ch[1:0] is a global Pre-emphasis control for all four lanes, see 表8-5. This register works with

Reg30h[7:6]

• Reg0D[6:3] is a global EQ control for all four lanes

• Reg30h[7:6] is to let the TDP158 know what the data rate is. This is used for the delay component for pre-

emphasis signal.

• Reg30h[5:2] is used to turn on or off individual lanes

Power down states while in DP-Mode are implemented the same as if in normal operation. See the 节6.7 for the

outputs based upon the VSADJ 6 kΩVSADJ resistor.

8.4 Device Functional Modes

8.4.1 DDC Training for HDMI 2.0 Data Rate Monitor

As part of discovery, the source reads the sink E-EDID information to understand the sink’s capabilities. The

supported data rate comes from the HDMI Forum Vendor Specific Data Block (HF-VSDB)

MAX_TMDS_Character_Rate byte. Depending upon the value, the source will write to target address 0xA8

offset 0x20 bit1, TMDS_CLOCK_RATIO_STATUS. The TDP158 snoops the DDC link to determine the TMDS

clock ratio status and thus sets its own TMDS_CLOCK_RATIO_STATUS bit accordingly. If a ‘1’ is written by

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the source the TMDS clock is 1/40 of TMDS bit period. If a ‘0’ is written, then the TMDS clock is 1/10 of

TMDS bit period.

The TDP158 will always default to 1/10 of TMDS bit period unless a ‘1’is written to address 0xA8 offset 0x20

bit 1 or during a read by the source this bit is set. This helps determine source termination when automatic

source termination select is enabled. Otherwise this bit has no other impact on the TDP158. When HPD_SNK is

de-asserted this bit is reset to default values of 0 if this feature is enabled. If the source does not write this bit to

the sink or during the read the bit is not set the TDP158 will not set the output termination to 75 Ω to 150 Ω in

support of HDMI 2.0. If the TDP158 has entered a power down state using HDP_SNK = low or OE = low this bit

is cleared and will be set on a read or write where this bit is set. When DDC_TRAIN_SETDISABLE is 1’b0 the

TMDS_CLOCK_RATIO_STATUS bit will reflect the value of the DDC snoop. When DDC_TRAIN_SETDISABLE

is 1’b1 the TMDS_CLOCK_RATIO_STATUS bit is set by I²C and DDC snoop is ignored and thus automatic

TERM control is ignored and must be manually set. To go back to snoop and automatic TERM control the

DDC_TRAIN_SETDISABLE bit has to be cleared and TERM set back to automatic control.

8.4.2 DDC Functional Description

The TDP158 solves sink/source level issues by implementing a controller/target control mode for the DDC bus.

When the TDP158 detects the start condition on the DDC bus from the SDA_SRC/SCL_SRC it transfers the

data or clock signal to the SDA_SNK/SCL_SNK with little propagation delay. When SDA_SNK detects the

feedback from the downstream device, the TDP158 pulls up or pulls down the SDA_SRC bus and delivers the

signal to the source.

The DDC link defaults to 100 Kbps but can be set to various values including 400 Kbps by setting the correct

value to address 22h through the I²C interface. The HPD goes to high impedance when VCC is under low power

conditions, < 1.5 V.

备注

The TDP158 uses clock stretching for DDC transactions. As there are sources and sinks that do not

perform this function correctly, a system may not work correctly as DDC transactions are incorrectly

transmitted/received. To overcome this, a snoop configuration can be implemented where the

SDA/SCL from the source is connected directly to the SDA/SCL pins. The TDP158 needs the

SDA_SNK and SCL_SNK pins connected to the sink DDC pins so that the

TMDS_CLOCK_RATIO_STATUS bit can be automatically set; otherwise, it will have to be set through

I²C. For best noise immunity, the SDA_SRC and SCL_SRC pins should be connected to GND. Care

must be taken when this configuration is being implemented as the voltage level for DDC between the

source and sink may be different, 3.3 V versus 5 V.

8.5 Register Maps

The TDP158 local I²C interface is enabled when I²C_EN is high. The SCL_CTL and SDA_CTL terminals are

used for I²C clock and data respectively. The TDP158 I2C interface conforms to the two-wire serial interface

defined by the I²C Bus Specification, Version 2.1 (January 2000), and supports the fast mode transfer up to 400

Kbps. The device address byte is the first byte received following the START condition from the controller

device. The 7 bit device address for TDP158 decides by the combination of A0/EQ1 and A1/EQ2. 表8-6 clarifies

the TDP158 target address.

表8-6. TDP158 I2C Device Address Description

A1/A0

00

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (W/R)

HEX

BC/BD

BA/BB

B8/B9

B6/B7

1

0

1

0

1

0

1

0

1

0

1

0/1

01

10

11

The local I²C is 5-V tolerant, and no additional circuitry required. Local I²C buses run at 400 kHz supporting fast-

mode I²C operation.

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The following procedure is followed to write to the TDP158 I²C registers:

1. The controller initiates a write operation by generating a start condition (S), followed by the TDP158 7-bit

address and a zero-value “W/R”bit to indicate a write cycle.

2. The TDP158 acknowledges the address cycle.

3. The controller presents the sub-address (I²C register within TDP158) to be written, consisting of one byte of

data, MSB-first.

4. The TDP158 acknowledges the sub-address cycle.

5. The controller presents the first byte of data to be written to the I²C register.

6. The TDP158 acknowledges the byte transfer.

7. The controller may continue presenting additional bytes of data to be written, with each byte transfer

completing with an acknowledge from the TDP158.

8. The controller terminates the write operation by generating a stop condition (P).

The following procedure is followed to read the TDP158 I²C registers:

1. The controller initiates a read operation by generating a start condition (S), followed by the TDP158 7-bit

address and a one-value “W/R”bit to indicate a read cycle.

2. The TDP158 acknowledges the address cycle.

3. The TDP158 transmit the contents of the memory registers MSB-first starting at register 00h.

4. The TDP158 will wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the controller

after each byte transfer; the I²C controller acknowledges reception of each data byte transfer.

5. If an ACK is received, the TDP158 transmits the next byte of data.

6. The controller terminates the read operation by generating a stop condition (P).

备注

Upon reset, the TDP158 sub-address will always be set to 0x00. When no sub-address is included in

a read operation, the TDP158 sub-address will increment from previous acknowledged read or write

data byte. If it is required to read from a sub-address that is different from the TDP158 internal sub-

address, a write operation with only a sub-address specified is needed before performing the read

operation.

Refer to 节 8.5.1 for TDP158 local I²C register descriptions. Reads from reserved fields or addresses that are

not specified return zeros. The value written to reserved fields must match the value read from the reserved field

to not impact device features or performance.

8.5.1 Local I²C Control BIT Access TAG Convention

Reads from reserved fields shall return zero, and writes to read-only reserved registers shall be ignored. Writes

to reserved register which are marked with ‘W’ will produce unexpected behavior. All addresses not defined

by this specification shall be considered reserved. Reads from these addresses shall return zero and writes shall

be ignored.

8.5.2 BIT Access Tag Conventions

A table of bit descriptions is typically included for each register description that indicates the bit field name, field

description, and the field access tags. The field access tags are described in 表8-7.

表8-7. Field Access Tags

Access Tag

Name

Read

DESCRIPTION

R

W

S

The field shall be read by software

The field shall be written by software

Write

Set

The field shall be set by a write of one. Writes of Zero to the field have no effect

The field shall be cleared by a write of one. Writes of Zero to the field have no effect

Hardware may autonomously update this field

C

Clear

U

Update

No Access

NA

Not accessible or not applicable

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8.5.3 CSR Bit Field Definitions, DEVICE_ID (address = 00h≅07h)

图8-8. DEVICE_ID

7

6

5

4

3

2

1

0

DEVICE_ID

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-8. DEVICE_ID Field Descriptions

Bit

Field

Type

Default

Description

These fields return a string of ASCII characters “TDP158”

followed by one space characters

7:0

R

TDP158: Address 0x00 –0x07 = {- 0x54”T”, 0x44”D”,

0x50”P”, 0x31”1”, 0x35”5”, 0x38”8, 0x20, 0x20

8.5.4 CSR Bit Field Definitions, REV_ID (address = 08h )

图8-9. REV_ID Field Descriptions

7

6

5

4

3

2

1

0

REV_ID

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-9. REV_ID

Bit

Field

Type

Default

Description

This field identifies the device revision.

7:0

REV_ID

R

00000001

00000001 –TDP158 Revision

8.5.5 CSR Bit Field Definitions –MISC CONTROL 09h (address = 09h)

图8-10. MISC CONTROL 09h Field Descriptions

7

6

5

4

3

2

1

0

LANE_SWAP

Lane Control

DP-Mode

SIG_EN

PD_EN

HPD_AUTO_P

WRDWN_DISA

BLE

I2C_DR_CTL

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-10. MISC CONTROL 09h

Bit

Field

Type

Default

Description

This field Swaps the input lanes as per 图8-4 and 节8.3.4 and

valid when in HDMI mode only.

7

LANE_SWAP

R/W

1’b0

0 − Disable (default) No Lane Swap

1 − Enable: Swaps both Input and Output Lanes

See 节8.3.3

0 –Global (Default)

1 –Independent

6

Lane Control

R/W

1’b0

Note: In default mode reg0C and reg0D control all lanes. When

set to 1 each lane can be individually controlled for Swing, EQ,

Pre-emphasis.

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表8-10. MISC CONTROL 09h (continued)

Bit

Field

Type

Default

Description

See 节8.3.12

0 –Normal DP158 Operation (Default)

1 –All lanes behave as data lanes and full control through I2C

5

DP-Mode

R/W

1’b0

only

This field enables the clock lane activity detect circuitry. See 节

8.3.7

0 –Disable Clock detector circuit closed and receiver always

works in normal operation.

4

SIG_EN

R/W

1’b1

1 –Enable (default), Clock detector circuit will make the

receiver automatically enter the standby state when no valid

data detect.

0 –Normal working (default)

1 –Forced Power down by I2C, Lowest Power state

3

2

PD_EN

R/W

1’b0

0 –Automatically enters Power Down mode based on

HPD_SNK (default)

HPD_AUTO_PWRDWN_DISABL

1 –Will not automatically enter Power Down mode

I2C data rate supported for configuring device.

00 –5 Kbps

1:0

I2C_DR_CTL

R/W

01 –10 Kbps

2’b10

10 –100 Kbps( Default )

11 –400 Kbps

8.5.6 CSR Bit Field Definitions –MISC CONTROL 0Ah (address = 0Ah)

图8-11. MISC CONTROL 0Ah Field Descriptions

7

6

5

4

3

2

1

0

Reserved

HPDSNK_GAT

E_EN

Reserved

R

SLEW_CTL_DATA

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-11. MISC CONTROL 0Ah

Bit

Field

Type

Default

Description

7

Reserved

R

Reserved

1’b0

The field set the HPD_SNK signal pass through to HPD_SRC or

not and HPD_SRC whether held in the de-asserted state.

0 –HPD_SNK passed through to the HPD_SRC (default)

1 –HPD_SNK will not pass through to the HPD_SRC.

6

HPDSNK_GATE_EN

Reserved

R/W

R

1’b0

Reserved

5:2

4’b0000

See 节8.3.10

00 –Slowest ≅ 110

01 –Mid-Range 1 ≅ 95

10 –Mid-Range 2 ≅ 80 ps

11 –Fastest (Default) ≅ 60 ps

Values are typical

1:0

SLEW_CTL_DATA

R/W

2’b11

8.5.7 CSR Bit Field Definitions –MISC CONTROL 0Bh (address = 0Bh)

图8-12. MISC CONTROL 0Bh Field Descriptions

7

6

5

4

3

2

1

0

SLEW_CTL_CLK

Reserved

TERM

DDC_DR_SEL TMDS_CLOCK DDC_TRAIN_S

_RATIO_STATU ETDISABLE

S

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图8-12. MISC CONTROL 0Bh Field Descriptions (continued)

R/W

R

R/W

R/W/U

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-12. MISC CONTROL 0Bh

Bit

7:6

5

Field

Type

R/W

R

Reset

2’b01

1’b0

Description

See 节8.3.10

00 –Slowest ≅ 215 ps

01 –Mid-Range 1 (Default) ≅ 185 ps

10 –Mid-Range 2 ≅ 155 ps

11 –Fastest ≅ 125 ps

SLEW_CTL_CLK

Reserved

Values are typical

Reserved

Controls termination for HDMI TX. See 节8.3.8

00 –150 to 300 Ω

01 –No termination

10 –Follows TMDS_CLOCK_RATIO_STATUS bit (default).

When = 1 termination value is 75 to 150 Ω:

When = 0 No termination

4:3

TERM

R/W

2’b10

11 –75 to 150 Ω:

Note: When TMDS_CLOCK_RATIO_STATUS bit reg0Bh[1] = 1

this register will automatically be set to 11 for 75 to 150 Ω but

can be overwritten using this address

Defines the DDC output speed for DDC bridge

0 –100 Kbps (default)

2

DDC_DR_SEL

1’b0

1 –400 Kbps

This field is updated from snoop of I2C write to target address

0xA8 offset 0x20 bit 1 that occurred on the SDA_SRC/

SCL_SRC interface. When bit 1 of address 0xA8 offset 0x20 is

written to a 1’b1 or read as a 1’b1, then this field will be set

to a 1’b1. When bit 1 of address 0xA8 offset 0x20 is written to

a 1’b0, then this field will be set to a 1’b0. This field is reset

to default value whenever HPD_SNK is de-asserted for greater

than 2 ms. The main function of this bit is to automatically set

the proper TX termination when value = 1.

1

TMDS_CLOCK_RATIO_STATUS

R/W/U

1’b0

0 –HDMI 1.4b (default)

1 –HDMI 2.0

Note 1. When DDC_TRAIN_SETDISABLE is 1’b0 this bit will

reflect the value of the DDC snoop.

Note 2. When DDC_TRAIN_SETDISABLE is 1’b1 this bit is set

by I2C and DDC snoop is ignored. If this bit was set to 1 during

snoop prior to the DDC_TRAIN_SETDISABLE being set to 1 it

will be cleared to 0.

This field indicate the DDC training block function status.

0 –DDC training enable (default)

1 –DDC training disable –DDC snoop disabled

Note 1. When DDC_TRAIN_SETDISABLE is 1’b0 the

TMDS_CLOCK_RATIO_STUATU bit will reflect the value of the

DDC snoop.

Note 2. When DDC_TRAIN_SETDISABLE is 1’b1, this bit is

set by I2C and DDC snoop is ignored and thus automatic TERM

control is ignored and must be manually set and

TMDS_CLOCK_RATIO_STATUS bit will be cleared.

Note 3. To go back to snoop and automatic TERM control this bit

has to be cleared and TERM set back to automatic control.

0

DDC_TRAIN_SETDISABLE

R/W

1’b0

8.5.8 CSR Bit Field Definitions –MISC CONTROL 0Ch (address = 0Ch)

图8-13. MISC CONTROL 0Ch Field Descriptions

7

6

5

4

3

2

1

0

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图8-13. MISC CONTROL 0Ch Field Descriptions (continued)

VSWING_DATA

VSWING_CLK

HDMI _TWPST1[1:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-13. MISC CONTROL 0Ch

Bit

Field

Type

Reset

Description

Data Output Swing Control

000 –Vsadj set (default)

001 –Increase by 7%

010 –Increase by 14%

011 –Increase by 21%

100 –Decrease by 30%

101 –Decrease by 21%

110 –Decrease by 14%

111 –Decrease by 7%

7:5

VSWING_DATA

R/W

3’b000

Clock Output Swing Control: Default is set by Vsadj resistor

value and the value of reg0Dh[0].

000 –Vsadj set (default)

001 –Increase by 7%

010 –Increase by 14% 011 –Increase by 21%

100 –Decrease by 30%

101 –Decrease by 21%

110 –Decrease by 14%

111 –Decrease by 7%

4:2

1:0

VSWING_CLK

R/W

3’b000

HDMI Pre-emphasis

00 –No Pre-emphasis (default)

01 –3.5 dB 10 –6 dB

HDMI _TWPST1[1:0]

2’b00

11 –Reserved

NOTE: See Pre-emphasis Section for 6 dB explanation during

normal operation supporting HDMI

8.5.9 CSR Bit Field Definitions, Equalization Control Register (address = 0Dh)

图8-14. Equalization Control Register

7

6

5

4

3

2

1

0

Reserved

Data Lane Fixed EQ Values

R/W

Clock EQ Values

DIS_HDMI

2_SWG

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-14. Equalization Control Register Field Descriptions

Bit

Field

Type

Reset

Description

Reserved

7

Reserved

R

1’b0

(Section 节8.3.6 and 表8-3 for values)

0000 –0 dB (default)

6:3

2:1

Data Lane Fixed EQ Values

Clock EQ Values

R/W

4’b0000

2’b00

00 –0 dB (default)

01 –1.5 dB

10 –3 dB

11 –4.5 dB

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表8-14. Equalization Control Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

Disables halving the clock output swing when entering HDMI 2.0

mode from TMDS_CLOCK_RATIO_STATUS.

0 –Disables TMDS_CLOCK_RATIO_STATUS control of the

clock VOD so output swing is at full swing (default)

1 –Clock VOD is half of set values when

0

DIS_HDMI 2_SWG

R/W

1’b0

TMDS_CLOCK_RATIO_STATUS states in HDMI 2.0 mode

8.5.10 CSR Bit Field Definitions, POWER MODE STATUS (address = 20h)

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图8-15. POWER MODE STATUS

7

6

5

4

3

2

1

0

Power Down

Status Bit

Standby Status Loss of Signal

Reserved

Bit

Status Bit –

LOS

R/U

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-15. POWER MODE STATUS Field Descriptions

Bit

Field

Type

Reset

Description

0 –Normal Operation

1 –Device in Power Down Mode.

7

Power Down Status Bit

R/U

1’b0

0 –Normal Operation

1 –Device in Standby Mode

6

Standby Status Bit

R/U

1’b0

0 –Clock present

1 –No Clock present

5

R/U

R

Loss of Signal Status Bit –LOS

1’b0

Reserved

4:0

Reserved

5’b00000

8.5.11 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 30h)

See 节8.3.12 and 节8.3.3. Note: DP-Mode is valid only when DP-Mode Register P0_Reg09[5] is set to one.

图8-16. DP-Mode and INDIVIDUAL LANE CONTROL

7

6

5

4

3

2

1

0

Data Rate Select

Clock Lane

R/W

Lane D0

R/W

Lane D1

R/W

Lane D2

R/W

Reserved

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-16. DP-Mode and INDIVIDUAL LANE CONTROL Field Descriptions

Bit

Field

Type

Reset

Description

00 –5.4 Gbps (default)

01 –2.7 Gbps

10 –1.62 Gbps

11 - Reserved

7:6

Data Rate Select

R/W

2’b00

0 –Disabled

1 –Enabled (default)

5

4

3

Clock Lane

Lane D0

R/W

1’b1

0 –Disabled

1 –Enabled (default)

0 –Disabled

1 –Enabled (default)

Lane D1

0 –Disabled

1 –Enabled (default)

2

Lane D2

R/W

R

1’b1

Reserved

1:0

Reserved

2’b00

8.5.12 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 31h)

See Section 节 8.3.12 and 节 8.3.3 Note: DP-Mode is valid only when DP-Mode Register P0_Reg09[5] is set to

one.

图8-17. DP-Mode and INDIVIDUAL LANE CONTROL

7

6

5

4

3

2

1

0

VOD Swing Adjust for CLK Lane

Pre-emphasis Adjust for CLK

Lane

Reserved

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图8-17. DP-Mode and INDIVIDUAL LANE CONTROL (continued)

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-17. DP-Mode and INDIVIDUAL LANE CONTROL Field Descriptions

Bit

Field

Type

Reset

Description

000 –Vsadj set (default)

001 –Increase by 7%

010 –Increase by 14%

011 –Increase by 21%

100 –Decrease by 30%

101 –Decrease by 21%

110 –Decrease by 14%

111 –Decrease by 7%

7:5

VOD Swing Adjust for CLK Lane

R/W

3’b000

Note: reg09h[6] = 1 otherwise all lanes are global control.

00 –No Pre-emphasis (default)

01 –3.5 dB Pre-emphasis.

10 –6 dB Pre-emphasis

11 –Reserved

Note 1. reg09h[6] = 1 otherwise all lanes are global control.

Note 2. If in HDMI mode writes will be ignored and reg09h[7]

SWAP = 0. No pre-emphasis on clock.

4:3

2:0

Pre-emphasis Adjust for CLK Lane

Reserved

R/W

2’b00

Reserved

3’b000

8.5.13 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 32h)

See Section 节 8.3.12 and 节 8.3.3 Note: DP-Mode is valid only when DP-Mode Register P0_Reg09[5] is set to

one

图8-18. DP-Mode and INDIVIDUAL LANE CONTROL

7

6

VOD Swing Adjust for D0 Lane

R/W

5

4

3

2

1

0

Pre-emphasis Adjust for D0 Lane

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-18. DP-Mode and INDIVIDUAL LANE CONTROL Field Descriptions

Bit

Field

Type

Reset

Description

000 –Vsadj set (default)

001 –Increase by 7%

010 –Increase by 14%

011 –Increase by 21%

100 –Decrease by 30%

101 –Decrease by 21%

110 –Decrease by 14%

11 –Decrease by 7%

7:5

VOD Swing Adjust for D0 Lane

R/W

3’b000

Note: reg09h[6] = 1 otherwise all lanes are global control.

00 –No Pre-emphasis (default)

01 –3.5 dB Pre-emphasis.

4:3

2:0

Pre-emphasis Adjust for D0 Lane

Reserved

R/W

2’b00

10 –6 dB Pre-emphasis

11 –Reserved

Note: reg09h[6] = 1 otherwise all lanes are global control.

Reserved

3’b000

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8.5.14 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 33h)

See Section 节 8.3.12 and 节 8.3.3 Note: DP-Mode is valid only when DP-Mode Register P0_Reg09[5] is set to

one

图8-19. DP-Mode and INDIVIDUAL LANE CONTROL

7

6

VOD Swing Adjust for D1 Lane

R/W

5

4

3

2

1

0

Pre-emphasis Adjust for D1 Lane

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-19. DP-Mode and INDIVIDUAL LANE CONTROL Field Descriptions

Bit

Field

Type

Reset

Description

000 –Vsadj set (default)

001 –Increase by 7%

010 –Increase by 14%

011 –Increase by 21%

100 –Decrease by 30%

101 –Decrease by 21%

110 –Decrease by 14%

11 –Decrease by 7%

7:5

VOD Swing Adjust for D1 Lane

R/W

3’b000

Note: reg09h[6] = 1 otherwise all lanes are global control.

00 –No Pre-emphasis (default)

01 –3.5 dB Pre-emphasis.

4:3

2:0

Pre-emphasis Adjust for D1 Lane

Reserved

R/W

2’b00

10 –6 dB Pre-emphasis

11 –Reserved

Note: reg09h[6] = 1 otherwise all lanes are global control.

Reserved

3’b000

8.5.15 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 34h)

See Section 节 8.3.12 and 节 8.3.3 Note: DP-Mode is valid only when DP-Mode Register P0_Reg09[5] is set to

one

图8-20. DP-Mode and INDIVIDUAL LANE CONTROL

7

6

VOD Swing Adjust for D2 Lane

R/W

5

4

3

2

1

0

Pre-emphasis Adjust for D2 Lane

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-20. DP-Mode and INDIVIDUAL LANE CONTROL Field Descriptions

Bit

Field

Type

Reset

Description

000 –Vsadj set (default)

001 –Increase by 7%

010 –Increase by 14%

011 –Increase by 21%

100 –Decrease by 30%

101 –Decrease by 21%

110 –Decrease by 14%

11 –Decrease by 7%

7:5

VOD Swing Adjust for D2 Lane

R/W

3’b000

Note: reg09h[6] = 1 otherwise all lanes are global control.

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表8-20. DP-Mode and INDIVIDUAL LANE CONTROL Field Descriptions (continued)

Bit

4:3

2:0

Field

Type

R/W

Reset

Description

00 –No pre-emphasis (default)

01 –3.5 dB pre-emphasis

10 –6 dB pre-emphasis

11 –Reserved

Note 1. reg09h[6] = 1 otherwise all lanes are global control.

Note 2. If in HDMI mode writes will be ignored and reg09h[7]

SWAP = 1. No pre-emphasis on clock.

Pre-emphasis Adjust for D2 Lane

Reserved

2’b00

3’b000

Reserved

8.5.16 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 35h)

See Section 节 8.3.12 and 节 8.3.3 Note: DP-Mode is valid only when DP-Mode Register P0_Reg09[5] is set to

one

图8-21. DP-Mode and INDIVIDUAL LANE CONTROL

7

6

5

4

3

2

1

0

Reserved

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-21. DP-Mode and INDIVIDUAL LANE CONTROL Field Descriptions

Bit

Field

Type

Reset

Description

Reserved

7:0

Reserved

R

‘h00

8.5.17 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Dh)

See Section 节 8.3.12 and 节 8.3.3 Note: DP-Mode is valid only when DP-Mode Register P0_Reg09[5] is set to

one

图8-22. DP-Mode and INDIVIDUAL LANE CONTROL

7

6

5

4

3

2

1

0

Reserved

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-22. DP-Mode and INDIVIDUAL LANE CONTROL Field Descriptions

Bit

Field

Type

Reset

Description

Reserved

7:0

Reserved

R

‘h00

8.5.18 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Eh)

See Section 节 8.3.12 and 节 8.3.3 Note: DP-Mode is valid only when DP-Mode Register P0_Reg09[5] is set to

one

图8-23. DP-Mode and INDIVIDUAL LANE CONTROL

7

6

5

4

3

2

1

0

Data Lane 1 Fixed EQ Values

R/W

Data Lane 2 Fixed EQ Values

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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表8-23. DP-Mode and INDIVIDUAL LANE CONTROL Field Descriptions

Bit

Field

Type

Reset

Description

Section 8.3.6 and Table 8 2 for values

0000 –0 dB (default)

7:4

Data Lane 1 Fixed EQ Values

Data Lane 2 Fixed EQ Values

R/W

4’b0000

Section 8.3.6 and Table 8 2 for values

0000 –0 dB (default)

3:0

R/W

4’b0000

8.5.19 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Fh)

See 节8.3.12 and 节8.3.3. Note: DP-Mode is valid only when DP-Mode Register P0_Reg09[5] is set to one

图8-24. DP-Mode and INDIVIDUAL LANE CONTROL

7

6

5

4

3

2

1

0

CLK Lane Fixed EQ Values

R/W

Data Lane 0 Fixed EQ Values

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-24. DP-Mode and INDIVIDUAL LANE CONTROL Field Descriptions

Bit

Field

Type

Reset

Description

Section 8.3.6 and Table 8 2 for values

0000 –0 dB (default)

7:4

CLK Lane Fixed EQ Values

R/W

4’b0000

Section 8.3.6 and Table 8 2 for values

0000 –0 dB (default)

3:0

Data Lane 0 Fixed EQ Values

R/W

4’b0000

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9 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

The TDP158 was designed to work mainly in source applications such as Blu-Ray DVD players, gaming

systems, desktops, notebooks, or AVRs. The following sections provide design consideration for various types of

applications.

9.2 Typical Application

图9-1 provides a schematic representation of what is considered a standard implementation.

HDMI/DVI Receptacle

0.1 µF

1

2

4

5

6

7

9

1

3

30

29

27

26

25

2

5

ML0p

ML0n

IN_D2p

OUT_D2p

TMDS_D2p

TMDS_D2n

TMDS_D1p

TMDS_D1n

TMDS_D0p

TMDS_D0n

TMDS_CLKp

GND1

GND2

IN_D2n

IN_D1p

OUT_D2n

OUT_D1p

OUT_D1n

OUT_D0p

OUT_D0n

OUT_CLKp

OUT_CLKn

8

4

0.1 µF

GND3

GND4

GND5

GND6

ML1p

ML1n

ML2p

ML2n

ML3p

11

14

17

6

0.1 µF

IN_D1n

IN_D0p

7

9

24

22

21

0.1 µF

IN_D0n

10

12

13

IN_CLKp

TMDS_CLKn

CEC

5 V

10

3

ML3n

HPD

IN_CLKn

CEC

20

21

22

23

2 k

CASE_GND1

CASE_GND2

CASE_GND3

CASE_GND4

HPD_SRC

32

33

28

15

16

19

38

39

DDC_SCL

DDC_SDA

HPD

SCL_SNK

SDA_SNK

HPD_SNK

SCL_SRC

SDA_SRC

DDC_SCL

DDC_SCA

DDC_SCL

DDC_SDA

DDC_SCL

DDC_SCA

VCC_3.3 V

1 M

0.01 µF

0 kΩ

100 k

0

0 kΩ

0

NOTE: Connector side DDC is 5 V

while GPU may require 3.3 V DDC so

a level shifter may need here

CAD_DET

2 k

13

14

8

SCL_CTL/SWAP

SDA_CTL/PRE

I2C_EN

TERM

I2C_SCL

I2C_SDA

16

17

23

Optional

EQ1/A0

EQ2/A1

SLEW

VCC_3.3 V

36

18

34

OE

10 µF

0.1 µF

0

VSADJ

CEC

6 k

1%

VDD_1.1 V

10 µF

15

35

GND

THERMAL PAD

GND

19 NC

0.1 µF

0.1 µF 0.01 µF 0.01 µF

Populated only when using I2C

Populated only when using Pin Strapping

12 20

31 40

11 37

VCC_3.3 V

VDD_1.1 V

图9-1. TDP158 in Source Side Application

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9.2.1 Design Requirements

The TDP158 can be designed into many different applications. In all the applications there are certain

requirements for the system to work properly. Two voltage rails are required to support the lowest power

consumption possible. The OE pin must have a 0.1-µF capacitor to ground. This pin can be driven by a

processor but the pin needs to change states after the voltage rails have stabilized. Using the I²C is the best way

to configure the device, but pin strapping is also provided as I²C, which is not available in all cases. As sources

may have many different naming conventions, it is necessary to confirm that the link between the source and the

TDP158 are correctly mapped. A swap function is provided for the input pins in case signaling is reversed

between source and the device. The following control pin values are based upon driving pins with a

microcontroller; otherwise, the shown pullup/down configuration meets the device levels. The following table

provides information on the expected values to perform properly.

For this design, use the parameters shown in 表9-1.

表9-1. Design Parameters

Design Parameter

Value

3.3 V

V_CC

V_DD

1.1 V

Main Link Input Voltage

Control Pin Max Voltage for Low

Control Pin Voltage Range Mid

Control Pin Min Voltage for High

R_(VSADJ)Resistor

V_ID= 0.15 to 1.4 Vpp

Connect to 1 kΩpulldown resistor to GND

Connect to 1 kΩpullup resistor to V_CC

6.49 kΩ 1%

9.2.2 Detailed Design Procedure

9.2.2.1 Source Side

The TDP158 is a signal conditioning device that provides several forms of signal conditioning to support

compliance for HDMI or DVI at a source connector. These forms of signal conditioning are accomplished using

receive equalization, retiming, and output driver configurability. The transmitter will drive 1”–2”of board trace

and connector when compliance is required at the connector.

To design in the TDP158 the following need to be understood for a source side application:

• Determine the loss profile between the GPU/chipset and the HDMI /DVI connector.

• Based upon this loss profile and signal swing determine optimal location for the TDP158, to pass source

electrical compliance. Usually within 1”–2”of the connector.

• Use the typical application 图9-1 for information on control pin resistors.

• The TDP158 has a receiver equalizer but can also be configured using EQ1 and EQ2 control pins.

• Set the V_OD, pre-emphasis, termination, and edge rate levels appropriately to support compliance by using

the appropriate VSADJ resistor value and setting SDA_CTL/PRE, TERM and SLEW control pins.

• The thermal pad must be connected to ground.

• See schematics in 图9-1 on recommended decouple caps from V_CCpins to ground.

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9.2.2.2 DDC Pull Up Resistors

This section is for information only and subject to change depending upon system implementation. The pull-up

resistor value is determined by two requirements:

1. The maximum sink current of the I²C buffer:

The maximum sink current is 3 mA or slightly higher for an I²C driver supporting standard-mode I²C

operation.

V_CC

R_UP(min)

=

I_sink

(1)

2. The maximum transition time on the bus:

The maximum transition time, T, of an I²C bus is set by an RC time constant, where R is the pull-up resistor

value, and C is the total load capacitance. The parameter, k, can be calculated from 方程式3 by solving for t,

the times at which certain voltage thresholds are reached. Different input threshold combinations introduce

different values of t. 表9-2 summarizes the possible values of k under different threshold combinations.

T = k ì RC

(2)

-t

V(t)=V_DDì (1 - e ^RC

)

(3)

表9-2. Value k upon Different Input Threshold Voltages

V_th-\V_th+

0.1 V_CC

0.15 V_CC

0.2 V_CC

0.25 V_CC

0.3 V_CC

0.7 V_CC

1.0986

1.0415

0.9808

0.9163

0.8473

0.65 V_CC

0.9445

0.8873

0.8267

0.7621

0.6931

0.6 V_CC

0.8109

0.7538

0.6931

0.6286

0.5596

0.55 V_CC

0.6931

0.6360

0.5754

0.5108

0.4418

0.5 V_CC

0.5878

0.5306

0.4700

0.4055

0.3365

0.45 V_CC

0.4925

0.4353

0.3747

0.3102

0.2412

0.4 V_CC

0.4055

0.3483

0.2877

0.2231

0.1542

0.35 V_CC

0.3254

0.2683

0.2076

0.1431

0.0741

0.3 V_CC

0.2513

0.1942

0.1335

0.0690

From 方程式 1, Rup(min) = 5.5 V/3 mA = 1.83 kΩ to operate the bus under a 5-V pull-up voltage and provide

less than 3 mA when the I²C device is driving the bus to a low state. If a higher sink current, for example 4 mA,

is allowed, Rup(min) can be as low as 1.375 kΩ.

If DDC working at standard mode of 100 Kbps, the maximum transition time T is fixed, 1 μs, and using the k

values from 表 9-2, the recommended maximum total resistance of the pull-up resistors on an I²C bus can be

calculated for different system setups. If DDC working in fast mode of 400 Kbps, the transition time should be set

at 300 ns according to I²C specification.

To support the maximum load capacitance specified in the HDMI spec, C_(cable)(max) = 700 pF, C_(source)= 50 pF,

C_I= 50 pF, R(max) can be calculated as shown in 表9-3.

表9-3. Pull-Up Resistor Upon Different Threshold Voltages and 800-pF Loads

V_th-\V_th+

0.1 V_CC

0.15 V_CC

0.2 V_CC

0.25 V_CC

0.3 V_CC

0.7 V_CC

1.14

1.2

0.65 V_CC

0.6 V_CC

1.54

1.66

1.8

0.55 V_CC

0.5 V_CC

0.45 V_CC

0.4 V_CC

3.08

3.59

4.35

5.6

0.35 V_CC

0.3 V_CC

UNIT

kΩ

1.32

1.8

2.13

2.54

3.84

4.97

1.41

1.97

2.36

2.87

4.66

6.44

kΩ

1.27

1.36

1.48

1.51

2.17

2.66

3.34

6.02

9.36

kΩ

1.64

1.99

2.23

2.45

3.08

4.03

8.74

18.12

kΩ

1.8

2.83

3.72

5.18

8.11

16.87

kΩ

—

42

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To accommodate the 3-mA drive current specification, a narrower threshold voltage range is required to support

a maximum 800-pF load capacitance for a standard-mode I²C bus.

9.2.3 Application Curves

图9-3. Output Eye from High Loss Input Eye at

图9-2. High Loss Input Eye −20”4 mil Trace at

TDP158 Pin

图9-4. HDMI 2 Compliance Eye from High Loss Input Eye

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9.2.4 Application with DDC Snoop

9.2.4.1 Source Side HDMI Application

In source side applications, the TDP158 takes an AC-coupled HDMI signal and provides signal conditioning and

level shifting to support TMDS signaling. 图 9-5 provides an example of a DDC snoop version. Notes in both

schematics provide important system design considerations. To help reduce overall EMI in a system the VCC

and VDD decoupling caps need to be as close to the pins as possible. The drawings shown one set but multiple

sets may be needed for each pin.

Control pins should be tied to 1 kΩ pullup to VCC, 1 kΩ pulldown to GND, or left floating. Drawings show 0-Ω

resistors as this provides flexibility. In noisy systems a 0.1-µF capacitor to GND may reduce glitches on these

pins and are not shown in the drawings. As 图 9-5 shows, connect the DDC source and sink pins to GND as the

SCL/SDA_SRC if an application requires the DDC source and sink pins to be completely bypassed. If this is

done, then the TX termination must be controlled by the TERM pin or through I²C.

HDMI/DVI Receptacle

0.1 µF

1

2

4

5

6

7

9

1

3

30

29

27

26

25

2

5

ML0p

ML0n

IN_D2p

OUT_D2p

TMDS_D2p

TMDS_D2n

TMDS_D1p

TMDS_D1n

TMDS_D0p

TMDS_D0n

TMDS_CLKp

GND1

GND2

IN_D2n

IN_D1p

OUT_D2n

OUT_D1p

OUT_D1n

OUT_D0p

OUT_D0n

OUT_CLKp

OUT_CLKn

8

4

0.1 µF

GND3

GND4

GND5

GND6

ML1p

ML1n

ML2p

ML2n

ML3p

11

14

17

6

0.1 µF

IN_D1n

IN_D0p

7

9

24

22

21

0.1 µF

IN_D0n

10

12

13

IN_CLKp

TMDS_CLKn

CEC

5 V

10

3

ML3n

HPD

IN_CLKn

CEC

20

21

22

23

2 k

CASE_GND1

CASE_GND2

CASE_GND3

CASE_GND4

HPD_SRC

32

33

28

15

16

19

DDC_SCL

DDC_SDA

HPD

SCL_SNK

SDA_SNK

HPD_SNK

VCC_3.3 V

2 k

38

39

DDC_SCL

DDC_SDA

SCL_SRC

SDA_SRC

VCC_3.3 V

1 M

0.01 µF

0 kΩ

100 k

0

0 kΩ

0

CAD_DET

2 k

13

14

8

VCC_3.3 V

SCL_CTL/SWAP

SDA_CTL/PRE

I2C_EN

TERM

I2C_SCL

I2C_SDA

16

17

23

10 µF

0.1 µF

Optional

EQ1/A0

EQ2/A1

SLEW

36

18

34

OE

0.1 µF

0

VSADJ

CEC

6 k

1%

AUXp

VDD_1.1 V

10 µF

15

35

GND

THERMAL PAD

GND

19 NC

0.1 µF

0.1 µF 0.01 µF 0.01 µF

Populated only when using I2C

Populated only when using Pin Strapping

12 20

31 40

11 37

VCC_3.3 V

VDD_1.1 V

图9-5. TDP158 Source Side Application with DDC Snoop

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9.2.5 9.1.2 Source Side HDMI /DP Application Using DP-Mode

The TDP158 has a special mode that will allow the device to support either HDMI or DP applications. The device

is put into this mode by setting reg09h[5] to 1. The device will self-configure with the following settings and

become I²C programmable only. The TDP158 does not support automatic Link Training for DisplayPort. AUX

channel bypasses device.

• All four lanes are turned on and configured for 5.4 Gbps data rate.

• Sets V_ODswing to ≅ 410 mV (This value is based upon a VSADJ value of 6 kΩ).

• Reg0Ch[7:5] is used to control VOD swing for all lanes.

• Reg0Ch[1:0] is used to control pre-emphasis for all lanes.

• Reg30h[7:2] is used to turn on or off individual lanes as well as informing the TDP158 what the data rate is.

This is used for the delay component for pre-emphasis signal.

For DisplayPort the link is AC coupled. This shows

one way of doing this otherwise the capacitors

could be moved to a dongle or the end equipment.

30

IN_D2p

HDMI/DVI Receptacle or

DP Receptacle

0.1 µF

1

2

4

5

6

7

9

1

3

2

5

ML0p

ML0n

OUT_D2p

TMDS_D2p

TMDS_D2n

TMDS_D1p

TMDS_D1n

TMDS_D0p

TMDS_D0n

TMDS_CLKp

GND1

GND2

0.1 µF

29

27

26

25

IN_D2n

IN_D1p

OUT_D2n

OUT_D1p

OUT_D1n

OUT_D0p

OUT_D0n

OUT_CLKp

OUT_CLKn

8

4

0.1 µF

GND3

GND4

GND5

GND6

ML1p

ML1n

ML2p

ML2n

ML3p

11

14

17

6

0.1 µF

IN_D1n

IN_D0p

7

9

24

22

21

0.1 µF

IN_D0n

10

12

13

IN_CLKp

TMDS_CLKn

CEC

5 V

10

3

ML3n

HPD

IN_CLKn

0.1 µF

CEC

20

21

22

23

2 k

CASE_GND1

CASE_GND2

CASE_GND3

CASE_GND4

HPD_SRC

32

33

28

15

16

19

DDC_SCL

DDC_SDA

HPD

SCL_SNK

SDA_SNK

HPD_SNK

VCC_3.3 V

2 k

38

39

DDC_SCL

DDC_SDA

SCL_SRC

SDA_SRC

VCC_3.3 V

1 M

0.01 µF

AUXp

AUXn

100 k

AUXn

0

CAD_DET

2 k

13

14

8

VCC_3.3 V

SCL_CTL/SWAP

SDA_CTL/PRE

I2C_EN

TERM

I2C_SCL

I2C_SDA

16

17

23

10 µF

0.1 µF

Optional

0.1 µF

36

18

EQ1/A0

EQ2/A1

SLEW

OE

34

VSADJ

CEC

6 k

1%

0

AUXp

AUXn

AUXp

AUXn

I2C Programming

only so these can

be left floating

15

35

GND

VDD_1.1 V

10 µF

GND

THERMAL PAD

19 NC

0.1 µF

0.1 µF 0.01 µF 0.01 µF

12 20

31 40

11 37

VCC_3.3 V

VDD_1.1 V

图9-6. TDP158 in Dual Role Source Side Application

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10 Power Supply Recommendations

10.1 Power Management

To minimize the power consumption of customer application, TDP158 used the dual power supply. V_CCis 3.3 V

with 10% range to support the I/O voltage. The V_DDis 1.1 V with ≅ 5% range to supply the internal digital control

circuit. TDP158 operates in 3 different working states.

• Power Down mode:

– When OE = Low, the device will put itself into the lowest power state by shutting down all function blocks.

• OE re-asserted means the pin transitions from low to high. Transitioning the OE pin from L →H

creates a reset. If the device is programmed through I²C, then it must be reprogrammed.

– Writing a 1 to register 09h[3].

– OE = High, HPD_SNK = Low for > 2 ms

• Standby mode:

– HPD_SNK = High but no valid clock signal detect on clock lane.

• Normal operation:

– When HPD assert, the device output will enable based on the signal detector circuit result.

– HPD_SRC = HPD_SNK in all conditions. The HPD channel operational when V_CCover 3 V.

备注

When the TDP158 is put into a power down state the I²C registers are cleared. This is important as

the TMDS_CLOCK_RATIO_STATUS bit will be cleared. If cleared and HDMI 2.0 resolutions are to be

supported the TDP158 expects the source to write a 1 to this bit location. If the read has the bit set,

the TDP158 will set this bit; otherwise, the source termination must be set manually.

10.2 Standby Power

The TDP158/I implement a two stage standby power process.

Stage 1: If there is no signal on the clock line, then the maximum I_VCC≅ 7 mA and maximum I_VDD≅ 7 mA.

Stage 2: If a signal (like a noise or clock signal) is on the clock line, then the TDP158 investigates the clock line

for 3 μs to 5 μs and detects if a signal is present.

• If a clock is detected, then the TDP158 will go into normal operation.

• If it is determined that no clock is present, then the TDP158 will re-enter stage 1.

In stage 2; maximum I_VCC≅ 7 mA and maximum I_VDD≅ 27 mA.

表10-1. Power Modes

INPUTS

STATUS

OUT_Dx

OUT_CLK

OE

L

HPD_SNK

Reg09[2]

IN_CLK

HPD_SRC

H

IN_Dx

High-Z

SDA/SCL_CTL

DDC

Disabled

Active

Mode

Power Down

Mode

X

1

X

Disable

Active

High-Z

Normal

operation

H

HPD_SNK

RX Active

TX Active

Standby Mode

(Squelch

waiting)

No Valid TMDS

Clock

D0-D2 Disabled

IN_CLK Active

H

X

H

1

0

HPD_SNK

Active

High-Z

TX Active

High-Z

Active

Valid TMDS

Clock

Normal

operation

RX Active

Standby Mode

(Squelch

waiting)

No Valid TMDS

Clock

D0-D2 Disabled

IN_CLK Active

Valid TMDS

Clock

Normal

operation

RX Active

TX Active

46

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11 Layout

11.1 Layout Guidelines

For the TDP158 on a high-K board, it is required to solder the PowerPAD^™onto the thermal land to ground. A

thermal land is the area of solder-tinned-copper underneath the PowerPAD™ package. On a high-K board the

TDP158 can operate over the full temperature range by soldering the PowerPAD™ onto the thermal land. On a

low-K board, for the device to operate across the temperature range on a low-K board, a 1-oz Cu trace

connecting the GND pins to the thermal land must be used. A simulation shows R_θJA= 100.84°C/W allowing

545 mW power dissipation at 70°C ambient temperature. A general PCB design guide for PowerPAD packages

is provided in the document SLMA002. TI recommends using a four layer stack up at a minimum to accomplish a

low-EMI PCB design. TI recommends six layers as the TDP158 is a two voltage rail device.

• Routing the high-speed TMDS traces on the top layer avoids the use of vias, avoids the introduction of their

inductances, and allows for clean interconnects from the HDMI connectors to the Redriver inputs and

outputs. It is important to match the electrical length of these high speed traces to minimize both inter-pair

and intra-pair skew.

• Placing a solid ground plane next to the high-speed single layer establishes controlled impedance for

transmission link interconnects and provides an excellent low –inductance path for the return current flow.

• Placing a power plane next to the ground plane creates and additional high-frequency bypass capacitance.

• Routing slower seed control signals on the bottom layer allows for greater flexibility as these signal links

usually have margin to tolerate discontinuities such as vias.

• If an additional supply voltage plane or signal layer is needed, add a second power/ground plane system to

the stack to keep symmetry. This makes the stack mechanically stable and prevents it from warping. Also the

power and ground plane of each power system can be place closer together, thus increasing the high

frequency bypass capacitance significantly.

Layer 1: TMDS signal layer

5 to 10

mils

Layer 2: Ground Plane

Layer 3: V_CCPower Plane

20 to 40

mils

Layer 4: V_DDPower Plane

Layer 5: Ground Plane

Layer 3: Power Plane

5 to 10

mils

Layer 4: Control signal layer

Layer 6: Control signal layer

图11-1. Recommended 4 –or 6 –Layer PCB Stack

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11.2 Layout Example

SLEW

SCL_SRC

SDA_SNK

SCL_SNK

2kQ

V_CC

2kQ

5V

2kQ

V_CC

SDA_SRC

Match High Speed traces

length as close as possible to

minimize Ske

100nF

IN_D2p/n

100nF

Match High Speed traces

length as close as possible to

minimize Ske

1

OUT_D2p/n

HPD_SRC

HPD_SNK

100nF

IN_D1p/n

OUT_D1p/n

100nF

GND

IN_D0p/n

OUT_D0p/n

V_CC

100nF

1lQ

V_CC

A1/EQ2

I2C_EN

GND

1lQ

GND

OUT_CLKp/n

100nF

IN_CLKp/n

100nF

Place V_CCand V_DDdecoupling

caps as close to V_CCand V_DD

pins as possible

1lQ

GND

SWAP

SCL_CTL

2kO/1lQ

V_CC

For I2C only Pop pull up and

use 2 lQ

2kO/1lQ

V_CC

DE

VSADJ

SDA_CTL

For DE and SWAP only Pop pull up

or pull down and use 65 lQ

TERM

A0/EQ1

The differential input lanes and differential output lanes should be separated as close to the TDP158 as feasible to minimize crosstalk.

Adding a ground flood plain between each differential lane further reduces crosstalk and thus improves signal integrity at high speed

data rates.

图11-2. Example Layout for Source Side Application

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, PowerPAD Thermally Enhanced Package

• [HDMI ] High-definition Multimedia Interface CTS Version 1.4b October, 2011

• [HDMI ] High-definition Multimedia Interface CTS Version 2.0o June 2016

• [HDMI ] High-definition Multimedia Interface Specification Version 1.4b October, 2011

• [HDMI ] High-definition Multimedia Interface Specification Version 2.0 September 4, 2013

• [I2C] The I2C-Bus specification version 2.1 January 2000

12.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.4 Trademarks

TMDS^™is a trademark of Wabtec Holding Corp.

HDMI ^™is a trademark of HDMI Licensing Administrator, Inc.

DisplayPort^™is a trademark of Video Electronics Standards Association.

Blu-ray^™is a trademark of Blu-ray Disc Accociation.

PowerPAD^™and TI E2E^™are trademarks of Texas Instruments.

所有商标均为其各自所有者的财产。

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

RSB0040E

WQFN - 0.8 mm max height

S

C

A

L

E

2

.

7

0

PLASTIC QUAD FLATPACK - NO LEAD

5.1

4.9

B

A

PIN 1 INDEX AREA

5.1

4.9

C

0.8 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X 3.6

(0.2) TYP

EXPOSED

11

20

THERMAL PAD

36X 0.4

10

21

2X

41

SYMM

3.6

3.15 0.1

1

30

0.25

0.15

40X

40

31

PIN 1 ID

(OPTIONAL)

0.1

C A B

SYMM

0.5

0.3

0.05

40X

4219096/A 11/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RSB0040E

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

3.15)

SYMM

40

31

40X (0.6)

40X (0.2)

1

30

36X (0.4)

41

SYMM

(4.8)

(1.325)

(

0.2) TYP

VIA

10

21

(R0.05)

TYP

11

20

(1.325)

(4.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219096/A 11/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RSB0040E

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(0.785)

4X ( 1.37)

40

31

40X (0.6)

1

30

40X (0.2)

36X (0.4)

SYMM

(0.785)

(4.8)

41

(R0.05) TYP

10

21

METAL

TYP

20

11

SYMM

(4.8)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD 41

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4219096/A 11/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TDP158
厂家：	TEXAS INSTRUMENTS
描述：	6Gbps DP++ 1.1 至 HDMI 2.0 转接驱动器驱动驱动器
文件：	总58页 (文件大小：2260K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TDP158 [TI]

相关型号：

TDP158RSBR

TDP158RSBT

TDP16011001AUF

TDP16011001BUF

TDP16011001CUF

TDP16011001DUF

TDP16011001EUF

TDP16011001FUF

TDP16011002AUF

TDP16011002BUF

TDP16011002CUF

TDP16011002DUF