TFP401A-Q1 [TI]
汽车类 Panelbus ™ DVI 接收器 165MHz、HSYNC 抗抖动;
| 型号： | TFP401A-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 Panelbus ™ DVI 接收器 165MHz、HSYNC 抗抖动 |
| 文件： | 总36页 (文件大小：2469K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TFP401A-Q1
ZHCSAH8B –NOVEMBER 2012 –REVISED MARCH 2022
TFP401A-Q1 TI Panelbus™ 汽车类数字接收器
1 特性
3 说明
• 符合汽车应用要求
• 具有符合AEC-Q100 标准的下列特性：
德州仪器 (TI) 的 TFP401A-Q1 器件是一款 TI
Panelbus™ 平板显示产品，是全系列兼容端到端 DVI
1.0 解决方案的一部分。主要针对的是台式机 LCD 显
示器和数字投影仪，TFP401A-Q1 器件可应用于任何
需要高速数字接口的设计中。
– 器件温度等级3：-40°C 至85°C 环境工作温度
范围
– 器件HBM ESD 分类等级H2
– 器件CDM ESD 分类等级C3B
• 支持高达165 MHz 的像素速率（包括60Hz 时的
1080p 和WUXGA）
TFP401A-Q1 器件支持高达 1080p 的显示分辨率和 24
位真彩色像素格式的 WUXGA。它还具有设计灵活
性，可在每个时钟内驱动 1 个或 2 个像素，支持 TFT
或 DSTN 面板并提供用时间触发的像素输出来减少接
地反弹的选项。
• 符合数字可视化接口(DVI) 技术规范1
• 真彩色，24 位/像素，1670 万种颜色（每时钟驱动
1 或2 个像素）
PowerPAD 先进的封装技术可获得业界最佳的功率耗
散、封装尺寸和超低接地电感。
• 通过激光修整内部端接电阻器，实现出色的固定阻
抗匹配
• 高达1 个像素时钟周期的偏移容限
• 4 倍过采样
• 降低功耗：1.8V 内核运行，3.3V I/O 和电源2
• 使用错时像素输出来减少接地反弹
• 使用TI PowerPAD™ 封装实现低噪声和良好的功率
耗散
TFP401A-Q1 将创新的 Panelbus 电路与 TI 先进的
0.18 µm EPIC-5™ CMOS 工艺技术以及 TI 的
PowerPAD 封装技术组合在一起，用于实现可靠的低
功耗、低噪声、高速数字接口解决方案。
器件信息(1)
• 采用TI 0.18µm EPIC-5™ CMOS 工艺的先进技术
• TFP401A-Q1 具有HSYNC 抖动抗扰能力3
封装尺寸（标称值）
器件型号
封装
TFP401A-Q1
PQFP (100)
14.00mm × 14.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
• 高清电视
• 高清PC 显示器
• 数字视频
• 高清投影仪
• DVI/HDMI 接收器4
Copyright © 2017, Texas Instruments Incorporated
TFP401A-Q1 框图
1
TFP401A-Q1 器件包含可以从DVI 发送器创建稳定HSYNC 的附加电路，这些发送器会在已发送的HSYNC 信号上引入有害抖动。
TFP401A-Q1 器件具有一个内部稳压器，可通过外部3.3V 电源提供1.8V 内核电源。
数字可视化接口规范(DVI) 是数字显示工作组(DDWG) 为了与数字显示屏建立高速数字连接而开发的一个行业标准。TFP401A-Q1 与
DVI 技术规范修订版本1.0 兼容。
2
3
4
仅HDMI 视频
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLDS190
TFP401A-Q1
ZHCSAH8B –NOVEMBER 2012 –REVISED MARCH 2022
www.ti.com.cn
Table of Contents
7.1 Overview...................................................................12
7.2 Functional Block Diagram.........................................12
7.3 Feature Description...................................................12
7.4 Device Functional Modes..........................................15
8 Application and Implementation..................................17
8.1 Application Information............................................. 17
8.2 Power Supply Recommendations.............................21
8.3 Layout....................................................................... 21
9 Device and Documentation Support............................27
9.1 接收文档更新通知..................................................... 27
9.2 支持资源....................................................................27
9.3 Trademarks...............................................................27
9.4 Electrostatic Discharge Caution................................27
9.5 术语表....................................................................... 27
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information....................................................6
6.5 DC Digital I/O Electrical Characteristics......................7
6.6 DC Electrical Characteristics...................................... 7
6.7 AC Electrical Characteristics ......................................7
6.8 Timing Requirements..................................................8
6.9 Switching Characteristics..........................................10
6.10 Typical Characteristics............................................ 11
7 Detailed Description......................................................12
Information.................................................................... 27
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (January 2017) to Revision B (March 2022)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• Added the Thermal Package information to the Pin Functions table..................................................................3
• Added TFP401A-Q1 to the Imax vs Input Frequency figure............................................................................. 11
• Added sentence to end of first paragraph that recommends soldering package thermal pad to PCB in order to
minimize stress on peripheral pins................................................................................................................... 26
Changes from Revision * (November 2012) to Revision A (January 2017)
Page
• 添加了器件信息表、引脚配置和功能部分、ESD 等级表、应用和实施部分、电源相关建议部分、布局部
分、器件和文档支持部分以及机械、封装和可订购信息部分............................................................................ 1
• 将特性部分中的“器件HBM ESD 分类等级C3B”更改为“器件CDM ESD 分类等级C3”...........................1
• Changed the Operating free-air temperature MIN value From: 0°C To: –40°C and the MAX value From: 70°C
To: 85°C in the Recommended Operating Conditions .......................................................................................6
• Changed the Thermal Information table values..................................................................................................6
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5 Pin Configuration and Functions
76
OGND
QO23
OVDD
AGND
Rx2+
Rx2−
AVDD
AGND
AVDD
Rx1+
Rx1−
AGND
AVDD
AGND
Rx0+
Rx0−
QO1
QO0
HSYNC
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
77
78
79
VSYNC
DE
80
81
OGND
ODCK
OVDD
CTL3
CTL2
CTL1
GND
DVDD
QE23
QE22
QE21
QE20
QE19
QE18
QE17
QE16
OVDD
OGND
QE15
QE14
82
83
84
85
86
87
88
Thermal Pad
89
90
91
92
AGND
RxC+
RxC−
AVDD
93
94
95
96
EXT_RES
97
PVDD
98
PGND
RSVD
OCK_INV
99
100
图5-1. PZP Package, 100-Pin PQFP PowerPAD Package (Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
AGND
AVDD
NO.
79, 83, 87, 89,
92
GND
VDD
DO
Analog ground –Ground reference and current return for analog circuitry
Analog VDD –Power supply for analog circuitry. Nominally 3.3 V
82, 84, 88, 95
42, 41, 40
General-purpose control signals –Used for user-defined control. CTL1 is not powered down
through PDO.
CTL[3:1]
Output data enable –Used to indicate time of active video display versus non-active display or
blank time. During blank, the device transmits only HSYNC, VSYNC, and CTL[3:1]. During times
of active display, or non-blank, the device transmits only pixel data, QE[23:0], and QO[23:0].
High: Active display time
DE
46
1
DO
DI
Low: Blank time
Output clock data format –Controls the output clock (ODCK) format for either TFT or DSTN
panel support. For TFT support, the ODCK clock runs continuously. For DSTN support, ODCK
only clocks when DE is high; otherwise, ODCK remains low when DE is low.
High: DSTN support –ODCK held low when DE = low
DFO
Low: TFT support –ODCK runs continuously.
GND
5, 39, 68
6, 38, 67
GND
VDD
Digital ground –Ground reference and current return for digital core
Digital VDD –Power supply for digital core. Nominally 3.3 V.
DVDD
Internal impedance matching –The TFP401A-Q1 device has internal optimization for impedance
matching at 50 Ω. An external resistor tied to this pin has no effect on device performance.
EXT_RES
96
AI
HSYNC
RSVD
48
99
DO
DI
Horizontal sync output
Reserved. Tie this pin high for normal operation.
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表5-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
18, 29, 43, 57,
78
OVDD
VDD
DO
Output driver VDD –Power supply for output drivers. Nominally 3.3 V
Output data clock –Pixel clock. The device synchronizes all pixel outputs QE[23:0] and QO[23:0]
(if in 2-pixels-per-clock mode), along with DE, HSYNC, VSYNC and CTL[3:1], to this clock.
ODCK
OGND
44
19, 28, 45, 58,
76
GND
Output driver ground –Ground reference and current return for digital output drivers
ODCK polarity –Selects ODCK edge to which pixel data (QE[23:0] and QO[23:0]) and control
signals (HSYNC, VSYNC, DE, CTL[3:1]) latch.
Normal mode:
High: Latches output data on rising ODCK edge
Low: Latches output data on falling ODCK edge
OCK_INV
100
DI
DI
Power down –An active-low signal that controls the TFP401A-Q1 power-down state. During
power down, all output buffers switch to a high-impedance state. The device powers down all
analog circuits and disables all inputs, except for PD.
If leaving PD unconnected, an internal pullup defaults the TFP401A-Q1 device to normal
operation.
PD
2
High : Normal operation
Low: Power down
Output drive power down –An active-low signal that controls the power-down state of the output
drivers. During output drive power down, the output drivers (except SCDT and CTL1) are driven to
a high-impedance state. When PDO is left unconnected, an internal pullup defaults the TFP401A-
Q1 device to normal operation.
PDO
9
DI
High: Normal operation; output drivers on
Low: Output drive powered down
PGND
98
GND
PLL GND –Ground reference and current return for internal PLL.
Pixel select –Selects between 1- and 2-pixels-per-clock output modes. During the 2-pixels-per-
clock mode, the device outputs both even pixels, QE[23:0], and odd pixels, QO[23:0], in tandem
on a given clock cycle. During 1-pixel-per-clock mode, the device outputs even and odd pixels
sequentially, one at a time, with the even pixel first, on the even-pixel bus, QE[23:0]. (The first
pixel per line is pixel-0, the even pixel. The second pixel per line is pixel-1, the odd pixel).
High: 2 pixels per clock
PIXS
4
DI
Low: 1 pixel per clock
PVDD
97
VDD
DO
PLL VDD –Power supply for internal PLL
Even green-pixel output –Output for even and odd green pixels when in 1-pixel-per-clock mode.
Output for even-only green pixel when in 2-pixels-per-clock mode. Output data synchronizes to the
output data clock, ODCK.
LSB: QE8, pin 20
QE[8:15]
20–27
MSB: QE15, pin 27
Even red-pixel output –Output for even and odd red pixels when in 1-pixel-per-clock mode.
Output for even-only red pixel when in 2-pixels-per-clock mode. Output data synchronizes to the
QE[16:23]
QO[0:7]
DO
DO
DO
30–37
49–56
59–66
output data clock, ODCK.
LSB: QE16, pin 30
MSB: QE23, pin 37
Odd blue-pixel output –Output for odd-only blue pixel when in 2-pixels-per-clock mode. Not
used, and held low, when in 1-pixel-per-clock mode. Output data synchronizes to the output data
clock, ODCK.
LSB: QO0, pin 49
MSB: QO7, pin 56
Odd green-pixel output –Output for odd-only green pixel when in 2-pixels-per-clock mode. Not
used, and held low, when in 1-pixel-per-clock mode. Output data synchronizes to the output data
clock, ODCK.
QO[8:15]
LSB: QO8, pin 59
MSB: QO15, pin 66
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表5-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
Odd red-pixel output –Output for odd-only red pixel when in 2-pixels-per-clock mode. Not used,
and held low, when in 1-pixel-per-clock mode. Output data synchronizes to the output data clock,
QO[16:23]
DO
69–75, 77
ODCK.
LSB: QO16, pin 69
MSB: QO23, pin 77
Even blue-pixel output –Output for even and odd blue pixels when in 1-pixel-per-clock mode.
Output for even-only blue pixel when in 2-pixels-per-clock mode. Output data synchronizes to the
QE[0:7]
DO
10–17
output data clock, ODCK.
LSB: QE0, pin 10
MSB: QE7, pin 17
Clock positive receiver input –Positive side of reference clock. TMDS low-voltage signal
differential-input pair.
RxC+
93
94
AI
AI
Clock negative receiver input –Negative side of reference clock. TMDS low-voltage signal
differential-input pair.
RxC–
Channel-0 positive receiver input –Positive side of channel-0. TMDS low-voltage signal
differential-input pair.
Channel-0 receives blue pixel data in active display and HSYNC, VSYNC control signals in blank.
Rx0+
Rx0–
Rx1+
Rx1–
Rx2+
Rx2–
90
91
85
86
80
81
AI
AI
AI
AI
AI
AI
Channel-0 negative receiver input –Negative side of channel-0. TMDS low-voltage signal
differential-input pair.
Channel-1 positive receiver input –Positive side of channel-1 TMDS low-voltage signal
differential-input pair.
Channel-1 receives green-pixel data in active display and CTL1 control signals in blank.
Channel-1 negative receiver input –Negative side of channel-1 TMDS low-voltage signal
differential-input pair.
Channel-2 positive receiver input –Positive side of channel-2 TMDS low-voltage signal
differential-input pair.
Channel-2 receives red-pixel data in active display and CTL2, CTL3 control signals in blank.
Channel-2 negative receiver input –Negative side of channel-2 TMDS low-voltage signal
differential-input pair
Sync detect - Output to signal when the link is active or inactive. The link is active when DE is
actively switching. The TFP401A-Q1 device monitors the state of DE to determine link activity.
SCDT can be tied externally to PDO to power down the output drivers when the link is inactive.
High: Active link
SCDT
ST
8
3
DO
DI
Low: Inactive link
Output drive strength select –Selects output drive strength for high- or low-current drive. (See dc
specifications for IOH and IOL versus the ST state).
High: High drive strength
Low: Low drive strength
Staggered pixel select –An active-low signal used in the 2-pixels-per-clock pixel mode (PIXS =
high). Time-staggers the even and odd pixel outputs to reduce ground bounce. Normal operation
outputs the odd and even pixels simultaneously.
STAG
7
DI
High: Normal simultaneous even-and-odd pixel output
Low: Time-staggered even-and-odd pixel output
VSYNC
47
DO
Vertical sync output
Thermal pad. Recommend soldering the package thermal pad to thermal pad on PCB. Soldering
the thermal pad will help to release stress through the solder, otherwise the stress will be
absorbed by the peripheral pins.
Thermal Pad
—
(1) DI = Digital Input; DO = Digital Output; AI = Analog Input; AO = Analog Output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
–0.3
–0.3
–40
–65
MAX
4
UNIT
V
Supply-voltage range
DVDD, AVDD, OVDD, PVDD
Input-voltage range, logic and analog signals
Operating ambient temperature range, TA
Storage temperature, Tstg
4
V
85
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model (HBM), per AEC Q100-002(1)
All pins
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC
Q100-011
Corner pins (1, 25. 26. 50.
51, 75, 76, and 100)
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN NOM MAX UNIT
VDD
Rt
Supply voltage (DVDD, AVDD, PVDD, OVDD
)
3
45
3.3
50
25
3.6
55
85
V
Single-ended analog-input termination resistance
Operating free-air temperature
Ω
TA
°C
–40
6.4 Thermal Information
TFP401A-Q1
PZP (PQFP)
100 PINS
24.9
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
13.2
8.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJT
8.5
ψJB
RθJC(bot)
0.7
(1) For more information about traditional and new thermal metrics, see the Semicondictor and IC Package Thermal Metrics application
report.
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6.5 DC Digital I/O Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
High-level digital input voltage
Low-level digital input voltage
TEST CONDITIONS
MIN
2
TYP MAX UNIT
VIH
VIL
DVDD
0.8
16.3
10.3
19
V
V
0
ST = high, VOH = 2.4 V
ST = low, VOH = 2.4 V
ST = high, VOL = 0.8 V
ST = low, VOL = 0.8 V
PD = low or PDO = low
5
10
6
IOH
High-level output drive current
mA
3
8
13
7
IOL
IOZ
Low-level output drive current
Hi-Z output leakage current
mA
4
11
1
–1
μA
6.6 DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
75
TYP
MAX
UNIT
mV
VID
Analog-input differential voltage(1)
Analog-input common-mode voltage(1)
Open-circuit analog input voltage
1200
VIC
mV
AVDD –300
AVDD –10
AVDD –37
VI(OC)
AVDD + 10
mV
mA
Normal 2-pixels-per-clock power-supply
current(2)
ODCK = 82.5 MHz, 2 pixels per
clock
IDD(2PIX)
370
10
IPD
Power-down current(3)
PD = low
mA
mA
IPDO
Output-drive power-down current(3)
PDO = low
35
(1) Specified as dc characteristic with no overshoot or undershoot.
(2) Alternating 2-pixel black and 2-pixel white patterns. ST = high, STAG = high, QE[23:0] and QO[23:0] CL = 10 pF.
(3) Analog inputs are open-circuit (transmitter disconnected from the TFP401A-Q1 device).
6.7 AC Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
150
25
TYP MAX
1560
UNIT
VID(2)
fODCK
Differential input sensitivity(1)
mVp-p
PIXS = low (1-PIX/CLK)
PIXS = high (2-PIX/CLK)
165
ODCK frequency
ODCK duty-cycle
MHz
12.5
45%
82.5
60% 75%
(1) Specified as ac parameter to include sensitivity to overshoot, undershoot, and reflection.
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6.8 Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
(1)
Analog input intra-pair (+ to –) differential skew (2)
Analog input inter-pair or channel-to-channel skew (2)
Worst-case differential input-clock jitter tolerance(2) (4)
tps
tccs
tijit
0.4
1
tbit
(3)
tpix
50
ps
ns
ST = low, CL = 5 pF
2.4
1.9
2.4
1.9
2.4
1.9
2.4
1.9
tf1
tr1
tr2
tf2
Fall time of data and control signals(5) (6)
Rise time of data and control signals(5) (6)
Rise time of ODCK clock(5)
ST = high, CL = 10 pF
ST = low, CL = 5 pF
ST = high, CL = 10 pF
ST = low, CL = 5 pF
ST = high, CL = 10 pF
ST = low, CL = 5 pF
ST = high, CL = 10 pF
ns
ns
ns
Fall time of ODCK clock(5)
1 pixel per clock, PIXS = low,
OCK_INV = low
1.8
3.8
0.6
0.6
2.5
2.9
2.1
4
Setup time, data and control signal to falling edge of
ODCK
2 pixels per clock, PIXS = high,
STAG = high, OCK_INV = low
tsu1
ns
ns
ns
2 pixels and STAG, PIXS = high,
STAG = low, OCK_INV = low
1 pixel per clock, PIXS = low,
OCK_INV = low
Hold time, data and control signal to falling edge of
ODCK
2 pixels and STAG, PIXS = high,
STAG = low, OCK_INV = low
th1
2 pixels per clock, PIXS = high,
STAG = high, OCK_INV = low
1 pixels per clock, PIXS = low,
OCK_INV = high
Setup time, data and control signal to rising edge of
ODCK
2 pixels per clock, PIXS = high,
STAG = high, OCK_INV = high
tsu2
2 pixels and STAG, PIXS = high,
STAG = low, OCK_INV = high
1.5
0.3
2.4
1 pixel per clock, PIXS = low,
OCK_INV = high
Hold time, data and control signal to rising edge of
ODCK
2 pixels and STAG, PIXS = high,
STAG = low, OCK_INV = high
th2
ns
ns
2 pixels per clock, PIXS = high,
STAG = high, OCK_INV = high
2.1
tpix
Pixel time(3)
6.06
40
(1) tbit is 1/10 the pixel time, tpix
.
(2) Specified by characterization.
(3) tpix is the pixel time defined as the period of the RxC clock input. The period of the output clock, ODCK, is equal to tpix when in 1-pixel-
per-clock mode or 2 tpix when in 2-pixels-per-clock mode.
(4) Measured differentially at 50% crossing using ODCK output clock as trigger.
(5) Rise and fall times measured as time between 20% and 80% of signal amplitude.
(6) Data and control signals are QE[23:0], QO[23:0], DE, HSYNC, VSYNC. and CTL[3:1].
(7) Amount of time detected between DE transitions determines whether link is active or inactive. SCDT indicates link activity.
tr1
tf1
80%
QE[23:0], QO[23:0], DE,
CTK[3:1], HSYNC, VSYNC
80%
20%
20%
图6-1. Rise and Fall Times of Data and Control Signals
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t
r2
t
f2
80%
20%
80%
20%
ODCK
图6-2. Rise and Fall Times of ODCK
1/fODCK
ODCK
图6-3. ODCK Frequency
t(su1)
t(su2)
t(h1)
t(h2)
VOH
VOL
VOH
VOL
ODCK
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
QE[23:0], QO[23:0] DE,
CTL[3:1], HSYNC, VSYNC
OCK_INV
图6-4. Data Setup and Hold Times to Rising and Falling Edges of ODCK
VOH
ODCK
td(st)
QE[23:0]
50%
图6-5. ODCK High to QE[23:0] Staggered Data Output
PD
VIL
tpd(PDL)
QE[23:0], QO[23:0],
ODCK, DE, CTL[3:1],
HSYNC, VSYNC, SCDT
图6-6. Delay From PD Low to Hi-Z Outputs
PDO
VIL
tpd(PDOL)
QE[23:0], QO[23:0],
ODCK, DE, CTL[3:2],
HSYNC, VSYNC
图6-7. Delay From PDO Low to Hi-Z Outputs
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VIH
PD
tp(PDH-V)
DFO, ST, PIXS, STAG,
Rx[2:0]+, Rx[2:0]–,
OCK_INV
图6-8. Delay From PD Low to High Until Inputs Are Active
t
t
t(FSC)
t(HSC)
DE
SCDT
图6-9. Time From DE Transitions to SCDT Low and SCDT High
6.9 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tpd(PDL)
Propagation delay time from PD low
to Hi-Z outputs
9
ns
Propagation delay time from PDO
low to Hi-Z outputs
tpd(PDOL)
tt(HSC)
9
ns
tpix
tpix
tpix
Delay time from DE transition to
SCDT low(7)
1e6
1600
0.25
Delay time from DE transition to
SCDT high(7)
tt(FSC)
td(st)
Delay time, ODCK latching edge to
QE[23:0] data output
STAG = low, PIXS = high
tps
Rx+
50%
Rx–
图6-10. Analog Input Intra-Pair Differential Skew
t
wL(PDL_MIN)
V
IL
PD
图6-11. Minimum Time PD Low
TX2
TX1
50%
t
ccs
50%
TX0
图6-12. Analog Input Channel-to-Channel Skew
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t
t
DEH
DEL
DE
图6-13. Minimum DE Low and Maximum DE High
6.10 Typical Characteristics
180
160
140
120
100
80
60
40
20
TFP401A-Q1
0
0
20
40
60
80 100 120 140 160 180 200
Input Clock (MHz)
D001
图6-14. Imax vs Input Frequency
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7 Detailed Description
7.1 Overview
The TFP401A-Q1 device is a digital visual interface (DVI)-compliant TMDS digital receiver used in digital flat-
panel display systems to receive and decode TMDS-encoded RGB pixel data streams. In a digital display
system, a host (usually a PC or workstation) contains a TMDS-compatible transmitter that receives 24-bit pixel
data along with appropriate control signals. The host encodes the data and control signals into a high-speed low-
voltage differential serial bit stream (fit for transmission over a twisted-pair cable) to a display device. The display
device (usually a flat-panel monitor) requires a TMDS-compatible receiver like the TI TFP401A-Q1 device to
decode the serial bit stream back to the same 24-bit pixel data and control signals that originated at the host.
This decoded data is then suitable for application directly to the flat-panel drive circuitry to produce an image on
the display. Host and display separation distances can be up to 5 meters or more, making serial transmission of
the pixel data preferable. Support of modern display resolutions up to UXGA requires a high-bandwidth receiver
with good jitter and skew tolerance.
7.2 Functional Block Diagram
3.3 V
3.3 V
1.8 V
Regulator
Internal 50-W
Termination
3.3 V
RED(0-7)
QE(0-23)
QO(0-23)
Channel 2
CH2(0-9)
CH1(0-9)
CTL3
CTL2
Rx2+
Rx2-
+
_
Latch
Latch
ODCK
DE
GRN(0-7)
CTL1
Channel 1
Channel 0
Data Recovery
and
Rx1+
Rx1-
+
_
TMDS
Panel
SCDT
Decoder
Interface
CTL3
CTL2
Synchronization
BLU(0-7)
VSYNC
HSYNC
CH0(0-9)
CTL1
Rx0+
Rx0-
+
_
Latch
PLL
VSYNC
HSYNC
RxC+
RxC-
+
_
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7.3 Feature Description
7.3.1 TMDS Pixel Data and Control Signal Encoding
The device transmits only one of two possible transition-minimized differential signaling (TMDS) characters for a
given pixel at a given time. The transmitter keeps a running count of the number of ones and zeros previously
sent, and transmits the character that minimizes the number of transitions to approximate a dc balance of the
transmission line.
Reception of RGB pixel data during active display time uses three TMDS channels, DE = high. The same three
channels also receive control signals, HSYNC, VSYNC, and user-defined control signals CTL[3:1]. Reception of
these control signals occurs during inactive display or blanking-time. Blanking-time is when DE = low. The
following table maps the received input data to the appropriate TMDS input channel in a DVI-compliant system.
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表7-1. TMDS Pixel Data and Control Signal Encoding
RECEIVED PIXEL DATA
ACTIVE DISPLAY DE = HIGH
OUTPUT PINS
(VALID FOR DE = HIGH)
INPUT CHANNEL
Channel-2 (Rx2 ±)
Red[7:0]
QE[23:16] QO[23:16]
Green[7:0]
Blue[7:0]
Channel-1 (Rx1 ±)
Channel-0 (Rx0 ±)
QE[15:8] QO[15:8]
QE[7:0] QO[7:0]
RECEIVED CONTROL DATA
BLANKING DE = LOW
OUTPUT PINS
(VALID FOR DE = LOW)
INPUT CHANNEL
CTL[3:2]
Channel-2 (Rx2 ±)
Channel-1 (Rx1 ±)
Channel-0 (Rx0 ±)
CTL[3:2]
CTL1
CTL[1: 0](1)
HSYNC, VSYNC
HSYNC, VSYNC
(1) Some TMDS transmitters transmit a CTL0 signal. The TFP401A-Q1 device decodes and transfers CTL[3:1] and ignores CTL0
characters. CTL0 is not available as a TFP401A-Q1 output.
The TFP401A-Q1 device discriminates between valid pixel TMDS characters and control TMDS characters to
determine the state of active display versus blanking, in effect, the state of DE.
7.3.2 TFP401A-Q1 Clocking and Data Synchronization
The TFP401A-Q1 device receives a clock reference from the DVI transmitter that has a period equal to the pixel
time, tpix. Another name for the frequency of this clock is the pixel rate. Because the TMDS encoded data on
Rx[2:0] contains 10 bits per 8-bit pixel, it follows that the Rx[2:0] serial bit rate is 10 times the pixel rate. For
example, the required pixel rate to support a UXGA resolution with 60-Hz refresh rate is 165 MHz. The TMDS
serial bit rate is 10× the pixel rate, or 1.65 Gb/s. Due to the transmission of this high-speed digital bit stream, on
three separate channels (or twisted-pair wires) of long distances (3–5 meters), there is no assurance of phase
synchronization between the data steams and the input reference clock. In addition, skew between the three
data channels is common. The TFP401A-Q1 device uses a 4× oversampling scheme of the input data streams
to achieve reliable synchronization with up to 1-tpix channel-to-channel skew tolerance. Accumulated jitter on the
clock and data lines due to reflections and external noise sources is also typical of high-speed serial data
transmission; hence, the TFP401A-Q1 design for high jitter tolerance.
A phase-locked loop (PLL) conditions the input clock of the TFP401A-Q1 device to remove high-frequency jitter
from the clock. The PLL provides four 10× clock outputs of different phase to locate and sync the TMDS data
streams (4× oversampling). During active display, the pixel data encoding is for transition minimization, whereas
in blank, the control data encoding is for transition maximization. Transmitting in blank for a minimum period of
time, 128 tpix, requires a DVI-compliant transmitter to ensure sufficient time for data synchronization when the
receiver sees a transition-maximized code. Synchronization during blank, when the data is transition-maximized,
ensures reliable data-bit boundary detection. Phase synchronization to the data streams, maintained as long as
the link remains active, is unique for each of the three input channels.
7.3.3 TFP401A-Q1 TMDS Input Levels and Input Impedance Matching
The TMDS inputs to the TFP401A-Q1 receiver have a fixed single-ended termination to AVDD. A laser trim
process internally optimizes the TFP401A-Q1 device to fix the impedance precisely at 50 Ω. The device
functions normally with or without a resistor on the EXT_RES pin, so it remains drop-in compatible with current
sockets. The fixed impedance eliminates the need for an external resistor while providing optimum impedance
matching to standard 50-ΩDVI cables.
图 7-1 shows a conceptual schematic of a DVI transmitter and TFP401A-Q1 receiver connection. A transmitter
drives the twisted-pair cable through a current source, usually using an open-drain type of output driver. The
internal resistor, matched to the cable impedance at the TFP401A-Q1 input, provides a pullup to AVDD. Naturally,
with the transmitter disconnected and the TFP401A-Q1 DVI inputs left unconnected, the TFP401A-Q1 receiver
inputs pull up to AVDD. 图 7-2 shows the single-ended differential signal and full-differential signal. The design of
the TFP401A-Q1 device is for response to differential signal swings ranging from 150 mV to 1.56 V, with
common-mode voltages ranging from (AVDD –300 mV) to (AVDD –37 mV).
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DVI
TI TFP401/401A
Receiver
Transmitter
AVDD
DVI Compliant Cable
Internal Termination
at 50 W
DATA
DATA
+
_
Current
Source
Copyright © 2017, Texas Instruments Incorporated
图7-1. TMDS Differential Input and Transmitter Connection
VIDIFF
+1/2 VIDIFF
–1/2 VIDIFF
1/2 VIDIFF
AVCC
AVCC – 1/2 VIDIFF
a) Single-Ended Input Signal
b) Differential Input Signal
图7-2. TMDS Inputs
7.3.4 TFP401A-Q1 Device Incorporates HSYNC Jitter Immunity
Several DVI transmitters available in the market introduce jitter on the transmitted HSYNC and VSYNC signals
during the TMDS encryption process. The HSYNC signal can shift by one pixel position (one clock) from nominal
in either direction, resulting in up to two cycles of HSYNC shift. This jitter carries through to the DVI receiver, and
if the position of HSYNC shifts continuously, the receiver can lose track of the input timing, causing pixel noise to
occur on the display. For this reason, one should use a DVI-compliant receiver with HSYNC jitter immunity in all
displays that could be connected to host PCs with transmitters that have this HSYNC jitter problem.
The TFP401A-Q1 integrates HSYNC regeneration circuitry that provides a seamless interface to these
noncompliant transmitters. The regeneration circuitry always fixes the position of the data enable (DE) signal in
relation to data, irrespective of the location of HSYNC. The TFP401A-Q1 receiver uses the DE and clock signals
to recreate stable vertical and horizontal sync signals. The circuit filters the HSYNC output of the receiver and
shifts HSYNC to the nearest eighth bit boundary, producing a stable output with respect to the data, as shown in
图7-3. This ensures accurate data synchronization at the input of the display timing controller.
This HSYNC regeneration circuit is transparent to the monitor, and removal is unnecessary even if the
transmitted HSYNC is stable. For example, the PanelBus line of DVI 1.0-compliant transmitters, such as the
TFP6422 and TFP420, do not have the HSYNC jitter problem. The TFP401A-Q1 device operates correctly with
either compliant or noncompliant transmitters. In contrast, the TFP401A-Q1 device is ideal for customers who
have control over the transmit portion of the design, such as bundled-system manufacturers and for internal
monitor use (the DVI connection between monitor and panel modules).
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ODCK
HSYNC Shift by 1 Clock
HSYNC IN
DE
HSYNC OUT
图7-3. HSYNC Regeneration Timing Diagram
7.4 Device Functional Modes
7.4.1 TFP401A-Q1 Modes of Operation
The TFP401A-Q1 device provides system design flexibility and value by providing the system designer with
configurable options or modes of operation to support varying system architectures. 表 7-2 outlines the various
supportable panel modes, along with appropriate external control pin settings.
表7-2. Supported Panel Modes
PANEL
TFT or 16-bit DSTN
TFT or 16-bit DSTN
TFT
PIXEL RATE
1 pixel per clock
1 pixel per clock
2 pixels per clock
2 pixels per clock
1 pixel per clock
1 pixel per clock
2 pixels per clock
2 pixels per clock
ODCK LATCH EDGE
ODCK
Free run
Free run
Free run
Free run
Gated low
Gated low
Gated low
Gated low
DFO
PIXS
OCK_INV
Falling
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Rising
Falling
TFT
Rising
24-bit DSTN
None
Falling
Rising
24-bit DSTN
24-bit DSTN
Falling
Rising
7.4.2 TFP401A-Q1 Output Driver Configurations
The TFP401A-Q1 device provides flexibility by offering various output driver features for use to optimize power
consumption, ground bounce, and power-supply noise. The following sections outline the output driver features
and their effects.
Output Driver Power Down (PDO = low): Pulling PDO low places all the output drivers, except CTL1 and
SCDT, into a high-impedance state. One can tie the SCDT output, which indicates link-disabled or link-inactive,
directly to the PDO input to disable the output drivers when the link is inactive or when the cable is disconnected.
An internal pullup on the PDO pin defaults the TFP401A-Q1 device to the normal nonpower-down output-drive
mode if left unconnected.
Drive Strength (ST = high for high drive strength, ST = low for low drive strength): The TFP401A-Q1 device
allows for selectable output drive strength on the data, control, and ODCK outputs. See the DC Electrical
Characteristics table for the values of IOH and IOL current drives for a given ST state. The high output-drive
strength offers approximately two times the drive as the low output-drive strength.
Time-Staggered Pixel Output: This option works only in conjunction with the 2-pixels-per-clock mode (PIXS =
high). Setting STAG = low time-staggers the even- and odd-pixel outputs so as to reduce the amount of
instantaneous current surge from the power supply. Depending on the PCB layout and design, this can help
reduce the amount of system ground bounce and power-supply noise. The time stagger is such that in 2-pixels-
per-clock mode, the even pixel is delayed from the latching edge of ODCK by 0.25 tcip. (tcip is the period of
ODCK. The ODCK period is 2 tpix when in 2-pixels-per-clock mode.)
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Depending on system constraints of output load, pixel rate, panel input architecture, and board cost, the
TFP401A-Q1 drive-strength and staggered-pixel options allow flexibility to reduce system power-supply noise,
ground bounce, and EMI.
Power Management: The TFP401A-Q1 device offers several system power-management features.
The output-driver power down (PDO = low) is an intermediate mode which offers several uses. During this
mode, all output drivers except SCDT and CTL1 go into a high-impedance state while the rest of the device
circuitry remains active.
Power down (PD = low) of the TFP401A-Q1 device is a complete power down in that it powers down the digital
core, the analog circuitry, and output drivers. All output drivers go into a Hi-Z state. Of all the inputs, only PD
remains active. The TFP401A-Q1 device does not respond to any digital or analog inputs until PD is pulled high.
Both PDO and PD have internal pullups, so if left unconnected they default the TFP401A-Q1 device to normal
operating modes.
Sync Detect: The TFP401A-Q1 device offers an output, SCDT, to indicate link activity. The TFP401A-Q1 device
monitors activity on DE to determine if the link is active. When 1 million (1e6) pixel clock periods pass without a
transition on DE, the TFP401A-Q1 device considers the link inactive, and drives SCDT low. While SCDT is low, if
two DE transitions are detected within 1600 pixel clock periods, the device considers the link active and pulls
SCDT high.
A use of SCDT is to signal a system power management circuit to initiate a system power down when the device
considers the link inactive. The SCDT can also be tied directly to the TFP401A-Q1 PDO input to power down the
output drivers when the link is inactive. It is not recommended to use SCDT to drive the PD input, because once
in complete power-down, the analog inputs are ignored and the SCDT state does not change. An external
system power-management circuit to drive PD is preferred.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The TFP401A-Q1 is a DVI (Digital Visual Interface) compliant digital receiver that is used in digital flat panel
display systems to receive and decode T.M.D.S. encoded RGB pixel data streams. In a digital display system a
host, usually a PC or workstation, contains a DVI compliant transmitter that receives 24 bit pixel data along with
appropriate control signals and encodes them into a high speed low voltage differential serial bit stream fit for
transmission over a twisted-pair cable to a display device. The display device, usually a flat-panel monitor, will
require a DVI compliant receiver like the TI TFP401A-Q1 to decode the serial bit stream back to the same 24 bit
pixel data and control signals that originated at the host. This decoded data can then be applied directly to the
flat panel drive circuitry to produce an image on the display. Since the host and display can be separated by
distances up to 5 meters or more, serial transmission of the pixel data is preferred. The TFP401A-Q1 will support
resolutions up to UXGA.
8.1.1 Typical Application
图8-1. Typical Application
8.1.1.1 Design Requirements
表8-1. Design Parameters
PARAMETER
Power supply
VALUE
3.3 V-DC at 1 A
Single-ended
25 MHz to 165 MHz
24 bits/pixel
Rising edge
No
Input clock
Input clock frequency range
Output format
Input clock latching
I2C EEPROM support
De-skew
No
8.1.1.2 Detailed Design Procedure
8.1.1.2.1 Data and Control Signals
The trace length of data and control signals out of the receiver should be kept as close to equal as possible.
Trace separation should be ≈5X Height. As a general rule, traces also should be less than 2.8 inches if possible
(longer traces can be acceptable).
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Calculation:
Delay = 85 × SQRT er
(1)
(2)
(3)
er = 4.35; relative permitivity of 50% resin FR-4 at 1 GHz
Delay = 177 pS/inch
space
Length of rising edge = Tr(picoseconds)/Delay; Tr = 3 nS
= 3000 ps/177 ps per inch
(4)
(5)
(6)
= 16.9 inches
space
Length of rising edge / 6 = Maximum length of trace for lumped circuit
16.9 / 6 = 2.8 inches
(7)
(8)
图8-2. TFP401A-Q1 App Info Data and Control Signals
8.1.1.2.2 Configuration Options
The TFP401A-Q1 can be configured in several modes depending on the required output format, for example 1-
byte/clock, 2-bytes/clock, falling/rising clock edge.
You can leave place holders for future configuration changes.
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图8-3. TFP401A-Q1 App Info Config Options
8.1.1.2.3 Power Supplies Decoupling
Digital, analog and PLL supplies must be decoupled from each other to avoid electrical noise on the PLL and the
core.
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图8-4. TFP401A-Q1 App Info Power Decoupling
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8.1.1.3 Application Curves
Sometimes the panel does not support the same format as the GPU (graphics processor unit). In these cases
the user must decide how to connect the unused bits.
The below plots show the mismatches between the 18-bit GPU and a 24-bit LCD where x and y represent the 2
LSB of the panel.
250
200
150
100
50
250
200
150
100
50
x=GND, y=1
x=B7, y=B6
B2 B1 = GND, B0 =1
B2 B1 B0 = B7 B6 B5
0
0
1
4
7
10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58 61 64
Pixel Samples
1
3
5
7
9
11 13 15 17 19 21 23 25 27 29 31
Pixel Samples
图8-6. 18B GPU to 24b LCD
图8-5. 16b GPU to 24b LCD
8.1.1.4 DVDD
Place one 0.01-µF capacitor as close as possible between each DVDD device pin (Pins 6, 38, and 67) and
ground.
8.1.1.5 OVDD
Place one 0.01-µF capacitor as close as possible between each OVDD device pin (Pins 18, 29, 43, 57, and 78)
and ground.
A 22-µF tantalum capacitor should be placed between the supply and 0.01-µF capacitors.
A ferrite bead should be used between the source and the 22-µF capacitor.
8.1.1.6 AVDD
Place one 0.01-µF capacitor as close as possible between each AVDD device pin (Pins 82, 84, 88, and 95) and
ground.
A 22-µF tantalum capacitor should be placed between the supply and 0.01-µF capacitors.
A ferrite bead should be used between the source and the 22-µF capacitor.
8.1.1.7 PVDD
Place three 0.01-µF capacitors in parallel as close as possible between the PVDD device pin (Pin 97) and
ground. A 22-µF tantalum capacitor should be placed between the supply and 0.01-µF capacitors. A ferrite bead
should be used between the source and the 22-µF capacitor.
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8.2 Power Supply Recommendations
Use solid ground planes, tie ground planes together with as many vias as is practical. This will provide a
desirable return path for current. Each supply should be on separate split power planes, where each power
plane should be as large an area as possible. Connect PanelBus receiver power and ground pins and all bypass
caps to appropriate power or ground plane with via. Vias should be as fat and short as practical, the goal is to
minimize the inductance.
8.3 Layout
8.3.1 Layout Guidelines
8.3.1.1 Layer Stack
The pinout of Texas Instruments High Speed Interface (HSI) devices features differential signal pairs and the
remaining signals comprise the supply rails, VCC and ground, and lower speed signals such as control pins. As
an example, consider a device X which is a repeater/re-driver, so both its inputs and outputs are high-speed
differential signals. These guidelines can be applied to other high-speed devices such as drivers, receivers,
multiplexers, and so on.
A minimum of four layers is required to accomplish a low EMI PCB design. Layer stacking should be in the
following order (top-to-bottom): high-speed differential signal layer, ground plane, power plane and control signal
layer.
图8-7. Layer Stack
8.3.1.2 Routing High-Speed Differential Signal Traces (RxC-, RxC+, Rx0-, Rx0+, Rx1-, Rx1+, Rx2-, Rx2+)
Trace impedance should be controlled for optimal performance. Each differential pair should be equal in length
and symmetrical and should have equal impedance to ground with a trace separation of 2X to 4X Height. A
differential trace separation of 4X Height yields about 6% cross-talk (6% effect on impedance). TI recommends
that differential trace routing should be side by side, though it is not important that the differential traces be tightly
coupled together because tight coupling is not achievable on PCB traces. Typical ratios on PCB’s are only
20-50%, 99.9% is the value of a well-balanced twisted pair cable. Each differential trace should be as short as
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possible (< 2 inches preferably) with no 90° angles. These high-speed transmission traces hould be on layer 1
(top layer).
RxC-, RxC+, Rx0-, Rx0+, Rx1-, Rx1+, Rx2-, Rx2+ signals all route directly from the DVI connector pins to the
device, no external components are needed.
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8.3.2 Layout Example
• DVI connector trace matching
图8-8. DVI Connector
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• Keep data lines as far as possible from each other
图8-9. Data Route
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• Connect the thermal pad to ground
图8-10. GND Route
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8.3.3 TI PowerPAD 100-TQFP Package
The TFP401A-Q1 device comes in TI's thermally enhanced PowerPAD 100-TQFP package. The PowerPAD
package is a 14-mm × 14-mm × 1-mm TQFP outline with 0.5-mm lead pitch. The PowerPAD package has a
specially designed die mount pad that offers improved thermal capability over typical TQFP packages of the
same outline. The TI 100-TQFP PowerPAD package offers a back-side solder plane that connects directly to the
die mount pad for enhanced thermal conduction. There is no thermal requirement for soldering the back side of
the TFP401A-Q1 device to the application board, because the device power dissipation is well within the
package capability when not soldered. However, to minimize stress on peripheral pins, it is highly recommended
to solder the thermal pad to PCB.
Soldering the back side of the device to the PCB ground plane is recommended for electrical considerations.
Because the die pad is electrically connected to the chip substrate and hence to chip ground, connection of the
PowerPAD's back side to a PCB ground plane helps to improve EMI, ground bounce, and power-supply noise
performance.
表 8-2 outlines the thermal properties of the TI 100-TQFP PowerPAD package. The 100-TQFP non-PowerPAD
package is included only for reference.
表8-2. TI 100-TQFP (14 mm × 14 mm × 1 mm) With 0.5-mm Lead Pitch
WITHOUT
PowerPAD™
PACKAGE
PowerPAD™ PACKAGE,
NOT CONNECTED TO PCB
THERMAL PLANE
PowerPAD™ PACKAGE,
CONNECTED TO PCB
THERMAL PLANE(1)
PARAMETER
Theta-JA(1) (2)
45°C/W
3.11°C/W
1.6 W
27.3°C/W
0.12°C/W
2.7 W
17.3°C/W
0.12°C/W
4.3 W
Theta-JC(1) (2)
Maximum power dissipation(1) (2) (3)
(1) Specified with 2-oz. (0.071 mm thick) Cu PCB plating.
(2) Airflow is at 0 LFM (0 m/s) (no airflow).
(3) Measured at ambient temperature, TA = 70°C.
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9 Device and Documentation Support
9.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.3 Trademarks
Panelbus™, PowerPAD™, and EPIC-5™ are trademarks of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TFP401AIPZPRQ1
ACTIVE
HTQFP
PZP
100
1000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TFP401AI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TFP401A-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2022
Catalog : TFP401A
•
Enhanced Product : TFP401A-EP
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Oct-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TFP401AIPZPRQ1
HTQFP
PZP
100
1000
330.0
24.4
17.0
17.0
1.5
20.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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5-Oct-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTQFP PZP 100
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
TFP401AIPZPRQ1
1000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
PZP 100
14 x 14, 0.5 mm pitch
PowerPAD TM TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224739/A
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Copyright © 2023，德州仪器 (TI) 公司
相关型号：
TFP401ACPZP
SPECIALTY CONSUMER CIRCUIT, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, POWER, THERMALLY ENHANCED, PLASTIC, TQFP-100
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